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From: Andre Przywara <andre.przywara@arm.com>
To: Rob Herring <robh@kernel.org>, Liviu Dudau <liviu.dudau@arm.com>,
	Sudeep Holla <sudeep.holla@arm.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	Mark Rutland <mark.rutland@arm.com>,
	Marc Zyngier <maz@kernel.org>
Subject: [PATCH v3 09/20] arm64: dts: arm: juno: Fix GIC child nodes
Date: Wed, 13 May 2020 11:30:05 +0100	[thread overview]
Message-ID: <20200513103016.130417-10-andre.przywara@arm.com> (raw)
In-Reply-To: <20200513103016.130417-1-andre.przywara@arm.com>

The GIC DT nodes for the Juno boards were not fully compliant with
the DT binding, which has certain expectations about child nodes and
their size and address cells values.

Use smaller #address-cells and #size-cells values, as the binding
requests, and adjust the reg properties accordingly.
This requires adjusting the interrupt nexus nodes as well, as one
field of the interrupt-map property depends on the GIC's address-size.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm64/boot/dts/arm/juno-base.dtsi | 50 +++++++++++++-------------
 1 file changed, 25 insertions(+), 25 deletions(-)

diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index 3feefd61eb76..dfb2fef37030 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -74,35 +74,35 @@
 		      <0x0 0x2c02f000 0 0x2000>,
 		      <0x0 0x2c04f000 0 0x2000>,
 		      <0x0 0x2c06f000 0 0x2000>;
-		#address-cells = <2>;
+		#address-cells = <1>;
 		#interrupt-cells = <3>;
-		#size-cells = <2>;
+		#size-cells = <1>;
 		interrupt-controller;
 		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
-		ranges = <0 0 0 0x2c1c0000 0 0x40000>;
+		ranges = <0 0 0x2c1c0000 0x40000>;
 
 		v2m_0: v2m@0 {
 			compatible = "arm,gic-v2m-frame";
 			msi-controller;
-			reg = <0 0 0 0x10000>;
+			reg = <0 0x10000>;
 		};
 
 		v2m@10000 {
 			compatible = "arm,gic-v2m-frame";
 			msi-controller;
-			reg = <0 0x10000 0 0x10000>;
+			reg = <0x10000 0x10000>;
 		};
 
 		v2m@20000 {
 			compatible = "arm,gic-v2m-frame";
 			msi-controller;
-			reg = <0 0x20000 0 0x10000>;
+			reg = <0x20000 0x10000>;
 		};
 
 		v2m@30000 {
 			compatible = "arm,gic-v2m-frame";
 			msi-controller;
-			reg = <0 0x30000 0 0x10000>;
+			reg = <0x30000 0x10000>;
 		};
 	};
 
@@ -546,10 +546,10 @@
 			 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
 		#interrupt-cells = <1>;
 		interrupt-map-mask = <0 0 0 7>;
-		interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
-				<0 0 0 2 &gic 0 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
-				<0 0 0 3 &gic 0 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
-				<0 0 0 4 &gic 0 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-map = <0 0 0 1 &gic 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 0 2 &gic 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 0 3 &gic 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 0 4 &gic 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 		msi-parent = <&v2m_0>;
 		status = "disabled";
 		iommu-map-mask = <0x0>;	/* RC has no means to output PCI RID */
@@ -813,19 +813,19 @@
 
 		#interrupt-cells = <1>;
 		interrupt-map-mask = <0 0 15>;
-		interrupt-map = <0 0  0 &gic 0 0 GIC_SPI  68 IRQ_TYPE_LEVEL_HIGH>,
-				<0 0  1 &gic 0 0 GIC_SPI  69 IRQ_TYPE_LEVEL_HIGH>,
-				<0 0  2 &gic 0 0 GIC_SPI  70 IRQ_TYPE_LEVEL_HIGH>,
-				<0 0  3 &gic 0 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
-				<0 0  4 &gic 0 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
-				<0 0  5 &gic 0 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
-				<0 0  6 &gic 0 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
-				<0 0  7 &gic 0 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
-				<0 0  8 &gic 0 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
-				<0 0  9 &gic 0 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
-				<0 0 10 &gic 0 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
-				<0 0 11 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
-				<0 0 12 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-map = <0 0  0 &gic 0 GIC_SPI  68 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0  1 &gic 0 GIC_SPI  69 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0  2 &gic 0 GIC_SPI  70 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0  3 &gic 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0  4 &gic 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0  5 &gic 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0  6 &gic 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0  7 &gic 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0  8 &gic 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0  9 &gic 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 10 &gic 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 11 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 12 &gic 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
 	site2: tlx@60000000 {
@@ -835,6 +835,6 @@
 		ranges = <0 0 0x60000000 0x10000000>;
 		#interrupt-cells = <1>;
 		interrupt-map-mask = <0 0>;
-		interrupt-map = <0 0 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-map = <0 0 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 	};
 };
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: Andre Przywara <andre.przywara@arm.com>
To: Rob Herring <robh@kernel.org>, Liviu Dudau <liviu.dudau@arm.com>,
	Sudeep Holla <sudeep.holla@arm.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	Marc Zyngier <maz@kernel.org>
Subject: [PATCH v3 09/20] arm64: dts: arm: juno: Fix GIC child nodes
Date: Wed, 13 May 2020 11:30:05 +0100	[thread overview]
Message-ID: <20200513103016.130417-10-andre.przywara@arm.com> (raw)
In-Reply-To: <20200513103016.130417-1-andre.przywara@arm.com>

The GIC DT nodes for the Juno boards were not fully compliant with
the DT binding, which has certain expectations about child nodes and
their size and address cells values.

Use smaller #address-cells and #size-cells values, as the binding
requests, and adjust the reg properties accordingly.
This requires adjusting the interrupt nexus nodes as well, as one
field of the interrupt-map property depends on the GIC's address-size.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm64/boot/dts/arm/juno-base.dtsi | 50 +++++++++++++-------------
 1 file changed, 25 insertions(+), 25 deletions(-)

diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index 3feefd61eb76..dfb2fef37030 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -74,35 +74,35 @@
 		      <0x0 0x2c02f000 0 0x2000>,
 		      <0x0 0x2c04f000 0 0x2000>,
 		      <0x0 0x2c06f000 0 0x2000>;
-		#address-cells = <2>;
+		#address-cells = <1>;
 		#interrupt-cells = <3>;
-		#size-cells = <2>;
+		#size-cells = <1>;
 		interrupt-controller;
 		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
-		ranges = <0 0 0 0x2c1c0000 0 0x40000>;
+		ranges = <0 0 0x2c1c0000 0x40000>;
 
 		v2m_0: v2m@0 {
 			compatible = "arm,gic-v2m-frame";
 			msi-controller;
-			reg = <0 0 0 0x10000>;
+			reg = <0 0x10000>;
 		};
 
 		v2m@10000 {
 			compatible = "arm,gic-v2m-frame";
 			msi-controller;
-			reg = <0 0x10000 0 0x10000>;
+			reg = <0x10000 0x10000>;
 		};
 
 		v2m@20000 {
 			compatible = "arm,gic-v2m-frame";
 			msi-controller;
-			reg = <0 0x20000 0 0x10000>;
+			reg = <0x20000 0x10000>;
 		};
 
 		v2m@30000 {
 			compatible = "arm,gic-v2m-frame";
 			msi-controller;
-			reg = <0 0x30000 0 0x10000>;
+			reg = <0x30000 0x10000>;
 		};
 	};
 
@@ -546,10 +546,10 @@
 			 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
 		#interrupt-cells = <1>;
 		interrupt-map-mask = <0 0 0 7>;
-		interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
-				<0 0 0 2 &gic 0 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
-				<0 0 0 3 &gic 0 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
-				<0 0 0 4 &gic 0 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-map = <0 0 0 1 &gic 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 0 2 &gic 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 0 3 &gic 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 0 4 &gic 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 		msi-parent = <&v2m_0>;
 		status = "disabled";
 		iommu-map-mask = <0x0>;	/* RC has no means to output PCI RID */
@@ -813,19 +813,19 @@
 
 		#interrupt-cells = <1>;
 		interrupt-map-mask = <0 0 15>;
-		interrupt-map = <0 0  0 &gic 0 0 GIC_SPI  68 IRQ_TYPE_LEVEL_HIGH>,
-				<0 0  1 &gic 0 0 GIC_SPI  69 IRQ_TYPE_LEVEL_HIGH>,
-				<0 0  2 &gic 0 0 GIC_SPI  70 IRQ_TYPE_LEVEL_HIGH>,
-				<0 0  3 &gic 0 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
-				<0 0  4 &gic 0 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
-				<0 0  5 &gic 0 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
-				<0 0  6 &gic 0 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
-				<0 0  7 &gic 0 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
-				<0 0  8 &gic 0 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
-				<0 0  9 &gic 0 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
-				<0 0 10 &gic 0 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
-				<0 0 11 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
-				<0 0 12 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-map = <0 0  0 &gic 0 GIC_SPI  68 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0  1 &gic 0 GIC_SPI  69 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0  2 &gic 0 GIC_SPI  70 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0  3 &gic 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0  4 &gic 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0  5 &gic 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0  6 &gic 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0  7 &gic 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0  8 &gic 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0  9 &gic 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 10 &gic 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 11 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 12 &gic 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
 	site2: tlx@60000000 {
@@ -835,6 +835,6 @@
 		ranges = <0 0 0x60000000 0x10000000>;
 		#interrupt-cells = <1>;
 		interrupt-map-mask = <0 0>;
-		interrupt-map = <0 0 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-map = <0 0 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 	};
 };
-- 
2.17.1


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  parent reply	other threads:[~2020-05-13 10:30 UTC|newest]

Thread overview: 94+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-13 10:29 [PATCH v3 00/20] dts/dt-bindings: Fix Arm Ltd. ARMv8 "boards" Andre Przywara
2020-05-13 10:29 ` Andre Przywara
2020-05-13 10:29 ` [PATCH v3 01/20] dt-bindings: arm: gic: Allow combining arm,gic-400 compatible strings Andre Przywara
2020-05-13 10:29   ` [PATCH v3 01/20] dt-bindings: arm: gic: Allow combining arm, gic-400 " Andre Przywara
2020-05-15  3:16   ` Rob Herring
2020-05-15  3:16     ` Rob Herring
2020-05-19  7:39   ` [PATCH v3 01/20] dt-bindings: arm: gic: Allow combining arm,gic-400 " Geert Uytterhoeven
2020-05-19  7:39     ` Geert Uytterhoeven
2020-05-19  9:19     ` André Przywara
2020-05-19  9:19       ` André Przywara
2020-05-26 15:49       ` Rob Herring
2020-05-26 15:49         ` Rob Herring
2020-05-13 10:29 ` [PATCH v3 02/20] arm64: dts: arm: Fix node address fields Andre Przywara
2020-05-13 10:29   ` Andre Przywara
2020-05-13 17:01   ` Sudeep Holla
2020-05-13 17:01     ` Sudeep Holla
2020-05-13 10:29 ` [PATCH v3 03/20] arm64: dts: arm: fvp: Move fixed devices out of bus node Andre Przywara
2020-05-13 10:29   ` Andre Przywara
2020-05-13 17:22   ` Sudeep Holla
2020-05-13 17:22     ` Sudeep Holla
2020-05-13 10:30 ` [PATCH v3 04/20] arm64: dts: arm: vexpress: " Andre Przywara
2020-05-13 10:30   ` Andre Przywara
2020-05-13 17:26   ` Sudeep Holla
2020-05-13 17:26     ` Sudeep Holla
2020-05-28  2:48   ` Guenter Roeck
2020-05-28  2:48     ` Guenter Roeck
2020-05-28  2:55     ` Guenter Roeck
2020-05-28  2:55       ` Guenter Roeck
2020-06-27  3:57       ` Guenter Roeck
2020-06-27  3:57         ` Guenter Roeck
2020-06-29  8:55         ` Sudeep Holla
2020-06-29  8:55           ` Sudeep Holla
2020-05-28 13:30     ` André Przywara
2020-05-28 13:30       ` André Przywara
2020-06-01 10:14       ` André Przywara
2020-06-01 10:14         ` André Przywara
2020-06-01 23:12         ` Rob Herring
2020-06-01 23:12           ` Rob Herring
2020-06-03 11:20           ` André Przywara
2020-06-03 11:20             ` André Przywara
2020-06-03 13:49             ` Rob Herring
2020-06-03 13:49               ` Rob Herring
2020-05-13 10:30 ` [PATCH v3 05/20] arm64: dts: arm: foundation: Move fixed clocks " Andre Przywara
2020-05-13 10:30   ` Andre Przywara
2020-05-13 10:30 ` [PATCH v3 06/20] arm64: dts: arm: juno: Move fixed devices " Andre Przywara
2020-05-13 10:30   ` Andre Przywara
2020-05-13 10:30 ` [PATCH v3 07/20] arm64: dts: juno: Fix mem-timer Andre Przywara
2020-05-13 10:30   ` Andre Przywara
2020-05-13 10:30 ` [PATCH v3 08/20] arm64: dts: arm: model: Fix GIC compatible names Andre Przywara
2020-05-13 10:30   ` Andre Przywara
2020-05-13 18:21   ` Sudeep Holla
2020-05-13 18:21     ` Sudeep Holla
2020-05-15 15:10     ` André Przywara
2020-05-15 15:10       ` André Przywara
2020-05-13 10:30 ` Andre Przywara [this message]
2020-05-13 10:30   ` [PATCH v3 09/20] arm64: dts: arm: juno: Fix GIC child nodes Andre Przywara
2020-05-13 10:30 ` [PATCH v3 10/20] arm64: dts: arm: foundation: " Andre Przywara
2020-05-13 10:30   ` Andre Przywara
2020-05-13 10:30 ` [PATCH v3 11/20] arm64: dts: arm: Fix ITS node names and #msi-cells Andre Przywara
2020-05-13 10:30   ` Andre Przywara
2020-05-13 10:30 ` [PATCH v3 12/20] arm64: dts: juno: usb: Use proper DT node name Andre Przywara
2020-05-13 10:30   ` Andre Przywara
2020-05-13 10:30 ` [PATCH v3 13/20] arm64: dts: arm: Fix serial node names Andre Przywara
2020-05-13 10:30   ` Andre Przywara
2020-05-13 10:30 ` [PATCH v3 14/20] arm64: dts: fvp: Fix SMMU DT node Andre Przywara
2020-05-13 10:30   ` Andre Przywara
2020-05-13 10:30 ` [PATCH v3 15/20] arm64: dts: arm: Fix bus node names Andre Przywara
2020-05-13 10:30   ` Andre Przywara
2020-05-13 10:30 ` [PATCH v3 16/20] arm64: dts: juno: Fix GPU interrupt order Andre Przywara
2020-05-13 10:30   ` Andre Przywara
2020-05-13 18:24   ` Sudeep Holla
2020-05-13 18:24     ` Sudeep Holla
2020-05-15 15:13     ` André Przywara
2020-05-15 15:13       ` André Przywara
2020-05-13 10:30 ` [PATCH v3 17/20] arm64: dts: arm: Fix VExpress LED names Andre Przywara
2020-05-13 10:30   ` Andre Przywara
2020-05-13 10:30 ` [PATCH v3 18/20] arm64: dts: juno: Fix SCPI shared mem node name Andre Przywara
2020-05-13 10:30   ` Andre Przywara
2020-05-13 10:30 ` [PATCH v3 19/20] dt-bindings: mali-midgard: Allow dma-coherent Andre Przywara
2020-05-13 10:30   ` Andre Przywara
2020-05-13 10:30   ` Andre Przywara
2020-05-15  3:16   ` Rob Herring
2020-05-15  3:16     ` Rob Herring
2020-05-15  3:16     ` Rob Herring
2020-05-13 10:30 ` [PATCH v3 20/20] dt-bindings: ehci/ohci: Allow iommus property Andre Przywara
2020-05-13 10:30   ` Andre Przywara
2020-05-13 18:28   ` Sudeep Holla
2020-05-13 18:28     ` Sudeep Holla
2020-05-15  3:17   ` Rob Herring
2020-05-15  3:17     ` Rob Herring
2020-05-18  8:15 ` [PATCH v3 00/20] dts/dt-bindings: Fix Arm Ltd. ARMv8 "boards" Sudeep Holla
2020-05-18  8:15   ` Sudeep Holla
2020-05-18 11:31 ` Sudeep Holla
2020-05-18 11:31   ` Sudeep Holla

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