All of lore.kernel.org
 help / color / mirror / Atom feed
From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org, qemu-devel@nongnu.org
Cc: alistair23@gmail.com,
	Richard Henderson <richard.henderson@linaro.org>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL v2 09/32] target/riscv: Move the hfence instructions to the rvh decode
Date: Fri, 19 Jun 2020 09:57:54 -0700	[thread overview]
Message-ID: <20200619165817.4144200-10-alistair.francis@wdc.com> (raw)
In-Reply-To: <20200619165817.4144200-1-alistair.francis@wdc.com>

Also correct the name of the VVMA instruction.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/insn32.decode                    |  8 ++-
 .../riscv/insn_trans/trans_privileged.inc.c   | 38 -------------
 target/riscv/insn_trans/trans_rvh.inc.c       | 57 +++++++++++++++++++
 target/riscv/translate.c                      |  1 +
 4 files changed, 63 insertions(+), 41 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_rvh.inc.c

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b883672e63..4c8d1215ce 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -64,7 +64,7 @@
 @r2      .......   ..... ..... ... ..... ....... %rs1 %rd
 
 @hfence_gvma ....... ..... .....   ... ..... ....... %rs2 %rs1
-@hfence_bvma ....... ..... .....   ... ..... ....... %rs2 %rs1
+@hfence_vvma ....... ..... .....   ... ..... ....... %rs2 %rs1
 
 @sfence_vma ....... ..... .....   ... ..... ....... %rs2 %rs1
 @sfence_vm  ....... ..... .....   ... ..... ....... %rs1
@@ -77,8 +77,6 @@ uret        0000000    00010 00000 000 00000 1110011
 sret        0001000    00010 00000 000 00000 1110011
 mret        0011000    00010 00000 000 00000 1110011
 wfi         0001000    00101 00000 000 00000 1110011
-hfence_gvma 0110001    ..... ..... 000 00000 1110011 @hfence_gvma
-hfence_bvma 0010001    ..... ..... 000 00000 1110011 @hfence_bvma
 sfence_vma  0001001    ..... ..... 000 00000 1110011 @sfence_vma
 sfence_vm   0001000    00100 ..... 000 00000 1110011 @sfence_vm
 
@@ -207,3 +205,7 @@ fcvt_w_d   1100001  00000 ..... ... ..... 1010011 @r2_rm
 fcvt_wu_d  1100001  00001 ..... ... ..... 1010011 @r2_rm
 fcvt_d_w   1101001  00000 ..... ... ..... 1010011 @r2_rm
 fcvt_d_wu  1101001  00001 ..... ... ..... 1010011 @r2_rm
+
+# *** RV32H Base Instruction Set ***
+hfence_gvma 0110001  .....  ..... 000 00000 1110011 @hfence_gvma
+hfence_vvma 0010001  .....  ..... 000 00000 1110011 @hfence_vvma
diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/insn_trans/trans_privileged.inc.c
index 5f26e0f5ea..2a61a853bf 100644
--- a/target/riscv/insn_trans/trans_privileged.inc.c
+++ b/target/riscv/insn_trans/trans_privileged.inc.c
@@ -95,41 +95,3 @@ static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a)
 {
     return false;
 }
-
-static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
-{
-#ifndef CONFIG_USER_ONLY
-    if (has_ext(ctx, RVH)) {
-        /* Hpervisor extensions exist */
-        /*
-         * if (env->priv == PRV_M ||
-         *   (env->priv == PRV_S &&
-         *    !riscv_cpu_virt_enabled(env) &&
-         *    get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
-         */
-            gen_helper_tlb_flush(cpu_env);
-            return true;
-        /* } */
-    }
-#endif
-    return false;
-}
-
-static bool trans_hfence_bvma(DisasContext *ctx, arg_sfence_vma *a)
-{
-#ifndef CONFIG_USER_ONLY
-    if (has_ext(ctx, RVH)) {
-        /* Hpervisor extensions exist */
-        /*
-         * if (env->priv == PRV_M ||
-         *   (env->priv == PRV_S &&
-         *    !riscv_cpu_virt_enabled(env) &&
-         *    get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
-         */
-            gen_helper_tlb_flush(cpu_env);
-            return true;
-        /* } */
-    }
-#endif
-    return false;
-}
diff --git a/target/riscv/insn_trans/trans_rvh.inc.c b/target/riscv/insn_trans/trans_rvh.inc.c
new file mode 100644
index 0000000000..2c0359819d
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvh.inc.c
@@ -0,0 +1,57 @@
+/*
+ * RISC-V translation routines for the RVXI Base Integer Instruction Set.
+ *
+ * Copyright (c) 2020 Western Digital
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
+{
+#ifndef CONFIG_USER_ONLY
+    if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
+        has_ext(ctx, RVH)) {
+        /* Hpervisor extensions exist */
+        /*
+         * if (env->priv == PRV_M ||
+         *   (env->priv == PRV_S &&
+         *    !riscv_cpu_virt_enabled(env) &&
+         *    get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
+         */
+            gen_helper_tlb_flush(cpu_env);
+            return true;
+        /* } */
+    }
+#endif
+    return false;
+}
+
+static bool trans_hfence_vvma(DisasContext *ctx, arg_sfence_vma *a)
+{
+#ifndef CONFIG_USER_ONLY
+    if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
+        has_ext(ctx, RVH)) {
+        /* Hpervisor extensions exist */
+        /*
+         * if (env->priv == PRV_M ||
+         *   (env->priv == PRV_S &&
+         *    !riscv_cpu_virt_enabled(env) &&
+         *    get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
+         */
+            gen_helper_tlb_flush(cpu_env);
+            return true;
+        /* } */
+    }
+#endif
+    return false;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 43bf7e39a6..ce71ca7a92 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -711,6 +711,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
 #include "insn_trans/trans_rva.inc.c"
 #include "insn_trans/trans_rvf.inc.c"
 #include "insn_trans/trans_rvd.inc.c"
+#include "insn_trans/trans_rvh.inc.c"
 #include "insn_trans/trans_privileged.inc.c"
 
 /* Include the auto-generated decoder for 16 bit insn */
-- 
2.27.0



  parent reply	other threads:[~2020-06-19 17:15 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
2020-06-19 16:57 ` [PULL v2 01/32] riscv: Add helper to make NaN-boxing for FP register Alistair Francis
2020-06-19 16:57 ` [PULL v2 02/32] sifive_e: Support the revB machine Alistair Francis
2020-06-19 16:57 ` [PULL v2 03/32] riscv: Generalize CPU init routine for the base CPU Alistair Francis
2020-06-23  6:22   ` Bin Meng
2020-06-23  9:08     ` Markus Armbruster
2020-06-23 23:28       ` Alistair Francis
2020-06-19 16:57 ` [PULL v2 04/32] riscv: Generalize CPU init routine for the gcsu CPU Alistair Francis
2020-06-19 16:57 ` [PULL v2 05/32] riscv: Generalize CPU init routine for the imacu CPU Alistair Francis
2020-06-19 16:57 ` [PULL v2 06/32] riscv: Keep the CPU init routine names consistent Alistair Francis
2020-06-19 16:57 ` [PULL v2 07/32] target/riscv: Set access as data_load when validating stage-2 PTEs Alistair Francis
2020-06-19 16:57 ` [PULL v2 08/32] target/riscv: Report errors validating 2nd-stage PTEs Alistair Francis
2020-06-19 16:57 ` Alistair Francis [this message]
2020-06-19 16:57 ` [PULL v2 10/32] target/riscv: Implement checks for hfence Alistair Francis
2020-06-19 16:57 ` [PULL v2 11/32] riscv/opentitan: Fix the ROM size Alistair Francis
2020-06-19 16:57 ` [PULL v2 12/32] hw/char: Initial commit of Ibex UART Alistair Francis
2020-06-19 16:57 ` [PULL v2 13/32] hw/intc: Initial commit of lowRISC Ibex PLIC Alistair Francis
2020-06-19 16:57 ` [PULL v2 14/32] riscv/opentitan: Connect the PLIC device Alistair Francis
2020-06-19 16:58 ` [PULL v2 15/32] riscv/opentitan: Connect the UART device Alistair Francis
2020-06-19 16:58 ` [PULL v2 16/32] target/riscv: Use a smaller guess size for no-MMU PMP Alistair Francis
2020-06-19 16:58 ` [PULL v2 17/32] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions Alistair Francis
2020-06-19 16:58 ` [PULL v2 18/32] hw/riscv: opentitan: " Alistair Francis
2020-06-19 16:58 ` [PULL v2 19/32] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit Alistair Francis
2020-06-19 16:58 ` [PULL v2 20/32] hw/riscv: sifive_u: Generate device tree node for OTP Alistair Francis
2020-06-19 16:58 ` [PULL v2 21/32] hw/riscv: sifive_gpio: Clean up the codes Alistair Francis
2020-06-19 16:58 ` [PULL v2 22/32] hw/riscv: sifive_gpio: Add a new 'ngpio' property Alistair Francis
2020-06-19 16:58 ` [PULL v2 23/32] hw/riscv: sifive_u: Hook a GPIO controller Alistair Francis
2020-06-19 16:58 ` [PULL v2 24/32] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs Alistair Francis
2020-06-19 16:58 ` [PULL v2 25/32] hw/riscv: sifive_u: Add reset functionality Alistair Francis
2020-06-19 16:58 ` [PULL v2 26/32] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name Alistair Francis
2020-06-19 16:58 ` [PULL v2 27/32] hw/riscv: sifive_u: Add a new property msel for MSEL pin state Alistair Francis
2020-06-19 16:58 ` [PULL v2 28/32] target/riscv: Rename IBEX CPU init routine Alistair Francis
2020-06-19 16:58 ` [PULL v2 29/32] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 Alistair Francis
2020-06-19 16:58 ` [PULL v2 30/32] hw/riscv: sifive_u: Support different boot source per MSEL pin state Alistair Francis
2020-06-19 16:58 ` [PULL v2 31/32] hw/riscv: sifive_u: Sort the SoC memmap table entries Alistair Francis
2020-06-19 16:58 ` [PULL v2 32/32] hw/riscv: sifive_u: Add a dummy DDR memory controller device Alistair Francis
2020-06-19 18:29 ` [PULL v2 00/32] riscv-to-apply queue no-reply
2020-06-22 15:01 ` Peter Maydell

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20200619165817.4144200-10-alistair.francis@wdc.com \
    --to=alistair.francis@wdc.com \
    --cc=alistair23@gmail.com \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    --cc=richard.henderson@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.