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From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org, qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Bin Meng <bin.meng@windriver.com>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL v2 18/32] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions
Date: Fri, 19 Jun 2020 09:58:03 -0700	[thread overview]
Message-ID: <20200619165817.4144200-19-alistair.francis@wdc.com> (raw)
In-Reply-To: <20200619165817.4144200-1-alistair.francis@wdc.com>

From: Bin Meng <bin.meng@windriver.com>

This was done in the virt & sifive_u codes, but opentitan codes were
missed. Remove the riscv_ prefix of the machine* and soc* functions.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-3-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-3-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/opentitan.c | 29 ++++++++++++++---------------
 1 file changed, 14 insertions(+), 15 deletions(-)

diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 675ce900bd..19223e4c29 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -53,7 +53,7 @@ static const struct MemmapEntry {
     [IBEX_PADCTRL] =        {  0x40160000,  0x10000 }
 };
 
-static void riscv_opentitan_init(MachineState *machine)
+static void opentitan_board_init(MachineState *machine)
 {
     const struct MemmapEntry *memmap = ibex_memmap;
     OpenTitanState *s = g_new0(OpenTitanState, 1);
@@ -70,7 +70,6 @@ static void riscv_opentitan_init(MachineState *machine)
     memory_region_add_subregion(sys_mem,
         memmap[IBEX_RAM].base, main_mem);
 
-
     if (machine->firmware) {
         riscv_load_firmware(machine->firmware, memmap[IBEX_RAM].base, NULL);
     }
@@ -80,17 +79,17 @@ static void riscv_opentitan_init(MachineState *machine)
     }
 }
 
-static void riscv_opentitan_machine_init(MachineClass *mc)
+static void opentitan_machine_init(MachineClass *mc)
 {
     mc->desc = "RISC-V Board compatible with OpenTitan";
-    mc->init = riscv_opentitan_init;
+    mc->init = opentitan_board_init;
     mc->max_cpus = 1;
     mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
 }
 
-DEFINE_MACHINE("opentitan", riscv_opentitan_machine_init)
+DEFINE_MACHINE("opentitan", opentitan_machine_init)
 
-static void riscv_lowrisc_ibex_soc_init(Object *obj)
+static void lowrisc_ibex_soc_init(Object *obj)
 {
     LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
 
@@ -101,7 +100,7 @@ static void riscv_lowrisc_ibex_soc_init(Object *obj)
     object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
 }
 
-static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
+static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
 {
     const struct MemmapEntry *memmap = ibex_memmap;
     MachineState *ms = MACHINE(qdev_get_machine());
@@ -186,26 +185,26 @@ static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
         memmap[IBEX_PADCTRL].base, memmap[IBEX_PADCTRL].size);
 }
 
-static void riscv_lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
+static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
 
-    dc->realize = riscv_lowrisc_ibex_soc_realize;
+    dc->realize = lowrisc_ibex_soc_realize;
     /* Reason: Uses serial_hds in realize function, thus can't be used twice */
     dc->user_creatable = false;
 }
 
-static const TypeInfo riscv_lowrisc_ibex_soc_type_info = {
+static const TypeInfo lowrisc_ibex_soc_type_info = {
     .name = TYPE_RISCV_IBEX_SOC,
     .parent = TYPE_DEVICE,
     .instance_size = sizeof(LowRISCIbexSoCState),
-    .instance_init = riscv_lowrisc_ibex_soc_init,
-    .class_init = riscv_lowrisc_ibex_soc_class_init,
+    .instance_init = lowrisc_ibex_soc_init,
+    .class_init = lowrisc_ibex_soc_class_init,
 };
 
-static void riscv_lowrisc_ibex_soc_register_types(void)
+static void lowrisc_ibex_soc_register_types(void)
 {
-    type_register_static(&riscv_lowrisc_ibex_soc_type_info);
+    type_register_static(&lowrisc_ibex_soc_type_info);
 }
 
-type_init(riscv_lowrisc_ibex_soc_register_types)
+type_init(lowrisc_ibex_soc_register_types)
-- 
2.27.0



  parent reply	other threads:[~2020-06-19 17:20 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-19 16:57 [PULL v2 00/32] riscv-to-apply queue Alistair Francis
2020-06-19 16:57 ` [PULL v2 01/32] riscv: Add helper to make NaN-boxing for FP register Alistair Francis
2020-06-19 16:57 ` [PULL v2 02/32] sifive_e: Support the revB machine Alistair Francis
2020-06-19 16:57 ` [PULL v2 03/32] riscv: Generalize CPU init routine for the base CPU Alistair Francis
2020-06-23  6:22   ` Bin Meng
2020-06-23  9:08     ` Markus Armbruster
2020-06-23 23:28       ` Alistair Francis
2020-06-19 16:57 ` [PULL v2 04/32] riscv: Generalize CPU init routine for the gcsu CPU Alistair Francis
2020-06-19 16:57 ` [PULL v2 05/32] riscv: Generalize CPU init routine for the imacu CPU Alistair Francis
2020-06-19 16:57 ` [PULL v2 06/32] riscv: Keep the CPU init routine names consistent Alistair Francis
2020-06-19 16:57 ` [PULL v2 07/32] target/riscv: Set access as data_load when validating stage-2 PTEs Alistair Francis
2020-06-19 16:57 ` [PULL v2 08/32] target/riscv: Report errors validating 2nd-stage PTEs Alistair Francis
2020-06-19 16:57 ` [PULL v2 09/32] target/riscv: Move the hfence instructions to the rvh decode Alistair Francis
2020-06-19 16:57 ` [PULL v2 10/32] target/riscv: Implement checks for hfence Alistair Francis
2020-06-19 16:57 ` [PULL v2 11/32] riscv/opentitan: Fix the ROM size Alistair Francis
2020-06-19 16:57 ` [PULL v2 12/32] hw/char: Initial commit of Ibex UART Alistair Francis
2020-06-19 16:57 ` [PULL v2 13/32] hw/intc: Initial commit of lowRISC Ibex PLIC Alistair Francis
2020-06-19 16:57 ` [PULL v2 14/32] riscv/opentitan: Connect the PLIC device Alistair Francis
2020-06-19 16:58 ` [PULL v2 15/32] riscv/opentitan: Connect the UART device Alistair Francis
2020-06-19 16:58 ` [PULL v2 16/32] target/riscv: Use a smaller guess size for no-MMU PMP Alistair Francis
2020-06-19 16:58 ` [PULL v2 17/32] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions Alistair Francis
2020-06-19 16:58 ` Alistair Francis [this message]
2020-06-19 16:58 ` [PULL v2 19/32] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit Alistair Francis
2020-06-19 16:58 ` [PULL v2 20/32] hw/riscv: sifive_u: Generate device tree node for OTP Alistair Francis
2020-06-19 16:58 ` [PULL v2 21/32] hw/riscv: sifive_gpio: Clean up the codes Alistair Francis
2020-06-19 16:58 ` [PULL v2 22/32] hw/riscv: sifive_gpio: Add a new 'ngpio' property Alistair Francis
2020-06-19 16:58 ` [PULL v2 23/32] hw/riscv: sifive_u: Hook a GPIO controller Alistair Francis
2020-06-19 16:58 ` [PULL v2 24/32] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs Alistair Francis
2020-06-19 16:58 ` [PULL v2 25/32] hw/riscv: sifive_u: Add reset functionality Alistair Francis
2020-06-19 16:58 ` [PULL v2 26/32] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name Alistair Francis
2020-06-19 16:58 ` [PULL v2 27/32] hw/riscv: sifive_u: Add a new property msel for MSEL pin state Alistair Francis
2020-06-19 16:58 ` [PULL v2 28/32] target/riscv: Rename IBEX CPU init routine Alistair Francis
2020-06-19 16:58 ` [PULL v2 29/32] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 Alistair Francis
2020-06-19 16:58 ` [PULL v2 30/32] hw/riscv: sifive_u: Support different boot source per MSEL pin state Alistair Francis
2020-06-19 16:58 ` [PULL v2 31/32] hw/riscv: sifive_u: Sort the SoC memmap table entries Alistair Francis
2020-06-19 16:58 ` [PULL v2 32/32] hw/riscv: sifive_u: Add a dummy DDR memory controller device Alistair Francis
2020-06-19 18:29 ` [PULL v2 00/32] riscv-to-apply queue no-reply
2020-06-22 15:01 ` Peter Maydell

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