From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>, Frank Chang <frank.chang@sifive.com>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Richard Henderson <richard.henderson@linaro.org>, Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [RFC v2 45/76] target/riscv: rvv-0.9: single-width bit shift instructions Date: Wed, 22 Jul 2020 17:16:08 +0800 [thread overview] Message-ID: <20200722091641.8834-46-frank.chang@sifive.com> (raw) In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> From: Frank Chang <frank.chang@sifive.com> Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits. Signed-off-by: Frank Chang <frank.chang@sifive.com> --- target/riscv/insn_trans/trans_rvv.inc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index d531c4edd1..3998011ef7 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1947,9 +1947,9 @@ GEN_OPIVX_GVEC_SHIFT_TRANS(vsll_vx, shls) GEN_OPIVX_GVEC_SHIFT_TRANS(vsrl_vx, shrs) GEN_OPIVX_GVEC_SHIFT_TRANS(vsra_vx, sars) -GEN_OPIVI_GVEC_TRANS(vsll_vi, IMM_ZX, vsll_vx, shli) -GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_ZX, vsrl_vx, shri) -GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_ZX, vsra_vx, sari) +GEN_OPIVI_GVEC_TRANS(vsll_vi, IMM_TRUNC_SEW, vsll_vx, shli) +GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_TRUNC_SEW, vsrl_vx, shri) +GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_TRUNC_SEW, vsra_vx, sari) /* Vector Narrowing Integer Right Shift Instructions */ static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a) -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Frank Chang <frank.chang@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, LIU Zhiwei <zhiwei_liu@c-sky.com>, Richard Henderson <richard.henderson@linaro.org> Subject: [RFC v2 45/76] target/riscv: rvv-0.9: single-width bit shift instructions Date: Wed, 22 Jul 2020 17:16:08 +0800 [thread overview] Message-ID: <20200722091641.8834-46-frank.chang@sifive.com> (raw) In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> From: Frank Chang <frank.chang@sifive.com> Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits. Signed-off-by: Frank Chang <frank.chang@sifive.com> --- target/riscv/insn_trans/trans_rvv.inc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index d531c4edd1..3998011ef7 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1947,9 +1947,9 @@ GEN_OPIVX_GVEC_SHIFT_TRANS(vsll_vx, shls) GEN_OPIVX_GVEC_SHIFT_TRANS(vsrl_vx, shrs) GEN_OPIVX_GVEC_SHIFT_TRANS(vsra_vx, sars) -GEN_OPIVI_GVEC_TRANS(vsll_vi, IMM_ZX, vsll_vx, shli) -GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_ZX, vsrl_vx, shri) -GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_ZX, vsra_vx, sari) +GEN_OPIVI_GVEC_TRANS(vsll_vi, IMM_TRUNC_SEW, vsll_vx, shli) +GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_TRUNC_SEW, vsrl_vx, shri) +GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_TRUNC_SEW, vsra_vx, sari) /* Vector Narrowing Integer Right Shift Instructions */ static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a) -- 2.17.1
next prev parent reply other threads:[~2020-07-22 9:45 UTC|newest] Thread overview: 292+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-07-22 9:15 [RFC v2 00/76] target/riscv: support vector extension v0.9 frank.chang 2020-07-22 9:15 ` [RFC v2 01/76] target/riscv: drop vector 0.7.1 support frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-22 16:37 ` Alistair Francis 2020-07-22 16:37 ` Alistair Francis 2020-07-27 19:54 ` Palmer Dabbelt 2020-07-27 19:54 ` Palmer Dabbelt 2020-07-27 19:55 ` Alistair Francis 2020-07-27 19:55 ` Alistair Francis 2020-07-30 8:07 ` Frank Chang 2020-07-30 8:07 ` Frank Chang 2020-07-30 12:27 ` Richard Henderson 2020-07-22 9:15 ` [RFC v2 02/76] target/riscv: rvv-0.9: support vector 0.9 frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-22 16:13 ` Richard Henderson 2020-07-22 16:13 ` Richard Henderson 2020-07-22 9:15 ` [RFC v2 03/76] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-22 16:18 ` Richard Henderson 2020-07-22 16:18 ` Richard Henderson 2020-07-22 9:15 ` [RFC v2 04/76] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64() frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-22 9:15 ` [RFC v2 05/76] target/riscv: fix return value of do_opivx_widen() frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-22 9:15 ` [RFC v2 06/76] target/riscv: fix vill bit index in vtype register frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-22 9:15 ` [RFC v2 07/76] target/riscv: Use FIELD_EX32() to extract wd field frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-22 16:19 ` Richard Henderson 2020-07-22 16:19 ` Richard Henderson 2020-07-22 9:15 ` [RFC v2 08/76] target/riscv: rvv-0.9: add mstatus VS field frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-22 16:33 ` Richard Henderson 2020-07-22 16:33 ` Richard Henderson 2020-07-22 9:15 ` [RFC v2 09/76] target/riscv: rvv-0.9: add sstatus " frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-22 16:34 ` Richard Henderson 2020-07-22 16:34 ` Richard Henderson 2020-07-22 9:15 ` [RFC v2 10/76] target/riscv: rvv-0.9: add translation-time vector context status frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-22 16:53 ` Richard Henderson 2020-07-22 16:53 ` Richard Henderson 2020-07-22 9:15 ` [RFC v2 11/76] target/riscv: rvv-0.9: remove vxrm and vxsat fields from fcsr register frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-22 16:54 ` Richard Henderson 2020-07-22 16:54 ` Richard Henderson 2020-07-22 9:15 ` [RFC v2 12/76] target/riscv: rvv-0.9: add vcsr register frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-22 16:57 ` Richard Henderson 2020-07-22 16:57 ` Richard Henderson 2020-07-22 9:15 ` [RFC v2 13/76] target/riscv: rvv-0.9: add vlenb register frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-22 16:58 ` Richard Henderson 2020-07-22 16:58 ` Richard Henderson 2020-07-22 9:15 ` [RFC v2 14/76] target/riscv: rvv-0.9: remove MLEN calculations frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-22 17:04 ` Richard Henderson 2020-07-22 17:04 ` Richard Henderson 2020-07-22 9:15 ` [RFC v2 15/76] target/riscv: rvv-0.9: add fractional LMUL frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-22 17:30 ` Richard Henderson 2020-07-22 17:30 ` Richard Henderson 2020-07-23 2:11 ` Frank Chang 2020-07-23 2:11 ` Frank Chang 2020-07-22 9:15 ` [RFC v2 16/76] target/riscv: rvv-0.9: add VMA and VTA frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-22 18:00 ` Richard Henderson 2020-07-22 18:00 ` Richard Henderson 2020-07-23 2:18 ` Frank Chang 2020-07-23 2:18 ` Frank Chang 2020-07-22 9:15 ` [RFC v2 17/76] target/riscv: rvv-0.9: update check functions frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-22 9:15 ` [RFC v2 18/76] target/riscv: introduce more imm value modes in translator functions frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-22 18:08 ` Richard Henderson 2020-07-22 18:08 ` Richard Henderson 2020-07-22 9:15 ` [RFC v2 19/76] target/riscv: rvv-0.9: add narrower_nanbox_fpr helper frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-22 19:15 ` Richard Henderson 2020-07-22 19:15 ` Richard Henderson 2020-07-23 7:13 ` Frank Chang 2020-07-23 7:13 ` Frank Chang 2020-07-23 16:14 ` Richard Henderson 2020-07-23 16:14 ` Richard Henderson 2020-07-22 9:15 ` [RFC v2 20/76] target/riscv: rvv-0.9: apply narrower nanbox helper in opfvf_trans frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-22 9:15 ` [RFC v2 21/76] target/riscv: rvv-0.9: configure instructions frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-22 20:00 ` Richard Henderson 2020-07-22 20:00 ` Richard Henderson 2020-07-22 9:15 ` [RFC v2 22/76] target/riscv: rvv-0.9: stride load and store instructions frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-22 9:15 ` [RFC v2 23/76] target/riscv: rvv-0.9: index " frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-22 9:15 ` [RFC v2 24/76] target/riscv: rvv-0.9: fix address index overflow bug of indexed load/store insns frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-22 9:15 ` [RFC v2 25/76] target/riscv: rvv-0.9: fault-only-first unit stride load frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-22 9:15 ` [RFC v2 26/76] target/riscv: rvv-0.9: amo operations frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-22 9:15 ` [RFC v2 27/76] target/riscv: rvv-0.9: load/store whole register instructions frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-29 20:30 ` Richard Henderson 2020-07-29 20:30 ` Richard Henderson 2020-07-22 9:15 ` [RFC v2 28/76] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-30 12:44 ` Richard Henderson 2020-07-30 12:44 ` Richard Henderson 2020-07-22 9:15 ` [RFC v2 29/76] target/riscv: rvv-0.9: take fractional LMUL into vector max elements calculation frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-30 12:52 ` Richard Henderson 2020-07-30 12:52 ` Richard Henderson 2020-07-22 9:15 ` [RFC v2 30/76] target/riscv: rvv-0.9: floating-point square-root instruction frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-30 13:02 ` Richard Henderson 2020-07-30 13:02 ` Richard Henderson 2020-07-22 9:15 ` [RFC v2 31/76] target/riscv: rvv-0.9: floating-point classify instructions frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-30 13:02 ` Richard Henderson 2020-07-30 13:02 ` Richard Henderson 2020-07-22 9:15 ` [RFC v2 32/76] target/riscv: rvv-0.9: mask population count instruction frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-30 13:05 ` Richard Henderson 2020-07-30 13:05 ` Richard Henderson 2020-07-22 9:15 ` [RFC v2 33/76] target/riscv: rvv-0.9: find-first-set mask bit instruction frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-30 13:13 ` Richard Henderson 2020-07-30 13:13 ` Richard Henderson 2020-07-22 9:15 ` [RFC v2 34/76] target/riscv: rvv-0.9: set-X-first mask bit instructions frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-30 13:26 ` Richard Henderson 2020-07-30 13:26 ` Richard Henderson 2020-07-22 9:15 ` [RFC v2 35/76] target/riscv: rvv-0.9: iota instruction frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-30 13:29 ` Richard Henderson 2020-07-30 13:29 ` Richard Henderson 2020-07-22 9:15 ` [RFC v2 36/76] target/riscv: rvv-0.9: element index instruction frank.chang 2020-07-22 9:15 ` frank.chang 2020-07-30 13:30 ` Richard Henderson 2020-07-30 13:30 ` Richard Henderson 2020-07-22 9:16 ` [RFC v2 37/76] target/riscv: rvv-0.9: allow load element with sign-extended frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-30 13:43 ` Richard Henderson 2020-07-30 13:43 ` Richard Henderson 2020-07-22 9:16 ` [RFC v2 38/76] target/riscv: rvv-0.9: register gather instructions frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-22 9:16 ` [RFC v2 39/76] target/riscv: rvv-0.9: integer scalar move instructions frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-30 14:50 ` Richard Henderson 2020-07-30 14:50 ` Richard Henderson 2020-07-22 9:16 ` [RFC v2 40/76] target/riscv: rvv-0.9: floating-point move instruction frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-30 19:57 ` Richard Henderson 2020-07-30 19:57 ` Richard Henderson 2020-07-30 20:05 ` Richard Henderson 2020-07-30 20:05 ` Richard Henderson 2020-07-22 9:16 ` [RFC v2 41/76] target/riscv: rvv-0.9: floating-point scalar move instructions frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-30 20:03 ` Richard Henderson 2020-07-30 20:03 ` Richard Henderson 2020-07-22 9:16 ` [RFC v2 42/76] target/riscv: rvv-0.9: whole register " frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-30 20:14 ` Richard Henderson 2020-07-30 20:14 ` Richard Henderson 2020-07-22 9:16 ` [RFC v2 43/76] target/riscv: rvv-0.9: integer extension instructions frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-30 20:35 ` Richard Henderson 2020-07-30 20:35 ` Richard Henderson 2020-07-31 10:17 ` Frank Chang 2020-07-31 10:17 ` Frank Chang 2020-07-31 17:30 ` Richard Henderson 2020-07-31 17:30 ` Richard Henderson 2020-07-22 9:16 ` [RFC v2 44/76] target/riscv: rvv-0.9: single-width averaging add and subtract instructions frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-30 20:45 ` Richard Henderson 2020-07-30 20:45 ` Richard Henderson 2020-07-22 9:16 ` frank.chang [this message] 2020-07-22 9:16 ` [RFC v2 45/76] target/riscv: rvv-0.9: single-width bit shift instructions frank.chang 2020-07-30 20:47 ` Richard Henderson 2020-07-30 20:47 ` Richard Henderson 2020-07-22 9:16 ` [RFC v2 46/76] target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-22 9:16 ` [RFC v2 47/76] target/riscv: rvv-0.9: narrowing integer right shift instructions frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-30 21:02 ` Richard Henderson 2020-07-30 21:02 ` Richard Henderson 2020-07-22 9:16 ` [RFC v2 48/76] target/riscv: rvv-0.9: widening integer multiply-add instructions frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-30 21:04 ` Richard Henderson 2020-07-30 21:04 ` Richard Henderson 2020-07-22 9:16 ` [RFC v2 49/76] target/riscv: rvv-0.9: quad-widening " frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-30 21:19 ` Richard Henderson 2020-07-30 21:19 ` Richard Henderson 2020-07-22 9:16 ` [RFC v2 50/76] target/riscv: rvv-0.9: single-width saturating add and subtract instructions frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-30 21:24 ` Richard Henderson 2020-07-30 21:24 ` Richard Henderson 2020-08-04 2:40 ` Frank Chang 2020-08-04 2:40 ` Frank Chang 2020-08-05 16:48 ` Richard Henderson 2020-08-05 16:48 ` Richard Henderson 2020-07-22 9:16 ` [RFC v2 51/76] target/riscv: rvv-0.9: integer comparison instructions frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-30 21:30 ` Richard Henderson 2020-07-30 21:30 ` Richard Henderson 2020-07-22 9:16 ` [RFC v2 52/76] fpu: implement full set compare for fp16 frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-22 11:35 ` Alex Bennée 2020-07-22 11:35 ` Alex Bennée 2020-07-22 9:16 ` [RFC v2 53/76] target/riscv: use softfloat lib float16 comparison functions frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-30 21:32 ` Richard Henderson 2020-07-30 21:32 ` Richard Henderson 2020-07-22 9:16 ` [RFC v2 54/76] target/riscv: rvv-0.9: floating-point compare instructions frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-22 9:16 ` [RFC v2 55/76] target/riscv: rvv-0.9: single-width integer reduction instructions frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-22 9:16 ` [RFC v2 56/76] target/riscv: rvv-0.9: widening " frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-31 15:13 ` Richard Henderson 2020-07-31 15:13 ` Richard Henderson 2020-07-22 9:16 ` [RFC v2 57/76] target/riscv: rvv-0.9: mask-register logical instructions frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-22 9:16 ` [RFC v2 58/76] target/riscv: rvv-0.9: slide instructions frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-31 15:57 ` Richard Henderson 2020-07-31 15:57 ` Richard Henderson 2020-07-22 9:16 ` [RFC v2 59/76] target/riscv: rvv-0.9: floating-point " frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-31 16:05 ` Richard Henderson 2020-07-31 16:05 ` Richard Henderson 2020-08-03 10:35 ` Frank Chang 2020-08-03 10:35 ` Frank Chang 2020-08-03 18:57 ` Richard Henderson 2020-08-03 18:57 ` Richard Henderson 2020-07-22 9:16 ` [RFC v2 60/76] target/riscv: rvv-0.9: narrowing fixed-point clip instructions frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-31 16:07 ` Richard Henderson 2020-07-31 16:07 ` Richard Henderson 2020-07-22 9:16 ` [RFC v2 61/76] target/riscv: rvv-0.9: floating-point/integer type-convert instructions frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-31 16:32 ` Richard Henderson 2020-07-31 16:32 ` Richard Henderson 2020-07-22 9:16 ` [RFC v2 62/76] target/riscv: rvv-0.9: single-width floating-point reduction frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-31 16:45 ` Richard Henderson 2020-07-31 16:45 ` Richard Henderson 2020-07-22 9:16 ` [RFC v2 63/76] target/riscv: rvv-0.9: widening floating-point reduction instructions frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-22 9:16 ` [RFC v2 64/76] target/riscv: rvv-0.9: single-width scaling shift instructions frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-31 16:59 ` Richard Henderson 2020-07-31 16:59 ` Richard Henderson 2020-07-22 9:16 ` [RFC v2 65/76] target/riscv: rvv-0.9: remove widening saturating scaled multiply-add frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-31 17:02 ` Richard Henderson 2020-07-31 17:02 ` Richard Henderson 2020-07-22 9:16 ` [RFC v2 66/76] target/riscv: rvv-0.9: remove vmford.vv and vmford.vf frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-31 17:03 ` Richard Henderson 2020-07-31 17:03 ` Richard Henderson 2020-07-22 9:16 ` [RFC v2 67/76] target/riscv: rvv-0.9: remove integer extract instruction frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-31 17:05 ` Richard Henderson 2020-07-31 17:05 ` Richard Henderson 2020-07-22 9:16 ` [RFC v2 68/76] fpu: add api to handle alternative sNaN propagation frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-22 9:16 ` [RFC v2 69/76] target/riscv: rvv-0.9: floating-point min/max instructions frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-22 9:16 ` [RFC v2 70/76] softfloat: add fp16 and uint8/int8 interconvert functions frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-22 9:16 ` [RFC v2 71/76] target/riscv: rvv-0.9: widening floating-point/integer type-convert frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-31 17:10 ` Richard Henderson 2020-07-31 17:10 ` Richard Henderson 2020-07-22 9:16 ` [RFC v2 72/76] target/riscv: rvv-0.9: narrowing " frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-31 17:18 ` Richard Henderson 2020-07-31 17:18 ` Richard Henderson 2020-07-22 9:16 ` [RFC v2 73/76] fpu: fix float16 nan check frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-22 9:16 ` [RFC v2 74/76] target/riscv: gdb: modify gdb csr xml file to align with csr register map frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-22 9:16 ` [RFC v2 75/76] target/riscv: gdb: support vector registers for rv64 frank.chang 2020-07-22 9:16 ` frank.chang 2020-07-31 17:25 ` Richard Henderson 2020-07-31 17:25 ` Richard Henderson 2020-08-03 11:31 ` Alex Bennée 2020-08-03 11:31 ` Alex Bennée 2020-07-22 9:16 ` [RFC v2 76/76] target/riscv: gdb: support vector registers for rv32 frank.chang 2020-07-22 9:16 ` frank.chang
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20200722091641.8834-46-frank.chang@sifive.com \ --to=frank.chang@sifive.com \ --cc=Alistair.Francis@wdc.com \ --cc=kbastian@mail.uni-paderborn.de \ --cc=palmer@dabbelt.com \ --cc=qemu-devel@nongnu.org \ --cc=qemu-riscv@nongnu.org \ --cc=richard.henderson@linaro.org \ --cc=sagark@eecs.berkeley.edu \ --cc=zhiwei_liu@c-sky.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.