From: frank.chang@sifive.com
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>,
Frank Chang <frank.chang@sifive.com>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [RFC v2 46/76] target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow
Date: Wed, 22 Jul 2020 17:16:09 +0800 [thread overview]
Message-ID: <20200722091641.8834-47-frank.chang@sifive.com> (raw)
In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com>
From: Frank Chang <frank.chang@sifive.com>
Clear tail elements only if VTA is agnostic.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 20 +++++-----
target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
target/riscv/vector_helper.c | 50 ++++++++++++++-----------
3 files changed, 40 insertions(+), 32 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 0521ca4ab4..481f909d47 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -324,16 +324,16 @@ vwsubu_wv 110110 . ..... ..... 010 ..... 1010111 @r_vm
vwsubu_wx 110110 . ..... ..... 110 ..... 1010111 @r_vm
vwsub_wv 110111 . ..... ..... 010 ..... 1010111 @r_vm
vwsub_wx 110111 . ..... ..... 110 ..... 1010111 @r_vm
-vadc_vvm 010000 1 ..... ..... 000 ..... 1010111 @r_vm_1
-vadc_vxm 010000 1 ..... ..... 100 ..... 1010111 @r_vm_1
-vadc_vim 010000 1 ..... ..... 011 ..... 1010111 @r_vm_1
-vmadc_vvm 010001 1 ..... ..... 000 ..... 1010111 @r_vm_1
-vmadc_vxm 010001 1 ..... ..... 100 ..... 1010111 @r_vm_1
-vmadc_vim 010001 1 ..... ..... 011 ..... 1010111 @r_vm_1
-vsbc_vvm 010010 1 ..... ..... 000 ..... 1010111 @r_vm_1
-vsbc_vxm 010010 1 ..... ..... 100 ..... 1010111 @r_vm_1
-vmsbc_vvm 010011 1 ..... ..... 000 ..... 1010111 @r_vm_1
-vmsbc_vxm 010011 1 ..... ..... 100 ..... 1010111 @r_vm_1
+vadc_vvm 010000 0 ..... ..... 000 ..... 1010111 @r_vm_1
+vadc_vxm 010000 0 ..... ..... 100 ..... 1010111 @r_vm_1
+vadc_vim 010000 0 ..... ..... 011 ..... 1010111 @r_vm_1
+vmadc_vvm 010001 . ..... ..... 000 ..... 1010111 @r_vm
+vmadc_vxm 010001 . ..... ..... 100 ..... 1010111 @r_vm
+vmadc_vim 010001 . ..... ..... 011 ..... 1010111 @r_vm
+vsbc_vvm 010010 0 ..... ..... 000 ..... 1010111 @r_vm_1
+vsbc_vxm 010010 0 ..... ..... 100 ..... 1010111 @r_vm_1
+vmsbc_vvm 010011 . ..... ..... 000 ..... 1010111 @r_vm
+vmsbc_vxm 010011 . ..... ..... 100 ..... 1010111 @r_vm
vand_vv 001001 . ..... ..... 000 ..... 1010111 @r_vm
vand_vx 001001 . ..... ..... 100 ..... 1010111 @r_vm
vand_vi 001001 . ..... ..... 011 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 3998011ef7..45853812f7 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1806,7 +1806,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
/*
* For vadc and vsbc, an illegal instruction exception is raised if the
- * destination vector register is v0 and LMUL > 1. (Section 12.3)
+ * destination vector register is v0 and LMUL > 1. (Section 12.4)
*/
static bool opivv_vadc_check(DisasContext *s, arg_rmrr *a)
{
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index aa940080a7..95248238df 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1316,24 +1316,28 @@ GEN_VEXT_VADC_VXM(vsbc_vxm_d, uint64_t, H8, DO_VSBC, clearq)
(__typeof(N))(N + M) < N)
#define DO_MSBC(N, M, C) (C ? N <= M : N < M)
-#define GEN_VEXT_VMADC_VVM(NAME, ETYPE, H, DO_OP) \
-void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
- CPURISCVState *env, uint32_t desc) \
-{ \
- uint32_t vl = env->vl; \
- uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
- uint32_t i; \
- \
- for (i = 0; i < vl; i++) { \
- ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
- ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- uint8_t carry = vext_elem_mask(v0, i); \
- \
- vext_set_elem_mask(vd, i, DO_OP(s2, s1, carry)); \
- } \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
- } \
+#define GEN_VEXT_VMADC_VVM(NAME, ETYPE, H, DO_OP) \
+void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t vl = env->vl; \
+ uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false);\
+ uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
+ uint32_t i; \
+ \
+ for (i = 0; i < vl; i++) { \
+ ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
+ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
+ uint8_t carry = !vm ? vext_elem_mask(v0, i) : 0; \
+ \
+ vext_set_elem_mask(vd, i, DO_OP(s2, s1, carry)); \
+ } \
+ if (vta == 1) { \
+ for (; i < vlmax; i++) { \
+ vext_set_elem_mask(vd, i, 1); \
+ } \
+ } \
}
GEN_VEXT_VMADC_VVM(vmadc_vvm_b, uint8_t, H1, DO_MADC)
@@ -1352,17 +1356,21 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
{ \
uint32_t vl = env->vl; \
uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false);\
+ uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- uint8_t carry = vext_elem_mask(v0, i); \
+ uint8_t carry = !vm ? vext_elem_mask(v0, i) : 0; \
\
vext_set_elem_mask(vd, i, \
DO_OP(s2, (ETYPE)(target_long)s1, carry)); \
} \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
+ if (vta == 1) { \
+ for (; i < vlmax; i++) { \
+ vext_set_elem_mask(vd, i, 1); \
+ } \
} \
}
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: frank.chang@sifive.com
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Frank Chang <frank.chang@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
LIU Zhiwei <zhiwei_liu@c-sky.com>,
Richard Henderson <richard.henderson@linaro.org>
Subject: [RFC v2 46/76] target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow
Date: Wed, 22 Jul 2020 17:16:09 +0800 [thread overview]
Message-ID: <20200722091641.8834-47-frank.chang@sifive.com> (raw)
In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com>
From: Frank Chang <frank.chang@sifive.com>
Clear tail elements only if VTA is agnostic.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 20 +++++-----
target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
target/riscv/vector_helper.c | 50 ++++++++++++++-----------
3 files changed, 40 insertions(+), 32 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 0521ca4ab4..481f909d47 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -324,16 +324,16 @@ vwsubu_wv 110110 . ..... ..... 010 ..... 1010111 @r_vm
vwsubu_wx 110110 . ..... ..... 110 ..... 1010111 @r_vm
vwsub_wv 110111 . ..... ..... 010 ..... 1010111 @r_vm
vwsub_wx 110111 . ..... ..... 110 ..... 1010111 @r_vm
-vadc_vvm 010000 1 ..... ..... 000 ..... 1010111 @r_vm_1
-vadc_vxm 010000 1 ..... ..... 100 ..... 1010111 @r_vm_1
-vadc_vim 010000 1 ..... ..... 011 ..... 1010111 @r_vm_1
-vmadc_vvm 010001 1 ..... ..... 000 ..... 1010111 @r_vm_1
-vmadc_vxm 010001 1 ..... ..... 100 ..... 1010111 @r_vm_1
-vmadc_vim 010001 1 ..... ..... 011 ..... 1010111 @r_vm_1
-vsbc_vvm 010010 1 ..... ..... 000 ..... 1010111 @r_vm_1
-vsbc_vxm 010010 1 ..... ..... 100 ..... 1010111 @r_vm_1
-vmsbc_vvm 010011 1 ..... ..... 000 ..... 1010111 @r_vm_1
-vmsbc_vxm 010011 1 ..... ..... 100 ..... 1010111 @r_vm_1
+vadc_vvm 010000 0 ..... ..... 000 ..... 1010111 @r_vm_1
+vadc_vxm 010000 0 ..... ..... 100 ..... 1010111 @r_vm_1
+vadc_vim 010000 0 ..... ..... 011 ..... 1010111 @r_vm_1
+vmadc_vvm 010001 . ..... ..... 000 ..... 1010111 @r_vm
+vmadc_vxm 010001 . ..... ..... 100 ..... 1010111 @r_vm
+vmadc_vim 010001 . ..... ..... 011 ..... 1010111 @r_vm
+vsbc_vvm 010010 0 ..... ..... 000 ..... 1010111 @r_vm_1
+vsbc_vxm 010010 0 ..... ..... 100 ..... 1010111 @r_vm_1
+vmsbc_vvm 010011 . ..... ..... 000 ..... 1010111 @r_vm
+vmsbc_vxm 010011 . ..... ..... 100 ..... 1010111 @r_vm
vand_vv 001001 . ..... ..... 000 ..... 1010111 @r_vm
vand_vx 001001 . ..... ..... 100 ..... 1010111 @r_vm
vand_vi 001001 . ..... ..... 011 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 3998011ef7..45853812f7 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1806,7 +1806,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
/*
* For vadc and vsbc, an illegal instruction exception is raised if the
- * destination vector register is v0 and LMUL > 1. (Section 12.3)
+ * destination vector register is v0 and LMUL > 1. (Section 12.4)
*/
static bool opivv_vadc_check(DisasContext *s, arg_rmrr *a)
{
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index aa940080a7..95248238df 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1316,24 +1316,28 @@ GEN_VEXT_VADC_VXM(vsbc_vxm_d, uint64_t, H8, DO_VSBC, clearq)
(__typeof(N))(N + M) < N)
#define DO_MSBC(N, M, C) (C ? N <= M : N < M)
-#define GEN_VEXT_VMADC_VVM(NAME, ETYPE, H, DO_OP) \
-void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
- CPURISCVState *env, uint32_t desc) \
-{ \
- uint32_t vl = env->vl; \
- uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
- uint32_t i; \
- \
- for (i = 0; i < vl; i++) { \
- ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
- ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- uint8_t carry = vext_elem_mask(v0, i); \
- \
- vext_set_elem_mask(vd, i, DO_OP(s2, s1, carry)); \
- } \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
- } \
+#define GEN_VEXT_VMADC_VVM(NAME, ETYPE, H, DO_OP) \
+void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t vl = env->vl; \
+ uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false);\
+ uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
+ uint32_t i; \
+ \
+ for (i = 0; i < vl; i++) { \
+ ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
+ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
+ uint8_t carry = !vm ? vext_elem_mask(v0, i) : 0; \
+ \
+ vext_set_elem_mask(vd, i, DO_OP(s2, s1, carry)); \
+ } \
+ if (vta == 1) { \
+ for (; i < vlmax; i++) { \
+ vext_set_elem_mask(vd, i, 1); \
+ } \
+ } \
}
GEN_VEXT_VMADC_VVM(vmadc_vvm_b, uint8_t, H1, DO_MADC)
@@ -1352,17 +1356,21 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
{ \
uint32_t vl = env->vl; \
uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false);\
+ uint32_t vm = vext_vm(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- uint8_t carry = vext_elem_mask(v0, i); \
+ uint8_t carry = !vm ? vext_elem_mask(v0, i) : 0; \
\
vext_set_elem_mask(vd, i, \
DO_OP(s2, (ETYPE)(target_long)s1, carry)); \
} \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
+ if (vta == 1) { \
+ for (; i < vlmax; i++) { \
+ vext_set_elem_mask(vd, i, 1); \
+ } \
} \
}
--
2.17.1
next prev parent reply other threads:[~2020-07-22 9:47 UTC|newest]
Thread overview: 292+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-22 9:15 [RFC v2 00/76] target/riscv: support vector extension v0.9 frank.chang
2020-07-22 9:15 ` [RFC v2 01/76] target/riscv: drop vector 0.7.1 support frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-22 16:37 ` Alistair Francis
2020-07-22 16:37 ` Alistair Francis
2020-07-27 19:54 ` Palmer Dabbelt
2020-07-27 19:54 ` Palmer Dabbelt
2020-07-27 19:55 ` Alistair Francis
2020-07-27 19:55 ` Alistair Francis
2020-07-30 8:07 ` Frank Chang
2020-07-30 8:07 ` Frank Chang
2020-07-30 12:27 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 02/76] target/riscv: rvv-0.9: support vector 0.9 frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-22 16:13 ` Richard Henderson
2020-07-22 16:13 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 03/76] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-22 16:18 ` Richard Henderson
2020-07-22 16:18 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 04/76] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64() frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-22 9:15 ` [RFC v2 05/76] target/riscv: fix return value of do_opivx_widen() frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-22 9:15 ` [RFC v2 06/76] target/riscv: fix vill bit index in vtype register frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-22 9:15 ` [RFC v2 07/76] target/riscv: Use FIELD_EX32() to extract wd field frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-22 16:19 ` Richard Henderson
2020-07-22 16:19 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 08/76] target/riscv: rvv-0.9: add mstatus VS field frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-22 16:33 ` Richard Henderson
2020-07-22 16:33 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 09/76] target/riscv: rvv-0.9: add sstatus " frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-22 16:34 ` Richard Henderson
2020-07-22 16:34 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 10/76] target/riscv: rvv-0.9: add translation-time vector context status frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-22 16:53 ` Richard Henderson
2020-07-22 16:53 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 11/76] target/riscv: rvv-0.9: remove vxrm and vxsat fields from fcsr register frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-22 16:54 ` Richard Henderson
2020-07-22 16:54 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 12/76] target/riscv: rvv-0.9: add vcsr register frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-22 16:57 ` Richard Henderson
2020-07-22 16:57 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 13/76] target/riscv: rvv-0.9: add vlenb register frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-22 16:58 ` Richard Henderson
2020-07-22 16:58 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 14/76] target/riscv: rvv-0.9: remove MLEN calculations frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-22 17:04 ` Richard Henderson
2020-07-22 17:04 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 15/76] target/riscv: rvv-0.9: add fractional LMUL frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-22 17:30 ` Richard Henderson
2020-07-22 17:30 ` Richard Henderson
2020-07-23 2:11 ` Frank Chang
2020-07-23 2:11 ` Frank Chang
2020-07-22 9:15 ` [RFC v2 16/76] target/riscv: rvv-0.9: add VMA and VTA frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-22 18:00 ` Richard Henderson
2020-07-22 18:00 ` Richard Henderson
2020-07-23 2:18 ` Frank Chang
2020-07-23 2:18 ` Frank Chang
2020-07-22 9:15 ` [RFC v2 17/76] target/riscv: rvv-0.9: update check functions frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-22 9:15 ` [RFC v2 18/76] target/riscv: introduce more imm value modes in translator functions frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-22 18:08 ` Richard Henderson
2020-07-22 18:08 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 19/76] target/riscv: rvv-0.9: add narrower_nanbox_fpr helper frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-22 19:15 ` Richard Henderson
2020-07-22 19:15 ` Richard Henderson
2020-07-23 7:13 ` Frank Chang
2020-07-23 7:13 ` Frank Chang
2020-07-23 16:14 ` Richard Henderson
2020-07-23 16:14 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 20/76] target/riscv: rvv-0.9: apply narrower nanbox helper in opfvf_trans frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-22 9:15 ` [RFC v2 21/76] target/riscv: rvv-0.9: configure instructions frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-22 20:00 ` Richard Henderson
2020-07-22 20:00 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 22/76] target/riscv: rvv-0.9: stride load and store instructions frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-22 9:15 ` [RFC v2 23/76] target/riscv: rvv-0.9: index " frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-22 9:15 ` [RFC v2 24/76] target/riscv: rvv-0.9: fix address index overflow bug of indexed load/store insns frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-22 9:15 ` [RFC v2 25/76] target/riscv: rvv-0.9: fault-only-first unit stride load frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-22 9:15 ` [RFC v2 26/76] target/riscv: rvv-0.9: amo operations frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-22 9:15 ` [RFC v2 27/76] target/riscv: rvv-0.9: load/store whole register instructions frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-29 20:30 ` Richard Henderson
2020-07-29 20:30 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 28/76] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-30 12:44 ` Richard Henderson
2020-07-30 12:44 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 29/76] target/riscv: rvv-0.9: take fractional LMUL into vector max elements calculation frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-30 12:52 ` Richard Henderson
2020-07-30 12:52 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 30/76] target/riscv: rvv-0.9: floating-point square-root instruction frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-30 13:02 ` Richard Henderson
2020-07-30 13:02 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 31/76] target/riscv: rvv-0.9: floating-point classify instructions frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-30 13:02 ` Richard Henderson
2020-07-30 13:02 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 32/76] target/riscv: rvv-0.9: mask population count instruction frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-30 13:05 ` Richard Henderson
2020-07-30 13:05 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 33/76] target/riscv: rvv-0.9: find-first-set mask bit instruction frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-30 13:13 ` Richard Henderson
2020-07-30 13:13 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 34/76] target/riscv: rvv-0.9: set-X-first mask bit instructions frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-30 13:26 ` Richard Henderson
2020-07-30 13:26 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 35/76] target/riscv: rvv-0.9: iota instruction frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-30 13:29 ` Richard Henderson
2020-07-30 13:29 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 36/76] target/riscv: rvv-0.9: element index instruction frank.chang
2020-07-22 9:15 ` frank.chang
2020-07-30 13:30 ` Richard Henderson
2020-07-30 13:30 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 37/76] target/riscv: rvv-0.9: allow load element with sign-extended frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-30 13:43 ` Richard Henderson
2020-07-30 13:43 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 38/76] target/riscv: rvv-0.9: register gather instructions frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-22 9:16 ` [RFC v2 39/76] target/riscv: rvv-0.9: integer scalar move instructions frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-30 14:50 ` Richard Henderson
2020-07-30 14:50 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 40/76] target/riscv: rvv-0.9: floating-point move instruction frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-30 19:57 ` Richard Henderson
2020-07-30 19:57 ` Richard Henderson
2020-07-30 20:05 ` Richard Henderson
2020-07-30 20:05 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 41/76] target/riscv: rvv-0.9: floating-point scalar move instructions frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-30 20:03 ` Richard Henderson
2020-07-30 20:03 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 42/76] target/riscv: rvv-0.9: whole register " frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-30 20:14 ` Richard Henderson
2020-07-30 20:14 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 43/76] target/riscv: rvv-0.9: integer extension instructions frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-30 20:35 ` Richard Henderson
2020-07-30 20:35 ` Richard Henderson
2020-07-31 10:17 ` Frank Chang
2020-07-31 10:17 ` Frank Chang
2020-07-31 17:30 ` Richard Henderson
2020-07-31 17:30 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 44/76] target/riscv: rvv-0.9: single-width averaging add and subtract instructions frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-30 20:45 ` Richard Henderson
2020-07-30 20:45 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 45/76] target/riscv: rvv-0.9: single-width bit shift instructions frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-30 20:47 ` Richard Henderson
2020-07-30 20:47 ` Richard Henderson
2020-07-22 9:16 ` frank.chang [this message]
2020-07-22 9:16 ` [RFC v2 46/76] target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow frank.chang
2020-07-22 9:16 ` [RFC v2 47/76] target/riscv: rvv-0.9: narrowing integer right shift instructions frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-30 21:02 ` Richard Henderson
2020-07-30 21:02 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 48/76] target/riscv: rvv-0.9: widening integer multiply-add instructions frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-30 21:04 ` Richard Henderson
2020-07-30 21:04 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 49/76] target/riscv: rvv-0.9: quad-widening " frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-30 21:19 ` Richard Henderson
2020-07-30 21:19 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 50/76] target/riscv: rvv-0.9: single-width saturating add and subtract instructions frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-30 21:24 ` Richard Henderson
2020-07-30 21:24 ` Richard Henderson
2020-08-04 2:40 ` Frank Chang
2020-08-04 2:40 ` Frank Chang
2020-08-05 16:48 ` Richard Henderson
2020-08-05 16:48 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 51/76] target/riscv: rvv-0.9: integer comparison instructions frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-30 21:30 ` Richard Henderson
2020-07-30 21:30 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 52/76] fpu: implement full set compare for fp16 frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-22 11:35 ` Alex Bennée
2020-07-22 11:35 ` Alex Bennée
2020-07-22 9:16 ` [RFC v2 53/76] target/riscv: use softfloat lib float16 comparison functions frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-30 21:32 ` Richard Henderson
2020-07-30 21:32 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 54/76] target/riscv: rvv-0.9: floating-point compare instructions frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-22 9:16 ` [RFC v2 55/76] target/riscv: rvv-0.9: single-width integer reduction instructions frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-22 9:16 ` [RFC v2 56/76] target/riscv: rvv-0.9: widening " frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-31 15:13 ` Richard Henderson
2020-07-31 15:13 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 57/76] target/riscv: rvv-0.9: mask-register logical instructions frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-22 9:16 ` [RFC v2 58/76] target/riscv: rvv-0.9: slide instructions frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-31 15:57 ` Richard Henderson
2020-07-31 15:57 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 59/76] target/riscv: rvv-0.9: floating-point " frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-31 16:05 ` Richard Henderson
2020-07-31 16:05 ` Richard Henderson
2020-08-03 10:35 ` Frank Chang
2020-08-03 10:35 ` Frank Chang
2020-08-03 18:57 ` Richard Henderson
2020-08-03 18:57 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 60/76] target/riscv: rvv-0.9: narrowing fixed-point clip instructions frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-31 16:07 ` Richard Henderson
2020-07-31 16:07 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 61/76] target/riscv: rvv-0.9: floating-point/integer type-convert instructions frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-31 16:32 ` Richard Henderson
2020-07-31 16:32 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 62/76] target/riscv: rvv-0.9: single-width floating-point reduction frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-31 16:45 ` Richard Henderson
2020-07-31 16:45 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 63/76] target/riscv: rvv-0.9: widening floating-point reduction instructions frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-22 9:16 ` [RFC v2 64/76] target/riscv: rvv-0.9: single-width scaling shift instructions frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-31 16:59 ` Richard Henderson
2020-07-31 16:59 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 65/76] target/riscv: rvv-0.9: remove widening saturating scaled multiply-add frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-31 17:02 ` Richard Henderson
2020-07-31 17:02 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 66/76] target/riscv: rvv-0.9: remove vmford.vv and vmford.vf frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-31 17:03 ` Richard Henderson
2020-07-31 17:03 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 67/76] target/riscv: rvv-0.9: remove integer extract instruction frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-31 17:05 ` Richard Henderson
2020-07-31 17:05 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 68/76] fpu: add api to handle alternative sNaN propagation frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-22 9:16 ` [RFC v2 69/76] target/riscv: rvv-0.9: floating-point min/max instructions frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-22 9:16 ` [RFC v2 70/76] softfloat: add fp16 and uint8/int8 interconvert functions frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-22 9:16 ` [RFC v2 71/76] target/riscv: rvv-0.9: widening floating-point/integer type-convert frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-31 17:10 ` Richard Henderson
2020-07-31 17:10 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 72/76] target/riscv: rvv-0.9: narrowing " frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-31 17:18 ` Richard Henderson
2020-07-31 17:18 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 73/76] fpu: fix float16 nan check frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-22 9:16 ` [RFC v2 74/76] target/riscv: gdb: modify gdb csr xml file to align with csr register map frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-22 9:16 ` [RFC v2 75/76] target/riscv: gdb: support vector registers for rv64 frank.chang
2020-07-22 9:16 ` frank.chang
2020-07-31 17:25 ` Richard Henderson
2020-07-31 17:25 ` Richard Henderson
2020-08-03 11:31 ` Alex Bennée
2020-08-03 11:31 ` Alex Bennée
2020-07-22 9:16 ` [RFC v2 76/76] target/riscv: gdb: support vector registers for rv32 frank.chang
2020-07-22 9:16 ` frank.chang
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