From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [Intel-gfx] [PATCH v5 15/22] drm/i915/dg1: Update voltage swing tables for DP
Date: Fri, 24 Jul 2020 14:39:11 -0700 [thread overview]
Message-ID: <20200724213918.27424-16-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20200724213918.27424-1-lucas.demarchi@intel.com>
From: Matt Roper <matthew.d.roper@intel.com>
DG1's vswing tables are the same for eDP and HDMI but have slight
differences from ICL/TGL for DP.
Bspec: 49291
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 34 ++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 714b2bc96f23..c19d5a375eba 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
{ 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
};
+static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr[] = {
+ /* NT mV Trans mV db */
+ { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
+ { 0xA, 0x48, 0x35, 0x00, 0x0A }, /* 350 500 3.1 */
+ { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
+ { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */
+ { 0xA, 0x43, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
+ { 0xC, 0x60, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
+ { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
+ { 0xC, 0x60, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */
+ { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 600 900 3.5 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
+};
+
+static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr2[] = {
+ /* NT mV Trans mV db */
+ { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
+ { 0xA, 0x48, 0x35, 0x00, 0x0A }, /* 350 500 3.1 */
+ { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
+ { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */
+ { 0xA, 0x43, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
+ { 0xC, 0x60, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
+ { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
+ { 0xC, 0x58, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */
+ { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
+};
+
struct icl_mg_phy_ddi_buf_trans {
u32 cri_txdeemph_override_11_6;
u32 cri_txdeemph_override_5_0;
@@ -1034,6 +1062,12 @@ icl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
} else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
return icl_combo_phy_ddi_translations_edp_hbr2;
+ } else if (IS_DG1(dev_priv) && rate > 270000) {
+ *n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr2);
+ return dg1_combo_phy_ddi_translations_dp_hbr2;
+ } else if (IS_DG1(dev_priv)) {
+ *n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr);
+ return dg1_combo_phy_ddi_translations_dp_hbr;
}
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
--
2.26.2
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next prev parent reply other threads:[~2020-07-24 21:39 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-24 21:38 [Intel-gfx] [PATCH v5 00/22] Introduce DG1 Lucas De Marchi
2020-07-24 21:38 ` [Intel-gfx] [PATCH v5 01/22] drm/i915/dg1: Initialize RAWCLK properly Lucas De Marchi
2020-07-28 16:35 ` Souza, Jose
2020-07-24 21:38 ` [Intel-gfx] [PATCH v5 02/22] drm/i915/dg1: Define MOCS table for DG1 Lucas De Marchi
2020-07-28 19:38 ` Matt Roper
2020-07-24 21:38 ` [Intel-gfx] [PATCH v5 03/22] drm/i915/dg1: Add DG1 power wells Lucas De Marchi
2020-07-28 20:51 ` Matt Roper
2020-08-13 7:59 ` Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 04/22] drm/i915/dg1: Increase mmio size to 4MB Lucas De Marchi
2020-07-28 21:48 ` Matt Roper
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 05/22] drm/i915/dg1: Wait for pcode/uncore handshake at startup Lucas De Marchi
2020-08-03 23:24 ` Souza, Jose
2020-08-24 19:24 ` Lucas De Marchi
2020-08-24 19:29 ` Souza, Jose
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 06/22] drm/i915/dg1: Add DPLL macros for DG1 Lucas De Marchi
2020-07-28 21:54 ` Matt Roper
2020-08-13 8:07 ` Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 07/22] drm/i915/dg1: Add and setup DPLLs " Lucas De Marchi
2020-07-28 22:14 ` Matt Roper
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 08/22] drm/i915/dg1: Enable DPLL " Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 09/22] drm/i915/dg1: add hpd interrupt handling Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 10/22] drm/i915/dg1: invert HPD pins Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 11/22] drm/i915/dg1: gmbus pin mapping Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 12/22] drm/i915/dg1: Enable first 2 ports for DG1 Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 13/22] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 14/22] drm/i915/dg1: Update comp master/slave relationships for PHYs Lucas De Marchi
2020-07-24 21:39 ` Lucas De Marchi [this message]
2020-08-03 23:48 ` [Intel-gfx] [PATCH v5 15/22] drm/i915/dg1: Update voltage swing tables for DP Souza, Jose
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 16/22] drm/i915/dg1: provide port/phy mapping for vbt Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 17/22] drm/i915/dg1: map/unmap pll clocks Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 18/22] drm/i915/dg1: enable PORT C/D aka D/E Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 19/22] drm/i915/dg1: Load DMC Lucas De Marchi
2020-08-03 23:27 ` Souza, Jose
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 20/22] drm/i915/dg1: Add initial DG1 workarounds Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 21/22] drm/i915/dg1: DG1 does not support DC6 Lucas De Marchi
2020-08-03 23:33 ` Souza, Jose
2020-08-24 21:26 ` Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 22/22] drm/i915/dg1: Change DMC_DEBUG{1, 2} registers Lucas De Marchi
2020-08-03 23:31 ` Souza, Jose
2020-08-07 13:14 ` Anshuman Gupta
2020-08-07 17:26 ` Souza, Jose
2020-08-10 5:48 ` Anshuman Gupta
2020-08-13 7:56 ` Lucas De Marchi
2020-07-24 21:45 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 Patchwork
2020-07-24 21:46 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-07-24 22:08 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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