Re: [Intel-gfx] [PATCH v5 01/22] drm/i915/dg1: Initialize RAWCLK properly

["Souza, Jose" <jose.souza@intel.com>]

On Fri, 2020-07-24 at 14:38 -0700, Lucas De Marchi wrote:
> From: Matt Roper <
> matthew.d.roper@intel.com
> >
> 
> DG1 always uses a 38.4 MHz rawclk rather than the 19.2/24 MHz
> frequencies on CNP+.  Note that register bits associated with this
> frequency confusingly use 37 for the divider field rather than 38 as you
> might expect.
> 
> For simplicity, let's just assume that this 38.4 MHz frequency will hold
> true for other future platforms with "fake" PCH south displays and that
> the CNP-style behavior will remain for other platforms with a real PCH.
> 
> Bspec: 49950
> Bspec: 49309

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> Cc: Aditya Swarup <
> aditya.swarup@intel.com
> >
> Cc: Clinton Taylor <
> Clinton.A.Taylor@intel.com
> >
> Cc: Lucas De Marchi <
> lucas.demarchi@intel.com
> >
> Signed-off-by: Matt Roper <
> matthew.d.roper@intel.com
> >
> Signed-off-by: Lucas De Marchi <
> lucas.demarchi@intel.com
> >
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 16 +++++++++++++++-
>  1 file changed, 15 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 9d6cacbdb691..7722831346ba 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2680,6 +2680,18 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv)
>  			       DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
>  }
>  
> +static int dg1_rawclk(struct drm_i915_private *dev_priv)
> +{
> +	/*
> +	 * DG1 always uses a 38.4 MHz rawclk.  The bspec tells us
> +	 * "Program Numerator=2, Denominator=4, Divider=37 decimal."
> +	 */
> +	I915_WRITE(PCH_RAWCLK_FREQ,
> +		   CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2));
> +
> +	return 38400;
> +}
> +
>  static int cnp_rawclk(struct drm_i915_private *dev_priv)
>  {
>  	u32 rawclk;
> @@ -2788,7 +2800,9 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
>  {
>  	u32 freq;
>  
> -	if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
> +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> +		freq = dg1_rawclk(dev_priv);
> +	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
>  		freq = cnp_rawclk(dev_priv);
>  	else if (HAS_PCH_SPLIT(dev_priv))
>  		freq = pch_rawclk(dev_priv);
> 
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