* [PATCH 2/4] drm/amd/powerplay: enable swSMU mgpu fan boost support
2020-08-12 4:56 [PATCH 1/4] drm/amd/powerplay: optimize the interface for mgpu fan boost enablement Evan Quan
@ 2020-08-12 4:56 ` Evan Quan
2020-08-12 4:56 ` [PATCH 3/4] drm/amd/powerplay: enable Navi1X mgpu fan boost feature Evan Quan
2020-08-12 4:56 ` [PATCH 4/4] drm/amd/powerplay: enable Sienna Cichlid " Evan Quan
2 siblings, 0 replies; 6+ messages in thread
From: Evan Quan @ 2020-08-12 4:56 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, Evan Quan
Enable mgpu fan boost feature on swSMU routines.
Change-Id: I2a48af3ed8b63cc1e601c8d6981e4d6bb3a0b7b8
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 5 ++++-
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 17 +++++++++++++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
3 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
index 9d80cdaf83f1..d9ebb567c0df 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
@@ -1222,9 +1222,12 @@ int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev)
void *pp_handle = adev->powerplay.pp_handle;
const struct amd_pm_funcs *pp_funcs =
adev->powerplay.pp_funcs;
+ struct smu_context *smu = &adev->smu;
int ret = 0;
- if (pp_funcs && pp_funcs->enable_mgpu_fan_boost)
+ if (is_support_sw_smu(adev))
+ ret = smu_enable_mgpu_fan_boost(smu);
+ else if (pp_funcs && pp_funcs->enable_mgpu_fan_boost)
ret = pp_funcs->enable_mgpu_fan_boost(pp_handle);
return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index c70f94377644..6c596aeb0b2a 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -2632,3 +2632,20 @@ ssize_t smu_sys_get_gpu_metrics(struct smu_context *smu,
return size;
}
+
+int smu_enable_mgpu_fan_boost(struct smu_context *smu)
+{
+ int ret = 0;
+
+ if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
+ return -EOPNOTSUPP;
+
+ mutex_lock(&smu->mutex);
+
+ if (smu->ppt_funcs->enable_mgpu_fan_boost)
+ ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu);
+
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 8de39b31e7c2..c0098965f460 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -595,6 +595,7 @@ struct pptable_funcs {
size_t (*get_pp_feature_mask)(struct smu_context *smu, char *buf);
int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask);
ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table);
+ int (*enable_mgpu_fan_boost)(struct smu_context *smu);
};
typedef enum {
@@ -798,5 +799,7 @@ int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value);
ssize_t smu_sys_get_gpu_metrics(struct smu_context *smu, void **table);
+int smu_enable_mgpu_fan_boost(struct smu_context *smu);
+
#endif
#endif
--
2.28.0
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^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 3/4] drm/amd/powerplay: enable Navi1X mgpu fan boost feature
2020-08-12 4:56 [PATCH 1/4] drm/amd/powerplay: optimize the interface for mgpu fan boost enablement Evan Quan
2020-08-12 4:56 ` [PATCH 2/4] drm/amd/powerplay: enable swSMU mgpu fan boost support Evan Quan
@ 2020-08-12 4:56 ` Evan Quan
2020-08-12 6:09 ` Nirmoy
2020-08-12 13:42 ` Alex Deucher
2020-08-12 4:56 ` [PATCH 4/4] drm/amd/powerplay: enable Sienna Cichlid " Evan Quan
2 siblings, 2 replies; 6+ messages in thread
From: Evan Quan @ 2020-08-12 4:56 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, Evan Quan
Support Navi1X mgpu fan boost enablement.
Change-Id: Iafbf07c56462120d2db578b6af45dd7f985a4cc1
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
.../drm/amd/powerplay/inc/smu_v11_0_ppsmc.h | 4 +++-
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 21 +++++++++++++++++++
2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_ppsmc.h
index 406bfd187ce8..fa0174dc7e0e 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_ppsmc.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_ppsmc.h
@@ -123,7 +123,9 @@
#define PPSMC_MSG_DALDisableDummyPstateChange 0x49
#define PPSMC_MSG_DALEnableDummyPstateChange 0x4A
-#define PPSMC_Message_Count 0x4B
+#define PPSMC_MSG_SetMGpuFanBoostLimitRpm 0x4C
+
+#define PPSMC_Message_Count 0x4D
typedef uint32_t PPSMC_Result;
typedef uint32_t PPSMC_Msg;
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 61e2971be9f3..a86cd819b44b 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -138,6 +138,7 @@ static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALEnableDummyPstateChange, 0),
MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0),
MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0),
+ MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
};
static struct cmn2asic_mapping navi10_clk_map[SMU_CLK_COUNT] = {
@@ -2555,6 +2556,25 @@ static ssize_t navi10_get_gpu_metrics(struct smu_context *smu,
return sizeof(struct gpu_metrics_v1_0);
}
+static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
+{
+ struct amdgpu_device *adev = smu->adev;
+ uint32_t param = 0;
+
+ /* Navi12 does not support this */
+ if (adev->asic_type == CHIP_NAVI12)
+ return 0;
+
+ if (adev->pdev->device == 0x7312 &&
+ adev->external_rev_id == 0)
+ param = 0xD188;
+
+ return smu_cmn_send_smc_msg_with_param(smu,
+ SMU_MSG_SetMGpuFanBoostLimitRpm,
+ param,
+ NULL);
+}
+
static const struct pptable_funcs navi10_ppt_funcs = {
.get_allowed_feature_mask = navi10_get_allowed_feature_mask,
.set_default_dpm_table = navi10_set_default_dpm_table,
@@ -2636,6 +2656,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
.get_gpu_metrics = navi10_get_gpu_metrics,
+ .enable_mgpu_fan_boost = navi10_enable_mgpu_fan_boost,
};
void navi10_set_ppt_funcs(struct smu_context *smu)
--
2.28.0
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^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 3/4] drm/amd/powerplay: enable Navi1X mgpu fan boost feature
2020-08-12 4:56 ` [PATCH 3/4] drm/amd/powerplay: enable Navi1X mgpu fan boost feature Evan Quan
@ 2020-08-12 6:09 ` Nirmoy
2020-08-12 13:42 ` Alex Deucher
1 sibling, 0 replies; 6+ messages in thread
From: Nirmoy @ 2020-08-12 6:09 UTC (permalink / raw)
To: Evan Quan, amd-gfx; +Cc: alexander.deucher
On 8/12/20 6:56 AM, Evan Quan wrote:
> Support Navi1X mgpu fan boost enablement.
>
> Change-Id: Iafbf07c56462120d2db578b6af45dd7f985a4cc1
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
> .../drm/amd/powerplay/inc/smu_v11_0_ppsmc.h | 4 +++-
> drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 21 +++++++++++++++++++
> 2 files changed, 24 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_ppsmc.h
> index 406bfd187ce8..fa0174dc7e0e 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_ppsmc.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_ppsmc.h
> @@ -123,7 +123,9 @@
> #define PPSMC_MSG_DALDisableDummyPstateChange 0x49
> #define PPSMC_MSG_DALEnableDummyPstateChange 0x4A
>
> -#define PPSMC_Message_Count 0x4B
> +#define PPSMC_MSG_SetMGpuFanBoostLimitRpm 0x4C
> +
> +#define PPSMC_Message_Count 0x4D
>
> typedef uint32_t PPSMC_Result;
> typedef uint32_t PPSMC_Msg;
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index 61e2971be9f3..a86cd819b44b 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -138,6 +138,7 @@ static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
> MSG_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALEnableDummyPstateChange, 0),
> MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0),
> MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0),
> + MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
> };
>
> static struct cmn2asic_mapping navi10_clk_map[SMU_CLK_COUNT] = {
> @@ -2555,6 +2556,25 @@ static ssize_t navi10_get_gpu_metrics(struct smu_context *smu,
> return sizeof(struct gpu_metrics_v1_0);
> }
>
> +static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
> +{
> + struct amdgpu_device *adev = smu->adev;
> + uint32_t param = 0;
> +
> + /* Navi12 does not support this */
> + if (adev->asic_type == CHIP_NAVI12)
> + return 0;
> +
> + if (adev->pdev->device == 0x7312 &&
> + adev->external_rev_id == 0)
> + param = 0xD188;
Can you please add a comment explaining above condition?
Apart from that, the series is Acked-by: Nirmoy Das <nirmoy.das@amd.com>
> +
> + return smu_cmn_send_smc_msg_with_param(smu,
> + SMU_MSG_SetMGpuFanBoostLimitRpm,
> + param,
> + NULL);
> +}
> +
> static const struct pptable_funcs navi10_ppt_funcs = {
> .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
> .set_default_dpm_table = navi10_set_default_dpm_table,
> @@ -2636,6 +2656,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
> .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
> .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
> .get_gpu_metrics = navi10_get_gpu_metrics,
> + .enable_mgpu_fan_boost = navi10_enable_mgpu_fan_boost,
> };
>
> void navi10_set_ppt_funcs(struct smu_context *smu)
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^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH 3/4] drm/amd/powerplay: enable Navi1X mgpu fan boost feature
2020-08-12 4:56 ` [PATCH 3/4] drm/amd/powerplay: enable Navi1X mgpu fan boost feature Evan Quan
2020-08-12 6:09 ` Nirmoy
@ 2020-08-12 13:42 ` Alex Deucher
1 sibling, 0 replies; 6+ messages in thread
From: Alex Deucher @ 2020-08-12 13:42 UTC (permalink / raw)
To: Evan Quan; +Cc: Deucher, Alexander, amd-gfx list
On Wed, Aug 12, 2020 at 12:57 AM Evan Quan <evan.quan@amd.com> wrote:
>
> Support Navi1X mgpu fan boost enablement.
>
> Change-Id: Iafbf07c56462120d2db578b6af45dd7f985a4cc1
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
> .../drm/amd/powerplay/inc/smu_v11_0_ppsmc.h | 4 +++-
> drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 21 +++++++++++++++++++
> 2 files changed, 24 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_ppsmc.h
> index 406bfd187ce8..fa0174dc7e0e 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_ppsmc.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_ppsmc.h
> @@ -123,7 +123,9 @@
> #define PPSMC_MSG_DALDisableDummyPstateChange 0x49
> #define PPSMC_MSG_DALEnableDummyPstateChange 0x4A
>
> -#define PPSMC_Message_Count 0x4B
> +#define PPSMC_MSG_SetMGpuFanBoostLimitRpm 0x4C
> +
> +#define PPSMC_Message_Count 0x4D
>
> typedef uint32_t PPSMC_Result;
> typedef uint32_t PPSMC_Msg;
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index 61e2971be9f3..a86cd819b44b 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -138,6 +138,7 @@ static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
> MSG_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALEnableDummyPstateChange, 0),
> MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0),
> MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0),
> + MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
> };
>
> static struct cmn2asic_mapping navi10_clk_map[SMU_CLK_COUNT] = {
> @@ -2555,6 +2556,25 @@ static ssize_t navi10_get_gpu_metrics(struct smu_context *smu,
> return sizeof(struct gpu_metrics_v1_0);
> }
>
> +static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
> +{
> + struct amdgpu_device *adev = smu->adev;
> + uint32_t param = 0;
> +
> + /* Navi12 does not support this */
> + if (adev->asic_type == CHIP_NAVI12)
> + return 0;
> +
> + if (adev->pdev->device == 0x7312 &&
> + adev->external_rev_id == 0)
You want adev->pdev->revision here. With that fixed, series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> + param = 0xD188;
> +
> + return smu_cmn_send_smc_msg_with_param(smu,
> + SMU_MSG_SetMGpuFanBoostLimitRpm,
> + param,
> + NULL);
> +}
> +
> static const struct pptable_funcs navi10_ppt_funcs = {
> .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
> .set_default_dpm_table = navi10_set_default_dpm_table,
> @@ -2636,6 +2656,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
> .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
> .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
> .get_gpu_metrics = navi10_get_gpu_metrics,
> + .enable_mgpu_fan_boost = navi10_enable_mgpu_fan_boost,
> };
>
> void navi10_set_ppt_funcs(struct smu_context *smu)
> --
> 2.28.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 4/4] drm/amd/powerplay: enable Sienna Cichlid mgpu fan boost feature
2020-08-12 4:56 [PATCH 1/4] drm/amd/powerplay: optimize the interface for mgpu fan boost enablement Evan Quan
2020-08-12 4:56 ` [PATCH 2/4] drm/amd/powerplay: enable swSMU mgpu fan boost support Evan Quan
2020-08-12 4:56 ` [PATCH 3/4] drm/amd/powerplay: enable Navi1X mgpu fan boost feature Evan Quan
@ 2020-08-12 4:56 ` Evan Quan
2 siblings, 0 replies; 6+ messages in thread
From: Evan Quan @ 2020-08-12 4:56 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, Evan Quan
Support Sienna Cichlid mgpu fan boost enablement.
Change-Id: Ibcaeeff7c0accb490402a1714d23adbe1bb7804e
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index f55dd0c2f3c8..907db635f959 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -124,6 +124,7 @@ static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT]
MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0),
MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
+ MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
};
static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
@@ -2707,6 +2708,14 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
return sizeof(struct gpu_metrics_v1_0);
}
+static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
+{
+ return smu_cmn_send_smc_msg_with_param(smu,
+ SMU_MSG_SetMGpuFanBoostLimitRpm,
+ 0,
+ NULL);
+}
+
static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
.get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
.set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
@@ -2784,6 +2793,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
.get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
+ .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
};
void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
--
2.28.0
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^ permalink raw reply related [flat|nested] 6+ messages in thread