From: Suman Anna <s-anna@ti.com> To: Nishanth Menon <nm@ti.com>, Tero Kristo <t-kristo@ti.com> Cc: <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, Suman Anna <s-anna@ti.com> Subject: [PATCH 6/7] arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C71x DSP Date: Wed, 19 Aug 2020 20:03:30 -0500 [thread overview] Message-ID: <20200820010331.2911-7-s-anna@ti.com> (raw) In-Reply-To: <20200820010331.2911-1-s-anna@ti.com> Two carveout reserved memory nodes have been added for the lone C71x DSP remote processor device present within the MAIN voltage domain for the TI J721E EVM boards. These nodes are assigned to the respective rproc device node as well. The first region will be used as the DMA pool for the rproc device, and the second region will furnish the static carveout regions for the firmware memory. The current carveout addresses and sizes are defined statically for each device. The C71x DSP processor does support a MMU called CMMU, but is not currently supported and as such requires the exact memory used by the firmware to be set-aside. The firmware images currently do not need any RSC_CARVEOUT entries either in their resource tables to allocate the memory for firmware memory segments. The reserved memory nodes can be disabled later on if there is no use-case defined to use the C71x DSP remoteproc processor. Signed-off-by: Suman Anna <s-anna@ti.com> --- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index f1a8190e3b5a..600586cc22e5 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -49,6 +49,18 @@ c66_1_memory_region: c66-memory@a7100000 { reg = <0x00 0xa7100000 0x00 0xf00000>; no-map; }; + + c71_0_dma_memory_region: c71-dma-memory@a8000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: c71-memory@a8100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8100000 0x00 0xf00000>; + no-map; + }; }; }; @@ -106,3 +118,8 @@ &c66_1 { memory-region = <&c66_1_dma_memory_region>, <&c66_1_memory_region>; }; + +&c71_0 { + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; -- 2.28.0
WARNING: multiple messages have this Message-ID (diff)
From: Suman Anna <s-anna@ti.com> To: Nishanth Menon <nm@ti.com>, Tero Kristo <t-kristo@ti.com> Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 6/7] arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C71x DSP Date: Wed, 19 Aug 2020 20:03:30 -0500 [thread overview] Message-ID: <20200820010331.2911-7-s-anna@ti.com> (raw) In-Reply-To: <20200820010331.2911-1-s-anna@ti.com> Two carveout reserved memory nodes have been added for the lone C71x DSP remote processor device present within the MAIN voltage domain for the TI J721E EVM boards. These nodes are assigned to the respective rproc device node as well. The first region will be used as the DMA pool for the rproc device, and the second region will furnish the static carveout regions for the firmware memory. The current carveout addresses and sizes are defined statically for each device. The C71x DSP processor does support a MMU called CMMU, but is not currently supported and as such requires the exact memory used by the firmware to be set-aside. The firmware images currently do not need any RSC_CARVEOUT entries either in their resource tables to allocate the memory for firmware memory segments. The reserved memory nodes can be disabled later on if there is no use-case defined to use the C71x DSP remoteproc processor. Signed-off-by: Suman Anna <s-anna@ti.com> --- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index f1a8190e3b5a..600586cc22e5 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -49,6 +49,18 @@ c66_1_memory_region: c66-memory@a7100000 { reg = <0x00 0xa7100000 0x00 0xf00000>; no-map; }; + + c71_0_dma_memory_region: c71-dma-memory@a8000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: c71-memory@a8100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8100000 0x00 0xf00000>; + no-map; + }; }; }; @@ -106,3 +118,8 @@ &c66_1 { memory-region = <&c66_1_dma_memory_region>, <&c66_1_memory_region>; }; + +&c71_0 { + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; -- 2.28.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-08-20 1:03 UTC|newest] Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-08-20 1:03 [PATCH 0/7] Add C66x & C71x DSP nodes on J721E SoCs Suman Anna 2020-08-20 1:03 ` Suman Anna 2020-08-20 1:03 ` [PATCH 1/7] arm64: dts: ti: k3-j721e-main: Add C66x DSP nodes Suman Anna 2020-08-20 1:03 ` Suman Anna 2020-08-20 1:03 ` [PATCH 2/7] arm64: dts: ti: k3-j721e-common-proc-board: Add mailboxes to C66x DSPs Suman Anna 2020-08-20 1:03 ` Suman Anna 2020-08-20 11:42 ` Nishanth Menon 2020-08-20 11:42 ` Nishanth Menon 2020-08-20 13:25 ` Suman Anna 2020-08-20 13:25 ` Suman Anna 2020-08-20 19:03 ` Nishanth Menon 2020-08-20 19:03 ` Nishanth Menon 2020-08-24 22:00 ` Suman Anna 2020-08-24 22:00 ` Suman Anna 2020-08-25 10:42 ` Nishanth Menon 2020-08-25 10:42 ` Nishanth Menon 2020-08-25 17:25 ` Suman Anna 2020-08-25 17:25 ` Suman Anna 2020-08-20 1:03 ` [PATCH 3/7] arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C66 DSPs Suman Anna 2020-08-20 1:03 ` Suman Anna 2020-08-20 1:03 ` [PATCH 4/7] arm64: dts: ti: k3-j721e-main: Add C71x DSP node Suman Anna 2020-08-20 1:03 ` Suman Anna 2020-08-20 1:03 ` [PATCH 5/7] arm64: dts: ti: k3-j721e-common-proc-board: Add mailboxes to C71x DSP Suman Anna 2020-08-20 1:03 ` Suman Anna 2020-08-20 1:03 ` Suman Anna [this message] 2020-08-20 1:03 ` [PATCH 6/7] arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for " Suman Anna 2020-08-20 1:03 ` [PATCH 7/7] arm64: dts: ti: k3-j721e-som-p0: Reserve memory for IPC between RTOS cores Suman Anna 2020-08-20 1:03 ` Suman Anna
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