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From: Roger Pau Monne <roger.pau@citrix.com>
To: <xen-devel@lists.xenproject.org>
Cc: Roger Pau Monne <roger.pau@citrix.com>,
	Jan Beulich <jbeulich@suse.com>,
	Andrew Cooper <andrew.cooper3@citrix.com>, Wei Liu <wl@xen.org>
Subject: [PATCH v2 4/8] x86/svm: drop writes to BU_CFG on revF chips
Date: Thu, 20 Aug 2020 17:08:31 +0200	[thread overview]
Message-ID: <20200820150835.27440-5-roger.pau@citrix.com> (raw)
In-Reply-To: <20200820150835.27440-1-roger.pau@citrix.com>

We already have special casing to handle reads of this MSR for revF
chips, so do as the comment in svm_msr_read_intercept says and drop
writes. This is in preparation for changing the default MSR write
behavior, which will instead return #GP on not explicitly handled
writes.

Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
---
Changes since v1:
 - New in this version.
---
 xen/arch/x86/hvm/svm/svm.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c
index 2d0823e7e1..7586b77268 100644
--- a/xen/arch/x86/hvm/svm/svm.c
+++ b/xen/arch/x86/hvm/svm/svm.c
@@ -2125,6 +2125,12 @@ static int svm_msr_write_intercept(unsigned int msr, uint64_t msr_content)
         nsvm->ns_msr_hsavepa = msr_content;
         break;
 
+    case MSR_F10_BU_CFG:
+        /* See comment in svm_msr_read_intercept. */
+        if ( boot_cpu_data.x86 != 0xf )
+            goto gpf;
+        break;
+
     case MSR_AMD64_TSC_RATIO:
         if ( msr_content & TSC_RATIO_RSVD_BITS )
             goto gpf;
-- 
2.28.0



  parent reply	other threads:[~2020-08-20 15:09 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-20 15:08 [PATCH v2 0/8] x86: switch default MSR behavior Roger Pau Monne
2020-08-20 15:08 ` [PATCH v2 1/8] x86/vmx: handle writes to MISC_ENABLE MSR Roger Pau Monne
2020-08-20 15:08 ` [PATCH v2 2/8] x86/svm: silently drop writes to SYSCFG and related MSRs Roger Pau Monne
2020-08-27 15:03   ` Jan Beulich
2020-08-31 14:37     ` Roger Pau Monné
2020-08-31 14:45       ` Roger Pau Monné
2020-08-31 15:21         ` Jan Beulich
2020-08-31 15:20       ` Jan Beulich
2020-08-20 15:08 ` [PATCH v2 3/8] x86/msr: explicitly handle AMD DE_CFG Roger Pau Monne
2020-08-20 17:08   ` Andrew Cooper
2020-08-21 11:52     ` Roger Pau Monné
2020-08-21 14:03       ` Andrew Cooper
2020-08-21 14:09         ` Roger Pau Monné
2020-08-20 15:08 ` Roger Pau Monne [this message]
2020-08-27 15:42   ` [PATCH v2 4/8] x86/svm: drop writes to BU_CFG on revF chips Jan Beulich
2020-08-20 15:08 ` [PATCH v2 5/8] x86/pv: allow reading FEATURE_CONTROL MSR Roger Pau Monne
2020-08-27 15:53   ` Jan Beulich
2020-08-31 15:12     ` Roger Pau Monné
2020-08-31 15:25       ` Jan Beulich
2020-08-20 15:08 ` [PATCH v2 6/8] x86/pv: disallow access to unknown MSRs Roger Pau Monne
2020-08-28  8:45   ` Jan Beulich
2020-08-20 15:08 ` [PATCH v2 7/8] x86/hvm: Disallow " Roger Pau Monne
2020-08-28  8:51   ` Jan Beulich
2020-08-20 15:08 ` [PATCH v2 8/8] x86/msr: Drop compatibility #GP handling in guest_{rd, wr}msr() Roger Pau Monne
2020-08-28  8:55   ` [PATCH v2 8/8] x86/msr: Drop compatibility #GP handling in guest_{rd,wr}msr() Jan Beulich
2020-08-31 15:22     ` Roger Pau Monné

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