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From: Jan Beulich <jbeulich@suse.com>
To: Roger Pau Monne <roger.pau@citrix.com>
Cc: xen-devel@lists.xenproject.org,
	Andrew Cooper <andrew.cooper3@citrix.com>, Wei Liu <wl@xen.org>
Subject: Re: [PATCH v2 2/8] x86/svm: silently drop writes to SYSCFG and related MSRs
Date: Thu, 27 Aug 2020 17:03:50 +0200	[thread overview]
Message-ID: <52cde027-e7c2-3ca7-3d7e-7abfe19198da@suse.com> (raw)
In-Reply-To: <20200820150835.27440-3-roger.pau@citrix.com>

On 20.08.2020 17:08, Roger Pau Monne wrote:
> --- a/xen/arch/x86/hvm/svm/svm.c
> +++ b/xen/arch/x86/hvm/svm/svm.c
> @@ -1917,6 +1917,21 @@ static int svm_msr_read_intercept(unsigned int msr, uint64_t *msr_content)
>              goto gpf;
>          break;
>  
> +    case MSR_K8_TOP_MEM1:
> +    case MSR_K8_TOP_MEM2:
> +        *msr_content = 0;
> +        break;

Any reason you don't fold this with ...

> +    case MSR_K8_SYSCFG:
> +        /*
> +         * Return MtrrFixDramEn: albeit the current emulated MTRR
> +         * implementation doesn't support the Extended Type-Field Format having
> +         * such bit set is common on AMD hardware and is harmless as long as
> +         * MtrrFixDramModEn isn't set.
> +         */
> +        *msr_content = K8_MTRRFIXRANGE_DRAM_ENABLE;
> +        break;
> +
>      case MSR_K8_VM_CR:
>          *msr_content = 0;
>          break;

... this existing case, and ...

> @@ -2094,6 +2109,12 @@ static int svm_msr_write_intercept(unsigned int msr, uint64_t msr_content)
>              goto gpf;
>          break;
>  
> +    case MSR_K8_TOP_MEM1:
> +    case MSR_K8_TOP_MEM2:
> +    case MSR_K8_SYSCFG:
> +        /* Drop writes. */
> +        break;
> +
>      case MSR_K8_VM_CR:
>          /* ignore write. handle all bits as read-only. */
>          break;

... similarly these?

Jan


  reply	other threads:[~2020-08-27 15:04 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-20 15:08 [PATCH v2 0/8] x86: switch default MSR behavior Roger Pau Monne
2020-08-20 15:08 ` [PATCH v2 1/8] x86/vmx: handle writes to MISC_ENABLE MSR Roger Pau Monne
2020-08-20 15:08 ` [PATCH v2 2/8] x86/svm: silently drop writes to SYSCFG and related MSRs Roger Pau Monne
2020-08-27 15:03   ` Jan Beulich [this message]
2020-08-31 14:37     ` Roger Pau Monné
2020-08-31 14:45       ` Roger Pau Monné
2020-08-31 15:21         ` Jan Beulich
2020-08-31 15:20       ` Jan Beulich
2020-08-20 15:08 ` [PATCH v2 3/8] x86/msr: explicitly handle AMD DE_CFG Roger Pau Monne
2020-08-20 17:08   ` Andrew Cooper
2020-08-21 11:52     ` Roger Pau Monné
2020-08-21 14:03       ` Andrew Cooper
2020-08-21 14:09         ` Roger Pau Monné
2020-08-20 15:08 ` [PATCH v2 4/8] x86/svm: drop writes to BU_CFG on revF chips Roger Pau Monne
2020-08-27 15:42   ` Jan Beulich
2020-08-20 15:08 ` [PATCH v2 5/8] x86/pv: allow reading FEATURE_CONTROL MSR Roger Pau Monne
2020-08-27 15:53   ` Jan Beulich
2020-08-31 15:12     ` Roger Pau Monné
2020-08-31 15:25       ` Jan Beulich
2020-08-20 15:08 ` [PATCH v2 6/8] x86/pv: disallow access to unknown MSRs Roger Pau Monne
2020-08-28  8:45   ` Jan Beulich
2020-08-20 15:08 ` [PATCH v2 7/8] x86/hvm: Disallow " Roger Pau Monne
2020-08-28  8:51   ` Jan Beulich
2020-08-20 15:08 ` [PATCH v2 8/8] x86/msr: Drop compatibility #GP handling in guest_{rd, wr}msr() Roger Pau Monne
2020-08-28  8:55   ` [PATCH v2 8/8] x86/msr: Drop compatibility #GP handling in guest_{rd,wr}msr() Jan Beulich
2020-08-31 15:22     ` Roger Pau Monné

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