* [PATCH 0/3] add support for Hisilicon SD5203 SoC
@ 2020-09-03 12:27 ` Zhen Lei
0 siblings, 0 replies; 12+ messages in thread
From: Zhen Lei @ 2020-09-03 12:27 UTC (permalink / raw)
To: Wei Xu, Rob Herring, linux-arm-kernel, devicetree, linux-kernel
Cc: Kefeng Wang, Zhen Lei
Add SD5203 SoC config option and devicetree file, also enable its debug UART.
Kefeng Wang (3):
ARM: hisi: add support for SD5203 SoC
ARM: debug: add UART early console support for SD5203
ARM: dts: add SD5203 dts
arch/arm/Kconfig.debug | 11 ++++-
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/sd5203.dts | 90 ++++++++++++++++++++++++++++++++++++
arch/arm/mach-hisi/Kconfig | 16 ++++++-
4 files changed, 116 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/boot/dts/sd5203.dts
--
2.26.0.106.g9fadedd
_______________________________________________
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^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/3] ARM: hisi: add support for SD5203 SoC
2020-09-03 12:27 ` Zhen Lei
@ 2020-09-03 12:27 ` Zhen Lei
-1 siblings, 0 replies; 12+ messages in thread
From: Zhen Lei @ 2020-09-03 12:27 UTC (permalink / raw)
To: Wei Xu, Rob Herring, linux-arm-kernel, devicetree, linux-kernel
Cc: Zhen Lei, Kefeng Wang
From: Kefeng Wang <wangkefeng.wang@huawei.com>
Enable support for the Hisilicon SD5203 SoC. The core is ARM926EJ-S.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
arch/arm/mach-hisi/Kconfig | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig
index 3b010fe7c0e9..3fb831033697 100644
--- a/arch/arm/mach-hisi/Kconfig
+++ b/arch/arm/mach-hisi/Kconfig
@@ -1,9 +1,9 @@
# SPDX-License-Identifier: GPL-2.0-only
config ARCH_HISI
bool "Hisilicon SoC Support"
- depends on ARCH_MULTI_V7
+ depends on ARCH_MULTI_V7 || ARCH_MULTI_V5
select ARM_AMBA
- select ARM_GIC
+ select ARM_GIC if ARCH_MULTI_V7
select ARM_TIMER_SP804
select POWER_RESET
select POWER_RESET_HISI
@@ -15,6 +15,7 @@ menu "Hisilicon platform type"
config ARCH_HI3xxx
bool "Hisilicon Hi36xx family"
+ depends on ARCH_MULTI_V7
select CACHE_L2X0
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
@@ -25,6 +26,7 @@ config ARCH_HI3xxx
config ARCH_HIP01
bool "Hisilicon HIP01 family"
+ depends on ARCH_MULTI_V7
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select ARM_GLOBAL_TIMER
@@ -33,6 +35,7 @@ config ARCH_HIP01
config ARCH_HIP04
bool "Hisilicon HiP04 Cortex A15 family"
+ depends on ARCH_MULTI_V7
select ARM_ERRATA_798181 if SMP
select HAVE_ARM_ARCH_TIMER
select MCPM if SMP
@@ -43,6 +46,7 @@ config ARCH_HIP04
config ARCH_HIX5HD2
bool "Hisilicon X5HD2 family"
+ depends on ARCH_MULTI_V7
select CACHE_L2X0
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
@@ -50,6 +54,14 @@ config ARCH_HIX5HD2
select PINCTRL_SINGLE
help
Support for Hisilicon HIX5HD2 SoC family
+
+config ARCH_SD5203
+ bool "Hisilicon SD5203 family"
+ depends on ARCH_MULTI_V5
+ select HISILICON_SD5203_VIC
+ help
+ Support for Hisilicon SD5203 SoC family
+
endmenu
endif
--
2.26.0.106.g9fadedd
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 1/3] ARM: hisi: add support for SD5203 SoC
@ 2020-09-03 12:27 ` Zhen Lei
0 siblings, 0 replies; 12+ messages in thread
From: Zhen Lei @ 2020-09-03 12:27 UTC (permalink / raw)
To: Wei Xu, Rob Herring, linux-arm-kernel, devicetree, linux-kernel
Cc: Kefeng Wang, Zhen Lei
From: Kefeng Wang <wangkefeng.wang@huawei.com>
Enable support for the Hisilicon SD5203 SoC. The core is ARM926EJ-S.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
arch/arm/mach-hisi/Kconfig | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig
index 3b010fe7c0e9..3fb831033697 100644
--- a/arch/arm/mach-hisi/Kconfig
+++ b/arch/arm/mach-hisi/Kconfig
@@ -1,9 +1,9 @@
# SPDX-License-Identifier: GPL-2.0-only
config ARCH_HISI
bool "Hisilicon SoC Support"
- depends on ARCH_MULTI_V7
+ depends on ARCH_MULTI_V7 || ARCH_MULTI_V5
select ARM_AMBA
- select ARM_GIC
+ select ARM_GIC if ARCH_MULTI_V7
select ARM_TIMER_SP804
select POWER_RESET
select POWER_RESET_HISI
@@ -15,6 +15,7 @@ menu "Hisilicon platform type"
config ARCH_HI3xxx
bool "Hisilicon Hi36xx family"
+ depends on ARCH_MULTI_V7
select CACHE_L2X0
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
@@ -25,6 +26,7 @@ config ARCH_HI3xxx
config ARCH_HIP01
bool "Hisilicon HIP01 family"
+ depends on ARCH_MULTI_V7
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select ARM_GLOBAL_TIMER
@@ -33,6 +35,7 @@ config ARCH_HIP01
config ARCH_HIP04
bool "Hisilicon HiP04 Cortex A15 family"
+ depends on ARCH_MULTI_V7
select ARM_ERRATA_798181 if SMP
select HAVE_ARM_ARCH_TIMER
select MCPM if SMP
@@ -43,6 +46,7 @@ config ARCH_HIP04
config ARCH_HIX5HD2
bool "Hisilicon X5HD2 family"
+ depends on ARCH_MULTI_V7
select CACHE_L2X0
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
@@ -50,6 +54,14 @@ config ARCH_HIX5HD2
select PINCTRL_SINGLE
help
Support for Hisilicon HIX5HD2 SoC family
+
+config ARCH_SD5203
+ bool "Hisilicon SD5203 family"
+ depends on ARCH_MULTI_V5
+ select HISILICON_SD5203_VIC
+ help
+ Support for Hisilicon SD5203 SoC family
+
endmenu
endif
--
2.26.0.106.g9fadedd
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/3] ARM: debug: add UART early console support for SD5203
2020-09-03 12:27 ` Zhen Lei
@ 2020-09-03 12:27 ` Zhen Lei
-1 siblings, 0 replies; 12+ messages in thread
From: Zhen Lei @ 2020-09-03 12:27 UTC (permalink / raw)
To: Wei Xu, Rob Herring, linux-arm-kernel, devicetree, linux-kernel
Cc: Zhen Lei, Kefeng Wang
From: Kefeng Wang <wangkefeng.wang@huawei.com>
Add support of early console for SD5203.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
arch/arm/Kconfig.debug | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 80000a66a4e3..d27a7764c3bf 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -1086,6 +1086,14 @@ choice
on SA-11x0 UART ports. The kernel will check for the first
enabled UART in a sequence 3-1-2.
+ config DEBUG_SD5203_UART
+ bool "Hisilicon SD5203 Debug UART"
+ depends on ARCH_SD5203
+ select DEBUG_UART_8250
+ help
+ Say Y here if you want kernel low-level debugging support
+ on SD5203 UART.
+
config DEBUG_SOCFPGA_UART0
depends on ARCH_SOCFPGA
bool "Use SOCFPGA UART0 for low-level debug"
@@ -1639,6 +1647,7 @@ config DEBUG_UART_PHYS
default 0x11006000 if DEBUG_MT6589_UART0
default 0x11009000 if DEBUG_MT8135_UART3
default 0x16000000 if DEBUG_INTEGRATOR
+ default 0x1600d000 if DEBUG_SD5203_UART
default 0x18000300 if DEBUG_BCM_5301X
default 0x18000400 if DEBUG_BCM_HR2
default 0x18010000 if DEBUG_SIRFATLAS7_UART0
@@ -1841,7 +1850,7 @@ config DEBUG_UART_VIRT
default 0xfec60000 if DEBUG_SIRFPRIMA2_UART1
default 0xfec90000 if DEBUG_RK32_UART2
default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1
- default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2
+ default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_SD5203_UART
default 0xfed60000 if DEBUG_RK29_UART0
default 0xfed64000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2
default 0xfed68000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3
--
2.26.0.106.g9fadedd
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/3] ARM: debug: add UART early console support for SD5203
@ 2020-09-03 12:27 ` Zhen Lei
0 siblings, 0 replies; 12+ messages in thread
From: Zhen Lei @ 2020-09-03 12:27 UTC (permalink / raw)
To: Wei Xu, Rob Herring, linux-arm-kernel, devicetree, linux-kernel
Cc: Kefeng Wang, Zhen Lei
From: Kefeng Wang <wangkefeng.wang@huawei.com>
Add support of early console for SD5203.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
arch/arm/Kconfig.debug | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 80000a66a4e3..d27a7764c3bf 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -1086,6 +1086,14 @@ choice
on SA-11x0 UART ports. The kernel will check for the first
enabled UART in a sequence 3-1-2.
+ config DEBUG_SD5203_UART
+ bool "Hisilicon SD5203 Debug UART"
+ depends on ARCH_SD5203
+ select DEBUG_UART_8250
+ help
+ Say Y here if you want kernel low-level debugging support
+ on SD5203 UART.
+
config DEBUG_SOCFPGA_UART0
depends on ARCH_SOCFPGA
bool "Use SOCFPGA UART0 for low-level debug"
@@ -1639,6 +1647,7 @@ config DEBUG_UART_PHYS
default 0x11006000 if DEBUG_MT6589_UART0
default 0x11009000 if DEBUG_MT8135_UART3
default 0x16000000 if DEBUG_INTEGRATOR
+ default 0x1600d000 if DEBUG_SD5203_UART
default 0x18000300 if DEBUG_BCM_5301X
default 0x18000400 if DEBUG_BCM_HR2
default 0x18010000 if DEBUG_SIRFATLAS7_UART0
@@ -1841,7 +1850,7 @@ config DEBUG_UART_VIRT
default 0xfec60000 if DEBUG_SIRFPRIMA2_UART1
default 0xfec90000 if DEBUG_RK32_UART2
default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1
- default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2
+ default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_SD5203_UART
default 0xfed60000 if DEBUG_RK29_UART0
default 0xfed64000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2
default 0xfed68000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3
--
2.26.0.106.g9fadedd
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/3] ARM: dts: add SD5203 dts
2020-09-03 12:27 ` Zhen Lei
@ 2020-09-03 12:27 ` Zhen Lei
-1 siblings, 0 replies; 12+ messages in thread
From: Zhen Lei @ 2020-09-03 12:27 UTC (permalink / raw)
To: Wei Xu, Rob Herring, linux-arm-kernel, devicetree, linux-kernel
Cc: Zhen Lei, Kefeng Wang
From: Kefeng Wang <wangkefeng.wang@huawei.com>
Add sd5203.dts for Hisilicon SD5203 SoC platform.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/sd5203.dts | 90 ++++++++++++++++++++++++++++++++++++
2 files changed, 92 insertions(+)
create mode 100644 arch/arm/boot/dts/sd5203.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4572db3fa5ae..1d1262df5c55 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -357,6 +357,8 @@ dtb-$(CONFIG_ARCH_MPS2) += \
mps2-an399.dtb
dtb-$(CONFIG_ARCH_MOXART) += \
moxart-uc7112lx.dtb
+dtb-$(CONFIG_ARCH_SD5203) += \
+ sd5203.dtb
dtb-$(CONFIG_SOC_IMX1) += \
imx1-ads.dtb \
imx1-apf9328.dtb
diff --git a/arch/arm/boot/dts/sd5203.dts b/arch/arm/boot/dts/sd5203.dts
new file mode 100644
index 000000000000..99da46072f72
--- /dev/null
+++ b/arch/arm/boot/dts/sd5203.dts
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020 Hisilicon Limited.
+ *
+ * DTS file for Hisilicon SD5203 Board
+ */
+
+/dts-v1/;
+
+/ {
+ model = "Hisilicon SD5203";
+ compatible = "hisilicon,sd5203";
+ interrupt-parent = <&vic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chosen {
+ bootargs="console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000";
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
+ };
+
+ memory@30000000 {
+ device_type = "memory";
+ reg = <0x30000000 0x8000000>;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges;
+
+ vic: interrupt-controller@10130000 {
+ compatible = "hisilicon,sd5203-vic";
+ reg = <0x10130000 0x1000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ refclk125mhz: refclk125mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ timer0: timer@16002000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x16002000 0x1000>;
+ interrupts = <4>;
+ clocks = <&refclk125mhz>;
+ clock-names = "apb_pclk";
+ };
+
+ timer1: timer@16003000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x16003000 0x1000>;
+ interrupts = <5>;
+ clocks = <&refclk125mhz>;
+ clock-names = "apb_pclk";
+ };
+
+ uart0: serial@1600D000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x1600D000 0x1000>;
+ bus_id = "uart0";
+ clocks = <&refclk125mhz>;
+ clock-names = "apb_pclk";
+ reg-shift = <2>;
+ interrupts = <17>;
+ };
+
+ uart1: serial@1600C000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x1600C000 0x1000>;
+ clocks = <&refclk125mhz>;
+ clock-names = "apb_pclk";
+ reg-shift = <2>;
+ interrupts = <16>;
+ status = "disabled";
+ };
+ };
+};
--
2.26.0.106.g9fadedd
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 3/3] ARM: dts: add SD5203 dts
@ 2020-09-03 12:27 ` Zhen Lei
0 siblings, 0 replies; 12+ messages in thread
From: Zhen Lei @ 2020-09-03 12:27 UTC (permalink / raw)
To: Wei Xu, Rob Herring, linux-arm-kernel, devicetree, linux-kernel
Cc: Kefeng Wang, Zhen Lei
From: Kefeng Wang <wangkefeng.wang@huawei.com>
Add sd5203.dts for Hisilicon SD5203 SoC platform.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/sd5203.dts | 90 ++++++++++++++++++++++++++++++++++++
2 files changed, 92 insertions(+)
create mode 100644 arch/arm/boot/dts/sd5203.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4572db3fa5ae..1d1262df5c55 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -357,6 +357,8 @@ dtb-$(CONFIG_ARCH_MPS2) += \
mps2-an399.dtb
dtb-$(CONFIG_ARCH_MOXART) += \
moxart-uc7112lx.dtb
+dtb-$(CONFIG_ARCH_SD5203) += \
+ sd5203.dtb
dtb-$(CONFIG_SOC_IMX1) += \
imx1-ads.dtb \
imx1-apf9328.dtb
diff --git a/arch/arm/boot/dts/sd5203.dts b/arch/arm/boot/dts/sd5203.dts
new file mode 100644
index 000000000000..99da46072f72
--- /dev/null
+++ b/arch/arm/boot/dts/sd5203.dts
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020 Hisilicon Limited.
+ *
+ * DTS file for Hisilicon SD5203 Board
+ */
+
+/dts-v1/;
+
+/ {
+ model = "Hisilicon SD5203";
+ compatible = "hisilicon,sd5203";
+ interrupt-parent = <&vic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chosen {
+ bootargs="console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000";
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
+ };
+
+ memory@30000000 {
+ device_type = "memory";
+ reg = <0x30000000 0x8000000>;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges;
+
+ vic: interrupt-controller@10130000 {
+ compatible = "hisilicon,sd5203-vic";
+ reg = <0x10130000 0x1000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ refclk125mhz: refclk125mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ timer0: timer@16002000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x16002000 0x1000>;
+ interrupts = <4>;
+ clocks = <&refclk125mhz>;
+ clock-names = "apb_pclk";
+ };
+
+ timer1: timer@16003000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x16003000 0x1000>;
+ interrupts = <5>;
+ clocks = <&refclk125mhz>;
+ clock-names = "apb_pclk";
+ };
+
+ uart0: serial@1600D000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x1600D000 0x1000>;
+ bus_id = "uart0";
+ clocks = <&refclk125mhz>;
+ clock-names = "apb_pclk";
+ reg-shift = <2>;
+ interrupts = <17>;
+ };
+
+ uart1: serial@1600C000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x1600C000 0x1000>;
+ clocks = <&refclk125mhz>;
+ clock-names = "apb_pclk";
+ reg-shift = <2>;
+ interrupts = <16>;
+ status = "disabled";
+ };
+ };
+};
--
2.26.0.106.g9fadedd
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH 3/3] ARM: dts: add SD5203 dts
2020-09-03 12:27 ` Zhen Lei
@ 2020-09-14 9:29 ` Wei Xu
-1 siblings, 0 replies; 12+ messages in thread
From: Wei Xu @ 2020-09-14 9:29 UTC (permalink / raw)
To: Zhen Lei, Rob Herring, linux-arm-kernel, devicetree, linux-kernel
Cc: Kefeng Wang
Hi Zhen,
On 2020/9/3 20:27, Zhen Lei wrote:
> From: Kefeng Wang <wangkefeng.wang@huawei.com>
>
> Add sd5203.dts for Hisilicon SD5203 SoC platform.
>
> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
> ---
> arch/arm/boot/dts/Makefile | 2 +
> arch/arm/boot/dts/sd5203.dts | 90 ++++++++++++++++++++++++++++++++++++
> 2 files changed, 92 insertions(+)
> create mode 100644 arch/arm/boot/dts/sd5203.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 4572db3fa5ae..1d1262df5c55 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -357,6 +357,8 @@ dtb-$(CONFIG_ARCH_MPS2) += \
> mps2-an399.dtb
> dtb-$(CONFIG_ARCH_MOXART) += \
> moxart-uc7112lx.dtb
> +dtb-$(CONFIG_ARCH_SD5203) += \
> + sd5203.dtb
> dtb-$(CONFIG_SOC_IMX1) += \
> imx1-ads.dtb \
> imx1-apf9328.dtb
> diff --git a/arch/arm/boot/dts/sd5203.dts b/arch/arm/boot/dts/sd5203.dts
> new file mode 100644
> index 000000000000..99da46072f72
> --- /dev/null
> +++ b/arch/arm/boot/dts/sd5203.dts
> @@ -0,0 +1,90 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2020 Hisilicon Limited.
> + *
> + * DTS file for Hisilicon SD5203 Board
> + */
> +
> +/dts-v1/;
> +
> +/ {
> + model = "Hisilicon SD5203";
> + compatible = "hisilicon,sd5203";
Can you please add the binding document as well?
> + interrupt-parent = <&vic>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + chosen {
> + bootargs="console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000";
> + };
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + cpu {
> + compatible = "arm,arm926ej-s";
> + device_type = "cpu";
> + };
> +
> + memory@30000000 {
> + device_type = "memory";
> + reg = <0x30000000 0x8000000>;
> + };
> +
> + soc {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "simple-bus";
> + ranges;
> +
> + vic: interrupt-controller@10130000 {
> + compatible = "hisilicon,sd5203-vic";
Ditto.
Thanks!
Best Regards,
Wei
> + reg = <0x10130000 0x1000>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> +
> + refclk125mhz: refclk125mhz {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <125000000>;
> + };
> +
> + timer0: timer@16002000 {
> + compatible = "arm,sp804", "arm,primecell";
> + reg = <0x16002000 0x1000>;
> + interrupts = <4>;
> + clocks = <&refclk125mhz>;
> + clock-names = "apb_pclk";
> + };
> +
> + timer1: timer@16003000 {
> + compatible = "arm,sp804", "arm,primecell";
> + reg = <0x16003000 0x1000>;
> + interrupts = <5>;
> + clocks = <&refclk125mhz>;
> + clock-names = "apb_pclk";
> + };
> +
> + uart0: serial@1600D000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x1600D000 0x1000>;
> + bus_id = "uart0";
> + clocks = <&refclk125mhz>;
> + clock-names = "apb_pclk";
> + reg-shift = <2>;
> + interrupts = <17>;
> + };
> +
> + uart1: serial@1600C000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x1600C000 0x1000>;
> + clocks = <&refclk125mhz>;
> + clock-names = "apb_pclk";
> + reg-shift = <2>;
> + interrupts = <16>;
> + status = "disabled";
> + };
> + };
> +};
>
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 3/3] ARM: dts: add SD5203 dts
@ 2020-09-14 9:29 ` Wei Xu
0 siblings, 0 replies; 12+ messages in thread
From: Wei Xu @ 2020-09-14 9:29 UTC (permalink / raw)
To: Zhen Lei, Rob Herring, linux-arm-kernel, devicetree, linux-kernel
Cc: Kefeng Wang
Hi Zhen,
On 2020/9/3 20:27, Zhen Lei wrote:
> From: Kefeng Wang <wangkefeng.wang@huawei.com>
>
> Add sd5203.dts for Hisilicon SD5203 SoC platform.
>
> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
> ---
> arch/arm/boot/dts/Makefile | 2 +
> arch/arm/boot/dts/sd5203.dts | 90 ++++++++++++++++++++++++++++++++++++
> 2 files changed, 92 insertions(+)
> create mode 100644 arch/arm/boot/dts/sd5203.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 4572db3fa5ae..1d1262df5c55 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -357,6 +357,8 @@ dtb-$(CONFIG_ARCH_MPS2) += \
> mps2-an399.dtb
> dtb-$(CONFIG_ARCH_MOXART) += \
> moxart-uc7112lx.dtb
> +dtb-$(CONFIG_ARCH_SD5203) += \
> + sd5203.dtb
> dtb-$(CONFIG_SOC_IMX1) += \
> imx1-ads.dtb \
> imx1-apf9328.dtb
> diff --git a/arch/arm/boot/dts/sd5203.dts b/arch/arm/boot/dts/sd5203.dts
> new file mode 100644
> index 000000000000..99da46072f72
> --- /dev/null
> +++ b/arch/arm/boot/dts/sd5203.dts
> @@ -0,0 +1,90 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2020 Hisilicon Limited.
> + *
> + * DTS file for Hisilicon SD5203 Board
> + */
> +
> +/dts-v1/;
> +
> +/ {
> + model = "Hisilicon SD5203";
> + compatible = "hisilicon,sd5203";
Can you please add the binding document as well?
> + interrupt-parent = <&vic>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + chosen {
> + bootargs="console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000";
> + };
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + cpu {
> + compatible = "arm,arm926ej-s";
> + device_type = "cpu";
> + };
> +
> + memory@30000000 {
> + device_type = "memory";
> + reg = <0x30000000 0x8000000>;
> + };
> +
> + soc {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "simple-bus";
> + ranges;
> +
> + vic: interrupt-controller@10130000 {
> + compatible = "hisilicon,sd5203-vic";
Ditto.
Thanks!
Best Regards,
Wei
> + reg = <0x10130000 0x1000>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> +
> + refclk125mhz: refclk125mhz {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <125000000>;
> + };
> +
> + timer0: timer@16002000 {
> + compatible = "arm,sp804", "arm,primecell";
> + reg = <0x16002000 0x1000>;
> + interrupts = <4>;
> + clocks = <&refclk125mhz>;
> + clock-names = "apb_pclk";
> + };
> +
> + timer1: timer@16003000 {
> + compatible = "arm,sp804", "arm,primecell";
> + reg = <0x16003000 0x1000>;
> + interrupts = <5>;
> + clocks = <&refclk125mhz>;
> + clock-names = "apb_pclk";
> + };
> +
> + uart0: serial@1600D000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x1600D000 0x1000>;
> + bus_id = "uart0";
> + clocks = <&refclk125mhz>;
> + clock-names = "apb_pclk";
> + reg-shift = <2>;
> + interrupts = <17>;
> + };
> +
> + uart1: serial@1600C000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x1600C000 0x1000>;
> + clocks = <&refclk125mhz>;
> + clock-names = "apb_pclk";
> + reg-shift = <2>;
> + interrupts = <16>;
> + status = "disabled";
> + };
> + };
> +};
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 3/3] ARM: dts: add SD5203 dts
2020-09-14 9:29 ` Wei Xu
@ 2020-09-14 9:55 ` Leizhen (ThunderTown)
-1 siblings, 0 replies; 12+ messages in thread
From: Leizhen (ThunderTown) @ 2020-09-14 9:55 UTC (permalink / raw)
To: Wei Xu, Rob Herring, linux-arm-kernel, devicetree, linux-kernel
Cc: Kefeng Wang
On 2020/9/14 17:29, Wei Xu wrote:
> Hi Zhen,
>
> On 2020/9/3 20:27, Zhen Lei wrote:
>> From: Kefeng Wang <wangkefeng.wang@huawei.com>
>>
>> Add sd5203.dts for Hisilicon SD5203 SoC platform.
>>
>> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
>> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
>> ---
>> arch/arm/boot/dts/Makefile | 2 +
>> arch/arm/boot/dts/sd5203.dts | 90 ++++++++++++++++++++++++++++++++++++
>> 2 files changed, 92 insertions(+)
>> create mode 100644 arch/arm/boot/dts/sd5203.dts
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index 4572db3fa5ae..1d1262df5c55 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -357,6 +357,8 @@ dtb-$(CONFIG_ARCH_MPS2) += \
>> mps2-an399.dtb
>> dtb-$(CONFIG_ARCH_MOXART) += \
>> moxart-uc7112lx.dtb
>> +dtb-$(CONFIG_ARCH_SD5203) += \
>> + sd5203.dtb
>> dtb-$(CONFIG_SOC_IMX1) += \
>> imx1-ads.dtb \
>> imx1-apf9328.dtb
>> diff --git a/arch/arm/boot/dts/sd5203.dts b/arch/arm/boot/dts/sd5203.dts
>> new file mode 100644
>> index 000000000000..99da46072f72
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sd5203.dts
>> @@ -0,0 +1,90 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) 2020 Hisilicon Limited.
>> + *
>> + * DTS file for Hisilicon SD5203 Board
>> + */
>> +
>> +/dts-v1/;
>> +
>> +/ {
>> + model = "Hisilicon SD5203";
>> + compatible = "hisilicon,sd5203";
>
> Can you please add the binding document as well?
OK, I will do it.
>
>> + interrupt-parent = <&vic>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + chosen {
>> + bootargs="console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000";
>> + };
>> +
>> + aliases {
>> + serial0 = &uart0;
>> + };
>> +
>> + cpu {
>> + compatible = "arm,arm926ej-s";
>> + device_type = "cpu";
>> + };
>> +
>> + memory@30000000 {
>> + device_type = "memory";
>> + reg = <0x30000000 0x8000000>;
>> + };
>> +
>> + soc {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + compatible = "simple-bus";
>> + ranges;
>> +
>> + vic: interrupt-controller@10130000 {
>> + compatible = "hisilicon,sd5203-vic";
As Marc Zyngier's suggestion, I discarded adding an independent SD5203-VIC
driver, but make the dw-apb-ictl irqchip driver to support hierarchy irq domain.
I will send V4 of this irqchip driver today.
Here is the link of V3:
https://lkml.org/lkml/2020/9/9/94
>
> Ditto.
> Thanks!
>
> Best Regards,
> Wei
>
>> + reg = <0x10130000 0x1000>;
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> +
>> + refclk125mhz: refclk125mhz {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <125000000>;
>> + };
>> +
>> + timer0: timer@16002000 {
>> + compatible = "arm,sp804", "arm,primecell";
>> + reg = <0x16002000 0x1000>;
>> + interrupts = <4>;
>> + clocks = <&refclk125mhz>;
>> + clock-names = "apb_pclk";
>> + };
>> +
>> + timer1: timer@16003000 {
>> + compatible = "arm,sp804", "arm,primecell";
>> + reg = <0x16003000 0x1000>;
>> + interrupts = <5>;
>> + clocks = <&refclk125mhz>;
>> + clock-names = "apb_pclk";
>> + };
>> +
>> + uart0: serial@1600D000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x1600D000 0x1000>;
>> + bus_id = "uart0";
>> + clocks = <&refclk125mhz>;
>> + clock-names = "apb_pclk";
>> + reg-shift = <2>;
>> + interrupts = <17>;
>> + };
>> +
>> + uart1: serial@1600C000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x1600C000 0x1000>;
>> + clocks = <&refclk125mhz>;
>> + clock-names = "apb_pclk";
>> + reg-shift = <2>;
>> + interrupts = <16>;
>> + status = "disabled";
>> + };
>> + };
>> +};
>>
>
> .
>
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 3/3] ARM: dts: add SD5203 dts
@ 2020-09-14 9:55 ` Leizhen (ThunderTown)
0 siblings, 0 replies; 12+ messages in thread
From: Leizhen (ThunderTown) @ 2020-09-14 9:55 UTC (permalink / raw)
To: Wei Xu, Rob Herring, linux-arm-kernel, devicetree, linux-kernel
Cc: Kefeng Wang
On 2020/9/14 17:29, Wei Xu wrote:
> Hi Zhen,
>
> On 2020/9/3 20:27, Zhen Lei wrote:
>> From: Kefeng Wang <wangkefeng.wang@huawei.com>
>>
>> Add sd5203.dts for Hisilicon SD5203 SoC platform.
>>
>> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
>> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
>> ---
>> arch/arm/boot/dts/Makefile | 2 +
>> arch/arm/boot/dts/sd5203.dts | 90 ++++++++++++++++++++++++++++++++++++
>> 2 files changed, 92 insertions(+)
>> create mode 100644 arch/arm/boot/dts/sd5203.dts
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index 4572db3fa5ae..1d1262df5c55 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -357,6 +357,8 @@ dtb-$(CONFIG_ARCH_MPS2) += \
>> mps2-an399.dtb
>> dtb-$(CONFIG_ARCH_MOXART) += \
>> moxart-uc7112lx.dtb
>> +dtb-$(CONFIG_ARCH_SD5203) += \
>> + sd5203.dtb
>> dtb-$(CONFIG_SOC_IMX1) += \
>> imx1-ads.dtb \
>> imx1-apf9328.dtb
>> diff --git a/arch/arm/boot/dts/sd5203.dts b/arch/arm/boot/dts/sd5203.dts
>> new file mode 100644
>> index 000000000000..99da46072f72
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sd5203.dts
>> @@ -0,0 +1,90 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) 2020 Hisilicon Limited.
>> + *
>> + * DTS file for Hisilicon SD5203 Board
>> + */
>> +
>> +/dts-v1/;
>> +
>> +/ {
>> + model = "Hisilicon SD5203";
>> + compatible = "hisilicon,sd5203";
>
> Can you please add the binding document as well?
OK, I will do it.
>
>> + interrupt-parent = <&vic>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + chosen {
>> + bootargs="console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000";
>> + };
>> +
>> + aliases {
>> + serial0 = &uart0;
>> + };
>> +
>> + cpu {
>> + compatible = "arm,arm926ej-s";
>> + device_type = "cpu";
>> + };
>> +
>> + memory@30000000 {
>> + device_type = "memory";
>> + reg = <0x30000000 0x8000000>;
>> + };
>> +
>> + soc {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + compatible = "simple-bus";
>> + ranges;
>> +
>> + vic: interrupt-controller@10130000 {
>> + compatible = "hisilicon,sd5203-vic";
As Marc Zyngier's suggestion, I discarded adding an independent SD5203-VIC
driver, but make the dw-apb-ictl irqchip driver to support hierarchy irq domain.
I will send V4 of this irqchip driver today.
Here is the link of V3:
https://lkml.org/lkml/2020/9/9/94
>
> Ditto.
> Thanks!
>
> Best Regards,
> Wei
>
>> + reg = <0x10130000 0x1000>;
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> +
>> + refclk125mhz: refclk125mhz {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <125000000>;
>> + };
>> +
>> + timer0: timer@16002000 {
>> + compatible = "arm,sp804", "arm,primecell";
>> + reg = <0x16002000 0x1000>;
>> + interrupts = <4>;
>> + clocks = <&refclk125mhz>;
>> + clock-names = "apb_pclk";
>> + };
>> +
>> + timer1: timer@16003000 {
>> + compatible = "arm,sp804", "arm,primecell";
>> + reg = <0x16003000 0x1000>;
>> + interrupts = <5>;
>> + clocks = <&refclk125mhz>;
>> + clock-names = "apb_pclk";
>> + };
>> +
>> + uart0: serial@1600D000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x1600D000 0x1000>;
>> + bus_id = "uart0";
>> + clocks = <&refclk125mhz>;
>> + clock-names = "apb_pclk";
>> + reg-shift = <2>;
>> + interrupts = <17>;
>> + };
>> +
>> + uart1: serial@1600C000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x1600C000 0x1000>;
>> + clocks = <&refclk125mhz>;
>> + clock-names = "apb_pclk";
>> + reg-shift = <2>;
>> + interrupts = <16>;
>> + status = "disabled";
>> + };
>> + };
>> +};
>>
>
> .
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 12+ messages in thread