From: kernel test robot <lkp@intel.com>
To: kbuild-all@lists.01.org
Subject: Re: [RFC PATCH v7 09/21] riscv: Add task switch support for vector
Date: Thu, 10 Sep 2020 23:48:16 +0800 [thread overview]
Message-ID: <202009102351.tGfyBoII%lkp@intel.com> (raw)
In-Reply-To: <0cade5900d72628cbf6a4a021858f000924d560b.1599719352.git.greentime.hu@sifive.com>
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Hi Greentime,
[FYI, it's a private test report for your RFC patch.]
[auto build test ERROR on linus/master]
[also build test ERROR on v5.9-rc4 next-20200910]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Greentime-Hu/riscv-Add-vector-ISA-support/20200910-163426
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 7fe10096c1508c7f033d34d0741809f8eecc1ed4
config: riscv-allmodconfig (attached as .config)
compiler: riscv64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=riscv
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All error/warnings (new ones prefixed by >>):
arch/riscv/kernel/process.c:42:6: warning: no previous prototype for 'show_regs' [-Wmissing-prototypes]
42 | void show_regs(struct pt_regs *regs)
| ^~~~~~~~~
arch/riscv/kernel/process.c:118:5: warning: no previous prototype for 'arch_dup_task_struct' [-Wmissing-prototypes]
118 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
| ^~~~~~~~~~~~~~~~~~~~
>> arch/riscv/kernel/process.c:143:6: warning: no previous prototype for 'arch_release_task_struct' [-Wmissing-prototypes]
143 | void arch_release_task_struct(struct task_struct *tsk)
| ^~~~~~~~~~~~~~~~~~~~~~~~
--
arch/riscv/kernel/vector.S: Assembler messages:
arch/riscv/kernel/vector.S:42: Error: unrecognized opcode `vsetvli t4,t5,e8,m8'
>> arch/riscv/kernel/vector.S:43: Error: unrecognized opcode `vse8.v v0,(a1)'
>> arch/riscv/kernel/vector.S:45: Error: unrecognized opcode `vse8.v v8,(a1)'
>> arch/riscv/kernel/vector.S:47: Error: unrecognized opcode `vse8.v v16,(a1)'
>> arch/riscv/kernel/vector.S:49: Error: unrecognized opcode `vse8.v v24,(a1)'
arch/riscv/kernel/vector.S:65: Error: unrecognized opcode `vsetvli t4,t5,e8,m8'
>> arch/riscv/kernel/vector.S:66: Error: unrecognized opcode `vle8.v v0,(a1)'
>> arch/riscv/kernel/vector.S:68: Error: unrecognized opcode `vle8.v v8,(a1)'
>> arch/riscv/kernel/vector.S:70: Error: unrecognized opcode `vle8.v v16,(a1)'
>> arch/riscv/kernel/vector.S:72: Error: unrecognized opcode `vle8.v v24,(a1)'
>> arch/riscv/kernel/vector.S:78: Error: unrecognized opcode `vsetvl x0,t2,t1'
# https://github.com/0day-ci/linux/commit/606b544e14a96142b4f5ede48937fc5643b12725
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Greentime-Hu/riscv-Add-vector-ISA-support/20200910-163426
git checkout 606b544e14a96142b4f5ede48937fc5643b12725
vim +43 arch/riscv/kernel/vector.S
32
33 ENTRY(__vstate_save)
34 li status, SR_VS
35 csrs sstatus, status
36
37 csrr x_vstart, CSR_VSTART
38 csrr x_vtype, CSR_VTYPE
39 csrr x_vl, CSR_VL
40 csrr x_vcsr, CSR_VCSR
41 li m_one, -1
42 vsetvli incr, m_one, e8, m8
> 43 vse8.v v0, (datap)
44 add datap, datap, incr
> 45 vse8.v v8, (datap)
46 add datap, datap, incr
> 47 vse8.v v16, (datap)
48 add datap, datap, incr
> 49 vse8.v v24, (datap)
50
51 REG_S x_vstart, RISCV_V_STATE_VSTART(vstatep)
52 REG_S x_vtype, RISCV_V_STATE_VTYPE(vstatep)
53 REG_S x_vl, RISCV_V_STATE_VL(vstatep)
54 REG_S x_vcsr, RISCV_V_STATE_VCSR(vstatep)
55
56 csrc sstatus, status
57 ret
58 ENDPROC(__vstate_save)
59
60 ENTRY(__vstate_restore)
61 li status, SR_VS
62 csrs sstatus, status
63
64 li m_one, -1
65 vsetvli incr, m_one, e8, m8
> 66 vle8.v v0, (datap)
67 add datap, datap, incr
> 68 vle8.v v8, (datap)
69 add datap, datap, incr
> 70 vle8.v v16, (datap)
71 add datap, datap, incr
> 72 vle8.v v24, (datap)
73
74 REG_L x_vstart, RISCV_V_STATE_VSTART(vstatep)
75 REG_L x_vtype, RISCV_V_STATE_VTYPE(vstatep)
76 REG_L x_vl, RISCV_V_STATE_VL(vstatep)
77 REG_L x_vcsr, RISCV_V_STATE_VCSR(vstatep)
> 78 vsetvl x0, x_vl, x_vtype
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
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next prev parent reply other threads:[~2020-09-10 15:48 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-10 8:11 [RFC PATCH v7 00/21] riscv: Add vector ISA support Greentime Hu
2020-09-10 8:11 ` Greentime Hu
2020-09-10 8:11 ` [RFC PATCH v7 01/21] riscv: Separate patch for cflags and aflags Greentime Hu
2020-09-10 8:11 ` Greentime Hu
2020-09-10 8:11 ` [RFC PATCH v7 02/21] riscv: Rename __switch_to_aux -> fpu Greentime Hu
2020-09-10 8:11 ` Greentime Hu
2020-09-10 8:11 ` [RFC PATCH v7 03/21] riscv: Extending cpufeature.c to detect V-extension Greentime Hu
2020-09-10 8:11 ` Greentime Hu
2020-09-10 8:11 ` [RFC PATCH v7 04/21] riscv: Add new csr defines related to vector extension Greentime Hu
2020-09-10 8:11 ` Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 05/21] riscv: Add vector feature to compile Greentime Hu
2020-09-10 8:12 ` Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 06/21] riscv: Add has_vector/riscv_vsize to save vector features Greentime Hu
2020-09-10 8:12 ` Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 07/21] riscv: Reset vector register Greentime Hu
2020-09-10 8:12 ` Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 08/21] riscv: Add vector struct and assembler definitions Greentime Hu
2020-09-10 8:12 ` Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 09/21] riscv: Add task switch support for vector Greentime Hu
2020-09-10 8:12 ` Greentime Hu
2020-09-10 15:48 ` kernel test robot [this message]
2020-09-10 8:12 ` [RFC PATCH v7 10/21] " Greentime Hu
2020-09-10 8:12 ` Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 11/21] riscv: Add ptrace vector support Greentime Hu
2020-09-10 8:12 ` Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 12/21] riscv: Add sigcontext save/restore for vector Greentime Hu
2020-09-10 8:12 ` Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 13/21] riscv: signal: Report signal frame size to userspace via auxv Greentime Hu
2020-09-10 8:12 ` Greentime Hu
2020-09-10 18:35 ` kernel test robot
2020-09-10 8:12 ` [RFC PATCH v7 14/21] riscv: Add support for kernel mode vector Greentime Hu
2020-09-10 8:12 ` Greentime Hu
2020-09-10 20:53 ` kernel test robot
2020-09-10 8:12 ` [RFC PATCH v7 15/21] riscv: Use CSR_STATUS to replace sstatus in vector.S Greentime Hu
2020-09-10 8:12 ` Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 16/21] riscv: Add vector extension XOR implementation Greentime Hu
2020-09-10 8:12 ` Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 17/21] riscv: Initialize vector registers with proper vsetvli then it can work normally Greentime Hu
2020-09-10 8:12 ` Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 18/21] riscv: Optimize vector registers initialization Greentime Hu
2020-09-10 8:12 ` Greentime Hu
2020-09-10 23:33 ` kernel test robot
2020-09-10 8:12 ` [RFC PATCH v7 19/21] riscv: Fix an illegal instruction exception when accessing vlenb without enable vector first Greentime Hu
2020-09-10 8:12 ` Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 20/21] riscv: Allocate space for vector registers in start_thread() Greentime Hu
2020-09-10 8:12 ` Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 21/21] riscv: Optimize task switch codes of vector Greentime Hu
2020-09-10 8:12 ` Greentime Hu
2020-09-11 2:13 ` kernel test robot
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