All of lore.kernel.org
 help / color / mirror / Atom feed
From: Greentime Hu <greentime.hu@sifive.com>
To: greentime.hu@sifive.com, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu,
	palmer@dabbelt.com, paul.walmsley@sifive.com
Cc: Guo Ren <guoren@linux.alibaba.com>
Subject: [RFC PATCH v7 06/21] riscv: Add has_vector/riscv_vsize to save vector features.
Date: Thu, 10 Sep 2020 16:12:01 +0800	[thread overview]
Message-ID: <d5aedcd12c8a2f777063fec8926ee396d1e263a7.1599719352.git.greentime.hu@sifive.com> (raw)
In-Reply-To: <cover.1599719352.git.greentime.hu@sifive.com>

This patch is used to detect vector support status of CPU and use
riscv_vsize to save the size of all the vector registers. It assumes
all harts has the same capabilities in SMP system.

[guoren@linux.alibaba.com: add has_vector checking]
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
---
 arch/riscv/kernel/cpufeature.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index f11ada3fa906..4d4f78f6a5db 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -21,6 +21,10 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
 #ifdef CONFIG_FPU
 bool has_fpu __read_mostly;
 #endif
+#ifdef CONFIG_VECTOR
+bool has_vector __read_mostly;
+unsigned long riscv_vsize __read_mostly;
+#endif
 
 /**
  * riscv_isa_extension_base() - Get base extension word
@@ -149,4 +153,12 @@ void riscv_fill_hwcap(void)
 	if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D))
 		has_fpu = true;
 #endif
+
+#ifdef CONFIG_VECTOR
+	if (elf_hwcap & COMPAT_HWCAP_ISA_V) {
+		has_vector = true;
+		/* There are 32 vector registers with vlenb length. */
+		riscv_vsize = csr_read(CSR_VLENB) * 32;
+	}
+#endif
 }
-- 
2.28.0


WARNING: multiple messages have this Message-ID (diff)
From: Greentime Hu <greentime.hu@sifive.com>
To: greentime.hu@sifive.com, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu,
	palmer@dabbelt.com, paul.walmsley@sifive.com
Cc: Guo Ren <guoren@linux.alibaba.com>
Subject: [RFC PATCH v7 06/21] riscv: Add has_vector/riscv_vsize to save vector features.
Date: Thu, 10 Sep 2020 16:12:01 +0800	[thread overview]
Message-ID: <d5aedcd12c8a2f777063fec8926ee396d1e263a7.1599719352.git.greentime.hu@sifive.com> (raw)
In-Reply-To: <cover.1599719352.git.greentime.hu@sifive.com>

This patch is used to detect vector support status of CPU and use
riscv_vsize to save the size of all the vector registers. It assumes
all harts has the same capabilities in SMP system.

[guoren@linux.alibaba.com: add has_vector checking]
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
---
 arch/riscv/kernel/cpufeature.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index f11ada3fa906..4d4f78f6a5db 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -21,6 +21,10 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
 #ifdef CONFIG_FPU
 bool has_fpu __read_mostly;
 #endif
+#ifdef CONFIG_VECTOR
+bool has_vector __read_mostly;
+unsigned long riscv_vsize __read_mostly;
+#endif
 
 /**
  * riscv_isa_extension_base() - Get base extension word
@@ -149,4 +153,12 @@ void riscv_fill_hwcap(void)
 	if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D))
 		has_fpu = true;
 #endif
+
+#ifdef CONFIG_VECTOR
+	if (elf_hwcap & COMPAT_HWCAP_ISA_V) {
+		has_vector = true;
+		/* There are 32 vector registers with vlenb length. */
+		riscv_vsize = csr_read(CSR_VLENB) * 32;
+	}
+#endif
 }
-- 
2.28.0


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  parent reply	other threads:[~2020-09-10  8:17 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-10  8:11 [RFC PATCH v7 00/21] riscv: Add vector ISA support Greentime Hu
2020-09-10  8:11 ` Greentime Hu
2020-09-10  8:11 ` [RFC PATCH v7 01/21] riscv: Separate patch for cflags and aflags Greentime Hu
2020-09-10  8:11   ` Greentime Hu
2020-09-10  8:11 ` [RFC PATCH v7 02/21] riscv: Rename __switch_to_aux -> fpu Greentime Hu
2020-09-10  8:11   ` Greentime Hu
2020-09-10  8:11 ` [RFC PATCH v7 03/21] riscv: Extending cpufeature.c to detect V-extension Greentime Hu
2020-09-10  8:11   ` Greentime Hu
2020-09-10  8:11 ` [RFC PATCH v7 04/21] riscv: Add new csr defines related to vector extension Greentime Hu
2020-09-10  8:11   ` Greentime Hu
2020-09-10  8:12 ` [RFC PATCH v7 05/21] riscv: Add vector feature to compile Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-10  8:12 ` Greentime Hu [this message]
2020-09-10  8:12   ` [RFC PATCH v7 06/21] riscv: Add has_vector/riscv_vsize to save vector features Greentime Hu
2020-09-10  8:12 ` [RFC PATCH v7 07/21] riscv: Reset vector register Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-10  8:12 ` [RFC PATCH v7 08/21] riscv: Add vector struct and assembler definitions Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-10  8:12 ` [RFC PATCH v7 09/21] riscv: Add task switch support for vector Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-10 15:48   ` kernel test robot
2020-09-10  8:12 ` [RFC PATCH v7 10/21] " Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-10  8:12 ` [RFC PATCH v7 11/21] riscv: Add ptrace vector support Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-10  8:12 ` [RFC PATCH v7 12/21] riscv: Add sigcontext save/restore for vector Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-10  8:12 ` [RFC PATCH v7 13/21] riscv: signal: Report signal frame size to userspace via auxv Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-10 18:35   ` kernel test robot
2020-09-10  8:12 ` [RFC PATCH v7 14/21] riscv: Add support for kernel mode vector Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-10 20:53   ` kernel test robot
2020-09-10  8:12 ` [RFC PATCH v7 15/21] riscv: Use CSR_STATUS to replace sstatus in vector.S Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-10  8:12 ` [RFC PATCH v7 16/21] riscv: Add vector extension XOR implementation Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-10  8:12 ` [RFC PATCH v7 17/21] riscv: Initialize vector registers with proper vsetvli then it can work normally Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-10  8:12 ` [RFC PATCH v7 18/21] riscv: Optimize vector registers initialization Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-10 23:33   ` kernel test robot
2020-09-10  8:12 ` [RFC PATCH v7 19/21] riscv: Fix an illegal instruction exception when accessing vlenb without enable vector first Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-10  8:12 ` [RFC PATCH v7 20/21] riscv: Allocate space for vector registers in start_thread() Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-10  8:12 ` [RFC PATCH v7 21/21] riscv: Optimize task switch codes of vector Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-11  2:13   ` kernel test robot

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=d5aedcd12c8a2f777063fec8926ee396d1e263a7.1599719352.git.greentime.hu@sifive.com \
    --to=greentime.hu@sifive.com \
    --cc=aou@eecs.berkeley.edu \
    --cc=guoren@linux.alibaba.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=palmer@dabbelt.com \
    --cc=paul.walmsley@sifive.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.