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From: Greentime Hu <greentime.hu@sifive.com>
To: greentime.hu@sifive.com, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu,
	palmer@dabbelt.com, paul.walmsley@sifive.com
Cc: Guo Ren <guoren@linux.alibaba.com>, Guo Ren <guoren@kernel.org>
Subject: [RFC PATCH v7 04/21] riscv: Add new csr defines related to vector extension
Date: Thu, 10 Sep 2020 16:11:59 +0800	[thread overview]
Message-ID: <c75e35c53ad8eb24a3f21f17f383d1f0177138a8.1599719352.git.greentime.hu@sifive.com> (raw)
In-Reply-To: <cover.1599719352.git.greentime.hu@sifive.com>

Follow the riscv vector spec to add new csr numbers.

[guoren@linux.alibaba.com: first porting for new vector related csr]
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Acked-by: Guo Ren <guoren@kernel.org>
---
 arch/riscv/include/asm/csr.h | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index cec462e198ce..0d4c89fb97b5 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -24,6 +24,12 @@
 #define SR_FS_CLEAN	_AC(0x00004000, UL)
 #define SR_FS_DIRTY	_AC(0x00006000, UL)
 
+#define SR_VS           _AC(0x00000600, UL) /* Vector Status */
+#define SR_VS_OFF       _AC(0x00000000, UL)
+#define SR_VS_INITIAL   _AC(0x00000200, UL)
+#define SR_VS_CLEAN     _AC(0x00000400, UL)
+#define SR_VS_DIRTY     _AC(0x00000600, UL)
+
 #define SR_XS		_AC(0x00018000, UL) /* Extension Status */
 #define SR_XS_OFF	_AC(0x00000000, UL)
 #define SR_XS_INITIAL	_AC(0x00008000, UL)
@@ -31,9 +37,9 @@
 #define SR_XS_DIRTY	_AC(0x00018000, UL)
 
 #ifndef CONFIG_64BIT
-#define SR_SD		_AC(0x80000000, UL) /* FS/XS dirty */
+#define SR_SD		_AC(0x80000000, UL) /* FS/VS/XS dirty */
 #else
-#define SR_SD		_AC(0x8000000000000000, UL) /* FS/XS dirty */
+#define SR_SD		_AC(0x8000000000000000, UL) /* FS/VS/XS dirty */
 #endif
 
 /* SATP flags */
@@ -111,6 +117,12 @@
 #define CSR_PMPADDR0		0x3b0
 #define CSR_MHARTID		0xf14
 
+#define CSR_VSTART		0x8
+#define CSR_VCSR		0xf
+#define CSR_VL			0xc20
+#define CSR_VTYPE		0xc21
+#define CSR_VLENB		0xc22
+
 #ifdef CONFIG_RISCV_M_MODE
 # define CSR_STATUS	CSR_MSTATUS
 # define CSR_IE		CSR_MIE
-- 
2.28.0


WARNING: multiple messages have this Message-ID (diff)
From: Greentime Hu <greentime.hu@sifive.com>
To: greentime.hu@sifive.com, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu,
	palmer@dabbelt.com, paul.walmsley@sifive.com
Cc: Guo Ren <guoren@linux.alibaba.com>, Guo Ren <guoren@kernel.org>
Subject: [RFC PATCH v7 04/21] riscv: Add new csr defines related to vector extension
Date: Thu, 10 Sep 2020 16:11:59 +0800	[thread overview]
Message-ID: <c75e35c53ad8eb24a3f21f17f383d1f0177138a8.1599719352.git.greentime.hu@sifive.com> (raw)
In-Reply-To: <cover.1599719352.git.greentime.hu@sifive.com>

Follow the riscv vector spec to add new csr numbers.

[guoren@linux.alibaba.com: first porting for new vector related csr]
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Acked-by: Guo Ren <guoren@kernel.org>
---
 arch/riscv/include/asm/csr.h | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index cec462e198ce..0d4c89fb97b5 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -24,6 +24,12 @@
 #define SR_FS_CLEAN	_AC(0x00004000, UL)
 #define SR_FS_DIRTY	_AC(0x00006000, UL)
 
+#define SR_VS           _AC(0x00000600, UL) /* Vector Status */
+#define SR_VS_OFF       _AC(0x00000000, UL)
+#define SR_VS_INITIAL   _AC(0x00000200, UL)
+#define SR_VS_CLEAN     _AC(0x00000400, UL)
+#define SR_VS_DIRTY     _AC(0x00000600, UL)
+
 #define SR_XS		_AC(0x00018000, UL) /* Extension Status */
 #define SR_XS_OFF	_AC(0x00000000, UL)
 #define SR_XS_INITIAL	_AC(0x00008000, UL)
@@ -31,9 +37,9 @@
 #define SR_XS_DIRTY	_AC(0x00018000, UL)
 
 #ifndef CONFIG_64BIT
-#define SR_SD		_AC(0x80000000, UL) /* FS/XS dirty */
+#define SR_SD		_AC(0x80000000, UL) /* FS/VS/XS dirty */
 #else
-#define SR_SD		_AC(0x8000000000000000, UL) /* FS/XS dirty */
+#define SR_SD		_AC(0x8000000000000000, UL) /* FS/VS/XS dirty */
 #endif
 
 /* SATP flags */
@@ -111,6 +117,12 @@
 #define CSR_PMPADDR0		0x3b0
 #define CSR_MHARTID		0xf14
 
+#define CSR_VSTART		0x8
+#define CSR_VCSR		0xf
+#define CSR_VL			0xc20
+#define CSR_VTYPE		0xc21
+#define CSR_VLENB		0xc22
+
 #ifdef CONFIG_RISCV_M_MODE
 # define CSR_STATUS	CSR_MSTATUS
 # define CSR_IE		CSR_MIE
-- 
2.28.0


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  parent reply	other threads:[~2020-09-10  8:15 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-10  8:11 [RFC PATCH v7 00/21] riscv: Add vector ISA support Greentime Hu
2020-09-10  8:11 ` Greentime Hu
2020-09-10  8:11 ` [RFC PATCH v7 01/21] riscv: Separate patch for cflags and aflags Greentime Hu
2020-09-10  8:11   ` Greentime Hu
2020-09-10  8:11 ` [RFC PATCH v7 02/21] riscv: Rename __switch_to_aux -> fpu Greentime Hu
2020-09-10  8:11   ` Greentime Hu
2020-09-10  8:11 ` [RFC PATCH v7 03/21] riscv: Extending cpufeature.c to detect V-extension Greentime Hu
2020-09-10  8:11   ` Greentime Hu
2020-09-10  8:11 ` Greentime Hu [this message]
2020-09-10  8:11   ` [RFC PATCH v7 04/21] riscv: Add new csr defines related to vector extension Greentime Hu
2020-09-10  8:12 ` [RFC PATCH v7 05/21] riscv: Add vector feature to compile Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-10  8:12 ` [RFC PATCH v7 06/21] riscv: Add has_vector/riscv_vsize to save vector features Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-10  8:12 ` [RFC PATCH v7 07/21] riscv: Reset vector register Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-10  8:12 ` [RFC PATCH v7 08/21] riscv: Add vector struct and assembler definitions Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-10  8:12 ` [RFC PATCH v7 09/21] riscv: Add task switch support for vector Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-10 15:48   ` kernel test robot
2020-09-10  8:12 ` [RFC PATCH v7 10/21] " Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-10  8:12 ` [RFC PATCH v7 11/21] riscv: Add ptrace vector support Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-10  8:12 ` [RFC PATCH v7 12/21] riscv: Add sigcontext save/restore for vector Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-10  8:12 ` [RFC PATCH v7 13/21] riscv: signal: Report signal frame size to userspace via auxv Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-10 18:35   ` kernel test robot
2020-09-10  8:12 ` [RFC PATCH v7 14/21] riscv: Add support for kernel mode vector Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-10 20:53   ` kernel test robot
2020-09-10  8:12 ` [RFC PATCH v7 15/21] riscv: Use CSR_STATUS to replace sstatus in vector.S Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-10  8:12 ` [RFC PATCH v7 16/21] riscv: Add vector extension XOR implementation Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-10  8:12 ` [RFC PATCH v7 17/21] riscv: Initialize vector registers with proper vsetvli then it can work normally Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-10  8:12 ` [RFC PATCH v7 18/21] riscv: Optimize vector registers initialization Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-10 23:33   ` kernel test robot
2020-09-10  8:12 ` [RFC PATCH v7 19/21] riscv: Fix an illegal instruction exception when accessing vlenb without enable vector first Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-10  8:12 ` [RFC PATCH v7 20/21] riscv: Allocate space for vector registers in start_thread() Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-10  8:12 ` [RFC PATCH v7 21/21] riscv: Optimize task switch codes of vector Greentime Hu
2020-09-10  8:12   ` Greentime Hu
2020-09-11  2:13   ` kernel test robot

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