From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, Alistair Francis <Alistair.Francis@wdc.com>
Subject: [PATCH v2 5/6] target/riscv: Set instance_align on RISCVCPU TypeInfo
Date: Tue, 15 Sep 2020 17:46:37 -0700 [thread overview]
Message-ID: <20200916004638.2444147-6-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200916004638.2444147-1-richard.henderson@linaro.org>
Fix alignment of CPURISCVState.vreg.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Cc: qemu-riscv@nongnu.org
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 57c006df5d..0bbfd7f457 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -628,6 +628,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.name = TYPE_RISCV_CPU,
.parent = TYPE_CPU,
.instance_size = sizeof(RISCVCPU),
+ .instance_align = __alignof__(RISCVCPU),
.instance_init = riscv_cpu_init,
.abstract = true,
.class_size = sizeof(RISCVCPUClass),
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Alistair Francis <Alistair.Francis@wdc.com>, qemu-riscv@nongnu.org
Subject: [PATCH v2 5/6] target/riscv: Set instance_align on RISCVCPU TypeInfo
Date: Tue, 15 Sep 2020 17:46:37 -0700 [thread overview]
Message-ID: <20200916004638.2444147-6-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200916004638.2444147-1-richard.henderson@linaro.org>
Fix alignment of CPURISCVState.vreg.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Cc: qemu-riscv@nongnu.org
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 57c006df5d..0bbfd7f457 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -628,6 +628,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.name = TYPE_RISCV_CPU,
.parent = TYPE_CPU,
.instance_size = sizeof(RISCVCPU),
+ .instance_align = __alignof__(RISCVCPU),
.instance_init = riscv_cpu_init,
.abstract = true,
.class_size = sizeof(RISCVCPUClass),
--
2.25.1
next prev parent reply other threads:[~2020-09-16 0:48 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-16 0:46 [PATCH v2 0/6] qom: Allow object to be aligned Richard Henderson
2020-09-16 0:46 ` Richard Henderson
2020-09-16 0:46 ` [PATCH v2 1/6] util/oslib-win32: Use _aligned_malloc for qemu_try_memalign Richard Henderson
2020-09-16 3:39 ` Stefan Weil
2020-09-17 18:43 ` Eduardo Habkost
2020-09-17 20:34 ` Richard Henderson
2020-09-16 0:46 ` [PATCH v2 2/6] qom: Allow objects to be allocated with increased alignment Richard Henderson
2020-09-16 0:46 ` [PATCH v2 3/6] target/arm: Set instance_align on CPUARM TypeInfo Richard Henderson
2020-09-16 0:46 ` [PATCH v2 4/6] target/ppc: Set instance_align on PowerPCCPU TypeInfo Richard Henderson
2020-09-16 2:18 ` David Gibson
2020-09-16 0:46 ` Richard Henderson [this message]
2020-09-16 0:46 ` [PATCH v2 5/6] target/riscv: Set instance_align on RISCVCPU TypeInfo Richard Henderson
2020-09-16 14:58 ` Alistair Francis
2020-09-16 14:58 ` Alistair Francis
2020-09-16 0:46 ` [PATCH v2 6/6] target/s390x: Set instance_align on S390CPU TypeInfo Richard Henderson
2020-09-18 18:00 ` [PATCH v2 0/6] qom: Allow object to be aligned Eduardo Habkost
2020-09-18 18:00 ` Eduardo Habkost
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