From: Will Deacon <will@kernel.org>
To: Robin Murphy <robin.murphy@arm.com>
Cc: robh@kernel.org, tomeu.vizoso@collabora.com,
narmstrong@baylibre.com, khilman@baylibre.com,
dri-devel@lists.freedesktop.org, steven.price@arm.com,
iommu@lists.linux-foundation.org,
alyssa.rosenzweig@collabora.com,
linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org, jbrunet@baylibre.com
Subject: Re: [PATCH 1/3] iommu/io-pgtable-arm: Support coherency for Mali LPAE
Date: Mon, 21 Sep 2020 23:24:34 +0100 [thread overview]
Message-ID: <20200921222434.GB4409@willie-the-truck> (raw)
In-Reply-To: <71cc6c53-7bd1-da1a-05fa-8172510b33d8@arm.com>
On Mon, Sep 21, 2020 at 10:53:23PM +0100, Robin Murphy wrote:
> On 2020-09-21 18:57, Will Deacon wrote:
> > On Wed, Sep 16, 2020 at 12:51:05AM +0100, Robin Murphy wrote:
> > > Midgard GPUs have ACE-Lite master interfaces which allows systems to
> > > integrate them in an I/O-coherent manner. It seems that from the GPU's
> > > viewpoint, the rest of the system is its outer shareable domain, and so
> > > even when snoop signals are wired up, they are only emitted for outer
> > > shareable accesses. As such, setting the TTBR_SHARE_OUTER bit does
> > > indeed get coherent pagetable walks working nicely for the coherent
> > > T620 in the Arm Juno SoC.
> >
> > I can't help but think some of this commentary deserves to be in the code
> > as well.
>
> Sure, if you want.
Yes, please.
> > Do you know if this sort of thing is done for other SoCs too, or is this
> > just a Juno quirk?
>
> Yup, this is a "Midgard working as designed" thing. Juno is the coherent
> example I have to hand, but off the top of my head I believe some of the
> Exynos SoCs can also use their GPUs coherently if a switch is flipped in the
> interconnect to change routing between the CCI and a direct-to-RAM path; I
> expect there are probably further Midgard examples that I'm not aware of.
> Then there are definitely coherent Bifrost GPUs like the Amlogic S922/A311
> that prompted me to revive this patch, which we currently drive in "Legacy"
> mode and thus behave the same way as Midgard (Bifrost's "AArch64" mode
> realigns Ish and Osh with the rest of the system, and instead invents a new
> "Internal Shareable" value in between Nsh and Ish to represent the
> shareability between cores within the GPU for which Midgard hijacked Ish).
That is more than I wanted to know :) "Internal Shareable", jeez...
Thanks,
Will
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will@kernel.org>
To: Robin Murphy <robin.murphy@arm.com>
Cc: robh@kernel.org, tomeu.vizoso@collabora.com,
narmstrong@baylibre.com, khilman@baylibre.com,
dri-devel@lists.freedesktop.org, steven.price@arm.com,
iommu@lists.linux-foundation.org,
alyssa.rosenzweig@collabora.com,
linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org, jbrunet@baylibre.com
Subject: Re: [PATCH 1/3] iommu/io-pgtable-arm: Support coherency for Mali LPAE
Date: Mon, 21 Sep 2020 23:24:34 +0100 [thread overview]
Message-ID: <20200921222434.GB4409@willie-the-truck> (raw)
In-Reply-To: <71cc6c53-7bd1-da1a-05fa-8172510b33d8@arm.com>
On Mon, Sep 21, 2020 at 10:53:23PM +0100, Robin Murphy wrote:
> On 2020-09-21 18:57, Will Deacon wrote:
> > On Wed, Sep 16, 2020 at 12:51:05AM +0100, Robin Murphy wrote:
> > > Midgard GPUs have ACE-Lite master interfaces which allows systems to
> > > integrate them in an I/O-coherent manner. It seems that from the GPU's
> > > viewpoint, the rest of the system is its outer shareable domain, and so
> > > even when snoop signals are wired up, they are only emitted for outer
> > > shareable accesses. As such, setting the TTBR_SHARE_OUTER bit does
> > > indeed get coherent pagetable walks working nicely for the coherent
> > > T620 in the Arm Juno SoC.
> >
> > I can't help but think some of this commentary deserves to be in the code
> > as well.
>
> Sure, if you want.
Yes, please.
> > Do you know if this sort of thing is done for other SoCs too, or is this
> > just a Juno quirk?
>
> Yup, this is a "Midgard working as designed" thing. Juno is the coherent
> example I have to hand, but off the top of my head I believe some of the
> Exynos SoCs can also use their GPUs coherently if a switch is flipped in the
> interconnect to change routing between the CCI and a direct-to-RAM path; I
> expect there are probably further Midgard examples that I'm not aware of.
> Then there are definitely coherent Bifrost GPUs like the Amlogic S922/A311
> that prompted me to revive this patch, which we currently drive in "Legacy"
> mode and thus behave the same way as Midgard (Bifrost's "AArch64" mode
> realigns Ish and Osh with the rest of the system, and instead invents a new
> "Internal Shareable" value in between Nsh and Ish to represent the
> shareability between cores within the GPU for which Midgard hijacked Ish).
That is more than I wanted to know :) "Internal Shareable", jeez...
Thanks,
Will
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will@kernel.org>
To: Robin Murphy <robin.murphy@arm.com>
Cc: tomeu.vizoso@collabora.com, narmstrong@baylibre.com,
khilman@baylibre.com, dri-devel@lists.freedesktop.org,
steven.price@arm.com, iommu@lists.linux-foundation.org,
alyssa.rosenzweig@collabora.com,
linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org, jbrunet@baylibre.com
Subject: Re: [PATCH 1/3] iommu/io-pgtable-arm: Support coherency for Mali LPAE
Date: Mon, 21 Sep 2020 23:24:34 +0100 [thread overview]
Message-ID: <20200921222434.GB4409@willie-the-truck> (raw)
In-Reply-To: <71cc6c53-7bd1-da1a-05fa-8172510b33d8@arm.com>
On Mon, Sep 21, 2020 at 10:53:23PM +0100, Robin Murphy wrote:
> On 2020-09-21 18:57, Will Deacon wrote:
> > On Wed, Sep 16, 2020 at 12:51:05AM +0100, Robin Murphy wrote:
> > > Midgard GPUs have ACE-Lite master interfaces which allows systems to
> > > integrate them in an I/O-coherent manner. It seems that from the GPU's
> > > viewpoint, the rest of the system is its outer shareable domain, and so
> > > even when snoop signals are wired up, they are only emitted for outer
> > > shareable accesses. As such, setting the TTBR_SHARE_OUTER bit does
> > > indeed get coherent pagetable walks working nicely for the coherent
> > > T620 in the Arm Juno SoC.
> >
> > I can't help but think some of this commentary deserves to be in the code
> > as well.
>
> Sure, if you want.
Yes, please.
> > Do you know if this sort of thing is done for other SoCs too, or is this
> > just a Juno quirk?
>
> Yup, this is a "Midgard working as designed" thing. Juno is the coherent
> example I have to hand, but off the top of my head I believe some of the
> Exynos SoCs can also use their GPUs coherently if a switch is flipped in the
> interconnect to change routing between the CCI and a direct-to-RAM path; I
> expect there are probably further Midgard examples that I'm not aware of.
> Then there are definitely coherent Bifrost GPUs like the Amlogic S922/A311
> that prompted me to revive this patch, which we currently drive in "Legacy"
> mode and thus behave the same way as Midgard (Bifrost's "AArch64" mode
> realigns Ish and Osh with the rest of the system, and instead invents a new
> "Internal Shareable" value in between Nsh and Ish to represent the
> shareability between cores within the GPU for which Midgard hijacked Ish).
That is more than I wanted to know :) "Internal Shareable", jeez...
Thanks,
Will
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will@kernel.org>
To: Robin Murphy <robin.murphy@arm.com>
Cc: robh@kernel.org, tomeu.vizoso@collabora.com,
narmstrong@baylibre.com, khilman@baylibre.com,
dri-devel@lists.freedesktop.org, steven.price@arm.com,
iommu@lists.linux-foundation.org,
alyssa.rosenzweig@collabora.com,
linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org, jbrunet@baylibre.com
Subject: Re: [PATCH 1/3] iommu/io-pgtable-arm: Support coherency for Mali LPAE
Date: Mon, 21 Sep 2020 23:24:34 +0100 [thread overview]
Message-ID: <20200921222434.GB4409@willie-the-truck> (raw)
In-Reply-To: <71cc6c53-7bd1-da1a-05fa-8172510b33d8@arm.com>
On Mon, Sep 21, 2020 at 10:53:23PM +0100, Robin Murphy wrote:
> On 2020-09-21 18:57, Will Deacon wrote:
> > On Wed, Sep 16, 2020 at 12:51:05AM +0100, Robin Murphy wrote:
> > > Midgard GPUs have ACE-Lite master interfaces which allows systems to
> > > integrate them in an I/O-coherent manner. It seems that from the GPU's
> > > viewpoint, the rest of the system is its outer shareable domain, and so
> > > even when snoop signals are wired up, they are only emitted for outer
> > > shareable accesses. As such, setting the TTBR_SHARE_OUTER bit does
> > > indeed get coherent pagetable walks working nicely for the coherent
> > > T620 in the Arm Juno SoC.
> >
> > I can't help but think some of this commentary deserves to be in the code
> > as well.
>
> Sure, if you want.
Yes, please.
> > Do you know if this sort of thing is done for other SoCs too, or is this
> > just a Juno quirk?
>
> Yup, this is a "Midgard working as designed" thing. Juno is the coherent
> example I have to hand, but off the top of my head I believe some of the
> Exynos SoCs can also use their GPUs coherently if a switch is flipped in the
> interconnect to change routing between the CCI and a direct-to-RAM path; I
> expect there are probably further Midgard examples that I'm not aware of.
> Then there are definitely coherent Bifrost GPUs like the Amlogic S922/A311
> that prompted me to revive this patch, which we currently drive in "Legacy"
> mode and thus behave the same way as Midgard (Bifrost's "AArch64" mode
> realigns Ish and Osh with the rest of the system, and instead invents a new
> "Internal Shareable" value in between Nsh and Ish to represent the
> shareability between cores within the GPU for which Midgard hijacked Ish).
That is more than I wanted to know :) "Internal Shareable", jeez...
Thanks,
Will
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
next prev parent reply other threads:[~2020-09-21 22:24 UTC|newest]
Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-15 23:51 [PATCH 0/3] drm: panfrost: Coherency support Robin Murphy
2020-09-15 23:51 ` Robin Murphy
2020-09-15 23:51 ` Robin Murphy
2020-09-15 23:51 ` Robin Murphy
2020-09-15 23:51 ` [PATCH 1/3] iommu/io-pgtable-arm: Support coherency for Mali LPAE Robin Murphy
2020-09-15 23:51 ` Robin Murphy
2020-09-15 23:51 ` Robin Murphy
2020-09-15 23:51 ` Robin Murphy
2020-09-21 17:57 ` Will Deacon
2020-09-21 17:57 ` Will Deacon
2020-09-21 17:57 ` Will Deacon
2020-09-21 17:57 ` Will Deacon
2020-09-21 21:53 ` Robin Murphy
2020-09-21 21:53 ` Robin Murphy
2020-09-21 21:53 ` Robin Murphy
2020-09-21 21:53 ` Robin Murphy
2020-09-21 22:24 ` Will Deacon [this message]
2020-09-21 22:24 ` Will Deacon
2020-09-21 22:24 ` Will Deacon
2020-09-21 22:24 ` Will Deacon
2020-09-15 23:51 ` [PATCH 2/3] drm/panfrost: Support cache-coherent integrations Robin Murphy
2020-09-15 23:51 ` Robin Murphy
2020-09-15 23:51 ` Robin Murphy
2020-09-15 23:51 ` Robin Murphy
2020-09-17 10:37 ` Steven Price
2020-09-17 10:37 ` Steven Price
2020-09-17 10:37 ` Steven Price
2020-09-17 10:37 ` Steven Price
2020-09-15 23:51 ` [PATCH 3/3] arm64: dts: meson: Describe G12b GPU as coherent Robin Murphy
2020-09-15 23:51 ` Robin Murphy
2020-09-15 23:51 ` Robin Murphy
2020-09-15 23:51 ` Robin Murphy
2020-09-16 8:26 ` Neil Armstrong
2020-09-16 8:26 ` Neil Armstrong
2020-09-16 8:26 ` Neil Armstrong
2020-09-16 8:26 ` Neil Armstrong
2020-10-05 8:15 ` Boris Brezillon
2020-10-05 8:15 ` Boris Brezillon
2020-10-05 8:15 ` Boris Brezillon
2020-10-05 8:15 ` Boris Brezillon
2020-10-05 8:34 ` Steven Price
2020-10-05 8:34 ` Steven Price
2020-10-05 8:34 ` Steven Price
2020-10-05 8:34 ` Steven Price
2020-10-05 8:39 ` Boris Brezillon
2020-10-05 8:39 ` Boris Brezillon
2020-10-05 8:39 ` Boris Brezillon
2020-10-05 8:39 ` Boris Brezillon
2020-10-05 10:05 ` Steven Price
2020-10-05 10:05 ` Steven Price
2020-10-05 10:05 ` Steven Price
2020-10-05 10:05 ` Steven Price
2020-09-16 14:54 ` Neil Armstrong
2020-09-16 14:54 ` Neil Armstrong
2020-09-16 14:54 ` Neil Armstrong
2020-09-16 14:54 ` Neil Armstrong
2020-09-16 14:54 ` [PATCH 0/3] drm: panfrost: Coherency support Neil Armstrong
2020-09-16 14:54 ` Neil Armstrong
2020-09-16 14:54 ` Neil Armstrong
2020-09-16 14:54 ` Neil Armstrong
2020-09-16 17:04 ` Alyssa Rosenzweig
2020-09-16 17:04 ` Alyssa Rosenzweig
2020-09-16 17:04 ` Alyssa Rosenzweig
2020-09-16 17:04 ` Alyssa Rosenzweig
2020-09-16 17:46 ` Rob Herring
2020-09-16 17:46 ` Rob Herring
2020-09-16 17:46 ` Rob Herring
2020-09-16 17:46 ` Rob Herring
2020-09-17 10:38 ` Steven Price
2020-09-17 10:38 ` Steven Price
2020-09-17 10:38 ` Steven Price
2020-09-17 10:38 ` Steven Price
2020-09-17 10:51 ` Tomeu Vizoso
2020-09-17 10:51 ` Tomeu Vizoso
2020-09-17 10:51 ` Tomeu Vizoso
2020-09-17 10:51 ` Tomeu Vizoso
2020-09-17 11:00 ` Steven Price
2020-09-17 11:00 ` Steven Price
2020-09-17 11:00 ` Steven Price
2020-09-17 11:00 ` Steven Price
2020-09-17 12:03 ` Alyssa Rosenzweig
2020-09-17 12:03 ` Alyssa Rosenzweig
2020-09-17 12:03 ` Alyssa Rosenzweig
2020-09-17 12:03 ` Alyssa Rosenzweig
2020-09-17 12:38 ` Robin Murphy
2020-09-17 12:38 ` Robin Murphy
2020-09-17 12:38 ` Robin Murphy
2020-09-17 12:38 ` Robin Murphy
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