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* [Intel-gfx] [PATCH 1/2] drm/i915: Make intel_{enable, disable}_sagv() static
@ 2020-09-25 12:17 Ville Syrjala
  2020-09-25 12:17 ` [Intel-gfx] [PATCH 2/2] drm/i915: Don't hide the intel_crtc_atomic_check() call Ville Syrjala
                   ` (4 more replies)
  0 siblings, 5 replies; 7+ messages in thread
From: Ville Syrjala @ 2020-09-25 12:17 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

intel_{enable,disable}_sagv() are no longer needed outside the
compilation unit. Make them static.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 4 ++--
 drivers/gpu/drm/i915/intel_pm.h | 2 --
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 34e0d22d456b..8cd62402d597 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3706,7 +3706,7 @@ skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
  *  - All planes can enable watermarks for latencies >= SAGV engine block time
  *  - We're not using an interlaced display configuration
  */
-int
+static int
 intel_enable_sagv(struct drm_i915_private *dev_priv)
 {
 	int ret;
@@ -3740,7 +3740,7 @@ intel_enable_sagv(struct drm_i915_private *dev_priv)
 	return 0;
 }
 
-int
+static int
 intel_disable_sagv(struct drm_i915_private *dev_priv)
 {
 	int ret;
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index a2473594c2db..eab83e251dd5 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -49,8 +49,6 @@ void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
 bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
 			   const struct intel_bw_state *bw_state);
-int intel_enable_sagv(struct drm_i915_private *dev_priv);
-int intel_disable_sagv(struct drm_i915_private *dev_priv);
 void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
 void intel_sagv_post_plane_update(struct intel_atomic_state *state);
 bool skl_wm_level_equals(const struct skl_wm_level *l1,
-- 
2.26.2

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^ permalink raw reply related	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2020-09-26  0:28 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-25 12:17 [Intel-gfx] [PATCH 1/2] drm/i915: Make intel_{enable, disable}_sagv() static Ville Syrjala
2020-09-25 12:17 ` [Intel-gfx] [PATCH 2/2] drm/i915: Don't hide the intel_crtc_atomic_check() call Ville Syrjala
2020-09-26  0:28   ` Souza, Jose
2020-09-25 12:34 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915: Make intel_{enable, disable}_sagv() static Patchwork
2020-09-25 12:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-09-25 17:39 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-09-26  0:28 ` [Intel-gfx] [PATCH 1/2] " Souza, Jose

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