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* [PATCH] drm/vc4: hdmi: Block odd horizontal timings
@ 2020-09-25 13:00 ` Maxime Ripard
  0 siblings, 0 replies; 10+ messages in thread
From: Maxime Ripard @ 2020-09-25 13:00 UTC (permalink / raw)
  To: Daniel Vetter, David Airlie, Maarten Lankhorst,
	Thomas Zimmermann, Maxime Ripard, Eric Anholt
  Cc: Tim Gover, Dave Stevenson, dri-devel, bcm-kernel-feedback-list,
	linux-rpi-kernel, Phil Elwell, linux-arm-kernel

The FIFO between the pixelvalve and the HDMI controller runs at 2 pixels
per clock cycle, and cannot deal with odd timings.

Let's reject any mode with such timings.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
 drivers/gpu/drm/vc4/vc4_hdmi.c | 12 ++++++++++++
 drivers/gpu/drm/vc4/vc4_hdmi.h |  3 +++
 2 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 1c4dc774d56e..acfb4e235214 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -879,6 +879,11 @@ static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
 	struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 	unsigned long long pixel_rate = mode->clock * 1000;
 
+	if (vc4_hdmi->variant->broken_odd_h_timings &&
+	    ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
+	     (mode->hsync_end % 2) || (mode->htotal % 2)))
+		return -EINVAL;
+
 	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 		pixel_rate *= 2;
 
@@ -901,6 +906,11 @@ vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
 {
 	struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 
+	if (vc4_hdmi->variant->broken_odd_h_timings &&
+	    ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
+	     (mode->hsync_end % 2) || (mode->htotal % 2)))
+		return MODE_H_ILLEGAL;
+
 	if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
 		return MODE_CLOCK_HIGH;
 
@@ -1950,6 +1960,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
 		PHY_LANE_2,
 		PHY_LANE_CK,
 	},
+	.broken_odd_h_timings	= true,
 
 	.init_resources		= vc5_hdmi_init_resources,
 	.csc_setup		= vc5_hdmi_csc_setup,
@@ -1975,6 +1986,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
 		PHY_LANE_CK,
 		PHY_LANE_2,
 	},
+	.broken_odd_h_timings	= true,
 
 	.init_resources		= vc5_hdmi_init_resources,
 	.csc_setup		= vc5_hdmi_csc_setup,
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h
index af45b0d81dec..40e51ece8efe 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
@@ -62,6 +62,9 @@ struct vc4_hdmi_variant {
 	 */
 	enum vc4_hdmi_phy_channel phy_lane_mapping[4];
 
+	/* The BCM2711 cannot deal with odd horizontal pixel timings */
+	bool broken_odd_h_timings;
+
 	/* Callback to get the resources (memory region, interrupts,
 	 * clocks, etc) for that variant.
 	 */
-- 
2.26.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 10+ messages in thread
* [PATCH] drm/vc4: hdmi: Block odd horizontal timings
@ 2020-09-25 13:00 ` Maxime Ripard
  0 siblings, 0 replies; 10+ messages in thread
From: Maxime Ripard @ 2020-09-25 13:00 UTC (permalink / raw)
  To: Daniel Vetter, David Airlie, Maarten Lankhorst,
	Thomas Zimmermann, Maxime Ripard, Eric Anholt
  Cc: Tim Gover, Dave Stevenson, dri-devel, bcm-kernel-feedback-list,
	linux-rpi-kernel, Phil Elwell, linux-arm-kernel

The FIFO between the pixelvalve and the HDMI controller runs at 2 pixels
per clock cycle, and cannot deal with odd timings.

Let's reject any mode with such timings.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
 drivers/gpu/drm/vc4/vc4_hdmi.c | 12 ++++++++++++
 drivers/gpu/drm/vc4/vc4_hdmi.h |  3 +++
 2 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 1c4dc774d56e..acfb4e235214 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -879,6 +879,11 @@ static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
 	struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 	unsigned long long pixel_rate = mode->clock * 1000;
 
+	if (vc4_hdmi->variant->broken_odd_h_timings &&
+	    ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
+	     (mode->hsync_end % 2) || (mode->htotal % 2)))
+		return -EINVAL;
+
 	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 		pixel_rate *= 2;
 
@@ -901,6 +906,11 @@ vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
 {
 	struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 
+	if (vc4_hdmi->variant->broken_odd_h_timings &&
+	    ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
+	     (mode->hsync_end % 2) || (mode->htotal % 2)))
+		return MODE_H_ILLEGAL;
+
 	if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
 		return MODE_CLOCK_HIGH;
 
@@ -1950,6 +1960,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
 		PHY_LANE_2,
 		PHY_LANE_CK,
 	},
+	.broken_odd_h_timings	= true,
 
 	.init_resources		= vc5_hdmi_init_resources,
 	.csc_setup		= vc5_hdmi_csc_setup,
@@ -1975,6 +1986,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
 		PHY_LANE_CK,
 		PHY_LANE_2,
 	},
+	.broken_odd_h_timings	= true,
 
 	.init_resources		= vc5_hdmi_init_resources,
 	.csc_setup		= vc5_hdmi_csc_setup,
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h
index af45b0d81dec..40e51ece8efe 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
@@ -62,6 +62,9 @@ struct vc4_hdmi_variant {
 	 */
 	enum vc4_hdmi_phy_channel phy_lane_mapping[4];
 
+	/* The BCM2711 cannot deal with odd horizontal pixel timings */
+	bool broken_odd_h_timings;
+
 	/* Callback to get the resources (memory region, interrupts,
 	 * clocks, etc) for that variant.
 	 */
-- 
2.26.2

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply related	[flat|nested] 10+ messages in thread
* Re: [PATCH] drm/vc4: hdmi: Block odd horizontal timings
  2020-09-25 13:00 ` Maxime Ripard
@ 2020-10-28 13:42   ` Dave Stevenson
  -1 siblings, 0 replies; 10+ messages in thread
From: Dave Stevenson @ 2020-10-28 13:42 UTC (permalink / raw)
  To: Maxime Ripard
  Cc: Tim Gover, David Airlie, Maarten Lankhorst, DRI Development,
	Eric Anholt, bcm-kernel-feedback-list, linux-rpi-kernel,
	Thomas Zimmermann, Daniel Vetter, Phil Elwell, linux-arm-kernel

Hi Maxime

On Fri, 25 Sep 2020 at 14:00, Maxime Ripard <maxime@cerno.tech> wrote:
>
> The FIFO between the pixelvalve and the HDMI controller runs at 2 pixels
> per clock cycle, and cannot deal with odd timings.
>
> Let's reject any mode with such timings.
>
> Signed-off-by: Maxime Ripard <maxime@cerno.tech>

It's unsupported due to the architecture rather than broken.

I'd hope the compiler would convert "% 2" to "& 1" in these cases, but
it's not a critical performance path anyway.

Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>

> ---
>  drivers/gpu/drm/vc4/vc4_hdmi.c | 12 ++++++++++++
>  drivers/gpu/drm/vc4/vc4_hdmi.h |  3 +++
>  2 files changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
> index 1c4dc774d56e..acfb4e235214 100644
> --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
> +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
> @@ -879,6 +879,11 @@ static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
>         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
>         unsigned long long pixel_rate = mode->clock * 1000;
>
> +       if (vc4_hdmi->variant->broken_odd_h_timings &&
> +           ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
> +            (mode->hsync_end % 2) || (mode->htotal % 2)))
> +               return -EINVAL;
> +
>         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
>                 pixel_rate *= 2;
>
> @@ -901,6 +906,11 @@ vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
>  {
>         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
>
> +       if (vc4_hdmi->variant->broken_odd_h_timings &&
> +           ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
> +            (mode->hsync_end % 2) || (mode->htotal % 2)))
> +               return MODE_H_ILLEGAL;
> +
>         if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
>                 return MODE_CLOCK_HIGH;
>
> @@ -1950,6 +1960,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
>                 PHY_LANE_2,
>                 PHY_LANE_CK,
>         },
> +       .broken_odd_h_timings   = true,
>
>         .init_resources         = vc5_hdmi_init_resources,
>         .csc_setup              = vc5_hdmi_csc_setup,
> @@ -1975,6 +1986,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
>                 PHY_LANE_CK,
>                 PHY_LANE_2,
>         },
> +       .broken_odd_h_timings   = true,
>
>         .init_resources         = vc5_hdmi_init_resources,
>         .csc_setup              = vc5_hdmi_csc_setup,
> diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h
> index af45b0d81dec..40e51ece8efe 100644
> --- a/drivers/gpu/drm/vc4/vc4_hdmi.h
> +++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
> @@ -62,6 +62,9 @@ struct vc4_hdmi_variant {
>          */
>         enum vc4_hdmi_phy_channel phy_lane_mapping[4];
>
> +       /* The BCM2711 cannot deal with odd horizontal pixel timings */
> +       bool broken_odd_h_timings;
> +
>         /* Callback to get the resources (memory region, interrupts,
>          * clocks, etc) for that variant.
>          */
> --
> 2.26.2
>

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH] drm/vc4: hdmi: Block odd horizontal timings
@ 2020-10-28 13:42   ` Dave Stevenson
  0 siblings, 0 replies; 10+ messages in thread
From: Dave Stevenson @ 2020-10-28 13:42 UTC (permalink / raw)
  To: Maxime Ripard
  Cc: Tim Gover, David Airlie, DRI Development,
	bcm-kernel-feedback-list, linux-rpi-kernel, Thomas Zimmermann,
	Daniel Vetter, Phil Elwell, linux-arm-kernel

Hi Maxime

On Fri, 25 Sep 2020 at 14:00, Maxime Ripard <maxime@cerno.tech> wrote:
>
> The FIFO between the pixelvalve and the HDMI controller runs at 2 pixels
> per clock cycle, and cannot deal with odd timings.
>
> Let's reject any mode with such timings.
>
> Signed-off-by: Maxime Ripard <maxime@cerno.tech>

It's unsupported due to the architecture rather than broken.

I'd hope the compiler would convert "% 2" to "& 1" in these cases, but
it's not a critical performance path anyway.

Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>

> ---
>  drivers/gpu/drm/vc4/vc4_hdmi.c | 12 ++++++++++++
>  drivers/gpu/drm/vc4/vc4_hdmi.h |  3 +++
>  2 files changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
> index 1c4dc774d56e..acfb4e235214 100644
> --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
> +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
> @@ -879,6 +879,11 @@ static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
>         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
>         unsigned long long pixel_rate = mode->clock * 1000;
>
> +       if (vc4_hdmi->variant->broken_odd_h_timings &&
> +           ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
> +            (mode->hsync_end % 2) || (mode->htotal % 2)))
> +               return -EINVAL;
> +
>         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
>                 pixel_rate *= 2;
>
> @@ -901,6 +906,11 @@ vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
>  {
>         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
>
> +       if (vc4_hdmi->variant->broken_odd_h_timings &&
> +           ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
> +            (mode->hsync_end % 2) || (mode->htotal % 2)))
> +               return MODE_H_ILLEGAL;
> +
>         if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
>                 return MODE_CLOCK_HIGH;
>
> @@ -1950,6 +1960,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
>                 PHY_LANE_2,
>                 PHY_LANE_CK,
>         },
> +       .broken_odd_h_timings   = true,
>
>         .init_resources         = vc5_hdmi_init_resources,
>         .csc_setup              = vc5_hdmi_csc_setup,
> @@ -1975,6 +1986,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
>                 PHY_LANE_CK,
>                 PHY_LANE_2,
>         },
> +       .broken_odd_h_timings   = true,
>
>         .init_resources         = vc5_hdmi_init_resources,
>         .csc_setup              = vc5_hdmi_csc_setup,
> diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h
> index af45b0d81dec..40e51ece8efe 100644
> --- a/drivers/gpu/drm/vc4/vc4_hdmi.h
> +++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
> @@ -62,6 +62,9 @@ struct vc4_hdmi_variant {
>          */
>         enum vc4_hdmi_phy_channel phy_lane_mapping[4];
>
> +       /* The BCM2711 cannot deal with odd horizontal pixel timings */
> +       bool broken_odd_h_timings;
> +
>         /* Callback to get the resources (memory region, interrupts,
>          * clocks, etc) for that variant.
>          */
> --
> 2.26.2
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH] drm/vc4: hdmi: Block odd horizontal timings
  2020-10-28 13:42   ` Dave Stevenson
@ 2020-10-29  9:17     ` Maxime Ripard
  -1 siblings, 0 replies; 10+ messages in thread
From: Maxime Ripard @ 2020-10-29  9:17 UTC (permalink / raw)
  To: Dave Stevenson
  Cc: Tim Gover, David Airlie, Maarten Lankhorst, DRI Development,
	Eric Anholt, bcm-kernel-feedback-list, linux-rpi-kernel,
	Thomas Zimmermann, Daniel Vetter, Phil Elwell, linux-arm-kernel


[-- Attachment #1.1: Type: text/plain, Size: 562 bytes --]

Hi!

On Wed, Oct 28, 2020 at 01:42:20PM +0000, Dave Stevenson wrote:
> Hi Maxime
> 
> On Fri, 25 Sep 2020 at 14:00, Maxime Ripard <maxime@cerno.tech> wrote:
> >
> > The FIFO between the pixelvalve and the HDMI controller runs at 2 pixels
> > per clock cycle, and cannot deal with odd timings.
> >
> > Let's reject any mode with such timings.
> >
> > Signed-off-by: Maxime Ripard <maxime@cerno.tech>

Thanks for your review

> It's unsupported due to the architecture rather than broken.

Would you prefer s/broken/unsupported/ then?

Maxime

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[-- Attachment #2: Type: text/plain, Size: 176 bytes --]

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH] drm/vc4: hdmi: Block odd horizontal timings
@ 2020-10-29  9:17     ` Maxime Ripard
  0 siblings, 0 replies; 10+ messages in thread
From: Maxime Ripard @ 2020-10-29  9:17 UTC (permalink / raw)
  To: Dave Stevenson
  Cc: Tim Gover, David Airlie, DRI Development,
	bcm-kernel-feedback-list, linux-rpi-kernel, Thomas Zimmermann,
	Daniel Vetter, Phil Elwell, linux-arm-kernel


[-- Attachment #1.1: Type: text/plain, Size: 562 bytes --]

Hi!

On Wed, Oct 28, 2020 at 01:42:20PM +0000, Dave Stevenson wrote:
> Hi Maxime
> 
> On Fri, 25 Sep 2020 at 14:00, Maxime Ripard <maxime@cerno.tech> wrote:
> >
> > The FIFO between the pixelvalve and the HDMI controller runs at 2 pixels
> > per clock cycle, and cannot deal with odd timings.
> >
> > Let's reject any mode with such timings.
> >
> > Signed-off-by: Maxime Ripard <maxime@cerno.tech>

Thanks for your review

> It's unsupported due to the architecture rather than broken.

Would you prefer s/broken/unsupported/ then?

Maxime

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH] drm/vc4: hdmi: Block odd horizontal timings
  2020-10-29  9:17     ` Maxime Ripard
@ 2020-10-29 10:49       ` Dave Stevenson
  -1 siblings, 0 replies; 10+ messages in thread
From: Dave Stevenson @ 2020-10-29 10:49 UTC (permalink / raw)
  To: Maxime Ripard
  Cc: Tim Gover, David Airlie, Maarten Lankhorst, DRI Development,
	Eric Anholt, bcm-kernel-feedback-list, linux-rpi-kernel,
	Thomas Zimmermann, Daniel Vetter, Phil Elwell, linux-arm-kernel

On Thu, 29 Oct 2020 at 09:17, Maxime Ripard <maxime@cerno.tech> wrote:
>
> Hi!
>
> On Wed, Oct 28, 2020 at 01:42:20PM +0000, Dave Stevenson wrote:
> > Hi Maxime
> >
> > On Fri, 25 Sep 2020 at 14:00, Maxime Ripard <maxime@cerno.tech> wrote:
> > >
> > > The FIFO between the pixelvalve and the HDMI controller runs at 2 pixels
> > > per clock cycle, and cannot deal with odd timings.
> > >
> > > Let's reject any mode with such timings.
> > >
> > > Signed-off-by: Maxime Ripard <maxime@cerno.tech>
>
> Thanks for your review
>
> > It's unsupported due to the architecture rather than broken.
>
> Would you prefer s/broken/unsupported/ then?

If you needed to respin then yes, but it's not that big a deal.

  Dave

_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH] drm/vc4: hdmi: Block odd horizontal timings
@ 2020-10-29 10:49       ` Dave Stevenson
  0 siblings, 0 replies; 10+ messages in thread
From: Dave Stevenson @ 2020-10-29 10:49 UTC (permalink / raw)
  To: Maxime Ripard
  Cc: Tim Gover, David Airlie, DRI Development,
	bcm-kernel-feedback-list, linux-rpi-kernel, Thomas Zimmermann,
	Daniel Vetter, Phil Elwell, linux-arm-kernel

On Thu, 29 Oct 2020 at 09:17, Maxime Ripard <maxime@cerno.tech> wrote:
>
> Hi!
>
> On Wed, Oct 28, 2020 at 01:42:20PM +0000, Dave Stevenson wrote:
> > Hi Maxime
> >
> > On Fri, 25 Sep 2020 at 14:00, Maxime Ripard <maxime@cerno.tech> wrote:
> > >
> > > The FIFO between the pixelvalve and the HDMI controller runs at 2 pixels
> > > per clock cycle, and cannot deal with odd timings.
> > >
> > > Let's reject any mode with such timings.
> > >
> > > Signed-off-by: Maxime Ripard <maxime@cerno.tech>
>
> Thanks for your review
>
> > It's unsupported due to the architecture rather than broken.
>
> Would you prefer s/broken/unsupported/ then?

If you needed to respin then yes, but it's not that big a deal.

  Dave
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH] drm/vc4: hdmi: Block odd horizontal timings
  2020-10-29 10:49       ` Dave Stevenson
@ 2020-10-29 12:26         ` Maxime Ripard
  -1 siblings, 0 replies; 10+ messages in thread
From: Maxime Ripard @ 2020-10-29 12:26 UTC (permalink / raw)
  To: Dave Stevenson
  Cc: Tim Gover, David Airlie, Maarten Lankhorst, DRI Development,
	Eric Anholt, bcm-kernel-feedback-list, linux-rpi-kernel,
	Thomas Zimmermann, Daniel Vetter, Phil Elwell, linux-arm-kernel


[-- Attachment #1.1: Type: text/plain, Size: 961 bytes --]

On Thu, Oct 29, 2020 at 10:49:22AM +0000, Dave Stevenson wrote:
> On Thu, 29 Oct 2020 at 09:17, Maxime Ripard <maxime@cerno.tech> wrote:
> >
> > Hi!
> >
> > On Wed, Oct 28, 2020 at 01:42:20PM +0000, Dave Stevenson wrote:
> > > Hi Maxime
> > >
> > > On Fri, 25 Sep 2020 at 14:00, Maxime Ripard <maxime@cerno.tech> wrote:
> > > >
> > > > The FIFO between the pixelvalve and the HDMI controller runs at 2 pixels
> > > > per clock cycle, and cannot deal with odd timings.
> > > >
> > > > Let's reject any mode with such timings.
> > > >
> > > > Signed-off-by: Maxime Ripard <maxime@cerno.tech>
> >
> > Thanks for your review
> >
> > > It's unsupported due to the architecture rather than broken.
> >
> > Would you prefer s/broken/unsupported/ then?
> 
> If you needed to respin then yes, but it's not that big a deal.

It had a merge confict (with the 10/12 bit HDMI series) so I ended up
sending a new version with that fixed.

Maxime

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^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH] drm/vc4: hdmi: Block odd horizontal timings
@ 2020-10-29 12:26         ` Maxime Ripard
  0 siblings, 0 replies; 10+ messages in thread
From: Maxime Ripard @ 2020-10-29 12:26 UTC (permalink / raw)
  To: Dave Stevenson
  Cc: Tim Gover, David Airlie, DRI Development,
	bcm-kernel-feedback-list, linux-rpi-kernel, Thomas Zimmermann,
	Daniel Vetter, Phil Elwell, linux-arm-kernel


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On Thu, Oct 29, 2020 at 10:49:22AM +0000, Dave Stevenson wrote:
> On Thu, 29 Oct 2020 at 09:17, Maxime Ripard <maxime@cerno.tech> wrote:
> >
> > Hi!
> >
> > On Wed, Oct 28, 2020 at 01:42:20PM +0000, Dave Stevenson wrote:
> > > Hi Maxime
> > >
> > > On Fri, 25 Sep 2020 at 14:00, Maxime Ripard <maxime@cerno.tech> wrote:
> > > >
> > > > The FIFO between the pixelvalve and the HDMI controller runs at 2 pixels
> > > > per clock cycle, and cannot deal with odd timings.
> > > >
> > > > Let's reject any mode with such timings.
> > > >
> > > > Signed-off-by: Maxime Ripard <maxime@cerno.tech>
> >
> > Thanks for your review
> >
> > > It's unsupported due to the architecture rather than broken.
> >
> > Would you prefer s/broken/unsupported/ then?
> 
> If you needed to respin then yes, but it's not that big a deal.

It had a merge confict (with the 10/12 bit HDMI series) so I ended up
sending a new version with that fixed.

Maxime

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^ permalink raw reply	[flat|nested] 10+ messages in thread
end of thread, other threads:[~2020-10-30  8:25 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-25 13:00 [PATCH] drm/vc4: hdmi: Block odd horizontal timings Maxime Ripard
2020-09-25 13:00 ` Maxime Ripard
2020-10-28 13:42 ` Dave Stevenson
2020-10-28 13:42   ` Dave Stevenson
2020-10-29  9:17   ` Maxime Ripard
2020-10-29  9:17     ` Maxime Ripard
2020-10-29 10:49     ` Dave Stevenson
2020-10-29 10:49       ` Dave Stevenson
2020-10-29 12:26       ` Maxime Ripard
2020-10-29 12:26         ` Maxime Ripard

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