From: Jordan Crouse <jcrouse@codeaurora.org> To: Rob Clark <robdclark@gmail.com> Cc: dri-devel@lists.freedesktop.org, Rob Clark <robdclark@chromium.org>, Sean Paul <sean@poorly.run>, David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>, Eric Anholt <eric@anholt.net>, Emil Velikov <emil.velikov@collabora.com>, AngeloGioacchino Del Regno <kholk11@gmail.com>, Ben Dooks <ben.dooks@codethink.co.uk>, Jonathan Marek <jonathan@marek.ca>, Akhil P Oommen <akhilpo@codeaurora.org>, Sharat Masetty <smasetty@codeaurora.org>, "open list:DRM DRIVER FOR MSM ADRENO GPU" <linux-arm-msm@vger.kernel.org>, "open list:DRM DRIVER FOR MSM ADRENO GPU" <freedreno@lists.freedesktop.org>, open list <linux-kernel@vger.kernel.org> Subject: Re: [PATCH 05/14] drm/msm: Document and rename preempt_lock Date: Mon, 5 Oct 2020 08:22:26 -0600 [thread overview] Message-ID: <20201005142226.GD4204@jcrouse1-lnx.qualcomm.com> (raw) In-Reply-To: <20201004192152.3298573-6-robdclark@gmail.com> On Sun, Oct 04, 2020 at 12:21:37PM -0700, Rob Clark wrote: > From: Rob Clark <robdclark@chromium.org> > > Before adding another lock, give ring->lock a more descriptive name. Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> > Signed-off-by: Rob Clark <robdclark@chromium.org> > --- > drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++-- > drivers/gpu/drm/msm/adreno/a5xx_preempt.c | 12 ++++++------ > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 ++-- > drivers/gpu/drm/msm/msm_ringbuffer.c | 2 +- > drivers/gpu/drm/msm/msm_ringbuffer.h | 7 ++++++- > 5 files changed, 17 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > index c941c8138f25..543437a2186e 100644 > --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > @@ -36,7 +36,7 @@ void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, > OUT_RING(ring, upper_32_bits(shadowptr(a5xx_gpu, ring))); > } > > - spin_lock_irqsave(&ring->lock, flags); > + spin_lock_irqsave(&ring->preempt_lock, flags); > > /* Copy the shadow to the actual register */ > ring->cur = ring->next; > @@ -44,7 +44,7 @@ void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, > /* Make sure to wrap wptr if we need to */ > wptr = get_wptr(ring); > > - spin_unlock_irqrestore(&ring->lock, flags); > + spin_unlock_irqrestore(&ring->preempt_lock, flags); > > /* Make sure everything is posted before making a decision */ > mb(); > diff --git a/drivers/gpu/drm/msm/adreno/a5xx_preempt.c b/drivers/gpu/drm/msm/adreno/a5xx_preempt.c > index 7e04509c4e1f..183de1139eeb 100644 > --- a/drivers/gpu/drm/msm/adreno/a5xx_preempt.c > +++ b/drivers/gpu/drm/msm/adreno/a5xx_preempt.c > @@ -45,9 +45,9 @@ static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) > if (!ring) > return; > > - spin_lock_irqsave(&ring->lock, flags); > + spin_lock_irqsave(&ring->preempt_lock, flags); > wptr = get_wptr(ring); > - spin_unlock_irqrestore(&ring->lock, flags); > + spin_unlock_irqrestore(&ring->preempt_lock, flags); > > gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); > } > @@ -62,9 +62,9 @@ static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) > bool empty; > struct msm_ringbuffer *ring = gpu->rb[i]; > > - spin_lock_irqsave(&ring->lock, flags); > + spin_lock_irqsave(&ring->preempt_lock, flags); > empty = (get_wptr(ring) == ring->memptrs->rptr); > - spin_unlock_irqrestore(&ring->lock, flags); > + spin_unlock_irqrestore(&ring->preempt_lock, flags); > > if (!empty) > return ring; > @@ -132,9 +132,9 @@ void a5xx_preempt_trigger(struct msm_gpu *gpu) > } > > /* Make sure the wptr doesn't update while we're in motion */ > - spin_lock_irqsave(&ring->lock, flags); > + spin_lock_irqsave(&ring->preempt_lock, flags); > a5xx_gpu->preempt[ring->id]->wptr = get_wptr(ring); > - spin_unlock_irqrestore(&ring->lock, flags); > + spin_unlock_irqrestore(&ring->preempt_lock, flags); > > /* Set the address of the incoming preemption record */ > gpu_write64(gpu, REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO, > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index 8915882e4444..fc85f008d69d 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -65,7 +65,7 @@ static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) > OUT_RING(ring, upper_32_bits(shadowptr(a6xx_gpu, ring))); > } > > - spin_lock_irqsave(&ring->lock, flags); > + spin_lock_irqsave(&ring->preempt_lock, flags); > > /* Copy the shadow to the actual register */ > ring->cur = ring->next; > @@ -73,7 +73,7 @@ static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) > /* Make sure to wrap wptr if we need to */ > wptr = get_wptr(ring); > > - spin_unlock_irqrestore(&ring->lock, flags); > + spin_unlock_irqrestore(&ring->preempt_lock, flags); > > /* Make sure everything is posted before making a decision */ > mb(); > diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.c b/drivers/gpu/drm/msm/msm_ringbuffer.c > index 935bf9b1d941..1b6958e908dc 100644 > --- a/drivers/gpu/drm/msm/msm_ringbuffer.c > +++ b/drivers/gpu/drm/msm/msm_ringbuffer.c > @@ -46,7 +46,7 @@ struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id, > ring->memptrs_iova = memptrs_iova; > > INIT_LIST_HEAD(&ring->submits); > - spin_lock_init(&ring->lock); > + spin_lock_init(&ring->preempt_lock); > > snprintf(name, sizeof(name), "gpu-ring-%d", ring->id); > > diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.h b/drivers/gpu/drm/msm/msm_ringbuffer.h > index 0987d6bf848c..4956d1bc5d0e 100644 > --- a/drivers/gpu/drm/msm/msm_ringbuffer.h > +++ b/drivers/gpu/drm/msm/msm_ringbuffer.h > @@ -46,7 +46,12 @@ struct msm_ringbuffer { > struct msm_rbmemptrs *memptrs; > uint64_t memptrs_iova; > struct msm_fence_context *fctx; > - spinlock_t lock; > + > + /* > + * preempt_lock protects preemption and serializes wptr updates against > + * preemption. Can be aquired from irq context. > + */ > + spinlock_t preempt_lock; > }; > > struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id, > -- > 2.26.2 > -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
WARNING: multiple messages have this Message-ID (diff)
From: Jordan Crouse <jcrouse@codeaurora.org> To: Rob Clark <robdclark@gmail.com> Cc: Rob Clark <robdclark@chromium.org>, "open list:DRM DRIVER FOR MSM ADRENO GPU" <freedreno@lists.freedesktop.org>, Jonathan Marek <jonathan@marek.ca>, David Airlie <airlied@linux.ie>, "open list:DRM DRIVER FOR MSM ADRENO GPU" <linux-arm-msm@vger.kernel.org>, Sharat Masetty <smasetty@codeaurora.org>, Akhil P Oommen <akhilpo@codeaurora.org>, dri-devel@lists.freedesktop.org, open list <linux-kernel@vger.kernel.org>, Ben Dooks <ben.dooks@codethink.co.uk>, AngeloGioacchino Del Regno <kholk11@gmail.com>, Sean Paul <sean@poorly.run>, Emil Velikov <emil.velikov@collabora.com> Subject: Re: [PATCH 05/14] drm/msm: Document and rename preempt_lock Date: Mon, 5 Oct 2020 08:22:26 -0600 [thread overview] Message-ID: <20201005142226.GD4204@jcrouse1-lnx.qualcomm.com> (raw) In-Reply-To: <20201004192152.3298573-6-robdclark@gmail.com> On Sun, Oct 04, 2020 at 12:21:37PM -0700, Rob Clark wrote: > From: Rob Clark <robdclark@chromium.org> > > Before adding another lock, give ring->lock a more descriptive name. Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> > Signed-off-by: Rob Clark <robdclark@chromium.org> > --- > drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++-- > drivers/gpu/drm/msm/adreno/a5xx_preempt.c | 12 ++++++------ > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 ++-- > drivers/gpu/drm/msm/msm_ringbuffer.c | 2 +- > drivers/gpu/drm/msm/msm_ringbuffer.h | 7 ++++++- > 5 files changed, 17 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > index c941c8138f25..543437a2186e 100644 > --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > @@ -36,7 +36,7 @@ void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, > OUT_RING(ring, upper_32_bits(shadowptr(a5xx_gpu, ring))); > } > > - spin_lock_irqsave(&ring->lock, flags); > + spin_lock_irqsave(&ring->preempt_lock, flags); > > /* Copy the shadow to the actual register */ > ring->cur = ring->next; > @@ -44,7 +44,7 @@ void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, > /* Make sure to wrap wptr if we need to */ > wptr = get_wptr(ring); > > - spin_unlock_irqrestore(&ring->lock, flags); > + spin_unlock_irqrestore(&ring->preempt_lock, flags); > > /* Make sure everything is posted before making a decision */ > mb(); > diff --git a/drivers/gpu/drm/msm/adreno/a5xx_preempt.c b/drivers/gpu/drm/msm/adreno/a5xx_preempt.c > index 7e04509c4e1f..183de1139eeb 100644 > --- a/drivers/gpu/drm/msm/adreno/a5xx_preempt.c > +++ b/drivers/gpu/drm/msm/adreno/a5xx_preempt.c > @@ -45,9 +45,9 @@ static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) > if (!ring) > return; > > - spin_lock_irqsave(&ring->lock, flags); > + spin_lock_irqsave(&ring->preempt_lock, flags); > wptr = get_wptr(ring); > - spin_unlock_irqrestore(&ring->lock, flags); > + spin_unlock_irqrestore(&ring->preempt_lock, flags); > > gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); > } > @@ -62,9 +62,9 @@ static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) > bool empty; > struct msm_ringbuffer *ring = gpu->rb[i]; > > - spin_lock_irqsave(&ring->lock, flags); > + spin_lock_irqsave(&ring->preempt_lock, flags); > empty = (get_wptr(ring) == ring->memptrs->rptr); > - spin_unlock_irqrestore(&ring->lock, flags); > + spin_unlock_irqrestore(&ring->preempt_lock, flags); > > if (!empty) > return ring; > @@ -132,9 +132,9 @@ void a5xx_preempt_trigger(struct msm_gpu *gpu) > } > > /* Make sure the wptr doesn't update while we're in motion */ > - spin_lock_irqsave(&ring->lock, flags); > + spin_lock_irqsave(&ring->preempt_lock, flags); > a5xx_gpu->preempt[ring->id]->wptr = get_wptr(ring); > - spin_unlock_irqrestore(&ring->lock, flags); > + spin_unlock_irqrestore(&ring->preempt_lock, flags); > > /* Set the address of the incoming preemption record */ > gpu_write64(gpu, REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO, > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index 8915882e4444..fc85f008d69d 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -65,7 +65,7 @@ static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) > OUT_RING(ring, upper_32_bits(shadowptr(a6xx_gpu, ring))); > } > > - spin_lock_irqsave(&ring->lock, flags); > + spin_lock_irqsave(&ring->preempt_lock, flags); > > /* Copy the shadow to the actual register */ > ring->cur = ring->next; > @@ -73,7 +73,7 @@ static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) > /* Make sure to wrap wptr if we need to */ > wptr = get_wptr(ring); > > - spin_unlock_irqrestore(&ring->lock, flags); > + spin_unlock_irqrestore(&ring->preempt_lock, flags); > > /* Make sure everything is posted before making a decision */ > mb(); > diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.c b/drivers/gpu/drm/msm/msm_ringbuffer.c > index 935bf9b1d941..1b6958e908dc 100644 > --- a/drivers/gpu/drm/msm/msm_ringbuffer.c > +++ b/drivers/gpu/drm/msm/msm_ringbuffer.c > @@ -46,7 +46,7 @@ struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id, > ring->memptrs_iova = memptrs_iova; > > INIT_LIST_HEAD(&ring->submits); > - spin_lock_init(&ring->lock); > + spin_lock_init(&ring->preempt_lock); > > snprintf(name, sizeof(name), "gpu-ring-%d", ring->id); > > diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.h b/drivers/gpu/drm/msm/msm_ringbuffer.h > index 0987d6bf848c..4956d1bc5d0e 100644 > --- a/drivers/gpu/drm/msm/msm_ringbuffer.h > +++ b/drivers/gpu/drm/msm/msm_ringbuffer.h > @@ -46,7 +46,12 @@ struct msm_ringbuffer { > struct msm_rbmemptrs *memptrs; > uint64_t memptrs_iova; > struct msm_fence_context *fctx; > - spinlock_t lock; > + > + /* > + * preempt_lock protects preemption and serializes wptr updates against > + * preemption. Can be aquired from irq context. > + */ > + spinlock_t preempt_lock; > }; > > struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id, > -- > 2.26.2 > -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2020-10-05 14:22 UTC|newest] Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-10-04 19:21 [PATCH 00/14] drm/msm: de-struct_mutex-ification Rob Clark 2020-10-04 19:21 ` Rob Clark 2020-10-04 19:21 ` [PATCH 01/14] drm/msm: Use correct drm_gem_object_put() in fail case Rob Clark 2020-10-04 19:21 ` Rob Clark 2020-10-04 19:21 ` [PATCH 02/14] drm/msm: Drop chatty trace Rob Clark 2020-10-04 19:21 ` Rob Clark 2020-10-05 14:15 ` [Freedreno] " Jordan Crouse 2020-10-05 14:15 ` Jordan Crouse 2020-10-04 19:21 ` [PATCH 03/14] drm/msm: Move update_fences() Rob Clark 2020-10-04 19:21 ` Rob Clark 2020-10-05 14:16 ` [Freedreno] " Jordan Crouse 2020-10-05 14:16 ` Jordan Crouse 2020-10-04 19:21 ` [PATCH 04/14] drm/msm: Add priv->mm_lock to protect active/inactive lists Rob Clark 2020-10-04 19:21 ` Rob Clark 2020-10-04 22:15 ` Daniel Vetter 2020-10-04 22:15 ` Daniel Vetter 2020-10-05 0:10 ` Rob Clark 2020-10-05 0:10 ` Rob Clark 2020-10-05 14:19 ` [Freedreno] " Jordan Crouse 2020-10-05 14:19 ` Jordan Crouse 2020-10-04 19:21 ` [PATCH 05/14] drm/msm: Document and rename preempt_lock Rob Clark 2020-10-04 19:21 ` Rob Clark 2020-10-05 14:22 ` Jordan Crouse [this message] 2020-10-05 14:22 ` Jordan Crouse 2020-10-04 19:21 ` [PATCH 06/14] drm/msm: Protect ring->submits with it's own lock Rob Clark 2020-10-04 19:21 ` Rob Clark 2020-10-05 14:23 ` [Freedreno] " Jordan Crouse 2020-10-05 14:23 ` Jordan Crouse 2020-10-04 19:21 ` [PATCH 07/14] drm/msm: Refcount submits Rob Clark 2020-10-04 19:21 ` Rob Clark 2020-10-05 13:56 ` Daniel Vetter 2020-10-05 13:56 ` Daniel Vetter 2020-10-05 16:24 ` Rob Clark 2020-10-05 16:24 ` Rob Clark 2020-10-05 14:27 ` [Freedreno] " Jordan Crouse 2020-10-05 14:27 ` Jordan Crouse 2020-10-04 19:21 ` [PATCH 08/14] drm/msm: Remove obj->gpu Rob Clark 2020-10-04 19:21 ` Rob Clark 2020-10-05 14:28 ` [Freedreno] " Jordan Crouse 2020-10-05 14:28 ` Jordan Crouse 2020-10-04 19:21 ` [PATCH 09/14] drm/msm: Drop struct_mutex from the retire path Rob Clark 2020-10-04 19:21 ` Rob Clark 2020-10-05 14:29 ` [Freedreno] " Jordan Crouse 2020-10-05 14:29 ` Jordan Crouse 2020-10-04 19:21 ` [PATCH 10/14] drm/msm: Drop struct_mutex in free_object() path Rob Clark 2020-10-04 19:21 ` Rob Clark 2020-10-04 19:21 ` [PATCH 11/14] drm/msm: remove msm_gem_free_work Rob Clark 2020-10-04 19:21 ` Rob Clark 2020-10-04 19:21 ` [PATCH 12/14] drm/msm: drop struct_mutex in madvise path Rob Clark 2020-10-04 19:21 ` Rob Clark 2020-10-04 19:21 ` [PATCH 13/14] drm/msm: Drop struct_mutex in shrinker path Rob Clark 2020-10-04 19:21 ` Rob Clark 2020-10-05 9:24 ` Hillf Danton 2020-10-05 14:02 ` Daniel Vetter 2020-10-05 14:02 ` Daniel Vetter 2020-10-05 16:17 ` Kristian Høgsberg 2020-10-05 16:17 ` Kristian Høgsberg 2020-10-06 0:44 ` Hillf Danton 2020-10-06 3:40 ` Rob Clark 2020-10-06 3:40 ` Rob Clark 2020-10-06 8:24 ` Hillf Danton 2020-10-06 9:35 ` Daniel Vetter 2020-10-06 9:35 ` Daniel Vetter 2020-10-05 16:49 ` Rob Clark 2020-10-05 16:49 ` Rob Clark 2020-10-05 18:18 ` Daniel Vetter 2020-10-05 18:18 ` Daniel Vetter 2020-10-04 19:21 ` [PATCH 14/14] drm/msm: Don't implicit-sync if only a single ring Rob Clark 2020-10-04 19:21 ` Rob Clark 2020-10-05 16:24 ` [Freedreno] [PATCH 00/14] drm/msm: de-struct_mutex-ification Kristian Høgsberg 2020-10-05 16:24 ` Kristian Høgsberg 2020-10-05 18:20 ` Daniel Vetter 2020-10-05 18:20 ` Daniel Vetter 2020-10-06 3:25 ` Rob Clark 2020-10-06 3:25 ` Rob Clark
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