* [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits
2020-10-07 8:44 [PATCH v2 000/106] CCS driver Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 002/106] smiapp: Use CCS register flags Sakari Ailus
` (96 more replies)
2020-10-07 8:44 ` [PATCH v2 020/106] dt-bindings: nokia,smia: Fix link-frequencies documentation Sakari Ailus
` (8 subsequent siblings)
9 siblings, 97 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
Add register definitions of the MIPI CCS 1.1 standard.
The CCS driver makes extended use of device's capability registers that
are dependent on CCS version. This involves having an in-memory data
structure for limit and capability information, creating that data
structure and accessing it.
The register definitions as well as the definitions of this data structure
are generated from a text file using a Perl script. Do the generation here
and so avoid making manual, error-prone changes to the several generated
files.
Also add ccs-os.h header that contains Linux headers to be included.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/Makefile | 15 +-
drivers/media/i2c/smiapp/ccs-os.h | 15 +
drivers/media/i2c/smiapp/ccs-regs.txt | 1041 +++++++++++++++++++++++++
drivers/media/i2c/smiapp/mk-ccs-regs | 405 ++++++++++
4 files changed, 1475 insertions(+), 1 deletion(-)
create mode 100644 drivers/media/i2c/smiapp/ccs-os.h
create mode 100644 drivers/media/i2c/smiapp/ccs-regs.txt
create mode 100644 drivers/media/i2c/smiapp/mk-ccs-regs
diff --git a/drivers/media/i2c/smiapp/Makefile b/drivers/media/i2c/smiapp/Makefile
index 86f57a43f8e8..4638d1e14ebc 100644
--- a/drivers/media/i2c/smiapp/Makefile
+++ b/drivers/media/i2c/smiapp/Makefile
@@ -1,6 +1,19 @@
# SPDX-License-Identifier: GPL-2.0-only
smiapp-objs += smiapp-core.o smiapp-regs.o \
- smiapp-quirk.o smiapp-limits.o
+ smiapp-quirk.o smiapp-limits.o \
+ ccs-limits.o
obj-$(CONFIG_VIDEO_SMIAPP) += smiapp.o
ccflags-y += -I $(srctree)/drivers/media/i2c
+
+quiet_cmd_perlgen = PERL $(src)/mk-ccs-regs
+ cmd_perlgen = $(PERL) $(src)/mk-ccs-regs -e $(obj)/ccs-regs.h \
+ -L $(obj)/ccs-limits.h -l $(obj)/ccs-limits.c \
+ -c $(src)/ccs-regs.txt
+
+$(obj)/ccs-limits.c: $(src)/ccs-regs.txt
+ $(call cmd,perlgen)
+
+$(obj)/ccs-regs.h $(obj)/ccs-limits.h: $(obj)/ccs-limits.c
+
+clean-files: $(obj)/ccs-regs.h $(obj)/ccs-limits.h $(obj)/ccs-limits.c
diff --git a/drivers/media/i2c/smiapp/ccs-os.h b/drivers/media/i2c/smiapp/ccs-os.h
new file mode 100644
index 000000000000..f2445733f5d5
--- /dev/null
+++ b/drivers/media/i2c/smiapp/ccs-os.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright 2020 Intel Corporation */
+
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/limits.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+
+typedef struct device * printf_ctx;
+#define os_printf dev_dbg
+#define os_calloc(size) kvcalloc(1, size, GFP_KERNEL)
+#define os_free kvfree
+#define align2 ALIGN
diff --git a/drivers/media/i2c/smiapp/ccs-regs.txt b/drivers/media/i2c/smiapp/ccs-regs.txt
new file mode 100644
index 000000000000..9219b1421334
--- /dev/null
+++ b/drivers/media/i2c/smiapp/ccs-regs.txt
@@ -0,0 +1,1041 @@
+# Copyright (C) 2019--2020 Intel Corporation
+# SPDX-License-Identifier: BSD-3-Clause
+
+# register rflags
+# - f field LSB MSB rflags
+# - e enum value # after a field
+# - e enum value [LSB MSB]
+# - b bool bit
+# - l arg name min max elsize [discontig...]
+#
+# rflags
+# 8, 16, 32 register bits (default is 8)
+# v1.1 defined in version 1.1
+# f formula
+# float_ireal iReal or IEEE 754; 32 bits
+# ireal unsigned iReal
+
+# general status registers
+module_model_id 0x0000 16
+module_revision_number_major 0x0002 8
+frame_count 0x0005 8
+pixel_order 0x0006 8
+- e GRBG 0
+- e RGGB 1
+- e BGGR 2
+- e GBRG 3
+MIPI_CCS_version 0x0007 8
+- e v1_0 0x10
+- e v1_1 0x11
+- f major 4 7
+- f minor 0 3
+data_pedestal 0x0008 16
+module_manufacturer_id 0x000e 16
+module_revision_number_minor 0x0010 8
+module_date_year 0x0012 8
+module_date_month 0x0013 8
+module_date_day 0x0014 8
+module_date_phase 0x0015 8
+- f 0 2
+- e ts 0
+- e es 1
+- e cs 2
+- e mp 3
+sensor_model_id 0x0016 16
+sensor_revision_number 0x0018 8
+sensor_firmware_version 0x001a 8
+serial_number 0x001c 32
+sensor_manufacturer_id 0x0020 16
+sensor_revision_number_16 0x0022 16
+
+# frame format description registers
+frame_format_model_type 0x0040 8
+- e 2-byte 1
+- e 4-byte 2
+frame_format_model_subtype 0x0041 8
+- f rows 0 3
+- f columns 4 7
+frame_format_descriptor(n) 0x0042 16 f
+- l n 0 14 2
+- f pixels 0 11
+- f pcode 12 15
+- e embedded 1
+- e dummy_pixel 2
+- e black_pixel 3
+- e dark_pixel 4
+- e visible_pixel 5
+- e manuf_specific_0 8
+- e manuf_specific_1 9
+- e manuf_specific_2 10
+- e manuf_specific_3 11
+- e manuf_specific_4 12
+- e manuf_specific_5 13
+- e manuf_specific_6 14
+frame_format_descriptor_4(n) 0x0060 32 f
+- l n 0 7 4
+- f pixels 0 15
+- f pcode 28 31
+- e embedded 1
+- e dummy_pixel 2
+- e black_pixel 3
+- e dark_pixel 4
+- e visible_pixel 5
+- e manuf_specific_0 8
+- e manuf_specific_1 9
+- e manuf_specific_2 10
+- e manuf_specific_3 11
+- e manuf_specific_4 12
+- e manuf_specific_5 13
+- e manuf_specific_6 14
+
+# analog gain description registers
+analog_gain_capability 0x0080 16
+- e global 0
+- e alternate_global 2
+analog_gain_code_min 0x0084 16
+analog_gain_code_max 0x0086 16
+analog_gain_code_step 0x0088 16
+analog_gain_type 0x008a 16
+analog_gain_m0 0x008c 16
+analog_gain_c0 0x008e 16
+analog_gain_m1 0x0090 16
+analog_gain_c1 0x0092 16
+analog_linear_gain_min 0x0094 16 v1.1
+analog_linear_gain_max 0x0096 16 v1.1
+analog_linear_gain_step_size 0x0098 16 v1.1
+analog_exponential_gain_min 0x009a 16 v1.1
+analog_exponential_gain_max 0x009c 16 v1.1
+analog_exponential_gain_step_size 0x009e 16 v1.1
+
+# data format description registers
+data_format_model_type 0x00c0 8
+- e normal 1
+- e extended 2
+data_format_model_subtype 0x00c1 8
+- f rows 0 3
+- f columns 4 7
+data_format_descriptor(n) 0x00c2 16 f
+- l n 0 15 2
+- f compressed 0 7
+- f uncompressed 8 15
+
+# general set-up registers
+mode_select 0x0100 8
+- e software_standby 0
+- e streaming 1
+image_orientation 0x0101 8
+- b horizontal_mirror 0
+- b vertical_flip 1
+software_reset 0x0103 8
+- e off 0
+- e on 1
+grouped_parameter_hold 0x0104 8
+mask_corrupted_frames 0x0105 8
+- e allow 0
+- e mask 1
+fast_standby_ctrl 0x0106 8
+- e complete_frames 0
+- e frame_truncation 1
+CCI_address_ctrl 0x0107 8
+2nd_CCI_if_ctrl 0x0108 8
+- b enable 0
+- b ack 1
+2nd_CCI_address_ctrl 0x0109 8
+CSI_channel_identifier 0x0110 8
+CSI_signaling_mode 0x0111 8
+- e csi_2_dphy 2
+- e csi_2_cphy 3
+CSI_data_format 0x0112 16
+CSI_lane_mode 0x0114 8
+DPCM_Frame_DT 0x011d 8
+Bottom_embedded_data_DT 0x011e 8
+Bottom_embedded_data_VC 0x011f 8
+
+gain_mode 0x0120 8
+- e global 0
+- e alternate 1
+ADC_bit_depth 0x0121 8
+emb_data_ctrl 0x0122 v1.1
+- b raw8_packing_for_raw16 0
+- b raw10_packing_for_raw20 1
+- b raw12_packing_for_raw24 2
+
+GPIO_TRIG_mode 0x0130 8
+extclk_frequency_mhz 0x0136 16 ireal
+temp_sensor_ctrl 0x0138 8
+- b enable 0
+temp_sensor_mode 0x0139 8
+temp_sensor_output 0x013a 8
+
+# integration time registers
+fine_integration_time 0x0200 16
+coarse_integration_time 0x0202 16
+
+# analog gain registers
+analog_gain_code_global 0x0204 16
+analog_linear_gain_global 0x0206 16 v1.1
+analog_exponential_gain_global 0x0208 16 v1.1
+
+# digital gain registers
+digital_gain_global 0x020e 16
+
+# hdr control registers
+Short_analog_gain_global 0x0216 16
+Short_digital_gain_global 0x0218 16
+
+HDR_mode 0x0220 8
+- b enabled 0
+- b separate_analog_gain 1
+- b upscaling 2
+- b reset_sync 3
+- b timing_mode 4
+- b exposure_ctrl_direct 5
+- b separate_digital_gain 6
+HDR_resolution_reduction 0x0221 8
+- f row 0 3
+- f column 4 7
+Exposure_ratio 0x0222 8
+HDR_internal_bit_depth 0x0223 8
+Direct_short_integration_time 0x0224 16
+Short_analog_linear_gain_global 0x0226 16 v1.1
+Short_analog_exponential_gain_global 0x0228 16 v1.1
+
+# clock set-up registers
+vt_pix_clk_div 0x0300 16
+vt_sys_clk_div 0x0302 16
+pre_pll_clk_div 0x0304 16
+#vt_pre_pll_clk_div 0x0304 16
+pll_multiplier 0x0306 16
+#vt_pll_multiplier 0x0306 16
+op_pix_clk_div 0x0308 16
+op_sys_clk_div 0x030a 16
+op_pre_pll_clk_div 0x030c 16
+op_pll_multiplier 0x031e 16
+pll_mode 0x0310 8
+- f 0 0
+- e single 0
+- e dual 1
+op_pix_clk_div_rev 0x0312 16 v1.1
+op_sys_clk_div_rev 0x0314 16 v1.1
+
+# frame timing registers
+frame_length_lines 0x0340 16
+line_length_pck 0x0342 16
+
+# image size registers
+x_addr_start 0x0344 16
+y_addr_start 0x0346 16
+x_addr_end 0x0348 16
+y_addr_end 0x034a 16
+x_output_size 0x034c 16
+y_output_size 0x034e 16
+
+# timing mode registers
+Frame_length_ctrl 0x0350 8
+- b automatic 0
+Timing_mode_ctrl 0x0352 8
+- b manual_readout 0
+- b delayed_exposure 1
+Start_readout_rs 0x0353 8
+- b manual_readout_start 0
+Frame_margin 0x0354 16
+
+# sub-sampling registers
+x_even_inc 0x0380 16
+x_odd_inc 0x0382 16
+y_even_inc 0x0384 16
+y_odd_inc 0x0386 16
+
+# monochrome readout registers
+monochrome_en 0x0390 v1.1
+- e enabled 0
+
+# image scaling registers
+Scaling_mode 0x0400 16
+- e no_scaling 0
+- e horizontal 1
+scale_m 0x0404 16
+scale_n 0x0406 16
+digital_crop_x_offset 0x0408 16
+digital_crop_y_offset 0x040a 16
+digital_crop_image_width 0x040c 16
+digital_crop_image_height 0x040e 16
+
+# image compression registers
+compression_mode 0x0500 16
+- e none 0
+- e dpcm_pcm_simple 1
+
+# test pattern registers
+test_pattern_mode 0x0600 16
+- e none 0
+- e solid_color 1
+- e color_bars 2
+- e fade_to_grey 3
+- e pn9 4
+- e color_tile 5
+test_data_red 0x0602 16
+test_data_greenR 0x0604 16
+test_data_blue 0x0606 16
+test_data_greenB 0x0608 16
+value_step_size_smooth 0x060a 8
+value_step_size_quantised 0x060b 8
+
+# phy configuration registers
+tclk_post 0x0800 8
+ths_prepare 0x0801 8
+ths_zero_min 0x0802 8
+ths_trail 0x0803 8
+tclk_trail_min 0x0804 8
+tclk_prepare 0x0805 8
+tclk_zero 0x0806 8
+tlpx 0x0807 8
+phy_ctrl 0x0808 8
+- e auto 0
+- e UI 1
+- e manual 2
+tclk_post_ex 0x080a 16
+ths_prepare_ex 0x080c 16
+ths_zero_min_ex 0x080e 16
+ths_trail_ex 0x0810 16
+tclk_trail_min_ex 0x0812 16
+tclk_prepare_ex 0x0814 16
+tclk_zero_ex 0x0816 16
+tlpx_ex 0x0818 16
+
+# link rate register
+requested_link_rate 0x0820 32 u16.16
+
+# equalization control registers
+DPHY_equalization_mode 0x0824 8 v1.1
+- b eq2 0
+PHY_equalization_ctrl 0x0825 8 v1.1
+- b enable 0
+
+# d-phy preamble control registers
+DPHY_preamble_ctrl 0x0826 8 v1.1
+- b enable 0
+DPHY_preamble_length 0x0826 8 v1.1
+
+# d-phy spread spectrum control registers
+PHY_SSC_ctrl 0x0828 8 v1.1
+- b enable 0
+
+# manual lp control register
+manual_LP_ctrl 0x0829 8 v1.1
+- b enable 0
+
+# additional phy configuration registers
+twakeup 0x082a v1.1
+tinit 0x082b v1.1
+ths_exit 0x082c v1.1
+ths_exit_ex 0x082e 16 v1.1
+
+# phy calibration configuration registers
+PHY_periodic_calibration_ctrl 0x0830 8
+- b frame_blanking 0
+PHY_periodic_calibration_interval 0x0831 8
+PHY_init_calibration_ctrl 0x0832 8
+- b stream_start 0
+DPHY_calibration_mode 0x0833 8 v1.1
+- b also_alternate 0
+CPHY_calibration_mode 0x0834 8 v1.1
+- e format_1 0
+- e format_2 1
+- e format_3 2
+t3_calpreamble_length 0x0835 8 v1.1
+t3_calpreamble_length_per 0x0836 8 v1.1
+t3_calaltseq_length 0x0837 8 v1.1
+t3_calaltseq_length_per 0x0838 8 v1.1
+FM2_init_seed 0x083a 16 v1.1
+t3_caludefseq_length 0x083c 16 v1.1
+t3_caludefseq_length_per 0x083e 16 v1.1
+
+# c-phy manual control registers
+TGR_Preamble_Length 0x0841 8
+- b preamable_prog_seq 7
+- f begin_preamble_length 0 5
+TGR_Post_Length 0x0842 8
+- f post_length 0 4
+TGR_Preamble_Prog_Sequence(n2) 0x0843
+- l n2 0 6 1
+- f symbol_n_1 3 5
+- f symbol_n 0 2
+t3_prepare 0x084e 16
+t3_lpx 0x0850 16
+
+# alps control register
+ALPS_ctrl 0x085a 8
+- b lvlp_dphy 0
+- b lvlp_cphy 1
+- b alp_cphy 2
+
+# lrte control registers
+TX_REG_CSI_EPD_EN_SSP_cphy 0x0860 16
+TX_REG_CSI_EPD_OP_SLP_cphy 0x0862 16
+TX_REG_CSI_EPD_EN_SSP_dphy 0x0864 16
+TX_REG_CSI_EPD_OP_SLP_dphy 0x0866 16
+TX_REG_CSI_EPD_MISC_OPTION_cphy 0x0868 v1.1
+TX_REG_CSI_EPD_MISC_OPTION_dphy 0x0869 v1.1
+
+# scrambling control registers
+Scrambling_ctrl 0x0870
+- b enabled 0
+- f 2 3
+- e 1_seed_cphy 0
+- e 4_seed_cphy 3
+lane_seed_value(seed, lane) 0x0872 16
+- l seed 0 3 0x10
+- l lane 0 7 0x2
+
+# usl control registers
+TX_USL_REV_ENTRY 0x08c0 16 v1.1
+TX_USL_REV_Clock_Counter 0x08c2 16 v1.1
+TX_USL_REV_LP_Counter 0x08c4 16 v1.1
+TX_USL_REV_Frame_Counter 0x08c6 16 v1.1
+TX_USL_REV_Chronological_Timer 0x08c8 16 v1.1
+TX_USL_FWD_ENTRY 0x08ca 16 v1.1
+TX_USL_GPIO 0x08cc 16 v1.1
+TX_USL_Operation 0x08ce 16 v1.1
+- b reset 0
+TX_USL_ALP_ctrl 0x08d0 16 v1.1
+- b clock_pause 0
+TX_USL_APP_BTA_ACK_TIMEOUT 0x08d2 16 v1.1
+TX_USL_SNS_BTA_ACK_TIMEOUT 0x08d2 16 v1.1
+USL_Clock_Mode_d_ctrl 0x08d2 v1.1
+- b cont_clock_standby 0
+- b cont_clock_vblank 1
+- b cont_clock_hblank 2
+
+# binning configuration registers
+binning_mode 0x0900 8
+binning_type 0x0901 8
+binning_weighting 0x0902 8
+
+# data transfer interface registers
+data_transfer_if_1_ctrl 0x0a00 8
+- b enable 0
+- b write 1
+- b clear_error 2
+data_transfer_if_1_status 0x0a01 8
+- b read_if_ready 0
+- b write_if_ready 1
+- b data_corrupted 2
+- b improper_if_usage 3
+data_transfer_if_1_page_select 0x0a02 8
+data_transfer_if_1_data(p) 0x0a04 8 f
+- l p 0 63 1
+
+# image processing and sensor correction configuration registers
+shading_correction_en 0x0b00 8
+- b enable 0
+luminance_correction_level 0x0b01 8
+green_imbalance_filter_en 0x0b02 8
+- b enable 0
+mapped_defect_correct_en 0x0b05 8
+- b enable 0
+single_defect_correct_en 0x0b06 8
+- b enable 0
+dynamic_couplet_correct_en 0x0b08 8
+- b enable 0
+combined_defect_correct_en 0x0b0a 8
+- b enable 0
+module_specific_correction_en 0x0b0c 8
+- b enable 0
+dynamic_triplet_defect_correct_en 0x0b13 8
+- b enable 0
+NF_ctrl 0x0b15 8
+- b luma 0
+- b chroma 1
+- b combined 2
+
+# optical black pixel readout registers
+OB_readout_control 0x0b30 8
+- b enable 0
+- b interleaving 1
+OB_virtual_channel 0x0b31 8
+OB_DT 0x0b32 8
+OB_data_format 0x0b33 8
+
+# color temperature feedback registers
+color_temperature 0x0b8c 16
+absolute_gain_greenr 0x0b8e 16
+absolute_gain_red 0x0b90 16
+absolute_gain_blue 0x0b92 16
+absolute_gain_greenb 0x0b94 16
+
+# cfa conversion registers
+CFA_conversion_ctrl 0x0ba0 v1.1
+- b bayer_conversion_enable 0
+
+# flash strobe and sa strobe control registers
+flash_strobe_adjustment 0x0c12 8
+flash_strobe_start_point 0x0c14 16
+tflash_strobe_delay_rs_ctrl 0x0c16 16
+tflash_strobe_width_high_rs_ctrl 0x0c18 16
+flash_mode_rs 0x0c1a 8
+- b continuous 0
+- b truncate 1
+- b async 3
+flash_trigger_rs 0x0c1b 8
+flash_status 0x0c1c 8
+- b retimed 0
+sa_strobe_mode 0x0c1d 8
+- b continuous 0
+- b truncate 1
+- b async 3
+- b adjust_edge 4
+sa_strobe_start_point 0x0c1e 16
+tsa_strobe_delay_ctrl 0x0c20 16
+tsa_strobe_width_ctrl 0x0c22 16
+sa_strobe_trigger 0x0c24 8
+sa_strobe_status 0x0c25 8
+- b retimed 0
+tSA_strobe_re_delay_ctrl 0x0c30 16
+tSA_strobe_fe_delay_ctrl 0x0c32 16
+
+# pdaf control registers
+PDAF_ctrl 0x0d00 16
+- b enable 0
+- b processed 1
+- b interleaved 2
+- b visible_pdaf_correction 3
+PDAF_VC 0x0d02 8
+PDAF_DT 0x0d03 8
+pd_x_addr_start 0x0d04 16
+pd_y_addr_start 0x0d06 16
+pd_x_addr_end 0x0d08 16
+pd_y_addr_end 0x0d0a 16
+
+# bracketing interface configuration registers
+bracketing_LUT_ctrl 0x0e00 8
+bracketing_LUT_mode 0x0e01 8
+- b continue_streaming 0
+- b loop_mode 1
+bracketing_LUT_entry_ctrl 0x0e02 8
+bracketing_LUT_frame(n) 0x0e10 v1.1 f
+- l n 0 0xef 1
+
+# integration time and gain parameter limit registers
+integration_time_capability 0x1000 16
+- b fine 0
+coarse_integration_time_min 0x1004 16
+coarse_integration_time_max_margin 0x1006 16
+fine_integration_time_min 0x1008 16
+fine_integration_time_max_margin 0x100a 16
+
+# digital gain parameter limit registers
+digital_gain_capability 0x1081
+- e none 0
+- e global 2
+digital_gain_min 0x1084 16
+digital_gain_max 0x1086 16
+digital_gain_step_size 0x1088 16
+
+# data pedestal capability registers
+Pedestal_capability 0x10e0 8 v1.1
+
+# adc capability registers
+ADC_capability 0x10f0 8
+- b bit_depth_ctrl 0
+ADC_bit_depth_capability 0x10f4 32 v1.1
+
+# video timing parameter limit registers
+min_ext_clk_freq_mhz 0x1100 32 float_ireal
+max_ext_clk_freq_mhz 0x1104 32 float_ireal
+min_pre_pll_clk_div 0x1108 16
+# min_vt_pre_pll_clk_div 0x1108 16
+max_pre_pll_clk_div 0x110a 16
+# max_vt_pre_pll_clk_div 0x110a 16
+min_pll_ip_clk_freq_mhz 0x110c 32 float_ireal
+# min_vt_pll_ip_clk_freq_mhz 0x110c 32 float_ireal
+max_pll_ip_clk_freq_mhz 0x1110 32 float_ireal
+# max_vt_pll_ip_clk_freq_mhz 0x1110 32 float_ireal
+min_pll_multiplier 0x1114 16
+# min_vt_pll_multiplier 0x1114 16
+max_pll_multiplier 0x1116 16
+# max_vt_pll_multiplier 0x1116 16
+min_pll_op_clk_freq_mhz 0x1118 32 float_ireal
+max_pll_op_clk_freq_mhz 0x111c 32 float_ireal
+
+# video timing set-up capability registers
+min_vt_sys_clk_div 0x1120 16
+max_vt_sys_clk_div 0x1122 16
+min_vt_sys_clk_freq_mhz 0x1124 32 float_ireal
+max_vt_sys_clk_freq_mhz 0x1128 32 float_ireal
+min_vt_pix_clk_freq_mhz 0x112c 32 float_ireal
+max_vt_pix_clk_freq_mhz 0x1130 32 float_ireal
+min_vt_pix_clk_div 0x1134 16
+max_vt_pix_clk_div 0x1136 16
+clock_calculation 0x1138
+- b lane_speed 0
+- b link_decoupled 1
+- b dual_pll_op_sys_ddr 2
+- b dual_pll_op_pix_ddr 3
+num_of_vt_lanes 0x1139
+num_of_op_lanes 0x113a
+op_bits_per_lane 0x113b 8 v1.1
+
+# frame timing parameter limits
+min_frame_length_lines 0x1140 16
+max_frame_length_lines 0x1142 16
+min_line_length_pck 0x1144 16
+max_line_length_pck 0x1146 16
+min_line_blanking_pck 0x1148 16
+min_frame_blanking_lines 0x114a 16
+min_line_length_pck_step_size 0x114c
+timing_mode_capability 0x114d
+- b auto_frame_length 0
+- b rolling_shutter_manual_readout 2
+- b delayed_exposure_start 3
+- b manual_exposure_embedded_data 4
+frame_margin_max_value 0x114e 16
+frame_margin_min_value 0x1150
+gain_delay_type 0x1151
+- e fixed 0
+- e variable 1
+
+# output clock set-up capability registers
+min_op_sys_clk_div 0x1160 16
+max_op_sys_clk_div 0x1162 16
+min_op_sys_clk_freq_mhz 0x1164 32 float_ireal
+max_op_sys_clk_freq_mhz 0x1168 32 float_ireal
+min_op_pix_clk_div 0x116c 16
+max_op_pix_clk_div 0x116e 16
+min_op_pix_clk_freq_mhz 0x1170 32 float_ireal
+max_op_pix_clk_freq_mhz 0x1174 32 float_ireal
+
+# image size parameter limit registers
+x_addr_min 0x1180 16
+y_addr_min 0x1182 16
+x_addr_max 0x1184 16
+y_addr_max 0x1186 16
+min_x_output_size 0x1188 16
+min_y_output_size 0x118a 16
+max_x_output_size 0x118c 16
+max_y_output_size 0x118e 16
+
+x_addr_start_div_constant 0x1190 v1.1
+y_addr_start_div_constant 0x1191 v1.1
+x_addr_end_div_constant 0x1192 v1.1
+y_addr_end_div_constant 0x1193 v1.1
+x_size_div 0x1194 v1.1
+y_size_div 0x1195 v1.1
+x_output_div 0x1196 v1.1
+y_output_div 0x1197 v1.1
+non_flexible_resolution_support 0x1198 v1.1
+- b new_pix_addr 0
+- b new_output_res 1
+- b output_crop_no_pad 2
+- b output_size_lane_dep 3
+
+min_op_pre_pll_clk_div 0x11a0 16
+max_op_pre_pll_clk_div 0x11a2 16
+min_op_pll_ip_clk_freq_mhz 0x11a4 32 float_ireal
+max_op_pll_ip_clk_freq_mhz 0x11a8 32 float_ireal
+min_op_pll_multiplier 0x11ac 16
+max_op_pll_multiplier 0x11ae 16
+min_op_pll_op_clk_freq_mhz 0x11b0 32 float_ireal
+max_op_pll_op_clk_freq_mhz 0x11b4 32 float_ireal
+clock_tree_pll_capability 0x11b8 8
+- b dual_pll 0
+- b single_pll 1
+- b ext_divider 2
+- b flexible_op_pix_clk_div 3
+clock_capa_type_capability 0x11b9 v1.1
+- b ireal 0
+
+# sub-sampling parameters limit registers
+min_even_inc 0x11c0 16
+min_odd_inc 0x11c2 16
+max_even_inc 0x11c4 16
+max_odd_inc 0x11c6 16
+aux_subsamp_capability 0x11c8 v1.1
+- b factor_power_of_2 1
+aux_subsamp_mono_capability 0x11c9 v1.1
+- b factor_power_of_2 1
+monochrome_capability 0x11ca v1.1
+- e inc_odd 0
+- e inc_even 1
+pixel_readout_capability 0x11cb v1.1
+- e bayer 0
+- e monochrome 1
+- e bayer_and_mono 2
+min_even_inc_mono 0x11cc 16 v1.1
+max_even_inc_mono 0x11ce 16 v1.1
+min_odd_inc_mono 0x11d0 16 v1.1
+max_odd_inc_mono 0x11d2 16 v1.1
+min_even_inc_bc2 0x11d4 16 v1.1
+max_even_inc_bc2 0x11d6 16 v1.1
+min_odd_inc_bc2 0x11d8 16 v1.1
+max_odd_inc_bc2 0x11da 16 v1.1
+min_even_inc_mono_bc2 0x11dc 16 v1.1
+max_even_inc_mono_bc2 0x11de 16 v1.1
+min_odd_inc_mono_bc2 0x11f0 16 v1.1
+max_odd_inc_mono_bc2 0x11f2 16 v1.1
+
+# image scaling limit parameters
+scaling_capability 0x1200 16
+- e none 0
+- e horizontal 1
+- e reserved 2
+scaler_m_min 0x1204 16
+scaler_m_max 0x1206 16
+scaler_n_min 0x1208 16
+scaler_n_max 0x120a 16
+digital_crop_capability 0x120e
+- e none 0
+- e input_crop 1
+
+# hdr limit registers
+hdr_capability_1 0x1210
+- b 2x2_binning 0
+- b combined_analog_gain 1
+- b separate_analog_gain 2
+- b upscaling 3
+- b reset_sync 4
+- b direct_short_exp_timing 5
+- b direct_short_exp_synthesis 6
+min_hdr_bit_depth 0x1211
+hdr_resolution_sub_types 0x1212
+hdr_resolution_sub_type(n) 0x1213
+- l n 0 1 1
+- f row 0 3
+- f column 4 7
+hdr_capability_2 0x121b
+- b combined_digital_gain 0
+- b separate_digital_gain 1
+- b timing_mode 3
+- b synthesis_mode 4
+max_hdr_bit_depth 0x121c
+
+# usl capability register
+usl_support_capability 0x1230 v1.1
+- b clock_tree 0
+- b rev_clock_tree 1
+- b rev_clock_calc 2
+usl_clock_mode_d_capability 0x1231 v1.1
+- b cont_clock_standby 0
+- b cont_clock_vblank 1
+- b cont_clock_hblank 2
+- b noncont_clock_standby 3
+- b noncont_clock_vblank 4
+- b noncont_clock_hblank 5
+min_op_sys_clk_div_rev 0x1234 v1.1
+max_op_sys_clk_div_rev 0x1236 v1.1
+min_op_pix_clk_div_rev 0x1238 v1.1
+max_op_pix_clk_div_rev 0x123a v1.1
+min_op_sys_clk_freq_rev_mhz 0x123c 32 v1.1 float_ireal
+max_op_sys_clk_freq_rev_mhz 0x1240 32 v1.1 float_ireal
+min_op_pix_clk_freq_rev_mhz 0x1244 32 v1.1 float_ireal
+max_op_pix_clk_freq_rev_mhz 0x1248 32 v1.1 float_ireal
+max_bitrate_rev_d_mode_mbps 0x124c 32 v1.1 ireal
+max_symrate_rev_c_mode_msps 0x1250 32 v1.1 ireal
+
+# image compression capability registers
+compression_capability 0x1300
+- b dpcm_pcm_simple 0
+
+# test mode capability registers
+test_mode_capability 0x1310 16
+- b solid_color 0
+- b color_bars 1
+- b fade_to_grey 2
+- b pn9 3
+- b color_tile 5
+pn9_data_format1 0x1312
+pn9_data_format2 0x1313
+pn9_data_format3 0x1314
+pn9_data_format4 0x1315
+pn9_misc_capability 0x1316
+- f num_pixels 0 2
+- b compression 3
+test_pattern_capability 0x1317 v1.1
+- b no_repeat 1
+pattern_size_div_m1 0x1318 v1.1
+
+# fifo capability registers
+fifo_support_capability 0x1502
+- e none 0
+- e derating 1
+- e derating_overrating 2
+
+# csi-2 capability registers
+phy_ctrl_capability 0x1600
+- b auto_phy_ctl 0
+- b ui_phy_ctl 1
+- b dphy_time_ui_reg_1_ctl 2
+- b dphy_time_ui_reg_2_ctl 3
+- b dphy_time_ctl 4
+- b dphy_ext_time_ui_reg_1_ctl 5
+- b dphy_ext_time_ui_reg_2_ctl 6
+- b dphy_ext_time_ctl 7
+csi_dphy_lane_mode_capability 0x1601
+- b 1_lane 0
+- b 2_lane 1
+- b 3_lane 2
+- b 4_lane 3
+- b 5_lane 4
+- b 6_lane 5
+- b 7_lane 6
+- b 8_lane 7
+csi_signaling_mode_capability 0x1602
+- b csi_dphy 2
+- b csi_cphy 3
+fast_standby_capability 0x1603
+- e no_frame_truncation 0
+- e frame_truncation 1
+csi_address_control_capability 0x1604
+- b cci_addr_change 0
+- b 2nd_cci_addr 1
+- b sw_changeable_2nd_cci_addr 2
+data_type_capability 0x1605
+- b dpcm_programmable 0
+- b bottom_embedded_dt_programmable 1
+- b bottom_embedded_vc_programmable 2
+- b ext_vc_range 3
+csi_cphy_lane_mode_capability 0x1606
+- b 1_lane 0
+- b 2_lane 1
+- b 3_lane 2
+- b 4_lane 3
+- b 5_lane 4
+- b 6_lane 5
+- b 7_lane 6
+- b 8_lane 7
+emb_data_capability 0x1607 v1.1
+- b two_bytes_per_raw16 0
+- b two_bytes_per_raw20 1
+- b two_bytes_per_raw24 2
+- b no_one_byte_per_raw16 3
+- b no_one_byte_per_raw20 4
+- b no_one_byte_per_raw24 5
+max_per_lane_bitrate_lane_d_mode_mbps(n) 0x1608 32 ireal
+- l n 0 7 4 4,0x32
+temp_sensor_capability 0x1618
+- b supported 0
+- b CCS_format 1
+- b reset_0x80 2
+max_per_lane_bitrate_lane_c_mode_mbps(n) 0x161a 32 ireal
+- l n 0 7 4 4,0x30
+dphy_equalization_capability 0x162b
+- b equalization_ctrl 0
+- b eq1 1
+- b eq2 2
+cphy_equalization_capability 0x162c
+- b equalization_ctrl 0
+dphy_preamble_capability 0x162d
+- b preamble_seq_ctrl 0
+dphy_ssc_capability 0x162e
+- b supported 0
+cphy_calibration_capability 0x162f
+- b manual 0
+- b manual_streaming 1
+- b format_1_ctrl 2
+- b format_2_ctrl 3
+- b format_3_ctrl 4
+dphy_calibration_capability 0x1630
+- b manual 0
+- b manual_streaming 1
+- b alternate_seq 2
+phy_ctrl_capability_2 0x1631
+- b tgr_length 0
+- b tgr_preamble_prog_seq 1
+- b extra_cphy_manual_timing 2
+- b clock_based_manual_cdphy 3
+- b clock_based_manual_dphy 4
+- b clock_based_manual_cphy 5
+- b manual_lp_dphy 6
+- b manual_lp_cphy 7
+lrte_cphy_capability 0x1632
+- b pdq_short 0
+- b spacer_short 1
+- b pdq_long 2
+- b spacer_long 3
+- b spacer_no_pdq 4
+lrte_dphy_capability 0x1633
+- b pdq_short_opt1 0
+- b spacer_short_opt1 1
+- b pdq_long_opt1 2
+- b spacer_long_opt1 3
+- b spacer_short_opt2 4
+- b spacer_long_opt2 5
+- b spacer_no_pdq_opt1 6
+- b spacer_variable_opt2 7
+alps_capability_dphy 0x1634
+- e lvlp_not_supported 0 0x3
+- e lvlp_supported 1 0x3
+- e controllable_lvlp 2 0x3
+alps_capability_cphy 0x1635
+- e lvlp_not_supported 0 0x3
+- e lvlp_supported 1 0x3
+- e controllable_lvlp 2 0x3
+- e alp_not_supported 0xc 0xc
+- e alp_supported 0xd 0xc
+- e controllable_alp 0xe 0xc
+scrambling_capability 0x1636
+- b scrambling_supported 0
+- f max_seeds_per_lane_c 1 2
+- e 1 0
+- e 4 3
+- f num_seed_regs 3 5
+- e 0 0
+- e 1 1
+- e 4 4
+- b num_seed_per_lane 6
+dphy_manual_constant 0x1637
+cphy_manual_constant 0x1638
+CSI2_interface_capability_misc 0x1639 v1.1
+- b eotp_short_pkt_opt2 0
+PHY_ctrl_capability_3 0x165c v1.1
+- b dphy_timing_not_multiple 0
+- b dphy_min_timing_value_1 1
+- b twakeup_supported 2
+- b tinit_supported 3
+- b ths_exit_supported 4
+- b cphy_timing_not_multiple 5
+- b cphy_min_timing_value_1 6
+dphy_sf 0x165d v1.1
+cphy_sf 0x165e v1.1
+- f twakeup 0 3
+- f tinit 4 7
+dphy_limits_1 0x165f v1.1
+- f ths_prepare 0 3
+- f ths_zero 4 7
+dphy_limits_2 0x1660 v1.1
+- f ths_trail 0 3
+- f tclk_trail_min 4 7
+dphy_limits_3 0x1661 v1.1
+- f tclk_prepare 0 3
+- f tclk_zero 4 7
+dphy_limits_4 0x1662 v1.1
+- f tclk_post 0 3
+- f tlpx 4 7
+dphy_limits_5 0x1663 v1.1
+- f ths_exit 0 3
+- f twakeup 4 7
+dphy_limits_6 0x1664 v1.1
+- f tinit 0 3
+cphy_limits_1 0x1665 v1.1
+- f t3_prepare_max 0 3
+- f t3_lpx_max 4 7
+cphy_limits_2 0x1666 v1.1
+- f ths_exit_max 0 3
+- f twakeup_max 4 7
+cphy_limits_3 0x1667 v1.1
+- f tinit_max 0 3
+
+# binning capability registers
+min_frame_length_lines_bin 0x1700 16
+max_frame_length_lines_bin 0x1702 16
+min_line_length_pck_bin 0x1704 16
+max_line_length_pck_bin 0x1706 16
+min_line_blanking_pck_bin 0x1708 16
+fine_integration_time_min_bin 0x170a 16
+fine_integration_time_max_margin_bin 0x170c 16
+binning_capability 0x1710
+- e unsupported 0
+- e binning_then_subsampling 1
+- e subsampling_then_binning 2
+binning_weighting_capability 0x1711
+- b averaged 0
+- b summed 1
+- b bayer_corrected 2
+- b module_specific_weight 3
+binning_sub_types 0x1712
+binning_sub_type(n) 0x1713
+- l n 0 63 1
+- f row 0 3
+- f column 4 7
+binning_weighting_mono_capability 0x1771 v1.1
+- b averaged 0
+- b summed 1
+- b bayer_corrected 2
+- b module_specific_weight 3
+binning_sub_types_mono 0x1772 v1.1
+binning_sub_type_mono(n) 0x1773 v1.1 f
+- l n 0 63 1
+
+# data transfer interface capability registers
+data_transfer_if_capability 0x1800
+- b supported 0
+- b polling 2
+
+# sensor correction capability registers
+shading_correction_capability 0x1900
+- b color_shading 0
+- b luminance_correction 1
+green_imbalance_capability 0x1901
+- b supported 0
+module_specific_correction_capability 0x1903
+defect_correction_capability 0x1904 16
+- b mapped_defect 0
+- b dynamic_couplet 2
+- b dynamic_single 5
+- b combined_dynamic 8
+defect_correction_capability_2 0x1906 16
+- b dynamic_triplet 3
+nf_capability 0x1908
+- b luma 0
+- b chroma 1
+- b combined 2
+
+# optical black readout capability registers
+ob_readout_capability 0x1980
+- b controllable_readout 0
+- b visible_pixel_readout 1
+- b different_vc_readout 2
+- b different_dt_readout 3
+- b prog_data_format 4
+
+# color feedback capability registers
+color_feedback_capability 0x1987
+- b kelvin 0
+- b awb_gain 1
+
+# cfa pattern capability registers
+CFA_pattern_capability 0x1990 v1.1
+- e bayer 0
+- e monochrome 1
+- e 4x4_quad_bayer 2
+- e vendor_specific 3
+CFA_pattern_conversion_capability 0x1991 v1.1
+- b bayer 0
+
+# timer capability registers
+flash_mode_capability 0x1a02
+- b single_strobe 0
+sa_strobe_mode_capability 0x1a03
+- b fixed_width 0
+- b edge_ctrl 1
+
+# soft reset capability registers
+reset_max_delay 0x1a10 v1.1
+reset_min_time 0x1a11 v1.1
+
+# pdaf capability registers
+pdaf_capability_1 0x1b80
+- b supported 0
+- b processed_bottom_embedded 1
+- b processed_interleaved 2
+- b raw_bottom_embedded 3
+- b raw_interleaved 4
+- b visible_pdaf_correction 5
+- b vc_interleaving 6
+- b dt_interleaving 7
+pdaf_capability_2 0x1b81
+- b ROI 0
+- b after_digital_crop 1
+- b ctrl_retimed 2
+
+# bracketing interface capability registers
+bracketing_lut_capability_1 0x1c00
+- b coarse_integration 0
+- b global_analog_gain 1
+- b flash 4
+- b global_digital_gain 5
+- b alternate_global_analog_gain 6
+bracketing_lut_capability_2 0x1c01
+- b single_bracketing_mode 0
+- b looped_bracketing_mode 1
+bracketing_lut_size 0x1c02
diff --git a/drivers/media/i2c/smiapp/mk-ccs-regs b/drivers/media/i2c/smiapp/mk-ccs-regs
new file mode 100644
index 000000000000..b345d4122ea2
--- /dev/null
+++ b/drivers/media/i2c/smiapp/mk-ccs-regs
@@ -0,0 +1,405 @@
+#!/usr/bin/perl -w
+#
+# Copyright (C) 2019--2020 Intel Corporation
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
+
+use Getopt::Long qw(:config no_ignore_case);
+use File::Basename;
+
+my $ccsregs = "ccs-regs.txt";
+my $header;
+my $regarray;
+my $limitc;
+my $limith;
+my $help;
+
+GetOptions("ccsregs|c=s" => \$ccsregs,
+ "header|e=s" => \$header,
+ "regarray|r=s" => \$regarray,
+ "limitc|l=s" => \$limitc,
+ "limith|L=s" => \$limith,
+ "help|h" => \$help) or die "can't parse options";
+
+$help = 1 if ! defined $header || ! defined $limitc || ! defined $limith;
+
+if (defined $help) {
+ print <<EOH
+$0 - Create CCS register definitions for C
+
+usage: $0 -c ccs-regs.txt -h header -r regarray -l limit-c -L limit-header
+
+ -c ccs register file
+ -e header file name
+ -r register description array file name
+ -l limit and capability array file name
+ -L limit and capability header file name
+EOH
+ ;
+ exit 0;
+}
+
+open(my $R, "< $ccsregs") or die "can't open $ccsregs";
+
+open(my $H, "> $header") or die "can't open $header";
+my $A;
+if (defined $regarray) {
+ open($A, "> $regarray") or die "can't open $regarray";
+}
+open(my $LC, "> $limitc") or die "can't open $limitc";
+open(my $LH, "> $limith") or die "can't open $limith";
+
+my %this;
+
+sub is_limit_reg($) {
+ my $addr = hex $_[0];
+
+ return 0 if $addr < 0x40; # weed out status registers
+ return 0 if $addr >= 0x100 && $addr < 0xfff; # weed out configuration registers
+
+ return 1;
+}
+
+my $uc_header = basename uc $header;
+$uc_header =~ s/[^A-Z0-9]/_/g;
+
+my $copyright = "/* Copyright (C) 2019--2020 Intel Corporation */\n";
+my $license = "SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause";
+
+for my $fh ($A, $LC) {
+ print $fh "// $license\n$copyright\n" if defined $fh;
+}
+
+for my $fh ($H, $LH) {
+ print $fh "/* $license */\n$copyright\n";
+}
+
+print $H <<EOF
+#ifndef __${uc_header}__
+#define __${uc_header}__
+
+#define CCS_FL_BASE 16
+#define CCS_FL_16BIT (1U << CCS_FL_BASE)
+#define CCS_FL_32BIT (1U << (CCS_FL_BASE + 1))
+#define CCS_FL_FLOAT_IREAL (1U << (CCS_FL_BASE + 2))
+#define CCS_FL_IREAL (1U << (CCS_FL_BASE + 3))
+
+#define CCS_R_ADDR(r) ((r) & 0xffff)
+
+EOF
+ ;
+
+print $A <<EOF
+#include <stdint.h>
+#include <stdio.h>
+#include "ccs-extra.h"
+#include "ccs-regs.h"
+
+EOF
+ if defined $A;
+
+my $uc_limith = basename uc $limith;
+$uc_limith =~ s/[^A-Z0-9]/_/g;
+
+print $LH <<EOF
+#ifndef __${uc_limith}__
+#define __${uc_limith}__
+
+#include "ccs-os.h"
+
+struct ccs_limit {
+ uint32_t reg;
+ uint16_t size;
+ uint16_t flags;
+ const char *name;
+};
+
+#define CCS_L_FL_SAME_REG (1U << 0)
+
+extern const struct ccs_limit ccs_limits[];
+
+EOF
+ ;
+
+print $LC <<EOF
+#include "ccs-limits.h"
+#include "ccs-regs.h"
+
+const struct ccs_limit ccs_limits[] = {
+EOF
+ ;
+
+my $limitcount = 0;
+my $argdescs;
+my $reglist = "const struct ccs_reg_desc ccs_reg_desc[] = {\n";
+
+sub name_split($$) {
+ my ($name, $addr) = @_;
+ my $args;
+
+ $name =~ /([^\(]+?)(\(.*)/;
+ ($name, $args) = ($1, $2);
+ $args = [split /,\s*/, $args];
+ foreach my $t (@$args) {
+ $t =~ s/[\(\)]//g;
+ $t =~ s/\//\\\//g;
+ }
+
+ return ($name, $addr, $args);
+}
+
+sub tabconv($) {
+ $_ = shift;
+
+ my @l = split "\n", $_;
+
+ map {
+ s/ {8,8}/\t/g;
+ s/\t\K +//;
+ } @l;
+
+ return (join "\n", @l) . "\n";
+}
+
+sub elem_size(@) {
+ my @flags = @_;
+
+ return 2 if grep /^16$/, @flags;
+ return 4 if grep /^32$/, @flags;
+ return 1;
+}
+
+sub arr_size($) {
+ my $this = $_[0];
+ my $size = $this->{elsize};
+ my $h = $this->{argparams};
+
+ foreach my $arg (@{$this->{args}}) {
+ my $apref = $h->{$arg};
+
+ $size *= $apref->{max} - $apref->{min} + 1;
+ }
+
+ return $size;
+}
+
+sub print_args($$$) {
+ my ($this, $postfix, $is_same_reg) = @_;
+ my ($args, $argparams, $name) =
+ ($this->{args}, $this->{argparams}, $this->{name});
+ my $varname = "ccs_reg_arg_" . (lc $name) . $postfix;
+ my @mins;
+ my @sorted_args = @{$this->{sorted_args}};
+ my $lim_arg;
+ my $size = arr_size($this);
+
+ $argdescs .= "static const struct ccs_reg_arg " . $varname . "[] = {\n";
+
+ foreach my $sorted_arg (@sorted_args) {
+ push @mins, $argparams->{$sorted_arg}->{min};
+ }
+
+ foreach my $sorted_arg (@sorted_args) {
+ my $h = $argparams->{$sorted_arg};
+
+ $argdescs .= "\t{ \"$sorted_arg\", $h->{min}, $h->{max}, $h->{elsize} },\n";
+
+ $lim_arg .= defined $lim_arg ? ", $h->{min}" : "$h->{min}";
+ }
+
+ $argdescs .= "};\n\n";
+
+ $reglist .= "\t{ CCS_R_" . (uc $name) . "(" . (join ",", (@mins)) .
+ "), $size, sizeof($varname) / sizeof(*$varname)," .
+ " \"" . (lc $name) . "\", $varname },\n";
+
+ print $LC tabconv sprintf "\t{ CCS_R_" . (uc $name) . "($lim_arg), " .
+ $size . ", " . ($is_same_reg ? "CCS_L_FL_SAME_REG" : "0") .
+ ", \"$name" . (defined $this->{discontig} ? " $lim_arg" : "") . "\" },\n"
+ if is_limit_reg $this->{base_addr};
+}
+
+my $hdr_data;
+
+while (<$R>) {
+ chop;
+ s/^\s*//;
+ next if /^[#;]/ || /^$/;
+ if (s/^-\s*//) {
+ if (s/^b\s*//) {
+ my ($bit, $addr) = split /\t+/;
+ $bit = uc $bit;
+ $hdr_data .= sprintf "#define %-62s %s", "CCS_" . (uc ${this{name}}) ."_$bit", "(1U << $addr)\n";
+ } elsif (s/^f\s*//) {
+ s/[,\.-]/_/g;
+ my @a = split /\s+/;
+ my ($msb, $lsb, $this_field) = reverse @a;
+ @a = ( { "name" => "SHIFT", "addr" => $lsb, "fmt" => "%uU", },
+ { "name" => "MASK", "addr" => (1 << ($msb + 1)) - 1 - ((1 << $lsb) - 1), "fmt" => "0x%" . join(".", ($this{"elsize"} >> 2) x 2) . "x" } );
+ $this{"field"} = $this_field;
+ foreach my $ar (@a) {
+ #print $ar->{fmt}."\n";
+ $hdr_data .= sprintf "#define %-62s " . $ar->{"fmt"} . "\n", "CCS_" . (uc $this{"name"}) . (defined $this_field ? "_" . uc $this_field : "") . "_" . $ar->{"name"}, $ar->{"addr"} . "\n";
+ }
+ } elsif (s/^e\s*//) {
+ s/[,\.-]/_/g;
+ my ($enum, $addr) = split /\s+/;
+ $enum = uc $enum;
+ $hdr_data .= sprintf "#define %-62s %s", "CCS_" . (uc ${this{name}}) . (defined $this{"field"} ? "_" . uc $this{"field"} : "") ."_$enum", $addr . ($addr =~ /0x/i ? "" : "U") . "\n";
+ } elsif (s/^l\s*//) {
+ my ($arg, $min, $max, $elsize, @discontig) = split /\s+/;
+ my $size;
+
+ foreach my $num ($min, $max) {
+ $num = hex $num if $num =~ /0x/i;
+ }
+
+ $hdr_data .= sprintf "#define %-62s %s", "CCS_LIM_" . (uc ${this{name}} . "_MIN_$arg"), $min . ($min =~ /0x/i ? "" : "U") . "\n";
+ $hdr_data .= sprintf "#define %-62s %s", "CCS_LIM_" . (uc ${this{name}} . "_MAX_$arg"), $max . ($max =~ /0x/i ? "" : "U") . "\n";
+
+ my $h = $this{argparams};
+
+ $h->{$arg} = { "min" => $min,
+ "max" => $max,
+ "elsize" => $elsize =~ /^0x/ ? hex $elsize : $elsize,
+ "discontig" => \@discontig };
+
+ $this{discontig} = $arg if @discontig;
+
+ next if $#{$this{args}} + 1 != scalar keys %{$this{argparams}};
+
+ my $reg_formula = "($this{addr}";
+ my $lim_formula;
+
+ foreach my $arg (@{$this{args}}) {
+ my $d = $h->{$arg}->{discontig};
+ my $times = $h->{$arg}->{elsize} != 1 ?
+ " * " . $h->{$arg}->{elsize} : "";
+
+ if (@$d) {
+ my ($lim, $offset) = split /,/, $d->[0];
+
+ $reg_formula .= " + (($arg) < $lim ? ($arg)$times : $offset + (($arg) - $lim)$times)";
+ } else {
+ $reg_formula .= " + ($arg)$times";
+ }
+
+ $lim_formula .= (defined $lim_formula ? " + " : "") . "($arg)$times";
+ }
+
+ $reg_formula .= ")\n";
+ $lim_formula =~ s/^\(([a-z0-9]+)\)$/$1/i;
+
+ print $H tabconv sprintf("#define %-62s %s", "CCS_R_" . (uc $this{name}) .
+ $this{arglist}, $reg_formula);
+
+ print $H tabconv $hdr_data;
+ undef $hdr_data;
+
+ # Sort arguments in descending order by size
+ @{$this{sorted_args}} = sort {
+ $h->{$a}->{elsize} <= $h->{$b}->{elsize}
+ } @{$this{args}};
+
+ if (defined $this{discontig}) {
+ my $da = $this{argparams}->{$this{discontig}};
+ my ($first_discontig) = split /,/, $da->{discontig}->[0];
+ my $max = $da->{max};
+
+ $da->{max} = $first_discontig - 1;
+ print_args(\%this, "", 0);
+
+ $da->{min} = $da->{max} + 1;
+ $da->{max} = $max;
+ print_args(\%this, $first_discontig, 1);
+ } else {
+ print_args(\%this, "", 0);
+ }
+
+ next unless is_limit_reg $this{base_addr};
+
+ print $LH tabconv sprintf "#define %-63s%s\n",
+ "CCS_L_" . (uc $this{name}) . "_OFFSET(" .
+ (join ", ", @{$this{args}}) . ")", "($lim_formula)";
+ }
+
+ if (! @{$this{args}}) {
+ print $H tabconv($hdr_data);
+ undef $hdr_data;
+ }
+
+ next;
+ }
+
+ my ($name, $addr, @flags) = split /\t+/, $_;
+ my $args = [];
+
+ my $sp;
+
+ ($name, $addr, $args) = name_split($name, $addr) if /\(.*\)/;
+
+ $name =~ s/[,\.-]/_/g;
+
+ my $flagstring = "";
+ my $size = elem_size(@flags);
+ $flagstring .= "| CCS_FL_16BIT " if $size eq "2";
+ $flagstring .= "| CCS_FL_32BIT " if $size eq "4";
+ $flagstring .= "| CCS_FL_FLOAT_IREAL " if grep /^float_ireal$/, @flags;
+ $flagstring .= "| CCS_FL_IREAL " if grep /^ireal$/, @flags;
+ $flagstring =~ s/^\| //;
+ $flagstring =~ s/ $//;
+ $flagstring = "($flagstring)" if $flagstring =~ /\|/;
+ my $base_addr = $addr;
+ $addr = "($addr | $flagstring)" if $flagstring ne "";
+
+ my $arglist = @$args ? "(" . (join ", ", @$args) . ")" : "";
+ $hdr_data .= sprintf "#define %-62s %s\n", "CCS_R_" . (uc $name), $addr
+ if !@$args;
+
+ $name =~ s/\(.*//;
+
+ %this = ( name => $name,
+ addr => $addr,
+ base_addr => $base_addr,
+ argparams => {},
+ args => $args,
+ arglist => $arglist,
+ elsize => $size,
+ );
+
+ if (!@$args) {
+ $reglist .= "\t{ CCS_R_" . (uc $name) . ", 1, 0, \"" . (lc $name) . "\", NULL },\n";
+ print $H tabconv $hdr_data;
+ undef $hdr_data;
+
+ print $LC tabconv sprintf "\t{ CCS_R_" . (uc $name) . ", " .
+ $this{elsize} . ", 0, \"$name\" },\n"
+ if is_limit_reg $this{base_addr};
+ }
+
+ print $LH tabconv sprintf "#define %-63s%s\n",
+ "CCS_L_" . (uc $this{name}), $limitcount++
+ if is_limit_reg $this{base_addr};
+}
+
+if (defined $A) {
+ print $A $argdescs, $reglist;
+
+ print $A "\t{ 0 }\n";
+
+ print $A "};\n";
+}
+
+print $H "\n#endif /* __${uc_header}__ */\n";
+
+print $LH tabconv sprintf "#define %-63s%s\n", "CCS_L_LAST", $limitcount;
+
+print $LH "\n#endif /* __${uc_limith}__ */\n";
+
+print $LC "\t{ 0 } /* Guardian */\n";
+print $LC "};\n";
+
+close($R);
+close($H);
+close($A) if defined $A;
+close($LC);
+close($LH);
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 002/106] smiapp: Use CCS register flags
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 003/106] smiapp: Calculate CCS limit offsets and limit buffer size Sakari Ailus
` (95 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
Use the CCS register flags instead of the old smia flags. The
new flags include the register width information that was separate from
the register flags previously.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/smiapp-reg-defs.h | 8 ++++----
drivers/media/i2c/smiapp/smiapp-regs.c | 20 +++++++++++++-------
drivers/media/i2c/smiapp/smiapp-regs.h | 13 ++++---------
3 files changed, 21 insertions(+), 20 deletions(-)
diff --git a/drivers/media/i2c/smiapp/smiapp-reg-defs.h b/drivers/media/i2c/smiapp/smiapp-reg-defs.h
index 865488befc09..ec574007908b 100644
--- a/drivers/media/i2c/smiapp/smiapp-reg-defs.h
+++ b/drivers/media/i2c/smiapp/smiapp-reg-defs.h
@@ -7,11 +7,11 @@
* Copyright (C) 2011--2012 Nokia Corporation
* Contact: Sakari Ailus <sakari.ailus@iki.fi>
*/
-#define SMIAPP_REG_MK_U8(r) ((SMIAPP_REG_8BIT << 16) | (r))
-#define SMIAPP_REG_MK_U16(r) ((SMIAPP_REG_16BIT << 16) | (r))
-#define SMIAPP_REG_MK_U32(r) ((SMIAPP_REG_32BIT << 16) | (r))
+#define SMIAPP_REG_MK_U8(r) (r)
+#define SMIAPP_REG_MK_U16(r) (CCS_FL_16BIT | (r))
+#define SMIAPP_REG_MK_U32(r) (CCS_FL_32BIT | (r))
-#define SMIAPP_REG_MK_F32(r) (SMIAPP_REG_FLAG_FLOAT | (SMIAPP_REG_32BIT << 16) | (r))
+#define SMIAPP_REG_MK_F32(r) (CCS_FL_FLOAT_IREAL | CCS_FL_32BIT | (r))
#define SMIAPP_REG_U16_MODEL_ID SMIAPP_REG_MK_U16(0x0000)
#define SMIAPP_REG_U8_REVISION_NUMBER_MAJOR SMIAPP_REG_MK_U8(0x0002)
diff --git a/drivers/media/i2c/smiapp/smiapp-regs.c b/drivers/media/i2c/smiapp/smiapp-regs.c
index 1b58b7c6c839..904054d303ba 100644
--- a/drivers/media/i2c/smiapp/smiapp-regs.c
+++ b/drivers/media/i2c/smiapp/smiapp-regs.c
@@ -133,6 +133,16 @@ static int ____smiapp_read_8only(struct smiapp_sensor *sensor, u16 reg,
return 0;
}
+unsigned int ccs_reg_width(u32 reg)
+{
+ if (reg & CCS_FL_16BIT)
+ return sizeof(uint16_t);
+ if (reg & CCS_FL_32BIT)
+ return sizeof(uint32_t);
+
+ return sizeof(uint8_t);
+}
+
/*
* Read a 8/16/32-bit i2c register. The value is returned in 'val'.
* Returns zero if successful, or non-zero otherwise.
@@ -141,13 +151,9 @@ static int __smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val,
bool only8)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- u8 len = SMIAPP_REG_WIDTH(reg);
+ unsigned int len = ccs_reg_width(reg);
int rval;
- if (len != SMIAPP_REG_8BIT && len != SMIAPP_REG_16BIT
- && len != SMIAPP_REG_32BIT)
- return -EINVAL;
-
if (!only8)
rval = ____smiapp_read(sensor, SMIAPP_REG_ADDR(reg), len, val);
else
@@ -156,7 +162,7 @@ static int __smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val,
if (rval < 0)
return rval;
- if (reg & SMIAPP_REG_FLAG_FLOAT)
+ if (reg & CCS_FL_FLOAT_IREAL)
*val = float_to_u32_mul_1000000(client, *val);
return 0;
@@ -204,7 +210,7 @@ int smiapp_write_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val)
struct i2c_msg msg;
unsigned char data[6];
unsigned int retries;
- u8 len = SMIAPP_REG_WIDTH(reg);
+ unsigned int len = ccs_reg_width(reg);
int r;
if (len > sizeof(data) - 2)
diff --git a/drivers/media/i2c/smiapp/smiapp-regs.h b/drivers/media/i2c/smiapp/smiapp-regs.h
index 8fda6ed5668c..7223f5f89109 100644
--- a/drivers/media/i2c/smiapp/smiapp-regs.h
+++ b/drivers/media/i2c/smiapp/smiapp-regs.h
@@ -14,16 +14,9 @@
#include <linux/i2c.h>
#include <linux/types.h>
-#define SMIAPP_REG_ADDR(reg) ((u16)reg)
-#define SMIAPP_REG_WIDTH(reg) ((u8)(reg >> 16))
-#define SMIAPP_REG_FLAGS(reg) ((u8)(reg >> 24))
-
-/* Use upper 8 bits of the type field for flags */
-#define SMIAPP_REG_FLAG_FLOAT (1 << 24)
+#include "ccs-regs.h"
-#define SMIAPP_REG_8BIT 1
-#define SMIAPP_REG_16BIT 2
-#define SMIAPP_REG_32BIT 4
+#define SMIAPP_REG_ADDR(reg) ((u16)reg)
struct smiapp_sensor;
@@ -33,4 +26,6 @@ int smiapp_read_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val);
int smiapp_write_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val);
int smiapp_write(struct smiapp_sensor *sensor, u32 reg, u32 val);
+unsigned int ccs_reg_width(u32 reg);
+
#endif
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 003/106] smiapp: Calculate CCS limit offsets and limit buffer size
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 002/106] smiapp: Use CCS register flags Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-11-05 7:43 ` Mauro Carvalho Chehab
2020-10-07 8:44 ` [PATCH v2 004/106] smiapp: Remove macros for defining registers, merge definitions Sakari Ailus
` (94 subsequent siblings)
96 siblings, 1 reply; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
Calculate the limit offsets and the size of the limit buffer. CCS limits
are read into this buffer, and the offsets are helpful in accessing the
information in it.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/smiapp-core.c | 40 +++++++++++++++++++++++++-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c
index 105ef29152e8..47e983e9cd87 100644
--- a/drivers/media/i2c/smiapp/smiapp-core.c
+++ b/drivers/media/i2c/smiapp/smiapp-core.c
@@ -27,6 +27,7 @@
#include <media/v4l2-fwnode.h>
#include <media/v4l2-device.h>
+#include "ccs-limits.h"
#include "smiapp.h"
#define SMIAPP_ALIGN_DIM(dim, flags) \
@@ -34,6 +35,11 @@
? ALIGN((dim), 2) \
: (dim) & ~1)
+struct ccs_limit_offset {
+ u16 lim;
+ u16 info;
+} ccs_limit_offsets[CCS_L_LAST + 1];
+
/*
* smiapp_module_idents - supported camera modules
*/
@@ -3166,7 +3172,39 @@ static struct i2c_driver smiapp_i2c_driver = {
.id_table = smiapp_id_table,
};
-module_i2c_driver(smiapp_i2c_driver);
+static int smiapp_module_init(void)
+{
+ unsigned int i, l;
+
+ for (i = 0, l = 0; ccs_limits[i].size && l < CCS_L_LAST; i++) {
+ if (!(ccs_limits[i].flags & CCS_L_FL_SAME_REG)) {
+ ccs_limit_offsets[l + 1].lim =
+ ALIGN(ccs_limit_offsets[l].lim +
+ ccs_limits[i].size,
+ ccs_reg_width(ccs_limits[i + 1].reg));
+ ccs_limit_offsets[l].info = i;
+ l++;
+ } else {
+ ccs_limit_offsets[l].lim += ccs_limits[i].size;
+ }
+ }
+
+ if (WARN_ON(ccs_limits[i].size))
+ return -EINVAL;
+
+ if (WARN_ON(l != CCS_L_LAST))
+ return -EINVAL;
+
+ return i2c_register_driver(THIS_MODULE, &smiapp_i2c_driver);
+}
+
+static void smiapp_module_cleanup(void)
+{
+ i2c_del_driver(&smiapp_i2c_driver);
+}
+
+module_init(smiapp_module_init);
+module_exit(smiapp_module_cleanup);
MODULE_AUTHOR("Sakari Ailus <sakari.ailus@iki.fi>");
MODULE_DESCRIPTION("Generic SMIA/SMIA++ camera module driver");
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 004/106] smiapp: Remove macros for defining registers, merge definitions
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 002/106] smiapp: Use CCS register flags Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 003/106] smiapp: Calculate CCS limit offsets and limit buffer size Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 005/106] smiapp: Add macros for accessing CCS registers Sakari Ailus
` (93 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
Remove macros for defining new SMIA registers, instead put the register
flags to the register definition itself. Also move the register flags to
the same file.
This is not expected to be updated but rather left there as a reference.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/smiapp-quirk.c | 2 +-
drivers/media/i2c/smiapp/smiapp-reg-defs.h | 1046 +++++++++++---------
drivers/media/i2c/smiapp/smiapp-reg.h | 116 ---
drivers/media/i2c/smiapp/smiapp.h | 2 +-
4 files changed, 570 insertions(+), 596 deletions(-)
delete mode 100644 drivers/media/i2c/smiapp/smiapp-reg.h
diff --git a/drivers/media/i2c/smiapp/smiapp-quirk.c b/drivers/media/i2c/smiapp/smiapp-quirk.c
index ab96d6067fc3..308ca0b03f5a 100644
--- a/drivers/media/i2c/smiapp/smiapp-quirk.c
+++ b/drivers/media/i2c/smiapp/smiapp-quirk.c
@@ -14,7 +14,7 @@
static int smiapp_write_8(struct smiapp_sensor *sensor, u16 reg, u8 val)
{
- return smiapp_write(sensor, SMIAPP_REG_MK_U8(reg), val);
+ return smiapp_write(sensor, reg, val);
}
static int smiapp_write_8s(struct smiapp_sensor *sensor,
diff --git a/drivers/media/i2c/smiapp/smiapp-reg-defs.h b/drivers/media/i2c/smiapp/smiapp-reg-defs.h
index ec574007908b..06b69b1ab55f 100644
--- a/drivers/media/i2c/smiapp/smiapp-reg-defs.h
+++ b/drivers/media/i2c/smiapp/smiapp-reg-defs.h
@@ -7,483 +7,573 @@
* Copyright (C) 2011--2012 Nokia Corporation
* Contact: Sakari Ailus <sakari.ailus@iki.fi>
*/
-#define SMIAPP_REG_MK_U8(r) (r)
-#define SMIAPP_REG_MK_U16(r) (CCS_FL_16BIT | (r))
-#define SMIAPP_REG_MK_U32(r) (CCS_FL_32BIT | (r))
-#define SMIAPP_REG_MK_F32(r) (CCS_FL_FLOAT_IREAL | CCS_FL_32BIT | (r))
+#ifndef __SMIAPP_REG_DEFS_H__
+#define __SMIAPP_REG_DEFS_H__
-#define SMIAPP_REG_U16_MODEL_ID SMIAPP_REG_MK_U16(0x0000)
-#define SMIAPP_REG_U8_REVISION_NUMBER_MAJOR SMIAPP_REG_MK_U8(0x0002)
-#define SMIAPP_REG_U8_MANUFACTURER_ID SMIAPP_REG_MK_U8(0x0003)
-#define SMIAPP_REG_U8_SMIA_VERSION SMIAPP_REG_MK_U8(0x0004)
-#define SMIAPP_REG_U8_FRAME_COUNT SMIAPP_REG_MK_U8(0x0005)
-#define SMIAPP_REG_U8_PIXEL_ORDER SMIAPP_REG_MK_U8(0x0006)
-#define SMIAPP_REG_U16_DATA_PEDESTAL SMIAPP_REG_MK_U16(0x0008)
-#define SMIAPP_REG_U8_PIXEL_DEPTH SMIAPP_REG_MK_U8(0x000c)
-#define SMIAPP_REG_U8_REVISION_NUMBER_MINOR SMIAPP_REG_MK_U8(0x0010)
-#define SMIAPP_REG_U8_SMIAPP_VERSION SMIAPP_REG_MK_U8(0x0011)
-#define SMIAPP_REG_U8_MODULE_DATE_YEAR SMIAPP_REG_MK_U8(0x0012)
-#define SMIAPP_REG_U8_MODULE_DATE_MONTH SMIAPP_REG_MK_U8(0x0013)
-#define SMIAPP_REG_U8_MODULE_DATE_DAY SMIAPP_REG_MK_U8(0x0014)
-#define SMIAPP_REG_U8_MODULE_DATE_PHASE SMIAPP_REG_MK_U8(0x0015)
-#define SMIAPP_REG_U16_SENSOR_MODEL_ID SMIAPP_REG_MK_U16(0x0016)
-#define SMIAPP_REG_U8_SENSOR_REVISION_NUMBER SMIAPP_REG_MK_U8(0x0018)
-#define SMIAPP_REG_U8_SENSOR_MANUFACTURER_ID SMIAPP_REG_MK_U8(0x0019)
-#define SMIAPP_REG_U8_SENSOR_FIRMWARE_VERSION SMIAPP_REG_MK_U8(0x001a)
-#define SMIAPP_REG_U32_SERIAL_NUMBER SMIAPP_REG_MK_U32(0x001c)
-#define SMIAPP_REG_U8_FRAME_FORMAT_MODEL_TYPE SMIAPP_REG_MK_U8(0x0040)
-#define SMIAPP_REG_U8_FRAME_FORMAT_MODEL_SUBTYPE SMIAPP_REG_MK_U8(0x0041)
-#define SMIAPP_REG_U16_FRAME_FORMAT_DESCRIPTOR_2(n) SMIAPP_REG_MK_U16(0x0042 + ((n) << 1)) /* 0 <= n <= 14 */
-#define SMIAPP_REG_U32_FRAME_FORMAT_DESCRIPTOR_4(n) SMIAPP_REG_MK_U32(0x0060 + ((n) << 2)) /* 0 <= n <= 7 */
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CAPABILITY SMIAPP_REG_MK_U16(0x0080)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MIN SMIAPP_REG_MK_U16(0x0084)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MAX SMIAPP_REG_MK_U16(0x0086)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_STEP SMIAPP_REG_MK_U16(0x0088)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_TYPE SMIAPP_REG_MK_U16(0x008a)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_M0 SMIAPP_REG_MK_U16(0x008c)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_C0 SMIAPP_REG_MK_U16(0x008e)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_M1 SMIAPP_REG_MK_U16(0x0090)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_C1 SMIAPP_REG_MK_U16(0x0092)
-#define SMIAPP_REG_U8_DATA_FORMAT_MODEL_TYPE SMIAPP_REG_MK_U8(0x00c0)
-#define SMIAPP_REG_U8_DATA_FORMAT_MODEL_SUBTYPE SMIAPP_REG_MK_U8(0x00c1)
-#define SMIAPP_REG_U16_DATA_FORMAT_DESCRIPTOR(n) SMIAPP_REG_MK_U16(0x00c2 + ((n) << 1))
-#define SMIAPP_REG_U8_MODE_SELECT SMIAPP_REG_MK_U8(0x0100)
-#define SMIAPP_REG_U8_IMAGE_ORIENTATION SMIAPP_REG_MK_U8(0x0101)
-#define SMIAPP_REG_U8_SOFTWARE_RESET SMIAPP_REG_MK_U8(0x0103)
-#define SMIAPP_REG_U8_GROUPED_PARAMETER_HOLD SMIAPP_REG_MK_U8(0x0104)
-#define SMIAPP_REG_U8_MASK_CORRUPTED_FRAMES SMIAPP_REG_MK_U8(0x0105)
-#define SMIAPP_REG_U8_FAST_STANDBY_CTRL SMIAPP_REG_MK_U8(0x0106)
-#define SMIAPP_REG_U8_CCI_ADDRESS_CONTROL SMIAPP_REG_MK_U8(0x0107)
-#define SMIAPP_REG_U8_2ND_CCI_IF_CONTROL SMIAPP_REG_MK_U8(0x0108)
-#define SMIAPP_REG_U8_2ND_CCI_ADDRESS_CONTROL SMIAPP_REG_MK_U8(0x0109)
-#define SMIAPP_REG_U8_CSI_CHANNEL_IDENTIFIER SMIAPP_REG_MK_U8(0x0110)
-#define SMIAPP_REG_U8_CSI_SIGNALLING_MODE SMIAPP_REG_MK_U8(0x0111)
-#define SMIAPP_REG_U16_CSI_DATA_FORMAT SMIAPP_REG_MK_U16(0x0112)
-#define SMIAPP_REG_U8_CSI_LANE_MODE SMIAPP_REG_MK_U8(0x0114)
-#define SMIAPP_REG_U8_CSI2_10_TO_8_DT SMIAPP_REG_MK_U8(0x0115)
-#define SMIAPP_REG_U8_CSI2_10_TO_7_DT SMIAPP_REG_MK_U8(0x0116)
-#define SMIAPP_REG_U8_CSI2_10_TO_6_DT SMIAPP_REG_MK_U8(0x0117)
-#define SMIAPP_REG_U8_CSI2_12_TO_8_DT SMIAPP_REG_MK_U8(0x0118)
-#define SMIAPP_REG_U8_CSI2_12_TO_7_DT SMIAPP_REG_MK_U8(0x0119)
-#define SMIAPP_REG_U8_CSI2_12_TO_6_DT SMIAPP_REG_MK_U8(0x011a)
-#define SMIAPP_REG_U8_CSI2_14_TO_10_DT SMIAPP_REG_MK_U8(0x011b)
-#define SMIAPP_REG_U8_CSI2_14_TO_8_DT SMIAPP_REG_MK_U8(0x011c)
-#define SMIAPP_REG_U8_CSI2_16_TO_10_DT SMIAPP_REG_MK_U8(0x011d)
-#define SMIAPP_REG_U8_CSI2_16_TO_8_DT SMIAPP_REG_MK_U8(0x011e)
-#define SMIAPP_REG_U8_GAIN_MODE SMIAPP_REG_MK_U8(0x0120)
-#define SMIAPP_REG_U16_VANA_VOLTAGE SMIAPP_REG_MK_U16(0x0130)
-#define SMIAPP_REG_U16_VDIG_VOLTAGE SMIAPP_REG_MK_U16(0x0132)
-#define SMIAPP_REG_U16_VIO_VOLTAGE SMIAPP_REG_MK_U16(0x0134)
-#define SMIAPP_REG_U16_EXTCLK_FREQUENCY_MHZ SMIAPP_REG_MK_U16(0x0136)
-#define SMIAPP_REG_U8_TEMP_SENSOR_CONTROL SMIAPP_REG_MK_U8(0x0138)
-#define SMIAPP_REG_U8_TEMP_SENSOR_MODE SMIAPP_REG_MK_U8(0x0139)
-#define SMIAPP_REG_U8_TEMP_SENSOR_OUTPUT SMIAPP_REG_MK_U8(0x013a)
-#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME SMIAPP_REG_MK_U16(0x0200)
-#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME SMIAPP_REG_MK_U16(0x0202)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GLOBAL SMIAPP_REG_MK_U16(0x0204)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GREENR SMIAPP_REG_MK_U16(0x0206)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_RED SMIAPP_REG_MK_U16(0x0208)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_BLUE SMIAPP_REG_MK_U16(0x020a)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GREENB SMIAPP_REG_MK_U16(0x020c)
-#define SMIAPP_REG_U16_DIGITAL_GAIN_GREENR SMIAPP_REG_MK_U16(0x020e)
-#define SMIAPP_REG_U16_DIGITAL_GAIN_RED SMIAPP_REG_MK_U16(0x0210)
-#define SMIAPP_REG_U16_DIGITAL_GAIN_BLUE SMIAPP_REG_MK_U16(0x0212)
-#define SMIAPP_REG_U16_DIGITAL_GAIN_GREENB SMIAPP_REG_MK_U16(0x0214)
-#define SMIAPP_REG_U16_VT_PIX_CLK_DIV SMIAPP_REG_MK_U16(0x0300)
-#define SMIAPP_REG_U16_VT_SYS_CLK_DIV SMIAPP_REG_MK_U16(0x0302)
-#define SMIAPP_REG_U16_PRE_PLL_CLK_DIV SMIAPP_REG_MK_U16(0x0304)
-#define SMIAPP_REG_U16_PLL_MULTIPLIER SMIAPP_REG_MK_U16(0x0306)
-#define SMIAPP_REG_U16_OP_PIX_CLK_DIV SMIAPP_REG_MK_U16(0x0308)
-#define SMIAPP_REG_U16_OP_SYS_CLK_DIV SMIAPP_REG_MK_U16(0x030a)
-#define SMIAPP_REG_U16_FRAME_LENGTH_LINES SMIAPP_REG_MK_U16(0x0340)
-#define SMIAPP_REG_U16_LINE_LENGTH_PCK SMIAPP_REG_MK_U16(0x0342)
-#define SMIAPP_REG_U16_X_ADDR_START SMIAPP_REG_MK_U16(0x0344)
-#define SMIAPP_REG_U16_Y_ADDR_START SMIAPP_REG_MK_U16(0x0346)
-#define SMIAPP_REG_U16_X_ADDR_END SMIAPP_REG_MK_U16(0x0348)
-#define SMIAPP_REG_U16_Y_ADDR_END SMIAPP_REG_MK_U16(0x034a)
-#define SMIAPP_REG_U16_X_OUTPUT_SIZE SMIAPP_REG_MK_U16(0x034c)
-#define SMIAPP_REG_U16_Y_OUTPUT_SIZE SMIAPP_REG_MK_U16(0x034e)
-#define SMIAPP_REG_U16_X_EVEN_INC SMIAPP_REG_MK_U16(0x0380)
-#define SMIAPP_REG_U16_X_ODD_INC SMIAPP_REG_MK_U16(0x0382)
-#define SMIAPP_REG_U16_Y_EVEN_INC SMIAPP_REG_MK_U16(0x0384)
-#define SMIAPP_REG_U16_Y_ODD_INC SMIAPP_REG_MK_U16(0x0386)
-#define SMIAPP_REG_U16_SCALING_MODE SMIAPP_REG_MK_U16(0x0400)
-#define SMIAPP_REG_U16_SPATIAL_SAMPLING SMIAPP_REG_MK_U16(0x0402)
-#define SMIAPP_REG_U16_SCALE_M SMIAPP_REG_MK_U16(0x0404)
-#define SMIAPP_REG_U16_SCALE_N SMIAPP_REG_MK_U16(0x0406)
-#define SMIAPP_REG_U16_DIGITAL_CROP_X_OFFSET SMIAPP_REG_MK_U16(0x0408)
-#define SMIAPP_REG_U16_DIGITAL_CROP_Y_OFFSET SMIAPP_REG_MK_U16(0x040a)
-#define SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_WIDTH SMIAPP_REG_MK_U16(0x040c)
-#define SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_HEIGHT SMIAPP_REG_MK_U16(0x040e)
-#define SMIAPP_REG_U16_COMPRESSION_MODE SMIAPP_REG_MK_U16(0x0500)
-#define SMIAPP_REG_U16_TEST_PATTERN_MODE SMIAPP_REG_MK_U16(0x0600)
-#define SMIAPP_REG_U16_TEST_DATA_RED SMIAPP_REG_MK_U16(0x0602)
-#define SMIAPP_REG_U16_TEST_DATA_GREENR SMIAPP_REG_MK_U16(0x0604)
-#define SMIAPP_REG_U16_TEST_DATA_BLUE SMIAPP_REG_MK_U16(0x0606)
-#define SMIAPP_REG_U16_TEST_DATA_GREENB SMIAPP_REG_MK_U16(0x0608)
-#define SMIAPP_REG_U16_HORIZONTAL_CURSOR_WIDTH SMIAPP_REG_MK_U16(0x060a)
-#define SMIAPP_REG_U16_HORIZONTAL_CURSOR_POSITION SMIAPP_REG_MK_U16(0x060c)
-#define SMIAPP_REG_U16_VERTICAL_CURSOR_WIDTH SMIAPP_REG_MK_U16(0x060e)
-#define SMIAPP_REG_U16_VERTICAL_CURSOR_POSITION SMIAPP_REG_MK_U16(0x0610)
-#define SMIAPP_REG_U16_FIFO_WATER_MARK_PIXELS SMIAPP_REG_MK_U16(0x0700)
-#define SMIAPP_REG_U8_TCLK_POST SMIAPP_REG_MK_U8(0x0800)
-#define SMIAPP_REG_U8_THS_PREPARE SMIAPP_REG_MK_U8(0x0801)
-#define SMIAPP_REG_U8_THS_ZERO_MIN SMIAPP_REG_MK_U8(0x0802)
-#define SMIAPP_REG_U8_THS_TRAIL SMIAPP_REG_MK_U8(0x0803)
-#define SMIAPP_REG_U8_TCLK_TRAIL_MIN SMIAPP_REG_MK_U8(0x0804)
-#define SMIAPP_REG_U8_TCLK_PREPARE SMIAPP_REG_MK_U8(0x0805)
-#define SMIAPP_REG_U8_TCLK_ZERO SMIAPP_REG_MK_U8(0x0806)
-#define SMIAPP_REG_U8_TLPX SMIAPP_REG_MK_U8(0x0807)
-#define SMIAPP_REG_U8_DPHY_CTRL SMIAPP_REG_MK_U8(0x0808)
-#define SMIAPP_REG_U32_REQUESTED_LINK_BIT_RATE_MBPS SMIAPP_REG_MK_U32(0x0820)
-#define SMIAPP_REG_U8_BINNING_MODE SMIAPP_REG_MK_U8(0x0900)
-#define SMIAPP_REG_U8_BINNING_TYPE SMIAPP_REG_MK_U8(0x0901)
-#define SMIAPP_REG_U8_BINNING_WEIGHTING SMIAPP_REG_MK_U8(0x0902)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_CTRL SMIAPP_REG_MK_U8(0x0a00)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_STATUS SMIAPP_REG_MK_U8(0x0a01)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_PAGE_SELECT SMIAPP_REG_MK_U8(0x0a02)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_0 SMIAPP_REG_MK_U8(0x0a04)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_1 SMIAPP_REG_MK_U8(0x0a05)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_2 SMIAPP_REG_MK_U8(0x0a06)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_3 SMIAPP_REG_MK_U8(0x0a07)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_4 SMIAPP_REG_MK_U8(0x0a08)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_5 SMIAPP_REG_MK_U8(0x0a09)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_12 SMIAPP_REG_MK_U8(0x0a10)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_13 SMIAPP_REG_MK_U8(0x0a11)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_14 SMIAPP_REG_MK_U8(0x0a12)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_15 SMIAPP_REG_MK_U8(0x0a13)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_16 SMIAPP_REG_MK_U8(0x0a14)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_17 SMIAPP_REG_MK_U8(0x0a15)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_18 SMIAPP_REG_MK_U8(0x0a16)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_19 SMIAPP_REG_MK_U8(0x0a17)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_20 SMIAPP_REG_MK_U8(0x0a18)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_21 SMIAPP_REG_MK_U8(0x0a19)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_22 SMIAPP_REG_MK_U8(0x0a1a)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_23 SMIAPP_REG_MK_U8(0x0a1b)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_24 SMIAPP_REG_MK_U8(0x0a1c)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_25 SMIAPP_REG_MK_U8(0x0a1d)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_26 SMIAPP_REG_MK_U8(0x0a1e)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_27 SMIAPP_REG_MK_U8(0x0a1f)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_28 SMIAPP_REG_MK_U8(0x0a20)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_29 SMIAPP_REG_MK_U8(0x0a21)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_30 SMIAPP_REG_MK_U8(0x0a22)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_31 SMIAPP_REG_MK_U8(0x0a23)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_32 SMIAPP_REG_MK_U8(0x0a24)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_33 SMIAPP_REG_MK_U8(0x0a25)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_34 SMIAPP_REG_MK_U8(0x0a26)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_35 SMIAPP_REG_MK_U8(0x0a27)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_36 SMIAPP_REG_MK_U8(0x0a28)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_37 SMIAPP_REG_MK_U8(0x0a29)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_38 SMIAPP_REG_MK_U8(0x0a2a)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_39 SMIAPP_REG_MK_U8(0x0a2b)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_40 SMIAPP_REG_MK_U8(0x0a2c)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_41 SMIAPP_REG_MK_U8(0x0a2d)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_42 SMIAPP_REG_MK_U8(0x0a2e)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_43 SMIAPP_REG_MK_U8(0x0a2f)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_44 SMIAPP_REG_MK_U8(0x0a30)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_45 SMIAPP_REG_MK_U8(0x0a31)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_46 SMIAPP_REG_MK_U8(0x0a32)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_47 SMIAPP_REG_MK_U8(0x0a33)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_48 SMIAPP_REG_MK_U8(0x0a34)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_49 SMIAPP_REG_MK_U8(0x0a35)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_50 SMIAPP_REG_MK_U8(0x0a36)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_51 SMIAPP_REG_MK_U8(0x0a37)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_52 SMIAPP_REG_MK_U8(0x0a38)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_53 SMIAPP_REG_MK_U8(0x0a39)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_54 SMIAPP_REG_MK_U8(0x0a3a)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_55 SMIAPP_REG_MK_U8(0x0a3b)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_56 SMIAPP_REG_MK_U8(0x0a3c)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_57 SMIAPP_REG_MK_U8(0x0a3d)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_58 SMIAPP_REG_MK_U8(0x0a3e)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_59 SMIAPP_REG_MK_U8(0x0a3f)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_60 SMIAPP_REG_MK_U8(0x0a40)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_61 SMIAPP_REG_MK_U8(0x0a41)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_62 SMIAPP_REG_MK_U8(0x0a42)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_63 SMIAPP_REG_MK_U8(0x0a43)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_CTRL SMIAPP_REG_MK_U8(0x0a44)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_STATUS SMIAPP_REG_MK_U8(0x0a45)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_PAGE_SELECT SMIAPP_REG_MK_U8(0x0a46)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_0 SMIAPP_REG_MK_U8(0x0a48)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_1 SMIAPP_REG_MK_U8(0x0a49)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_2 SMIAPP_REG_MK_U8(0x0a4a)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_3 SMIAPP_REG_MK_U8(0x0a4b)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_4 SMIAPP_REG_MK_U8(0x0a4c)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_5 SMIAPP_REG_MK_U8(0x0a4d)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_6 SMIAPP_REG_MK_U8(0x0a4e)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_7 SMIAPP_REG_MK_U8(0x0a4f)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_8 SMIAPP_REG_MK_U8(0x0a50)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_9 SMIAPP_REG_MK_U8(0x0a51)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_10 SMIAPP_REG_MK_U8(0x0a52)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_11 SMIAPP_REG_MK_U8(0x0a53)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_12 SMIAPP_REG_MK_U8(0x0a54)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_13 SMIAPP_REG_MK_U8(0x0a55)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_14 SMIAPP_REG_MK_U8(0x0a56)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_15 SMIAPP_REG_MK_U8(0x0a57)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_16 SMIAPP_REG_MK_U8(0x0a58)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_17 SMIAPP_REG_MK_U8(0x0a59)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_18 SMIAPP_REG_MK_U8(0x0a5a)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_19 SMIAPP_REG_MK_U8(0x0a5b)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_20 SMIAPP_REG_MK_U8(0x0a5c)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_21 SMIAPP_REG_MK_U8(0x0a5d)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_22 SMIAPP_REG_MK_U8(0x0a5e)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_23 SMIAPP_REG_MK_U8(0x0a5f)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_24 SMIAPP_REG_MK_U8(0x0a60)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_25 SMIAPP_REG_MK_U8(0x0a61)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_26 SMIAPP_REG_MK_U8(0x0a62)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_27 SMIAPP_REG_MK_U8(0x0a63)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_28 SMIAPP_REG_MK_U8(0x0a64)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_29 SMIAPP_REG_MK_U8(0x0a65)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_30 SMIAPP_REG_MK_U8(0x0a66)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_31 SMIAPP_REG_MK_U8(0x0a67)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_32 SMIAPP_REG_MK_U8(0x0a68)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_33 SMIAPP_REG_MK_U8(0x0a69)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_34 SMIAPP_REG_MK_U8(0x0a6a)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_35 SMIAPP_REG_MK_U8(0x0a6b)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_36 SMIAPP_REG_MK_U8(0x0a6c)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_37 SMIAPP_REG_MK_U8(0x0a6d)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_38 SMIAPP_REG_MK_U8(0x0a6e)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_39 SMIAPP_REG_MK_U8(0x0a6f)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_40 SMIAPP_REG_MK_U8(0x0a70)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_41 SMIAPP_REG_MK_U8(0x0a71)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_42 SMIAPP_REG_MK_U8(0x0a72)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_43 SMIAPP_REG_MK_U8(0x0a73)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_44 SMIAPP_REG_MK_U8(0x0a74)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_45 SMIAPP_REG_MK_U8(0x0a75)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_46 SMIAPP_REG_MK_U8(0x0a76)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_47 SMIAPP_REG_MK_U8(0x0a77)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_48 SMIAPP_REG_MK_U8(0x0a78)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_49 SMIAPP_REG_MK_U8(0x0a79)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_50 SMIAPP_REG_MK_U8(0x0a7a)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_51 SMIAPP_REG_MK_U8(0x0a7b)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_52 SMIAPP_REG_MK_U8(0x0a7c)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_53 SMIAPP_REG_MK_U8(0x0a7d)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_54 SMIAPP_REG_MK_U8(0x0a7e)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_55 SMIAPP_REG_MK_U8(0x0a7f)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_56 SMIAPP_REG_MK_U8(0x0a80)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_57 SMIAPP_REG_MK_U8(0x0a81)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_58 SMIAPP_REG_MK_U8(0x0a82)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_59 SMIAPP_REG_MK_U8(0x0a83)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_60 SMIAPP_REG_MK_U8(0x0a84)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_61 SMIAPP_REG_MK_U8(0x0a85)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_62 SMIAPP_REG_MK_U8(0x0a86)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_63 SMIAPP_REG_MK_U8(0x0a87)
-#define SMIAPP_REG_U8_SHADING_CORRECTION_ENABLE SMIAPP_REG_MK_U8(0x0b00)
-#define SMIAPP_REG_U8_LUMINANCE_CORRECTION_LEVEL SMIAPP_REG_MK_U8(0x0b01)
-#define SMIAPP_REG_U8_GREEN_IMBALANCE_FILTER_ENABLE SMIAPP_REG_MK_U8(0x0b02)
-#define SMIAPP_REG_U8_GREEN_IMBALANCE_FILTER_WEIGHT SMIAPP_REG_MK_U8(0x0b03)
-#define SMIAPP_REG_U8_BLACK_LEVEL_CORRECTION_ENABLE SMIAPP_REG_MK_U8(0x0b04)
-#define SMIAPP_REG_U8_MAPPED_COUPLET_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b05)
-#define SMIAPP_REG_U8_SINGLE_DEFECT_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b06)
-#define SMIAPP_REG_U8_SINGLE_DEFECT_CORRECT_WEIGHT SMIAPP_REG_MK_U8(0x0b07)
-#define SMIAPP_REG_U8_DYNAMIC_COUPLET_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b08)
-#define SMIAPP_REG_U8_DYNAMIC_COUPLET_CORRECT_WEIGHT SMIAPP_REG_MK_U8(0x0b09)
-#define SMIAPP_REG_U8_COMBINED_DEFECT_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b0a)
-#define SMIAPP_REG_U8_COMBINED_DEFECT_CORRECT_WEIGHT SMIAPP_REG_MK_U8(0x0b0b)
-#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_ENABLE SMIAPP_REG_MK_U8(0x0b0c)
-#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_WEIGHT SMIAPP_REG_MK_U8(0x0b0d)
-#define SMIAPP_REG_U8_MAPPED_LINE_DEFECT_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b0e)
-#define SMIAPP_REG_U8_MAPPED_LINE_DEFECT_CORRECT_ADJUST SMIAPP_REG_MK_U8(0x0b0f)
-#define SMIAPP_REG_U8_MAPPED_COUPLET_CORRECT_ADJUST SMIAPP_REG_MK_U8(0x0b10)
-#define SMIAPP_REG_U8_MAPPED_TRIPLET_DEFECT_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b11)
-#define SMIAPP_REG_U8_MAPPED_TRIPLET_DEFECT_CORRECT_ADJUST SMIAPP_REG_MK_U8(0x0b12)
-#define SMIAPP_REG_U8_DYNAMIC_TRIPLET_DEFECT_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b13)
-#define SMIAPP_REG_U8_DYNAMIC_TRIPLET_DEFECT_CORRECT_ADJUST SMIAPP_REG_MK_U8(0x0b14)
-#define SMIAPP_REG_U8_DYNAMIC_LINE_DEFECT_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b15)
-#define SMIAPP_REG_U8_DYNAMIC_LINE_DEFECT_CORRECT_ADJUST SMIAPP_REG_MK_U8(0x0b16)
-#define SMIAPP_REG_U8_EDOF_MODE SMIAPP_REG_MK_U8(0x0b80)
-#define SMIAPP_REG_U8_SHARPNESS SMIAPP_REG_MK_U8(0x0b83)
-#define SMIAPP_REG_U8_DENOISING SMIAPP_REG_MK_U8(0x0b84)
-#define SMIAPP_REG_U8_MODULE_SPECIFIC SMIAPP_REG_MK_U8(0x0b85)
-#define SMIAPP_REG_U16_DEPTH_OF_FIELD SMIAPP_REG_MK_U16(0x0b86)
-#define SMIAPP_REG_U16_FOCUS_DISTANCE SMIAPP_REG_MK_U16(0x0b88)
-#define SMIAPP_REG_U8_ESTIMATION_MODE_CTRL SMIAPP_REG_MK_U8(0x0b8a)
-#define SMIAPP_REG_U16_COLOUR_TEMPERATURE SMIAPP_REG_MK_U16(0x0b8c)
-#define SMIAPP_REG_U16_ABSOLUTE_GAIN_GREENR SMIAPP_REG_MK_U16(0x0b8e)
-#define SMIAPP_REG_U16_ABSOLUTE_GAIN_RED SMIAPP_REG_MK_U16(0x0b90)
-#define SMIAPP_REG_U16_ABSOLUTE_GAIN_BLUE SMIAPP_REG_MK_U16(0x0b92)
-#define SMIAPP_REG_U16_ABSOLUTE_GAIN_GREENB SMIAPP_REG_MK_U16(0x0b94)
-#define SMIAPP_REG_U8_ESTIMATION_ZONE_MODE SMIAPP_REG_MK_U8(0x0bc0)
-#define SMIAPP_REG_U16_FIXED_ZONE_WEIGHTING SMIAPP_REG_MK_U16(0x0bc2)
-#define SMIAPP_REG_U16_CUSTOM_ZONE_X_START SMIAPP_REG_MK_U16(0x0bc4)
-#define SMIAPP_REG_U16_CUSTOM_ZONE_Y_START SMIAPP_REG_MK_U16(0x0bc6)
-#define SMIAPP_REG_U16_CUSTOM_ZONE_WIDTH SMIAPP_REG_MK_U16(0x0bc8)
-#define SMIAPP_REG_U16_CUSTOM_ZONE_HEIGHT SMIAPP_REG_MK_U16(0x0bca)
-#define SMIAPP_REG_U8_GLOBAL_RESET_CTRL1 SMIAPP_REG_MK_U8(0x0c00)
-#define SMIAPP_REG_U8_GLOBAL_RESET_CTRL2 SMIAPP_REG_MK_U8(0x0c01)
-#define SMIAPP_REG_U8_GLOBAL_RESET_MODE_CONFIG_1 SMIAPP_REG_MK_U8(0x0c02)
-#define SMIAPP_REG_U8_GLOBAL_RESET_MODE_CONFIG_2 SMIAPP_REG_MK_U8(0x0c03)
-#define SMIAPP_REG_U16_TRDY_CTRL SMIAPP_REG_MK_U16(0x0c04)
-#define SMIAPP_REG_U16_TRDOUT_CTRL SMIAPP_REG_MK_U16(0x0c06)
-#define SMIAPP_REG_U16_TSHUTTER_STROBE_DELAY_CTRL SMIAPP_REG_MK_U16(0x0c08)
-#define SMIAPP_REG_U16_TSHUTTER_STROBE_WIDTH_CTRL SMIAPP_REG_MK_U16(0x0c0a)
-#define SMIAPP_REG_U16_TFLASH_STROBE_DELAY_CTRL SMIAPP_REG_MK_U16(0x0c0c)
-#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_HIGH_CTRL SMIAPP_REG_MK_U16(0x0c0e)
-#define SMIAPP_REG_U16_TGRST_INTERVAL_CTRL SMIAPP_REG_MK_U16(0x0c10)
-#define SMIAPP_REG_U8_FLASH_STROBE_ADJUSTMENT SMIAPP_REG_MK_U8(0x0c12)
-#define SMIAPP_REG_U16_FLASH_STROBE_START_POINT SMIAPP_REG_MK_U16(0x0c14)
-#define SMIAPP_REG_U16_TFLASH_STROBE_DELAY_RS_CTRL SMIAPP_REG_MK_U16(0x0c16)
-#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_HIGH_RS_CTRL SMIAPP_REG_MK_U16(0x0c18)
-#define SMIAPP_REG_U8_FLASH_MODE_RS SMIAPP_REG_MK_U8(0x0c1a)
-#define SMIAPP_REG_U8_FLASH_TRIGGER_RS SMIAPP_REG_MK_U8(0x0c1b)
-#define SMIAPP_REG_U8_FLASH_STATUS SMIAPP_REG_MK_U8(0x0c1c)
-#define SMIAPP_REG_U8_SA_STROBE_MODE SMIAPP_REG_MK_U8(0x0c1d)
-#define SMIAPP_REG_U16_SA_STROBE_START_POINT SMIAPP_REG_MK_U16(0x0c1e)
-#define SMIAPP_REG_U16_TSA_STROBE_DELAY_CTRL SMIAPP_REG_MK_U16(0x0c20)
-#define SMIAPP_REG_U16_TSA_STROBE_WIDTH_CTRL SMIAPP_REG_MK_U16(0x0c22)
-#define SMIAPP_REG_U8_SA_STROBE_TRIGGER SMIAPP_REG_MK_U8(0x0c24)
-#define SMIAPP_REG_U8_SPECIAL_ACTUATOR_STATUS SMIAPP_REG_MK_U8(0x0c25)
-#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH2_HIGH_RS_CTRL SMIAPP_REG_MK_U16(0x0c26)
-#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_LOW_RS_CTRL SMIAPP_REG_MK_U16(0x0c28)
-#define SMIAPP_REG_U8_TFLASH_STROBE_COUNT_RS_CTRL SMIAPP_REG_MK_U8(0x0c2a)
-#define SMIAPP_REG_U8_TFLASH_STROBE_COUNT_CTRL SMIAPP_REG_MK_U8(0x0c2b)
-#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH2_HIGH_CTRL SMIAPP_REG_MK_U16(0x0c2c)
-#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_LOW_CTRL SMIAPP_REG_MK_U16(0x0c2e)
-#define SMIAPP_REG_U8_LOW_LEVEL_CTRL SMIAPP_REG_MK_U8(0x0c80)
-#define SMIAPP_REG_U16_MAIN_TRIGGER_REF_POINT SMIAPP_REG_MK_U16(0x0c82)
-#define SMIAPP_REG_U16_MAIN_TRIGGER_T3 SMIAPP_REG_MK_U16(0x0c84)
-#define SMIAPP_REG_U8_MAIN_TRIGGER_COUNT SMIAPP_REG_MK_U8(0x0c86)
-#define SMIAPP_REG_U16_PHASE1_TRIGGER_T3 SMIAPP_REG_MK_U16(0x0c88)
-#define SMIAPP_REG_U8_PHASE1_TRIGGER_COUNT SMIAPP_REG_MK_U8(0x0c8a)
-#define SMIAPP_REG_U16_PHASE2_TRIGGER_T3 SMIAPP_REG_MK_U16(0x0c8c)
-#define SMIAPP_REG_U8_PHASE2_TRIGGER_COUNT SMIAPP_REG_MK_U8(0x0c8e)
-#define SMIAPP_REG_U8_MECH_SHUTTER_CTRL SMIAPP_REG_MK_U8(0x0d00)
-#define SMIAPP_REG_U8_OPERATION_MODE SMIAPP_REG_MK_U8(0x0d01)
-#define SMIAPP_REG_U8_ACT_STATE1 SMIAPP_REG_MK_U8(0x0d02)
-#define SMIAPP_REG_U8_ACT_STATE2 SMIAPP_REG_MK_U8(0x0d03)
-#define SMIAPP_REG_U16_FOCUS_CHANGE SMIAPP_REG_MK_U16(0x0d80)
-#define SMIAPP_REG_U16_FOCUS_CHANGE_CONTROL SMIAPP_REG_MK_U16(0x0d82)
-#define SMIAPP_REG_U16_FOCUS_CHANGE_NUMBER_PHASE1 SMIAPP_REG_MK_U16(0x0d84)
-#define SMIAPP_REG_U16_FOCUS_CHANGE_NUMBER_PHASE2 SMIAPP_REG_MK_U16(0x0d86)
-#define SMIAPP_REG_U8_STROBE_COUNT_PHASE1 SMIAPP_REG_MK_U8(0x0d88)
-#define SMIAPP_REG_U8_STROBE_COUNT_PHASE2 SMIAPP_REG_MK_U8(0x0d89)
-#define SMIAPP_REG_U8_POSITION SMIAPP_REG_MK_U8(0x0d8a)
-#define SMIAPP_REG_U8_BRACKETING_LUT_CONTROL SMIAPP_REG_MK_U8(0x0e00)
-#define SMIAPP_REG_U8_BRACKETING_LUT_MODE SMIAPP_REG_MK_U8(0x0e01)
-#define SMIAPP_REG_U8_BRACKETING_LUT_ENTRY_CONTROL SMIAPP_REG_MK_U8(0x0e02)
-#define SMIAPP_REG_U8_LUT_PARAMETERS_START SMIAPP_REG_MK_U8(0x0e10)
-#define SMIAPP_REG_U8_LUT_PARAMETERS_END SMIAPP_REG_MK_U8(0x0eff)
-#define SMIAPP_REG_U16_INTEGRATION_TIME_CAPABILITY SMIAPP_REG_MK_U16(0x1000)
-#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MIN SMIAPP_REG_MK_U16(0x1004)
-#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MAX_MARGIN SMIAPP_REG_MK_U16(0x1006)
-#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN SMIAPP_REG_MK_U16(0x1008)
-#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN SMIAPP_REG_MK_U16(0x100a)
-#define SMIAPP_REG_U16_DIGITAL_GAIN_CAPABILITY SMIAPP_REG_MK_U16(0x1080)
-#define SMIAPP_REG_U16_DIGITAL_GAIN_MIN SMIAPP_REG_MK_U16(0x1084)
-#define SMIAPP_REG_U16_DIGITAL_GAIN_MAX SMIAPP_REG_MK_U16(0x1086)
-#define SMIAPP_REG_U16_DIGITAL_GAIN_STEP_SIZE SMIAPP_REG_MK_U16(0x1088)
-#define SMIAPP_REG_F32_MIN_EXT_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1100)
-#define SMIAPP_REG_F32_MAX_EXT_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1104)
-#define SMIAPP_REG_U16_MIN_PRE_PLL_CLK_DIV SMIAPP_REG_MK_U16(0x1108)
-#define SMIAPP_REG_U16_MAX_PRE_PLL_CLK_DIV SMIAPP_REG_MK_U16(0x110a)
-#define SMIAPP_REG_F32_MIN_PLL_IP_FREQ_HZ SMIAPP_REG_MK_F32(0x110c)
-#define SMIAPP_REG_F32_MAX_PLL_IP_FREQ_HZ SMIAPP_REG_MK_F32(0x1110)
-#define SMIAPP_REG_U16_MIN_PLL_MULTIPLIER SMIAPP_REG_MK_U16(0x1114)
-#define SMIAPP_REG_U16_MAX_PLL_MULTIPLIER SMIAPP_REG_MK_U16(0x1116)
-#define SMIAPP_REG_F32_MIN_PLL_OP_FREQ_HZ SMIAPP_REG_MK_F32(0x1118)
-#define SMIAPP_REG_F32_MAX_PLL_OP_FREQ_HZ SMIAPP_REG_MK_F32(0x111c)
-#define SMIAPP_REG_U16_MIN_VT_SYS_CLK_DIV SMIAPP_REG_MK_U16(0x1120)
-#define SMIAPP_REG_U16_MAX_VT_SYS_CLK_DIV SMIAPP_REG_MK_U16(0x1122)
-#define SMIAPP_REG_F32_MIN_VT_SYS_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1124)
-#define SMIAPP_REG_F32_MAX_VT_SYS_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1128)
-#define SMIAPP_REG_F32_MIN_VT_PIX_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x112c)
-#define SMIAPP_REG_F32_MAX_VT_PIX_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1130)
-#define SMIAPP_REG_U16_MIN_VT_PIX_CLK_DIV SMIAPP_REG_MK_U16(0x1134)
-#define SMIAPP_REG_U16_MAX_VT_PIX_CLK_DIV SMIAPP_REG_MK_U16(0x1136)
-#define SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES SMIAPP_REG_MK_U16(0x1140)
-#define SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES SMIAPP_REG_MK_U16(0x1142)
-#define SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK SMIAPP_REG_MK_U16(0x1144)
-#define SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK SMIAPP_REG_MK_U16(0x1146)
-#define SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK SMIAPP_REG_MK_U16(0x1148)
-#define SMIAPP_REG_U16_MIN_FRAME_BLANKING_LINES SMIAPP_REG_MK_U16(0x114a)
-#define SMIAPP_REG_U8_MIN_LINE_LENGTH_PCK_STEP_SIZE SMIAPP_REG_MK_U8(0x114c)
-#define SMIAPP_REG_U16_MIN_OP_SYS_CLK_DIV SMIAPP_REG_MK_U16(0x1160)
-#define SMIAPP_REG_U16_MAX_OP_SYS_CLK_DIV SMIAPP_REG_MK_U16(0x1162)
-#define SMIAPP_REG_F32_MIN_OP_SYS_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1164)
-#define SMIAPP_REG_F32_MAX_OP_SYS_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1168)
-#define SMIAPP_REG_U16_MIN_OP_PIX_CLK_DIV SMIAPP_REG_MK_U16(0x116c)
-#define SMIAPP_REG_U16_MAX_OP_PIX_CLK_DIV SMIAPP_REG_MK_U16(0x116e)
-#define SMIAPP_REG_F32_MIN_OP_PIX_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1170)
-#define SMIAPP_REG_F32_MAX_OP_PIX_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1174)
-#define SMIAPP_REG_U16_X_ADDR_MIN SMIAPP_REG_MK_U16(0x1180)
-#define SMIAPP_REG_U16_Y_ADDR_MIN SMIAPP_REG_MK_U16(0x1182)
-#define SMIAPP_REG_U16_X_ADDR_MAX SMIAPP_REG_MK_U16(0x1184)
-#define SMIAPP_REG_U16_Y_ADDR_MAX SMIAPP_REG_MK_U16(0x1186)
-#define SMIAPP_REG_U16_MIN_X_OUTPUT_SIZE SMIAPP_REG_MK_U16(0x1188)
-#define SMIAPP_REG_U16_MIN_Y_OUTPUT_SIZE SMIAPP_REG_MK_U16(0x118a)
-#define SMIAPP_REG_U16_MAX_X_OUTPUT_SIZE SMIAPP_REG_MK_U16(0x118c)
-#define SMIAPP_REG_U16_MAX_Y_OUTPUT_SIZE SMIAPP_REG_MK_U16(0x118e)
-#define SMIAPP_REG_U16_MIN_EVEN_INC SMIAPP_REG_MK_U16(0x11c0)
-#define SMIAPP_REG_U16_MAX_EVEN_INC SMIAPP_REG_MK_U16(0x11c2)
-#define SMIAPP_REG_U16_MIN_ODD_INC SMIAPP_REG_MK_U16(0x11c4)
-#define SMIAPP_REG_U16_MAX_ODD_INC SMIAPP_REG_MK_U16(0x11c6)
-#define SMIAPP_REG_U16_SCALING_CAPABILITY SMIAPP_REG_MK_U16(0x1200)
-#define SMIAPP_REG_U16_SCALER_M_MIN SMIAPP_REG_MK_U16(0x1204)
-#define SMIAPP_REG_U16_SCALER_M_MAX SMIAPP_REG_MK_U16(0x1206)
-#define SMIAPP_REG_U16_SCALER_N_MIN SMIAPP_REG_MK_U16(0x1208)
-#define SMIAPP_REG_U16_SCALER_N_MAX SMIAPP_REG_MK_U16(0x120a)
-#define SMIAPP_REG_U16_SPATIAL_SAMPLING_CAPABILITY SMIAPP_REG_MK_U16(0x120c)
-#define SMIAPP_REG_U8_DIGITAL_CROP_CAPABILITY SMIAPP_REG_MK_U8(0x120e)
-#define SMIAPP_REG_U16_COMPRESSION_CAPABILITY SMIAPP_REG_MK_U16(0x1300)
-#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINRED SMIAPP_REG_MK_U16(0x1400)
-#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINRED SMIAPP_REG_MK_U16(0x1402)
-#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINRED SMIAPP_REG_MK_U16(0x1404)
-#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINGREEN SMIAPP_REG_MK_U16(0x1406)
-#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINGREEN SMIAPP_REG_MK_U16(0x1408)
-#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINGREEN SMIAPP_REG_MK_U16(0x140a)
-#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINBLUE SMIAPP_REG_MK_U16(0x140c)
-#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINBLUE SMIAPP_REG_MK_U16(0x140e)
-#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINBLUE SMIAPP_REG_MK_U16(0x1410)
-#define SMIAPP_REG_U16_FIFO_SIZE_PIXELS SMIAPP_REG_MK_U16(0x1500)
-#define SMIAPP_REG_U8_FIFO_SUPPORT_CAPABILITY SMIAPP_REG_MK_U8(0x1502)
-#define SMIAPP_REG_U8_DPHY_CTRL_CAPABILITY SMIAPP_REG_MK_U8(0x1600)
-#define SMIAPP_REG_U8_CSI_LANE_MODE_CAPABILITY SMIAPP_REG_MK_U8(0x1601)
-#define SMIAPP_REG_U8_CSI_SIGNALLING_MODE_CAPABILITY SMIAPP_REG_MK_U8(0x1602)
-#define SMIAPP_REG_U8_FAST_STANDBY_CAPABILITY SMIAPP_REG_MK_U8(0x1603)
-#define SMIAPP_REG_U8_CCI_ADDRESS_CONTROL_CAPABILITY SMIAPP_REG_MK_U8(0x1604)
-#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_1_LANE_MODE_MBPS SMIAPP_REG_MK_U32(0x1608)
-#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_2_LANE_MODE_MBPS SMIAPP_REG_MK_U32(0x160c)
-#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_3_LANE_MODE_MBPS SMIAPP_REG_MK_U32(0x1610)
-#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_4_LANE_MODE_MBPS SMIAPP_REG_MK_U32(0x1614)
-#define SMIAPP_REG_U8_TEMP_SENSOR_CAPABILITY SMIAPP_REG_MK_U8(0x1618)
-#define SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES_BIN SMIAPP_REG_MK_U16(0x1700)
-#define SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES_BIN SMIAPP_REG_MK_U16(0x1702)
-#define SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK_BIN SMIAPP_REG_MK_U16(0x1704)
-#define SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK_BIN SMIAPP_REG_MK_U16(0x1706)
-#define SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK_BIN SMIAPP_REG_MK_U16(0x1708)
-#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN_BIN SMIAPP_REG_MK_U16(0x170a)
-#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN SMIAPP_REG_MK_U16(0x170c)
-#define SMIAPP_REG_U8_BINNING_CAPABILITY SMIAPP_REG_MK_U8(0x1710)
-#define SMIAPP_REG_U8_BINNING_WEIGHTING_CAPABILITY SMIAPP_REG_MK_U8(0x1711)
-#define SMIAPP_REG_U8_BINNING_SUBTYPES SMIAPP_REG_MK_U8(0x1712)
-#define SMIAPP_REG_U8_BINNING_TYPE_n(n) SMIAPP_REG_MK_U8(0x1713 + (n)) /* 1 <= n <= 237 */
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_CAPABILITY SMIAPP_REG_MK_U8(0x1800)
-#define SMIAPP_REG_U8_SHADING_CORRECTION_CAPABILITY SMIAPP_REG_MK_U8(0x1900)
-#define SMIAPP_REG_U8_GREEN_IMBALANCE_CAPABILITY SMIAPP_REG_MK_U8(0x1901)
-#define SMIAPP_REG_U8_BLACK_LEVEL_CAPABILITY SMIAPP_REG_MK_U8(0x1902)
-#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_CAPABILITY SMIAPP_REG_MK_U8(0x1903)
-#define SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY SMIAPP_REG_MK_U16(0x1904)
-#define SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY_2 SMIAPP_REG_MK_U16(0x1906)
-#define SMIAPP_REG_U8_EDOF_CAPABILITY SMIAPP_REG_MK_U8(0x1980)
-#define SMIAPP_REG_U8_ESTIMATION_FRAMES SMIAPP_REG_MK_U8(0x1981)
-#define SMIAPP_REG_U8_SUPPORTS_SHARPNESS_ADJ SMIAPP_REG_MK_U8(0x1982)
-#define SMIAPP_REG_U8_SUPPORTS_DENOISING_ADJ SMIAPP_REG_MK_U8(0x1983)
-#define SMIAPP_REG_U8_SUPPORTS_MODULE_SPECIFIC_ADJ SMIAPP_REG_MK_U8(0x1984)
-#define SMIAPP_REG_U8_SUPPORTS_DEPTH_OF_FIELD_ADJ SMIAPP_REG_MK_U8(0x1985)
-#define SMIAPP_REG_U8_SUPPORTS_FOCUS_DISTANCE_ADJ SMIAPP_REG_MK_U8(0x1986)
-#define SMIAPP_REG_U8_COLOUR_FEEDBACK_CAPABILITY SMIAPP_REG_MK_U8(0x1987)
-#define SMIAPP_REG_U8_EDOF_SUPPORT_AB_NXM SMIAPP_REG_MK_U8(0x1988)
-#define SMIAPP_REG_U8_ESTIMATION_MODE_CAPABILITY SMIAPP_REG_MK_U8(0x19c0)
-#define SMIAPP_REG_U8_ESTIMATION_ZONE_CAPABILITY SMIAPP_REG_MK_U8(0x19c1)
-#define SMIAPP_REG_U16_EST_DEPTH_OF_FIELD SMIAPP_REG_MK_U16(0x19c2)
-#define SMIAPP_REG_U16_EST_FOCUS_DISTANCE SMIAPP_REG_MK_U16(0x19c4)
-#define SMIAPP_REG_U16_CAPABILITY_TRDY_MIN SMIAPP_REG_MK_U16(0x1a00)
-#define SMIAPP_REG_U8_FLASH_MODE_CAPABILITY SMIAPP_REG_MK_U8(0x1a02)
-#define SMIAPP_REG_U16_MECH_SHUT_AND_ACT_START_ADDR SMIAPP_REG_MK_U16(0x1b02)
-#define SMIAPP_REG_U8_ACTUATOR_CAPABILITY SMIAPP_REG_MK_U8(0x1b04)
-#define SMIAPP_REG_U16_ACTUATOR_TYPE SMIAPP_REG_MK_U16(0x1b40)
-#define SMIAPP_REG_U8_AF_DEVICE_ADDRESS SMIAPP_REG_MK_U8(0x1b42)
-#define SMIAPP_REG_U16_FOCUS_CHANGE_ADDRESS SMIAPP_REG_MK_U16(0x1b44)
-#define SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_1 SMIAPP_REG_MK_U8(0x1c00)
-#define SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_2 SMIAPP_REG_MK_U8(0x1c01)
-#define SMIAPP_REG_U8_BRACKETING_LUT_SIZE SMIAPP_REG_MK_U8(0x1c02)
+/* Register addresses */
+#define SMIAPP_REG_U16_MODEL_ID (0x0000 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_REVISION_NUMBER_MAJOR 0x0002
+#define SMIAPP_REG_U8_MANUFACTURER_ID 0x0003
+#define SMIAPP_REG_U8_SMIA_VERSION 0x0004
+#define SMIAPP_REG_U8_FRAME_COUNT 0x0005
+#define SMIAPP_REG_U8_PIXEL_ORDER 0x0006
+#define SMIAPP_REG_U16_DATA_PEDESTAL (0x0008 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_PIXEL_DEPTH 0x000c
+#define SMIAPP_REG_U8_REVISION_NUMBER_MINOR 0x0010
+#define SMIAPP_REG_U8_SMIAPP_VERSION 0x0011
+#define SMIAPP_REG_U8_MODULE_DATE_YEAR 0x0012
+#define SMIAPP_REG_U8_MODULE_DATE_MONTH 0x0013
+#define SMIAPP_REG_U8_MODULE_DATE_DAY 0x0014
+#define SMIAPP_REG_U8_MODULE_DATE_PHASE 0x0015
+#define SMIAPP_REG_U16_SENSOR_MODEL_ID (0x0016 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_SENSOR_REVISION_NUMBER 0x0018
+#define SMIAPP_REG_U8_SENSOR_MANUFACTURER_ID 0x0019
+#define SMIAPP_REG_U8_SENSOR_FIRMWARE_VERSION 0x001a
+#define SMIAPP_REG_U32_SERIAL_NUMBER (0x001c | CCS_FL_32BIT)
+#define SMIAPP_REG_U8_FRAME_FORMAT_MODEL_TYPE 0x0040
+#define SMIAPP_REG_U8_FRAME_FORMAT_MODEL_SUBTYPE 0x0041
+#define SMIAPP_REG_U16_FRAME_FORMAT_DESCRIPTOR_2(n) ((0x0042 + ((n) << 1)) | CCS_FL_16BIT) /* 0 <= n <= 14 */
+#define SMIAPP_REG_U32_FRAME_FORMAT_DESCRIPTOR_4(n) ((0x0060 + ((n) << 2)) | CCS_FL_32BIT) /* 0 <= n <= 7 */
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CAPABILITY (0x0080 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MIN (0x0084 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MAX (0x0086 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_STEP (0x0088 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_TYPE (0x008a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_M0 (0x008c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_C0 (0x008e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_M1 (0x0090 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_C1 (0x0092 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_DATA_FORMAT_MODEL_TYPE 0x00c0
+#define SMIAPP_REG_U8_DATA_FORMAT_MODEL_SUBTYPE 0x00c1
+#define SMIAPP_REG_U16_DATA_FORMAT_DESCRIPTOR(n) ((0x00c2 + ((n) << 1)) | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_MODE_SELECT 0x0100
+#define SMIAPP_REG_U8_IMAGE_ORIENTATION 0x0101
+#define SMIAPP_REG_U8_SOFTWARE_RESET 0x0103
+#define SMIAPP_REG_U8_GROUPED_PARAMETER_HOLD 0x0104
+#define SMIAPP_REG_U8_MASK_CORRUPTED_FRAMES 0x0105
+#define SMIAPP_REG_U8_FAST_STANDBY_CTRL 0x0106
+#define SMIAPP_REG_U8_CCI_ADDRESS_CONTROL 0x0107
+#define SMIAPP_REG_U8_2ND_CCI_IF_CONTROL 0x0108
+#define SMIAPP_REG_U8_2ND_CCI_ADDRESS_CONTROL 0x0109
+#define SMIAPP_REG_U8_CSI_CHANNEL_IDENTIFIER 0x0110
+#define SMIAPP_REG_U8_CSI_SIGNALLING_MODE 0x0111
+#define SMIAPP_REG_U16_CSI_DATA_FORMAT (0x0112 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_CSI_LANE_MODE 0x0114
+#define SMIAPP_REG_U8_CSI2_10_TO_8_DT 0x0115
+#define SMIAPP_REG_U8_CSI2_10_TO_7_DT 0x0116
+#define SMIAPP_REG_U8_CSI2_10_TO_6_DT 0x0117
+#define SMIAPP_REG_U8_CSI2_12_TO_8_DT 0x0118
+#define SMIAPP_REG_U8_CSI2_12_TO_7_DT 0x0119
+#define SMIAPP_REG_U8_CSI2_12_TO_6_DT 0x011a
+#define SMIAPP_REG_U8_CSI2_14_TO_10_DT 0x011b
+#define SMIAPP_REG_U8_CSI2_14_TO_8_DT 0x011c
+#define SMIAPP_REG_U8_CSI2_16_TO_10_DT 0x011d
+#define SMIAPP_REG_U8_CSI2_16_TO_8_DT 0x011e
+#define SMIAPP_REG_U8_GAIN_MODE 0x0120
+#define SMIAPP_REG_U16_VANA_VOLTAGE (0x0130 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_VDIG_VOLTAGE (0x0132 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_VIO_VOLTAGE (0x0134 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_EXTCLK_FREQUENCY_MHZ (0x0136 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_TEMP_SENSOR_CONTROL 0x0138
+#define SMIAPP_REG_U8_TEMP_SENSOR_MODE 0x0139
+#define SMIAPP_REG_U8_TEMP_SENSOR_OUTPUT 0x013a
+#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME (0x0200 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME (0x0202 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GLOBAL (0x0204 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GREENR (0x0206 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_RED (0x0208 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_BLUE (0x020a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GREENB (0x020c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_GREENR (0x020e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_RED (0x0210 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_BLUE (0x0212 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_GREENB (0x0214 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_VT_PIX_CLK_DIV (0x0300 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_VT_SYS_CLK_DIV (0x0302 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_PRE_PLL_CLK_DIV (0x0304 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_PLL_MULTIPLIER (0x0306 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_OP_PIX_CLK_DIV (0x0308 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_OP_SYS_CLK_DIV (0x030a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FRAME_LENGTH_LINES (0x0340 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_LINE_LENGTH_PCK (0x0342 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_X_ADDR_START (0x0344 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_Y_ADDR_START (0x0346 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_X_ADDR_END (0x0348 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_Y_ADDR_END (0x034a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_X_OUTPUT_SIZE (0x034c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_Y_OUTPUT_SIZE (0x034e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_X_EVEN_INC (0x0380 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_X_ODD_INC (0x0382 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_Y_EVEN_INC (0x0384 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_Y_ODD_INC (0x0386 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALING_MODE (0x0400 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SPATIAL_SAMPLING (0x0402 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALE_M (0x0404 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALE_N (0x0406 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_CROP_X_OFFSET (0x0408 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_CROP_Y_OFFSET (0x040a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_WIDTH (0x040c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_HEIGHT (0x040e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_COMPRESSION_MODE (0x0500 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TEST_PATTERN_MODE (0x0600 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TEST_DATA_RED (0x0602 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TEST_DATA_GREENR (0x0604 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TEST_DATA_BLUE (0x0606 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TEST_DATA_GREENB (0x0608 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_HORIZONTAL_CURSOR_WIDTH (0x060a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_HORIZONTAL_CURSOR_POSITION (0x060c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_VERTICAL_CURSOR_WIDTH (0x060e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_VERTICAL_CURSOR_POSITION (0x0610 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FIFO_WATER_MARK_PIXELS (0x0700 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_TCLK_POST 0x0800
+#define SMIAPP_REG_U8_THS_PREPARE 0x0801
+#define SMIAPP_REG_U8_THS_ZERO_MIN 0x0802
+#define SMIAPP_REG_U8_THS_TRAIL 0x0803
+#define SMIAPP_REG_U8_TCLK_TRAIL_MIN 0x0804
+#define SMIAPP_REG_U8_TCLK_PREPARE 0x0805
+#define SMIAPP_REG_U8_TCLK_ZERO 0x0806
+#define SMIAPP_REG_U8_TLPX 0x0807
+#define SMIAPP_REG_U8_DPHY_CTRL 0x0808
+#define SMIAPP_REG_U32_REQUESTED_LINK_BIT_RATE_MBPS (0x0820 | CCS_FL_32BIT)
+#define SMIAPP_REG_U8_BINNING_MODE 0x0900
+#define SMIAPP_REG_U8_BINNING_TYPE 0x0901
+#define SMIAPP_REG_U8_BINNING_WEIGHTING 0x0902
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_CTRL 0x0a00
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_STATUS 0x0a01
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_PAGE_SELECT 0x0a02
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_0 0x0a04
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_1 0x0a05
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_2 0x0a06
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_3 0x0a07
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_4 0x0a08
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_5 0x0a09
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_12 0x0a10
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_13 0x0a11
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_14 0x0a12
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_15 0x0a13
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_16 0x0a14
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_17 0x0a15
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_18 0x0a16
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_19 0x0a17
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_20 0x0a18
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_21 0x0a19
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_22 0x0a1a
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_23 0x0a1b
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_24 0x0a1c
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_25 0x0a1d
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_26 0x0a1e
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_27 0x0a1f
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_28 0x0a20
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_29 0x0a21
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_30 0x0a22
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_31 0x0a23
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_32 0x0a24
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_33 0x0a25
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_34 0x0a26
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_35 0x0a27
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_36 0x0a28
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_37 0x0a29
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_38 0x0a2a
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_39 0x0a2b
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_40 0x0a2c
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_41 0x0a2d
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_42 0x0a2e
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_43 0x0a2f
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_44 0x0a30
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_45 0x0a31
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_46 0x0a32
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_47 0x0a33
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_48 0x0a34
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_49 0x0a35
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_50 0x0a36
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_51 0x0a37
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_52 0x0a38
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_53 0x0a39
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_54 0x0a3a
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_55 0x0a3b
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_56 0x0a3c
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_57 0x0a3d
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_58 0x0a3e
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_59 0x0a3f
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_60 0x0a40
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_61 0x0a41
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_62 0x0a42
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_63 0x0a43
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_CTRL 0x0a44
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_STATUS 0x0a45
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_PAGE_SELECT 0x0a46
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_0 0x0a48
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_1 0x0a49
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_2 0x0a4a
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_3 0x0a4b
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_4 0x0a4c
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_5 0x0a4d
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_6 0x0a4e
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_7 0x0a4f
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_8 0x0a50
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_9 0x0a51
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_10 0x0a52
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_11 0x0a53
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_12 0x0a54
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_13 0x0a55
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_14 0x0a56
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_15 0x0a57
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_16 0x0a58
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_17 0x0a59
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_18 0x0a5a
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_19 0x0a5b
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_20 0x0a5c
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_21 0x0a5d
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_22 0x0a5e
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_23 0x0a5f
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_24 0x0a60
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_25 0x0a61
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_26 0x0a62
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_27 0x0a63
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_28 0x0a64
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_29 0x0a65
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_30 0x0a66
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_31 0x0a67
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_32 0x0a68
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_33 0x0a69
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_34 0x0a6a
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_35 0x0a6b
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_36 0x0a6c
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_37 0x0a6d
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_38 0x0a6e
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_39 0x0a6f
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_40 0x0a70
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_41 0x0a71
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_42 0x0a72
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_43 0x0a73
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_44 0x0a74
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_45 0x0a75
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_46 0x0a76
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_47 0x0a77
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_48 0x0a78
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_49 0x0a79
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_50 0x0a7a
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_51 0x0a7b
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_52 0x0a7c
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_53 0x0a7d
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_54 0x0a7e
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_55 0x0a7f
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_56 0x0a80
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_57 0x0a81
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_58 0x0a82
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_59 0x0a83
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_60 0x0a84
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_61 0x0a85
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_62 0x0a86
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_63 0x0a87
+#define SMIAPP_REG_U8_SHADING_CORRECTION_ENABLE 0x0b00
+#define SMIAPP_REG_U8_LUMINANCE_CORRECTION_LEVEL 0x0b01
+#define SMIAPP_REG_U8_GREEN_IMBALANCE_FILTER_ENABLE 0x0b02
+#define SMIAPP_REG_U8_GREEN_IMBALANCE_FILTER_WEIGHT 0x0b03
+#define SMIAPP_REG_U8_BLACK_LEVEL_CORRECTION_ENABLE 0x0b04
+#define SMIAPP_REG_U8_MAPPED_COUPLET_CORRECT_ENABLE 0x0b05
+#define SMIAPP_REG_U8_SINGLE_DEFECT_CORRECT_ENABLE 0x0b06
+#define SMIAPP_REG_U8_SINGLE_DEFECT_CORRECT_WEIGHT 0x0b07
+#define SMIAPP_REG_U8_DYNAMIC_COUPLET_CORRECT_ENABLE 0x0b08
+#define SMIAPP_REG_U8_DYNAMIC_COUPLET_CORRECT_WEIGHT 0x0b09
+#define SMIAPP_REG_U8_COMBINED_DEFECT_CORRECT_ENABLE 0x0b0a
+#define SMIAPP_REG_U8_COMBINED_DEFECT_CORRECT_WEIGHT 0x0b0b
+#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_ENABLE 0x0b0c
+#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_WEIGHT 0x0b0d
+#define SMIAPP_REG_U8_MAPPED_LINE_DEFECT_CORRECT_ENABLE 0x0b0e
+#define SMIAPP_REG_U8_MAPPED_LINE_DEFECT_CORRECT_ADJUST 0x0b0f
+#define SMIAPP_REG_U8_MAPPED_COUPLET_CORRECT_ADJUST 0x0b10
+#define SMIAPP_REG_U8_MAPPED_TRIPLET_DEFECT_CORRECT_ENABLE 0x0b11
+#define SMIAPP_REG_U8_MAPPED_TRIPLET_DEFECT_CORRECT_ADJUST 0x0b12
+#define SMIAPP_REG_U8_DYNAMIC_TRIPLET_DEFECT_CORRECT_ENABLE 0x0b13
+#define SMIAPP_REG_U8_DYNAMIC_TRIPLET_DEFECT_CORRECT_ADJUST 0x0b14
+#define SMIAPP_REG_U8_DYNAMIC_LINE_DEFECT_CORRECT_ENABLE 0x0b15
+#define SMIAPP_REG_U8_DYNAMIC_LINE_DEFECT_CORRECT_ADJUST 0x0b16
+#define SMIAPP_REG_U8_EDOF_MODE 0x0b80
+#define SMIAPP_REG_U8_SHARPNESS 0x0b83
+#define SMIAPP_REG_U8_DENOISING 0x0b84
+#define SMIAPP_REG_U8_MODULE_SPECIFIC 0x0b85
+#define SMIAPP_REG_U16_DEPTH_OF_FIELD (0x0b86 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FOCUS_DISTANCE (0x0b88 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_ESTIMATION_MODE_CTRL 0x0b8a
+#define SMIAPP_REG_U16_COLOUR_TEMPERATURE (0x0b8c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ABSOLUTE_GAIN_GREENR (0x0b8e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ABSOLUTE_GAIN_RED (0x0b90 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ABSOLUTE_GAIN_BLUE (0x0b92 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ABSOLUTE_GAIN_GREENB (0x0b94 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_ESTIMATION_ZONE_MODE 0x0bc0
+#define SMIAPP_REG_U16_FIXED_ZONE_WEIGHTING (0x0bc2 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_CUSTOM_ZONE_X_START (0x0bc4 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_CUSTOM_ZONE_Y_START (0x0bc6 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_CUSTOM_ZONE_WIDTH (0x0bc8 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_CUSTOM_ZONE_HEIGHT (0x0bca | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_GLOBAL_RESET_CTRL1 0x0c00
+#define SMIAPP_REG_U8_GLOBAL_RESET_CTRL2 0x0c01
+#define SMIAPP_REG_U8_GLOBAL_RESET_MODE_CONFIG_1 0x0c02
+#define SMIAPP_REG_U8_GLOBAL_RESET_MODE_CONFIG_2 0x0c03
+#define SMIAPP_REG_U16_TRDY_CTRL (0x0c04 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TRDOUT_CTRL (0x0c06 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TSHUTTER_STROBE_DELAY_CTRL (0x0c08 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TSHUTTER_STROBE_WIDTH_CTRL (0x0c0a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TFLASH_STROBE_DELAY_CTRL (0x0c0c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_HIGH_CTRL (0x0c0e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TGRST_INTERVAL_CTRL (0x0c10 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_FLASH_STROBE_ADJUSTMENT 0x0c12
+#define SMIAPP_REG_U16_FLASH_STROBE_START_POINT (0x0c14 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TFLASH_STROBE_DELAY_RS_CTRL (0x0c16 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_HIGH_RS_CTRL (0x0c18 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_FLASH_MODE_RS 0x0c1a
+#define SMIAPP_REG_U8_FLASH_TRIGGER_RS 0x0c1b
+#define SMIAPP_REG_U8_FLASH_STATUS 0x0c1c
+#define SMIAPP_REG_U8_SA_STROBE_MODE 0x0c1d
+#define SMIAPP_REG_U16_SA_STROBE_START_POINT (0x0c1e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TSA_STROBE_DELAY_CTRL (0x0c20 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TSA_STROBE_WIDTH_CTRL (0x0c22 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_SA_STROBE_TRIGGER 0x0c24
+#define SMIAPP_REG_U8_SPECIAL_ACTUATOR_STATUS 0x0c25
+#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH2_HIGH_RS_CTRL (0x0c26 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_LOW_RS_CTRL (0x0c28 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_TFLASH_STROBE_COUNT_RS_CTRL 0x0c2a
+#define SMIAPP_REG_U8_TFLASH_STROBE_COUNT_CTRL 0x0c2b
+#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH2_HIGH_CTRL (0x0c2c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_LOW_CTRL (0x0c2e | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_LOW_LEVEL_CTRL 0x0c80
+#define SMIAPP_REG_U16_MAIN_TRIGGER_REF_POINT (0x0c82 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAIN_TRIGGER_T3 (0x0c84 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_MAIN_TRIGGER_COUNT 0x0c86
+#define SMIAPP_REG_U16_PHASE1_TRIGGER_T3 (0x0c88 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_PHASE1_TRIGGER_COUNT 0x0c8a
+#define SMIAPP_REG_U16_PHASE2_TRIGGER_T3 (0x0c8c | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_PHASE2_TRIGGER_COUNT 0x0c8e
+#define SMIAPP_REG_U8_MECH_SHUTTER_CTRL 0x0d00
+#define SMIAPP_REG_U8_OPERATION_MODE 0x0d01
+#define SMIAPP_REG_U8_ACT_STATE1 0x0d02
+#define SMIAPP_REG_U8_ACT_STATE2 0x0d03
+#define SMIAPP_REG_U16_FOCUS_CHANGE (0x0d80 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FOCUS_CHANGE_CONTROL (0x0d82 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FOCUS_CHANGE_NUMBER_PHASE1 (0x0d84 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FOCUS_CHANGE_NUMBER_PHASE2 (0x0d86 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_STROBE_COUNT_PHASE1 0x0d88
+#define SMIAPP_REG_U8_STROBE_COUNT_PHASE2 0x0d89
+#define SMIAPP_REG_U8_POSITION 0x0d8a
+#define SMIAPP_REG_U8_BRACKETING_LUT_CONTROL 0x0e00
+#define SMIAPP_REG_U8_BRACKETING_LUT_MODE 0x0e01
+#define SMIAPP_REG_U8_BRACKETING_LUT_ENTRY_CONTROL 0x0e02
+#define SMIAPP_REG_U8_LUT_PARAMETERS_START 0x0e10
+#define SMIAPP_REG_U8_LUT_PARAMETERS_END 0x0eff
+#define SMIAPP_REG_U16_INTEGRATION_TIME_CAPABILITY (0x1000 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MIN (0x1004 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MAX_MARGIN (0x1006 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN (0x1008 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN (0x100a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_CAPABILITY (0x1080 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_MIN (0x1084 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_MAX (0x1086 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_STEP_SIZE (0x1088 | CCS_FL_16BIT)
+#define SMIAPP_REG_F32_MIN_EXT_CLK_FREQ_HZ (0x1100 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MAX_EXT_CLK_FREQ_HZ (0x1104 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_U16_MIN_PRE_PLL_CLK_DIV (0x1108 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_PRE_PLL_CLK_DIV (0x110a | CCS_FL_16BIT)
+#define SMIAPP_REG_F32_MIN_PLL_IP_FREQ_HZ (0x110c | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MAX_PLL_IP_FREQ_HZ (0x1110 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_U16_MIN_PLL_MULTIPLIER (0x1114 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_PLL_MULTIPLIER (0x1116 | CCS_FL_16BIT)
+#define SMIAPP_REG_F32_MIN_PLL_OP_FREQ_HZ (0x1118 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MAX_PLL_OP_FREQ_HZ (0x111c | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_U16_MIN_VT_SYS_CLK_DIV (0x1120 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_VT_SYS_CLK_DIV (0x1122 | CCS_FL_16BIT)
+#define SMIAPP_REG_F32_MIN_VT_SYS_CLK_FREQ_HZ (0x1124 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MAX_VT_SYS_CLK_FREQ_HZ (0x1128 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MIN_VT_PIX_CLK_FREQ_HZ (0x112c | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MAX_VT_PIX_CLK_FREQ_HZ (0x1130 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_U16_MIN_VT_PIX_CLK_DIV (0x1134 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_VT_PIX_CLK_DIV (0x1136 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES (0x1140 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES (0x1142 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK (0x1144 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK (0x1146 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK (0x1148 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_FRAME_BLANKING_LINES (0x114a | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_MIN_LINE_LENGTH_PCK_STEP_SIZE 0x114c
+#define SMIAPP_REG_U16_MIN_OP_SYS_CLK_DIV (0x1160 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_OP_SYS_CLK_DIV (0x1162 | CCS_FL_16BIT)
+#define SMIAPP_REG_F32_MIN_OP_SYS_CLK_FREQ_HZ (0x1164 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MAX_OP_SYS_CLK_FREQ_HZ (0x1168 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_U16_MIN_OP_PIX_CLK_DIV (0x116c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_OP_PIX_CLK_DIV (0x116e | CCS_FL_16BIT)
+#define SMIAPP_REG_F32_MIN_OP_PIX_CLK_FREQ_HZ (0x1170 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MAX_OP_PIX_CLK_FREQ_HZ (0x1174 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_U16_X_ADDR_MIN (0x1180 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_Y_ADDR_MIN (0x1182 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_X_ADDR_MAX (0x1184 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_Y_ADDR_MAX (0x1186 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_X_OUTPUT_SIZE (0x1188 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_Y_OUTPUT_SIZE (0x118a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_X_OUTPUT_SIZE (0x118c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_Y_OUTPUT_SIZE (0x118e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_EVEN_INC (0x11c0 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_EVEN_INC (0x11c2 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_ODD_INC (0x11c4 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_ODD_INC (0x11c6 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALING_CAPABILITY (0x1200 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALER_M_MIN (0x1204 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALER_M_MAX (0x1206 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALER_N_MIN (0x1208 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALER_N_MAX (0x120a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SPATIAL_SAMPLING_CAPABILITY (0x120c | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_DIGITAL_CROP_CAPABILITY 0x120e
+#define SMIAPP_REG_U16_COMPRESSION_CAPABILITY (0x1300 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINRED (0x1400 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINRED (0x1402 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINRED (0x1404 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINGREEN (0x1406 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINGREEN (0x1408 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINGREEN (0x140a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINBLUE (0x140c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINBLUE (0x140e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINBLUE (0x1410 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FIFO_SIZE_PIXELS (0x1500 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_FIFO_SUPPORT_CAPABILITY 0x1502
+#define SMIAPP_REG_U8_DPHY_CTRL_CAPABILITY 0x1600
+#define SMIAPP_REG_U8_CSI_LANE_MODE_CAPABILITY 0x1601
+#define SMIAPP_REG_U8_CSI_SIGNALLING_MODE_CAPABILITY 0x1602
+#define SMIAPP_REG_U8_FAST_STANDBY_CAPABILITY 0x1603
+#define SMIAPP_REG_U8_CCI_ADDRESS_CONTROL_CAPABILITY 0x1604
+#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_1_LANE_MODE_MBPS (0x1608 | CCS_FL_32BIT)
+#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_2_LANE_MODE_MBPS (0x160c | CCS_FL_32BIT)
+#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_3_LANE_MODE_MBPS (0x1610 | CCS_FL_32BIT)
+#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_4_LANE_MODE_MBPS (0x1614 | CCS_FL_32BIT)
+#define SMIAPP_REG_U8_TEMP_SENSOR_CAPABILITY 0x1618
+#define SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES_BIN (0x1700 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES_BIN (0x1702 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK_BIN (0x1704 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK_BIN (0x1706 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK_BIN (0x1708 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN_BIN (0x170a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN (0x170c | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_BINNING_CAPABILITY 0x1710
+#define SMIAPP_REG_U8_BINNING_WEIGHTING_CAPABILITY 0x1711
+#define SMIAPP_REG_U8_BINNING_SUBTYPES 0x1712
+#define SMIAPP_REG_U8_BINNING_TYPE_n(n) (0x1713 + (n)) /* 1 <= n <= 237 */
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_CAPABILITY 0x1800
+#define SMIAPP_REG_U8_SHADING_CORRECTION_CAPABILITY 0x1900
+#define SMIAPP_REG_U8_GREEN_IMBALANCE_CAPABILITY 0x1901
+#define SMIAPP_REG_U8_BLACK_LEVEL_CAPABILITY 0x1902
+#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_CAPABILITY 0x1903
+#define SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY (0x1904 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY_2 (0x1906 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_EDOF_CAPABILITY 0x1980
+#define SMIAPP_REG_U8_ESTIMATION_FRAMES 0x1981
+#define SMIAPP_REG_U8_SUPPORTS_SHARPNESS_ADJ 0x1982
+#define SMIAPP_REG_U8_SUPPORTS_DENOISING_ADJ 0x1983
+#define SMIAPP_REG_U8_SUPPORTS_MODULE_SPECIFIC_ADJ 0x1984
+#define SMIAPP_REG_U8_SUPPORTS_DEPTH_OF_FIELD_ADJ 0x1985
+#define SMIAPP_REG_U8_SUPPORTS_FOCUS_DISTANCE_ADJ 0x1986
+#define SMIAPP_REG_U8_COLOUR_FEEDBACK_CAPABILITY 0x1987
+#define SMIAPP_REG_U8_EDOF_SUPPORT_AB_NXM 0x1988
+#define SMIAPP_REG_U8_ESTIMATION_MODE_CAPABILITY 0x19c0
+#define SMIAPP_REG_U8_ESTIMATION_ZONE_CAPABILITY 0x19c1
+#define SMIAPP_REG_U16_EST_DEPTH_OF_FIELD (0x19c2 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_EST_FOCUS_DISTANCE (0x19c4 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_CAPABILITY_TRDY_MIN (0x1a00 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_FLASH_MODE_CAPABILITY 0x1a02
+#define SMIAPP_REG_U16_MECH_SHUT_AND_ACT_START_ADDR (0x1b02 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_ACTUATOR_CAPABILITY 0x1b04
+#define SMIAPP_REG_U16_ACTUATOR_TYPE (0x1b40 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_AF_DEVICE_ADDRESS 0x1b42
+#define SMIAPP_REG_U16_FOCUS_CHANGE_ADDRESS (0x1b44 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_1 0x1c00
+#define SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_2 0x1c01
+#define SMIAPP_REG_U8_BRACKETING_LUT_SIZE 0x1c02
+
+/* Register bit definitions */
+#define SMIAPP_IMAGE_ORIENTATION_HFLIP BIT(0)
+#define SMIAPP_IMAGE_ORIENTATION_VFLIP BIT(1)
+
+#define SMIAPP_DATA_TRANSFER_IF_1_CTRL_EN BIT(0)
+#define SMIAPP_DATA_TRANSFER_IF_1_CTRL_WR_EN BIT(1)
+#define SMIAPP_DATA_TRANSFER_IF_1_CTRL_ERR_CLEAR BIT(2)
+#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_RD_READY BIT(0)
+#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_WR_READY BIT(1)
+#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_EDATA BIT(2)
+#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_EUSAGE BIT(3)
+
+#define SMIAPP_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED BIT(0)
+#define SMIAPP_DATA_TRANSFER_IF_CAPABILITY_POLL BIT(2)
+
+#define SMIAPP_SOFTWARE_RESET BIT(0)
+
+#define SMIAPP_FLASH_MODE_CAPABILITY_SINGLE_STROBE BIT(0)
+#define SMIAPP_FLASH_MODE_CAPABILITY_MULTIPLE_STROBE BIT(1)
+
+#define SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_CLOCK 0
+#define SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_STROBE 1
+#define SMIAPP_CSI_SIGNALLING_MODE_CSI2 2
+
+#define SMIAPP_DPHY_CTRL_AUTOMATIC 0
+/* DPHY control based on REQUESTED_LINK_BIT_RATE_MBPS */
+#define SMIAPP_DPHY_CTRL_UI 1
+#define SMIAPP_DPHY_CTRL_REGISTER 2
+
+#define SMIAPP_COMPRESSION_MODE_SIMPLE_PREDICTOR 1
+#define SMIAPP_COMPRESSION_MODE_ADVANCED_PREDICTOR 2
+
+#define SMIAPP_MODE_SELECT_SOFTWARE_STANDBY 0
+#define SMIAPP_MODE_SELECT_STREAMING 1
+
+#define SMIAPP_SCALING_MODE_NONE 0
+#define SMIAPP_SCALING_MODE_HORIZONTAL 1
+#define SMIAPP_SCALING_MODE_BOTH 2
+
+#define SMIAPP_SCALING_CAPABILITY_NONE 0
+#define SMIAPP_SCALING_CAPABILITY_HORIZONTAL 1
+#define SMIAPP_SCALING_CAPABILITY_BOTH 2 /* horizontal/both */
+
+/* digital crop right before scaler */
+#define SMIAPP_DIGITAL_CROP_CAPABILITY_NONE 0
+#define SMIAPP_DIGITAL_CROP_CAPABILITY_INPUT_CROP 1
+
+#define SMIAPP_BINNING_CAPABILITY_NO 0
+#define SMIAPP_BINNING_CAPABILITY_YES 1
+
+/* Maximum number of binning subtypes */
+#define SMIAPP_BINNING_SUBTYPES 253
+
+#define SMIAPP_PIXEL_ORDER_GRBG 0
+#define SMIAPP_PIXEL_ORDER_RGGB 1
+#define SMIAPP_PIXEL_ORDER_BGGR 2
+#define SMIAPP_PIXEL_ORDER_GBRG 3
+
+#define SMIAPP_DATA_FORMAT_MODEL_TYPE_NORMAL 1
+#define SMIAPP_DATA_FORMAT_MODEL_TYPE_EXTENDED 2
+#define SMIAPP_DATA_FORMAT_MODEL_TYPE_NORMAL_N 8
+#define SMIAPP_DATA_FORMAT_MODEL_TYPE_EXTENDED_N 16
+
+#define SMIAPP_FRAME_FORMAT_MODEL_TYPE_2BYTE 0x01
+#define SMIAPP_FRAME_FORMAT_MODEL_TYPE_4BYTE 0x02
+#define SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NROWS_MASK 0x0f
+#define SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NCOLS_MASK 0xf0
+#define SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NCOLS_SHIFT 4
+
+#define SMIAPP_FRAME_FORMAT_DESC_2_PIXELCODE_MASK 0xf000
+#define SMIAPP_FRAME_FORMAT_DESC_2_PIXELCODE_SHIFT 12
+#define SMIAPP_FRAME_FORMAT_DESC_2_PIXELS_MASK 0x0fff
+
+#define SMIAPP_FRAME_FORMAT_DESC_4_PIXELCODE_MASK 0xf0000000
+#define SMIAPP_FRAME_FORMAT_DESC_4_PIXELCODE_SHIFT 28
+#define SMIAPP_FRAME_FORMAT_DESC_4_PIXELS_MASK 0x0000ffff
+
+#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_EMBEDDED 1
+#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_DUMMY 2
+#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_BLACK 3
+#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_DARK 4
+#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_VISIBLE 5
+
+#define SMIAPP_FAST_STANDBY_CTRL_COMPLETE_FRAMES 0
+#define SMIAPP_FAST_STANDBY_CTRL_IMMEDIATE 1
+
+/* Scaling N factor */
+#define SMIAPP_SCALE_N 16
+
+#endif /* __SMIAPP_REG_DEFS_H__ */
diff --git a/drivers/media/i2c/smiapp/smiapp-reg.h b/drivers/media/i2c/smiapp/smiapp-reg.h
deleted file mode 100644
index e6f96309786f..000000000000
--- a/drivers/media/i2c/smiapp/smiapp-reg.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * drivers/media/i2c/smiapp/smiapp-reg.h
- *
- * Generic driver for SMIA/SMIA++ compliant camera modules
- *
- * Copyright (C) 2011--2012 Nokia Corporation
- * Contact: Sakari Ailus <sakari.ailus@iki.fi>
- */
-
-#ifndef __SMIAPP_REG_H_
-#define __SMIAPP_REG_H_
-
-#include <linux/bits.h>
-
-#include "smiapp-reg-defs.h"
-
-/* Bits for above register */
-#define SMIAPP_IMAGE_ORIENTATION_HFLIP BIT(0)
-#define SMIAPP_IMAGE_ORIENTATION_VFLIP BIT(1)
-
-#define SMIAPP_DATA_TRANSFER_IF_1_CTRL_EN BIT(0)
-#define SMIAPP_DATA_TRANSFER_IF_1_CTRL_WR_EN BIT(1)
-#define SMIAPP_DATA_TRANSFER_IF_1_CTRL_ERR_CLEAR BIT(2)
-#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_RD_READY BIT(0)
-#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_WR_READY BIT(1)
-#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_EDATA BIT(2)
-#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_EUSAGE BIT(3)
-
-#define SMIAPP_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED BIT(0)
-#define SMIAPP_DATA_TRANSFER_IF_CAPABILITY_POLL BIT(2)
-
-#define SMIAPP_SOFTWARE_RESET BIT(0)
-
-#define SMIAPP_FLASH_MODE_CAPABILITY_SINGLE_STROBE BIT(0)
-#define SMIAPP_FLASH_MODE_CAPABILITY_MULTIPLE_STROBE BIT(1)
-
-#define SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_CLOCK 0
-#define SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_STROBE 1
-#define SMIAPP_CSI_SIGNALLING_MODE_CSI2 2
-
-#define SMIAPP_DPHY_CTRL_AUTOMATIC 0
-/* DPHY control based on REQUESTED_LINK_BIT_RATE_MBPS */
-#define SMIAPP_DPHY_CTRL_UI 1
-#define SMIAPP_DPHY_CTRL_REGISTER 2
-
-#define SMIAPP_COMPRESSION_MODE_SIMPLE_PREDICTOR 1
-#define SMIAPP_COMPRESSION_MODE_ADVANCED_PREDICTOR 2
-
-#define SMIAPP_MODE_SELECT_SOFTWARE_STANDBY 0
-#define SMIAPP_MODE_SELECT_STREAMING 1
-
-#define SMIAPP_SCALING_MODE_NONE 0
-#define SMIAPP_SCALING_MODE_HORIZONTAL 1
-#define SMIAPP_SCALING_MODE_BOTH 2
-
-#define SMIAPP_SCALING_CAPABILITY_NONE 0
-#define SMIAPP_SCALING_CAPABILITY_HORIZONTAL 1
-#define SMIAPP_SCALING_CAPABILITY_BOTH 2 /* horizontal/both */
-
-/* digital crop right before scaler */
-#define SMIAPP_DIGITAL_CROP_CAPABILITY_NONE 0
-#define SMIAPP_DIGITAL_CROP_CAPABILITY_INPUT_CROP 1
-
-#define SMIAPP_BINNING_CAPABILITY_NO 0
-#define SMIAPP_BINNING_CAPABILITY_YES 1
-
-/* Maximum number of binning subtypes */
-#define SMIAPP_BINNING_SUBTYPES 253
-
-#define SMIAPP_PIXEL_ORDER_GRBG 0
-#define SMIAPP_PIXEL_ORDER_RGGB 1
-#define SMIAPP_PIXEL_ORDER_BGGR 2
-#define SMIAPP_PIXEL_ORDER_GBRG 3
-
-#define SMIAPP_DATA_FORMAT_MODEL_TYPE_NORMAL 1
-#define SMIAPP_DATA_FORMAT_MODEL_TYPE_EXTENDED 2
-#define SMIAPP_DATA_FORMAT_MODEL_TYPE_NORMAL_N 8
-#define SMIAPP_DATA_FORMAT_MODEL_TYPE_EXTENDED_N 16
-
-#define SMIAPP_FRAME_FORMAT_MODEL_TYPE_2BYTE 0x01
-#define SMIAPP_FRAME_FORMAT_MODEL_TYPE_4BYTE 0x02
-#define SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NROWS_MASK 0x0f
-#define SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NCOLS_MASK 0xf0
-#define SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NCOLS_SHIFT 4
-
-#define SMIAPP_FRAME_FORMAT_DESC_2_PIXELCODE_MASK 0xf000
-#define SMIAPP_FRAME_FORMAT_DESC_2_PIXELCODE_SHIFT 12
-#define SMIAPP_FRAME_FORMAT_DESC_2_PIXELS_MASK 0x0fff
-
-#define SMIAPP_FRAME_FORMAT_DESC_4_PIXELCODE_MASK 0xf0000000
-#define SMIAPP_FRAME_FORMAT_DESC_4_PIXELCODE_SHIFT 28
-#define SMIAPP_FRAME_FORMAT_DESC_4_PIXELS_MASK 0x0000ffff
-
-#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_EMBEDDED 1
-#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_DUMMY 2
-#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_BLACK 3
-#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_DARK 4
-#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_VISIBLE 5
-
-#define SMIAPP_FAST_STANDBY_CTRL_COMPLETE_FRAMES 0
-#define SMIAPP_FAST_STANDBY_CTRL_IMMEDIATE 1
-
-/* Scaling N factor */
-#define SMIAPP_SCALE_N 16
-
-/* Image statistics registers */
-/* Registers 0x2000 to 0x2fff are reserved for future
- * use for statistics features.
- */
-
-/* Manufacturer Specific Registers: 0x3000 to 0x3fff
- * The manufacturer specifies these as a black box.
- */
-
-#endif /* __SMIAPP_REG_H_ */
diff --git a/drivers/media/i2c/smiapp/smiapp.h b/drivers/media/i2c/smiapp/smiapp.h
index 6f469934f9e3..7cef97db7f47 100644
--- a/drivers/media/i2c/smiapp/smiapp.h
+++ b/drivers/media/i2c/smiapp/smiapp.h
@@ -16,7 +16,7 @@
#include <media/v4l2-subdev.h>
#include "smiapp-pll.h"
-#include "smiapp-reg.h"
+#include "smiapp-reg-defs.h"
#include "smiapp-regs.h"
#include "smiapp-quirk.h"
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 005/106] smiapp: Add macros for accessing CCS registers
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (2 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 004/106] smiapp: Remove macros for defining registers, merge definitions Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 006/106] smiapp: Use MIPI CCS version and manufacturer ID information Sakari Ailus
` (92 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
Add two helper macros for reading and writing the CCS registers as defined
in ccs-regs.h.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/smiapp-regs.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/media/i2c/smiapp/smiapp-regs.h b/drivers/media/i2c/smiapp/smiapp-regs.h
index 7223f5f89109..dc946096f368 100644
--- a/drivers/media/i2c/smiapp/smiapp-regs.h
+++ b/drivers/media/i2c/smiapp/smiapp-regs.h
@@ -28,4 +28,10 @@ int smiapp_write(struct smiapp_sensor *sensor, u32 reg, u32 val);
unsigned int ccs_reg_width(u32 reg);
+#define ccs_read(sensor, reg_name, val) \
+ smiapp_read(sensor, CCS_R_##reg_name, val)
+
+#define ccs_write(sensor, reg_name, val) \
+ smiapp_write(sensor, CCS_R_##reg_name, val)
+
#endif
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 006/106] smiapp: Use MIPI CCS version and manufacturer ID information
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (3 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 005/106] smiapp: Add macros for accessing CCS registers Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 007/106] smiapp: Read CCS limit values Sakari Ailus
` (91 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
Read MIPI CCS manufacturer and version information, and use the CCS IDs
over SMIA whenever they are set.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/smiapp-core.c | 76 +++++++++++++++++++-------
drivers/media/i2c/smiapp/smiapp.h | 20 ++++---
2 files changed, 68 insertions(+), 28 deletions(-)
diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c
index 47e983e9cd87..10900ac4aa1a 100644
--- a/drivers/media/i2c/smiapp/smiapp-core.c
+++ b/drivers/media/i2c/smiapp/smiapp-core.c
@@ -2356,9 +2356,14 @@ smiapp_sysfs_ident_read(struct device *dev, struct device_attribute *attr,
struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
struct smiapp_module_info *minfo = &sensor->minfo;
- return snprintf(buf, PAGE_SIZE, "%2.2x%4.4x%2.2x\n",
- minfo->manufacturer_id, minfo->model_id,
- minfo->revision_number_major) + 1;
+ if (minfo->mipi_manufacturer_id)
+ return snprintf(buf, PAGE_SIZE, "%4.4x%4.4x%2.2x\n",
+ minfo->mipi_manufacturer_id, minfo->model_id,
+ minfo->revision_number_major) + 1;
+ else
+ return snprintf(buf, PAGE_SIZE, "%2.2x%4.4x%2.2x\n",
+ minfo->smia_manufacturer_id, minfo->model_id,
+ minfo->revision_number_major) + 1;
}
static DEVICE_ATTR(ident, S_IRUGO, smiapp_sysfs_ident_read, NULL);
@@ -2377,8 +2382,11 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor)
minfo->name = SMIAPP_NAME;
/* Module info */
- rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_MANUFACTURER_ID,
- &minfo->manufacturer_id);
+ rval = ccs_read(sensor, MODULE_MANUFACTURER_ID,
+ &minfo->mipi_manufacturer_id);
+ if (!rval && !minfo->mipi_manufacturer_id)
+ rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_MANUFACTURER_ID,
+ &minfo->smia_manufacturer_id);
if (!rval)
rval = smiapp_read_8only(sensor, SMIAPP_REG_U16_MODEL_ID,
&minfo->model_id);
@@ -2404,9 +2412,12 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor)
/* Sensor info */
if (!rval)
+ rval = ccs_read(sensor, SENSOR_MANUFACTURER_ID,
+ &minfo->sensor_mipi_manufacturer_id);
+ if (!rval && !minfo->sensor_mipi_manufacturer_id)
rval = smiapp_read_8only(sensor,
SMIAPP_REG_U8_SENSOR_MANUFACTURER_ID,
- &minfo->sensor_manufacturer_id);
+ &minfo->sensor_smia_manufacturer_id);
if (!rval)
rval = smiapp_read_8only(sensor,
SMIAPP_REG_U16_SENSOR_MODEL_ID,
@@ -2422,9 +2433,11 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor)
/* SMIA */
if (!rval)
+ rval = ccs_read(sensor, MIPI_CCS_VERSION, &minfo->ccs_version);
+ if (!rval && !minfo->ccs_version)
rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_SMIA_VERSION,
&minfo->smia_version);
- if (!rval)
+ if (!rval && !minfo->ccs_version)
rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_SMIAPP_VERSION,
&minfo->smiapp_version);
@@ -2433,38 +2446,62 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor)
return -ENODEV;
}
- dev_dbg(&client->dev, "module 0x%2.2x-0x%4.4x\n",
- minfo->manufacturer_id, minfo->model_id);
+ if (minfo->mipi_manufacturer_id)
+ dev_dbg(&client->dev, "MIPI CCS module 0x%4.4x-0x%4.4x\n",
+ minfo->mipi_manufacturer_id, minfo->model_id);
+ else
+ dev_dbg(&client->dev, "SMIA module 0x%2.2x-0x%4.4x\n",
+ minfo->smia_manufacturer_id, minfo->model_id);
dev_dbg(&client->dev,
"module revision 0x%2.2x-0x%2.2x date %2.2d-%2.2d-%2.2d\n",
minfo->revision_number_major, minfo->revision_number_minor,
minfo->module_year, minfo->module_month, minfo->module_day);
- dev_dbg(&client->dev, "sensor 0x%2.2x-0x%4.4x\n",
- minfo->sensor_manufacturer_id, minfo->sensor_model_id);
+ if (minfo->sensor_mipi_manufacturer_id)
+ dev_dbg(&client->dev, "MIPI CCS sensor 0x%4.4x-0x%4.4x\n",
+ minfo->sensor_mipi_manufacturer_id,
+ minfo->sensor_model_id);
+ else
+ dev_dbg(&client->dev, "SMIA sensor 0x%2.2x-0x%4.4x\n",
+ minfo->sensor_smia_manufacturer_id,
+ minfo->sensor_model_id);
dev_dbg(&client->dev,
"sensor revision 0x%2.2x firmware version 0x%2.2x\n",
minfo->sensor_revision_number, minfo->sensor_firmware_version);
- dev_dbg(&client->dev, "smia version %2.2d smiapp version %2.2d\n",
- minfo->smia_version, minfo->smiapp_version);
+ if (minfo->ccs_version)
+ dev_dbg(&client->dev, "MIPI CCS version %u.%u",
+ (minfo->ccs_version & CCS_MIPI_CCS_VERSION_MAJOR_MASK)
+ >> CCS_MIPI_CCS_VERSION_MAJOR_SHIFT,
+ (minfo->ccs_version & CCS_MIPI_CCS_VERSION_MINOR_MASK));
+ else
+ dev_dbg(&client->dev,
+ "smia version %2.2d smiapp version %2.2d\n",
+ minfo->smia_version, minfo->smiapp_version);
/*
* Some modules have bad data in the lvalues below. Hope the
* rvalues have better stuff. The lvalues are module
* parameters whereas the rvalues are sensor parameters.
*/
- if (!minfo->manufacturer_id && !minfo->model_id) {
- minfo->manufacturer_id = minfo->sensor_manufacturer_id;
+ if (minfo->sensor_smia_manufacturer_id &&
+ !minfo->smia_manufacturer_id && !minfo->model_id) {
+ minfo->smia_manufacturer_id =
+ minfo->sensor_smia_manufacturer_id;
minfo->model_id = minfo->sensor_model_id;
minfo->revision_number_major = minfo->sensor_revision_number;
}
for (i = 0; i < ARRAY_SIZE(smiapp_module_idents); i++) {
- if (smiapp_module_idents[i].manufacturer_id
- != minfo->manufacturer_id)
+ if (smiapp_module_idents[i].mipi_manufacturer_id &&
+ smiapp_module_idents[i].mipi_manufacturer_id
+ != minfo->mipi_manufacturer_id)
+ continue;
+ if (smiapp_module_idents[i].smia_manufacturer_id &&
+ smiapp_module_idents[i].smia_manufacturer_id
+ != minfo->smia_manufacturer_id)
continue;
if (smiapp_module_idents[i].model_id != minfo->model_id)
continue;
@@ -2488,9 +2525,8 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor)
dev_warn(&client->dev,
"no quirks for this module; let's hope it's fully compliant\n");
- dev_dbg(&client->dev, "the sensor is called %s, ident %2.2x%4.4x%2.2x\n",
- minfo->name, minfo->manufacturer_id, minfo->model_id,
- minfo->revision_number_major);
+ dev_dbg(&client->dev, "the sensor is called %s\n",
+ minfo->name);
return 0;
}
diff --git a/drivers/media/i2c/smiapp/smiapp.h b/drivers/media/i2c/smiapp/smiapp.h
index 7cef97db7f47..b1d0e3d71630 100644
--- a/drivers/media/i2c/smiapp/smiapp.h
+++ b/drivers/media/i2c/smiapp/smiapp.h
@@ -91,8 +91,9 @@ struct smiapp_quirk;
#define SMIAPP_MODULE_IDENT_FLAG_REV_LE (1 << 0)
struct smiapp_module_ident {
- u8 manufacturer_id;
+ u16 mipi_manufacturer_id;
u16 model_id;
+ u8 smia_manufacturer_id;
u8 revision_number_major;
u8 flags;
@@ -102,7 +103,8 @@ struct smiapp_module_ident {
};
struct smiapp_module_info {
- u32 manufacturer_id;
+ u32 smia_manufacturer_id;
+ u32 mipi_manufacturer_id;
u32 model_id;
u32 revision_number_major;
u32 revision_number_minor;
@@ -111,13 +113,15 @@ struct smiapp_module_info {
u32 module_month;
u32 module_day;
- u32 sensor_manufacturer_id;
+ u32 sensor_smia_manufacturer_id;
+ u32 sensor_mipi_manufacturer_id;
u32 sensor_model_id;
u32 sensor_revision_number;
u32 sensor_firmware_version;
u32 smia_version;
u32 smiapp_version;
+ u32 ccs_version;
u32 smiapp_profile;
@@ -126,7 +130,7 @@ struct smiapp_module_info {
};
#define SMIAPP_IDENT_FQ(manufacturer, model, rev, fl, _name, _quirk) \
- { .manufacturer_id = manufacturer, \
+ { .smia_manufacturer_id = manufacturer, \
.model_id = model, \
.revision_number_major = rev, \
.flags = fl, \
@@ -134,7 +138,7 @@ struct smiapp_module_info {
.quirk = _quirk, }
#define SMIAPP_IDENT_LQ(manufacturer, model, rev, _name, _quirk) \
- { .manufacturer_id = manufacturer, \
+ { .smia_manufacturer_id = manufacturer, \
.model_id = model, \
.revision_number_major = rev, \
.flags = SMIAPP_MODULE_IDENT_FLAG_REV_LE, \
@@ -142,14 +146,14 @@ struct smiapp_module_info {
.quirk = _quirk, }
#define SMIAPP_IDENT_L(manufacturer, model, rev, _name) \
- { .manufacturer_id = manufacturer, \
+ { .smia_manufacturer_id = manufacturer, \
.model_id = model, \
.revision_number_major = rev, \
.flags = SMIAPP_MODULE_IDENT_FLAG_REV_LE, \
.name = _name, }
#define SMIAPP_IDENT_Q(manufacturer, model, rev, _name, _quirk) \
- { .manufacturer_id = manufacturer, \
+ { .smia_manufacturer_id = manufacturer, \
.model_id = model, \
.revision_number_major = rev, \
.flags = 0, \
@@ -157,7 +161,7 @@ struct smiapp_module_info {
.quirk = _quirk, }
#define SMIAPP_IDENT(manufacturer, model, rev, _name) \
- { .manufacturer_id = manufacturer, \
+ { .smia_manufacturer_id = manufacturer, \
.model_id = model, \
.revision_number_major = rev, \
.flags = 0, \
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 007/106] smiapp: Read CCS limit values
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (4 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 006/106] smiapp: Use MIPI CCS version and manufacturer ID information Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 008/106] smiapp: Switch to CCS limits Sakari Ailus
` (90 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
Read limit and capability values into a driver allocated buffer. This will
later replace (most of) the existing SMIA limits.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/smiapp-core.c | 177 ++++++++++++++++++++++++-
drivers/media/i2c/smiapp/smiapp.h | 4 +
2 files changed, 176 insertions(+), 5 deletions(-)
diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c
index 10900ac4aa1a..42df98740445 100644
--- a/drivers/media/i2c/smiapp/smiapp-core.c
+++ b/drivers/media/i2c/smiapp/smiapp-core.c
@@ -28,6 +28,7 @@
#include <media/v4l2-device.h>
#include "ccs-limits.h"
+#include "ccs-regs.h"
#include "smiapp.h"
#define SMIAPP_ALIGN_DIM(dim, flags) \
@@ -102,6 +103,164 @@ static int smiapp_read_all_smia_limits(struct smiapp_sensor *sensor)
return 0;
}
+static void ccs_assign_limit(void *ptr, unsigned int width, u32 val)
+{
+ switch (width) {
+ case sizeof(u8):
+ *(u8 *)ptr = val;
+ break;
+ case sizeof(u16):
+ *(u16 *)ptr = val;
+ break;
+ case sizeof(u32):
+ *(u32 *)ptr = val;
+ break;
+ }
+}
+
+static int ccs_limit_ptr(struct smiapp_sensor *sensor, unsigned int limit,
+ unsigned int offset, void **__ptr)
+{
+ const struct ccs_limit *linfo;
+
+ if (WARN_ON(limit >= CCS_L_LAST))
+ return -EINVAL;
+
+ linfo = &ccs_limits[ccs_limit_offsets[limit].info];
+
+ if (WARN_ON(!sensor->ccs_limits) ||
+ WARN_ON(offset + ccs_reg_width(linfo->reg) >
+ ccs_limit_offsets[limit + 1].lim))
+ return -EINVAL;
+
+ *__ptr = sensor->ccs_limits + ccs_limit_offsets[limit].lim + offset;
+
+ return 0;
+}
+
+void ccs_replace_limit(struct smiapp_sensor *sensor,
+ unsigned int limit, unsigned int offset, u32 val)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ const struct ccs_limit *linfo;
+ void *ptr;
+ int ret;
+
+ ret = ccs_limit_ptr(sensor, limit, offset, &ptr);
+ if (ret)
+ return;
+
+ linfo = &ccs_limits[ccs_limit_offsets[limit].info];
+
+ dev_dbg(&client->dev, "quirk: 0x%8.8x \"%s\" %u = %d, 0x%x\n",
+ linfo->reg, linfo->name, offset, val, val);
+
+ ccs_assign_limit(ptr, ccs_reg_width(linfo->reg), val);
+}
+
+static u32 ccs_get_limit(struct smiapp_sensor *sensor,
+ unsigned int limit, unsigned int offset)
+{
+ void *ptr;
+ int ret;
+
+ ret = ccs_limit_ptr(sensor, limit, offset, &ptr);
+ if (ret)
+ return 0;
+
+ switch (ccs_reg_width(ccs_limits[ccs_limit_offsets[limit].info].reg)) {
+ case sizeof(u8):
+ return *(u8 *)ptr;
+ case sizeof(u16):
+ return *(u16 *)ptr;
+ case sizeof(u32):
+ return *(u32 *)ptr;
+ }
+
+ WARN_ON(1);
+
+ return 0;
+}
+
+#define CCS_LIM(sensor, limit) \
+ ccs_get_limit(sensor, CCS_L_##limit, 0)
+
+#define CCS_LIM_AT(sensor, limit, offset) \
+ ccs_get_limit(sensor, CCS_L_##limit, CCS_L_##limit##_OFFSET(offset))
+
+static int ccs_read_all_limits(struct smiapp_sensor *sensor)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ void *ptr, *alloc, *end;
+ unsigned int i, l;
+ int ret;
+
+ kfree(sensor->ccs_limits);
+ sensor->ccs_limits = NULL;
+
+ alloc = kzalloc(ccs_limit_offsets[CCS_L_LAST].lim, GFP_KERNEL);
+ if (!alloc)
+ return -ENOMEM;
+
+ end = alloc + ccs_limit_offsets[CCS_L_LAST].lim;
+
+ for (i = 0, l = 0, ptr = alloc; ccs_limits[i].size; i++) {
+ u32 reg = ccs_limits[i].reg;
+ unsigned int width = ccs_reg_width(reg);
+ unsigned int j;
+
+ if (l == CCS_L_LAST) {
+ dev_err(&client->dev,
+ "internal error --- end of limit array\n");
+ ret = -EINVAL;
+ goto out_err;
+ }
+
+ for (j = 0; j < ccs_limits[i].size / width;
+ j++, reg += width, ptr += width) {
+ u32 val;
+
+ ret = smiapp_read(sensor, reg, &val);
+ if (ret)
+ goto out_err;
+
+ if (ptr + width > end) {
+ dev_err(&client->dev,
+ "internal error --- no room for regs\n");
+ ret = -EINVAL;
+ goto out_err;
+ }
+
+ ccs_assign_limit(ptr, width, val);
+
+ dev_dbg(&client->dev, "0x%8.8x \"%s\" = %u, 0x%x\n",
+ reg, ccs_limits[i].name, val, val);
+ }
+
+ if (ccs_limits[i].flags & CCS_L_FL_SAME_REG)
+ continue;
+
+ l++;
+ ptr = alloc + ccs_limit_offsets[l].lim;
+ }
+
+ if (l != CCS_L_LAST) {
+ dev_err(&client->dev,
+ "internal error --- insufficient limits\n");
+ ret = -EINVAL;
+ goto out_err;
+ }
+
+ sensor->ccs_limits = alloc;
+
+ return 0;
+
+out_err:
+ kfree(alloc);
+
+ return ret;
+}
+
static int smiapp_read_frame_fmt(struct smiapp_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
@@ -2970,10 +3129,14 @@ static int smiapp_probe(struct i2c_client *client)
goto out_power_off;
}
+ rval = ccs_read_all_limits(sensor);
+ if (rval)
+ goto out_power_off;
+
rval = smiapp_read_frame_fmt(sensor);
if (rval) {
rval = -ENODEV;
- goto out_power_off;
+ goto out_free_ccs_limits;
}
/*
@@ -2997,7 +3160,7 @@ static int smiapp_probe(struct i2c_client *client)
rval = smiapp_call_quirk(sensor, limits);
if (rval) {
dev_err(&client->dev, "limits quirks failed\n");
- goto out_power_off;
+ goto out_free_ccs_limits;
}
if (SMIA_LIM(sensor, BINNING_CAPABILITY)) {
@@ -3007,7 +3170,7 @@ static int smiapp_probe(struct i2c_client *client)
SMIAPP_REG_U8_BINNING_SUBTYPES, &val);
if (rval < 0) {
rval = -ENODEV;
- goto out_power_off;
+ goto out_free_ccs_limits;
}
sensor->nbinning_subtypes = min_t(u8, val,
SMIAPP_BINNING_SUBTYPES);
@@ -3017,7 +3180,7 @@ static int smiapp_probe(struct i2c_client *client)
sensor, SMIAPP_REG_U8_BINNING_TYPE_n(i), &val);
if (rval < 0) {
rval = -ENODEV;
- goto out_power_off;
+ goto out_free_ccs_limits;
}
sensor->binning_subtypes[i] =
*(struct smiapp_binning_subtype *)&val;
@@ -3033,7 +3196,7 @@ static int smiapp_probe(struct i2c_client *client)
if (device_create_file(&client->dev, &dev_attr_ident) != 0) {
dev_err(&client->dev, "sysfs ident entry creation failed\n");
rval = -ENOENT;
- goto out_power_off;
+ goto out_free_ccs_limits;
}
if (sensor->minfo.smiapp_version &&
@@ -3150,6 +3313,9 @@ static int smiapp_probe(struct i2c_client *client)
out_cleanup:
smiapp_cleanup(sensor);
+out_free_ccs_limits:
+ kfree(sensor->ccs_limits);
+
out_power_off:
smiapp_power_off(&client->dev);
mutex_destroy(&sensor->mutex);
@@ -3176,6 +3342,7 @@ static int smiapp_remove(struct i2c_client *client)
}
smiapp_cleanup(sensor);
mutex_destroy(&sensor->mutex);
+ kfree(sensor->ccs_limits);
return 0;
}
diff --git a/drivers/media/i2c/smiapp/smiapp.h b/drivers/media/i2c/smiapp/smiapp.h
index b1d0e3d71630..08ca1b3d1b2f 100644
--- a/drivers/media/i2c/smiapp/smiapp.h
+++ b/drivers/media/i2c/smiapp/smiapp.h
@@ -228,6 +228,7 @@ struct smiapp_sensor {
struct clk *ext_clk;
struct gpio_desc *xshutdown;
u32 limits[SMIAPP_LIMIT_LAST];
+ void *ccs_limits;
u8 nbinning_subtypes;
struct smiapp_binning_subtype binning_subtypes[SMIAPP_BINNING_SUBTYPES];
u32 mbus_frame_fmts;
@@ -281,4 +282,7 @@ struct smiapp_sensor {
#define to_smiapp_sensor(_sd) \
(to_smiapp_subdev(_sd)->sensor)
+void ccs_replace_limit(struct smiapp_sensor *sensor,
+ unsigned int limit, unsigned int offset, u32 val);
+
#endif /* __SMIAPP_PRIV_H_ */
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 008/106] smiapp: Switch to CCS limits
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (5 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 007/106] smiapp: Read CCS limit values Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 009/106] smiapp: Obtain frame descriptor from " Sakari Ailus
` (89 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
Use the CCS limit definitions instead of the SMIA ones. This allows
accessing CCS capabilities where needed as well as dropping the old SMIA
limits.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/Makefile | 3 +-
drivers/media/i2c/smiapp/smiapp-core.c | 255 ++++++++++-------------
drivers/media/i2c/smiapp/smiapp-limits.c | 118 -----------
drivers/media/i2c/smiapp/smiapp-limits.h | 114 ----------
drivers/media/i2c/smiapp/smiapp-quirk.c | 25 +--
drivers/media/i2c/smiapp/smiapp-quirk.h | 3 -
drivers/media/i2c/smiapp/smiapp.h | 10 -
7 files changed, 113 insertions(+), 415 deletions(-)
delete mode 100644 drivers/media/i2c/smiapp/smiapp-limits.c
delete mode 100644 drivers/media/i2c/smiapp/smiapp-limits.h
diff --git a/drivers/media/i2c/smiapp/Makefile b/drivers/media/i2c/smiapp/Makefile
index 4638d1e14ebc..2189de360db6 100644
--- a/drivers/media/i2c/smiapp/Makefile
+++ b/drivers/media/i2c/smiapp/Makefile
@@ -1,7 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
smiapp-objs += smiapp-core.o smiapp-regs.o \
- smiapp-quirk.o smiapp-limits.o \
- ccs-limits.o
+ smiapp-quirk.o ccs-limits.o
obj-$(CONFIG_VIDEO_SMIAPP) += smiapp.o
ccflags-y += -I $(srctree)/drivers/media/i2c
diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c
index 42df98740445..a7cbd9029caa 100644
--- a/drivers/media/i2c/smiapp/smiapp-core.c
+++ b/drivers/media/i2c/smiapp/smiapp-core.c
@@ -64,45 +64,6 @@ static const struct smiapp_module_ident smiapp_module_idents[] = {
*
*/
-static u32 smiapp_get_limit(struct smiapp_sensor *sensor,
- unsigned int limit)
-{
- if (WARN_ON(limit >= SMIAPP_LIMIT_LAST))
- return 1;
-
- return sensor->limits[limit];
-}
-
-#define SMIA_LIM(sensor, limit) \
- smiapp_get_limit(sensor, SMIAPP_LIMIT_##limit)
-
-static int smiapp_read_all_smia_limits(struct smiapp_sensor *sensor)
-{
- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- unsigned int i;
- int rval;
-
- for (i = 0; i < SMIAPP_LIMIT_LAST; i++) {
- u32 val;
-
- rval = smiapp_read(
- sensor, smiapp_reg_limits[i].addr, &val);
- if (rval)
- return rval;
-
- sensor->limits[i] = val;
-
- dev_dbg(&client->dev, "0x%8.8x \"%s\" = %u, 0x%x\n",
- smiapp_reg_limits[i].addr,
- smiapp_reg_limits[i].what, val, val);
- }
-
- if (SMIA_LIM(sensor, SCALER_N_MIN) == 0)
- smiapp_replace_limit(sensor, SMIAPP_LIMIT_SCALER_N_MIN, 16);
-
- return 0;
-}
-
static void ccs_assign_limit(void *ptr, unsigned int width, u32 val)
{
switch (width) {
@@ -253,6 +214,9 @@ static int ccs_read_all_limits(struct smiapp_sensor *sensor)
sensor->ccs_limits = alloc;
+ if (CCS_LIM(sensor, SCALER_N_MIN) < 16)
+ ccs_replace_limit(sensor, CCS_L_SCALER_N_MIN, 0, 16);
+
return 0;
out_err:
@@ -444,35 +408,35 @@ static int smiapp_pll_try(struct smiapp_sensor *sensor,
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
struct smiapp_pll_limits lim = {
- .min_pre_pll_clk_div = SMIA_LIM(sensor, MIN_PRE_PLL_CLK_DIV),
- .max_pre_pll_clk_div = SMIA_LIM(sensor, MAX_PRE_PLL_CLK_DIV),
- .min_pll_ip_freq_hz = SMIA_LIM(sensor, MIN_PLL_IP_FREQ_HZ),
- .max_pll_ip_freq_hz = SMIA_LIM(sensor, MAX_PLL_IP_FREQ_HZ),
- .min_pll_multiplier = SMIA_LIM(sensor, MIN_PLL_MULTIPLIER),
- .max_pll_multiplier = SMIA_LIM(sensor, MAX_PLL_MULTIPLIER),
- .min_pll_op_freq_hz = SMIA_LIM(sensor, MIN_PLL_OP_FREQ_HZ),
- .max_pll_op_freq_hz = SMIA_LIM(sensor, MAX_PLL_OP_FREQ_HZ),
-
- .op.min_sys_clk_div = SMIA_LIM(sensor, MIN_OP_SYS_CLK_DIV),
- .op.max_sys_clk_div = SMIA_LIM(sensor, MAX_OP_SYS_CLK_DIV),
- .op.min_pix_clk_div = SMIA_LIM(sensor, MIN_OP_PIX_CLK_DIV),
- .op.max_pix_clk_div = SMIA_LIM(sensor, MAX_OP_PIX_CLK_DIV),
- .op.min_sys_clk_freq_hz = SMIA_LIM(sensor, MIN_OP_SYS_CLK_FREQ_HZ),
- .op.max_sys_clk_freq_hz = SMIA_LIM(sensor, MAX_OP_SYS_CLK_FREQ_HZ),
- .op.min_pix_clk_freq_hz = SMIA_LIM(sensor, MIN_OP_PIX_CLK_FREQ_HZ),
- .op.max_pix_clk_freq_hz = SMIA_LIM(sensor, MAX_OP_PIX_CLK_FREQ_HZ),
-
- .vt.min_sys_clk_div = SMIA_LIM(sensor, MIN_VT_SYS_CLK_DIV),
- .vt.max_sys_clk_div = SMIA_LIM(sensor, MAX_VT_SYS_CLK_DIV),
- .vt.min_pix_clk_div = SMIA_LIM(sensor, MIN_VT_PIX_CLK_DIV),
- .vt.max_pix_clk_div = SMIA_LIM(sensor, MAX_VT_PIX_CLK_DIV),
- .vt.min_sys_clk_freq_hz = SMIA_LIM(sensor, MIN_VT_SYS_CLK_FREQ_HZ),
- .vt.max_sys_clk_freq_hz = SMIA_LIM(sensor, MAX_VT_SYS_CLK_FREQ_HZ),
- .vt.min_pix_clk_freq_hz = SMIA_LIM(sensor, MIN_VT_PIX_CLK_FREQ_HZ),
- .vt.max_pix_clk_freq_hz = SMIA_LIM(sensor, MAX_VT_PIX_CLK_FREQ_HZ),
-
- .min_line_length_pck_bin = SMIA_LIM(sensor, MIN_LINE_LENGTH_PCK_BIN),
- .min_line_length_pck = SMIA_LIM(sensor, MIN_LINE_LENGTH_PCK),
+ .min_pre_pll_clk_div = CCS_LIM(sensor, MIN_PRE_PLL_CLK_DIV),
+ .max_pre_pll_clk_div = CCS_LIM(sensor, MAX_PRE_PLL_CLK_DIV),
+ .min_pll_ip_freq_hz = CCS_LIM(sensor, MIN_PLL_IP_CLK_FREQ_MHZ),
+ .max_pll_ip_freq_hz = CCS_LIM(sensor, MAX_PLL_IP_CLK_FREQ_MHZ),
+ .min_pll_multiplier = CCS_LIM(sensor, MIN_PLL_MULTIPLIER),
+ .max_pll_multiplier = CCS_LIM(sensor, MAX_PLL_MULTIPLIER),
+ .min_pll_op_freq_hz = CCS_LIM(sensor, MIN_PLL_OP_CLK_FREQ_MHZ),
+ .max_pll_op_freq_hz = CCS_LIM(sensor, MAX_PLL_OP_CLK_FREQ_MHZ),
+
+ .op.min_sys_clk_div = CCS_LIM(sensor, MIN_OP_SYS_CLK_DIV),
+ .op.max_sys_clk_div = CCS_LIM(sensor, MAX_OP_SYS_CLK_DIV),
+ .op.min_pix_clk_div = CCS_LIM(sensor, MIN_OP_PIX_CLK_DIV),
+ .op.max_pix_clk_div = CCS_LIM(sensor, MAX_OP_PIX_CLK_DIV),
+ .op.min_sys_clk_freq_hz = CCS_LIM(sensor, MIN_OP_SYS_CLK_FREQ_MHZ),
+ .op.max_sys_clk_freq_hz = CCS_LIM(sensor, MAX_OP_SYS_CLK_FREQ_MHZ),
+ .op.min_pix_clk_freq_hz = CCS_LIM(sensor, MIN_OP_PIX_CLK_FREQ_MHZ),
+ .op.max_pix_clk_freq_hz = CCS_LIM(sensor, MAX_OP_PIX_CLK_FREQ_MHZ),
+
+ .vt.min_sys_clk_div = CCS_LIM(sensor, MIN_VT_SYS_CLK_DIV),
+ .vt.max_sys_clk_div = CCS_LIM(sensor, MAX_VT_SYS_CLK_DIV),
+ .vt.min_pix_clk_div = CCS_LIM(sensor, MIN_VT_PIX_CLK_DIV),
+ .vt.max_pix_clk_div = CCS_LIM(sensor, MAX_VT_PIX_CLK_DIV),
+ .vt.min_sys_clk_freq_hz = CCS_LIM(sensor, MIN_VT_SYS_CLK_FREQ_MHZ),
+ .vt.max_sys_clk_freq_hz = CCS_LIM(sensor, MAX_VT_SYS_CLK_FREQ_MHZ),
+ .vt.min_pix_clk_freq_hz = CCS_LIM(sensor, MIN_VT_PIX_CLK_FREQ_MHZ),
+ .vt.max_pix_clk_freq_hz = CCS_LIM(sensor, MAX_VT_PIX_CLK_FREQ_MHZ),
+
+ .min_line_length_pck_bin = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK_BIN),
+ .min_line_length_pck = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK),
};
return smiapp_pll_calculate(&client->dev, &lim, pll);
@@ -515,7 +479,7 @@ static void __smiapp_update_exposure_limits(struct smiapp_sensor *sensor)
max = sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height
+ sensor->vblank->val
- - SMIA_LIM(sensor, COARSE_INTEGRATION_TIME_MAX_MARGIN);
+ - CCS_LIM(sensor, COARSE_INTEGRATION_TIME_MAX_MARGIN);
__v4l2_ctrl_modify_range(ctrl, ctrl->minimum, max, ctrl->step, max);
}
@@ -770,10 +734,10 @@ static int smiapp_init_controls(struct smiapp_sensor *sensor)
sensor->analog_gain = v4l2_ctrl_new_std(
&sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops,
V4L2_CID_ANALOGUE_GAIN,
- SMIA_LIM(sensor, ANALOGUE_GAIN_CODE_MIN),
- SMIA_LIM(sensor, ANALOGUE_GAIN_CODE_MAX),
- max(SMIA_LIM(sensor, ANALOGUE_GAIN_CODE_STEP), 1U),
- SMIA_LIM(sensor, ANALOGUE_GAIN_CODE_MIN));
+ CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN),
+ CCS_LIM(sensor, ANALOG_GAIN_CODE_MAX),
+ max(CCS_LIM(sensor, ANALOG_GAIN_CODE_STEP), 1U),
+ CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN));
/* Exposure limits will be updated soon, use just something here. */
sensor->exposure = v4l2_ctrl_new_std(
@@ -1032,21 +996,21 @@ static void smiapp_update_blanking(struct smiapp_sensor *sensor)
int min, max;
if (sensor->binning_vertical > 1 || sensor->binning_horizontal > 1) {
- min_fll = SMIA_LIM(sensor, MIN_FRAME_LENGTH_LINES_BIN);
- max_fll = SMIA_LIM(sensor, MAX_FRAME_LENGTH_LINES_BIN);
- min_llp = SMIA_LIM(sensor, MIN_LINE_LENGTH_PCK_BIN);
- max_llp = SMIA_LIM(sensor, MAX_LINE_LENGTH_PCK_BIN);
- min_lbp = SMIA_LIM(sensor, MIN_LINE_BLANKING_PCK_BIN);
+ min_fll = CCS_LIM(sensor, MIN_FRAME_LENGTH_LINES_BIN);
+ max_fll = CCS_LIM(sensor, MAX_FRAME_LENGTH_LINES_BIN);
+ min_llp = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK_BIN);
+ max_llp = CCS_LIM(sensor, MAX_LINE_LENGTH_PCK_BIN);
+ min_lbp = CCS_LIM(sensor, MIN_LINE_BLANKING_PCK_BIN);
} else {
- min_fll = SMIA_LIM(sensor, MIN_FRAME_LENGTH_LINES);
- max_fll = SMIA_LIM(sensor, MAX_FRAME_LENGTH_LINES);
- min_llp = SMIA_LIM(sensor, MIN_LINE_LENGTH_PCK);
- max_llp = SMIA_LIM(sensor, MAX_LINE_LENGTH_PCK);
- min_lbp = SMIA_LIM(sensor, MIN_LINE_BLANKING_PCK);
+ min_fll = CCS_LIM(sensor, MIN_FRAME_LENGTH_LINES);
+ max_fll = CCS_LIM(sensor, MAX_FRAME_LENGTH_LINES);
+ min_llp = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK);
+ max_llp = CCS_LIM(sensor, MAX_LINE_LENGTH_PCK);
+ min_lbp = CCS_LIM(sensor, MIN_LINE_BLANKING_PCK);
}
min = max_t(int,
- SMIA_LIM(sensor, MIN_FRAME_BLANKING_LINES),
+ CCS_LIM(sensor, MIN_FRAME_BLANKING_LINES),
min_fll -
sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height);
max = max_fll - sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height;
@@ -1124,8 +1088,8 @@ static int smiapp_read_nvm_page(struct smiapp_sensor *sensor, u32 p, u8 *nvm,
return -ENODATA;
}
- if (SMIA_LIM(sensor, DATA_TRANSFER_IF_CAPABILITY) &
- SMIAPP_DATA_TRANSFER_IF_CAPABILITY_POLL) {
+ if (CCS_LIM(sensor, DATA_TRANSFER_IF_CAPABILITY) &
+ CCS_DATA_TRANSFER_IF_CAPABILITY_POLLING) {
for (i = 1000; i > 0; i--) {
if (s & SMIAPP_DATA_TRANSFER_IF_1_STATUS_RD_READY)
break;
@@ -1577,8 +1541,8 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
*/
/* Digital crop */
- if (SMIA_LIM(sensor, DIGITAL_CROP_CAPABILITY)
- == SMIAPP_DIGITAL_CROP_CAPABILITY_INPUT_CROP) {
+ if (CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY)
+ == CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP) {
rval = smiapp_write(
sensor, SMIAPP_REG_U16_DIGITAL_CROP_X_OFFSET,
sensor->scaler->crop[SMIAPP_PAD_SINK].left);
@@ -1605,8 +1569,8 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
}
/* Scaling */
- if (SMIA_LIM(sensor, SCALING_CAPABILITY)
- != SMIAPP_SCALING_CAPABILITY_NONE) {
+ if (CCS_LIM(sensor, SCALING_CAPABILITY)
+ != CCS_SCALING_CAPABILITY_NONE) {
rval = smiapp_write(sensor, SMIAPP_REG_U16_SCALING_MODE,
sensor->scaling_mode);
if (rval < 0)
@@ -1628,9 +1592,9 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
if (rval < 0)
goto out;
- if ((SMIA_LIM(sensor, FLASH_MODE_CAPABILITY) &
- (SMIAPP_FLASH_MODE_CAPABILITY_SINGLE_STROBE |
- SMIAPP_FLASH_MODE_CAPABILITY_MULTIPLE_STROBE)) &&
+ if (CCS_LIM(sensor, FLASH_MODE_CAPABILITY) &
+ (CCS_FLASH_MODE_CAPABILITY_SINGLE_STROBE |
+ SMIAPP_FLASH_MODE_CAPABILITY_MULTIPLE_STROBE) &&
sensor->hwcfg->strobe_setup != NULL &&
sensor->hwcfg->strobe_setup->trigger != 0) {
rval = smiapp_setup_flash_strobe(sensor);
@@ -1876,7 +1840,7 @@ static void smiapp_propagate(struct v4l2_subdev *subdev,
if (which == V4L2_SUBDEV_FORMAT_ACTIVE) {
if (ssd == sensor->scaler) {
sensor->scale_m =
- SMIA_LIM(sensor, SCALER_N_MIN);
+ CCS_LIM(sensor, SCALER_N_MIN);
sensor->scaling_mode =
SMIAPP_SCALING_MODE_NONE;
} else if (ssd == sensor->binner) {
@@ -1988,12 +1952,12 @@ static int smiapp_set_format(struct v4l2_subdev *subdev,
fmt->format.width =
clamp(fmt->format.width,
- SMIA_LIM(sensor, MIN_X_OUTPUT_SIZE),
- SMIA_LIM(sensor, MAX_X_OUTPUT_SIZE));
+ CCS_LIM(sensor, MIN_X_OUTPUT_SIZE),
+ CCS_LIM(sensor, MAX_X_OUTPUT_SIZE));
fmt->format.height =
clamp(fmt->format.height,
- SMIA_LIM(sensor, MIN_Y_OUTPUT_SIZE),
- SMIA_LIM(sensor, MAX_Y_OUTPUT_SIZE));
+ CCS_LIM(sensor, MIN_Y_OUTPUT_SIZE),
+ CCS_LIM(sensor, MAX_Y_OUTPUT_SIZE));
smiapp_get_crop_compose(subdev, cfg, crops, NULL, fmt->which);
@@ -2046,7 +2010,7 @@ static int scaling_goodness(struct v4l2_subdev *subdev, int w, int ask_w,
val -= abs(w - ask_w);
val -= abs(h - ask_h);
- if (w < SMIA_LIM(sensor, MIN_X_OUTPUT_SIZE))
+ if (w < CCS_LIM(sensor, MIN_X_OUTPUT_SIZE))
val -= SCALING_GOODNESS_EXTREME;
dev_dbg(&client->dev, "w %d ask_w %d h %d ask_h %d goodness %d\n",
@@ -2112,7 +2076,7 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
struct i2c_client *client = v4l2_get_subdevdata(subdev);
struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
u32 min, max, a, b, max_m;
- u32 scale_m = SMIA_LIM(sensor, SCALER_N_MIN);
+ u32 scale_m = CCS_LIM(sensor, SCALER_N_MIN);
int mode = SMIAPP_SCALING_MODE_HORIZONTAL;
u32 try[4];
u32 ntry = 0;
@@ -2125,19 +2089,19 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
crops[SMIAPP_PAD_SINK]->height);
a = crops[SMIAPP_PAD_SINK]->width
- * SMIA_LIM(sensor, SCALER_N_MIN) / sel->r.width;
+ * CCS_LIM(sensor, SCALER_N_MIN) / sel->r.width;
b = crops[SMIAPP_PAD_SINK]->height
- * SMIA_LIM(sensor, SCALER_N_MIN) / sel->r.height;
+ * CCS_LIM(sensor, SCALER_N_MIN) / sel->r.height;
max_m = crops[SMIAPP_PAD_SINK]->width
- * SMIA_LIM(sensor, SCALER_N_MIN)
- / SMIA_LIM(sensor, MIN_X_OUTPUT_SIZE);
+ * CCS_LIM(sensor, SCALER_N_MIN)
+ / CCS_LIM(sensor, MIN_X_OUTPUT_SIZE);
- a = clamp(a, SMIA_LIM(sensor, SCALER_M_MIN),
- SMIA_LIM(sensor, SCALER_M_MAX));
- b = clamp(b, SMIA_LIM(sensor, SCALER_M_MIN),
- SMIA_LIM(sensor, SCALER_M_MAX));
- max_m = clamp(max_m, SMIA_LIM(sensor, SCALER_M_MIN),
- SMIA_LIM(sensor, SCALER_M_MAX));
+ a = clamp(a, CCS_LIM(sensor, SCALER_M_MIN),
+ CCS_LIM(sensor, SCALER_M_MAX));
+ b = clamp(b, CCS_LIM(sensor, SCALER_M_MIN),
+ CCS_LIM(sensor, SCALER_M_MAX));
+ max_m = clamp(max_m, CCS_LIM(sensor, SCALER_M_MIN),
+ CCS_LIM(sensor, SCALER_M_MAX));
dev_dbg(&client->dev, "scaling: a %d b %d max_m %d\n", a, b, max_m);
@@ -2163,8 +2127,7 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
int this = scaling_goodness(
subdev,
crops[SMIAPP_PAD_SINK]->width
- / try[i]
- * SMIA_LIM(sensor, SCALER_N_MIN),
+ / try[i] * CCS_LIM(sensor, SCALER_N_MIN),
sel->r.width,
crops[SMIAPP_PAD_SINK]->height,
sel->r.height,
@@ -2178,18 +2141,18 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
best = this;
}
- if (SMIA_LIM(sensor, SCALING_CAPABILITY)
- == SMIAPP_SCALING_CAPABILITY_HORIZONTAL)
+ if (CCS_LIM(sensor, SCALING_CAPABILITY)
+ == CCS_SCALING_CAPABILITY_HORIZONTAL)
continue;
this = scaling_goodness(
subdev, crops[SMIAPP_PAD_SINK]->width
/ try[i]
- * SMIA_LIM(sensor, SCALER_N_MIN),
+ * CCS_LIM(sensor, SCALER_N_MIN),
sel->r.width,
crops[SMIAPP_PAD_SINK]->height
/ try[i]
- * SMIA_LIM(sensor, SCALER_N_MIN),
+ * CCS_LIM(sensor, SCALER_N_MIN),
sel->r.height,
sel->flags);
@@ -2203,12 +2166,12 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
sel->r.width =
(crops[SMIAPP_PAD_SINK]->width
/ scale_m
- * SMIA_LIM(sensor, SCALER_N_MIN)) & ~1;
+ * CCS_LIM(sensor, SCALER_N_MIN)) & ~1;
if (mode == SMIAPP_SCALING_MODE_BOTH)
sel->r.height =
(crops[SMIAPP_PAD_SINK]->height
/ scale_m
- * SMIA_LIM(sensor, SCALER_N_MIN))
+ * CCS_LIM(sensor, SCALER_N_MIN))
& ~1;
else
sel->r.height = crops[SMIAPP_PAD_SINK]->height;
@@ -2262,10 +2225,9 @@ static int __smiapp_sel_supported(struct v4l2_subdev *subdev,
if (ssd == sensor->src
&& sel->pad == SMIAPP_PAD_SRC)
return 0;
- if (ssd == sensor->scaler
- && sel->pad == SMIAPP_PAD_SINK
- && SMIA_LIM(sensor, DIGITAL_CROP_CAPABILITY)
- == SMIAPP_DIGITAL_CROP_CAPABILITY_INPUT_CROP)
+ if (ssd == sensor->scaler && sel->pad == SMIAPP_PAD_SINK &&
+ CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY)
+ == CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP)
return 0;
return -EINVAL;
case V4L2_SEL_TGT_NATIVE_SIZE:
@@ -2279,9 +2241,8 @@ static int __smiapp_sel_supported(struct v4l2_subdev *subdev,
return -EINVAL;
if (ssd == sensor->binner)
return 0;
- if (ssd == sensor->scaler
- && SMIA_LIM(sensor, SCALING_CAPABILITY)
- != SMIAPP_SCALING_CAPABILITY_NONE)
+ if (ssd == sensor->scaler && CCS_LIM(sensor, SCALING_CAPABILITY)
+ != CCS_SCALING_CAPABILITY_NONE)
return 0;
fallthrough;
default:
@@ -2345,8 +2306,8 @@ static void smiapp_get_native_size(struct smiapp_subdev *ssd,
{
r->top = 0;
r->left = 0;
- r->width = SMIA_LIM(ssd->sensor, X_ADDR_MAX) + 1;
- r->height = SMIA_LIM(ssd->sensor, Y_ADDR_MAX) + 1;
+ r->width = CCS_LIM(ssd->sensor, X_ADDR_MAX) + 1;
+ r->height = CCS_LIM(ssd->sensor, Y_ADDR_MAX) + 1;
}
static int __smiapp_get_selection(struct v4l2_subdev *subdev,
@@ -2431,10 +2392,10 @@ static int smiapp_set_selection(struct v4l2_subdev *subdev,
sel->r.height = SMIAPP_ALIGN_DIM(sel->r.height, sel->flags);
sel->r.width = max_t(unsigned int,
- SMIA_LIM(sensor, MIN_X_OUTPUT_SIZE),
+ CCS_LIM(sensor, MIN_X_OUTPUT_SIZE),
sel->r.width);
sel->r.height = max_t(unsigned int,
- SMIA_LIM(sensor, MIN_Y_OUTPUT_SIZE),
+ CCS_LIM(sensor, MIN_Y_OUTPUT_SIZE),
sel->r.height);
switch (sel->target) {
@@ -3123,12 +3084,6 @@ static int smiapp_probe(struct i2c_client *client)
goto out_power_off;
}
- rval = smiapp_read_all_smia_limits(sensor);
- if (rval) {
- rval = -ENODEV;
- goto out_power_off;
- }
-
rval = ccs_read_all_limits(sensor);
if (rval)
goto out_power_off;
@@ -3163,7 +3118,7 @@ static int smiapp_probe(struct i2c_client *client)
goto out_free_ccs_limits;
}
- if (SMIA_LIM(sensor, BINNING_CAPABILITY)) {
+ if (CCS_LIM(sensor, BINNING_CAPABILITY)) {
u32 val;
rval = smiapp_read(sensor,
@@ -3200,8 +3155,8 @@ static int smiapp_probe(struct i2c_client *client)
}
if (sensor->minfo.smiapp_version &&
- SMIA_LIM(sensor, DATA_TRANSFER_IF_CAPABILITY) &
- SMIAPP_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED) {
+ CCS_LIM(sensor, DATA_TRANSFER_IF_CAPABILITY) &
+ CCS_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED) {
if (device_create_file(&client->dev, &dev_attr_nvm) != 0) {
dev_err(&client->dev, "sysfs nvm entry failed\n");
rval = -EBUSY;
@@ -3210,22 +3165,22 @@ static int smiapp_probe(struct i2c_client *client)
}
/* We consider this as profile 0 sensor if any of these are zero. */
- if (!SMIA_LIM(sensor, MIN_OP_SYS_CLK_DIV) ||
- !SMIA_LIM(sensor, MAX_OP_SYS_CLK_DIV) ||
- !SMIA_LIM(sensor, MIN_OP_PIX_CLK_DIV) ||
- !SMIA_LIM(sensor, MAX_OP_PIX_CLK_DIV)) {
+ if (!CCS_LIM(sensor, MIN_OP_SYS_CLK_DIV) ||
+ !CCS_LIM(sensor, MAX_OP_SYS_CLK_DIV) ||
+ !CCS_LIM(sensor, MIN_OP_PIX_CLK_DIV) ||
+ !CCS_LIM(sensor, MAX_OP_PIX_CLK_DIV)) {
sensor->minfo.smiapp_profile = SMIAPP_PROFILE_0;
- } else if (SMIA_LIM(sensor, SCALING_CAPABILITY)
- != SMIAPP_SCALING_CAPABILITY_NONE) {
- if (SMIA_LIM(sensor, SCALING_CAPABILITY)
- == SMIAPP_SCALING_CAPABILITY_HORIZONTAL)
+ } else if (CCS_LIM(sensor, SCALING_CAPABILITY)
+ != CCS_SCALING_CAPABILITY_NONE) {
+ if (CCS_LIM(sensor, SCALING_CAPABILITY)
+ == CCS_SCALING_CAPABILITY_HORIZONTAL)
sensor->minfo.smiapp_profile = SMIAPP_PROFILE_1;
else
sensor->minfo.smiapp_profile = SMIAPP_PROFILE_2;
sensor->scaler = &sensor->ssds[sensor->ssds_used];
sensor->ssds_used++;
- } else if (SMIA_LIM(sensor, DIGITAL_CROP_CAPABILITY)
- == SMIAPP_DIGITAL_CROP_CAPABILITY_INPUT_CROP) {
+ } else if (CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY)
+ == CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP) {
sensor->scaler = &sensor->ssds[sensor->ssds_used];
sensor->ssds_used++;
}
@@ -3234,13 +3189,13 @@ static int smiapp_probe(struct i2c_client *client)
sensor->pixel_array = &sensor->ssds[sensor->ssds_used];
sensor->ssds_used++;
- sensor->scale_m = SMIA_LIM(sensor, SCALER_N_MIN);
+ sensor->scale_m = CCS_LIM(sensor, SCALER_N_MIN);
/* prepare PLL configuration input values */
sensor->pll.bus_type = SMIAPP_PLL_BUS_TYPE_CSI2;
sensor->pll.csi2.lanes = sensor->hwcfg->lanes;
sensor->pll.ext_clk_freq_hz = sensor->hwcfg->ext_clk;
- sensor->pll.scale_n = SMIA_LIM(sensor, SCALER_N_MIN);
+ sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN);
/* Profile 0 sensors have no separate OP clock branch. */
if (sensor->minfo.smiapp_profile == SMIAPP_PROFILE_0)
sensor->pll.flags |= SMIAPP_PLL_FLAG_NO_OP_CLOCKS;
diff --git a/drivers/media/i2c/smiapp/smiapp-limits.c b/drivers/media/i2c/smiapp/smiapp-limits.c
deleted file mode 100644
index de5ee5296713..000000000000
--- a/drivers/media/i2c/smiapp/smiapp-limits.c
+++ /dev/null
@@ -1,118 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * drivers/media/i2c/smiapp/smiapp-limits.c
- *
- * Generic driver for SMIA/SMIA++ compliant camera modules
- *
- * Copyright (C) 2011--2012 Nokia Corporation
- * Contact: Sakari Ailus <sakari.ailus@iki.fi>
- */
-
-#include "smiapp.h"
-
-struct smiapp_reg_limits smiapp_reg_limits[] = {
- { SMIAPP_REG_U16_ANALOGUE_GAIN_CAPABILITY, "analogue_gain_capability" }, /* 0 */
- { SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MIN, "analogue_gain_code_min" },
- { SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MAX, "analogue_gain_code_max" },
- { SMIAPP_REG_U8_THS_ZERO_MIN, "ths_zero_min" },
- { SMIAPP_REG_U8_TCLK_TRAIL_MIN, "tclk_trail_min" },
- { SMIAPP_REG_U16_INTEGRATION_TIME_CAPABILITY, "integration_time_capability" }, /* 5 */
- { SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MIN, "coarse_integration_time_min" },
- { SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MAX_MARGIN, "coarse_integration_time_max_margin" },
- { SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN, "fine_integration_time_min" },
- { SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN, "fine_integration_time_max_margin" },
- { SMIAPP_REG_U16_DIGITAL_GAIN_CAPABILITY, "digital_gain_capability" }, /* 10 */
- { SMIAPP_REG_U16_DIGITAL_GAIN_MIN, "digital_gain_min" },
- { SMIAPP_REG_U16_DIGITAL_GAIN_MAX, "digital_gain_max" },
- { SMIAPP_REG_F32_MIN_EXT_CLK_FREQ_HZ, "min_ext_clk_freq_hz" },
- { SMIAPP_REG_F32_MAX_EXT_CLK_FREQ_HZ, "max_ext_clk_freq_hz" },
- { SMIAPP_REG_U16_MIN_PRE_PLL_CLK_DIV, "min_pre_pll_clk_div" }, /* 15 */
- { SMIAPP_REG_U16_MAX_PRE_PLL_CLK_DIV, "max_pre_pll_clk_div" },
- { SMIAPP_REG_F32_MIN_PLL_IP_FREQ_HZ, "min_pll_ip_freq_hz" },
- { SMIAPP_REG_F32_MAX_PLL_IP_FREQ_HZ, "max_pll_ip_freq_hz" },
- { SMIAPP_REG_U16_MIN_PLL_MULTIPLIER, "min_pll_multiplier" },
- { SMIAPP_REG_U16_MAX_PLL_MULTIPLIER, "max_pll_multiplier" }, /* 20 */
- { SMIAPP_REG_F32_MIN_PLL_OP_FREQ_HZ, "min_pll_op_freq_hz" },
- { SMIAPP_REG_F32_MAX_PLL_OP_FREQ_HZ, "max_pll_op_freq_hz" },
- { SMIAPP_REG_U16_MIN_VT_SYS_CLK_DIV, "min_vt_sys_clk_div" },
- { SMIAPP_REG_U16_MAX_VT_SYS_CLK_DIV, "max_vt_sys_clk_div" },
- { SMIAPP_REG_F32_MIN_VT_SYS_CLK_FREQ_HZ, "min_vt_sys_clk_freq_hz" }, /* 25 */
- { SMIAPP_REG_F32_MAX_VT_SYS_CLK_FREQ_HZ, "max_vt_sys_clk_freq_hz" },
- { SMIAPP_REG_F32_MIN_VT_PIX_CLK_FREQ_HZ, "min_vt_pix_clk_freq_hz" },
- { SMIAPP_REG_F32_MAX_VT_PIX_CLK_FREQ_HZ, "max_vt_pix_clk_freq_hz" },
- { SMIAPP_REG_U16_MIN_VT_PIX_CLK_DIV, "min_vt_pix_clk_div" },
- { SMIAPP_REG_U16_MAX_VT_PIX_CLK_DIV, "max_vt_pix_clk_div" }, /* 30 */
- { SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES, "min_frame_length_lines" },
- { SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES, "max_frame_length_lines" },
- { SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK, "min_line_length_pck" },
- { SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK, "max_line_length_pck" },
- { SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK, "min_line_blanking_pck" }, /* 35 */
- { SMIAPP_REG_U16_MIN_FRAME_BLANKING_LINES, "min_frame_blanking_lines" },
- { SMIAPP_REG_U8_MIN_LINE_LENGTH_PCK_STEP_SIZE, "min_line_length_pck_step_size" },
- { SMIAPP_REG_U16_MIN_OP_SYS_CLK_DIV, "min_op_sys_clk_div" },
- { SMIAPP_REG_U16_MAX_OP_SYS_CLK_DIV, "max_op_sys_clk_div" },
- { SMIAPP_REG_F32_MIN_OP_SYS_CLK_FREQ_HZ, "min_op_sys_clk_freq_hz" }, /* 40 */
- { SMIAPP_REG_F32_MAX_OP_SYS_CLK_FREQ_HZ, "max_op_sys_clk_freq_hz" },
- { SMIAPP_REG_U16_MIN_OP_PIX_CLK_DIV, "min_op_pix_clk_div" },
- { SMIAPP_REG_U16_MAX_OP_PIX_CLK_DIV, "max_op_pix_clk_div" },
- { SMIAPP_REG_F32_MIN_OP_PIX_CLK_FREQ_HZ, "min_op_pix_clk_freq_hz" },
- { SMIAPP_REG_F32_MAX_OP_PIX_CLK_FREQ_HZ, "max_op_pix_clk_freq_hz" }, /* 45 */
- { SMIAPP_REG_U16_X_ADDR_MIN, "x_addr_min" },
- { SMIAPP_REG_U16_Y_ADDR_MIN, "y_addr_min" },
- { SMIAPP_REG_U16_X_ADDR_MAX, "x_addr_max" },
- { SMIAPP_REG_U16_Y_ADDR_MAX, "y_addr_max" },
- { SMIAPP_REG_U16_MIN_X_OUTPUT_SIZE, "min_x_output_size" }, /* 50 */
- { SMIAPP_REG_U16_MIN_Y_OUTPUT_SIZE, "min_y_output_size" },
- { SMIAPP_REG_U16_MAX_X_OUTPUT_SIZE, "max_x_output_size" },
- { SMIAPP_REG_U16_MAX_Y_OUTPUT_SIZE, "max_y_output_size" },
- { SMIAPP_REG_U16_MIN_EVEN_INC, "min_even_inc" },
- { SMIAPP_REG_U16_MAX_EVEN_INC, "max_even_inc" }, /* 55 */
- { SMIAPP_REG_U16_MIN_ODD_INC, "min_odd_inc" },
- { SMIAPP_REG_U16_MAX_ODD_INC, "max_odd_inc" },
- { SMIAPP_REG_U16_SCALING_CAPABILITY, "scaling_capability" },
- { SMIAPP_REG_U16_SCALER_M_MIN, "scaler_m_min" },
- { SMIAPP_REG_U16_SCALER_M_MAX, "scaler_m_max" }, /* 60 */
- { SMIAPP_REG_U16_SCALER_N_MIN, "scaler_n_min" },
- { SMIAPP_REG_U16_SCALER_N_MAX, "scaler_n_max" },
- { SMIAPP_REG_U16_SPATIAL_SAMPLING_CAPABILITY, "spatial_sampling_capability" },
- { SMIAPP_REG_U8_DIGITAL_CROP_CAPABILITY, "digital_crop_capability" },
- { SMIAPP_REG_U16_COMPRESSION_CAPABILITY, "compression_capability" }, /* 65 */
- { SMIAPP_REG_U8_FIFO_SUPPORT_CAPABILITY, "fifo_support_capability" },
- { SMIAPP_REG_U8_DPHY_CTRL_CAPABILITY, "dphy_ctrl_capability" },
- { SMIAPP_REG_U8_CSI_LANE_MODE_CAPABILITY, "csi_lane_mode_capability" },
- { SMIAPP_REG_U8_CSI_SIGNALLING_MODE_CAPABILITY, "csi_signalling_mode_capability" },
- { SMIAPP_REG_U8_FAST_STANDBY_CAPABILITY, "fast_standby_capability" }, /* 70 */
- { SMIAPP_REG_U8_CCI_ADDRESS_CONTROL_CAPABILITY, "cci_address_control_capability" },
- { SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_1_LANE_MODE_MBPS, "max_per_lane_bitrate_1_lane_mode_mbps" },
- { SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_2_LANE_MODE_MBPS, "max_per_lane_bitrate_2_lane_mode_mbps" },
- { SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_3_LANE_MODE_MBPS, "max_per_lane_bitrate_3_lane_mode_mbps" },
- { SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_4_LANE_MODE_MBPS, "max_per_lane_bitrate_4_lane_mode_mbps" }, /* 75 */
- { SMIAPP_REG_U8_TEMP_SENSOR_CAPABILITY, "temp_sensor_capability" },
- { SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES_BIN, "min_frame_length_lines_bin" },
- { SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES_BIN, "max_frame_length_lines_bin" },
- { SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK_BIN, "min_line_length_pck_bin" },
- { SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK_BIN, "max_line_length_pck_bin" }, /* 80 */
- { SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK_BIN, "min_line_blanking_pck_bin" },
- { SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN_BIN, "fine_integration_time_min_bin" },
- { SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN, "fine_integration_time_max_margin_bin" },
- { SMIAPP_REG_U8_BINNING_CAPABILITY, "binning_capability" },
- { SMIAPP_REG_U8_BINNING_WEIGHTING_CAPABILITY, "binning_weighting_capability" }, /* 85 */
- { SMIAPP_REG_U8_DATA_TRANSFER_IF_CAPABILITY, "data_transfer_if_capability" },
- { SMIAPP_REG_U8_SHADING_CORRECTION_CAPABILITY, "shading_correction_capability" },
- { SMIAPP_REG_U8_GREEN_IMBALANCE_CAPABILITY, "green_imbalance_capability" },
- { SMIAPP_REG_U8_BLACK_LEVEL_CAPABILITY, "black_level_capability" },
- { SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_CAPABILITY, "module_specific_correction_capability" }, /* 90 */
- { SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY, "defect_correction_capability" },
- { SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY_2, "defect_correction_capability_2" },
- { SMIAPP_REG_U8_EDOF_CAPABILITY, "edof_capability" },
- { SMIAPP_REG_U8_COLOUR_FEEDBACK_CAPABILITY, "colour_feedback_capability" },
- { SMIAPP_REG_U8_ESTIMATION_MODE_CAPABILITY, "estimation_mode_capability" }, /* 95 */
- { SMIAPP_REG_U8_ESTIMATION_ZONE_CAPABILITY, "estimation_zone_capability" },
- { SMIAPP_REG_U16_CAPABILITY_TRDY_MIN, "capability_trdy_min" },
- { SMIAPP_REG_U8_FLASH_MODE_CAPABILITY, "flash_mode_capability" },
- { SMIAPP_REG_U8_ACTUATOR_CAPABILITY, "actuator_capability" },
- { SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_1, "bracketing_lut_capability_1" }, /* 100 */
- { SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_2, "bracketing_lut_capability_2" },
- { SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_STEP, "analogue_gain_code_step" },
- { 0, NULL },
-};
diff --git a/drivers/media/i2c/smiapp/smiapp-limits.h b/drivers/media/i2c/smiapp/smiapp-limits.h
deleted file mode 100644
index dbac0b4975f9..000000000000
--- a/drivers/media/i2c/smiapp/smiapp-limits.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * drivers/media/i2c/smiapp/smiapp-limits.h
- *
- * Generic driver for SMIA/SMIA++ compliant camera modules
- *
- * Copyright (C) 2011--2012 Nokia Corporation
- * Contact: Sakari Ailus <sakari.ailus@iki.fi>
- */
-
-#define SMIAPP_LIMIT_ANALOGUE_GAIN_CAPABILITY 0
-#define SMIAPP_LIMIT_ANALOGUE_GAIN_CODE_MIN 1
-#define SMIAPP_LIMIT_ANALOGUE_GAIN_CODE_MAX 2
-#define SMIAPP_LIMIT_THS_ZERO_MIN 3
-#define SMIAPP_LIMIT_TCLK_TRAIL_MIN 4
-#define SMIAPP_LIMIT_INTEGRATION_TIME_CAPABILITY 5
-#define SMIAPP_LIMIT_COARSE_INTEGRATION_TIME_MIN 6
-#define SMIAPP_LIMIT_COARSE_INTEGRATION_TIME_MAX_MARGIN 7
-#define SMIAPP_LIMIT_FINE_INTEGRATION_TIME_MIN 8
-#define SMIAPP_LIMIT_FINE_INTEGRATION_TIME_MAX_MARGIN 9
-#define SMIAPP_LIMIT_DIGITAL_GAIN_CAPABILITY 10
-#define SMIAPP_LIMIT_DIGITAL_GAIN_MIN 11
-#define SMIAPP_LIMIT_DIGITAL_GAIN_MAX 12
-#define SMIAPP_LIMIT_MIN_EXT_CLK_FREQ_HZ 13
-#define SMIAPP_LIMIT_MAX_EXT_CLK_FREQ_HZ 14
-#define SMIAPP_LIMIT_MIN_PRE_PLL_CLK_DIV 15
-#define SMIAPP_LIMIT_MAX_PRE_PLL_CLK_DIV 16
-#define SMIAPP_LIMIT_MIN_PLL_IP_FREQ_HZ 17
-#define SMIAPP_LIMIT_MAX_PLL_IP_FREQ_HZ 18
-#define SMIAPP_LIMIT_MIN_PLL_MULTIPLIER 19
-#define SMIAPP_LIMIT_MAX_PLL_MULTIPLIER 20
-#define SMIAPP_LIMIT_MIN_PLL_OP_FREQ_HZ 21
-#define SMIAPP_LIMIT_MAX_PLL_OP_FREQ_HZ 22
-#define SMIAPP_LIMIT_MIN_VT_SYS_CLK_DIV 23
-#define SMIAPP_LIMIT_MAX_VT_SYS_CLK_DIV 24
-#define SMIAPP_LIMIT_MIN_VT_SYS_CLK_FREQ_HZ 25
-#define SMIAPP_LIMIT_MAX_VT_SYS_CLK_FREQ_HZ 26
-#define SMIAPP_LIMIT_MIN_VT_PIX_CLK_FREQ_HZ 27
-#define SMIAPP_LIMIT_MAX_VT_PIX_CLK_FREQ_HZ 28
-#define SMIAPP_LIMIT_MIN_VT_PIX_CLK_DIV 29
-#define SMIAPP_LIMIT_MAX_VT_PIX_CLK_DIV 30
-#define SMIAPP_LIMIT_MIN_FRAME_LENGTH_LINES 31
-#define SMIAPP_LIMIT_MAX_FRAME_LENGTH_LINES 32
-#define SMIAPP_LIMIT_MIN_LINE_LENGTH_PCK 33
-#define SMIAPP_LIMIT_MAX_LINE_LENGTH_PCK 34
-#define SMIAPP_LIMIT_MIN_LINE_BLANKING_PCK 35
-#define SMIAPP_LIMIT_MIN_FRAME_BLANKING_LINES 36
-#define SMIAPP_LIMIT_MIN_LINE_LENGTH_PCK_STEP_SIZE 37
-#define SMIAPP_LIMIT_MIN_OP_SYS_CLK_DIV 38
-#define SMIAPP_LIMIT_MAX_OP_SYS_CLK_DIV 39
-#define SMIAPP_LIMIT_MIN_OP_SYS_CLK_FREQ_HZ 40
-#define SMIAPP_LIMIT_MAX_OP_SYS_CLK_FREQ_HZ 41
-#define SMIAPP_LIMIT_MIN_OP_PIX_CLK_DIV 42
-#define SMIAPP_LIMIT_MAX_OP_PIX_CLK_DIV 43
-#define SMIAPP_LIMIT_MIN_OP_PIX_CLK_FREQ_HZ 44
-#define SMIAPP_LIMIT_MAX_OP_PIX_CLK_FREQ_HZ 45
-#define SMIAPP_LIMIT_X_ADDR_MIN 46
-#define SMIAPP_LIMIT_Y_ADDR_MIN 47
-#define SMIAPP_LIMIT_X_ADDR_MAX 48
-#define SMIAPP_LIMIT_Y_ADDR_MAX 49
-#define SMIAPP_LIMIT_MIN_X_OUTPUT_SIZE 50
-#define SMIAPP_LIMIT_MIN_Y_OUTPUT_SIZE 51
-#define SMIAPP_LIMIT_MAX_X_OUTPUT_SIZE 52
-#define SMIAPP_LIMIT_MAX_Y_OUTPUT_SIZE 53
-#define SMIAPP_LIMIT_MIN_EVEN_INC 54
-#define SMIAPP_LIMIT_MAX_EVEN_INC 55
-#define SMIAPP_LIMIT_MIN_ODD_INC 56
-#define SMIAPP_LIMIT_MAX_ODD_INC 57
-#define SMIAPP_LIMIT_SCALING_CAPABILITY 58
-#define SMIAPP_LIMIT_SCALER_M_MIN 59
-#define SMIAPP_LIMIT_SCALER_M_MAX 60
-#define SMIAPP_LIMIT_SCALER_N_MIN 61
-#define SMIAPP_LIMIT_SCALER_N_MAX 62
-#define SMIAPP_LIMIT_SPATIAL_SAMPLING_CAPABILITY 63
-#define SMIAPP_LIMIT_DIGITAL_CROP_CAPABILITY 64
-#define SMIAPP_LIMIT_COMPRESSION_CAPABILITY 65
-#define SMIAPP_LIMIT_FIFO_SUPPORT_CAPABILITY 66
-#define SMIAPP_LIMIT_DPHY_CTRL_CAPABILITY 67
-#define SMIAPP_LIMIT_CSI_LANE_MODE_CAPABILITY 68
-#define SMIAPP_LIMIT_CSI_SIGNALLING_MODE_CAPABILITY 69
-#define SMIAPP_LIMIT_FAST_STANDBY_CAPABILITY 70
-#define SMIAPP_LIMIT_CCI_ADDRESS_CONTROL_CAPABILITY 71
-#define SMIAPP_LIMIT_MAX_PER_LANE_BITRATE_1_LANE_MODE_MBPS 72
-#define SMIAPP_LIMIT_MAX_PER_LANE_BITRATE_2_LANE_MODE_MBPS 73
-#define SMIAPP_LIMIT_MAX_PER_LANE_BITRATE_3_LANE_MODE_MBPS 74
-#define SMIAPP_LIMIT_MAX_PER_LANE_BITRATE_4_LANE_MODE_MBPS 75
-#define SMIAPP_LIMIT_TEMP_SENSOR_CAPABILITY 76
-#define SMIAPP_LIMIT_MIN_FRAME_LENGTH_LINES_BIN 77
-#define SMIAPP_LIMIT_MAX_FRAME_LENGTH_LINES_BIN 78
-#define SMIAPP_LIMIT_MIN_LINE_LENGTH_PCK_BIN 79
-#define SMIAPP_LIMIT_MAX_LINE_LENGTH_PCK_BIN 80
-#define SMIAPP_LIMIT_MIN_LINE_BLANKING_PCK_BIN 81
-#define SMIAPP_LIMIT_FINE_INTEGRATION_TIME_MIN_BIN 82
-#define SMIAPP_LIMIT_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN 83
-#define SMIAPP_LIMIT_BINNING_CAPABILITY 84
-#define SMIAPP_LIMIT_BINNING_WEIGHTING_CAPABILITY 85
-#define SMIAPP_LIMIT_DATA_TRANSFER_IF_CAPABILITY 86
-#define SMIAPP_LIMIT_SHADING_CORRECTION_CAPABILITY 87
-#define SMIAPP_LIMIT_GREEN_IMBALANCE_CAPABILITY 88
-#define SMIAPP_LIMIT_BLACK_LEVEL_CAPABILITY 89
-#define SMIAPP_LIMIT_MODULE_SPECIFIC_CORRECTION_CAPABILITY 90
-#define SMIAPP_LIMIT_DEFECT_CORRECTION_CAPABILITY 91
-#define SMIAPP_LIMIT_DEFECT_CORRECTION_CAPABILITY_2 92
-#define SMIAPP_LIMIT_EDOF_CAPABILITY 93
-#define SMIAPP_LIMIT_COLOUR_FEEDBACK_CAPABILITY 94
-#define SMIAPP_LIMIT_ESTIMATION_MODE_CAPABILITY 95
-#define SMIAPP_LIMIT_ESTIMATION_ZONE_CAPABILITY 96
-#define SMIAPP_LIMIT_CAPABILITY_TRDY_MIN 97
-#define SMIAPP_LIMIT_FLASH_MODE_CAPABILITY 98
-#define SMIAPP_LIMIT_ACTUATOR_CAPABILITY 99
-#define SMIAPP_LIMIT_BRACKETING_LUT_CAPABILITY_1 100
-#define SMIAPP_LIMIT_BRACKETING_LUT_CAPABILITY_2 101
-#define SMIAPP_LIMIT_ANALOGUE_GAIN_CODE_STEP 102
-#define SMIAPP_LIMIT_LAST 103
diff --git a/drivers/media/i2c/smiapp/smiapp-quirk.c b/drivers/media/i2c/smiapp/smiapp-quirk.c
index 308ca0b03f5a..24630c7650d2 100644
--- a/drivers/media/i2c/smiapp/smiapp-quirk.c
+++ b/drivers/media/i2c/smiapp/smiapp-quirk.c
@@ -10,6 +10,8 @@
#include <linux/delay.h>
+#include "ccs-limits.h"
+
#include "smiapp.h"
static int smiapp_write_8(struct smiapp_sensor *sensor, u16 reg, u8 val)
@@ -36,17 +38,6 @@ static int smiapp_write_8s(struct smiapp_sensor *sensor,
return 0;
}
-void smiapp_replace_limit(struct smiapp_sensor *sensor,
- u32 limit, u32 val)
-{
- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
-
- dev_dbg(&client->dev, "quirk: 0x%8.8x \"%s\" = %d, 0x%x\n",
- smiapp_reg_limits[limit].addr,
- smiapp_reg_limits[limit].what, val, val);
- sensor->limits[limit] = val;
-}
-
static int jt8ew9_limits(struct smiapp_sensor *sensor)
{
if (sensor->minfo.revision_number_major < 0x03)
@@ -54,9 +45,8 @@ static int jt8ew9_limits(struct smiapp_sensor *sensor)
/* Below 24 gain doesn't have effect at all, */
/* but ~59 is needed for full dynamic range */
- smiapp_replace_limit(sensor, SMIAPP_LIMIT_ANALOGUE_GAIN_CODE_MIN, 59);
- smiapp_replace_limit(
- sensor, SMIAPP_LIMIT_ANALOGUE_GAIN_CODE_MAX, 6000);
+ ccs_replace_limit(sensor, CCS_L_ANALOG_GAIN_CODE_MIN, 0, 59);
+ ccs_replace_limit(sensor, CCS_L_ANALOG_GAIN_CODE_MAX, 0, 6000);
return 0;
}
@@ -126,9 +116,8 @@ const struct smiapp_quirk smiapp_imx125es_quirk = {
static int jt8ev1_limits(struct smiapp_sensor *sensor)
{
- smiapp_replace_limit(sensor, SMIAPP_LIMIT_X_ADDR_MAX, 4271);
- smiapp_replace_limit(sensor,
- SMIAPP_LIMIT_MIN_LINE_BLANKING_PCK_BIN, 184);
+ ccs_replace_limit(sensor, CCS_L_X_ADDR_MAX, 0, 4271);
+ ccs_replace_limit(sensor, CCS_L_MIN_LINE_BLANKING_PCK_BIN, 0, 184);
return 0;
}
@@ -221,7 +210,7 @@ const struct smiapp_quirk smiapp_jt8ev1_quirk = {
static int tcm8500md_limits(struct smiapp_sensor *sensor)
{
- smiapp_replace_limit(sensor, SMIAPP_LIMIT_MIN_PLL_IP_FREQ_HZ, 2700000);
+ ccs_replace_limit(sensor, CCS_L_MIN_PLL_IP_CLK_FREQ_MHZ, 0, 2700000);
return 0;
}
diff --git a/drivers/media/i2c/smiapp/smiapp-quirk.h b/drivers/media/i2c/smiapp/smiapp-quirk.h
index 17505be60c1d..8a479f17cd19 100644
--- a/drivers/media/i2c/smiapp/smiapp-quirk.h
+++ b/drivers/media/i2c/smiapp/smiapp-quirk.h
@@ -55,9 +55,6 @@ struct smiapp_reg_8 {
u8 val;
};
-void smiapp_replace_limit(struct smiapp_sensor *sensor,
- u32 limit, u32 val);
-
#define SMIAPP_MK_QUIRK_REG_8(_reg, _val) \
{ \
.reg = (u16)_reg, \
diff --git a/drivers/media/i2c/smiapp/smiapp.h b/drivers/media/i2c/smiapp/smiapp.h
index 08ca1b3d1b2f..1a67cf485dcc 100644
--- a/drivers/media/i2c/smiapp/smiapp.h
+++ b/drivers/media/i2c/smiapp/smiapp.h
@@ -84,8 +84,6 @@ struct smiapp_hwconfig {
struct smiapp_flash_strobe_parms *strobe_setup;
};
-#include "smiapp-limits.h"
-
struct smiapp_quirk;
#define SMIAPP_MODULE_IDENT_FLAG_REV_LE (1 << 0)
@@ -167,13 +165,6 @@ struct smiapp_module_info {
.flags = 0, \
.name = _name, }
-struct smiapp_reg_limits {
- u32 addr;
- char *what;
-};
-
-extern struct smiapp_reg_limits smiapp_reg_limits[];
-
struct smiapp_csi_data_format {
u32 code;
u8 width;
@@ -227,7 +218,6 @@ struct smiapp_sensor {
struct regulator *vana;
struct clk *ext_clk;
struct gpio_desc *xshutdown;
- u32 limits[SMIAPP_LIMIT_LAST];
void *ccs_limits;
u8 nbinning_subtypes;
struct smiapp_binning_subtype binning_subtypes[SMIAPP_BINNING_SUBTYPES];
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 009/106] smiapp: Obtain frame descriptor from CCS limits
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (6 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 008/106] smiapp: Switch to CCS limits Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 010/106] smiapp: Use CCS limits in reading data format descriptors Sakari Ailus
` (88 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
Obtain the frame descriptor from the CCS limits, instead of reading them
directly from the frame descriptor registers.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/smiapp-core.c | 70 +++++++++++---------------
1 file changed, 30 insertions(+), 40 deletions(-)
diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c
index a7cbd9029caa..af94df9dbc7d 100644
--- a/drivers/media/i2c/smiapp/smiapp-core.c
+++ b/drivers/media/i2c/smiapp/smiapp-core.c
@@ -228,34 +228,29 @@ static int ccs_read_all_limits(struct smiapp_sensor *sensor)
static int smiapp_read_frame_fmt(struct smiapp_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- u32 fmt_model_type, fmt_model_subtype, ncol_desc, nrow_desc;
+ u8 fmt_model_type, fmt_model_subtype, ncol_desc, nrow_desc;
unsigned int i;
int pixel_count = 0;
int line_count = 0;
- int rval;
-
- rval = smiapp_read(sensor, SMIAPP_REG_U8_FRAME_FORMAT_MODEL_TYPE,
- &fmt_model_type);
- if (rval)
- return rval;
- rval = smiapp_read(sensor, SMIAPP_REG_U8_FRAME_FORMAT_MODEL_SUBTYPE,
- &fmt_model_subtype);
- if (rval)
- return rval;
+ fmt_model_type = CCS_LIM(sensor, FRAME_FORMAT_MODEL_TYPE);
+ fmt_model_subtype = CCS_LIM(sensor, FRAME_FORMAT_MODEL_SUBTYPE);
ncol_desc = (fmt_model_subtype
- & SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NCOLS_MASK)
- >> SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NCOLS_SHIFT;
+ & CCS_FRAME_FORMAT_MODEL_SUBTYPE_COLUMNS_MASK)
+ >> CCS_FRAME_FORMAT_MODEL_SUBTYPE_COLUMNS_SHIFT;
nrow_desc = fmt_model_subtype
- & SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NROWS_MASK;
+ & CCS_FRAME_FORMAT_MODEL_SUBTYPE_ROWS_MASK;
dev_dbg(&client->dev, "format_model_type %s\n",
- fmt_model_type == SMIAPP_FRAME_FORMAT_MODEL_TYPE_2BYTE
+ fmt_model_type == CCS_FRAME_FORMAT_MODEL_TYPE_2_BYTE
? "2 byte" :
- fmt_model_type == SMIAPP_FRAME_FORMAT_MODEL_TYPE_4BYTE
+ fmt_model_type == CCS_FRAME_FORMAT_MODEL_TYPE_4_BYTE
? "4 byte" : "is simply bad");
+ dev_dbg(&client->dev, "%u column and %u row descriptors\n",
+ ncol_desc, nrow_desc);
+
for (i = 0; i < ncol_desc + nrow_desc; i++) {
u32 desc;
u32 pixelcode;
@@ -264,29 +259,24 @@ static int smiapp_read_frame_fmt(struct smiapp_sensor *sensor)
char *what;
u32 reg;
- if (fmt_model_type == SMIAPP_FRAME_FORMAT_MODEL_TYPE_2BYTE) {
- reg = SMIAPP_REG_U16_FRAME_FORMAT_DESCRIPTOR_2(i);
- rval = smiapp_read(sensor, reg, &desc);
- if (rval)
- return rval;
+ if (fmt_model_type == CCS_FRAME_FORMAT_MODEL_TYPE_2_BYTE) {
+ desc = CCS_LIM_AT(sensor, FRAME_FORMAT_DESCRIPTOR, i);
pixelcode =
(desc
- & SMIAPP_FRAME_FORMAT_DESC_2_PIXELCODE_MASK)
- >> SMIAPP_FRAME_FORMAT_DESC_2_PIXELCODE_SHIFT;
- pixels = desc & SMIAPP_FRAME_FORMAT_DESC_2_PIXELS_MASK;
+ & CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MASK)
+ >> CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_SHIFT;
+ pixels = desc & CCS_FRAME_FORMAT_DESCRIPTOR_PIXELS_MASK;
} else if (fmt_model_type
- == SMIAPP_FRAME_FORMAT_MODEL_TYPE_4BYTE) {
- reg = SMIAPP_REG_U32_FRAME_FORMAT_DESCRIPTOR_4(i);
- rval = smiapp_read(sensor, reg, &desc);
- if (rval)
- return rval;
+ == CCS_FRAME_FORMAT_MODEL_TYPE_4_BYTE) {
+ desc = CCS_LIM_AT(sensor, FRAME_FORMAT_DESCRIPTOR_4, i);
pixelcode =
(desc
- & SMIAPP_FRAME_FORMAT_DESC_4_PIXELCODE_MASK)
- >> SMIAPP_FRAME_FORMAT_DESC_4_PIXELCODE_SHIFT;
- pixels = desc & SMIAPP_FRAME_FORMAT_DESC_4_PIXELS_MASK;
+ & CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MASK)
+ >> CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_SHIFT;
+ pixels = desc &
+ CCS_FRAME_FORMAT_DESCRIPTOR_4_PIXELS_MASK;
} else {
dev_dbg(&client->dev,
"invalid frame format model type %d\n",
@@ -300,19 +290,19 @@ static int smiapp_read_frame_fmt(struct smiapp_sensor *sensor)
which = "rows";
switch (pixelcode) {
- case SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_EMBEDDED:
+ case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_EMBEDDED:
what = "embedded";
break;
- case SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_DUMMY:
+ case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_DUMMY_PIXEL:
what = "dummy";
break;
- case SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_BLACK:
+ case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_BLACK_PIXEL:
what = "black";
break;
- case SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_DARK:
+ case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_DARK_PIXEL:
what = "dark";
break;
- case SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_VISIBLE:
+ case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_VISIBLE_PIXEL:
what = "visible";
break;
default:
@@ -326,7 +316,7 @@ static int smiapp_read_frame_fmt(struct smiapp_sensor *sensor)
if (i < ncol_desc) {
if (pixelcode ==
- SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_VISIBLE)
+ CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_VISIBLE_PIXEL)
sensor->visible_pixel_start = pixel_count;
pixel_count += pixels;
continue;
@@ -334,13 +324,13 @@ static int smiapp_read_frame_fmt(struct smiapp_sensor *sensor)
/* Handle row descriptors */
switch (pixelcode) {
- case SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_EMBEDDED:
+ case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_EMBEDDED:
if (sensor->embedded_end)
break;
sensor->embedded_start = line_count;
sensor->embedded_end = line_count + pixels;
break;
- case SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_VISIBLE:
+ case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_VISIBLE_PIXEL:
sensor->image_start = line_count;
break;
}
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 010/106] smiapp: Use CCS limits in reading data format descriptors
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (7 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 009/106] smiapp: Obtain frame descriptor from " Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 011/106] smiapp: Use CCS limits in reading binning capabilities Sakari Ailus
` (87 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
The CCS limits have the information so use it instead.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/smiapp-core.c | 22 +++++++++-------------
1 file changed, 9 insertions(+), 13 deletions(-)
diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c
index af94df9dbc7d..0f703860af0e 100644
--- a/drivers/media/i2c/smiapp/smiapp-core.c
+++ b/drivers/media/i2c/smiapp/smiapp-core.c
@@ -842,10 +842,7 @@ static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor)
unsigned int i, pixel_order;
int rval;
- rval = smiapp_read(
- sensor, SMIAPP_REG_U8_DATA_FORMAT_MODEL_TYPE, &type);
- if (rval)
- return rval;
+ type = CCS_LIM(sensor, DATA_FORMAT_MODEL_TYPE);
dev_dbg(&client->dev, "data_format_model_type %d\n", type);
@@ -863,11 +860,11 @@ static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor)
pixel_order_str[pixel_order]);
switch (type) {
- case SMIAPP_DATA_FORMAT_MODEL_TYPE_NORMAL:
+ case CCS_DATA_FORMAT_MODEL_TYPE_NORMAL:
n = SMIAPP_DATA_FORMAT_MODEL_TYPE_NORMAL_N;
break;
- case SMIAPP_DATA_FORMAT_MODEL_TYPE_EXTENDED:
- n = SMIAPP_DATA_FORMAT_MODEL_TYPE_EXTENDED_N;
+ case CCS_DATA_FORMAT_MODEL_TYPE_EXTENDED:
+ n = CCS_LIM_DATA_FORMAT_DESCRIPTOR_MAX_N + 1;
break;
default:
return -EINVAL;
@@ -879,11 +876,7 @@ static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor)
for (i = 0; i < n; i++) {
unsigned int fmt, j;
- rval = smiapp_read(
- sensor,
- SMIAPP_REG_U16_DATA_FORMAT_DESCRIPTOR(i), &fmt);
- if (rval)
- return rval;
+ fmt = CCS_LIM_AT(sensor, DATA_FORMAT_DESCRIPTOR, i);
dev_dbg(&client->dev, "%u: bpp %u, compressed %u\n",
i, fmt >> 8, (u8)fmt);
@@ -895,7 +888,10 @@ static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor)
if (f->pixel_order != SMIAPP_PIXEL_ORDER_GRBG)
continue;
- if (f->width != fmt >> 8 || f->compressed != (u8)fmt)
+ if (f->width != fmt >>
+ CCS_DATA_FORMAT_DESCRIPTOR_UNCOMPRESSED_SHIFT ||
+ f->compressed !=
+ (fmt & CCS_DATA_FORMAT_DESCRIPTOR_COMPRESSED_MASK))
continue;
dev_dbg(&client->dev, "jolly good! %d\n", j);
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 011/106] smiapp: Use CCS limits in reading binning capabilities
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (8 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 010/106] smiapp: Use CCS limits in reading data format descriptors Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 012/106] smiapp: Use CCS registers Sakari Ailus
` (86 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
Use CCS limits for obtaining binning capabilities and subtypes.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/smiapp-core.c | 27 +++++++++-----------------
1 file changed, 9 insertions(+), 18 deletions(-)
diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c
index 0f703860af0e..a54ceef5c5ea 100644
--- a/drivers/media/i2c/smiapp/smiapp-core.c
+++ b/drivers/media/i2c/smiapp/smiapp-core.c
@@ -3105,26 +3105,17 @@ static int smiapp_probe(struct i2c_client *client)
}
if (CCS_LIM(sensor, BINNING_CAPABILITY)) {
- u32 val;
-
- rval = smiapp_read(sensor,
- SMIAPP_REG_U8_BINNING_SUBTYPES, &val);
- if (rval < 0) {
- rval = -ENODEV;
- goto out_free_ccs_limits;
- }
- sensor->nbinning_subtypes = min_t(u8, val,
- SMIAPP_BINNING_SUBTYPES);
+ sensor->nbinning_subtypes =
+ min_t(u8, CCS_LIM(sensor, BINNING_SUB_TYPES),
+ CCS_LIM_BINNING_SUB_TYPE_MAX_N);
for (i = 0; i < sensor->nbinning_subtypes; i++) {
- rval = smiapp_read(
- sensor, SMIAPP_REG_U8_BINNING_TYPE_n(i), &val);
- if (rval < 0) {
- rval = -ENODEV;
- goto out_free_ccs_limits;
- }
- sensor->binning_subtypes[i] =
- *(struct smiapp_binning_subtype *)&val;
+ sensor->binning_subtypes[i].horizontal =
+ CCS_LIM_AT(sensor, BINNING_SUB_TYPE, i) >>
+ CCS_BINNING_SUB_TYPE_COLUMN_SHIFT;
+ sensor->binning_subtypes[i].vertical =
+ CCS_LIM_AT(sensor, BINNING_SUB_TYPE, i) &
+ CCS_BINNING_SUB_TYPE_ROW_MASK;
dev_dbg(&client->dev, "binning %xx%x\n",
sensor->binning_subtypes[i].horizontal,
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 012/106] smiapp: Use CCS registers
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (9 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 011/106] smiapp: Use CCS limits in reading binning capabilities Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 013/106] smiapp: Remove quirk function for writing a single 8-bit register Sakari Ailus
` (85 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
Switch to CCS standard registers where they exist. The still relevant SMIA
registers are left as-is and the redundant ones are removed.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/smiapp-core.c | 272 +++++++++++--------------
drivers/media/i2c/smiapp/smiapp.h | 4 +-
2 files changed, 118 insertions(+), 158 deletions(-)
diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c
index a54ceef5c5ea..b9faf38d4bba 100644
--- a/drivers/media/i2c/smiapp/smiapp-core.c
+++ b/drivers/media/i2c/smiapp/smiapp-core.c
@@ -28,7 +28,6 @@
#include <media/v4l2-device.h>
#include "ccs-limits.h"
-#include "ccs-regs.h"
#include "smiapp.h"
#define SMIAPP_ALIGN_DIM(dim, flags) \
@@ -357,40 +356,34 @@ static int smiapp_pll_configure(struct smiapp_sensor *sensor)
struct smiapp_pll *pll = &sensor->pll;
int rval;
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_VT_PIX_CLK_DIV, pll->vt.pix_clk_div);
+ rval = ccs_write(sensor, VT_PIX_CLK_DIV, pll->vt.pix_clk_div);
if (rval < 0)
return rval;
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_VT_SYS_CLK_DIV, pll->vt.sys_clk_div);
+ rval = ccs_write(sensor, VT_SYS_CLK_DIV, pll->vt.sys_clk_div);
if (rval < 0)
return rval;
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_PRE_PLL_CLK_DIV, pll->pre_pll_clk_div);
+ rval = ccs_write(sensor, PRE_PLL_CLK_DIV, pll->pre_pll_clk_div);
if (rval < 0)
return rval;
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_PLL_MULTIPLIER, pll->pll_multiplier);
+ rval = ccs_write(sensor, PLL_MULTIPLIER, pll->pll_multiplier);
if (rval < 0)
return rval;
/* Lane op clock ratio does not apply here. */
- rval = smiapp_write(
- sensor, SMIAPP_REG_U32_REQUESTED_LINK_BIT_RATE_MBPS,
- DIV_ROUND_UP(pll->op.sys_clk_freq_hz, 1000000 / 256 / 256));
+ rval = ccs_write(sensor, REQUESTED_LINK_RATE,
+ DIV_ROUND_UP(pll->op.sys_clk_freq_hz,
+ 1000000 / 256 / 256));
if (rval < 0 || sensor->minfo.smiapp_profile == SMIAPP_PROFILE_0)
return rval;
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_OP_PIX_CLK_DIV, pll->op.pix_clk_div);
+ rval = ccs_write(sensor, OP_PIX_CLK_DIV, pll->op.pix_clk_div);
if (rval < 0)
return rval;
- return smiapp_write(
- sensor, SMIAPP_REG_U16_OP_SYS_CLK_DIV, pll->op.sys_clk_div);
+ return ccs_write(sensor, OP_SYS_CLK_DIV, pll->op.sys_clk_div);
}
static int smiapp_pll_try(struct smiapp_sensor *sensor,
@@ -522,10 +515,10 @@ static u32 smiapp_pixel_order(struct smiapp_sensor *sensor)
if (sensor->hflip) {
if (sensor->hflip->val)
- flip |= SMIAPP_IMAGE_ORIENTATION_HFLIP;
+ flip |= CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR;
if (sensor->vflip->val)
- flip |= SMIAPP_IMAGE_ORIENTATION_VFLIP;
+ flip |= CCS_IMAGE_ORIENTATION_VERTICAL_FLIP;
}
flip ^= sensor->hvflip_inv_mask;
@@ -585,10 +578,10 @@ static int smiapp_set_ctrl(struct v4l2_ctrl *ctrl)
return -EBUSY;
if (sensor->hflip->val)
- orient |= SMIAPP_IMAGE_ORIENTATION_HFLIP;
+ orient |= CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR;
if (sensor->vflip->val)
- orient |= SMIAPP_IMAGE_ORIENTATION_VFLIP;
+ orient |= CCS_IMAGE_ORIENTATION_VERTICAL_FLIP;
orient ^= sensor->hvflip_inv_mask;
@@ -633,60 +626,50 @@ static int smiapp_set_ctrl(struct v4l2_ctrl *ctrl)
switch (ctrl->id) {
case V4L2_CID_ANALOGUE_GAIN:
- rval = smiapp_write(
- sensor,
- SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GLOBAL, ctrl->val);
+ rval = ccs_write(sensor, ANALOG_GAIN_CODE_GLOBAL, ctrl->val);
break;
case V4L2_CID_EXPOSURE:
- rval = smiapp_write(
- sensor,
- SMIAPP_REG_U16_COARSE_INTEGRATION_TIME, ctrl->val);
+ rval = ccs_write(sensor, COARSE_INTEGRATION_TIME, ctrl->val);
break;
case V4L2_CID_HFLIP:
case V4L2_CID_VFLIP:
- rval = smiapp_write(sensor, SMIAPP_REG_U8_IMAGE_ORIENTATION,
- orient);
+ rval = ccs_write(sensor, IMAGE_ORIENTATION, orient);
break;
case V4L2_CID_VBLANK:
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_FRAME_LENGTH_LINES,
- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height
- + ctrl->val);
+ rval = ccs_write(sensor, FRAME_LENGTH_LINES,
+ sensor->pixel_array->crop[
+ SMIAPP_PA_PAD_SRC].height
+ + ctrl->val);
break;
case V4L2_CID_HBLANK:
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_LINE_LENGTH_PCK,
- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].width
- + ctrl->val);
+ rval = ccs_write(sensor, LINE_LENGTH_PCK,
+ sensor->pixel_array->crop[
+ SMIAPP_PA_PAD_SRC].width
+ + ctrl->val);
break;
case V4L2_CID_TEST_PATTERN:
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_TEST_PATTERN_MODE, ctrl->val);
+ rval = ccs_write(sensor, TEST_PATTERN_MODE, ctrl->val);
break;
case V4L2_CID_TEST_PATTERN_RED:
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_TEST_DATA_RED, ctrl->val);
+ rval = ccs_write(sensor, TEST_DATA_RED, ctrl->val);
break;
case V4L2_CID_TEST_PATTERN_GREENR:
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_TEST_DATA_GREENR, ctrl->val);
+ rval = ccs_write(sensor, TEST_DATA_GREENR, ctrl->val);
break;
case V4L2_CID_TEST_PATTERN_BLUE:
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_TEST_DATA_BLUE, ctrl->val);
+ rval = ccs_write(sensor, TEST_DATA_BLUE, ctrl->val);
break;
case V4L2_CID_TEST_PATTERN_GREENB:
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_TEST_DATA_GREENB, ctrl->val);
+ rval = ccs_write(sensor, TEST_DATA_GREENB, ctrl->val);
break;
case V4L2_CID_PIXEL_RATE:
@@ -846,8 +829,7 @@ static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor)
dev_dbg(&client->dev, "data_format_model_type %d\n", type);
- rval = smiapp_read(sensor, SMIAPP_REG_U8_PIXEL_ORDER,
- &pixel_order);
+ rval = ccs_read(sensor, PIXEL_ORDER, &pixel_order);
if (rval)
return rval;
@@ -1054,22 +1036,20 @@ static int smiapp_read_nvm_page(struct smiapp_sensor *sensor, u32 p, u8 *nvm,
*status = 0;
- rval = smiapp_write(sensor,
- SMIAPP_REG_U8_DATA_TRANSFER_IF_1_PAGE_SELECT, p);
+ rval = ccs_write(sensor, DATA_TRANSFER_IF_1_PAGE_SELECT, p);
if (rval)
return rval;
- rval = smiapp_write(sensor, SMIAPP_REG_U8_DATA_TRANSFER_IF_1_CTRL,
- SMIAPP_DATA_TRANSFER_IF_1_CTRL_EN);
+ rval = ccs_write(sensor, DATA_TRANSFER_IF_1_CTRL,
+ CCS_DATA_TRANSFER_IF_1_CTRL_ENABLE);
if (rval)
return rval;
- rval = smiapp_read(sensor, SMIAPP_REG_U8_DATA_TRANSFER_IF_1_STATUS,
- &s);
+ rval = ccs_read(sensor, DATA_TRANSFER_IF_1_STATUS, &s);
if (rval)
return rval;
- if (s & SMIAPP_DATA_TRANSFER_IF_1_STATUS_EUSAGE) {
+ if (s & CCS_DATA_TRANSFER_IF_1_STATUS_IMPROPER_IF_USAGE) {
*status = s;
return -ENODATA;
}
@@ -1077,14 +1057,10 @@ static int smiapp_read_nvm_page(struct smiapp_sensor *sensor, u32 p, u8 *nvm,
if (CCS_LIM(sensor, DATA_TRANSFER_IF_CAPABILITY) &
CCS_DATA_TRANSFER_IF_CAPABILITY_POLLING) {
for (i = 1000; i > 0; i--) {
- if (s & SMIAPP_DATA_TRANSFER_IF_1_STATUS_RD_READY)
+ if (s & CCS_DATA_TRANSFER_IF_1_STATUS_READ_IF_READY)
break;
- rval = smiapp_read(
- sensor,
- SMIAPP_REG_U8_DATA_TRANSFER_IF_1_STATUS,
- &s);
-
+ rval = ccs_read(sensor, DATA_TRANSFER_IF_1_STATUS, &s);
if (rval)
return rval;
}
@@ -1093,12 +1069,10 @@ static int smiapp_read_nvm_page(struct smiapp_sensor *sensor, u32 p, u8 *nvm,
return -ETIMEDOUT;
}
- for (i = 0; i < SMIAPP_NVM_PAGE_SIZE; i++) {
+ for (i = 0; i <= CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P; i++) {
u32 v;
- rval = smiapp_read(sensor,
- SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_0 + i,
- &v);
+ rval = ccs_read(sensor, DATA_TRANSFER_IF_1_DATA(i), &v);
if (rval)
return rval;
@@ -1115,20 +1089,21 @@ static int smiapp_read_nvm(struct smiapp_sensor *sensor, unsigned char *nvm,
u32 p;
int rval = 0, rval2;
- for (p = 0; p < nvm_size / SMIAPP_NVM_PAGE_SIZE && !rval; p++) {
+ for (p = 0; p < nvm_size / (CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P + 1)
+ && !rval; p++) {
rval = smiapp_read_nvm_page(sensor, p, nvm, &status);
- nvm += SMIAPP_NVM_PAGE_SIZE;
+ nvm += CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P + 1;
}
if (rval == -ENODATA &&
- status & SMIAPP_DATA_TRANSFER_IF_1_STATUS_EUSAGE)
+ status & CCS_DATA_TRANSFER_IF_1_STATUS_IMPROPER_IF_USAGE)
rval = 0;
- rval2 = smiapp_write(sensor, SMIAPP_REG_U8_DATA_TRANSFER_IF_1_CTRL, 0);
+ rval2 = ccs_write(sensor, DATA_TRANSFER_IF_1_CTRL, 0);
if (rval < 0)
return rval;
else
- return rval2 ?: p * SMIAPP_NVM_PAGE_SIZE;
+ return rval2 ?: p * (CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P + 1);
}
/*
@@ -1144,16 +1119,15 @@ static int smiapp_change_cci_addr(struct smiapp_sensor *sensor)
client->addr = sensor->hwcfg->i2c_addr_dfl;
- rval = smiapp_write(sensor,
- SMIAPP_REG_U8_CCI_ADDRESS_CONTROL,
- sensor->hwcfg->i2c_addr_alt << 1);
+ rval = ccs_write(sensor, CCI_ADDRESS_CTRL,
+ sensor->hwcfg->i2c_addr_alt << 1);
if (rval)
return rval;
client->addr = sensor->hwcfg->i2c_addr_alt;
/* verify addr change went ok */
- rval = smiapp_read(sensor, SMIAPP_REG_U8_CCI_ADDRESS_CONTROL, &val);
+ rval = ccs_read(sensor, CCI_ADDRESS_CTRL, &val);
if (rval)
return rval;
@@ -1259,34 +1233,30 @@ static int smiapp_setup_flash_strobe(struct smiapp_sensor *sensor)
strobe_width_high_rs = (tmp + strobe_adjustment - 1) /
strobe_adjustment;
- rval = smiapp_write(sensor, SMIAPP_REG_U8_FLASH_MODE_RS,
- strobe_setup->mode);
+ rval = ccs_write(sensor, FLASH_MODE_RS, strobe_setup->mode);
if (rval < 0)
goto out;
- rval = smiapp_write(sensor, SMIAPP_REG_U8_FLASH_STROBE_ADJUSTMENT,
- strobe_adjustment);
+ rval = ccs_write(sensor, FLASH_STROBE_ADJUSTMENT, strobe_adjustment);
if (rval < 0)
goto out;
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_HIGH_RS_CTRL,
- strobe_width_high_rs);
+ rval = ccs_write(sensor, TFLASH_STROBE_WIDTH_HIGH_RS_CTRL,
+ strobe_width_high_rs);
if (rval < 0)
goto out;
- rval = smiapp_write(sensor, SMIAPP_REG_U16_TFLASH_STROBE_DELAY_RS_CTRL,
- strobe_setup->strobe_delay);
+ rval = ccs_write(sensor, TFLASH_STROBE_DELAY_RS_CTRL,
+ strobe_setup->strobe_delay);
if (rval < 0)
goto out;
- rval = smiapp_write(sensor, SMIAPP_REG_U16_FLASH_STROBE_START_POINT,
- strobe_setup->stobe_start_point);
+ rval = ccs_write(sensor, FLASH_STROBE_START_POINT,
+ strobe_setup->stobe_start_point);
if (rval < 0)
goto out;
- rval = smiapp_write(sensor, SMIAPP_REG_U8_FLASH_TRIGGER_RS,
- strobe_setup->trigger);
+ rval = ccs_write(sensor, FLASH_TRIGGER_RS, strobe_setup->trigger);
out:
sensor->hwcfg->strobe_setup->trigger = 0;
@@ -1349,8 +1319,7 @@ static int smiapp_power_on(struct device *dev)
}
}
- rval = smiapp_write(sensor, SMIAPP_REG_U8_SOFTWARE_RESET,
- SMIAPP_SOFTWARE_RESET);
+ rval = ccs_write(sensor, SOFTWARE_RESET, CCS_SOFTWARE_RESET_ON);
if (rval < 0) {
dev_err(dev, "software reset failed\n");
goto out_cci_addr_fail;
@@ -1364,45 +1333,42 @@ static int smiapp_power_on(struct device *dev)
}
}
- rval = smiapp_write(sensor, SMIAPP_REG_U16_COMPRESSION_MODE,
- SMIAPP_COMPRESSION_MODE_SIMPLE_PREDICTOR);
+ rval = ccs_write(sensor, COMPRESSION_MODE,
+ CCS_COMPRESSION_MODE_DPCM_PCM_SIMPLE);
if (rval) {
dev_err(dev, "compression mode set failed\n");
goto out_cci_addr_fail;
}
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_EXTCLK_FREQUENCY_MHZ,
- sensor->hwcfg->ext_clk / (1000000 / (1 << 8)));
+ rval = ccs_write(sensor, EXTCLK_FREQUENCY_MHZ,
+ sensor->hwcfg->ext_clk / (1000000 / (1 << 8)));
if (rval) {
dev_err(dev, "extclk frequency set failed\n");
goto out_cci_addr_fail;
}
- rval = smiapp_write(sensor, SMIAPP_REG_U8_CSI_LANE_MODE,
- sensor->hwcfg->lanes - 1);
+ rval = ccs_write(sensor, CSI_LANE_MODE, sensor->hwcfg->lanes - 1);
if (rval) {
dev_err(dev, "csi lane mode set failed\n");
goto out_cci_addr_fail;
}
- rval = smiapp_write(sensor, SMIAPP_REG_U8_FAST_STANDBY_CTRL,
- SMIAPP_FAST_STANDBY_CTRL_IMMEDIATE);
+ rval = ccs_write(sensor, FAST_STANDBY_CTRL,
+ CCS_FAST_STANDBY_CTRL_FRAME_TRUNCATION);
if (rval) {
dev_err(dev, "fast standby set failed\n");
goto out_cci_addr_fail;
}
- rval = smiapp_write(sensor, SMIAPP_REG_U8_CSI_SIGNALLING_MODE,
- sensor->hwcfg->csi_signalling_mode);
+ rval = ccs_write(sensor, CSI_SIGNALING_MODE,
+ sensor->hwcfg->csi_signalling_mode);
if (rval) {
dev_err(dev, "csi signalling mode set failed\n");
goto out_cci_addr_fail;
}
/* DPHY control done by sensor based on requested link rate */
- rval = smiapp_write(sensor, SMIAPP_REG_U8_DPHY_CTRL,
- SMIAPP_DPHY_CTRL_UI);
+ rval = ccs_write(sensor, PHY_CTRL, CCS_PHY_CTRL_UI);
if (rval < 0)
goto out_cci_addr_fail;
@@ -1439,9 +1405,7 @@ static int smiapp_power_off(struct device *dev)
* will fail. So do a soft reset explicitly here.
*/
if (sensor->hwcfg->i2c_addr_alt)
- smiapp_write(sensor,
- SMIAPP_REG_U8_SOFTWARE_RESET,
- SMIAPP_SOFTWARE_RESET);
+ ccs_write(sensor, SOFTWARE_RESET, CCS_SOFTWARE_RESET_ON);
gpiod_set_value(sensor->xshutdown, 0);
clk_disable_unprepare(sensor->ext_clk);
@@ -1464,9 +1428,9 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
mutex_lock(&sensor->mutex);
- rval = smiapp_write(sensor, SMIAPP_REG_U16_CSI_DATA_FORMAT,
- (sensor->csi_format->width << 8) |
- sensor->csi_format->compressed);
+ rval = ccs_write(sensor, CSI_DATA_FORMAT,
+ (sensor->csi_format->width << 8) |
+ sensor->csi_format->compressed);
if (rval)
goto out;
@@ -1479,14 +1443,13 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
(sensor->binning_horizontal << 4)
| sensor->binning_vertical;
- rval = smiapp_write(
- sensor, SMIAPP_REG_U8_BINNING_TYPE, binning_type);
+ rval = ccs_write(sensor, BINNING_TYPE, binning_type);
if (rval < 0)
goto out;
binning_mode = 1;
}
- rval = smiapp_write(sensor, SMIAPP_REG_U8_BINNING_MODE, binning_mode);
+ rval = ccs_write(sensor, BINNING_MODE, binning_mode);
if (rval < 0)
goto out;
@@ -1496,26 +1459,26 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
goto out;
/* Analog crop start coordinates */
- rval = smiapp_write(sensor, SMIAPP_REG_U16_X_ADDR_START,
- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].left);
+ rval = ccs_write(sensor, X_ADDR_START,
+ sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].left);
if (rval < 0)
goto out;
- rval = smiapp_write(sensor, SMIAPP_REG_U16_Y_ADDR_START,
- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].top);
+ rval = ccs_write(sensor, Y_ADDR_START,
+ sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].top);
if (rval < 0)
goto out;
/* Analog crop end coordinates */
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_X_ADDR_END,
+ rval = ccs_write(
+ sensor, X_ADDR_END,
sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].left
+ sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].width - 1);
if (rval < 0)
goto out;
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_Y_ADDR_END,
+ rval = ccs_write(
+ sensor, Y_ADDR_END,
sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].top
+ sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height - 1);
if (rval < 0)
@@ -1529,26 +1492,26 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
/* Digital crop */
if (CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY)
== CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP) {
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_DIGITAL_CROP_X_OFFSET,
+ rval = ccs_write(
+ sensor, DIGITAL_CROP_X_OFFSET,
sensor->scaler->crop[SMIAPP_PAD_SINK].left);
if (rval < 0)
goto out;
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_DIGITAL_CROP_Y_OFFSET,
+ rval = ccs_write(
+ sensor, DIGITAL_CROP_Y_OFFSET,
sensor->scaler->crop[SMIAPP_PAD_SINK].top);
if (rval < 0)
goto out;
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_WIDTH,
+ rval = ccs_write(
+ sensor, DIGITAL_CROP_IMAGE_WIDTH,
sensor->scaler->crop[SMIAPP_PAD_SINK].width);
if (rval < 0)
goto out;
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_HEIGHT,
+ rval = ccs_write(
+ sensor, DIGITAL_CROP_IMAGE_HEIGHT,
sensor->scaler->crop[SMIAPP_PAD_SINK].height);
if (rval < 0)
goto out;
@@ -1557,24 +1520,22 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
/* Scaling */
if (CCS_LIM(sensor, SCALING_CAPABILITY)
!= CCS_SCALING_CAPABILITY_NONE) {
- rval = smiapp_write(sensor, SMIAPP_REG_U16_SCALING_MODE,
- sensor->scaling_mode);
+ rval = ccs_write(sensor, SCALING_MODE, sensor->scaling_mode);
if (rval < 0)
goto out;
- rval = smiapp_write(sensor, SMIAPP_REG_U16_SCALE_M,
- sensor->scale_m);
+ rval = ccs_write(sensor, SCALE_M, sensor->scale_m);
if (rval < 0)
goto out;
}
/* Output size from sensor */
- rval = smiapp_write(sensor, SMIAPP_REG_U16_X_OUTPUT_SIZE,
- sensor->src->crop[SMIAPP_PAD_SRC].width);
+ rval = ccs_write(sensor, X_OUTPUT_SIZE,
+ sensor->src->crop[SMIAPP_PAD_SRC].width);
if (rval < 0)
goto out;
- rval = smiapp_write(sensor, SMIAPP_REG_U16_Y_OUTPUT_SIZE,
- sensor->src->crop[SMIAPP_PAD_SRC].height);
+ rval = ccs_write(sensor, Y_OUTPUT_SIZE,
+ sensor->src->crop[SMIAPP_PAD_SRC].height);
if (rval < 0)
goto out;
@@ -1594,8 +1555,7 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
goto out;
}
- rval = smiapp_write(sensor, SMIAPP_REG_U8_MODE_SELECT,
- SMIAPP_MODE_SELECT_STREAMING);
+ rval = ccs_write(sensor, MODE_SELECT, CCS_MODE_SELECT_STREAMING);
out:
mutex_unlock(&sensor->mutex);
@@ -1609,8 +1569,7 @@ static int smiapp_stop_streaming(struct smiapp_sensor *sensor)
int rval;
mutex_lock(&sensor->mutex);
- rval = smiapp_write(sensor, SMIAPP_REG_U8_MODE_SELECT,
- SMIAPP_MODE_SELECT_SOFTWARE_STANDBY);
+ rval = ccs_write(sensor, MODE_SELECT, CCS_MODE_SELECT_SOFTWARE_STANDBY);
if (rval)
goto out;
@@ -1828,7 +1787,7 @@ static void smiapp_propagate(struct v4l2_subdev *subdev,
sensor->scale_m =
CCS_LIM(sensor, SCALER_N_MIN);
sensor->scaling_mode =
- SMIAPP_SCALING_MODE_NONE;
+ CCS_SCALING_MODE_NO_SCALING;
} else if (ssd == sensor->binner) {
sensor->binning_horizontal = 1;
sensor->binning_vertical = 1;
@@ -2063,7 +2022,7 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
u32 min, max, a, b, max_m;
u32 scale_m = CCS_LIM(sensor, SCALER_N_MIN);
- int mode = SMIAPP_SCALING_MODE_HORIZONTAL;
+ int mode = CCS_SCALING_MODE_HORIZONTAL;
u32 try[4];
u32 ntry = 0;
unsigned int i;
@@ -2123,7 +2082,7 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
if (this > best) {
scale_m = try[i];
- mode = SMIAPP_SCALING_MODE_HORIZONTAL;
+ mode = CCS_SCALING_MODE_HORIZONTAL;
best = this;
}
@@ -2494,26 +2453,24 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor)
rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_MANUFACTURER_ID,
&minfo->smia_manufacturer_id);
if (!rval)
- rval = smiapp_read_8only(sensor, SMIAPP_REG_U16_MODEL_ID,
+ rval = smiapp_read_8only(sensor, CCS_R_MODULE_MODEL_ID,
&minfo->model_id);
if (!rval)
rval = smiapp_read_8only(sensor,
- SMIAPP_REG_U8_REVISION_NUMBER_MAJOR,
+ CCS_R_MODULE_REVISION_NUMBER_MAJOR,
&minfo->revision_number_major);
if (!rval)
rval = smiapp_read_8only(sensor,
- SMIAPP_REG_U8_REVISION_NUMBER_MINOR,
+ CCS_R_MODULE_REVISION_NUMBER_MINOR,
&minfo->revision_number_minor);
if (!rval)
- rval = smiapp_read_8only(sensor,
- SMIAPP_REG_U8_MODULE_DATE_YEAR,
+ rval = smiapp_read_8only(sensor, CCS_R_MODULE_DATE_YEAR,
&minfo->module_year);
if (!rval)
- rval = smiapp_read_8only(sensor,
- SMIAPP_REG_U8_MODULE_DATE_MONTH,
+ rval = smiapp_read_8only(sensor, CCS_R_MODULE_DATE_MONTH,
&minfo->module_month);
if (!rval)
- rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_MODULE_DATE_DAY,
+ rval = smiapp_read_8only(sensor, CCS_R_MODULE_DATE_DAY,
&minfo->module_day);
/* Sensor info */
@@ -2522,19 +2479,19 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor)
&minfo->sensor_mipi_manufacturer_id);
if (!rval && !minfo->sensor_mipi_manufacturer_id)
rval = smiapp_read_8only(sensor,
- SMIAPP_REG_U8_SENSOR_MANUFACTURER_ID,
+ CCS_R_SENSOR_MANUFACTURER_ID,
&minfo->sensor_smia_manufacturer_id);
if (!rval)
rval = smiapp_read_8only(sensor,
- SMIAPP_REG_U16_SENSOR_MODEL_ID,
+ CCS_R_SENSOR_MODEL_ID,
&minfo->sensor_model_id);
if (!rval)
rval = smiapp_read_8only(sensor,
- SMIAPP_REG_U8_SENSOR_REVISION_NUMBER,
+ CCS_R_SENSOR_REVISION_NUMBER,
&minfo->sensor_revision_number);
if (!rval)
rval = smiapp_read_8only(sensor,
- SMIAPP_REG_U8_SENSOR_FIRMWARE_VERSION,
+ CCS_R_SENSOR_FIRMWARE_VERSION,
&minfo->sensor_firmware_version);
/* SMIA */
@@ -2919,7 +2876,7 @@ static struct smiapp_hwconfig *smiapp_get_hwconfig(struct device *dev)
switch (bus_cfg.bus_type) {
case V4L2_MBUS_CSI2_DPHY:
- hwcfg->csi_signalling_mode = SMIAPP_CSI_SIGNALLING_MODE_CSI2;
+ hwcfg->csi_signalling_mode = CCS_CSI_SIGNALING_MODE_CSI_2_DPHY;
hwcfg->lanes = bus_cfg.bus.mipi_csi2.num_data_lanes;
break;
case V4L2_MBUS_CCP2:
@@ -3095,8 +3052,9 @@ static int smiapp_probe(struct i2c_client *client)
*/
if (sensor->hwcfg->module_board_orient ==
SMIAPP_MODULE_BOARD_ORIENT_180)
- sensor->hvflip_inv_mask = SMIAPP_IMAGE_ORIENTATION_HFLIP |
- SMIAPP_IMAGE_ORIENTATION_VFLIP;
+ sensor->hvflip_inv_mask =
+ CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR |
+ CCS_IMAGE_ORIENTATION_VERTICAL_FLIP;
rval = smiapp_call_quirk(sensor, limits);
if (rval) {
diff --git a/drivers/media/i2c/smiapp/smiapp.h b/drivers/media/i2c/smiapp/smiapp.h
index 1a67cf485dcc..c6e4e05a7522 100644
--- a/drivers/media/i2c/smiapp/smiapp.h
+++ b/drivers/media/i2c/smiapp/smiapp.h
@@ -15,6 +15,8 @@
#include <media/v4l2-ctrls.h>
#include <media/v4l2-subdev.h>
+#include "ccs-regs.h"
+
#include "smiapp-pll.h"
#include "smiapp-reg-defs.h"
#include "smiapp-regs.h"
@@ -220,7 +222,7 @@ struct smiapp_sensor {
struct gpio_desc *xshutdown;
void *ccs_limits;
u8 nbinning_subtypes;
- struct smiapp_binning_subtype binning_subtypes[SMIAPP_BINNING_SUBTYPES];
+ struct smiapp_binning_subtype binning_subtypes[CCS_LIM_BINNING_SUB_TYPE_MAX_N + 1];
u32 mbus_frame_fmts;
const struct smiapp_csi_data_format *csi_format;
const struct smiapp_csi_data_format *internal_csi_format;
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 013/106] smiapp: Remove quirk function for writing a single 8-bit register
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (10 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 012/106] smiapp: Use CCS registers Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 014/106] smiapp: Rename register access functions Sakari Ailus
` (84 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
This function is no longer needed as the smiapp_write() function can be
used to write 8-bit registers with plain register addresses.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/smiapp-quirk.c | 15 +++++----------
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/drivers/media/i2c/smiapp/smiapp-quirk.c b/drivers/media/i2c/smiapp/smiapp-quirk.c
index 24630c7650d2..9422eb61b424 100644
--- a/drivers/media/i2c/smiapp/smiapp-quirk.c
+++ b/drivers/media/i2c/smiapp/smiapp-quirk.c
@@ -14,11 +14,6 @@
#include "smiapp.h"
-static int smiapp_write_8(struct smiapp_sensor *sensor, u16 reg, u8 val)
-{
- return smiapp_write(sensor, reg, val);
-}
-
static int smiapp_write_8s(struct smiapp_sensor *sensor,
const struct smiapp_reg_8 *regs, int len)
{
@@ -26,7 +21,7 @@ static int smiapp_write_8s(struct smiapp_sensor *sensor,
int rval;
for (; len > 0; len--, regs++) {
- rval = smiapp_write_8(sensor, regs->reg, regs->val);
+ rval = smiapp_write(sensor, regs->reg, regs->val);
if (rval < 0) {
dev_err(&client->dev,
"error %d writing reg 0x%4.4x, val 0x%2.2x",
@@ -170,7 +165,7 @@ static int jt8ev1_post_poweron(struct smiapp_sensor *sensor)
static int jt8ev1_pre_streamon(struct smiapp_sensor *sensor)
{
- return smiapp_write_8(sensor, 0x3328, 0x00);
+ return smiapp_write(sensor, 0x3328, 0x00);
}
static int jt8ev1_post_streamoff(struct smiapp_sensor *sensor)
@@ -178,7 +173,7 @@ static int jt8ev1_post_streamoff(struct smiapp_sensor *sensor)
int rval;
/* Workaround: allows fast standby to work properly */
- rval = smiapp_write_8(sensor, 0x3205, 0x04);
+ rval = smiapp_write(sensor, 0x3205, 0x04);
if (rval < 0)
return rval;
@@ -186,11 +181,11 @@ static int jt8ev1_post_streamoff(struct smiapp_sensor *sensor)
usleep_range(2000, 2050);
/* Restore it */
- rval = smiapp_write_8(sensor, 0x3205, 0x00);
+ rval = smiapp_write(sensor, 0x3205, 0x00);
if (rval < 0)
return rval;
- return smiapp_write_8(sensor, 0x3328, 0x80);
+ return smiapp_write(sensor, 0x3328, 0x80);
}
static int jt8ev1_init(struct smiapp_sensor *sensor)
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 014/106] smiapp: Rename register access functions
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (11 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 013/106] smiapp: Remove quirk function for writing a single 8-bit register Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 015/106] smiapp: Internal rename to CCS Sakari Ailus
` (83 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
Rename register access functions by changing smiapp to ccs.
The functions operating on register addresses have "addr" appended to the
name.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/smiapp-core.c | 67 +++++++++++++------------
drivers/media/i2c/smiapp/smiapp-quirk.c | 22 ++++----
drivers/media/i2c/smiapp/smiapp-regs.c | 47 ++++++++---------
drivers/media/i2c/smiapp/smiapp-regs.h | 14 +++---
4 files changed, 76 insertions(+), 74 deletions(-)
diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c
index b9faf38d4bba..5b322194cb4b 100644
--- a/drivers/media/i2c/smiapp/smiapp-core.c
+++ b/drivers/media/i2c/smiapp/smiapp-core.c
@@ -180,7 +180,7 @@ static int ccs_read_all_limits(struct smiapp_sensor *sensor)
j++, reg += width, ptr += width) {
u32 val;
- ret = smiapp_read(sensor, reg, &val);
+ ret = ccs_read_addr(sensor, reg, &val);
if (ret)
goto out_err;
@@ -2450,59 +2450,60 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor)
rval = ccs_read(sensor, MODULE_MANUFACTURER_ID,
&minfo->mipi_manufacturer_id);
if (!rval && !minfo->mipi_manufacturer_id)
- rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_MANUFACTURER_ID,
- &minfo->smia_manufacturer_id);
+ rval = ccs_read_addr_8only(sensor,
+ SMIAPP_REG_U8_MANUFACTURER_ID,
+ &minfo->smia_manufacturer_id);
if (!rval)
- rval = smiapp_read_8only(sensor, CCS_R_MODULE_MODEL_ID,
- &minfo->model_id);
+ rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_MODEL_ID,
+ &minfo->model_id);
if (!rval)
- rval = smiapp_read_8only(sensor,
- CCS_R_MODULE_REVISION_NUMBER_MAJOR,
- &minfo->revision_number_major);
+ rval = ccs_read_addr_8only(sensor,
+ CCS_R_MODULE_REVISION_NUMBER_MAJOR,
+ &minfo->revision_number_major);
if (!rval)
- rval = smiapp_read_8only(sensor,
- CCS_R_MODULE_REVISION_NUMBER_MINOR,
- &minfo->revision_number_minor);
+ rval = ccs_read_addr_8only(sensor,
+ CCS_R_MODULE_REVISION_NUMBER_MINOR,
+ &minfo->revision_number_minor);
if (!rval)
- rval = smiapp_read_8only(sensor, CCS_R_MODULE_DATE_YEAR,
- &minfo->module_year);
+ rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_DATE_YEAR,
+ &minfo->module_year);
if (!rval)
- rval = smiapp_read_8only(sensor, CCS_R_MODULE_DATE_MONTH,
- &minfo->module_month);
+ rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_DATE_MONTH,
+ &minfo->module_month);
if (!rval)
- rval = smiapp_read_8only(sensor, CCS_R_MODULE_DATE_DAY,
- &minfo->module_day);
+ rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_DATE_DAY,
+ &minfo->module_day);
/* Sensor info */
if (!rval)
rval = ccs_read(sensor, SENSOR_MANUFACTURER_ID,
&minfo->sensor_mipi_manufacturer_id);
if (!rval && !minfo->sensor_mipi_manufacturer_id)
- rval = smiapp_read_8only(sensor,
- CCS_R_SENSOR_MANUFACTURER_ID,
- &minfo->sensor_smia_manufacturer_id);
+ rval = ccs_read_addr_8only(sensor,
+ CCS_R_SENSOR_MANUFACTURER_ID,
+ &minfo->sensor_smia_manufacturer_id);
if (!rval)
- rval = smiapp_read_8only(sensor,
- CCS_R_SENSOR_MODEL_ID,
- &minfo->sensor_model_id);
+ rval = ccs_read_addr_8only(sensor,
+ CCS_R_SENSOR_MODEL_ID,
+ &minfo->sensor_model_id);
if (!rval)
- rval = smiapp_read_8only(sensor,
- CCS_R_SENSOR_REVISION_NUMBER,
- &minfo->sensor_revision_number);
+ rval = ccs_read_addr_8only(sensor,
+ CCS_R_SENSOR_REVISION_NUMBER,
+ &minfo->sensor_revision_number);
if (!rval)
- rval = smiapp_read_8only(sensor,
- CCS_R_SENSOR_FIRMWARE_VERSION,
- &minfo->sensor_firmware_version);
+ rval = ccs_read_addr_8only(sensor,
+ CCS_R_SENSOR_FIRMWARE_VERSION,
+ &minfo->sensor_firmware_version);
/* SMIA */
if (!rval)
rval = ccs_read(sensor, MIPI_CCS_VERSION, &minfo->ccs_version);
if (!rval && !minfo->ccs_version)
- rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_SMIA_VERSION,
- &minfo->smia_version);
+ rval = ccs_read_addr_8only(sensor, SMIAPP_REG_U8_SMIA_VERSION,
+ &minfo->smia_version);
if (!rval && !minfo->ccs_version)
- rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_SMIAPP_VERSION,
- &minfo->smiapp_version);
+ rval = ccs_read_addr_8only(sensor, SMIAPP_REG_U8_SMIAPP_VERSION,
+ &minfo->smiapp_version);
if (rval) {
dev_err(&client->dev, "sensor detection failed\n");
diff --git a/drivers/media/i2c/smiapp/smiapp-quirk.c b/drivers/media/i2c/smiapp/smiapp-quirk.c
index 9422eb61b424..5db97a16eccf 100644
--- a/drivers/media/i2c/smiapp/smiapp-quirk.c
+++ b/drivers/media/i2c/smiapp/smiapp-quirk.c
@@ -14,14 +14,14 @@
#include "smiapp.h"
-static int smiapp_write_8s(struct smiapp_sensor *sensor,
- const struct smiapp_reg_8 *regs, int len)
+static int ccs_write_addr_8s(struct smiapp_sensor *sensor,
+ const struct smiapp_reg_8 *regs, int len)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
int rval;
for (; len > 0; len--, regs++) {
- rval = smiapp_write(sensor, regs->reg, regs->val);
+ rval = ccs_write_addr(sensor, regs->reg, regs->val);
if (rval < 0) {
dev_err(&client->dev,
"error %d writing reg 0x%4.4x, val 0x%2.2x",
@@ -81,7 +81,7 @@ static int jt8ew9_post_poweron(struct smiapp_sensor *sensor)
};
- return smiapp_write_8s(sensor, regs, ARRAY_SIZE(regs));
+ return ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs));
}
const struct smiapp_quirk smiapp_jt8ew9_quirk = {
@@ -102,7 +102,7 @@ static int imx125es_post_poweron(struct smiapp_sensor *sensor)
{ 0x3b08, 0x8c },
};
- return smiapp_write_8s(sensor, regs, ARRAY_SIZE(regs));
+ return ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs));
}
const struct smiapp_quirk smiapp_imx125es_quirk = {
@@ -148,13 +148,13 @@ static int jt8ev1_post_poweron(struct smiapp_sensor *sensor)
{ 0x30b0, 0x01 },
};
- rval = smiapp_write_8s(sensor, regs, ARRAY_SIZE(regs));
+ rval = ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs));
if (rval < 0)
return rval;
switch (sensor->hwcfg->ext_clk) {
case 9600000:
- return smiapp_write_8s(sensor, regs_96,
+ return ccs_write_addr_8s(sensor, regs_96,
ARRAY_SIZE(regs_96));
default:
dev_warn(&client->dev, "no MSRs for %d Hz ext_clk\n",
@@ -165,7 +165,7 @@ static int jt8ev1_post_poweron(struct smiapp_sensor *sensor)
static int jt8ev1_pre_streamon(struct smiapp_sensor *sensor)
{
- return smiapp_write(sensor, 0x3328, 0x00);
+ return ccs_write_addr(sensor, 0x3328, 0x00);
}
static int jt8ev1_post_streamoff(struct smiapp_sensor *sensor)
@@ -173,7 +173,7 @@ static int jt8ev1_post_streamoff(struct smiapp_sensor *sensor)
int rval;
/* Workaround: allows fast standby to work properly */
- rval = smiapp_write(sensor, 0x3205, 0x04);
+ rval = ccs_write_addr(sensor, 0x3205, 0x04);
if (rval < 0)
return rval;
@@ -181,11 +181,11 @@ static int jt8ev1_post_streamoff(struct smiapp_sensor *sensor)
usleep_range(2000, 2050);
/* Restore it */
- rval = smiapp_write(sensor, 0x3205, 0x00);
+ rval = ccs_write_addr(sensor, 0x3205, 0x00);
if (rval < 0)
return rval;
- return smiapp_write(sensor, 0x3328, 0x80);
+ return ccs_write_addr(sensor, 0x3328, 0x80);
}
static int jt8ev1_init(struct smiapp_sensor *sensor)
diff --git a/drivers/media/i2c/smiapp/smiapp-regs.c b/drivers/media/i2c/smiapp/smiapp-regs.c
index 904054d303ba..173d9f8fe56c 100644
--- a/drivers/media/i2c/smiapp/smiapp-regs.c
+++ b/drivers/media/i2c/smiapp/smiapp-regs.c
@@ -66,8 +66,8 @@ static uint32_t float_to_u32_mul_1000000(struct i2c_client *client,
* Read a 8/16/32-bit i2c register. The value is returned in 'val'.
* Returns zero if successful, or non-zero otherwise.
*/
-static int ____smiapp_read(struct smiapp_sensor *sensor, u16 reg,
- u16 len, u32 *val)
+static int ____ccs_read_addr(struct smiapp_sensor *sensor, u16 reg, u16 len,
+ u32 *val)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
struct i2c_msg msg;
@@ -113,8 +113,8 @@ static int ____smiapp_read(struct smiapp_sensor *sensor, u16 reg,
}
/* Read a register using 8-bit access only. */
-static int ____smiapp_read_8only(struct smiapp_sensor *sensor, u16 reg,
- u16 len, u32 *val)
+static int ____ccs_read_addr_8only(struct smiapp_sensor *sensor, u16 reg,
+ u16 len, u32 *val)
{
unsigned int i;
int rval;
@@ -124,7 +124,7 @@ static int ____smiapp_read_8only(struct smiapp_sensor *sensor, u16 reg,
for (i = 0; i < len; i++) {
u32 val8;
- rval = ____smiapp_read(sensor, reg + i, 1, &val8);
+ rval = ____ccs_read_addr(sensor, reg + i, 1, &val8);
if (rval < 0)
return rval;
*val |= val8 << ((len - i - 1) << 3);
@@ -147,18 +147,19 @@ unsigned int ccs_reg_width(u32 reg)
* Read a 8/16/32-bit i2c register. The value is returned in 'val'.
* Returns zero if successful, or non-zero otherwise.
*/
-static int __smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val,
- bool only8)
+static int __ccs_read_addr(struct smiapp_sensor *sensor, u32 reg, u32 *val,
+ bool only8)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
unsigned int len = ccs_reg_width(reg);
int rval;
if (!only8)
- rval = ____smiapp_read(sensor, SMIAPP_REG_ADDR(reg), len, val);
+ rval = ____ccs_read_addr(sensor, SMIAPP_REG_ADDR(reg), len,
+ val);
else
- rval = ____smiapp_read_8only(sensor, SMIAPP_REG_ADDR(reg), len,
- val);
+ rval = ____ccs_read_addr_8only(sensor, SMIAPP_REG_ADDR(reg),
+ len, val);
if (rval < 0)
return rval;
@@ -168,16 +169,16 @@ static int __smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val,
return 0;
}
-int smiapp_read_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val)
+int ccs_read_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val)
{
- return __smiapp_read(
+ return __ccs_read_addr(
sensor, reg, val,
smiapp_needs_quirk(sensor,
SMIAPP_QUIRK_FLAG_8BIT_READ_ONLY));
}
-static int smiapp_read_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val,
- bool force8)
+static int ccs_read_addr_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val,
+ bool force8)
{
int rval;
@@ -189,22 +190,22 @@ static int smiapp_read_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val,
return rval;
if (force8)
- return __smiapp_read(sensor, reg, val, true);
+ return __ccs_read_addr(sensor, reg, val, true);
- return smiapp_read_no_quirk(sensor, reg, val);
+ return ccs_read_addr_no_quirk(sensor, reg, val);
}
-int smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val)
+int ccs_read_addr(struct smiapp_sensor *sensor, u32 reg, u32 *val)
{
- return smiapp_read_quirk(sensor, reg, val, false);
+ return ccs_read_addr_quirk(sensor, reg, val, false);
}
-int smiapp_read_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val)
+int ccs_read_addr_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val)
{
- return smiapp_read_quirk(sensor, reg, val, true);
+ return ccs_read_addr_quirk(sensor, reg, val, true);
}
-int smiapp_write_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val)
+int ccs_write_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
struct i2c_msg msg;
@@ -253,7 +254,7 @@ int smiapp_write_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val)
* Write to a 8/16-bit register.
* Returns zero if successful, or non-zero otherwise.
*/
-int smiapp_write(struct smiapp_sensor *sensor, u32 reg, u32 val)
+int ccs_write_addr(struct smiapp_sensor *sensor, u32 reg, u32 val)
{
int rval;
@@ -263,5 +264,5 @@ int smiapp_write(struct smiapp_sensor *sensor, u32 reg, u32 val)
if (rval < 0)
return rval;
- return smiapp_write_no_quirk(sensor, reg, val);
+ return ccs_write_addr_no_quirk(sensor, reg, val);
}
diff --git a/drivers/media/i2c/smiapp/smiapp-regs.h b/drivers/media/i2c/smiapp/smiapp-regs.h
index dc946096f368..5df794f65dfc 100644
--- a/drivers/media/i2c/smiapp/smiapp-regs.h
+++ b/drivers/media/i2c/smiapp/smiapp-regs.h
@@ -20,18 +20,18 @@
struct smiapp_sensor;
-int smiapp_read_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val);
-int smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val);
-int smiapp_read_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val);
-int smiapp_write_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val);
-int smiapp_write(struct smiapp_sensor *sensor, u32 reg, u32 val);
+int ccs_read_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val);
+int ccs_read_addr(struct smiapp_sensor *sensor, u32 reg, u32 *val);
+int ccs_read_addr_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val);
+int ccs_write_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val);
+int ccs_write_addr(struct smiapp_sensor *sensor, u32 reg, u32 val);
unsigned int ccs_reg_width(u32 reg);
#define ccs_read(sensor, reg_name, val) \
- smiapp_read(sensor, CCS_R_##reg_name, val)
+ ccs_read_addr(sensor, CCS_R_##reg_name, val)
#define ccs_write(sensor, reg_name, val) \
- smiapp_write(sensor, CCS_R_##reg_name, val)
+ ccs_write_addr(sensor, CCS_R_##reg_name, val)
#endif
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 015/106] smiapp: Internal rename to CCS
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (12 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 014/106] smiapp: Rename register access functions Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 016/106] smiapp: Differentiate CCS sensors from SMIA in subdev naming Sakari Ailus
` (82 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
Rename internal names to reflect the driver's new reference. The module
name remains the same.
Also fix trivial coding style issues on the way related to e.g. alignment
changes due to the rename.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/Makefile | 4 +-
.../i2c/smiapp/{smiapp-core.c => ccs-core.c} | 888 +++++++++---------
.../smiapp/{smiapp-quirk.c => ccs-quirk.c} | 43 +-
.../smiapp/{smiapp-quirk.h => ccs-quirk.h} | 46 +-
.../{smiapp-regs.c => ccs-reg-access.c} | 41 +-
.../{smiapp-regs.h => ccs-reg-access.h} | 16 +-
drivers/media/i2c/smiapp/{smiapp.h => ccs.h} | 124 +--
7 files changed, 576 insertions(+), 586 deletions(-)
rename drivers/media/i2c/smiapp/{smiapp-core.c => ccs-core.c} (75%)
rename drivers/media/i2c/smiapp/{smiapp-quirk.c => ccs-quirk.c} (83%)
rename drivers/media/i2c/smiapp/{smiapp-quirk.h => ccs-quirk.h} (59%)
rename drivers/media/i2c/smiapp/{smiapp-regs.c => ccs-reg-access.c} (79%)
rename drivers/media/i2c/smiapp/{smiapp-regs.h => ccs-reg-access.h} (55%)
rename drivers/media/i2c/smiapp/{smiapp.h => ccs.h} (65%)
diff --git a/drivers/media/i2c/smiapp/Makefile b/drivers/media/i2c/smiapp/Makefile
index 2189de360db6..f86f871f0a58 100644
--- a/drivers/media/i2c/smiapp/Makefile
+++ b/drivers/media/i2c/smiapp/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
-smiapp-objs += smiapp-core.o smiapp-regs.o \
- smiapp-quirk.o ccs-limits.o
+smiapp-objs += ccs-core.o ccs-reg-access.o \
+ ccs-quirk.o ccs-limits.o
obj-$(CONFIG_VIDEO_SMIAPP) += smiapp.o
ccflags-y += -I $(srctree)/drivers/media/i2c
diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/ccs-core.c
similarity index 75%
rename from drivers/media/i2c/smiapp/smiapp-core.c
rename to drivers/media/i2c/smiapp/ccs-core.c
index 5b322194cb4b..dd093a7d2ef4 100644
--- a/drivers/media/i2c/smiapp/smiapp-core.c
+++ b/drivers/media/i2c/smiapp/ccs-core.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * drivers/media/i2c/smiapp/smiapp-core.c
+ * drivers/media/i2c/smiapp/ccs-core.c
*
* Generic driver for SMIA/SMIA++ compliant camera modules
*
@@ -27,10 +27,10 @@
#include <media/v4l2-fwnode.h>
#include <media/v4l2-device.h>
+#include "ccs.h"
#include "ccs-limits.h"
-#include "smiapp.h"
-#define SMIAPP_ALIGN_DIM(dim, flags) \
+#define CCS_ALIGN_DIM(dim, flags) \
((flags) & V4L2_SEL_FLAG_GE \
? ALIGN((dim), 2) \
: (dim) & ~1)
@@ -41,20 +41,20 @@ struct ccs_limit_offset {
} ccs_limit_offsets[CCS_L_LAST + 1];
/*
- * smiapp_module_idents - supported camera modules
+ * ccs_module_idents - supported camera modules
*/
-static const struct smiapp_module_ident smiapp_module_idents[] = {
- SMIAPP_IDENT_L(0x01, 0x022b, -1, "vs6555"),
- SMIAPP_IDENT_L(0x01, 0x022e, -1, "vw6558"),
- SMIAPP_IDENT_L(0x07, 0x7698, -1, "ovm7698"),
- SMIAPP_IDENT_L(0x0b, 0x4242, -1, "smiapp-003"),
- SMIAPP_IDENT_L(0x0c, 0x208a, -1, "tcm8330md"),
- SMIAPP_IDENT_LQ(0x0c, 0x2134, -1, "tcm8500md", &smiapp_tcm8500md_quirk),
- SMIAPP_IDENT_L(0x0c, 0x213e, -1, "et8en2"),
- SMIAPP_IDENT_L(0x0c, 0x2184, -1, "tcm8580md"),
- SMIAPP_IDENT_LQ(0x0c, 0x560f, -1, "jt8ew9", &smiapp_jt8ew9_quirk),
- SMIAPP_IDENT_LQ(0x10, 0x4141, -1, "jt8ev1", &smiapp_jt8ev1_quirk),
- SMIAPP_IDENT_LQ(0x10, 0x4241, -1, "imx125es", &smiapp_imx125es_quirk),
+static const struct ccs_module_ident ccs_module_idents[] = {
+ CCS_IDENT_L(0x01, 0x022b, -1, "vs6555"),
+ CCS_IDENT_L(0x01, 0x022e, -1, "vw6558"),
+ CCS_IDENT_L(0x07, 0x7698, -1, "ovm7698"),
+ CCS_IDENT_L(0x0b, 0x4242, -1, "smiapp-003"),
+ CCS_IDENT_L(0x0c, 0x208a, -1, "tcm8330md"),
+ CCS_IDENT_LQ(0x0c, 0x2134, -1, "tcm8500md", &smiapp_tcm8500md_quirk),
+ CCS_IDENT_L(0x0c, 0x213e, -1, "et8en2"),
+ CCS_IDENT_L(0x0c, 0x2184, -1, "tcm8580md"),
+ CCS_IDENT_LQ(0x0c, 0x560f, -1, "jt8ew9", &smiapp_jt8ew9_quirk),
+ CCS_IDENT_LQ(0x10, 0x4141, -1, "jt8ev1", &smiapp_jt8ev1_quirk),
+ CCS_IDENT_LQ(0x10, 0x4241, -1, "imx125es", &smiapp_imx125es_quirk),
};
/*
@@ -78,7 +78,7 @@ static void ccs_assign_limit(void *ptr, unsigned int width, u32 val)
}
}
-static int ccs_limit_ptr(struct smiapp_sensor *sensor, unsigned int limit,
+static int ccs_limit_ptr(struct ccs_sensor *sensor, unsigned int limit,
unsigned int offset, void **__ptr)
{
const struct ccs_limit *linfo;
@@ -98,7 +98,7 @@ static int ccs_limit_ptr(struct smiapp_sensor *sensor, unsigned int limit,
return 0;
}
-void ccs_replace_limit(struct smiapp_sensor *sensor,
+void ccs_replace_limit(struct ccs_sensor *sensor,
unsigned int limit, unsigned int offset, u32 val)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
@@ -118,7 +118,7 @@ void ccs_replace_limit(struct smiapp_sensor *sensor,
ccs_assign_limit(ptr, ccs_reg_width(linfo->reg), val);
}
-static u32 ccs_get_limit(struct smiapp_sensor *sensor,
+static u32 ccs_get_limit(struct ccs_sensor *sensor,
unsigned int limit, unsigned int offset)
{
void *ptr;
@@ -148,7 +148,7 @@ static u32 ccs_get_limit(struct smiapp_sensor *sensor,
#define CCS_LIM_AT(sensor, limit, offset) \
ccs_get_limit(sensor, CCS_L_##limit, CCS_L_##limit##_OFFSET(offset))
-static int ccs_read_all_limits(struct smiapp_sensor *sensor)
+static int ccs_read_all_limits(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
void *ptr, *alloc, *end;
@@ -224,7 +224,7 @@ static int ccs_read_all_limits(struct smiapp_sensor *sensor)
return ret;
}
-static int smiapp_read_frame_fmt(struct smiapp_sensor *sensor)
+static int ccs_read_frame_fmt(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
u8 fmt_model_type, fmt_model_subtype, ncol_desc, nrow_desc;
@@ -351,7 +351,7 @@ static int smiapp_read_frame_fmt(struct smiapp_sensor *sensor)
return 0;
}
-static int smiapp_pll_configure(struct smiapp_sensor *sensor)
+static int ccs_pll_configure(struct ccs_sensor *sensor)
{
struct smiapp_pll *pll = &sensor->pll;
int rval;
@@ -386,8 +386,7 @@ static int smiapp_pll_configure(struct smiapp_sensor *sensor)
return ccs_write(sensor, OP_SYS_CLK_DIV, pll->op.sys_clk_div);
}
-static int smiapp_pll_try(struct smiapp_sensor *sensor,
- struct smiapp_pll *pll)
+static int ccs_pll_try(struct ccs_sensor *sensor, struct smiapp_pll *pll)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
struct smiapp_pll_limits lim = {
@@ -425,7 +424,7 @@ static int smiapp_pll_try(struct smiapp_sensor *sensor,
return smiapp_pll_calculate(&client->dev, &lim, pll);
}
-static int smiapp_pll_update(struct smiapp_sensor *sensor)
+static int ccs_pll_update(struct ccs_sensor *sensor)
{
struct smiapp_pll *pll = &sensor->pll;
int rval;
@@ -437,7 +436,7 @@ static int smiapp_pll_update(struct smiapp_sensor *sensor)
pll->scale_m = sensor->scale_m;
pll->bits_per_pixel = sensor->csi_format->compressed;
- rval = smiapp_pll_try(sensor, pll);
+ rval = ccs_pll_try(sensor, pll);
if (rval < 0)
return rval;
@@ -455,12 +454,12 @@ static int smiapp_pll_update(struct smiapp_sensor *sensor)
*
*/
-static void __smiapp_update_exposure_limits(struct smiapp_sensor *sensor)
+static void __ccs_update_exposure_limits(struct ccs_sensor *sensor)
{
struct v4l2_ctrl *ctrl = sensor->exposure;
int max;
- max = sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height
+ max = sensor->pixel_array->crop[CCS_PA_PAD_SRC].height
+ sensor->vblank->val
- CCS_LIM(sensor, COARSE_INTEGRATION_TIME_MAX_MARGIN);
@@ -475,40 +474,40 @@ static void __smiapp_update_exposure_limits(struct smiapp_sensor *sensor)
* 3. Pixel order, same as in pixel_order_str. Formats for all four pixel
* orders must be defined.
*/
-static const struct smiapp_csi_data_format smiapp_csi_data_formats[] = {
- { MEDIA_BUS_FMT_SGRBG16_1X16, 16, 16, SMIAPP_PIXEL_ORDER_GRBG, },
- { MEDIA_BUS_FMT_SRGGB16_1X16, 16, 16, SMIAPP_PIXEL_ORDER_RGGB, },
- { MEDIA_BUS_FMT_SBGGR16_1X16, 16, 16, SMIAPP_PIXEL_ORDER_BGGR, },
- { MEDIA_BUS_FMT_SGBRG16_1X16, 16, 16, SMIAPP_PIXEL_ORDER_GBRG, },
- { MEDIA_BUS_FMT_SGRBG14_1X14, 14, 14, SMIAPP_PIXEL_ORDER_GRBG, },
- { MEDIA_BUS_FMT_SRGGB14_1X14, 14, 14, SMIAPP_PIXEL_ORDER_RGGB, },
- { MEDIA_BUS_FMT_SBGGR14_1X14, 14, 14, SMIAPP_PIXEL_ORDER_BGGR, },
- { MEDIA_BUS_FMT_SGBRG14_1X14, 14, 14, SMIAPP_PIXEL_ORDER_GBRG, },
- { MEDIA_BUS_FMT_SGRBG12_1X12, 12, 12, SMIAPP_PIXEL_ORDER_GRBG, },
- { MEDIA_BUS_FMT_SRGGB12_1X12, 12, 12, SMIAPP_PIXEL_ORDER_RGGB, },
- { MEDIA_BUS_FMT_SBGGR12_1X12, 12, 12, SMIAPP_PIXEL_ORDER_BGGR, },
- { MEDIA_BUS_FMT_SGBRG12_1X12, 12, 12, SMIAPP_PIXEL_ORDER_GBRG, },
- { MEDIA_BUS_FMT_SGRBG10_1X10, 10, 10, SMIAPP_PIXEL_ORDER_GRBG, },
- { MEDIA_BUS_FMT_SRGGB10_1X10, 10, 10, SMIAPP_PIXEL_ORDER_RGGB, },
- { MEDIA_BUS_FMT_SBGGR10_1X10, 10, 10, SMIAPP_PIXEL_ORDER_BGGR, },
- { MEDIA_BUS_FMT_SGBRG10_1X10, 10, 10, SMIAPP_PIXEL_ORDER_GBRG, },
- { MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8, 10, 8, SMIAPP_PIXEL_ORDER_GRBG, },
- { MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8, 10, 8, SMIAPP_PIXEL_ORDER_RGGB, },
- { MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8, 10, 8, SMIAPP_PIXEL_ORDER_BGGR, },
- { MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8, 10, 8, SMIAPP_PIXEL_ORDER_GBRG, },
- { MEDIA_BUS_FMT_SGRBG8_1X8, 8, 8, SMIAPP_PIXEL_ORDER_GRBG, },
- { MEDIA_BUS_FMT_SRGGB8_1X8, 8, 8, SMIAPP_PIXEL_ORDER_RGGB, },
- { MEDIA_BUS_FMT_SBGGR8_1X8, 8, 8, SMIAPP_PIXEL_ORDER_BGGR, },
- { MEDIA_BUS_FMT_SGBRG8_1X8, 8, 8, SMIAPP_PIXEL_ORDER_GBRG, },
+static const struct ccs_csi_data_format ccs_csi_data_formats[] = {
+ { MEDIA_BUS_FMT_SGRBG16_1X16, 16, 16, CCS_PIXEL_ORDER_GRBG, },
+ { MEDIA_BUS_FMT_SRGGB16_1X16, 16, 16, CCS_PIXEL_ORDER_RGGB, },
+ { MEDIA_BUS_FMT_SBGGR16_1X16, 16, 16, CCS_PIXEL_ORDER_BGGR, },
+ { MEDIA_BUS_FMT_SGBRG16_1X16, 16, 16, CCS_PIXEL_ORDER_GBRG, },
+ { MEDIA_BUS_FMT_SGRBG14_1X14, 14, 14, CCS_PIXEL_ORDER_GRBG, },
+ { MEDIA_BUS_FMT_SRGGB14_1X14, 14, 14, CCS_PIXEL_ORDER_RGGB, },
+ { MEDIA_BUS_FMT_SBGGR14_1X14, 14, 14, CCS_PIXEL_ORDER_BGGR, },
+ { MEDIA_BUS_FMT_SGBRG14_1X14, 14, 14, CCS_PIXEL_ORDER_GBRG, },
+ { MEDIA_BUS_FMT_SGRBG12_1X12, 12, 12, CCS_PIXEL_ORDER_GRBG, },
+ { MEDIA_BUS_FMT_SRGGB12_1X12, 12, 12, CCS_PIXEL_ORDER_RGGB, },
+ { MEDIA_BUS_FMT_SBGGR12_1X12, 12, 12, CCS_PIXEL_ORDER_BGGR, },
+ { MEDIA_BUS_FMT_SGBRG12_1X12, 12, 12, CCS_PIXEL_ORDER_GBRG, },
+ { MEDIA_BUS_FMT_SGRBG10_1X10, 10, 10, CCS_PIXEL_ORDER_GRBG, },
+ { MEDIA_BUS_FMT_SRGGB10_1X10, 10, 10, CCS_PIXEL_ORDER_RGGB, },
+ { MEDIA_BUS_FMT_SBGGR10_1X10, 10, 10, CCS_PIXEL_ORDER_BGGR, },
+ { MEDIA_BUS_FMT_SGBRG10_1X10, 10, 10, CCS_PIXEL_ORDER_GBRG, },
+ { MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8, 10, 8, CCS_PIXEL_ORDER_GRBG, },
+ { MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8, 10, 8, CCS_PIXEL_ORDER_RGGB, },
+ { MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8, 10, 8, CCS_PIXEL_ORDER_BGGR, },
+ { MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8, 10, 8, CCS_PIXEL_ORDER_GBRG, },
+ { MEDIA_BUS_FMT_SGRBG8_1X8, 8, 8, CCS_PIXEL_ORDER_GRBG, },
+ { MEDIA_BUS_FMT_SRGGB8_1X8, 8, 8, CCS_PIXEL_ORDER_RGGB, },
+ { MEDIA_BUS_FMT_SBGGR8_1X8, 8, 8, CCS_PIXEL_ORDER_BGGR, },
+ { MEDIA_BUS_FMT_SGBRG8_1X8, 8, 8, CCS_PIXEL_ORDER_GBRG, },
};
static const char *pixel_order_str[] = { "GRBG", "RGGB", "BGGR", "GBRG" };
#define to_csi_format_idx(fmt) (((unsigned long)(fmt) \
- - (unsigned long)smiapp_csi_data_formats) \
- / sizeof(*smiapp_csi_data_formats))
+ - (unsigned long)ccs_csi_data_formats) \
+ / sizeof(*ccs_csi_data_formats))
-static u32 smiapp_pixel_order(struct smiapp_sensor *sensor)
+static u32 ccs_pixel_order(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
int flip = 0;
@@ -527,31 +526,31 @@ static u32 smiapp_pixel_order(struct smiapp_sensor *sensor)
return sensor->default_pixel_order ^ flip;
}
-static void smiapp_update_mbus_formats(struct smiapp_sensor *sensor)
+static void ccs_update_mbus_formats(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
unsigned int csi_format_idx =
to_csi_format_idx(sensor->csi_format) & ~3;
unsigned int internal_csi_format_idx =
to_csi_format_idx(sensor->internal_csi_format) & ~3;
- unsigned int pixel_order = smiapp_pixel_order(sensor);
+ unsigned int pixel_order = ccs_pixel_order(sensor);
sensor->mbus_frame_fmts =
sensor->default_mbus_frame_fmts << pixel_order;
sensor->csi_format =
- &smiapp_csi_data_formats[csi_format_idx + pixel_order];
+ &ccs_csi_data_formats[csi_format_idx + pixel_order];
sensor->internal_csi_format =
- &smiapp_csi_data_formats[internal_csi_format_idx
+ &ccs_csi_data_formats[internal_csi_format_idx
+ pixel_order];
BUG_ON(max(internal_csi_format_idx, csi_format_idx) + pixel_order
- >= ARRAY_SIZE(smiapp_csi_data_formats));
+ >= ARRAY_SIZE(ccs_csi_data_formats));
dev_dbg(&client->dev, "new pixel order %s\n",
pixel_order_str[pixel_order]);
}
-static const char * const smiapp_test_patterns[] = {
+static const char * const ccs_test_patterns[] = {
"Disabled",
"Solid Colour",
"Eight Vertical Colour Bars",
@@ -559,10 +558,10 @@ static const char * const smiapp_test_patterns[] = {
"Pseudorandom Sequence (PN9)",
};
-static int smiapp_set_ctrl(struct v4l2_ctrl *ctrl)
+static int ccs_set_ctrl(struct v4l2_ctrl *ctrl)
{
- struct smiapp_sensor *sensor =
- container_of(ctrl->handler, struct smiapp_subdev, ctrl_handler)
+ struct ccs_sensor *sensor =
+ container_of(ctrl->handler, struct ccs_subdev, ctrl_handler)
->sensor;
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
int pm_status;
@@ -585,17 +584,17 @@ static int smiapp_set_ctrl(struct v4l2_ctrl *ctrl)
orient ^= sensor->hvflip_inv_mask;
- smiapp_update_mbus_formats(sensor);
+ ccs_update_mbus_formats(sensor);
break;
case V4L2_CID_VBLANK:
exposure = sensor->exposure->val;
- __smiapp_update_exposure_limits(sensor);
+ __ccs_update_exposure_limits(sensor);
if (exposure > sensor->exposure->maximum) {
sensor->exposure->val = sensor->exposure->maximum;
- rval = smiapp_set_ctrl(sensor->exposure);
+ rval = ccs_set_ctrl(sensor->exposure);
if (rval < 0)
return rval;
}
@@ -605,7 +604,7 @@ static int smiapp_set_ctrl(struct v4l2_ctrl *ctrl)
if (sensor->streaming)
return -EBUSY;
- rval = smiapp_pll_update(sensor);
+ rval = ccs_pll_update(sensor);
if (rval)
return rval;
@@ -641,14 +640,14 @@ static int smiapp_set_ctrl(struct v4l2_ctrl *ctrl)
case V4L2_CID_VBLANK:
rval = ccs_write(sensor, FRAME_LENGTH_LINES,
sensor->pixel_array->crop[
- SMIAPP_PA_PAD_SRC].height
+ CCS_PA_PAD_SRC].height
+ ctrl->val);
break;
case V4L2_CID_HBLANK:
rval = ccs_write(sensor, LINE_LENGTH_PCK,
sensor->pixel_array->crop[
- SMIAPP_PA_PAD_SRC].width
+ CCS_PA_PAD_SRC].width
+ ctrl->val);
break;
@@ -689,11 +688,11 @@ static int smiapp_set_ctrl(struct v4l2_ctrl *ctrl)
return rval;
}
-static const struct v4l2_ctrl_ops smiapp_ctrl_ops = {
- .s_ctrl = smiapp_set_ctrl,
+static const struct v4l2_ctrl_ops ccs_ctrl_ops = {
+ .s_ctrl = ccs_set_ctrl,
};
-static int smiapp_init_controls(struct smiapp_sensor *sensor)
+static int ccs_init_controls(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
int rval;
@@ -705,7 +704,7 @@ static int smiapp_init_controls(struct smiapp_sensor *sensor)
sensor->pixel_array->ctrl_handler.lock = &sensor->mutex;
sensor->analog_gain = v4l2_ctrl_new_std(
- &sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops,
+ &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
V4L2_CID_ANALOGUE_GAIN,
CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN),
CCS_LIM(sensor, ANALOG_GAIN_CODE_MAX),
@@ -714,38 +713,38 @@ static int smiapp_init_controls(struct smiapp_sensor *sensor)
/* Exposure limits will be updated soon, use just something here. */
sensor->exposure = v4l2_ctrl_new_std(
- &sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops,
+ &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
V4L2_CID_EXPOSURE, 0, 0, 1, 0);
sensor->hflip = v4l2_ctrl_new_std(
- &sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops,
+ &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
V4L2_CID_HFLIP, 0, 1, 1, 0);
sensor->vflip = v4l2_ctrl_new_std(
- &sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops,
+ &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
V4L2_CID_VFLIP, 0, 1, 1, 0);
sensor->vblank = v4l2_ctrl_new_std(
- &sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops,
+ &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
V4L2_CID_VBLANK, 0, 1, 1, 0);
if (sensor->vblank)
sensor->vblank->flags |= V4L2_CTRL_FLAG_UPDATE;
sensor->hblank = v4l2_ctrl_new_std(
- &sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops,
+ &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
V4L2_CID_HBLANK, 0, 1, 1, 0);
if (sensor->hblank)
sensor->hblank->flags |= V4L2_CTRL_FLAG_UPDATE;
sensor->pixel_rate_parray = v4l2_ctrl_new_std(
- &sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops,
+ &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
V4L2_CID_PIXEL_RATE, 1, INT_MAX, 1, 1);
v4l2_ctrl_new_std_menu_items(&sensor->pixel_array->ctrl_handler,
- &smiapp_ctrl_ops, V4L2_CID_TEST_PATTERN,
- ARRAY_SIZE(smiapp_test_patterns) - 1,
- 0, 0, smiapp_test_patterns);
+ &ccs_ctrl_ops, V4L2_CID_TEST_PATTERN,
+ ARRAY_SIZE(ccs_test_patterns) - 1,
+ 0, 0, ccs_test_patterns);
if (sensor->pixel_array->ctrl_handler.error) {
dev_err(&client->dev,
@@ -766,7 +765,7 @@ static int smiapp_init_controls(struct smiapp_sensor *sensor)
sensor->src->ctrl_handler.lock = &sensor->mutex;
sensor->pixel_rate_csi = v4l2_ctrl_new_std(
- &sensor->src->ctrl_handler, &smiapp_ctrl_ops,
+ &sensor->src->ctrl_handler, &ccs_ctrl_ops,
V4L2_CID_PIXEL_RATE, 1, INT_MAX, 1, 1);
if (sensor->src->ctrl_handler.error) {
@@ -785,7 +784,7 @@ static int smiapp_init_controls(struct smiapp_sensor *sensor)
* For controls that require information on available media bus codes
* and linke frequencies.
*/
-static int smiapp_init_late_controls(struct smiapp_sensor *sensor)
+static int ccs_init_late_controls(struct ccs_sensor *sensor)
{
unsigned long *valid_link_freqs = &sensor->valid_link_freqs[
sensor->csi_format->compressed - sensor->compressed_min_bpp];
@@ -796,19 +795,19 @@ static int smiapp_init_late_controls(struct smiapp_sensor *sensor)
sensor->test_data[i] = v4l2_ctrl_new_std(
&sensor->pixel_array->ctrl_handler,
- &smiapp_ctrl_ops, V4L2_CID_TEST_PATTERN_RED + i,
+ &ccs_ctrl_ops, V4L2_CID_TEST_PATTERN_RED + i,
0, max_value, 1, max_value);
}
sensor->link_freq = v4l2_ctrl_new_int_menu(
- &sensor->src->ctrl_handler, &smiapp_ctrl_ops,
+ &sensor->src->ctrl_handler, &ccs_ctrl_ops,
V4L2_CID_LINK_FREQ, __fls(*valid_link_freqs),
__ffs(*valid_link_freqs), sensor->hwcfg->op_sys_clock);
return sensor->src->ctrl_handler.error;
}
-static void smiapp_free_controls(struct smiapp_sensor *sensor)
+static void ccs_free_controls(struct ccs_sensor *sensor)
{
unsigned int i;
@@ -816,7 +815,7 @@ static void smiapp_free_controls(struct smiapp_sensor *sensor)
v4l2_ctrl_handler_free(&sensor->ssds[i].ctrl_handler);
}
-static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor)
+static int ccs_get_mbus_formats(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
struct smiapp_pll *pll = &sensor->pll;
@@ -863,11 +862,11 @@ static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor)
dev_dbg(&client->dev, "%u: bpp %u, compressed %u\n",
i, fmt >> 8, (u8)fmt);
- for (j = 0; j < ARRAY_SIZE(smiapp_csi_data_formats); j++) {
- const struct smiapp_csi_data_format *f =
- &smiapp_csi_data_formats[j];
+ for (j = 0; j < ARRAY_SIZE(ccs_csi_data_formats); j++) {
+ const struct ccs_csi_data_format *f =
+ &ccs_csi_data_formats[j];
- if (f->pixel_order != SMIAPP_PIXEL_ORDER_GRBG)
+ if (f->pixel_order != CCS_PIXEL_ORDER_GRBG)
continue;
if (f->width != fmt >>
@@ -887,12 +886,12 @@ static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor)
pll->binning_vertical = 1;
pll->scale_m = sensor->scale_m;
- for (i = 0; i < ARRAY_SIZE(smiapp_csi_data_formats); i++) {
+ for (i = 0; i < ARRAY_SIZE(ccs_csi_data_formats); i++) {
sensor->compressed_min_bpp =
- min(smiapp_csi_data_formats[i].compressed,
+ min(ccs_csi_data_formats[i].compressed,
sensor->compressed_min_bpp);
compressed_max_bpp =
- max(smiapp_csi_data_formats[i].compressed,
+ max(ccs_csi_data_formats[i].compressed,
compressed_max_bpp);
}
@@ -903,9 +902,9 @@ static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor)
if (!sensor->valid_link_freqs)
return -ENOMEM;
- for (i = 0; i < ARRAY_SIZE(smiapp_csi_data_formats); i++) {
- const struct smiapp_csi_data_format *f =
- &smiapp_csi_data_formats[i];
+ for (i = 0; i < ARRAY_SIZE(ccs_csi_data_formats); i++) {
+ const struct ccs_csi_data_format *f =
+ &ccs_csi_data_formats[i];
unsigned long *valid_link_freqs =
&sensor->valid_link_freqs[
f->compressed - sensor->compressed_min_bpp];
@@ -919,7 +918,7 @@ static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor)
for (j = 0; sensor->hwcfg->op_sys_clock[j]; j++) {
pll->link_freq = sensor->hwcfg->op_sys_clock[j];
- rval = smiapp_pll_try(sensor, pll);
+ rval = ccs_pll_try(sensor, pll);
dev_dbg(&client->dev, "link freq %u Hz, bpp %u %s\n",
pll->link_freq, pll->bits_per_pixel,
rval ? "not ok" : "ok");
@@ -951,12 +950,12 @@ static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor)
return -EINVAL;
}
- smiapp_update_mbus_formats(sensor);
+ ccs_update_mbus_formats(sensor);
return 0;
}
-static void smiapp_update_blanking(struct smiapp_sensor *sensor)
+static void ccs_update_blanking(struct ccs_sensor *sensor)
{
struct v4l2_ctrl *vblank = sensor->vblank;
struct v4l2_ctrl *hblank = sensor->hblank;
@@ -980,42 +979,42 @@ static void smiapp_update_blanking(struct smiapp_sensor *sensor)
min = max_t(int,
CCS_LIM(sensor, MIN_FRAME_BLANKING_LINES),
min_fll -
- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height);
- max = max_fll - sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height;
+ sensor->pixel_array->crop[CCS_PA_PAD_SRC].height);
+ max = max_fll - sensor->pixel_array->crop[CCS_PA_PAD_SRC].height;
__v4l2_ctrl_modify_range(vblank, min, max, vblank->step, min);
min = max_t(int,
min_llp -
- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].width,
+ sensor->pixel_array->crop[CCS_PA_PAD_SRC].width,
min_lbp);
- max = max_llp - sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].width;
+ max = max_llp - sensor->pixel_array->crop[CCS_PA_PAD_SRC].width;
__v4l2_ctrl_modify_range(hblank, min, max, hblank->step, min);
- __smiapp_update_exposure_limits(sensor);
+ __ccs_update_exposure_limits(sensor);
}
-static int smiapp_pll_blanking_update(struct smiapp_sensor *sensor)
+static int ccs_pll_blanking_update(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
int rval;
- rval = smiapp_pll_update(sensor);
+ rval = ccs_pll_update(sensor);
if (rval < 0)
return rval;
/* Output from pixel array, including blanking */
- smiapp_update_blanking(sensor);
+ ccs_update_blanking(sensor);
dev_dbg(&client->dev, "vblank\t\t%d\n", sensor->vblank->val);
dev_dbg(&client->dev, "hblank\t\t%d\n", sensor->hblank->val);
dev_dbg(&client->dev, "real timeperframe\t100/%d\n",
sensor->pll.pixel_rate_pixel_array /
- ((sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].width
+ ((sensor->pixel_array->crop[CCS_PA_PAD_SRC].width
+ sensor->hblank->val) *
- (sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height
+ (sensor->pixel_array->crop[CCS_PA_PAD_SRC].height
+ sensor->vblank->val) / 100));
return 0;
@@ -1027,8 +1026,8 @@ static int smiapp_pll_blanking_update(struct smiapp_sensor *sensor)
*
*/
-static int smiapp_read_nvm_page(struct smiapp_sensor *sensor, u32 p, u8 *nvm,
- u8 *status)
+static int ccs_read_nvm_page(struct ccs_sensor *sensor, u32 p, u8 *nvm,
+ u8 *status)
{
unsigned int i;
int rval;
@@ -1082,8 +1081,8 @@ static int smiapp_read_nvm_page(struct smiapp_sensor *sensor, u32 p, u8 *nvm,
return 0;
}
-static int smiapp_read_nvm(struct smiapp_sensor *sensor, unsigned char *nvm,
- size_t nvm_size)
+static int ccs_read_nvm(struct ccs_sensor *sensor, unsigned char *nvm,
+ size_t nvm_size)
{
u8 status = 0;
u32 p;
@@ -1091,7 +1090,7 @@ static int smiapp_read_nvm(struct smiapp_sensor *sensor, unsigned char *nvm,
for (p = 0; p < nvm_size / (CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P + 1)
&& !rval; p++) {
- rval = smiapp_read_nvm_page(sensor, p, nvm, &status);
+ rval = ccs_read_nvm_page(sensor, p, nvm, &status);
nvm += CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P + 1;
}
@@ -1111,7 +1110,7 @@ static int smiapp_read_nvm(struct smiapp_sensor *sensor, unsigned char *nvm,
* SMIA++ CCI address control
*
*/
-static int smiapp_change_cci_addr(struct smiapp_sensor *sensor)
+static int ccs_change_cci_addr(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
int rval;
@@ -1142,9 +1141,9 @@ static int smiapp_change_cci_addr(struct smiapp_sensor *sensor)
* SMIA++ Mode Control
*
*/
-static int smiapp_setup_flash_strobe(struct smiapp_sensor *sensor)
+static int ccs_setup_flash_strobe(struct ccs_sensor *sensor)
{
- struct smiapp_flash_strobe_parms *strobe_setup;
+ struct ccs_flash_strobe_parms *strobe_setup;
unsigned int ext_freq = sensor->hwcfg->ext_clk;
u32 tmp;
u32 strobe_adjustment;
@@ -1268,16 +1267,16 @@ static int smiapp_setup_flash_strobe(struct smiapp_sensor *sensor)
* Power management
*/
-static int smiapp_power_on(struct device *dev)
+static int ccs_power_on(struct device *dev)
{
struct v4l2_subdev *subdev = dev_get_drvdata(dev);
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
/*
* The sub-device related to the I2C device is always the
* source one, i.e. ssds[0].
*/
- struct smiapp_sensor *sensor =
- container_of(ssd, struct smiapp_sensor, ssds[0]);
+ struct ccs_sensor *sensor =
+ container_of(ssd, struct ccs_sensor, ssds[0]);
unsigned int sleep;
int rval;
@@ -1312,7 +1311,7 @@ static int smiapp_power_on(struct device *dev)
*/
if (sensor->hwcfg->i2c_addr_alt) {
- rval = smiapp_change_cci_addr(sensor);
+ rval = ccs_change_cci_addr(sensor);
if (rval) {
dev_err(dev, "cci address change error\n");
goto out_cci_addr_fail;
@@ -1326,7 +1325,7 @@ static int smiapp_power_on(struct device *dev)
}
if (sensor->hwcfg->i2c_addr_alt) {
- rval = smiapp_change_cci_addr(sensor);
+ rval = ccs_change_cci_addr(sensor);
if (rval) {
dev_err(dev, "cci address change error\n");
goto out_cci_addr_fail;
@@ -1372,7 +1371,7 @@ static int smiapp_power_on(struct device *dev)
if (rval < 0)
goto out_cci_addr_fail;
- rval = smiapp_call_quirk(sensor, post_poweron);
+ rval = ccs_call_quirk(sensor, post_poweron);
if (rval) {
dev_err(dev, "post_poweron quirks failed\n");
goto out_cci_addr_fail;
@@ -1390,12 +1389,12 @@ static int smiapp_power_on(struct device *dev)
return rval;
}
-static int smiapp_power_off(struct device *dev)
+static int ccs_power_off(struct device *dev)
{
struct v4l2_subdev *subdev = dev_get_drvdata(dev);
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
- struct smiapp_sensor *sensor =
- container_of(ssd, struct smiapp_sensor, ssds[0]);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+ struct ccs_sensor *sensor =
+ container_of(ssd, struct ccs_sensor, ssds[0]);
/*
* Currently power/clock to lens are enable/disabled separately
@@ -1420,7 +1419,7 @@ static int smiapp_power_off(struct device *dev)
* Video stream management
*/
-static int smiapp_start_streaming(struct smiapp_sensor *sensor)
+static int ccs_start_streaming(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
unsigned int binning_mode;
@@ -1454,33 +1453,33 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
goto out;
/* Set up PLL */
- rval = smiapp_pll_configure(sensor);
+ rval = ccs_pll_configure(sensor);
if (rval)
goto out;
/* Analog crop start coordinates */
rval = ccs_write(sensor, X_ADDR_START,
- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].left);
+ sensor->pixel_array->crop[CCS_PA_PAD_SRC].left);
if (rval < 0)
goto out;
rval = ccs_write(sensor, Y_ADDR_START,
- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].top);
+ sensor->pixel_array->crop[CCS_PA_PAD_SRC].top);
if (rval < 0)
goto out;
/* Analog crop end coordinates */
rval = ccs_write(
sensor, X_ADDR_END,
- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].left
- + sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].width - 1);
+ sensor->pixel_array->crop[CCS_PA_PAD_SRC].left
+ + sensor->pixel_array->crop[CCS_PA_PAD_SRC].width - 1);
if (rval < 0)
goto out;
rval = ccs_write(
sensor, Y_ADDR_END,
- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].top
- + sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height - 1);
+ sensor->pixel_array->crop[CCS_PA_PAD_SRC].top
+ + sensor->pixel_array->crop[CCS_PA_PAD_SRC].height - 1);
if (rval < 0)
goto out;
@@ -1494,25 +1493,25 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
== CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP) {
rval = ccs_write(
sensor, DIGITAL_CROP_X_OFFSET,
- sensor->scaler->crop[SMIAPP_PAD_SINK].left);
+ sensor->scaler->crop[CCS_PAD_SINK].left);
if (rval < 0)
goto out;
rval = ccs_write(
sensor, DIGITAL_CROP_Y_OFFSET,
- sensor->scaler->crop[SMIAPP_PAD_SINK].top);
+ sensor->scaler->crop[CCS_PAD_SINK].top);
if (rval < 0)
goto out;
rval = ccs_write(
sensor, DIGITAL_CROP_IMAGE_WIDTH,
- sensor->scaler->crop[SMIAPP_PAD_SINK].width);
+ sensor->scaler->crop[CCS_PAD_SINK].width);
if (rval < 0)
goto out;
rval = ccs_write(
sensor, DIGITAL_CROP_IMAGE_HEIGHT,
- sensor->scaler->crop[SMIAPP_PAD_SINK].height);
+ sensor->scaler->crop[CCS_PAD_SINK].height);
if (rval < 0)
goto out;
}
@@ -1531,11 +1530,11 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
/* Output size from sensor */
rval = ccs_write(sensor, X_OUTPUT_SIZE,
- sensor->src->crop[SMIAPP_PAD_SRC].width);
+ sensor->src->crop[CCS_PAD_SRC].width);
if (rval < 0)
goto out;
rval = ccs_write(sensor, Y_OUTPUT_SIZE,
- sensor->src->crop[SMIAPP_PAD_SRC].height);
+ sensor->src->crop[CCS_PAD_SRC].height);
if (rval < 0)
goto out;
@@ -1544,12 +1543,12 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
SMIAPP_FLASH_MODE_CAPABILITY_MULTIPLE_STROBE) &&
sensor->hwcfg->strobe_setup != NULL &&
sensor->hwcfg->strobe_setup->trigger != 0) {
- rval = smiapp_setup_flash_strobe(sensor);
+ rval = ccs_setup_flash_strobe(sensor);
if (rval)
goto out;
}
- rval = smiapp_call_quirk(sensor, pre_streamon);
+ rval = ccs_call_quirk(sensor, pre_streamon);
if (rval) {
dev_err(&client->dev, "pre_streamon quirks failed\n");
goto out;
@@ -1563,7 +1562,7 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
return rval;
}
-static int smiapp_stop_streaming(struct smiapp_sensor *sensor)
+static int ccs_stop_streaming(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
int rval;
@@ -1573,7 +1572,7 @@ static int smiapp_stop_streaming(struct smiapp_sensor *sensor)
if (rval)
goto out;
- rval = smiapp_call_quirk(sensor, post_streamoff);
+ rval = ccs_call_quirk(sensor, post_streamoff);
if (rval)
dev_err(&client->dev, "post_streamoff quirks failed\n");
@@ -1586,7 +1585,7 @@ static int smiapp_stop_streaming(struct smiapp_sensor *sensor)
* V4L2 subdev video operations
*/
-static int smiapp_pm_get_init(struct smiapp_sensor *sensor)
+static int ccs_pm_get_init(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
int rval;
@@ -1610,9 +1609,9 @@ static int smiapp_pm_get_init(struct smiapp_sensor *sensor)
return 0;
}
-static int smiapp_set_stream(struct v4l2_subdev *subdev, int enable)
+static int ccs_set_stream(struct v4l2_subdev *subdev, int enable)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
int rval;
@@ -1620,7 +1619,7 @@ static int smiapp_set_stream(struct v4l2_subdev *subdev, int enable)
return 0;
if (!enable) {
- smiapp_stop_streaming(sensor);
+ ccs_stop_streaming(sensor);
sensor->streaming = false;
pm_runtime_mark_last_busy(&client->dev);
pm_runtime_put_autosuspend(&client->dev);
@@ -1628,13 +1627,13 @@ static int smiapp_set_stream(struct v4l2_subdev *subdev, int enable)
return 0;
}
- rval = smiapp_pm_get_init(sensor);
+ rval = ccs_pm_get_init(sensor);
if (rval)
return rval;
sensor->streaming = true;
- rval = smiapp_start_streaming(sensor);
+ rval = ccs_start_streaming(sensor);
if (rval < 0) {
sensor->streaming = false;
pm_runtime_mark_last_busy(&client->dev);
@@ -1644,12 +1643,12 @@ static int smiapp_set_stream(struct v4l2_subdev *subdev, int enable)
return rval;
}
-static int smiapp_enum_mbus_code(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_mbus_code_enum *code)
+static int ccs_enum_mbus_code(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_mbus_code_enum *code)
{
struct i2c_client *client = v4l2_get_subdevdata(subdev);
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
unsigned int i;
int idx = -1;
int rval = -EINVAL;
@@ -1659,7 +1658,7 @@ static int smiapp_enum_mbus_code(struct v4l2_subdev *subdev,
dev_err(&client->dev, "subdev %s, pad %d, index %d\n",
subdev->name, code->pad, code->index);
- if (subdev != &sensor->src->sd || code->pad != SMIAPP_PAD_SRC) {
+ if (subdev != &sensor->src->sd || code->pad != CCS_PAD_SRC) {
if (code->index)
goto out;
@@ -1668,12 +1667,12 @@ static int smiapp_enum_mbus_code(struct v4l2_subdev *subdev,
goto out;
}
- for (i = 0; i < ARRAY_SIZE(smiapp_csi_data_formats); i++) {
+ for (i = 0; i < ARRAY_SIZE(ccs_csi_data_formats); i++) {
if (sensor->mbus_frame_fmts & (1 << i))
idx++;
if (idx == code->index) {
- code->code = smiapp_csi_data_formats[i].code;
+ code->code = ccs_csi_data_formats[i].code;
dev_err(&client->dev, "found index %d, i %d, code %x\n",
code->index, i, code->code);
rval = 0;
@@ -1687,22 +1686,21 @@ static int smiapp_enum_mbus_code(struct v4l2_subdev *subdev,
return rval;
}
-static u32 __smiapp_get_mbus_code(struct v4l2_subdev *subdev,
- unsigned int pad)
+static u32 __ccs_get_mbus_code(struct v4l2_subdev *subdev, unsigned int pad)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
- if (subdev == &sensor->src->sd && pad == SMIAPP_PAD_SRC)
+ if (subdev == &sensor->src->sd && pad == CCS_PAD_SRC)
return sensor->csi_format->code;
else
return sensor->internal_csi_format->code;
}
-static int __smiapp_get_format(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_format *fmt)
+static int __ccs_get_format(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *fmt)
{
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
fmt->format = *v4l2_subdev_get_try_format(subdev, cfg,
@@ -1715,7 +1713,7 @@ static int __smiapp_get_format(struct v4l2_subdev *subdev,
else
r = &ssd->sink_fmt;
- fmt->format.code = __smiapp_get_mbus_code(subdev, fmt->pad);
+ fmt->format.code = __ccs_get_mbus_code(subdev, fmt->pad);
fmt->format.width = r->width;
fmt->format.height = r->height;
fmt->format.field = V4L2_FIELD_NONE;
@@ -1724,26 +1722,26 @@ static int __smiapp_get_format(struct v4l2_subdev *subdev,
return 0;
}
-static int smiapp_get_format(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_format *fmt)
+static int ccs_get_format(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *fmt)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
int rval;
mutex_lock(&sensor->mutex);
- rval = __smiapp_get_format(subdev, cfg, fmt);
+ rval = __ccs_get_format(subdev, cfg, fmt);
mutex_unlock(&sensor->mutex);
return rval;
}
-static void smiapp_get_crop_compose(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_rect **crops,
- struct v4l2_rect **comps, int which)
+static void ccs_get_crop_compose(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_rect **crops,
+ struct v4l2_rect **comps, int which)
{
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
unsigned int i;
if (which == V4L2_SUBDEV_FORMAT_ACTIVE) {
@@ -1761,27 +1759,27 @@ static void smiapp_get_crop_compose(struct v4l2_subdev *subdev,
}
if (comps) {
*comps = v4l2_subdev_get_try_compose(subdev, cfg,
- SMIAPP_PAD_SINK);
+ CCS_PAD_SINK);
BUG_ON(!*comps);
}
}
}
/* Changes require propagation only on sink pad. */
-static void smiapp_propagate(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg, int which,
- int target)
+static void ccs_propagate(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg, int which,
+ int target)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
- struct v4l2_rect *comp, *crops[SMIAPP_PADS];
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+ struct v4l2_rect *comp, *crops[CCS_PADS];
- smiapp_get_crop_compose(subdev, cfg, crops, &comp, which);
+ ccs_get_crop_compose(subdev, cfg, crops, &comp, which);
switch (target) {
case V4L2_SEL_TGT_CROP:
- comp->width = crops[SMIAPP_PAD_SINK]->width;
- comp->height = crops[SMIAPP_PAD_SINK]->height;
+ comp->width = crops[CCS_PAD_SINK]->width;
+ comp->height = crops[CCS_PAD_SINK]->height;
if (which == V4L2_SUBDEV_FORMAT_ACTIVE) {
if (ssd == sensor->scaler) {
sensor->scale_m =
@@ -1795,40 +1793,40 @@ static void smiapp_propagate(struct v4l2_subdev *subdev,
}
fallthrough;
case V4L2_SEL_TGT_COMPOSE:
- *crops[SMIAPP_PAD_SRC] = *comp;
+ *crops[CCS_PAD_SRC] = *comp;
break;
default:
BUG();
}
}
-static const struct smiapp_csi_data_format
-*smiapp_validate_csi_data_format(struct smiapp_sensor *sensor, u32 code)
+static const struct ccs_csi_data_format
+*ccs_validate_csi_data_format(struct ccs_sensor *sensor, u32 code)
{
unsigned int i;
- for (i = 0; i < ARRAY_SIZE(smiapp_csi_data_formats); i++) {
- if (sensor->mbus_frame_fmts & (1 << i)
- && smiapp_csi_data_formats[i].code == code)
- return &smiapp_csi_data_formats[i];
+ for (i = 0; i < ARRAY_SIZE(ccs_csi_data_formats); i++) {
+ if (sensor->mbus_frame_fmts & (1 << i) &&
+ ccs_csi_data_formats[i].code == code)
+ return &ccs_csi_data_formats[i];
}
return sensor->csi_format;
}
-static int smiapp_set_format_source(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_format *fmt)
+static int ccs_set_format_source(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *fmt)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- const struct smiapp_csi_data_format *csi_format,
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ const struct ccs_csi_data_format *csi_format,
*old_csi_format = sensor->csi_format;
unsigned long *valid_link_freqs;
u32 code = fmt->format.code;
unsigned int i;
int rval;
- rval = __smiapp_get_format(subdev, cfg, fmt);
+ rval = __ccs_get_format(subdev, cfg, fmt);
if (rval)
return rval;
@@ -1839,7 +1837,7 @@ static int smiapp_set_format_source(struct v4l2_subdev *subdev,
if (subdev != &sensor->src->sd)
return 0;
- csi_format = smiapp_validate_csi_data_format(sensor, code);
+ csi_format = ccs_validate_csi_data_format(sensor, code);
fmt->format.code = csi_format->code;
@@ -1866,23 +1864,23 @@ static int smiapp_set_format_source(struct v4l2_subdev *subdev,
__fls(*valid_link_freqs), ~*valid_link_freqs,
__ffs(*valid_link_freqs));
- return smiapp_pll_update(sensor);
+ return ccs_pll_update(sensor);
}
-static int smiapp_set_format(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_format *fmt)
+static int ccs_set_format(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *fmt)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
- struct v4l2_rect *crops[SMIAPP_PADS];
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+ struct v4l2_rect *crops[CCS_PADS];
mutex_lock(&sensor->mutex);
if (fmt->pad == ssd->source_pad) {
int rval;
- rval = smiapp_set_format_source(subdev, cfg, fmt);
+ rval = ccs_set_format_source(subdev, cfg, fmt);
mutex_unlock(&sensor->mutex);
@@ -1890,7 +1888,7 @@ static int smiapp_set_format(struct v4l2_subdev *subdev,
}
/* Sink pad. Width and height are changeable here. */
- fmt->format.code = __smiapp_get_mbus_code(subdev, fmt->pad);
+ fmt->format.code = __ccs_get_mbus_code(subdev, fmt->pad);
fmt->format.width &= ~1;
fmt->format.height &= ~1;
fmt->format.field = V4L2_FIELD_NONE;
@@ -1904,7 +1902,7 @@ static int smiapp_set_format(struct v4l2_subdev *subdev,
CCS_LIM(sensor, MIN_Y_OUTPUT_SIZE),
CCS_LIM(sensor, MAX_Y_OUTPUT_SIZE));
- smiapp_get_crop_compose(subdev, cfg, crops, NULL, fmt->which);
+ ccs_get_crop_compose(subdev, cfg, crops, NULL, fmt->which);
crops[ssd->sink_pad]->left = 0;
crops[ssd->sink_pad]->top = 0;
@@ -1912,8 +1910,7 @@ static int smiapp_set_format(struct v4l2_subdev *subdev,
crops[ssd->sink_pad]->height = fmt->format.height;
if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE)
ssd->sink_fmt = *crops[ssd->sink_pad];
- smiapp_propagate(subdev, cfg, fmt->which,
- V4L2_SEL_TGT_CROP);
+ ccs_propagate(subdev, cfg, fmt->which, V4L2_SEL_TGT_CROP);
mutex_unlock(&sensor->mutex);
@@ -1929,7 +1926,7 @@ static int smiapp_set_format(struct v4l2_subdev *subdev,
static int scaling_goodness(struct v4l2_subdev *subdev, int w, int ask_w,
int h, int ask_h, u32 flags)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
struct i2c_client *client = v4l2_get_subdevdata(subdev);
int val = 0;
@@ -1964,27 +1961,27 @@ static int scaling_goodness(struct v4l2_subdev *subdev, int w, int ask_w,
return val;
}
-static void smiapp_set_compose_binner(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_selection *sel,
- struct v4l2_rect **crops,
- struct v4l2_rect *comp)
+static void ccs_set_compose_binner(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_selection *sel,
+ struct v4l2_rect **crops,
+ struct v4l2_rect *comp)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
unsigned int i;
unsigned int binh = 1, binv = 1;
int best = scaling_goodness(
subdev,
- crops[SMIAPP_PAD_SINK]->width, sel->r.width,
- crops[SMIAPP_PAD_SINK]->height, sel->r.height, sel->flags);
+ crops[CCS_PAD_SINK]->width, sel->r.width,
+ crops[CCS_PAD_SINK]->height, sel->r.height, sel->flags);
for (i = 0; i < sensor->nbinning_subtypes; i++) {
int this = scaling_goodness(
subdev,
- crops[SMIAPP_PAD_SINK]->width
+ crops[CCS_PAD_SINK]->width
/ sensor->binning_subtypes[i].horizontal,
sel->r.width,
- crops[SMIAPP_PAD_SINK]->height
+ crops[CCS_PAD_SINK]->height
/ sensor->binning_subtypes[i].vertical,
sel->r.height, sel->flags);
@@ -1999,8 +1996,8 @@ static void smiapp_set_compose_binner(struct v4l2_subdev *subdev,
sensor->binning_horizontal = binh;
}
- sel->r.width = (crops[SMIAPP_PAD_SINK]->width / binh) & ~1;
- sel->r.height = (crops[SMIAPP_PAD_SINK]->height / binv) & ~1;
+ sel->r.width = (crops[CCS_PAD_SINK]->width / binh) & ~1;
+ sel->r.height = (crops[CCS_PAD_SINK]->height / binv) & ~1;
}
/*
@@ -2012,14 +2009,14 @@ static void smiapp_set_compose_binner(struct v4l2_subdev *subdev,
* Also try whether horizontal scaler or full scaler gives a better
* result.
*/
-static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_selection *sel,
- struct v4l2_rect **crops,
- struct v4l2_rect *comp)
+static void ccs_set_compose_scaler(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_selection *sel,
+ struct v4l2_rect **crops,
+ struct v4l2_rect *comp)
{
struct i2c_client *client = v4l2_get_subdevdata(subdev);
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
u32 min, max, a, b, max_m;
u32 scale_m = CCS_LIM(sensor, SCALER_N_MIN);
int mode = CCS_SCALING_MODE_HORIZONTAL;
@@ -2029,15 +2026,15 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
int best = INT_MIN;
sel->r.width = min_t(unsigned int, sel->r.width,
- crops[SMIAPP_PAD_SINK]->width);
+ crops[CCS_PAD_SINK]->width);
sel->r.height = min_t(unsigned int, sel->r.height,
- crops[SMIAPP_PAD_SINK]->height);
+ crops[CCS_PAD_SINK]->height);
- a = crops[SMIAPP_PAD_SINK]->width
+ a = crops[CCS_PAD_SINK]->width
* CCS_LIM(sensor, SCALER_N_MIN) / sel->r.width;
- b = crops[SMIAPP_PAD_SINK]->height
+ b = crops[CCS_PAD_SINK]->height
* CCS_LIM(sensor, SCALER_N_MIN) / sel->r.height;
- max_m = crops[SMIAPP_PAD_SINK]->width
+ max_m = crops[CCS_PAD_SINK]->width
* CCS_LIM(sensor, SCALER_N_MIN)
/ CCS_LIM(sensor, MIN_X_OUTPUT_SIZE);
@@ -2071,10 +2068,10 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
for (i = 0; i < ntry; i++) {
int this = scaling_goodness(
subdev,
- crops[SMIAPP_PAD_SINK]->width
+ crops[CCS_PAD_SINK]->width
/ try[i] * CCS_LIM(sensor, SCALER_N_MIN),
sel->r.width,
- crops[SMIAPP_PAD_SINK]->height,
+ crops[CCS_PAD_SINK]->height,
sel->r.height,
sel->flags);
@@ -2091,11 +2088,11 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
continue;
this = scaling_goodness(
- subdev, crops[SMIAPP_PAD_SINK]->width
+ subdev, crops[CCS_PAD_SINK]->width
/ try[i]
* CCS_LIM(sensor, SCALER_N_MIN),
sel->r.width,
- crops[SMIAPP_PAD_SINK]->height
+ crops[CCS_PAD_SINK]->height
/ try[i]
* CCS_LIM(sensor, SCALER_N_MIN),
sel->r.height,
@@ -2109,17 +2106,17 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
}
sel->r.width =
- (crops[SMIAPP_PAD_SINK]->width
+ (crops[CCS_PAD_SINK]->width
/ scale_m
* CCS_LIM(sensor, SCALER_N_MIN)) & ~1;
if (mode == SMIAPP_SCALING_MODE_BOTH)
sel->r.height =
- (crops[SMIAPP_PAD_SINK]->height
+ (crops[CCS_PAD_SINK]->height
/ scale_m
* CCS_LIM(sensor, SCALER_N_MIN))
& ~1;
else
- sel->r.height = crops[SMIAPP_PAD_SINK]->height;
+ sel->r.height = crops[CCS_PAD_SINK]->height;
if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
sensor->scale_m = scale_m;
@@ -2127,57 +2124,54 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
}
}
/* We're only called on source pads. This function sets scaling. */
-static int smiapp_set_compose(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_selection *sel)
+static int ccs_set_compose(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_selection *sel)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
- struct v4l2_rect *comp, *crops[SMIAPP_PADS];
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+ struct v4l2_rect *comp, *crops[CCS_PADS];
- smiapp_get_crop_compose(subdev, cfg, crops, &comp, sel->which);
+ ccs_get_crop_compose(subdev, cfg, crops, &comp, sel->which);
sel->r.top = 0;
sel->r.left = 0;
if (ssd == sensor->binner)
- smiapp_set_compose_binner(subdev, cfg, sel, crops, comp);
+ ccs_set_compose_binner(subdev, cfg, sel, crops, comp);
else
- smiapp_set_compose_scaler(subdev, cfg, sel, crops, comp);
+ ccs_set_compose_scaler(subdev, cfg, sel, crops, comp);
*comp = sel->r;
- smiapp_propagate(subdev, cfg, sel->which, V4L2_SEL_TGT_COMPOSE);
+ ccs_propagate(subdev, cfg, sel->which, V4L2_SEL_TGT_COMPOSE);
if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE)
- return smiapp_pll_blanking_update(sensor);
+ return ccs_pll_blanking_update(sensor);
return 0;
}
-static int __smiapp_sel_supported(struct v4l2_subdev *subdev,
- struct v4l2_subdev_selection *sel)
+static int __ccs_sel_supported(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_selection *sel)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
/* We only implement crop in three places. */
switch (sel->target) {
case V4L2_SEL_TGT_CROP:
case V4L2_SEL_TGT_CROP_BOUNDS:
- if (ssd == sensor->pixel_array
- && sel->pad == SMIAPP_PA_PAD_SRC)
+ if (ssd == sensor->pixel_array && sel->pad == CCS_PA_PAD_SRC)
return 0;
- if (ssd == sensor->src
- && sel->pad == SMIAPP_PAD_SRC)
+ if (ssd == sensor->src && sel->pad == CCS_PAD_SRC)
return 0;
- if (ssd == sensor->scaler && sel->pad == SMIAPP_PAD_SINK &&
+ if (ssd == sensor->scaler && sel->pad == CCS_PAD_SINK &&
CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY)
== CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP)
return 0;
return -EINVAL;
case V4L2_SEL_TGT_NATIVE_SIZE:
- if (ssd == sensor->pixel_array
- && sel->pad == SMIAPP_PA_PAD_SRC)
+ if (ssd == sensor->pixel_array && sel->pad == CCS_PA_PAD_SRC)
return 0;
return -EINVAL;
case V4L2_SEL_TGT_COMPOSE:
@@ -2195,16 +2189,16 @@ static int __smiapp_sel_supported(struct v4l2_subdev *subdev,
}
}
-static int smiapp_set_crop(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_selection *sel)
+static int ccs_set_crop(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_selection *sel)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
- struct v4l2_rect *src_size, *crops[SMIAPP_PADS];
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+ struct v4l2_rect *src_size, *crops[CCS_PADS];
struct v4l2_rect _r;
- smiapp_get_crop_compose(subdev, cfg, crops, NULL, sel->which);
+ ccs_get_crop_compose(subdev, cfg, crops, NULL, sel->which);
if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
if (sel->pad == ssd->sink_pad)
@@ -2226,7 +2220,7 @@ static int smiapp_set_crop(struct v4l2_subdev *subdev,
}
}
- if (ssd == sensor->src && sel->pad == SMIAPP_PAD_SRC) {
+ if (ssd == sensor->src && sel->pad == CCS_PAD_SRC) {
sel->r.left = 0;
sel->r.top = 0;
}
@@ -2239,15 +2233,13 @@ static int smiapp_set_crop(struct v4l2_subdev *subdev,
*crops[sel->pad] = sel->r;
- if (ssd != sensor->pixel_array && sel->pad == SMIAPP_PAD_SINK)
- smiapp_propagate(subdev, cfg, sel->which,
- V4L2_SEL_TGT_CROP);
+ if (ssd != sensor->pixel_array && sel->pad == CCS_PAD_SINK)
+ ccs_propagate(subdev, cfg, sel->which, V4L2_SEL_TGT_CROP);
return 0;
}
-static void smiapp_get_native_size(struct smiapp_subdev *ssd,
- struct v4l2_rect *r)
+static void ccs_get_native_size(struct ccs_subdev *ssd, struct v4l2_rect *r)
{
r->top = 0;
r->left = 0;
@@ -2255,21 +2247,21 @@ static void smiapp_get_native_size(struct smiapp_subdev *ssd,
r->height = CCS_LIM(ssd->sensor, Y_ADDR_MAX) + 1;
}
-static int __smiapp_get_selection(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_selection *sel)
+static int __ccs_get_selection(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_selection *sel)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
- struct v4l2_rect *comp, *crops[SMIAPP_PADS];
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+ struct v4l2_rect *comp, *crops[CCS_PADS];
struct v4l2_rect sink_fmt;
int ret;
- ret = __smiapp_sel_supported(subdev, sel);
+ ret = __ccs_sel_supported(subdev, sel);
if (ret)
return ret;
- smiapp_get_crop_compose(subdev, cfg, crops, &comp, sel->which);
+ ccs_get_crop_compose(subdev, cfg, crops, &comp, sel->which);
if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
sink_fmt = ssd->sink_fmt;
@@ -2287,7 +2279,7 @@ static int __smiapp_get_selection(struct v4l2_subdev *subdev,
case V4L2_SEL_TGT_CROP_BOUNDS:
case V4L2_SEL_TGT_NATIVE_SIZE:
if (ssd == sensor->pixel_array)
- smiapp_get_native_size(ssd, &sel->r);
+ ccs_get_native_size(ssd, &sel->r);
else if (sel->pad == ssd->sink_pad)
sel->r = sink_fmt;
else
@@ -2305,27 +2297,28 @@ static int __smiapp_get_selection(struct v4l2_subdev *subdev,
return 0;
}
-static int smiapp_get_selection(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_selection *sel)
+static int ccs_get_selection(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_selection *sel)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
int rval;
mutex_lock(&sensor->mutex);
- rval = __smiapp_get_selection(subdev, cfg, sel);
+ rval = __ccs_get_selection(subdev, cfg, sel);
mutex_unlock(&sensor->mutex);
return rval;
}
-static int smiapp_set_selection(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_selection *sel)
+
+static int ccs_set_selection(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_selection *sel)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
int ret;
- ret = __smiapp_sel_supported(subdev, sel);
+ ret = __ccs_sel_supported(subdev, sel);
if (ret)
return ret;
@@ -2333,8 +2326,8 @@ static int smiapp_set_selection(struct v4l2_subdev *subdev,
sel->r.left = max(0, sel->r.left & ~1);
sel->r.top = max(0, sel->r.top & ~1);
- sel->r.width = SMIAPP_ALIGN_DIM(sel->r.width, sel->flags);
- sel->r.height = SMIAPP_ALIGN_DIM(sel->r.height, sel->flags);
+ sel->r.width = CCS_ALIGN_DIM(sel->r.width, sel->flags);
+ sel->r.height = CCS_ALIGN_DIM(sel->r.height, sel->flags);
sel->r.width = max_t(unsigned int,
CCS_LIM(sensor, MIN_X_OUTPUT_SIZE),
@@ -2345,10 +2338,10 @@ static int smiapp_set_selection(struct v4l2_subdev *subdev,
switch (sel->target) {
case V4L2_SEL_TGT_CROP:
- ret = smiapp_set_crop(subdev, cfg, sel);
+ ret = ccs_set_crop(subdev, cfg, sel);
break;
case V4L2_SEL_TGT_COMPOSE:
- ret = smiapp_set_compose(subdev, cfg, sel);
+ ret = ccs_set_compose(subdev, cfg, sel);
break;
default:
ret = -EINVAL;
@@ -2358,17 +2351,17 @@ static int smiapp_set_selection(struct v4l2_subdev *subdev,
return ret;
}
-static int smiapp_get_skip_frames(struct v4l2_subdev *subdev, u32 *frames)
+static int ccs_get_skip_frames(struct v4l2_subdev *subdev, u32 *frames)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
*frames = sensor->frame_skip;
return 0;
}
-static int smiapp_get_skip_top_lines(struct v4l2_subdev *subdev, u32 *lines)
+static int ccs_get_skip_top_lines(struct v4l2_subdev *subdev, u32 *lines)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
*lines = sensor->image_start;
@@ -2380,22 +2373,22 @@ static int smiapp_get_skip_top_lines(struct v4l2_subdev *subdev, u32 *lines)
*/
static ssize_t
-smiapp_sysfs_nvm_read(struct device *dev, struct device_attribute *attr,
- char *buf)
+ccs_sysfs_nvm_read(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
struct v4l2_subdev *subdev = i2c_get_clientdata(to_i2c_client(dev));
struct i2c_client *client = v4l2_get_subdevdata(subdev);
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
int rval;
if (!sensor->dev_init_done)
return -EBUSY;
- rval = smiapp_pm_get_init(sensor);
+ rval = ccs_pm_get_init(sensor);
if (rval < 0)
return -ENODEV;
- rval = smiapp_read_nvm(sensor, buf, PAGE_SIZE);
+ rval = ccs_read_nvm(sensor, buf, PAGE_SIZE);
if (rval < 0) {
pm_runtime_put(&client->dev);
dev_err(&client->dev, "nvm read failed\n");
@@ -2411,15 +2404,15 @@ smiapp_sysfs_nvm_read(struct device *dev, struct device_attribute *attr,
*/
return rval;
}
-static DEVICE_ATTR(nvm, S_IRUGO, smiapp_sysfs_nvm_read, NULL);
+static DEVICE_ATTR(nvm, S_IRUGO, ccs_sysfs_nvm_read, NULL);
static ssize_t
-smiapp_sysfs_ident_read(struct device *dev, struct device_attribute *attr,
- char *buf)
+ccs_sysfs_ident_read(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
struct v4l2_subdev *subdev = i2c_get_clientdata(to_i2c_client(dev));
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- struct smiapp_module_info *minfo = &sensor->minfo;
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct ccs_module_info *minfo = &sensor->minfo;
if (minfo->mipi_manufacturer_id)
return snprintf(buf, PAGE_SIZE, "%4.4x%4.4x%2.2x\n",
@@ -2431,16 +2424,16 @@ smiapp_sysfs_ident_read(struct device *dev, struct device_attribute *attr,
minfo->revision_number_major) + 1;
}
-static DEVICE_ATTR(ident, S_IRUGO, smiapp_sysfs_ident_read, NULL);
+static DEVICE_ATTR(ident, S_IRUGO, ccs_sysfs_ident_read, NULL);
/* -----------------------------------------------------------------------------
* V4L2 subdev core operations
*/
-static int smiapp_identify_module(struct smiapp_sensor *sensor)
+static int ccs_identify_module(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- struct smiapp_module_info *minfo = &sensor->minfo;
+ struct ccs_module_info *minfo = &sensor->minfo;
unsigned int i;
int rval = 0;
@@ -2558,34 +2551,34 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor)
minfo->revision_number_major = minfo->sensor_revision_number;
}
- for (i = 0; i < ARRAY_SIZE(smiapp_module_idents); i++) {
- if (smiapp_module_idents[i].mipi_manufacturer_id &&
- smiapp_module_idents[i].mipi_manufacturer_id
+ for (i = 0; i < ARRAY_SIZE(ccs_module_idents); i++) {
+ if (ccs_module_idents[i].mipi_manufacturer_id &&
+ ccs_module_idents[i].mipi_manufacturer_id
!= minfo->mipi_manufacturer_id)
continue;
- if (smiapp_module_idents[i].smia_manufacturer_id &&
- smiapp_module_idents[i].smia_manufacturer_id
+ if (ccs_module_idents[i].smia_manufacturer_id &&
+ ccs_module_idents[i].smia_manufacturer_id
!= minfo->smia_manufacturer_id)
continue;
- if (smiapp_module_idents[i].model_id != minfo->model_id)
+ if (ccs_module_idents[i].model_id != minfo->model_id)
continue;
- if (smiapp_module_idents[i].flags
- & SMIAPP_MODULE_IDENT_FLAG_REV_LE) {
- if (smiapp_module_idents[i].revision_number_major
+ if (ccs_module_idents[i].flags
+ & CCS_MODULE_IDENT_FLAG_REV_LE) {
+ if (ccs_module_idents[i].revision_number_major
< minfo->revision_number_major)
continue;
} else {
- if (smiapp_module_idents[i].revision_number_major
+ if (ccs_module_idents[i].revision_number_major
!= minfo->revision_number_major)
continue;
}
- minfo->name = smiapp_module_idents[i].name;
- minfo->quirk = smiapp_module_idents[i].quirk;
+ minfo->name = ccs_module_idents[i].name;
+ minfo->quirk = ccs_module_idents[i].quirk;
break;
}
- if (i >= ARRAY_SIZE(smiapp_module_idents))
+ if (i >= ARRAY_SIZE(ccs_module_idents))
dev_warn(&client->dev,
"no quirks for this module; let's hope it's fully compliant\n");
@@ -2595,14 +2588,14 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor)
return 0;
}
-static const struct v4l2_subdev_ops smiapp_ops;
-static const struct v4l2_subdev_internal_ops smiapp_internal_ops;
-static const struct media_entity_operations smiapp_entity_ops;
+static const struct v4l2_subdev_ops ccs_ops;
+static const struct v4l2_subdev_internal_ops ccs_internal_ops;
+static const struct media_entity_operations ccs_entity_ops;
-static int smiapp_register_subdev(struct smiapp_sensor *sensor,
- struct smiapp_subdev *ssd,
- struct smiapp_subdev *sink_ssd,
- u16 source_pad, u16 sink_pad, u32 link_flags)
+static int ccs_register_subdev(struct ccs_sensor *sensor,
+ struct ccs_subdev *ssd,
+ struct ccs_subdev *sink_ssd,
+ u16 source_pad, u16 sink_pad, u32 link_flags)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
int rval;
@@ -2639,57 +2632,58 @@ static int smiapp_register_subdev(struct smiapp_sensor *sensor,
return 0;
}
-static void smiapp_unregistered(struct v4l2_subdev *subdev)
+static void ccs_unregistered(struct v4l2_subdev *subdev)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
unsigned int i;
for (i = 1; i < sensor->ssds_used; i++)
v4l2_device_unregister_subdev(&sensor->ssds[i].sd);
}
-static int smiapp_registered(struct v4l2_subdev *subdev)
+static int ccs_registered(struct v4l2_subdev *subdev)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
int rval;
if (sensor->scaler) {
- rval = smiapp_register_subdev(
- sensor, sensor->binner, sensor->scaler,
- SMIAPP_PAD_SRC, SMIAPP_PAD_SINK,
- MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
+ rval = ccs_register_subdev(sensor, sensor->binner,
+ sensor->scaler,
+ CCS_PAD_SRC, CCS_PAD_SINK,
+ MEDIA_LNK_FL_ENABLED |
+ MEDIA_LNK_FL_IMMUTABLE);
if (rval < 0)
return rval;
}
- rval = smiapp_register_subdev(
- sensor, sensor->pixel_array, sensor->binner,
- SMIAPP_PA_PAD_SRC, SMIAPP_PAD_SINK,
- MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
+ rval = ccs_register_subdev(sensor, sensor->pixel_array, sensor->binner,
+ CCS_PA_PAD_SRC, CCS_PAD_SINK,
+ MEDIA_LNK_FL_ENABLED |
+ MEDIA_LNK_FL_IMMUTABLE);
if (rval)
goto out_err;
return 0;
out_err:
- smiapp_unregistered(subdev);
+ ccs_unregistered(subdev);
return rval;
}
-static void smiapp_cleanup(struct smiapp_sensor *sensor)
+static void ccs_cleanup(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
device_remove_file(&client->dev, &dev_attr_nvm);
device_remove_file(&client->dev, &dev_attr_ident);
- smiapp_free_controls(sensor);
+ ccs_free_controls(sensor);
}
-static void smiapp_create_subdev(struct smiapp_sensor *sensor,
- struct smiapp_subdev *ssd, const char *name,
- unsigned short num_pads)
+static void ccs_create_subdev(struct ccs_sensor *sensor,
+ struct ccs_subdev *ssd, const char *name,
+ unsigned short num_pads)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
@@ -2697,7 +2691,7 @@ static void smiapp_create_subdev(struct smiapp_sensor *sensor,
return;
if (ssd != sensor->src)
- v4l2_subdev_init(&ssd->sd, &smiapp_ops);
+ v4l2_subdev_init(&ssd->sd, &ccs_ops);
ssd->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
ssd->sensor = sensor;
@@ -2707,7 +2701,7 @@ static void smiapp_create_subdev(struct smiapp_sensor *sensor,
v4l2_i2c_subdev_set_name(&ssd->sd, client, sensor->minfo.name, name);
- smiapp_get_native_size(ssd, &ssd->sink_fmt);
+ ccs_get_native_size(ssd, &ssd->sink_fmt);
ssd->compose.width = ssd->sink_fmt.width;
ssd->compose.height = ssd->sink_fmt.height;
@@ -2718,21 +2712,21 @@ static void smiapp_create_subdev(struct smiapp_sensor *sensor,
ssd->pads[ssd->sink_pad].flags = MEDIA_PAD_FL_SINK;
}
- ssd->sd.entity.ops = &smiapp_entity_ops;
+ ssd->sd.entity.ops = &ccs_entity_ops;
if (ssd == sensor->src)
return;
- ssd->sd.internal_ops = &smiapp_internal_ops;
+ ssd->sd.internal_ops = &ccs_internal_ops;
ssd->sd.owner = THIS_MODULE;
ssd->sd.dev = &client->dev;
v4l2_set_subdevdata(&ssd->sd, client);
}
-static int smiapp_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
+static int ccs_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
{
- struct smiapp_subdev *ssd = to_smiapp_subdev(sd);
- struct smiapp_sensor *sensor = ssd->sensor;
+ struct ccs_subdev *ssd = to_ccs_subdev(sd);
+ struct ccs_sensor *sensor = ssd->sensor;
unsigned int i;
mutex_lock(&sensor->mutex);
@@ -2744,7 +2738,7 @@ static int smiapp_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
v4l2_subdev_get_try_crop(sd, fh->pad, i);
struct v4l2_rect *try_comp;
- smiapp_get_native_size(ssd, try_crop);
+ ccs_get_native_size(ssd, try_crop);
try_fmt->width = try_crop->width;
try_fmt->height = try_crop->height;
@@ -2763,52 +2757,52 @@ static int smiapp_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
return 0;
}
-static const struct v4l2_subdev_video_ops smiapp_video_ops = {
- .s_stream = smiapp_set_stream,
+static const struct v4l2_subdev_video_ops ccs_video_ops = {
+ .s_stream = ccs_set_stream,
};
-static const struct v4l2_subdev_pad_ops smiapp_pad_ops = {
- .enum_mbus_code = smiapp_enum_mbus_code,
- .get_fmt = smiapp_get_format,
- .set_fmt = smiapp_set_format,
- .get_selection = smiapp_get_selection,
- .set_selection = smiapp_set_selection,
+static const struct v4l2_subdev_pad_ops ccs_pad_ops = {
+ .enum_mbus_code = ccs_enum_mbus_code,
+ .get_fmt = ccs_get_format,
+ .set_fmt = ccs_set_format,
+ .get_selection = ccs_get_selection,
+ .set_selection = ccs_set_selection,
};
-static const struct v4l2_subdev_sensor_ops smiapp_sensor_ops = {
- .g_skip_frames = smiapp_get_skip_frames,
- .g_skip_top_lines = smiapp_get_skip_top_lines,
+static const struct v4l2_subdev_sensor_ops ccs_sensor_ops = {
+ .g_skip_frames = ccs_get_skip_frames,
+ .g_skip_top_lines = ccs_get_skip_top_lines,
};
-static const struct v4l2_subdev_ops smiapp_ops = {
- .video = &smiapp_video_ops,
- .pad = &smiapp_pad_ops,
- .sensor = &smiapp_sensor_ops,
+static const struct v4l2_subdev_ops ccs_ops = {
+ .video = &ccs_video_ops,
+ .pad = &ccs_pad_ops,
+ .sensor = &ccs_sensor_ops,
};
-static const struct media_entity_operations smiapp_entity_ops = {
+static const struct media_entity_operations ccs_entity_ops = {
.link_validate = v4l2_subdev_link_validate,
};
-static const struct v4l2_subdev_internal_ops smiapp_internal_src_ops = {
- .registered = smiapp_registered,
- .unregistered = smiapp_unregistered,
- .open = smiapp_open,
+static const struct v4l2_subdev_internal_ops ccs_internal_src_ops = {
+ .registered = ccs_registered,
+ .unregistered = ccs_unregistered,
+ .open = ccs_open,
};
-static const struct v4l2_subdev_internal_ops smiapp_internal_ops = {
- .open = smiapp_open,
+static const struct v4l2_subdev_internal_ops ccs_internal_ops = {
+ .open = ccs_open,
};
/* -----------------------------------------------------------------------------
* I2C Driver
*/
-static int __maybe_unused smiapp_suspend(struct device *dev)
+static int __maybe_unused ccs_suspend(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct v4l2_subdev *subdev = i2c_get_clientdata(client);
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
bool streaming = sensor->streaming;
int rval;
@@ -2821,7 +2815,7 @@ static int __maybe_unused smiapp_suspend(struct device *dev)
}
if (sensor->streaming)
- smiapp_stop_streaming(sensor);
+ ccs_stop_streaming(sensor);
/* save state for resume */
sensor->streaming = streaming;
@@ -2829,24 +2823,24 @@ static int __maybe_unused smiapp_suspend(struct device *dev)
return 0;
}
-static int __maybe_unused smiapp_resume(struct device *dev)
+static int __maybe_unused ccs_resume(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct v4l2_subdev *subdev = i2c_get_clientdata(client);
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
int rval = 0;
pm_runtime_put(dev);
if (sensor->streaming)
- rval = smiapp_start_streaming(sensor);
+ rval = ccs_start_streaming(sensor);
return rval;
}
-static struct smiapp_hwconfig *smiapp_get_hwconfig(struct device *dev)
+static struct ccs_hwconfig *ccs_get_hwconfig(struct device *dev)
{
- struct smiapp_hwconfig *hwcfg;
+ struct ccs_hwconfig *hwcfg;
struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };
struct fwnode_handle *ep;
struct fwnode_handle *fwnode = dev_fwnode(dev);
@@ -2898,7 +2892,7 @@ static struct smiapp_hwconfig *smiapp_get_hwconfig(struct device *dev)
switch (rotation) {
case 180:
hwcfg->module_board_orient =
- SMIAPP_MODULE_BOARD_ORIENT_180;
+ CCS_MODULE_BOARD_ORIENT_180;
fallthrough;
case 0:
break;
@@ -2942,10 +2936,10 @@ static struct smiapp_hwconfig *smiapp_get_hwconfig(struct device *dev)
return NULL;
}
-static int smiapp_probe(struct i2c_client *client)
+static int ccs_probe(struct i2c_client *client)
{
- struct smiapp_sensor *sensor;
- struct smiapp_hwconfig *hwcfg = smiapp_get_hwconfig(&client->dev);
+ struct ccs_sensor *sensor;
+ struct ccs_hwconfig *hwcfg = ccs_get_hwconfig(&client->dev);
unsigned int i;
int rval;
@@ -2959,8 +2953,8 @@ static int smiapp_probe(struct i2c_client *client)
sensor->hwcfg = hwcfg;
sensor->src = &sensor->ssds[sensor->ssds_used];
- v4l2_i2c_subdev_init(&sensor->src->sd, client, &smiapp_ops);
- sensor->src->sd.internal_ops = &smiapp_internal_src_ops;
+ v4l2_i2c_subdev_init(&sensor->src->sd, client, &ccs_ops);
+ sensor->src->sd.internal_ops = &ccs_internal_src_ops;
sensor->vana = devm_regulator_get(&client->dev, "vana");
if (IS_ERR(sensor->vana)) {
@@ -3016,13 +3010,13 @@ static int smiapp_probe(struct i2c_client *client)
if (IS_ERR(sensor->xshutdown))
return PTR_ERR(sensor->xshutdown);
- rval = smiapp_power_on(&client->dev);
+ rval = ccs_power_on(&client->dev);
if (rval < 0)
return rval;
mutex_init(&sensor->mutex);
- rval = smiapp_identify_module(sensor);
+ rval = ccs_identify_module(sensor);
if (rval) {
rval = -ENODEV;
goto out_power_off;
@@ -3032,7 +3026,7 @@ static int smiapp_probe(struct i2c_client *client)
if (rval)
goto out_power_off;
- rval = smiapp_read_frame_fmt(sensor);
+ rval = ccs_read_frame_fmt(sensor);
if (rval) {
rval = -ENODEV;
goto out_free_ccs_limits;
@@ -3044,7 +3038,7 @@ static int smiapp_probe(struct i2c_client *client)
* The application of H-FLIP and V-FLIP on the sensor is modified by
* the sensor orientation on the board.
*
- * For SMIAPP_BOARD_SENSOR_ORIENT_180 the default behaviour is to set
+ * For CCS_BOARD_SENSOR_ORIENT_180 the default behaviour is to set
* both H-FLIP and V-FLIP for normal operation which also implies
* that a set/unset operation for user space HFLIP and VFLIP v4l2
* controls will need to be internally inverted.
@@ -3052,12 +3046,12 @@ static int smiapp_probe(struct i2c_client *client)
* Rotation also changes the bayer pattern.
*/
if (sensor->hwcfg->module_board_orient ==
- SMIAPP_MODULE_BOARD_ORIENT_180)
+ CCS_MODULE_BOARD_ORIENT_180)
sensor->hvflip_inv_mask =
CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR |
CCS_IMAGE_ORIENTATION_VERTICAL_FLIP;
- rval = smiapp_call_quirk(sensor, limits);
+ rval = ccs_call_quirk(sensor, limits);
if (rval) {
dev_err(&client->dev, "limits quirks failed\n");
goto out_free_ccs_limits;
@@ -3136,36 +3130,36 @@ static int smiapp_probe(struct i2c_client *client)
if (sensor->minfo.smiapp_profile == SMIAPP_PROFILE_0)
sensor->pll.flags |= SMIAPP_PLL_FLAG_NO_OP_CLOCKS;
- smiapp_create_subdev(sensor, sensor->scaler, " scaler", 2);
- smiapp_create_subdev(sensor, sensor->binner, " binner", 2);
- smiapp_create_subdev(sensor, sensor->pixel_array, " pixel_array", 1);
+ ccs_create_subdev(sensor, sensor->scaler, " scaler", 2);
+ ccs_create_subdev(sensor, sensor->binner, " binner", 2);
+ ccs_create_subdev(sensor, sensor->pixel_array, " pixel_array", 1);
dev_dbg(&client->dev, "profile %d\n", sensor->minfo.smiapp_profile);
sensor->pixel_array->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
- rval = smiapp_init_controls(sensor);
+ rval = ccs_init_controls(sensor);
if (rval < 0)
goto out_cleanup;
- rval = smiapp_call_quirk(sensor, init);
+ rval = ccs_call_quirk(sensor, init);
if (rval)
goto out_cleanup;
- rval = smiapp_get_mbus_formats(sensor);
+ rval = ccs_get_mbus_formats(sensor);
if (rval) {
rval = -ENODEV;
goto out_cleanup;
}
- rval = smiapp_init_late_controls(sensor);
+ rval = ccs_init_late_controls(sensor);
if (rval) {
rval = -ENODEV;
goto out_cleanup;
}
mutex_lock(&sensor->mutex);
- rval = smiapp_pll_blanking_update(sensor);
+ rval = ccs_pll_blanking_update(sensor);
mutex_unlock(&sensor->mutex);
if (rval) {
dev_err(&client->dev, "update mode failed\n");
@@ -3202,71 +3196,71 @@ static int smiapp_probe(struct i2c_client *client)
media_entity_cleanup(&sensor->src->sd.entity);
out_cleanup:
- smiapp_cleanup(sensor);
+ ccs_cleanup(sensor);
out_free_ccs_limits:
kfree(sensor->ccs_limits);
out_power_off:
- smiapp_power_off(&client->dev);
+ ccs_power_off(&client->dev);
mutex_destroy(&sensor->mutex);
return rval;
}
-static int smiapp_remove(struct i2c_client *client)
+static int ccs_remove(struct i2c_client *client)
{
struct v4l2_subdev *subdev = i2c_get_clientdata(client);
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
unsigned int i;
v4l2_async_unregister_subdev(subdev);
pm_runtime_disable(&client->dev);
if (!pm_runtime_status_suspended(&client->dev))
- smiapp_power_off(&client->dev);
+ ccs_power_off(&client->dev);
pm_runtime_set_suspended(&client->dev);
for (i = 0; i < sensor->ssds_used; i++) {
v4l2_device_unregister_subdev(&sensor->ssds[i].sd);
media_entity_cleanup(&sensor->ssds[i].sd.entity);
}
- smiapp_cleanup(sensor);
+ ccs_cleanup(sensor);
mutex_destroy(&sensor->mutex);
kfree(sensor->ccs_limits);
return 0;
}
-static const struct of_device_id smiapp_of_table[] = {
+static const struct of_device_id ccs_of_table[] = {
{ .compatible = "nokia,smia" },
{ },
};
-MODULE_DEVICE_TABLE(of, smiapp_of_table);
+MODULE_DEVICE_TABLE(of, ccs_of_table);
-static const struct i2c_device_id smiapp_id_table[] = {
+static const struct i2c_device_id ccs_id_table[] = {
{ SMIAPP_NAME, 0 },
{ },
};
-MODULE_DEVICE_TABLE(i2c, smiapp_id_table);
+MODULE_DEVICE_TABLE(i2c, ccs_id_table);
-static const struct dev_pm_ops smiapp_pm_ops = {
- SET_SYSTEM_SLEEP_PM_OPS(smiapp_suspend, smiapp_resume)
- SET_RUNTIME_PM_OPS(smiapp_power_off, smiapp_power_on, NULL)
+static const struct dev_pm_ops ccs_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(ccs_suspend, ccs_resume)
+ SET_RUNTIME_PM_OPS(ccs_power_off, ccs_power_on, NULL)
};
-static struct i2c_driver smiapp_i2c_driver = {
+static struct i2c_driver ccs_i2c_driver = {
.driver = {
- .of_match_table = smiapp_of_table,
- .name = SMIAPP_NAME,
- .pm = &smiapp_pm_ops,
+ .of_match_table = ccs_of_table,
+ .name = CCS_NAME,
+ .pm = &ccs_pm_ops,
},
- .probe_new = smiapp_probe,
- .remove = smiapp_remove,
- .id_table = smiapp_id_table,
+ .probe_new = ccs_probe,
+ .remove = ccs_remove,
+ .id_table = ccs_id_table,
};
-static int smiapp_module_init(void)
+static int ccs_module_init(void)
{
unsigned int i, l;
@@ -3289,17 +3283,17 @@ static int smiapp_module_init(void)
if (WARN_ON(l != CCS_L_LAST))
return -EINVAL;
- return i2c_register_driver(THIS_MODULE, &smiapp_i2c_driver);
+ return i2c_register_driver(THIS_MODULE, &ccs_i2c_driver);
}
-static void smiapp_module_cleanup(void)
+static void ccs_module_cleanup(void)
{
- i2c_del_driver(&smiapp_i2c_driver);
+ i2c_del_driver(&ccs_i2c_driver);
}
-module_init(smiapp_module_init);
-module_exit(smiapp_module_cleanup);
+module_init(ccs_module_init);
+module_exit(ccs_module_cleanup);
MODULE_AUTHOR("Sakari Ailus <sakari.ailus@iki.fi>");
-MODULE_DESCRIPTION("Generic SMIA/SMIA++ camera module driver");
+MODULE_DESCRIPTION("Generic MIPI CCS/SMIA/SMIA++ camera sensor driver");
MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/i2c/smiapp/smiapp-quirk.c b/drivers/media/i2c/smiapp/ccs-quirk.c
similarity index 83%
rename from drivers/media/i2c/smiapp/smiapp-quirk.c
rename to drivers/media/i2c/smiapp/ccs-quirk.c
index 5db97a16eccf..6c48d0901952 100644
--- a/drivers/media/i2c/smiapp/smiapp-quirk.c
+++ b/drivers/media/i2c/smiapp/ccs-quirk.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * drivers/media/i2c/smiapp/smiapp-quirk.c
+ * drivers/media/i2c/smiapp/ccs-quirk.c
*
* Generic driver for SMIA/SMIA++ compliant camera modules
*
@@ -10,12 +10,11 @@
#include <linux/delay.h>
+#include "ccs.h"
#include "ccs-limits.h"
-#include "smiapp.h"
-
-static int ccs_write_addr_8s(struct smiapp_sensor *sensor,
- const struct smiapp_reg_8 *regs, int len)
+static int ccs_write_addr_8s(struct ccs_sensor *sensor,
+ const struct ccs_reg_8 *regs, int len)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
int rval;
@@ -33,7 +32,7 @@ static int ccs_write_addr_8s(struct smiapp_sensor *sensor,
return 0;
}
-static int jt8ew9_limits(struct smiapp_sensor *sensor)
+static int jt8ew9_limits(struct ccs_sensor *sensor)
{
if (sensor->minfo.revision_number_major < 0x03)
sensor->frame_skip = 1;
@@ -46,9 +45,9 @@ static int jt8ew9_limits(struct smiapp_sensor *sensor)
return 0;
}
-static int jt8ew9_post_poweron(struct smiapp_sensor *sensor)
+static int jt8ew9_post_poweron(struct ccs_sensor *sensor)
{
- static const struct smiapp_reg_8 regs[] = {
+ static const struct ccs_reg_8 regs[] = {
{ 0x30a3, 0xd8 }, /* Output port control : LVDS ports only */
{ 0x30ae, 0x00 }, /* 0x0307 pll_multiplier maximum value on PLL input 9.6MHz ( 19.2MHz is divided on pre_pll_div) */
{ 0x30af, 0xd0 }, /* 0x0307 pll_multiplier maximum value on PLL input 9.6MHz ( 19.2MHz is divided on pre_pll_div) */
@@ -84,15 +83,15 @@ static int jt8ew9_post_poweron(struct smiapp_sensor *sensor)
return ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs));
}
-const struct smiapp_quirk smiapp_jt8ew9_quirk = {
+const struct ccs_quirk smiapp_jt8ew9_quirk = {
.limits = jt8ew9_limits,
.post_poweron = jt8ew9_post_poweron,
};
-static int imx125es_post_poweron(struct smiapp_sensor *sensor)
+static int imx125es_post_poweron(struct ccs_sensor *sensor)
{
/* Taken from v02. No idea what the other two are. */
- static const struct smiapp_reg_8 regs[] = {
+ static const struct ccs_reg_8 regs[] = {
/*
* 0x3302: clk during frame blanking:
* 0x00 - HS mode, 0x01 - LP11
@@ -105,11 +104,11 @@ static int imx125es_post_poweron(struct smiapp_sensor *sensor)
return ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs));
}
-const struct smiapp_quirk smiapp_imx125es_quirk = {
+const struct ccs_quirk smiapp_imx125es_quirk = {
.post_poweron = imx125es_post_poweron,
};
-static int jt8ev1_limits(struct smiapp_sensor *sensor)
+static int jt8ev1_limits(struct ccs_sensor *sensor)
{
ccs_replace_limit(sensor, CCS_L_X_ADDR_MAX, 0, 4271);
ccs_replace_limit(sensor, CCS_L_MIN_LINE_BLANKING_PCK_BIN, 0, 184);
@@ -117,11 +116,11 @@ static int jt8ev1_limits(struct smiapp_sensor *sensor)
return 0;
}
-static int jt8ev1_post_poweron(struct smiapp_sensor *sensor)
+static int jt8ev1_post_poweron(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
int rval;
- static const struct smiapp_reg_8 regs[] = {
+ static const struct ccs_reg_8 regs[] = {
{ 0x3031, 0xcd }, /* For digital binning (EQ_MONI) */
{ 0x30a3, 0xd0 }, /* FLASH STROBE enable */
{ 0x3237, 0x00 }, /* For control of pulse timing for ADC */
@@ -142,7 +141,7 @@ static int jt8ev1_post_poweron(struct smiapp_sensor *sensor)
{ 0x33cf, 0xec }, /* For Black sun */
{ 0x3328, 0x80 }, /* Ugh. No idea what's this. */
};
- static const struct smiapp_reg_8 regs_96[] = {
+ static const struct ccs_reg_8 regs_96[] = {
{ 0x30ae, 0x00 }, /* For control of ADC clock */
{ 0x30af, 0xd0 },
{ 0x30b0, 0x01 },
@@ -163,12 +162,12 @@ static int jt8ev1_post_poweron(struct smiapp_sensor *sensor)
}
}
-static int jt8ev1_pre_streamon(struct smiapp_sensor *sensor)
+static int jt8ev1_pre_streamon(struct ccs_sensor *sensor)
{
return ccs_write_addr(sensor, 0x3328, 0x00);
}
-static int jt8ev1_post_streamoff(struct smiapp_sensor *sensor)
+static int jt8ev1_post_streamoff(struct ccs_sensor *sensor)
{
int rval;
@@ -188,14 +187,14 @@ static int jt8ev1_post_streamoff(struct smiapp_sensor *sensor)
return ccs_write_addr(sensor, 0x3328, 0x80);
}
-static int jt8ev1_init(struct smiapp_sensor *sensor)
+static int jt8ev1_init(struct ccs_sensor *sensor)
{
sensor->pll.flags |= SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE;
return 0;
}
-const struct smiapp_quirk smiapp_jt8ev1_quirk = {
+const struct ccs_quirk smiapp_jt8ev1_quirk = {
.limits = jt8ev1_limits,
.post_poweron = jt8ev1_post_poweron,
.pre_streamon = jt8ev1_pre_streamon,
@@ -203,13 +202,13 @@ const struct smiapp_quirk smiapp_jt8ev1_quirk = {
.init = jt8ev1_init,
};
-static int tcm8500md_limits(struct smiapp_sensor *sensor)
+static int tcm8500md_limits(struct ccs_sensor *sensor)
{
ccs_replace_limit(sensor, CCS_L_MIN_PLL_IP_CLK_FREQ_MHZ, 0, 2700000);
return 0;
}
-const struct smiapp_quirk smiapp_tcm8500md_quirk = {
+const struct ccs_quirk smiapp_tcm8500md_quirk = {
.limits = tcm8500md_limits,
};
diff --git a/drivers/media/i2c/smiapp/smiapp-quirk.h b/drivers/media/i2c/smiapp/ccs-quirk.h
similarity index 59%
rename from drivers/media/i2c/smiapp/smiapp-quirk.h
rename to drivers/media/i2c/smiapp/ccs-quirk.h
index 8a479f17cd19..d208379158f2 100644
--- a/drivers/media/i2c/smiapp/smiapp-quirk.h
+++ b/drivers/media/i2c/smiapp/ccs-quirk.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * drivers/media/i2c/smiapp/smiapp-quirk.h
+ * drivers/media/i2c/smiapp/ccs-quirk.h
*
* Generic driver for SMIA/SMIA++ compliant camera modules
*
@@ -8,13 +8,13 @@
* Contact: Sakari Ailus <sakari.ailus@iki.fi>
*/
-#ifndef __SMIAPP_QUIRK__
-#define __SMIAPP_QUIRK__
+#ifndef __CCS_QUIRK__
+#define __CCS_QUIRK__
-struct smiapp_sensor;
+struct ccs_sensor;
/**
- * struct smiapp_quirk - quirks for sensors that deviate from SMIA++ standard
+ * struct ccs_quirk - quirks for sensors that deviate from SMIA++ standard
*
* @limits: Replace sensor->limits with values which can't be read from
* sensor registers. Called the first time the sensor is powered up.
@@ -36,43 +36,43 @@ struct smiapp_sensor;
* access may be done by the caller (default read
* value is zero), else negative error code on error
*/
-struct smiapp_quirk {
- int (*limits)(struct smiapp_sensor *sensor);
- int (*post_poweron)(struct smiapp_sensor *sensor);
- int (*pre_streamon)(struct smiapp_sensor *sensor);
- int (*post_streamoff)(struct smiapp_sensor *sensor);
- unsigned long (*pll_flags)(struct smiapp_sensor *sensor);
- int (*init)(struct smiapp_sensor *sensor);
- int (*reg_access)(struct smiapp_sensor *sensor, bool write, u32 *reg,
+struct ccs_quirk {
+ int (*limits)(struct ccs_sensor *sensor);
+ int (*post_poweron)(struct ccs_sensor *sensor);
+ int (*pre_streamon)(struct ccs_sensor *sensor);
+ int (*post_streamoff)(struct ccs_sensor *sensor);
+ unsigned long (*pll_flags)(struct ccs_sensor *sensor);
+ int (*init)(struct ccs_sensor *sensor);
+ int (*reg_access)(struct ccs_sensor *sensor, bool write, u32 *reg,
u32 *val);
unsigned long flags;
};
-#define SMIAPP_QUIRK_FLAG_8BIT_READ_ONLY (1 << 0)
+#define CCS_QUIRK_FLAG_8BIT_READ_ONLY (1 << 0)
-struct smiapp_reg_8 {
+struct ccs_reg_8 {
u16 reg;
u8 val;
};
-#define SMIAPP_MK_QUIRK_REG_8(_reg, _val) \
+#define CCS_MK_QUIRK_REG_8(_reg, _val) \
{ \
.reg = (u16)_reg, \
.val = _val, \
}
-#define smiapp_call_quirk(sensor, _quirk, ...) \
+#define ccs_call_quirk(sensor, _quirk, ...) \
((sensor)->minfo.quirk && \
(sensor)->minfo.quirk->_quirk ? \
(sensor)->minfo.quirk->_quirk(sensor, ##__VA_ARGS__) : 0)
-#define smiapp_needs_quirk(sensor, _quirk) \
+#define ccs_needs_quirk(sensor, _quirk) \
((sensor)->minfo.quirk ? \
(sensor)->minfo.quirk->flags & _quirk : 0)
-extern const struct smiapp_quirk smiapp_jt8ev1_quirk;
-extern const struct smiapp_quirk smiapp_imx125es_quirk;
-extern const struct smiapp_quirk smiapp_jt8ew9_quirk;
-extern const struct smiapp_quirk smiapp_tcm8500md_quirk;
+extern const struct ccs_quirk smiapp_jt8ev1_quirk;
+extern const struct ccs_quirk smiapp_imx125es_quirk;
+extern const struct ccs_quirk smiapp_jt8ew9_quirk;
+extern const struct ccs_quirk smiapp_tcm8500md_quirk;
-#endif /* __SMIAPP_QUIRK__ */
+#endif /* __CCS_QUIRK__ */
diff --git a/drivers/media/i2c/smiapp/smiapp-regs.c b/drivers/media/i2c/smiapp/ccs-reg-access.c
similarity index 79%
rename from drivers/media/i2c/smiapp/smiapp-regs.c
rename to drivers/media/i2c/smiapp/ccs-reg-access.c
index 173d9f8fe56c..4e6d212473fc 100644
--- a/drivers/media/i2c/smiapp/smiapp-regs.c
+++ b/drivers/media/i2c/smiapp/ccs-reg-access.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * drivers/media/i2c/smiapp/smiapp-regs.c
+ * drivers/media/i2c/smiapp/ccs-regs.c
*
* Generic driver for SMIA/SMIA++ compliant camera modules
*
@@ -13,8 +13,7 @@
#include <linux/delay.h>
#include <linux/i2c.h>
-#include "smiapp.h"
-#include "smiapp-regs.h"
+#include "ccs.h"
static uint32_t float_to_u32_mul_1000000(struct i2c_client *client,
uint32_t phloat)
@@ -66,7 +65,7 @@ static uint32_t float_to_u32_mul_1000000(struct i2c_client *client,
* Read a 8/16/32-bit i2c register. The value is returned in 'val'.
* Returns zero if successful, or non-zero otherwise.
*/
-static int ____ccs_read_addr(struct smiapp_sensor *sensor, u16 reg, u16 len,
+static int ____ccs_read_addr(struct ccs_sensor *sensor, u16 reg, u16 len,
u32 *val)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
@@ -113,7 +112,7 @@ static int ____ccs_read_addr(struct smiapp_sensor *sensor, u16 reg, u16 len,
}
/* Read a register using 8-bit access only. */
-static int ____ccs_read_addr_8only(struct smiapp_sensor *sensor, u16 reg,
+static int ____ccs_read_addr_8only(struct ccs_sensor *sensor, u16 reg,
u16 len, u32 *val)
{
unsigned int i;
@@ -147,7 +146,7 @@ unsigned int ccs_reg_width(u32 reg)
* Read a 8/16/32-bit i2c register. The value is returned in 'val'.
* Returns zero if successful, or non-zero otherwise.
*/
-static int __ccs_read_addr(struct smiapp_sensor *sensor, u32 reg, u32 *val,
+static int __ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val,
bool only8)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
@@ -155,11 +154,10 @@ static int __ccs_read_addr(struct smiapp_sensor *sensor, u32 reg, u32 *val,
int rval;
if (!only8)
- rval = ____ccs_read_addr(sensor, SMIAPP_REG_ADDR(reg), len,
- val);
+ rval = ____ccs_read_addr(sensor, CCS_REG_ADDR(reg), len, val);
else
- rval = ____ccs_read_addr_8only(sensor, SMIAPP_REG_ADDR(reg),
- len, val);
+ rval = ____ccs_read_addr_8only(sensor, CCS_REG_ADDR(reg), len,
+ val);
if (rval < 0)
return rval;
@@ -169,21 +167,20 @@ static int __ccs_read_addr(struct smiapp_sensor *sensor, u32 reg, u32 *val,
return 0;
}
-int ccs_read_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val)
+int ccs_read_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 *val)
{
return __ccs_read_addr(
sensor, reg, val,
- smiapp_needs_quirk(sensor,
- SMIAPP_QUIRK_FLAG_8BIT_READ_ONLY));
+ ccs_needs_quirk(sensor, CCS_QUIRK_FLAG_8BIT_READ_ONLY));
}
-static int ccs_read_addr_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val,
+static int ccs_read_addr_quirk(struct ccs_sensor *sensor, u32 reg, u32 *val,
bool force8)
{
int rval;
*val = 0;
- rval = smiapp_call_quirk(sensor, reg_access, false, ®, val);
+ rval = ccs_call_quirk(sensor, reg_access, false, ®, val);
if (rval == -ENOIOCTLCMD)
return 0;
if (rval < 0)
@@ -195,17 +192,17 @@ static int ccs_read_addr_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val,
return ccs_read_addr_no_quirk(sensor, reg, val);
}
-int ccs_read_addr(struct smiapp_sensor *sensor, u32 reg, u32 *val)
+int ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val)
{
return ccs_read_addr_quirk(sensor, reg, val, false);
}
-int ccs_read_addr_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val)
+int ccs_read_addr_8only(struct ccs_sensor *sensor, u32 reg, u32 *val)
{
return ccs_read_addr_quirk(sensor, reg, val, true);
}
-int ccs_write_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val)
+int ccs_write_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 val)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
struct i2c_msg msg;
@@ -222,7 +219,7 @@ int ccs_write_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val)
msg.len = 2 + len;
msg.buf = data;
- put_unaligned_be16(SMIAPP_REG_ADDR(reg), data);
+ put_unaligned_be16(CCS_REG_ADDR(reg), data);
put_unaligned_be32(val << (8 * (sizeof(val) - len)), data + 2);
for (retries = 0; retries < 5; retries++) {
@@ -245,7 +242,7 @@ int ccs_write_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val)
dev_err(&client->dev,
"wrote 0x%x to offset 0x%x error %d\n", val,
- SMIAPP_REG_ADDR(reg), r);
+ CCS_REG_ADDR(reg), r);
return r;
}
@@ -254,11 +251,11 @@ int ccs_write_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val)
* Write to a 8/16-bit register.
* Returns zero if successful, or non-zero otherwise.
*/
-int ccs_write_addr(struct smiapp_sensor *sensor, u32 reg, u32 val)
+int ccs_write_addr(struct ccs_sensor *sensor, u32 reg, u32 val)
{
int rval;
- rval = smiapp_call_quirk(sensor, reg_access, true, ®, &val);
+ rval = ccs_call_quirk(sensor, reg_access, true, ®, &val);
if (rval == -ENOIOCTLCMD)
return 0;
if (rval < 0)
diff --git a/drivers/media/i2c/smiapp/smiapp-regs.h b/drivers/media/i2c/smiapp/ccs-reg-access.h
similarity index 55%
rename from drivers/media/i2c/smiapp/smiapp-regs.h
rename to drivers/media/i2c/smiapp/ccs-reg-access.h
index 5df794f65dfc..76ac036a9538 100644
--- a/drivers/media/i2c/smiapp/smiapp-regs.h
+++ b/drivers/media/i2c/smiapp/ccs-reg-access.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * include/media/smiapp/smiapp-regs.h
+ * include/media/smiapp/ccs-regs.h
*
* Generic driver for SMIA/SMIA++ compliant camera modules
*
@@ -16,15 +16,15 @@
#include "ccs-regs.h"
-#define SMIAPP_REG_ADDR(reg) ((u16)reg)
+#define CCS_REG_ADDR(reg) ((u16)reg)
-struct smiapp_sensor;
+struct ccs_sensor;
-int ccs_read_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val);
-int ccs_read_addr(struct smiapp_sensor *sensor, u32 reg, u32 *val);
-int ccs_read_addr_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val);
-int ccs_write_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val);
-int ccs_write_addr(struct smiapp_sensor *sensor, u32 reg, u32 val);
+int ccs_read_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 *val);
+int ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val);
+int ccs_read_addr_8only(struct ccs_sensor *sensor, u32 reg, u32 *val);
+int ccs_write_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 val);
+int ccs_write_addr(struct ccs_sensor *sensor, u32 reg, u32 val);
unsigned int ccs_reg_width(u32 reg);
diff --git a/drivers/media/i2c/smiapp/smiapp.h b/drivers/media/i2c/smiapp/ccs.h
similarity index 65%
rename from drivers/media/i2c/smiapp/smiapp.h
rename to drivers/media/i2c/smiapp/ccs.h
index c6e4e05a7522..20b1125d87dc 100644
--- a/drivers/media/i2c/smiapp/smiapp.h
+++ b/drivers/media/i2c/smiapp/ccs.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * drivers/media/i2c/smiapp/smiapp.h
+ * drivers/media/i2c/smiapp/ccs.h
*
* Generic driver for SMIA/SMIA++ compliant camera modules
*
@@ -8,19 +8,18 @@
* Contact: Sakari Ailus <sakari.ailus@iki.fi>
*/
-#ifndef __SMIAPP_PRIV_H_
-#define __SMIAPP_PRIV_H_
+#ifndef __CCS_H__
+#define __CCS_H__
#include <linux/mutex.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-subdev.h>
+#include "ccs-quirk.h"
#include "ccs-regs.h"
-
-#include "smiapp-pll.h"
+#include "ccs-reg-access.h"
+#include "../smiapp-pll.h"
#include "smiapp-reg-defs.h"
-#include "smiapp-regs.h"
-#include "smiapp-quirk.h"
/*
* Standard SMIA++ constants
@@ -41,12 +40,13 @@
(1000 + (SMIAPP_RESET_DELAY_CLOCKS * 1000 \
+ (clk) / 1000 - 1) / ((clk) / 1000))
-#define SMIAPP_COLOUR_COMPONENTS 4
+#define CCS_COLOUR_COMPONENTS 4
-#define SMIAPP_NAME "smiapp"
+#define SMIAPP_NAME "smiapp"
+#define CCS_NAME "ccs"
-#define SMIAPP_DFL_I2C_ADDR (0x20 >> 1) /* Default I2C Address */
-#define SMIAPP_ALT_I2C_ADDR (0x6e >> 1) /* Alternate I2C Address */
+#define CCS_DFL_I2C_ADDR (0x20 >> 1) /* Default I2C Address */
+#define CCS_ALT_I2C_ADDR (0x6e >> 1) /* Alternate I2C Address */
/*
* Sometimes due to board layout considerations the camera module can be
@@ -54,12 +54,12 @@
* corrected by giving a default H-FLIP and V-FLIP in the sensor readout.
* FIXME: rotation also changes the bayer pattern.
*/
-enum smiapp_module_board_orient {
- SMIAPP_MODULE_BOARD_ORIENT_0 = 0,
- SMIAPP_MODULE_BOARD_ORIENT_180,
+enum ccs_module_board_orient {
+ CCS_MODULE_BOARD_ORIENT_0 = 0,
+ CCS_MODULE_BOARD_ORIENT_180,
};
-struct smiapp_flash_strobe_parms {
+struct ccs_flash_strobe_parms {
u8 mode;
u32 strobe_width_high_us;
u16 strobe_delay;
@@ -67,7 +67,7 @@ struct smiapp_flash_strobe_parms {
u8 trigger;
};
-struct smiapp_hwconfig {
+struct ccs_hwconfig {
/*
* Change the cci address if i2c_addr_alt is set.
* Both default and alternate cci addr need to be present
@@ -78,19 +78,19 @@ struct smiapp_hwconfig {
uint32_t ext_clk; /* sensor external clk */
unsigned int lanes; /* Number of CSI-2 lanes */
- uint32_t csi_signalling_mode; /* SMIAPP_CSI_SIGNALLING_MODE_* */
+ uint32_t csi_signalling_mode; /* CCS_CSI_SIGNALLING_MODE_* */
uint64_t *op_sys_clock;
- enum smiapp_module_board_orient module_board_orient;
+ enum ccs_module_board_orient module_board_orient;
- struct smiapp_flash_strobe_parms *strobe_setup;
+ struct ccs_flash_strobe_parms *strobe_setup;
};
-struct smiapp_quirk;
+struct ccs_quirk;
-#define SMIAPP_MODULE_IDENT_FLAG_REV_LE (1 << 0)
+#define CCS_MODULE_IDENT_FLAG_REV_LE (1 << 0)
-struct smiapp_module_ident {
+struct ccs_module_ident {
u16 mipi_manufacturer_id;
u16 model_id;
u8 smia_manufacturer_id;
@@ -99,10 +99,10 @@ struct smiapp_module_ident {
u8 flags;
char *name;
- const struct smiapp_quirk *quirk;
+ const struct ccs_quirk *quirk;
};
-struct smiapp_module_info {
+struct ccs_module_info {
u32 smia_manufacturer_id;
u32 mipi_manufacturer_id;
u32 model_id;
@@ -126,10 +126,10 @@ struct smiapp_module_info {
u32 smiapp_profile;
char *name;
- const struct smiapp_quirk *quirk;
+ const struct ccs_quirk *quirk;
};
-#define SMIAPP_IDENT_FQ(manufacturer, model, rev, fl, _name, _quirk) \
+#define CCS_IDENT_FQ(manufacturer, model, rev, fl, _name, _quirk) \
{ .smia_manufacturer_id = manufacturer, \
.model_id = model, \
.revision_number_major = rev, \
@@ -137,22 +137,22 @@ struct smiapp_module_info {
.name = _name, \
.quirk = _quirk, }
-#define SMIAPP_IDENT_LQ(manufacturer, model, rev, _name, _quirk) \
+#define CCS_IDENT_LQ(manufacturer, model, rev, _name, _quirk) \
{ .smia_manufacturer_id = manufacturer, \
.model_id = model, \
.revision_number_major = rev, \
- .flags = SMIAPP_MODULE_IDENT_FLAG_REV_LE, \
+ .flags = CCS_MODULE_IDENT_FLAG_REV_LE, \
.name = _name, \
.quirk = _quirk, }
-#define SMIAPP_IDENT_L(manufacturer, model, rev, _name) \
+#define CCS_IDENT_L(manufacturer, model, rev, _name) \
{ .smia_manufacturer_id = manufacturer, \
.model_id = model, \
.revision_number_major = rev, \
- .flags = SMIAPP_MODULE_IDENT_FLAG_REV_LE, \
+ .flags = CCS_MODULE_IDENT_FLAG_REV_LE, \
.name = _name, }
-#define SMIAPP_IDENT_Q(manufacturer, model, rev, _name, _quirk) \
+#define CCS_IDENT_Q(manufacturer, model, rev, _name, _quirk) \
{ .smia_manufacturer_id = manufacturer, \
.model_id = model, \
.revision_number_major = rev, \
@@ -160,49 +160,49 @@ struct smiapp_module_info {
.name = _name, \
.quirk = _quirk, }
-#define SMIAPP_IDENT(manufacturer, model, rev, _name) \
+#define CCS_IDENT(manufacturer, model, rev, _name) \
{ .smia_manufacturer_id = manufacturer, \
.model_id = model, \
.revision_number_major = rev, \
.flags = 0, \
.name = _name, }
-struct smiapp_csi_data_format {
+struct ccs_csi_data_format {
u32 code;
u8 width;
u8 compressed;
u8 pixel_order;
};
-#define SMIAPP_SUBDEVS 3
+#define CCS_SUBDEVS 3
-#define SMIAPP_PA_PAD_SRC 0
-#define SMIAPP_PAD_SINK 0
-#define SMIAPP_PAD_SRC 1
-#define SMIAPP_PADS 2
+#define CCS_PA_PAD_SRC 0
+#define CCS_PAD_SINK 0
+#define CCS_PAD_SRC 1
+#define CCS_PADS 2
-struct smiapp_binning_subtype {
+struct ccs_binning_subtype {
u8 horizontal:4;
u8 vertical:4;
} __packed;
-struct smiapp_subdev {
+struct ccs_subdev {
struct v4l2_subdev sd;
- struct media_pad pads[SMIAPP_PADS];
+ struct media_pad pads[CCS_PADS];
struct v4l2_rect sink_fmt;
- struct v4l2_rect crop[SMIAPP_PADS];
+ struct v4l2_rect crop[CCS_PADS];
struct v4l2_rect compose; /* compose on sink */
unsigned short sink_pad;
unsigned short source_pad;
int npads;
- struct smiapp_sensor *sensor;
+ struct ccs_sensor *sensor;
struct v4l2_ctrl_handler ctrl_handler;
};
/*
- * struct smiapp_sensor - Main device structure
+ * struct ccs_sensor - Main device structure
*/
-struct smiapp_sensor {
+struct ccs_sensor {
/*
* "mutex" is used to serialise access to all fields here
* except v4l2_ctrls at the end of the struct. "mutex" is also
@@ -210,22 +210,22 @@ struct smiapp_sensor {
* information.
*/
struct mutex mutex;
- struct smiapp_subdev ssds[SMIAPP_SUBDEVS];
+ struct ccs_subdev ssds[CCS_SUBDEVS];
u32 ssds_used;
- struct smiapp_subdev *src;
- struct smiapp_subdev *binner;
- struct smiapp_subdev *scaler;
- struct smiapp_subdev *pixel_array;
- struct smiapp_hwconfig *hwcfg;
+ struct ccs_subdev *src;
+ struct ccs_subdev *binner;
+ struct ccs_subdev *scaler;
+ struct ccs_subdev *pixel_array;
+ struct ccs_hwconfig *hwcfg;
struct regulator *vana;
struct clk *ext_clk;
struct gpio_desc *xshutdown;
void *ccs_limits;
u8 nbinning_subtypes;
- struct smiapp_binning_subtype binning_subtypes[CCS_LIM_BINNING_SUB_TYPE_MAX_N + 1];
+ struct ccs_binning_subtype binning_subtypes[CCS_LIM_BINNING_SUB_TYPE_MAX_N + 1];
u32 mbus_frame_fmts;
- const struct smiapp_csi_data_format *csi_format;
- const struct smiapp_csi_data_format *internal_csi_format;
+ const struct ccs_csi_data_format *csi_format;
+ const struct ccs_csi_data_format *internal_csi_format;
u32 default_mbus_frame_fmts;
int default_pixel_order;
@@ -246,7 +246,7 @@ struct smiapp_sensor {
bool dev_init_done;
u8 compressed_min_bpp;
- struct smiapp_module_info minfo;
+ struct ccs_module_info minfo;
struct smiapp_pll pll;
@@ -265,16 +265,16 @@ struct smiapp_sensor {
struct v4l2_ctrl *link_freq;
struct v4l2_ctrl *pixel_rate_csi;
/* test pattern colour components */
- struct v4l2_ctrl *test_data[SMIAPP_COLOUR_COMPONENTS];
+ struct v4l2_ctrl *test_data[CCS_COLOUR_COMPONENTS];
};
-#define to_smiapp_subdev(_sd) \
- container_of(_sd, struct smiapp_subdev, sd)
+#define to_ccs_subdev(_sd) \
+ container_of(_sd, struct ccs_subdev, sd)
-#define to_smiapp_sensor(_sd) \
- (to_smiapp_subdev(_sd)->sensor)
+#define to_ccs_sensor(_sd) \
+ (to_ccs_subdev(_sd)->sensor)
-void ccs_replace_limit(struct smiapp_sensor *sensor,
+void ccs_replace_limit(struct ccs_sensor *sensor,
unsigned int limit, unsigned int offset, u32 val);
-#endif /* __SMIAPP_PRIV_H_ */
+#endif /* __CCS_H__ */
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 016/106] smiapp: Differentiate CCS sensors from SMIA in subdev naming
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (13 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 015/106] smiapp: Internal rename to CCS Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 017/106] smiapp: Rename as "ccs" Sakari Ailus
` (81 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
Call CCS compliant sensors as "ccs" instead of "smiapp" in absence of a
device specific name. This is done based on the value of the manufacturer
ID register that is only present in CCS.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/ccs-core.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/media/i2c/smiapp/ccs-core.c b/drivers/media/i2c/smiapp/ccs-core.c
index dd093a7d2ef4..c82e311d2661 100644
--- a/drivers/media/i2c/smiapp/ccs-core.c
+++ b/drivers/media/i2c/smiapp/ccs-core.c
@@ -2437,8 +2437,6 @@ static int ccs_identify_module(struct ccs_sensor *sensor)
unsigned int i;
int rval = 0;
- minfo->name = SMIAPP_NAME;
-
/* Module info */
rval = ccs_read(sensor, MODULE_MANUFACTURER_ID,
&minfo->mipi_manufacturer_id);
@@ -2528,15 +2526,18 @@ static int ccs_identify_module(struct ccs_sensor *sensor)
"sensor revision 0x%2.2x firmware version 0x%2.2x\n",
minfo->sensor_revision_number, minfo->sensor_firmware_version);
- if (minfo->ccs_version)
+ if (minfo->ccs_version) {
dev_dbg(&client->dev, "MIPI CCS version %u.%u",
(minfo->ccs_version & CCS_MIPI_CCS_VERSION_MAJOR_MASK)
>> CCS_MIPI_CCS_VERSION_MAJOR_SHIFT,
(minfo->ccs_version & CCS_MIPI_CCS_VERSION_MINOR_MASK));
- else
+ minfo->name = CCS_NAME;
+ } else {
dev_dbg(&client->dev,
"smia version %2.2d smiapp version %2.2d\n",
minfo->smia_version, minfo->smiapp_version);
+ minfo->name = SMIAPP_NAME;
+ }
/*
* Some modules have bad data in the lvalues below. Hope the
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 017/106] smiapp: Rename as "ccs"
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (14 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 016/106] smiapp: Differentiate CCS sensors from SMIA in subdev naming Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 018/106] ccs: Remove profile concept Sakari Ailus
` (80 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
Rename the "smiapp" driver as "ccs". MIPI CCS is the contemporary standard
for raw Bayer camera sensors. The driver retains support for the SMIA++
and SMIA compliant camera sensors. A module alias is added for old user
space using "smiapp" module name.
Add Intel copyright while at it.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
MAINTAINERS | 20 +++++++++----------
drivers/media/i2c/Kconfig | 2 +-
drivers/media/i2c/Makefile | 2 +-
drivers/media/i2c/{smiapp => ccs}/Kconfig | 7 ++++---
drivers/media/i2c/{smiapp => ccs}/Makefile | 4 ++--
drivers/media/i2c/{smiapp => ccs}/ccs-core.c | 6 ++++--
drivers/media/i2c/{smiapp => ccs}/ccs-os.h | 0
drivers/media/i2c/{smiapp => ccs}/ccs-quirk.c | 5 +++--
drivers/media/i2c/{smiapp => ccs}/ccs-quirk.h | 5 +++--
.../i2c/{smiapp => ccs}/ccs-reg-access.c | 5 +++--
.../i2c/{smiapp => ccs}/ccs-reg-access.h | 5 +++--
.../media/i2c/{smiapp => ccs}/ccs-regs.txt | 0
drivers/media/i2c/{smiapp => ccs}/ccs.h | 3 ++-
drivers/media/i2c/{smiapp => ccs}/mk-ccs-regs | 0
.../i2c/{smiapp => ccs}/smiapp-reg-defs.h | 3 ++-
15 files changed, 38 insertions(+), 29 deletions(-)
rename drivers/media/i2c/{smiapp => ccs}/Kconfig (55%)
rename drivers/media/i2c/{smiapp => ccs}/Makefile (85%)
rename drivers/media/i2c/{smiapp => ccs}/ccs-core.c (99%)
rename drivers/media/i2c/{smiapp => ccs}/ccs-os.h (100%)
rename drivers/media/i2c/{smiapp => ccs}/ccs-quirk.c (97%)
rename drivers/media/i2c/{smiapp => ccs}/ccs-quirk.h (94%)
rename drivers/media/i2c/{smiapp => ccs}/ccs-reg-access.c (97%)
rename drivers/media/i2c/{smiapp => ccs}/ccs-reg-access.h (86%)
rename drivers/media/i2c/{smiapp => ccs}/ccs-regs.txt (100%)
rename drivers/media/i2c/{smiapp => ccs}/ccs.h (98%)
rename drivers/media/i2c/{smiapp => ccs}/mk-ccs-regs (100%)
rename drivers/media/i2c/{smiapp => ccs}/smiapp-reg-defs.h (99%)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7f49b7c8be65..f604993cead9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11560,6 +11560,16 @@ M: Oliver Neukum <oliver@neukum.org>
S: Maintained
F: drivers/usb/image/microtek.*
+MIPI CCS, SMIA AND SMIA++ IMAGE SENSOR DRIVER
+M: Sakari Ailus <sakari.ailus@linux.intel.com>
+L: linux-media@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
+F: drivers/media/i2c/ccs/
+F: drivers/media/i2c/smiapp-pll.c
+F: drivers/media/i2c/smiapp-pll.h
+F: include/uapi/linux/smiapp.h
+
MIPS
M: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
L: linux-mips@vger.kernel.org
@@ -15957,16 +15967,6 @@ S: Maintained
F: drivers/firmware/smccc/
F: include/linux/arm-smccc.h
-SMIA AND SMIA++ IMAGE SENSOR DRIVER
-M: Sakari Ailus <sakari.ailus@linux.intel.com>
-L: linux-media@vger.kernel.org
-S: Maintained
-F: Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
-F: drivers/media/i2c/smiapp-pll.c
-F: drivers/media/i2c/smiapp-pll.h
-F: drivers/media/i2c/smiapp/
-F: include/uapi/linux/smiapp.h
-
SMM665 HARDWARE MONITOR DRIVER
M: Guenter Roeck <linux@roeck-us.net>
L: linux-hwmon@vger.kernel.org
diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
index c64326ca331c..41a8b6189259 100644
--- a/drivers/media/i2c/Kconfig
+++ b/drivers/media/i2c/Kconfig
@@ -1233,7 +1233,7 @@ config VIDEO_S5K5BAF
This is a V4L2 sensor driver for Samsung S5K5BAF 2M
camera sensor with an embedded SoC image signal processor.
-source "drivers/media/i2c/smiapp/Kconfig"
+source "drivers/media/i2c/ccs/Kconfig"
source "drivers/media/i2c/et8ek8/Kconfig"
config VIDEO_S5C73M3
diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
index f0a77473979d..cb0be09e38bd 100644
--- a/drivers/media/i2c/Makefile
+++ b/drivers/media/i2c/Makefile
@@ -2,7 +2,7 @@
msp3400-objs := msp3400-driver.o msp3400-kthreads.o
obj-$(CONFIG_VIDEO_MSP3400) += msp3400.o
-obj-$(CONFIG_VIDEO_SMIAPP) += smiapp/
+obj-$(CONFIG_VIDEO_CCS) += ccs/
obj-$(CONFIG_VIDEO_ET8EK8) += et8ek8/
obj-$(CONFIG_VIDEO_CX25840) += cx25840/
obj-$(CONFIG_VIDEO_M5MOLS) += m5mols/
diff --git a/drivers/media/i2c/smiapp/Kconfig b/drivers/media/i2c/ccs/Kconfig
similarity index 55%
rename from drivers/media/i2c/smiapp/Kconfig
rename to drivers/media/i2c/ccs/Kconfig
index 6893b532824f..b4f8b10da420 100644
--- a/drivers/media/i2c/smiapp/Kconfig
+++ b/drivers/media/i2c/ccs/Kconfig
@@ -1,10 +1,11 @@
# SPDX-License-Identifier: GPL-2.0-only
-config VIDEO_SMIAPP
- tristate "SMIA++/SMIA sensor support"
+config VIDEO_CCS
+ tristate "MIPI CCS/SMIA++/SMIA sensor support"
depends on I2C && VIDEO_V4L2 && HAVE_CLK
select MEDIA_CONTROLLER
select VIDEO_V4L2_SUBDEV_API
select VIDEO_SMIAPP_PLL
select V4L2_FWNODE
help
- This is a generic driver for SMIA++/SMIA camera modules.
+ This is a generic driver for MIPI CCS, SMIA++ and SMIA compliant
+ camera sensors.
diff --git a/drivers/media/i2c/smiapp/Makefile b/drivers/media/i2c/ccs/Makefile
similarity index 85%
rename from drivers/media/i2c/smiapp/Makefile
rename to drivers/media/i2c/ccs/Makefile
index f86f871f0a58..0f3d11b86dad 100644
--- a/drivers/media/i2c/smiapp/Makefile
+++ b/drivers/media/i2c/ccs/Makefile
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
-smiapp-objs += ccs-core.o ccs-reg-access.o \
+ccs-objs += ccs-core.o ccs-reg-access.o \
ccs-quirk.o ccs-limits.o
-obj-$(CONFIG_VIDEO_SMIAPP) += smiapp.o
+obj-$(CONFIG_VIDEO_CCS) += ccs.o
ccflags-y += -I $(srctree)/drivers/media/i2c
diff --git a/drivers/media/i2c/smiapp/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
similarity index 99%
rename from drivers/media/i2c/smiapp/ccs-core.c
rename to drivers/media/i2c/ccs/ccs-core.c
index c82e311d2661..6a47a5c16bb1 100644
--- a/drivers/media/i2c/smiapp/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -1,9 +1,10 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * drivers/media/i2c/smiapp/ccs-core.c
+ * drivers/media/i2c/ccs/ccs-core.c
*
- * Generic driver for SMIA/SMIA++ compliant camera modules
+ * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
*
+ * Copyright (C) 2020 Intel Corporation
* Copyright (C) 2010--2012 Nokia Corporation
* Contact: Sakari Ailus <sakari.ailus@iki.fi>
*
@@ -3298,3 +3299,4 @@ module_exit(ccs_module_cleanup);
MODULE_AUTHOR("Sakari Ailus <sakari.ailus@iki.fi>");
MODULE_DESCRIPTION("Generic MIPI CCS/SMIA/SMIA++ camera sensor driver");
MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("smiapp");
diff --git a/drivers/media/i2c/smiapp/ccs-os.h b/drivers/media/i2c/ccs/ccs-os.h
similarity index 100%
rename from drivers/media/i2c/smiapp/ccs-os.h
rename to drivers/media/i2c/ccs/ccs-os.h
diff --git a/drivers/media/i2c/smiapp/ccs-quirk.c b/drivers/media/i2c/ccs/ccs-quirk.c
similarity index 97%
rename from drivers/media/i2c/smiapp/ccs-quirk.c
rename to drivers/media/i2c/ccs/ccs-quirk.c
index 6c48d0901952..5a24da1d7aa9 100644
--- a/drivers/media/i2c/smiapp/ccs-quirk.c
+++ b/drivers/media/i2c/ccs/ccs-quirk.c
@@ -1,9 +1,10 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * drivers/media/i2c/smiapp/ccs-quirk.c
+ * drivers/media/i2c/ccs/ccs-quirk.c
*
- * Generic driver for SMIA/SMIA++ compliant camera modules
+ * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
*
+ * Copyright (C) 2020 Intel Corporation
* Copyright (C) 2011--2012 Nokia Corporation
* Contact: Sakari Ailus <sakari.ailus@iki.fi>
*/
diff --git a/drivers/media/i2c/smiapp/ccs-quirk.h b/drivers/media/i2c/ccs/ccs-quirk.h
similarity index 94%
rename from drivers/media/i2c/smiapp/ccs-quirk.h
rename to drivers/media/i2c/ccs/ccs-quirk.h
index d208379158f2..3e7779e2fc4b 100644
--- a/drivers/media/i2c/smiapp/ccs-quirk.h
+++ b/drivers/media/i2c/ccs/ccs-quirk.h
@@ -1,9 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * drivers/media/i2c/smiapp/ccs-quirk.h
+ * drivers/media/i2c/ccs/ccs-quirk.h
*
- * Generic driver for SMIA/SMIA++ compliant camera modules
+ * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
*
+ * Copyright (C) 2020 Intel Corporation
* Copyright (C) 2011--2012 Nokia Corporation
* Contact: Sakari Ailus <sakari.ailus@iki.fi>
*/
diff --git a/drivers/media/i2c/smiapp/ccs-reg-access.c b/drivers/media/i2c/ccs/ccs-reg-access.c
similarity index 97%
rename from drivers/media/i2c/smiapp/ccs-reg-access.c
rename to drivers/media/i2c/ccs/ccs-reg-access.c
index 4e6d212473fc..a8e9a235bfb3 100644
--- a/drivers/media/i2c/smiapp/ccs-reg-access.c
+++ b/drivers/media/i2c/ccs/ccs-reg-access.c
@@ -1,9 +1,10 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * drivers/media/i2c/smiapp/ccs-regs.c
+ * drivers/media/i2c/ccs/ccs-reg-access.c
*
- * Generic driver for SMIA/SMIA++ compliant camera modules
+ * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
*
+ * Copyright (C) 2020 Intel Corporation
* Copyright (C) 2011--2012 Nokia Corporation
* Contact: Sakari Ailus <sakari.ailus@iki.fi>
*/
diff --git a/drivers/media/i2c/smiapp/ccs-reg-access.h b/drivers/media/i2c/ccs/ccs-reg-access.h
similarity index 86%
rename from drivers/media/i2c/smiapp/ccs-reg-access.h
rename to drivers/media/i2c/ccs/ccs-reg-access.h
index 76ac036a9538..9fdf5659ed09 100644
--- a/drivers/media/i2c/smiapp/ccs-reg-access.h
+++ b/drivers/media/i2c/ccs/ccs-reg-access.h
@@ -1,9 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * include/media/smiapp/ccs-regs.h
+ * include/media/ccs/ccs-reg-access.h
*
- * Generic driver for SMIA/SMIA++ compliant camera modules
+ * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
*
+ * Copyright (C) 2020 Intel Corporation
* Copyright (C) 2011--2012 Nokia Corporation
* Contact: Sakari Ailus <sakari.ailus@iki.fi>
*/
diff --git a/drivers/media/i2c/smiapp/ccs-regs.txt b/drivers/media/i2c/ccs/ccs-regs.txt
similarity index 100%
rename from drivers/media/i2c/smiapp/ccs-regs.txt
rename to drivers/media/i2c/ccs/ccs-regs.txt
diff --git a/drivers/media/i2c/smiapp/ccs.h b/drivers/media/i2c/ccs/ccs.h
similarity index 98%
rename from drivers/media/i2c/smiapp/ccs.h
rename to drivers/media/i2c/ccs/ccs.h
index 20b1125d87dc..7f6ed95b7b78 100644
--- a/drivers/media/i2c/smiapp/ccs.h
+++ b/drivers/media/i2c/ccs/ccs.h
@@ -2,8 +2,9 @@
/*
* drivers/media/i2c/smiapp/ccs.h
*
- * Generic driver for SMIA/SMIA++ compliant camera modules
+ * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
*
+ * Copyright (C) 2020 Intel Corporation
* Copyright (C) 2010--2012 Nokia Corporation
* Contact: Sakari Ailus <sakari.ailus@iki.fi>
*/
diff --git a/drivers/media/i2c/smiapp/mk-ccs-regs b/drivers/media/i2c/ccs/mk-ccs-regs
similarity index 100%
rename from drivers/media/i2c/smiapp/mk-ccs-regs
rename to drivers/media/i2c/ccs/mk-ccs-regs
diff --git a/drivers/media/i2c/smiapp/smiapp-reg-defs.h b/drivers/media/i2c/ccs/smiapp-reg-defs.h
similarity index 99%
rename from drivers/media/i2c/smiapp/smiapp-reg-defs.h
rename to drivers/media/i2c/ccs/smiapp-reg-defs.h
index 06b69b1ab55f..e80c110ebf3a 100644
--- a/drivers/media/i2c/smiapp/smiapp-reg-defs.h
+++ b/drivers/media/i2c/ccs/smiapp-reg-defs.h
@@ -2,8 +2,9 @@
/*
* drivers/media/i2c/smiapp/smiapp-reg-defs.h
*
- * Generic driver for SMIA/SMIA++ compliant camera modules
+ * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
*
+ * Copyright (C) 2020 Intel Corporation
* Copyright (C) 2011--2012 Nokia Corporation
* Contact: Sakari Ailus <sakari.ailus@iki.fi>
*/
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 018/106] ccs: Remove profile concept
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (15 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 017/106] smiapp: Rename as "ccs" Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 019/106] ccs: Give all subdevs a function Sakari Ailus
` (79 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
The driver doesn't do anything tangible with profiles. Remove the notion,
and use the capabilities directly.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 23 ++++++-----------------
drivers/media/i2c/ccs/ccs.h | 2 --
2 files changed, 6 insertions(+), 19 deletions(-)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 6a47a5c16bb1..22050d33f0e8 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -377,7 +377,7 @@ static int ccs_pll_configure(struct ccs_sensor *sensor)
rval = ccs_write(sensor, REQUESTED_LINK_RATE,
DIV_ROUND_UP(pll->op.sys_clk_freq_hz,
1000000 / 256 / 256));
- if (rval < 0 || sensor->minfo.smiapp_profile == SMIAPP_PROFILE_0)
+ if (rval < 0 || sensor->pll.flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)
return rval;
rval = ccs_write(sensor, OP_PIX_CLK_DIV, pll->op.pix_clk_div);
@@ -3096,23 +3096,17 @@ static int ccs_probe(struct i2c_client *client)
}
}
- /* We consider this as profile 0 sensor if any of these are zero. */
if (!CCS_LIM(sensor, MIN_OP_SYS_CLK_DIV) ||
!CCS_LIM(sensor, MAX_OP_SYS_CLK_DIV) ||
!CCS_LIM(sensor, MIN_OP_PIX_CLK_DIV) ||
!CCS_LIM(sensor, MAX_OP_PIX_CLK_DIV)) {
- sensor->minfo.smiapp_profile = SMIAPP_PROFILE_0;
+ /* No OP clock branch */
+ sensor->pll.flags |= SMIAPP_PLL_FLAG_NO_OP_CLOCKS;
} else if (CCS_LIM(sensor, SCALING_CAPABILITY)
- != CCS_SCALING_CAPABILITY_NONE) {
- if (CCS_LIM(sensor, SCALING_CAPABILITY)
- == CCS_SCALING_CAPABILITY_HORIZONTAL)
- sensor->minfo.smiapp_profile = SMIAPP_PROFILE_1;
- else
- sensor->minfo.smiapp_profile = SMIAPP_PROFILE_2;
- sensor->scaler = &sensor->ssds[sensor->ssds_used];
- sensor->ssds_used++;
- } else if (CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY)
+ != CCS_SCALING_CAPABILITY_NONE ||
+ CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY)
== CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP) {
+ /* We have a scaler or digital crop. */
sensor->scaler = &sensor->ssds[sensor->ssds_used];
sensor->ssds_used++;
}
@@ -3128,16 +3122,11 @@ static int ccs_probe(struct i2c_client *client)
sensor->pll.csi2.lanes = sensor->hwcfg->lanes;
sensor->pll.ext_clk_freq_hz = sensor->hwcfg->ext_clk;
sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN);
- /* Profile 0 sensors have no separate OP clock branch. */
- if (sensor->minfo.smiapp_profile == SMIAPP_PROFILE_0)
- sensor->pll.flags |= SMIAPP_PLL_FLAG_NO_OP_CLOCKS;
ccs_create_subdev(sensor, sensor->scaler, " scaler", 2);
ccs_create_subdev(sensor, sensor->binner, " binner", 2);
ccs_create_subdev(sensor, sensor->pixel_array, " pixel_array", 1);
- dev_dbg(&client->dev, "profile %d\n", sensor->minfo.smiapp_profile);
-
sensor->pixel_array->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
rval = ccs_init_controls(sensor);
diff --git a/drivers/media/i2c/ccs/ccs.h b/drivers/media/i2c/ccs/ccs.h
index 7f6ed95b7b78..8933f3d40fa5 100644
--- a/drivers/media/i2c/ccs/ccs.h
+++ b/drivers/media/i2c/ccs/ccs.h
@@ -124,8 +124,6 @@ struct ccs_module_info {
u32 smiapp_version;
u32 ccs_version;
- u32 smiapp_profile;
-
char *name;
const struct ccs_quirk *quirk;
};
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 019/106] ccs: Give all subdevs a function
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (16 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 018/106] ccs: Remove profile concept Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 027/106] ccs: Request for "reset" GPIO Sakari Ailus
` (78 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
This removes a warning at driver probe time telling that one or two
entities have no function set. The function used for both the binner and
scaler is the scaler.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 22050d33f0e8..1880ed31845e 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -2685,7 +2685,7 @@ static void ccs_cleanup(struct ccs_sensor *sensor)
static void ccs_create_subdev(struct ccs_sensor *sensor,
struct ccs_subdev *ssd, const char *name,
- unsigned short num_pads)
+ unsigned short num_pads, u32 function)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
@@ -2696,6 +2696,7 @@ static void ccs_create_subdev(struct ccs_sensor *sensor,
v4l2_subdev_init(&ssd->sd, &ccs_ops);
ssd->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
+ ssd->sd.entity.function = function;
ssd->sensor = sensor;
ssd->npads = num_pads;
@@ -3123,11 +3124,12 @@ static int ccs_probe(struct i2c_client *client)
sensor->pll.ext_clk_freq_hz = sensor->hwcfg->ext_clk;
sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN);
- ccs_create_subdev(sensor, sensor->scaler, " scaler", 2);
- ccs_create_subdev(sensor, sensor->binner, " binner", 2);
- ccs_create_subdev(sensor, sensor->pixel_array, " pixel_array", 1);
-
- sensor->pixel_array->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
+ ccs_create_subdev(sensor, sensor->scaler, " scaler", 2,
+ MEDIA_ENT_F_CAM_SENSOR);
+ ccs_create_subdev(sensor, sensor->binner, " binner", 2,
+ MEDIA_ENT_F_PROC_VIDEO_SCALER);
+ ccs_create_subdev(sensor, sensor->pixel_array, " pixel_array", 1,
+ MEDIA_ENT_F_PROC_VIDEO_SCALER);
rval = ccs_init_controls(sensor);
if (rval < 0)
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 027/106] ccs: Request for "reset" GPIO
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (17 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 019/106] ccs: Give all subdevs a function Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 028/106] ccs: Add MIPI CCS compatible strings Sakari Ailus
` (77 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
The DT bindings documented "reset-gpios" property but the driver never
made use of it. Instead it used a GPIO called "xshutdown", with apprently
wrong polarity.
Fix this by requesting "reset" GPIO with the right polarity first, and if
that fails, then request "xshutdown" GPIO with the old polarity. This way
it works for new users as expected while if someone, somewhere, depended
on "xshutdown" GPIO, that continues to work as well.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 14 ++++++++++++--
drivers/media/i2c/ccs/ccs.h | 1 +
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 1880ed31845e..775037ce361f 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -1295,6 +1295,7 @@ static int ccs_power_on(struct device *dev)
}
usleep_range(1000, 1000);
+ gpiod_set_value(sensor->reset, 0);
gpiod_set_value(sensor->xshutdown, 1);
sleep = SMIAPP_RESET_DELAY(sensor->hwcfg->ext_clk);
@@ -1381,6 +1382,7 @@ static int ccs_power_on(struct device *dev)
return 0;
out_cci_addr_fail:
+ gpiod_set_value(sensor->reset, 1);
gpiod_set_value(sensor->xshutdown, 0);
clk_disable_unprepare(sensor->ext_clk);
@@ -1407,6 +1409,7 @@ static int ccs_power_off(struct device *dev)
if (sensor->hwcfg->i2c_addr_alt)
ccs_write(sensor, SOFTWARE_RESET, CCS_SOFTWARE_RESET_ON);
+ gpiod_set_value(sensor->reset, 1);
gpiod_set_value(sensor->xshutdown, 0);
clk_disable_unprepare(sensor->ext_clk);
usleep_range(5000, 5000);
@@ -3008,8 +3011,15 @@ static int ccs_probe(struct i2c_client *client)
return -EINVAL;
}
- sensor->xshutdown = devm_gpiod_get_optional(&client->dev, "xshutdown",
- GPIOD_OUT_LOW);
+ sensor->reset = devm_gpiod_get_optional(&client->dev, "reset",
+ GPIOD_OUT_HIGH);
+ if (IS_ERR(sensor->reset))
+ return PTR_ERR(sensor->reset);
+ /* Support old users that may have used "xshutdown" property. */
+ if (!sensor->reset)
+ sensor->xshutdown = devm_gpiod_get_optional(&client->dev,
+ "xshutdown",
+ GPIOD_OUT_LOW);
if (IS_ERR(sensor->xshutdown))
return PTR_ERR(sensor->xshutdown);
diff --git a/drivers/media/i2c/ccs/ccs.h b/drivers/media/i2c/ccs/ccs.h
index 8933f3d40fa5..bfe39e02f5e9 100644
--- a/drivers/media/i2c/ccs/ccs.h
+++ b/drivers/media/i2c/ccs/ccs.h
@@ -219,6 +219,7 @@ struct ccs_sensor {
struct regulator *vana;
struct clk *ext_clk;
struct gpio_desc *xshutdown;
+ struct gpio_desc *reset;
void *ccs_limits;
u8 nbinning_subtypes;
struct ccs_binning_subtype binning_subtypes[CCS_LIM_BINNING_SUB_TYPE_MAX_N + 1];
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 028/106] ccs: Add MIPI CCS compatible strings
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (18 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 027/106] ccs: Request for "reset" GPIO Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 029/106] ccs: Remove the I²C ID table Sakari Ailus
` (76 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
Add "mipi-ccs-1.0" and "mipi-ccs-1.1" compatible strings to the CCS
driver.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 775037ce361f..e348f55c62a6 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -3236,6 +3236,9 @@ static int ccs_remove(struct i2c_client *client)
}
static const struct of_device_id ccs_of_table[] = {
+ { .compatible = "mipi-ccs-1.1" },
+ { .compatible = "mipi-ccs-1.0" },
+ { .compatible = "mipi-ccs" },
{ .compatible = "nokia,smia" },
{ },
};
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 029/106] ccs: Remove the I²C ID table
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (19 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 028/106] ccs: Add MIPI CCS compatible strings Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-11-05 9:34 ` Mauro Carvalho Chehab
2020-10-07 8:44 ` [PATCH v2 030/106] ccs: Remove remaining support for platform data Sakari Ailus
` (75 subsequent siblings)
96 siblings, 1 reply; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
The I²C ID table is no longer needed; remove it.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 7 -------
1 file changed, 7 deletions(-)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index e348f55c62a6..660d5ab2c89d 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -3244,12 +3244,6 @@ static const struct of_device_id ccs_of_table[] = {
};
MODULE_DEVICE_TABLE(of, ccs_of_table);
-static const struct i2c_device_id ccs_id_table[] = {
- { SMIAPP_NAME, 0 },
- { },
-};
-MODULE_DEVICE_TABLE(i2c, ccs_id_table);
-
static const struct dev_pm_ops ccs_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(ccs_suspend, ccs_resume)
SET_RUNTIME_PM_OPS(ccs_power_off, ccs_power_on, NULL)
@@ -3263,7 +3257,6 @@ static struct i2c_driver ccs_i2c_driver = {
},
.probe_new = ccs_probe,
.remove = ccs_remove,
- .id_table = ccs_id_table,
};
static int ccs_module_init(void)
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 030/106] ccs: Remove remaining support for platform data
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (20 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 029/106] ccs: Remove the I²C ID table Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 031/106] ccs: Make hwcfg part of the device specific struct Sakari Ailus
` (74 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
No need to support platform data; remove support for conveying hardware
configuration that way.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 660d5ab2c89d..ae94dafc12de 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -2854,9 +2854,6 @@ static struct ccs_hwconfig *ccs_get_hwconfig(struct device *dev)
int i;
int rval;
- if (!fwnode)
- return dev->platform_data;
-
ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
if (!ep)
return NULL;
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 031/106] ccs: Make hwcfg part of the device specific struct
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (21 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 030/106] ccs: Remove remaining support for platform data Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 032/106] ccs: Fix obtaining bus information from firmware Sakari Ailus
` (73 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
There's no need to allocate the hardware configuration struct separately.
Put it in struct ccs_sensor.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 94 ++++++++++++++++---------------
drivers/media/i2c/ccs/ccs-quirk.c | 4 +-
drivers/media/i2c/ccs/ccs.h | 2 +-
3 files changed, 51 insertions(+), 49 deletions(-)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index ae94dafc12de..811f738f23aa 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -803,7 +803,7 @@ static int ccs_init_late_controls(struct ccs_sensor *sensor)
sensor->link_freq = v4l2_ctrl_new_int_menu(
&sensor->src->ctrl_handler, &ccs_ctrl_ops,
V4L2_CID_LINK_FREQ, __fls(*valid_link_freqs),
- __ffs(*valid_link_freqs), sensor->hwcfg->op_sys_clock);
+ __ffs(*valid_link_freqs), sensor->hwcfg.op_sys_clock);
return sensor->src->ctrl_handler.error;
}
@@ -916,8 +916,8 @@ static int ccs_get_mbus_formats(struct ccs_sensor *sensor)
pll->bits_per_pixel = f->compressed;
- for (j = 0; sensor->hwcfg->op_sys_clock[j]; j++) {
- pll->link_freq = sensor->hwcfg->op_sys_clock[j];
+ for (j = 0; sensor->hwcfg.op_sys_clock[j]; j++) {
+ pll->link_freq = sensor->hwcfg.op_sys_clock[j];
rval = ccs_pll_try(sensor, pll);
dev_dbg(&client->dev, "link freq %u Hz, bpp %u %s\n",
@@ -1117,21 +1117,21 @@ static int ccs_change_cci_addr(struct ccs_sensor *sensor)
int rval;
u32 val;
- client->addr = sensor->hwcfg->i2c_addr_dfl;
+ client->addr = sensor->hwcfg.i2c_addr_dfl;
rval = ccs_write(sensor, CCI_ADDRESS_CTRL,
- sensor->hwcfg->i2c_addr_alt << 1);
+ sensor->hwcfg.i2c_addr_alt << 1);
if (rval)
return rval;
- client->addr = sensor->hwcfg->i2c_addr_alt;
+ client->addr = sensor->hwcfg.i2c_addr_alt;
/* verify addr change went ok */
rval = ccs_read(sensor, CCI_ADDRESS_CTRL, &val);
if (rval)
return rval;
- if (val != sensor->hwcfg->i2c_addr_alt << 1)
+ if (val != sensor->hwcfg.i2c_addr_alt << 1)
return -ENODEV;
return 0;
@@ -1145,13 +1145,13 @@ static int ccs_change_cci_addr(struct ccs_sensor *sensor)
static int ccs_setup_flash_strobe(struct ccs_sensor *sensor)
{
struct ccs_flash_strobe_parms *strobe_setup;
- unsigned int ext_freq = sensor->hwcfg->ext_clk;
+ unsigned int ext_freq = sensor->hwcfg.ext_clk;
u32 tmp;
u32 strobe_adjustment;
u32 strobe_width_high_rs;
int rval;
- strobe_setup = sensor->hwcfg->strobe_setup;
+ strobe_setup = sensor->hwcfg.strobe_setup;
/*
* How to calculate registers related to strobe length. Please
@@ -1259,7 +1259,7 @@ static int ccs_setup_flash_strobe(struct ccs_sensor *sensor)
rval = ccs_write(sensor, FLASH_TRIGGER_RS, strobe_setup->trigger);
out:
- sensor->hwcfg->strobe_setup->trigger = 0;
+ sensor->hwcfg.strobe_setup->trigger = 0;
return rval;
}
@@ -1298,7 +1298,7 @@ static int ccs_power_on(struct device *dev)
gpiod_set_value(sensor->reset, 0);
gpiod_set_value(sensor->xshutdown, 1);
- sleep = SMIAPP_RESET_DELAY(sensor->hwcfg->ext_clk);
+ sleep = SMIAPP_RESET_DELAY(sensor->hwcfg.ext_clk);
usleep_range(sleep, sleep);
/*
@@ -1312,7 +1312,7 @@ static int ccs_power_on(struct device *dev)
* is found.
*/
- if (sensor->hwcfg->i2c_addr_alt) {
+ if (sensor->hwcfg.i2c_addr_alt) {
rval = ccs_change_cci_addr(sensor);
if (rval) {
dev_err(dev, "cci address change error\n");
@@ -1326,7 +1326,7 @@ static int ccs_power_on(struct device *dev)
goto out_cci_addr_fail;
}
- if (sensor->hwcfg->i2c_addr_alt) {
+ if (sensor->hwcfg.i2c_addr_alt) {
rval = ccs_change_cci_addr(sensor);
if (rval) {
dev_err(dev, "cci address change error\n");
@@ -1342,13 +1342,13 @@ static int ccs_power_on(struct device *dev)
}
rval = ccs_write(sensor, EXTCLK_FREQUENCY_MHZ,
- sensor->hwcfg->ext_clk / (1000000 / (1 << 8)));
+ sensor->hwcfg.ext_clk / (1000000 / (1 << 8)));
if (rval) {
dev_err(dev, "extclk frequency set failed\n");
goto out_cci_addr_fail;
}
- rval = ccs_write(sensor, CSI_LANE_MODE, sensor->hwcfg->lanes - 1);
+ rval = ccs_write(sensor, CSI_LANE_MODE, sensor->hwcfg.lanes - 1);
if (rval) {
dev_err(dev, "csi lane mode set failed\n");
goto out_cci_addr_fail;
@@ -1362,7 +1362,7 @@ static int ccs_power_on(struct device *dev)
}
rval = ccs_write(sensor, CSI_SIGNALING_MODE,
- sensor->hwcfg->csi_signalling_mode);
+ sensor->hwcfg.csi_signalling_mode);
if (rval) {
dev_err(dev, "csi signalling mode set failed\n");
goto out_cci_addr_fail;
@@ -1406,7 +1406,7 @@ static int ccs_power_off(struct device *dev)
* really see a power off and next time the cci address change
* will fail. So do a soft reset explicitly here.
*/
- if (sensor->hwcfg->i2c_addr_alt)
+ if (sensor->hwcfg.i2c_addr_alt)
ccs_write(sensor, SOFTWARE_RESET, CCS_SOFTWARE_RESET_ON);
gpiod_set_value(sensor->reset, 1);
@@ -1545,8 +1545,8 @@ static int ccs_start_streaming(struct ccs_sensor *sensor)
if (CCS_LIM(sensor, FLASH_MODE_CAPABILITY) &
(CCS_FLASH_MODE_CAPABILITY_SINGLE_STROBE |
SMIAPP_FLASH_MODE_CAPABILITY_MULTIPLE_STROBE) &&
- sensor->hwcfg->strobe_setup != NULL &&
- sensor->hwcfg->strobe_setup->trigger != 0) {
+ sensor->hwcfg.strobe_setup != NULL &&
+ sensor->hwcfg.strobe_setup->trigger != 0) {
rval = ccs_setup_flash_strobe(sensor);
if (rval)
goto out;
@@ -2844,9 +2844,9 @@ static int __maybe_unused ccs_resume(struct device *dev)
return rval;
}
-static struct ccs_hwconfig *ccs_get_hwconfig(struct device *dev)
+static int ccs_get_hwconfig(struct ccs_sensor *sensor, struct device *dev)
{
- struct ccs_hwconfig *hwcfg;
+ struct ccs_hwconfig *hwcfg = &sensor->hwcfg;
struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };
struct fwnode_handle *ep;
struct fwnode_handle *fwnode = dev_fwnode(dev);
@@ -2856,7 +2856,7 @@ static struct ccs_hwconfig *ccs_get_hwconfig(struct device *dev)
ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
if (!ep)
- return NULL;
+ return -ENODEV;
bus_cfg.bus_type = V4L2_MBUS_CSI2_DPHY;
rval = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
@@ -2868,10 +2868,6 @@ static struct ccs_hwconfig *ccs_get_hwconfig(struct device *dev)
if (rval)
goto out_err;
- hwcfg = devm_kzalloc(dev, sizeof(*hwcfg), GFP_KERNEL);
- if (!hwcfg)
- goto out_err;
-
switch (bus_cfg.bus_type) {
case V4L2_MBUS_CSI2_DPHY:
hwcfg->csi_signalling_mode = CCS_CSI_SIGNALING_MODE_CSI_2_DPHY;
@@ -2885,6 +2881,7 @@ static struct ccs_hwconfig *ccs_get_hwconfig(struct device *dev)
break;
default:
dev_err(dev, "unsupported bus %u\n", bus_cfg.bus_type);
+ rval = -EINVAL;
goto out_err;
}
@@ -2901,6 +2898,7 @@ static struct ccs_hwconfig *ccs_get_hwconfig(struct device *dev)
break;
default:
dev_err(dev, "invalid rotation %u\n", rotation);
+ rval = -EINVAL;
goto out_err;
}
}
@@ -2915,14 +2913,17 @@ static struct ccs_hwconfig *ccs_get_hwconfig(struct device *dev)
if (!bus_cfg.nr_of_link_frequencies) {
dev_warn(dev, "no link frequencies defined\n");
+ rval = -EINVAL;
goto out_err;
}
hwcfg->op_sys_clock = devm_kcalloc(
dev, bus_cfg.nr_of_link_frequencies + 1 /* guardian */,
sizeof(*hwcfg->op_sys_clock), GFP_KERNEL);
- if (!hwcfg->op_sys_clock)
+ if (!hwcfg->op_sys_clock) {
+ rval = -ENOMEM;
goto out_err;
+ }
for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++) {
hwcfg->op_sys_clock[i] = bus_cfg.link_frequencies[i];
@@ -2931,29 +2932,30 @@ static struct ccs_hwconfig *ccs_get_hwconfig(struct device *dev)
v4l2_fwnode_endpoint_free(&bus_cfg);
fwnode_handle_put(ep);
- return hwcfg;
+
+ return 0;
out_err:
v4l2_fwnode_endpoint_free(&bus_cfg);
fwnode_handle_put(ep);
- return NULL;
+
+ return rval;
}
static int ccs_probe(struct i2c_client *client)
{
struct ccs_sensor *sensor;
- struct ccs_hwconfig *hwcfg = ccs_get_hwconfig(&client->dev);
unsigned int i;
int rval;
- if (hwcfg == NULL)
- return -ENODEV;
-
sensor = devm_kzalloc(&client->dev, sizeof(*sensor), GFP_KERNEL);
if (sensor == NULL)
return -ENOMEM;
- sensor->hwcfg = hwcfg;
+ rval = ccs_get_hwconfig(sensor, &client->dev);
+ if (rval)
+ return rval;
+
sensor->src = &sensor->ssds[sensor->ssds_used];
v4l2_i2c_subdev_init(&sensor->src->sd, client, &ccs_ops);
@@ -2976,33 +2978,33 @@ static int ccs_probe(struct i2c_client *client)
}
if (sensor->ext_clk) {
- if (sensor->hwcfg->ext_clk) {
+ if (sensor->hwcfg.ext_clk) {
unsigned long rate;
rval = clk_set_rate(sensor->ext_clk,
- sensor->hwcfg->ext_clk);
+ sensor->hwcfg.ext_clk);
if (rval < 0) {
dev_err(&client->dev,
"unable to set clock freq to %u\n",
- sensor->hwcfg->ext_clk);
+ sensor->hwcfg.ext_clk);
return rval;
}
rate = clk_get_rate(sensor->ext_clk);
- if (rate != sensor->hwcfg->ext_clk) {
+ if (rate != sensor->hwcfg.ext_clk) {
dev_err(&client->dev,
"can't set clock freq, asked for %u but got %lu\n",
- sensor->hwcfg->ext_clk, rate);
+ sensor->hwcfg.ext_clk, rate);
return rval;
}
} else {
- sensor->hwcfg->ext_clk = clk_get_rate(sensor->ext_clk);
+ sensor->hwcfg.ext_clk = clk_get_rate(sensor->ext_clk);
dev_dbg(&client->dev, "obtained clock freq %u\n",
- sensor->hwcfg->ext_clk);
+ sensor->hwcfg.ext_clk);
}
- } else if (sensor->hwcfg->ext_clk) {
+ } else if (sensor->hwcfg.ext_clk) {
dev_dbg(&client->dev, "assuming clock freq %u\n",
- sensor->hwcfg->ext_clk);
+ sensor->hwcfg.ext_clk);
} else {
dev_err(&client->dev, "unable to obtain clock freq\n");
return -EINVAL;
@@ -3055,7 +3057,7 @@ static int ccs_probe(struct i2c_client *client)
*
* Rotation also changes the bayer pattern.
*/
- if (sensor->hwcfg->module_board_orient ==
+ if (sensor->hwcfg.module_board_orient ==
CCS_MODULE_BOARD_ORIENT_180)
sensor->hvflip_inv_mask =
CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR |
@@ -3127,8 +3129,8 @@ static int ccs_probe(struct i2c_client *client)
/* prepare PLL configuration input values */
sensor->pll.bus_type = SMIAPP_PLL_BUS_TYPE_CSI2;
- sensor->pll.csi2.lanes = sensor->hwcfg->lanes;
- sensor->pll.ext_clk_freq_hz = sensor->hwcfg->ext_clk;
+ sensor->pll.csi2.lanes = sensor->hwcfg.lanes;
+ sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk;
sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN);
ccs_create_subdev(sensor, sensor->scaler, " scaler", 2,
diff --git a/drivers/media/i2c/ccs/ccs-quirk.c b/drivers/media/i2c/ccs/ccs-quirk.c
index 5a24da1d7aa9..facec28f8447 100644
--- a/drivers/media/i2c/ccs/ccs-quirk.c
+++ b/drivers/media/i2c/ccs/ccs-quirk.c
@@ -152,13 +152,13 @@ static int jt8ev1_post_poweron(struct ccs_sensor *sensor)
if (rval < 0)
return rval;
- switch (sensor->hwcfg->ext_clk) {
+ switch (sensor->hwcfg.ext_clk) {
case 9600000:
return ccs_write_addr_8s(sensor, regs_96,
ARRAY_SIZE(regs_96));
default:
dev_warn(&client->dev, "no MSRs for %d Hz ext_clk\n",
- sensor->hwcfg->ext_clk);
+ sensor->hwcfg.ext_clk);
return 0;
}
}
diff --git a/drivers/media/i2c/ccs/ccs.h b/drivers/media/i2c/ccs/ccs.h
index bfe39e02f5e9..2d1e8339f663 100644
--- a/drivers/media/i2c/ccs/ccs.h
+++ b/drivers/media/i2c/ccs/ccs.h
@@ -215,7 +215,7 @@ struct ccs_sensor {
struct ccs_subdev *binner;
struct ccs_subdev *scaler;
struct ccs_subdev *pixel_array;
- struct ccs_hwconfig *hwcfg;
+ struct ccs_hwconfig hwcfg;
struct regulator *vana;
struct clk *ext_clk;
struct gpio_desc *xshutdown;
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 032/106] ccs: Fix obtaining bus information from firmware
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (22 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 031/106] ccs: Make hwcfg part of the device specific struct Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 033/106] ccs: Add CCS static data parser library Sakari Ailus
` (72 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
Let v4l2_fwnode_endpoint_alloc_parse to figure out the type of the data
bus. As the old bindings did not require the "bus-type" property, we need
to rely on guessing between CSI-2 D-PHY and CCP2. Setting the type to
CSI-2 D-PHY will parse just that and succeed even if no data-lanes are
set.
Also add a comment on the matter to the driver to avoid breaking this in
the future.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 811f738f23aa..19ff15eda246 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -2847,7 +2847,7 @@ static int __maybe_unused ccs_resume(struct device *dev)
static int ccs_get_hwconfig(struct ccs_sensor *sensor, struct device *dev)
{
struct ccs_hwconfig *hwcfg = &sensor->hwcfg;
- struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };
+ struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = V4L2_MBUS_UNKNOWN };
struct fwnode_handle *ep;
struct fwnode_handle *fwnode = dev_fwnode(dev);
u32 rotation;
@@ -2858,13 +2858,11 @@ static int ccs_get_hwconfig(struct ccs_sensor *sensor, struct device *dev)
if (!ep)
return -ENODEV;
- bus_cfg.bus_type = V4L2_MBUS_CSI2_DPHY;
+ /*
+ * Note that we do need to rely on detecting the bus type between CSI-2
+ * D-PHY and CCP2 as the old bindings did not require it.
+ */
rval = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
- if (rval == -ENXIO) {
- bus_cfg = (struct v4l2_fwnode_endpoint)
- { .bus_type = V4L2_MBUS_CCP2 };
- rval = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
- }
if (rval)
goto out_err;
@@ -2873,6 +2871,7 @@ static int ccs_get_hwconfig(struct ccs_sensor *sensor, struct device *dev)
hwcfg->csi_signalling_mode = CCS_CSI_SIGNALING_MODE_CSI_2_DPHY;
hwcfg->lanes = bus_cfg.bus.mipi_csi2.num_data_lanes;
break;
+ case V4L2_MBUS_CSI1:
case V4L2_MBUS_CCP2:
hwcfg->csi_signalling_mode = (bus_cfg.bus.mipi_csi1.strobe) ?
SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_STROBE :
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 033/106] ccs: Add CCS static data parser library
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (23 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 032/106] ccs: Fix obtaining bus information from firmware Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-11-05 10:50 ` Mauro Carvalho Chehab
2020-10-07 8:44 ` [PATCH v2 034/106] ccs: Combine revision number major and minor into one Sakari Ailus
` (71 subsequent siblings)
96 siblings, 1 reply; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
Add a parser library for parsing the CCS static data format.
The library may be also compiled in user space as the format has uses also
in the user space. Therefore it is dual licensed under the 3-clause BSD
license as well.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/Makefile | 2 +-
drivers/media/i2c/ccs/ccs-data-defs.h | 215 ++++++
drivers/media/i2c/ccs/ccs-data.c | 949 ++++++++++++++++++++++++++
drivers/media/i2c/ccs/ccs-data.h | 116 ++++
4 files changed, 1281 insertions(+), 1 deletion(-)
create mode 100644 drivers/media/i2c/ccs/ccs-data-defs.h
create mode 100644 drivers/media/i2c/ccs/ccs-data.c
create mode 100644 drivers/media/i2c/ccs/ccs-data.h
diff --git a/drivers/media/i2c/ccs/Makefile b/drivers/media/i2c/ccs/Makefile
index 0f3d11b86dad..2f97b22460f1 100644
--- a/drivers/media/i2c/ccs/Makefile
+++ b/drivers/media/i2c/ccs/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
ccs-objs += ccs-core.o ccs-reg-access.o \
- ccs-quirk.o ccs-limits.o
+ ccs-quirk.o ccs-limits.o ccs-data.o
obj-$(CONFIG_VIDEO_CCS) += ccs.o
ccflags-y += -I $(srctree)/drivers/media/i2c
diff --git a/drivers/media/i2c/ccs/ccs-data-defs.h b/drivers/media/i2c/ccs/ccs-data-defs.h
new file mode 100644
index 000000000000..ffc5154d2c66
--- /dev/null
+++ b/drivers/media/i2c/ccs/ccs-data-defs.h
@@ -0,0 +1,215 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
+/* Copyright 2019--2020 Intel Corporation */
+
+#ifndef __CCS_DATA_DEFS_H__
+#define __CCS_DATA_DEFS_H__
+
+#include "ccs-data.h"
+
+#define CCS_STATIC_DATA_VERSION 0
+
+enum __ccs_data_length_specifier_id {
+ CCS_DATA_LENGTH_SPECIFIER_1 = 0,
+ CCS_DATA_LENGTH_SPECIFIER_2 = 1,
+ CCS_DATA_LENGTH_SPECIFIER_3 = 2
+};
+#define CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT 6
+
+struct __ccs_data_length_specifier {
+ uint8_t length;
+} __attribute__((packed));
+
+struct __ccs_data_length_specifier2 {
+ uint8_t length[2];
+} __attribute__((packed));
+
+struct __ccs_data_length_specifier3 {
+ uint8_t length[3];
+} __attribute__((packed));
+
+struct __ccs_data_block {
+ uint8_t id;
+ struct __ccs_data_length_specifier length;
+} __attribute__((packed));
+
+#define CCS_DATA_BLOCK_HEADER_ID_VERSION_SHIFT 5
+
+struct __ccs_data_block3 {
+ uint8_t id;
+ struct __ccs_data_length_specifier2 length;
+} __attribute__((packed));
+
+struct __ccs_data_block4 {
+ uint8_t id;
+ struct __ccs_data_length_specifier3 length;
+} __attribute__((packed));
+
+enum __ccs_data_block_id {
+ CCS_DATA_BLOCK_ID_DUMMY = 1,
+ CCS_DATA_BLOCK_ID_DATA_VERSION = 2,
+ CCS_DATA_BLOCK_ID_SENSOR_READ_ONLY_REGS = 3,
+ CCS_DATA_BLOCK_ID_MODULE_READ_ONLY_REGS = 4,
+ CCS_DATA_BLOCK_ID_SENSOR_MANUFACTURER_REGS = 5,
+ CCS_DATA_BLOCK_ID_MODULE_MANUFACTURER_REGS = 6,
+ CCS_DATA_BLOCK_ID_SENSOR_RULE_BASED_BLOCK = 32,
+ CCS_DATA_BLOCK_ID_MODULE_RULE_BASED_BLOCK = 33,
+ CCS_DATA_BLOCK_ID_SENSOR_PDAF_PIXEL_LOCATION = 36,
+ CCS_DATA_BLOCK_ID_MODULE_PDAF_PIXEL_LOCATION = 37,
+ CCS_DATA_BLOCK_ID_LICENSE = 40,
+ CCS_DATA_BLOCK_ID_END = 127,
+};
+
+struct __ccs_data_block_version {
+ uint8_t static_data_version_major[2];
+ uint8_t static_data_version_minor[2];
+ uint8_t year[2];
+ uint8_t month;
+ uint8_t day;
+} __attribute__((packed));
+
+struct __ccs_data_block_regs {
+ uint8_t reg_len;
+} __attribute__((packed));
+
+#define CCS_DATA_BLOCK_REGS_ADDR_MASK 0x07
+#define CCS_DATA_BLOCK_REGS_LEN_SHIFT 3
+#define CCS_DATA_BLOCK_REGS_LEN_MASK 0x38
+#define CCS_DATA_BLOCK_REGS_SEL_SHIFT 6
+enum ccs_data_block_regs_sel {
+ CCS_DATA_BLOCK_REGS_SEL_REGS = 0,
+ CCS_DATA_BLOCK_REGS_SEL_REGS2 = 1,
+ CCS_DATA_BLOCK_REGS_SEL_REGS3 = 2,
+};
+
+struct __ccs_data_block_regs2 {
+ uint8_t reg_len;
+ uint8_t addr;
+} __attribute__((packed));
+
+#define CCS_DATA_BLOCK_REGS_2_ADDR_MASK 0x01
+#define CCS_DATA_BLOCK_REGS_2_LEN_SHIFT 1
+#define CCS_DATA_BLOCK_REGS_2_LEN_MASK 0x3e
+
+struct __ccs_data_block_regs3 {
+ uint8_t reg_len;
+ uint8_t addr[2];
+} __attribute__((packed));
+
+#define CCS_DATA_BLOCK_REGS_3_LEN_MASK 0x3f
+
+enum __ccs_data_ffd_pixelcode {
+ CCS_DATA_BLOCK_FFD_PIXELCODE_EMBEDDED = 1,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_DUMMY = 2,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_BLACK = 3,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_DARK = 4,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_VISIBLE = 5,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_MS_0 = 8,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_MS_1 = 9,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_MS_2 = 10,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_MS_3 = 11,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_MS_4 = 12,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_MS_5 = 13,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_MS_6 = 14,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_OB = 16,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_OB = 17,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_LEFT_OB = 18,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_RIGHT_OB = 19,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_LEFT_OB = 20,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_RIGHT_OB = 21,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_LEFT_OB = 22,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_RIGHT_OB = 23,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_TOTAL = 24,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_PDAF = 32,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_PDAF = 33,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_LEFT_PDAF = 34,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_RIGHT_PDAF = 35,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_LEFT_PDAF = 36,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_RIGHT_PDAF = 37,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_LEFT_PDAF = 38,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_RIGHT_PDAF = 39,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_SEPARATED_PDAF = 40,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_ORIGINAL_ORDER_PDAF = 41,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_VENDOR_PDAF = 41,
+};
+
+struct __ccs_data_block_ffd_entry {
+ uint8_t pixelcode;
+ uint8_t reserved;
+ uint8_t value[2];
+} __attribute__((packed));
+
+struct __ccs_data_block_ffd {
+ uint8_t num_column_descs;
+ uint8_t num_row_descs;
+} __attribute__((packed));
+
+enum __ccs_data_block_rule_id {
+ CCS_DATA_BLOCK_RULE_ID_IF = 1,
+ CCS_DATA_BLOCK_RULE_ID_READ_ONLY_REGS = 2,
+ CCS_DATA_BLOCK_RULE_ID_FFD = 3,
+ CCS_DATA_BLOCK_RULE_ID_MSR = 4,
+ CCS_DATA_BLOCK_RULE_ID_PDAF_READOUT = 5,
+};
+
+struct __ccs_data_block_rule_if {
+ uint8_t addr[2];
+ uint8_t value;
+ uint8_t mask;
+} __attribute__((packed));
+
+enum __ccs_data_block_pdaf_readout_order{
+ CCS_DATA_BLOCK_PDAF_READOUT_ORDER_ORIGINAL = 1,
+ CCS_DATA_BLOCK_PDAF_READOUT_ORDER_SEPARATE_WITHIN_LINE = 2,
+ CCS_DATA_BLOCK_PDAF_READOUT_ORDER_SEPARATE_TYPES_SEPARATE_LINES = 3,
+};
+
+struct __ccs_data_block_pdaf_readout {
+ uint8_t pdaf_readout_info_reserved;
+ uint8_t pdaf_readout_info_order;
+} __attribute__((packed));
+
+struct __ccs_data_block_pdaf_pix_loc_block_desc {
+ uint8_t block_type_id;
+ uint8_t repeat_x[2];
+} __attribute__((packed));
+
+struct __ccs_data_block_pdaf_pix_loc_block_desc_group {
+ uint8_t num_block_descs[2];
+ uint8_t repeat_y;
+} __attribute__((packed));
+
+enum __ccs_data_block_pdaf_pix_loc_pixel_type {
+ CCS_DATA_PDAF_PIXEL_TYPE_LEFT_SEPARATED = 0,
+ CCS_DATA_PDAF_PIXEL_TYPE_RIGHT_SEPARATED = 1,
+ CCS_DATA_PDAF_PIXEL_TYPE_TOP_SEPARATED = 2,
+ CCS_DATA_PDAF_PIXEL_TYPE_BOTTOM_SEPARATED = 3,
+ CCS_DATA_PDAF_PIXEL_TYPE_LEFT_SIDE_BY_SIDE = 4,
+ CCS_DATA_PDAF_PIXEL_TYPE_RIGHT_SIDE_BY_SIDE = 5,
+ CCS_DATA_PDAF_PIXEL_TYPE_TOP_SIDE_BY_SIDE = 6,
+ CCS_DATA_PDAF_PIXEL_TYPE_BOTTOM_SIDE_BY_SIDE = 7,
+ CCS_DATA_PDAF_PIXEL_TYPE_TOP_LEFT = 8,
+ CCS_DATA_PDAF_PIXEL_TYPE_TOP_RIGHT = 9,
+ CCS_DATA_PDAF_PIXEL_TYPE_BOTTOM_LEFT = 10,
+ CCS_DATA_PDAF_PIXEL_TYPE_BOTTOM_RIGHT = 11,
+};
+
+struct __ccs_data_block_pdaf_pix_loc_pixel_desc {
+ uint8_t pixel_type;
+ uint8_t small_offset_x;
+ uint8_t small_offset_y;
+} __attribute__((packed));
+
+struct __ccs_data_block_pdaf_pix_loc {
+ uint8_t main_offset_x[2];
+ uint8_t main_offset_y[2];
+ uint8_t global_pdaf_type;
+ uint8_t block_width;
+ uint8_t block_height;
+ uint8_t num_block_desc_groups[2];
+} __attribute__((packed));
+
+struct __ccs_data_block_end {
+ uint8_t crc[4];
+} __attribute__((packed));
+
+#endif /* __CCS_DATA_DEFS_H__ */
diff --git a/drivers/media/i2c/ccs/ccs-data.c b/drivers/media/i2c/ccs/ccs-data.c
new file mode 100644
index 000000000000..16aeeee45936
--- /dev/null
+++ b/drivers/media/i2c/ccs/ccs-data.c
@@ -0,0 +1,949 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/* Copyright 2019--2020 Intel Corporation */
+
+#include "ccs-os.h"
+
+#include "ccs-data-defs.h"
+
+struct bin_container {
+ void *base;
+ void *now;
+ void *end;
+ size_t size;
+};
+
+static uint32_t u8_arr_to_u32(const uint8_t *arr, unsigned int size)
+{
+ unsigned int i;
+ uint32_t value = arr[0];
+
+ for (i = 1; i < size; i++) {
+ value <<= 8;
+ value += arr[i];
+ }
+
+ return value;
+}
+
+static void *bin_alloc(struct bin_container *bin, size_t len)
+{
+ void *ptr;
+
+ len = align2(len, 8);
+
+ if (bin->end - bin->now < len)
+ return NULL;
+
+ ptr = bin->now;
+ bin->now += len;
+
+ return ptr;
+}
+
+static void bin_reserve(struct bin_container *bin, size_t len)
+{
+ bin->size += align2(len, 8);
+}
+
+static int bin_backing_alloc(struct bin_container *bin)
+{
+ bin->base = bin->now = os_calloc(bin->size);
+ if (!bin->base)
+ return -ENOMEM;
+
+ bin->end = bin->base + bin->size;
+
+ return 0;
+}
+
+#define is_contained(var, endp) \
+ (sizeof(*var) <= (endp) - (void *)(var))
+#define has_headroom(ptr, headroom, endp) \
+ ((headroom) <= (endp) - (void *)(ptr))
+#define is_contained_with_headroom(var, headroom, endp) \
+ (sizeof(*var) + (headroom) <= (endp) - (void *)(var))
+
+static int
+ccs_data_parse_length_specifier(const struct __ccs_data_length_specifier *__len,
+ size_t *__hlen, size_t *__plen,
+ const void *endp)
+{
+ size_t hlen, plen;
+
+ if (!is_contained(__len, endp))
+ return -ENODATA;
+
+ switch (__len->length >> CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT) {
+ case CCS_DATA_LENGTH_SPECIFIER_1:
+ hlen = sizeof(*__len);
+ plen = __len->length &
+ ((1 << CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT) - 1);
+ break;
+ case CCS_DATA_LENGTH_SPECIFIER_2: {
+ struct __ccs_data_length_specifier2 *__len2 = (void *)__len;
+
+ if (!is_contained(__len2, endp))
+ return -ENODATA;
+
+ hlen = sizeof(*__len2);
+ plen = ((size_t)
+ (__len2->length[0] &
+ ((1 << CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT) - 1))
+ << 8) + __len2->length[1];
+ break;
+ }
+ case CCS_DATA_LENGTH_SPECIFIER_3: {
+ struct __ccs_data_length_specifier3 *__len3 = (void *)__len;
+
+ if (!is_contained(__len3, endp))
+ return -ENODATA;
+
+ hlen = sizeof(*__len3);
+ plen = ((size_t)
+ (__len3->length[0] &
+ ((1 << CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT) - 1))
+ << 16) + u8_arr_to_u32(&__len3->length[1],
+ sizeof(__len3->length) - 1);
+ break;
+ }
+ default:
+ return -EINVAL;
+ }
+
+ if (!has_headroom(__len, hlen + plen, endp))
+ return -ENODATA;
+
+ *__hlen = hlen;
+ *__plen = plen;
+
+ return 0;
+}
+
+static uint8_t
+ccs_data_parse_format_version(const struct __ccs_data_block *block)
+{
+ return block->id >> CCS_DATA_BLOCK_HEADER_ID_VERSION_SHIFT;
+}
+
+static uint8_t ccs_data_parse_block_id(const struct __ccs_data_block *block,
+ bool is_first)
+{
+ if (!is_first)
+ return block->id;
+
+ return block->id & ((1 << CCS_DATA_BLOCK_HEADER_ID_VERSION_SHIFT) - 1);
+}
+
+static int ccs_data_parse_version(struct bin_container *bin,
+ struct ccs_data_container *ccsdata,
+ const void *payload, const void *endp)
+{
+ const struct __ccs_data_block_version *v = payload;
+ struct ccs_data_block_version *vv;
+
+ if (v + 1 != endp)
+ return -ENODATA;
+
+ if (!bin->base) {
+ bin_reserve(bin, sizeof(*ccsdata->version));
+ return 0;
+ }
+
+ ccsdata->version = bin_alloc(bin, sizeof(*ccsdata->version));
+ if (!ccsdata->version)
+ return -ENOMEM;
+
+ vv = ccsdata->version;
+ vv->version_major = u8_arr_to_u32(v->static_data_version_major, 2);
+ vv->version_minor = u8_arr_to_u32(v->static_data_version_minor, 2);
+ vv->date_year = u8_arr_to_u32(v->year, 2);
+ vv->date_month = v->month;
+ vv->date_day = v->day;
+
+ return 0;
+}
+
+static void print_ccs_data_version(printf_ctx fh,
+ struct ccs_data_block_version *v)
+{
+ os_printf(fh,
+ "static data version %4.4x.%4.4x, date %4.4u-%2.2u-%2.2u\n",
+ v->version_major, v->version_minor,
+ v->date_year, v->date_month, v->date_day);
+}
+
+static int ccs_data_block_parse_header(const struct __ccs_data_block *block,
+ bool is_first, unsigned int *__block_id,
+ const void **payload,
+ const struct __ccs_data_block **next_block,
+ const void *endp, printf_ctx fh,
+ bool verbose)
+{
+ size_t plen, hlen;
+ uint8_t block_id;
+ int rval;
+
+ if (!is_contained(block, endp))
+ return -ENODATA;
+
+ rval = ccs_data_parse_length_specifier(&block->length, &hlen, &plen,
+ endp);
+ if (rval < 0)
+ return rval;
+
+ block_id = ccs_data_parse_block_id(block, is_first);
+
+ if (verbose)
+ os_printf(fh,
+ "Block ID 0x%2.2x, header length %zu, payload length %zu\n",
+ block_id, hlen, plen);
+
+ if (!has_headroom(&block->length, hlen + plen, endp))
+ return -ENODATA;
+
+ if (__block_id)
+ *__block_id = block_id;
+
+ if (payload)
+ *payload = (void *)&block->length + hlen;
+
+ if (next_block)
+ *next_block = (void *)&block->length + hlen + plen;
+
+ return 0;
+}
+
+static int ccs_data_parse_regs(struct bin_container *bin,
+ struct ccs_reg **__regs,
+ size_t *__num_regs, const void *payload,
+ const void *endp, printf_ctx fh)
+{
+ struct ccs_reg *regs_base, *regs;
+ size_t num_regs = 0;
+ uint16_t addr = 0;
+
+ if (bin->base && __regs) {
+ regs = regs_base = bin_alloc(bin, sizeof(*regs) * *__num_regs);
+ if (!regs)
+ return -ENOMEM;
+ }
+
+ while (payload < endp && num_regs < INT_MAX) {
+ const struct __ccs_data_block_regs *r = payload;
+ size_t len;
+ const void *data;
+
+ if (!is_contained(r, endp))
+ return -ENODATA;
+
+ switch (r->reg_len >> CCS_DATA_BLOCK_REGS_SEL_SHIFT) {
+ case CCS_DATA_BLOCK_REGS_SEL_REGS:
+ addr += r->reg_len & CCS_DATA_BLOCK_REGS_ADDR_MASK;
+ len = ((r->reg_len & CCS_DATA_BLOCK_REGS_LEN_MASK)
+ >> CCS_DATA_BLOCK_REGS_LEN_SHIFT) + 1;
+
+ if (!is_contained_with_headroom(r, len, endp))
+ return -ENODATA;
+
+ data = r + 1;
+ break;
+ case CCS_DATA_BLOCK_REGS_SEL_REGS2: {
+ const struct __ccs_data_block_regs2 *r2 = payload;
+
+ if (!is_contained(r2, endp))
+ return -ENODATA;
+
+ addr += ((uint16_t)(r2->reg_len &
+ CCS_DATA_BLOCK_REGS_2_ADDR_MASK) << 8)
+ + r2->addr;
+ len = ((r2->reg_len & CCS_DATA_BLOCK_REGS_2_LEN_MASK)
+ >> CCS_DATA_BLOCK_REGS_2_LEN_SHIFT) + 1;
+
+ if (!is_contained_with_headroom(r2, len, endp))
+ return -ENODATA;
+
+ data = r2 + 1;
+ break;
+ }
+ case CCS_DATA_BLOCK_REGS_SEL_REGS3: {
+ const struct __ccs_data_block_regs3 *r3 = payload;
+
+ if (!is_contained(r3, endp))
+ return -ENODATA;
+
+ addr = u8_arr_to_u32(r3->addr, sizeof(r3->addr));
+ len = (r3->reg_len & CCS_DATA_BLOCK_REGS_3_LEN_MASK) + 1;
+
+ if (!is_contained_with_headroom(r3, len, endp))
+ return -ENODATA;
+
+ data = r3 + 1;
+ break;
+ }
+ default:
+ return -EINVAL;
+ }
+
+ num_regs++;
+
+ if (!bin->base) {
+ bin_reserve(bin, len);
+ } else if (__regs) {
+ regs->addr = addr;
+ regs->len = len;
+ regs->value = bin_alloc(bin, len);
+ if (!regs->value)
+ return -ENOMEM;
+
+ memcpy(regs->value, data, len);
+ regs++;
+ }
+
+ addr += len;
+ payload = data + len;
+ }
+
+ if (!bin->base)
+ bin_reserve(bin, sizeof(*regs) * num_regs);
+
+ if (__num_regs)
+ *__num_regs = num_regs;
+
+ if (bin->base && __regs)
+ *__regs = regs_base;
+
+ return 0;
+}
+
+static int ccs_data_parse_reg_rules(struct bin_container *bin,
+ struct ccs_reg **__regs,
+ size_t *__num_regs,
+ const void *payload,
+ const void *endp, printf_ctx fh)
+{
+ int rval;
+
+ if (!bin->base)
+ return ccs_data_parse_regs(bin, NULL, NULL, payload, endp, fh);
+
+ rval = ccs_data_parse_regs(bin, NULL, __num_regs, payload, endp, fh);
+ if (rval)
+ return rval;
+
+ return ccs_data_parse_regs(bin, __regs, __num_regs, payload, endp,
+ fh);
+}
+
+static void assign_ffd_entry(struct ccs_frame_format_desc *desc,
+ const struct __ccs_data_block_ffd_entry *ent)
+{
+ desc->pixelcode = ent->pixelcode;
+ desc->value = u8_arr_to_u32(ent->value, sizeof(ent->value));
+}
+
+static int ccs_data_parse_ffd(struct bin_container *bin,
+ struct ccs_frame_format_descs **ffd,
+ const void *payload,
+ const void *endp, printf_ctx fh)
+{
+ const struct __ccs_data_block_ffd *__ffd = payload;
+ const struct __ccs_data_block_ffd_entry *__entry;
+ unsigned int i;
+
+ if (!is_contained(__ffd, endp))
+ return -ENODATA;
+
+ if ((void *)__ffd + sizeof(*__ffd) +
+ ((uint32_t)__ffd->num_column_descs +
+ (uint32_t)__ffd->num_row_descs) *
+ sizeof(struct __ccs_data_block_ffd_entry) != endp)
+ return -ENODATA;
+
+ if (!bin->base) {
+ bin_reserve(bin, sizeof(**ffd));
+ bin_reserve(bin, __ffd->num_column_descs *
+ sizeof(struct ccs_frame_format_desc));
+ bin_reserve(bin, __ffd->num_row_descs *
+ sizeof(struct ccs_frame_format_desc));
+
+ return 0;
+ }
+
+ *ffd = bin_alloc(bin, sizeof(**ffd));
+ if (!*ffd)
+ return -ENOMEM;
+
+ (*ffd)->num_column_descs = __ffd->num_column_descs;
+ (*ffd)->num_row_descs = __ffd->num_row_descs;
+ __entry = (void *)(__ffd + 1);
+
+ (*ffd)->column_descs = bin_alloc(bin, __ffd->num_column_descs *
+ sizeof(*(*ffd)->column_descs));
+ if (!(*ffd)->column_descs)
+ return -ENOMEM;
+
+ for (i = 0; i < __ffd->num_column_descs; i++, __entry++)
+ assign_ffd_entry(&(*ffd)->column_descs[i], __entry);
+
+ (*ffd)->row_descs = bin_alloc(bin, __ffd->num_row_descs *
+ sizeof(*(*ffd)->row_descs));
+ if (!(*ffd)->row_descs)
+ return -ENOMEM;
+
+ for (i = 0; i < __ffd->num_row_descs; i++, __entry++)
+ assign_ffd_entry(&(*ffd)->row_descs[i], __entry);
+
+ if (__entry != endp)
+ return -EPROTO;
+
+ return 0;
+}
+
+static int ccs_data_parse_pdaf_readout(struct bin_container *bin,
+ struct ccs_pdaf_readout **pdaf_readout,
+ const void *payload,
+ const void *endp, printf_ctx fh)
+{
+ const struct __ccs_data_block_pdaf_readout *__pdaf = payload;
+
+ if (!is_contained(__pdaf, endp))
+ return -ENODATA;
+
+ if (!bin->base) {
+ bin_reserve(bin, sizeof(**pdaf_readout));
+ } else {
+ *pdaf_readout = bin_alloc(bin, sizeof(**pdaf_readout));
+ if (!*pdaf_readout)
+ return -ENOMEM;
+
+ (*pdaf_readout)->pdaf_readout_info_order =
+ __pdaf->pdaf_readout_info_order;
+ }
+
+ return ccs_data_parse_ffd(bin, !bin->base ? NULL : &(*pdaf_readout)->ffd,
+ __pdaf + 1, endp, fh);
+}
+
+static int ccs_data_parse_rules(struct bin_container *bin,
+ struct ccs_rule **__rules,
+ size_t *__num_rules, const void *payload,
+ const void *endp, printf_ctx fh)
+{
+ struct ccs_rule *rules_base, *rules = NULL, *next_rule;
+ size_t num_rules = 0;
+ const void *__next_rule = payload;
+ int rval;
+
+ if (bin->base) {
+ rules_base = next_rule =
+ bin_alloc(bin, sizeof(*rules) * *__num_rules);
+ if (!rules_base)
+ return -ENOMEM;
+ }
+
+ while (__next_rule < endp) {
+ size_t rule_hlen, rule_plen, rule_plen2;
+ const uint8_t *__rule_type;
+ const void *rule_payload;
+
+ /* Size of a single rule */
+ rval = ccs_data_parse_length_specifier(__next_rule, &rule_hlen,
+ &rule_plen, endp);
+
+ if (rval < 0)
+ return rval;
+
+ __rule_type = __next_rule + rule_hlen;
+
+ if (!is_contained(__rule_type, endp))
+ return -ENODATA;
+
+ rule_payload = __rule_type + 1;
+ rule_plen2 = rule_plen - sizeof(*__rule_type);
+
+ switch (*__rule_type) {
+ case CCS_DATA_BLOCK_RULE_ID_IF: {
+ const struct __ccs_data_block_rule_if *__if_rules =
+ rule_payload;
+ const size_t __num_if_rules =
+ rule_plen2 / sizeof(*__if_rules);
+ struct ccs_if_rule *if_rule;
+
+ if (!has_headroom(__if_rules,
+ sizeof(*__if_rules) * __num_if_rules,
+ rule_payload + rule_plen2))
+ return -ENODATA;
+
+ /* Also check there is no extra data */
+ if (__if_rules + __num_if_rules !=
+ rule_payload + rule_plen2)
+ return -EINVAL;
+
+ if (!bin->base) {
+ bin_reserve(bin,
+ sizeof(*if_rule) *
+ __num_if_rules);
+ num_rules++;
+ } else {
+ unsigned int i;
+
+ rules = next_rule;
+ next_rule++;
+
+ if_rule = bin_alloc(bin,
+ sizeof(*if_rule) *
+ __num_if_rules);
+ if (!if_rule)
+ return -ENOMEM;
+
+ for (i = 0; i < __num_if_rules; i++) {
+ if_rule[i].addr =
+ u8_arr_to_u32(
+ __if_rules[i].addr,
+ sizeof(__if_rules[i].
+ addr));
+ if_rule[i].value = __if_rules[i].value;
+ if_rule[i].mask = __if_rules[i].mask;
+ }
+
+ rules->if_rules = if_rule;
+ rules->num_if_rules = __num_if_rules;
+ }
+ break;
+ }
+ case CCS_DATA_BLOCK_RULE_ID_READ_ONLY_REGS:
+ rval = ccs_data_parse_reg_rules(bin, &rules->read_only_regs,
+ &rules->num_read_only_regs,
+ rule_payload,
+ rule_payload + rule_plen2,
+ fh);
+ if (rval)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_RULE_ID_FFD:
+ rval = ccs_data_parse_ffd(bin, &rules->frame_format,
+ rule_payload,
+ rule_payload + rule_plen2,
+ fh);
+ if (rval)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_RULE_ID_MSR:
+ rval = ccs_data_parse_reg_rules(bin,
+ &rules->manufacturer_regs,
+ &rules->num_manufacturer_regs,
+ rule_payload,
+ rule_payload + rule_plen2,
+ fh);
+ if (rval)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_RULE_ID_PDAF_READOUT:
+ rval = ccs_data_parse_pdaf_readout(bin,
+ &rules->pdaf_readout,
+ rule_payload,
+ rule_payload + rule_plen2,
+ fh);
+ if (rval)
+ return rval;
+ break;
+ default:
+ os_printf(fh,
+ "Don't know how to handle rule type %u!\n",
+ *__rule_type);
+ return -EINVAL;
+ }
+ __next_rule = __next_rule + rule_hlen + rule_plen;
+ }
+
+ if (!bin->base) {
+ bin_reserve(bin, sizeof(*rules) * num_rules);
+ *__num_rules = num_rules;
+ } else {
+ *__rules = rules_base;
+ }
+
+ return 0;
+}
+
+static int ccs_data_parse_pdaf(struct bin_container *bin, struct ccs_pdaf_pix_loc **pdaf,
+ const void *payload, const void *endp,
+ printf_ctx fh)
+{
+ const struct __ccs_data_block_pdaf_pix_loc *__pdaf = payload;
+ const struct __ccs_data_block_pdaf_pix_loc_block_desc_group *__bdesc_group;
+ const struct __ccs_data_block_pdaf_pix_loc_pixel_desc *__pixel_desc;
+ unsigned int i;
+ uint16_t num_block_desc_groups;
+ uint8_t max_block_type_id = 0;
+ const uint8_t *__num_pixel_descs;
+
+ if (!is_contained(__pdaf, endp))
+ return -ENODATA;
+
+ if (bin->base) {
+ *pdaf = bin_alloc(bin, sizeof(**pdaf));
+ if (!*pdaf)
+ return -ENOMEM;
+ } else {
+ bin_reserve(bin, sizeof(**pdaf));
+ }
+
+ num_block_desc_groups =
+ u8_arr_to_u32(__pdaf->num_block_desc_groups,
+ sizeof(__pdaf->num_block_desc_groups));
+
+ if (bin->base) {
+ (*pdaf)->main_offset_x =
+ u8_arr_to_u32(__pdaf->main_offset_x,
+ sizeof(__pdaf->main_offset_x));
+ (*pdaf)->main_offset_y =
+ u8_arr_to_u32(__pdaf->main_offset_y,
+ sizeof(__pdaf->main_offset_y));
+ (*pdaf)->global_pdaf_type = __pdaf->global_pdaf_type;
+ (*pdaf)->block_width = __pdaf->block_width;
+ (*pdaf)->block_height = __pdaf->block_height;
+ (*pdaf)->num_block_desc_groups = num_block_desc_groups;
+ }
+
+ __bdesc_group = (const void *)(__pdaf + 1);
+
+ if (bin->base) {
+ (*pdaf)->block_desc_groups =
+ bin_alloc(bin,
+ sizeof(struct ccs_pdaf_pix_loc_block_desc_group) *
+ num_block_desc_groups);
+ if (!(*pdaf)->block_desc_groups)
+ return -ENOMEM;
+ } else {
+ bin_reserve(bin, sizeof(struct ccs_pdaf_pix_loc_block_desc_group) *
+ num_block_desc_groups);
+ }
+
+ for (i = 0; i < num_block_desc_groups; i++) {
+ const struct __ccs_data_block_pdaf_pix_loc_block_desc *__bdesc;
+ uint16_t num_block_descs;
+ unsigned int j;
+
+ if (!is_contained(__bdesc_group, endp))
+ return -ENODATA;
+
+ num_block_descs =
+ u8_arr_to_u32(__bdesc_group->num_block_descs,
+ sizeof(__bdesc_group->num_block_descs));
+
+ if (bin->base) {
+ (*pdaf)->block_desc_groups[i].repeat_y =
+ __bdesc_group->repeat_y;
+ (*pdaf)->block_desc_groups[i].num_block_descs =
+ num_block_descs;
+ }
+
+ __bdesc = (const void *)(__bdesc_group + 1);
+
+ if (bin->base) {
+ (*pdaf)->block_desc_groups[i].block_descs =
+ bin_alloc(bin,
+ sizeof(struct ccs_pdaf_pix_loc_block_desc) *
+ num_block_descs);
+ if (!(*pdaf)->block_desc_groups[i].block_descs)
+ return -ENOMEM;
+ } else {
+ bin_reserve(bin, sizeof(struct ccs_pdaf_pix_loc_block_desc) *
+ num_block_descs);
+ }
+
+ for (j = 0; j < num_block_descs; j++, __bdesc++) {
+ struct ccs_pdaf_pix_loc_block_desc *bdesc;
+
+ if (!is_contained(__bdesc, endp))
+ return -ENODATA;
+
+ if (max_block_type_id <= __bdesc->block_type_id)
+ max_block_type_id = __bdesc->block_type_id + 1;
+
+ if (!bin->base)
+ continue;
+
+ bdesc = &(*pdaf)->block_desc_groups[i].block_descs[j];
+
+ bdesc->repeat_x = u8_arr_to_u32(
+ __bdesc->repeat_x,
+ sizeof(__bdesc->repeat_x));
+
+ if (__bdesc->block_type_id >= num_block_descs)
+ return -EINVAL;
+
+ bdesc->block_type_id = __bdesc->block_type_id;
+ }
+
+ __bdesc_group = (const void *)__bdesc;
+ }
+
+ __num_pixel_descs = (const void *)__bdesc_group;
+
+ if (bin->base) {
+ (*pdaf)->pixel_desc_groups =
+ bin_alloc(bin,
+ sizeof(struct ccs_pdaf_pix_loc_pixel_desc_group) *
+ max_block_type_id);
+ if (!(*pdaf)->pixel_desc_groups)
+ return -ENOMEM;
+ (*pdaf)->num_pixel_desc_grups = max_block_type_id;
+ } else {
+ bin_reserve(bin, sizeof(struct ccs_pdaf_pix_loc_pixel_desc_group) *
+ max_block_type_id);
+ }
+
+ for (i = 0; i < max_block_type_id; i++) {
+ struct ccs_pdaf_pix_loc_pixel_desc_group *pdgroup;
+ unsigned int j;
+
+ if (!is_contained(__num_pixel_descs, endp))
+ return -ENODATA;
+
+ if (bin->base) {
+ pdgroup = &(*pdaf)->pixel_desc_groups[i];
+ pdgroup->descs =
+ bin_alloc(bin,
+ sizeof(struct ccs_pdaf_pix_loc_pixel_desc) *
+ *__num_pixel_descs);
+ if (!pdgroup->descs)
+ return -ENOMEM;
+ pdgroup->num_descs = *__num_pixel_descs;
+ } else {
+ bin_reserve(bin, sizeof(struct ccs_pdaf_pix_loc_pixel_desc) *
+ *__num_pixel_descs);
+ }
+
+ __pixel_desc = (const void *)(__num_pixel_descs + 1);
+
+ for (j = 0; j < *__num_pixel_descs; j++, __pixel_desc++) {
+ struct ccs_pdaf_pix_loc_pixel_desc *pdesc;
+
+ if (!is_contained(__pixel_desc, endp))
+ return -ENODATA;
+
+ if (!bin->base)
+ continue;
+
+ pdesc = &pdgroup->descs[j];
+ pdesc->pixel_type = __pixel_desc->pixel_type;
+ pdesc->small_offset_x = __pixel_desc->small_offset_x;
+ pdesc->small_offset_y = __pixel_desc->small_offset_y;
+ }
+
+ __num_pixel_descs = (const void *)(__pixel_desc + 1);
+ }
+
+ return 0;
+}
+
+static int ccs_data_parse_license(struct bin_container *bin,
+ char **__license,
+ size_t *__license_length,
+ const void *payload, const void *endp)
+{
+ size_t size = endp - payload;
+ char *license;
+
+ if (!bin->base) {
+ bin_reserve(bin, size);
+ return 0;
+ }
+
+ license = bin_alloc(bin, size);
+ if (!license)
+ return -ENOMEM;
+
+ memcpy(license, payload, size);
+
+ *__license = license;
+ *__license_length = size;
+
+ return 0;
+}
+
+static int ccs_data_parse_end(bool *end, const void *payload, const void *endp,
+ printf_ctx fh)
+{
+ const struct __ccs_data_block_end *__end = payload;
+
+ if (__end + 1 != endp) {
+ os_printf(fh, "Invalid end block length %u\n",
+ (unsigned int)(endp - payload));
+ return -ENODATA;
+ }
+
+ *end = true;
+
+ return 0;
+}
+
+static int __ccs_data_parse(struct bin_container *bin,
+ struct ccs_data_container *ccsdata,
+ const void *data, size_t len, printf_ctx fh,
+ bool verbose)
+{
+ const struct __ccs_data_block *block = data;
+ const struct __ccs_data_block *endp = data + len;
+ unsigned int version;
+ bool is_first = true;
+ int rval;
+
+ version = ccs_data_parse_format_version(block);
+ if (version != CCS_STATIC_DATA_VERSION) {
+ os_printf(fh, "Don't know how to handle version %u\n", version);
+ return -EINVAL;
+ }
+
+ if (verbose)
+ os_printf(fh, "Parsing CCS static data version %u\n", version);
+
+ if (!bin->base)
+ *ccsdata = (struct ccs_data_container){ 0 };
+
+ while (block < endp) {
+ const struct __ccs_data_block *next_block;
+ unsigned int block_id;
+ const void *payload;
+
+ rval = ccs_data_block_parse_header(block, is_first, &block_id,
+ &payload, &next_block, endp,
+ fh,
+ bin->base ? false : verbose);
+
+ if (rval < 0)
+ return rval;
+
+ switch (block_id) {
+ case CCS_DATA_BLOCK_ID_DUMMY:
+ break;
+ case CCS_DATA_BLOCK_ID_DATA_VERSION:
+ rval = ccs_data_parse_version(bin, ccsdata, payload,
+ next_block);
+ if (rval < 0)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_ID_SENSOR_READ_ONLY_REGS:
+ rval = ccs_data_parse_regs(
+ bin, &ccsdata->sensor_read_only_regs,
+ &ccsdata->num_sensor_read_only_regs, payload,
+ next_block, fh);
+ if (rval < 0)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_ID_SENSOR_MANUFACTURER_REGS:
+ rval = ccs_data_parse_regs(
+ bin, &ccsdata->sensor_manufacturer_regs,
+ &ccsdata->num_sensor_manufacturer_regs, payload,
+ next_block, fh);
+ if (rval < 0)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_ID_MODULE_READ_ONLY_REGS:
+ rval = ccs_data_parse_regs(
+ bin, &ccsdata->module_read_only_regs,
+ &ccsdata->num_module_read_only_regs, payload,
+ next_block, fh);
+ if (rval < 0)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_ID_MODULE_MANUFACTURER_REGS:
+ rval = ccs_data_parse_regs(
+ bin, &ccsdata->module_manufacturer_regs,
+ &ccsdata->num_module_manufacturer_regs, payload,
+ next_block, fh);
+ if (rval < 0)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_ID_SENSOR_PDAF_PIXEL_LOCATION:
+ rval = ccs_data_parse_pdaf(bin, &ccsdata->sensor_pdaf,
+ payload, next_block, fh);
+ if (rval < 0)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_ID_MODULE_PDAF_PIXEL_LOCATION:
+ rval = ccs_data_parse_pdaf(bin, &ccsdata->module_pdaf,
+ payload, next_block, fh);
+ if (rval < 0)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_ID_SENSOR_RULE_BASED_BLOCK:
+ rval = ccs_data_parse_rules(
+ bin, &ccsdata->sensor_rules,
+ &ccsdata->num_sensor_rules, payload, next_block,
+ fh);
+ if (rval < 0)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_ID_MODULE_RULE_BASED_BLOCK:
+ rval = ccs_data_parse_rules(
+ bin, &ccsdata->module_rules,
+ &ccsdata->num_module_rules, payload, next_block,
+ fh);
+ if (rval < 0)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_ID_LICENSE:
+ rval = ccs_data_parse_license(bin, &ccsdata->license,
+ &ccsdata->license_length,
+ payload, next_block);
+ if (rval < 0)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_ID_END:
+ rval = ccs_data_parse_end(&ccsdata->end, payload,
+ next_block, fh);
+ if (rval < 0)
+ return rval;
+ break;
+ default:
+ os_printf(fh, "WARNING: not handling block ID 0x%2.2x\n",
+ block_id);
+ }
+
+ block = next_block;
+ is_first = false;
+ }
+
+ return 0;
+}
+
+int ccs_data_parse(struct ccs_data_container *ccsdata,
+ const void *data, size_t len, printf_ctx fh, bool verbose)
+{
+ struct bin_container bin = { 0 };
+ int rval;
+
+ rval = __ccs_data_parse(&bin, ccsdata, data, len, fh, verbose);
+ if (rval)
+ return rval;
+
+ rval = bin_backing_alloc(&bin);
+ if (rval)
+ return rval;
+
+ rval = __ccs_data_parse(&bin, ccsdata, data, len, fh, false);
+ if (rval)
+ goto out_free;
+
+ if (verbose && ccsdata->version)
+ print_ccs_data_version(fh, ccsdata->version);
+
+ if (bin.now != bin.end) {
+ rval = -EPROTO;
+ os_printf(fh, "parsing mismatch; base %p; now %p; end %p\n",
+ bin.base, bin.now, bin.end);
+ goto out_free;
+ }
+
+ ccsdata->backing = bin.base;
+
+ return 0;
+
+out_free:
+ os_free(bin.base);
+
+ return rval;
+}
diff --git a/drivers/media/i2c/ccs/ccs-data.h b/drivers/media/i2c/ccs/ccs-data.h
new file mode 100644
index 000000000000..1dfc697fccdf
--- /dev/null
+++ b/drivers/media/i2c/ccs/ccs-data.h
@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
+/* Copyright 2019--2020 Intel Corporation */
+
+#ifndef __CCS_DATA_H__
+#define __CCS_DATA_H__
+
+#include "ccs-os.h"
+
+struct ccs_data_block_version {
+ uint16_t version_major;
+ uint16_t version_minor;
+ uint16_t date_year;
+ uint8_t date_month;
+ uint8_t date_day;
+};
+
+struct ccs_reg {
+ uint16_t addr;
+ uint16_t len;
+ uint8_t *value;
+};
+
+struct ccs_if_rule {
+ uint16_t addr;
+ uint8_t value;
+ uint8_t mask;
+};
+
+struct ccs_frame_format_desc {
+ uint8_t pixelcode;
+ uint16_t value;
+};
+
+struct ccs_frame_format_descs {
+ uint8_t num_column_descs;
+ uint8_t num_row_descs;
+ struct ccs_frame_format_desc *column_descs;
+ struct ccs_frame_format_desc *row_descs;
+};
+
+struct ccs_pdaf_readout {
+ uint8_t pdaf_readout_info_order;
+ struct ccs_frame_format_descs *ffd;
+};
+
+struct ccs_rule {
+ size_t num_if_rules;
+ struct ccs_if_rule *if_rules;
+ size_t num_read_only_regs;
+ struct ccs_reg *read_only_regs;
+ size_t num_manufacturer_regs;
+ struct ccs_reg *manufacturer_regs;
+ struct ccs_frame_format_descs *frame_format;
+ struct ccs_pdaf_readout *pdaf_readout;
+};
+
+struct ccs_pdaf_pix_loc_block_desc {
+ uint8_t block_type_id;
+ uint16_t repeat_x;
+};
+
+struct ccs_pdaf_pix_loc_block_desc_group {
+ uint8_t repeat_y;
+ uint16_t num_block_descs;
+ struct ccs_pdaf_pix_loc_block_desc *block_descs;
+};
+
+struct ccs_pdaf_pix_loc_pixel_desc {
+ uint8_t pixel_type;
+ uint8_t small_offset_x;
+ uint8_t small_offset_y;
+};
+
+struct ccs_pdaf_pix_loc_pixel_desc_group {
+ uint8_t num_descs;
+ struct ccs_pdaf_pix_loc_pixel_desc *descs;
+};
+
+struct ccs_pdaf_pix_loc {
+ uint16_t main_offset_x;
+ uint16_t main_offset_y;
+ uint8_t global_pdaf_type;
+ uint8_t block_width;
+ uint8_t block_height;
+ uint16_t num_block_desc_groups;
+ struct ccs_pdaf_pix_loc_block_desc_group *block_desc_groups;
+ uint8_t num_pixel_desc_grups;
+ struct ccs_pdaf_pix_loc_pixel_desc_group *pixel_desc_groups;
+};
+
+struct ccs_data_container {
+ struct ccs_data_block_version *version;
+ size_t num_sensor_read_only_regs;
+ struct ccs_reg *sensor_read_only_regs;
+ size_t num_sensor_manufacturer_regs;
+ struct ccs_reg *sensor_manufacturer_regs;
+ size_t num_sensor_rules;
+ struct ccs_rule *sensor_rules;
+ size_t num_module_read_only_regs;
+ struct ccs_reg *module_read_only_regs;
+ size_t num_module_manufacturer_regs;
+ struct ccs_reg *module_manufacturer_regs;
+ size_t num_module_rules;
+ struct ccs_rule *module_rules;
+ struct ccs_pdaf_pix_loc *sensor_pdaf;
+ struct ccs_pdaf_pix_loc *module_pdaf;
+ size_t license_length;
+ char *license;
+ bool end;
+ void *backing;
+};
+
+int ccs_data_parse(struct ccs_data_container *ccsdata, const void *data,
+ size_t len, printf_ctx fh, bool verbose);
+
+#endif /* __CCS_DATA_H__ */
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 034/106] ccs: Combine revision number major and minor into one
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (24 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 033/106] ccs: Add CCS static data parser library Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 035/106] ccs: Read CCS static data from firmware binaries Sakari Ailus
` (70 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
The module revision number major and minor are both 8 bits while the
sensor revision number is 16 bits. Combine the module revision into one
number.
This also adds printing the lowest 8 bits of the module version through
the sysfs attribute.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 25 ++++++++++++++-----------
drivers/media/i2c/ccs/ccs-quirk.c | 2 +-
drivers/media/i2c/ccs/ccs.h | 3 +--
3 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 19ff15eda246..34e86ddbb06a 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -2421,11 +2421,11 @@ ccs_sysfs_ident_read(struct device *dev, struct device_attribute *attr,
if (minfo->mipi_manufacturer_id)
return snprintf(buf, PAGE_SIZE, "%4.4x%4.4x%2.2x\n",
minfo->mipi_manufacturer_id, minfo->model_id,
- minfo->revision_number_major) + 1;
+ minfo->revision_number) + 1;
else
return snprintf(buf, PAGE_SIZE, "%2.2x%4.4x%2.2x\n",
minfo->smia_manufacturer_id, minfo->model_id,
- minfo->revision_number_major) + 1;
+ minfo->revision_number) + 1;
}
static DEVICE_ATTR(ident, S_IRUGO, ccs_sysfs_ident_read, NULL);
@@ -2439,6 +2439,7 @@ static int ccs_identify_module(struct ccs_sensor *sensor)
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
struct ccs_module_info *minfo = &sensor->minfo;
unsigned int i;
+ u32 rev;
int rval = 0;
/* Module info */
@@ -2454,11 +2455,13 @@ static int ccs_identify_module(struct ccs_sensor *sensor)
if (!rval)
rval = ccs_read_addr_8only(sensor,
CCS_R_MODULE_REVISION_NUMBER_MAJOR,
- &minfo->revision_number_major);
- if (!rval)
+ &rev);
+ if (!rval) {
rval = ccs_read_addr_8only(sensor,
CCS_R_MODULE_REVISION_NUMBER_MINOR,
- &minfo->revision_number_minor);
+ &minfo->revision_number);
+ minfo->revision_number |= rev << 8;
+ }
if (!rval)
rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_DATE_YEAR,
&minfo->module_year);
@@ -2513,9 +2516,9 @@ static int ccs_identify_module(struct ccs_sensor *sensor)
minfo->smia_manufacturer_id, minfo->model_id);
dev_dbg(&client->dev,
- "module revision 0x%2.2x-0x%2.2x date %2.2d-%2.2d-%2.2d\n",
- minfo->revision_number_major, minfo->revision_number_minor,
- minfo->module_year, minfo->module_month, minfo->module_day);
+ "module revision 0x%4.4x date %2.2d-%2.2d-%2.2d\n",
+ minfo->revision_number, minfo->module_year, minfo->module_month,
+ minfo->module_day);
if (minfo->sensor_mipi_manufacturer_id)
dev_dbg(&client->dev, "MIPI CCS sensor 0x%4.4x-0x%4.4x\n",
@@ -2553,7 +2556,7 @@ static int ccs_identify_module(struct ccs_sensor *sensor)
minfo->smia_manufacturer_id =
minfo->sensor_smia_manufacturer_id;
minfo->model_id = minfo->sensor_model_id;
- minfo->revision_number_major = minfo->sensor_revision_number;
+ minfo->revision_number = minfo->sensor_revision_number;
}
for (i = 0; i < ARRAY_SIZE(ccs_module_idents); i++) {
@@ -2570,11 +2573,11 @@ static int ccs_identify_module(struct ccs_sensor *sensor)
if (ccs_module_idents[i].flags
& CCS_MODULE_IDENT_FLAG_REV_LE) {
if (ccs_module_idents[i].revision_number_major
- < minfo->revision_number_major)
+ < (minfo->revision_number >> 8))
continue;
} else {
if (ccs_module_idents[i].revision_number_major
- != minfo->revision_number_major)
+ != (minfo->revision_number >> 8))
continue;
}
diff --git a/drivers/media/i2c/ccs/ccs-quirk.c b/drivers/media/i2c/ccs/ccs-quirk.c
index facec28f8447..07c5733b4244 100644
--- a/drivers/media/i2c/ccs/ccs-quirk.c
+++ b/drivers/media/i2c/ccs/ccs-quirk.c
@@ -35,7 +35,7 @@ static int ccs_write_addr_8s(struct ccs_sensor *sensor,
static int jt8ew9_limits(struct ccs_sensor *sensor)
{
- if (sensor->minfo.revision_number_major < 0x03)
+ if (sensor->minfo.revision_number < 0x0300)
sensor->frame_skip = 1;
/* Below 24 gain doesn't have effect at all, */
diff --git a/drivers/media/i2c/ccs/ccs.h b/drivers/media/i2c/ccs/ccs.h
index 2d1e8339f663..ad2ff5a74424 100644
--- a/drivers/media/i2c/ccs/ccs.h
+++ b/drivers/media/i2c/ccs/ccs.h
@@ -107,8 +107,7 @@ struct ccs_module_info {
u32 smia_manufacturer_id;
u32 mipi_manufacturer_id;
u32 model_id;
- u32 revision_number_major;
- u32 revision_number_minor;
+ u32 revision_number;
u32 module_year;
u32 module_month;
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 035/106] ccs: Read CCS static data from firmware binaries
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (25 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 034/106] ccs: Combine revision number major and minor into one Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-11-05 10:56 ` Mauro Carvalho Chehab
2020-10-07 8:44 ` [PATCH v2 036/106] ccs: Stop reading arrays after the first zero Sakari Ailus
` (69 subsequent siblings)
96 siblings, 1 reply; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
Read the CCS static data for sensors and modules. The files are expected
to be found in "ccs" directory.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 30 ++++++++++++++++++++++++++++++
drivers/media/i2c/ccs/ccs.h | 2 ++
2 files changed, 32 insertions(+)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 34e86ddbb06a..0cc6e7423f26 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -16,6 +16,7 @@
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
+#include <linux/firmware.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
@@ -2947,6 +2948,8 @@ static int ccs_get_hwconfig(struct ccs_sensor *sensor, struct device *dev)
static int ccs_probe(struct i2c_client *client)
{
struct ccs_sensor *sensor;
+ const struct firmware *fw;
+ char filename[40];
unsigned int i;
int rval;
@@ -3036,6 +3039,31 @@ static int ccs_probe(struct i2c_client *client)
goto out_power_off;
}
+ WARN_ON(snprintf(filename, sizeof(filename),
+ "ccs/ccs-sensor-%4.4x-%4.4x-%4.4x.fw",
+ sensor->minfo.sensor_mipi_manufacturer_id,
+ sensor->minfo.sensor_model_id,
+ sensor->minfo.sensor_revision_number) >=
+ sizeof(filename));
+ rval = request_firmware(&fw, filename, &client->dev);
+ if (!rval) {
+ ccs_data_parse(&sensor->sdata, fw->data, fw->size, &client->dev,
+ true);
+ release_firmware(fw);
+ }
+
+ WARN_ON(snprintf(filename, sizeof(filename),
+ "ccs/ccs-module-%4.4x-%4.4x-%4.4x.fw",
+ sensor->minfo.mipi_manufacturer_id,
+ sensor->minfo.model_id,
+ sensor->minfo.revision_number) >= sizeof(filename));
+ rval = request_firmware(&fw, filename, &client->dev);
+ if (!rval) {
+ ccs_data_parse(&sensor->mdata, fw->data, fw->size, &client->dev,
+ true);
+ release_firmware(fw);
+ }
+
rval = ccs_read_all_limits(sensor);
if (rval)
goto out_power_off;
@@ -3232,6 +3260,8 @@ static int ccs_remove(struct i2c_client *client)
ccs_cleanup(sensor);
mutex_destroy(&sensor->mutex);
kfree(sensor->ccs_limits);
+ kvfree(sensor->sdata.backing);
+ kvfree(sensor->mdata.backing);
return 0;
}
diff --git a/drivers/media/i2c/ccs/ccs.h b/drivers/media/i2c/ccs/ccs.h
index ad2ff5a74424..cbcd93b519da 100644
--- a/drivers/media/i2c/ccs/ccs.h
+++ b/drivers/media/i2c/ccs/ccs.h
@@ -16,6 +16,7 @@
#include <media/v4l2-ctrls.h>
#include <media/v4l2-subdev.h>
+#include "ccs-data.h"
#include "ccs-quirk.h"
#include "ccs-regs.h"
#include "ccs-reg-access.h"
@@ -227,6 +228,7 @@ struct ccs_sensor {
const struct ccs_csi_data_format *internal_csi_format;
u32 default_mbus_frame_fmts;
int default_pixel_order;
+ struct ccs_data_container sdata, mdata;
u8 binning_horizontal;
u8 binning_vertical;
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 036/106] ccs: Stop reading arrays after the first zero
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (26 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 035/106] ccs: Read CCS static data from firmware binaries Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 037/106] ccs: The functions to get compose or crop rectangle never return NULL Sakari Ailus
` (68 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
The register arrays have a certain size but not all the entries will be
relevant. In practice reading can be stopped after encountering a zero
value in the array. Do that to avoid extra reads.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 0cc6e7423f26..963f945ceaf0 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -193,6 +193,9 @@ static int ccs_read_all_limits(struct ccs_sensor *sensor)
goto out_err;
}
+ if (!val && j)
+ break;
+
ccs_assign_limit(ptr, width, val);
dev_dbg(&client->dev, "0x%8.8x \"%s\" = %u, 0x%x\n",
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 037/106] ccs: The functions to get compose or crop rectangle never return NULL
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (27 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 036/106] ccs: Stop reading arrays after the first zero Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 038/106] ccs: Replace somewhat harsh internal checks based on BUG with WARN_ON Sakari Ailus
` (67 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
The NULL check is not needed as the functions do not return NULL. Remove
the check (and BUG).
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 963f945ceaf0..d19267591d33 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -1760,16 +1760,12 @@ static void ccs_get_crop_compose(struct v4l2_subdev *subdev,
*comps = &ssd->compose;
} else {
if (crops) {
- for (i = 0; i < subdev->entity.num_pads; i++) {
+ for (i = 0; i < subdev->entity.num_pads; i++)
crops[i] = v4l2_subdev_get_try_crop(subdev, cfg, i);
- BUG_ON(!crops[i]);
- }
}
- if (comps) {
+ if (comps)
*comps = v4l2_subdev_get_try_compose(subdev, cfg,
CCS_PAD_SINK);
- BUG_ON(!*comps);
- }
}
}
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 038/106] ccs: Replace somewhat harsh internal checks based on BUG with WARN_ON
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (28 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 037/106] ccs: The functions to get compose or crop rectangle never return NULL Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 039/106] ccs: Refactor register reading a little Sakari Ailus
` (66 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
If an internal driver error was encountered, BUG was issued. Instead, do
less harsh WARN_ON_ONCE and try to manage with the consequences.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index d19267591d33..e01a5584b8b0 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -540,6 +540,10 @@ static void ccs_update_mbus_formats(struct ccs_sensor *sensor)
to_csi_format_idx(sensor->internal_csi_format) & ~3;
unsigned int pixel_order = ccs_pixel_order(sensor);
+ if (WARN_ON_ONCE(max(internal_csi_format_idx, csi_format_idx) +
+ pixel_order >= ARRAY_SIZE(ccs_csi_data_formats)))
+ return;
+
sensor->mbus_frame_fmts =
sensor->default_mbus_frame_fmts << pixel_order;
sensor->csi_format =
@@ -548,9 +552,6 @@ static void ccs_update_mbus_formats(struct ccs_sensor *sensor)
&ccs_csi_data_formats[internal_csi_format_idx
+ pixel_order];
- BUG_ON(max(internal_csi_format_idx, csi_format_idx) + pixel_order
- >= ARRAY_SIZE(ccs_csi_data_formats));
-
dev_dbg(&client->dev, "new pixel order %s\n",
pixel_order_str[pixel_order]);
}
@@ -1800,7 +1801,7 @@ static void ccs_propagate(struct v4l2_subdev *subdev,
*crops[CCS_PAD_SRC] = *comp;
break;
default:
- BUG();
+ WARN_ON_ONCE(1);
}
}
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 039/106] ccs: Refactor register reading a little
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (29 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 038/106] ccs: Replace somewhat harsh internal checks based on BUG with WARN_ON Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 040/106] ccs: Make real to integer number conversion optional Sakari Ailus
` (65 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
Rework quirk and 8-bit only access functions with a single function that
takes arguments. This is later extensible to support yet more flags.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-reg-access.c | 37 ++++++++++++--------------
1 file changed, 17 insertions(+), 20 deletions(-)
diff --git a/drivers/media/i2c/ccs/ccs-reg-access.c b/drivers/media/i2c/ccs/ccs-reg-access.c
index a8e9a235bfb3..abec746f3c93 100644
--- a/drivers/media/i2c/ccs/ccs-reg-access.c
+++ b/drivers/media/i2c/ccs/ccs-reg-access.c
@@ -168,39 +168,36 @@ static int __ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val,
return 0;
}
-int ccs_read_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 *val)
-{
- return __ccs_read_addr(
- sensor, reg, val,
- ccs_needs_quirk(sensor, CCS_QUIRK_FLAG_8BIT_READ_ONLY));
-}
-
-static int ccs_read_addr_quirk(struct ccs_sensor *sensor, u32 reg, u32 *val,
- bool force8)
+static int ccs_read_addr_raw(struct ccs_sensor *sensor, u32 reg, u32 *val,
+ bool force8, bool quirk)
{
int rval;
- *val = 0;
- rval = ccs_call_quirk(sensor, reg_access, false, ®, val);
- if (rval == -ENOIOCTLCMD)
- return 0;
- if (rval < 0)
- return rval;
+ if (quirk) {
+ *val = 0;
+ rval = ccs_call_quirk(sensor, reg_access, false, ®, val);
+ if (rval == -ENOIOCTLCMD)
+ return 0;
+ if (rval < 0)
+ return rval;
- if (force8)
- return __ccs_read_addr(sensor, reg, val, true);
+ if (force8)
+ return __ccs_read_addr(sensor, reg, val, true);
+ }
- return ccs_read_addr_no_quirk(sensor, reg, val);
+ return __ccs_read_addr(sensor, reg, val,
+ ccs_needs_quirk(sensor,
+ CCS_QUIRK_FLAG_8BIT_READ_ONLY));
}
int ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val)
{
- return ccs_read_addr_quirk(sensor, reg, val, false);
+ return ccs_read_addr_raw(sensor, reg, val, false, true);
}
int ccs_read_addr_8only(struct ccs_sensor *sensor, u32 reg, u32 *val)
{
- return ccs_read_addr_quirk(sensor, reg, val, true);
+ return ccs_read_addr_raw(sensor, reg, val, true, true);
}
int ccs_write_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 val)
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 040/106] ccs: Make real to integer number conversion optional
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (30 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 039/106] ccs: Refactor register reading a little Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 041/106] ccs: Move limit value real to integer conversion from read to access time Sakari Ailus
` (64 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
The limit values will be raw soon, and the conversion takes place later
on. Prepare for that.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-reg-access.c | 35 +++++++++++++++++++-------
drivers/media/i2c/ccs/ccs-reg-access.h | 2 ++
2 files changed, 28 insertions(+), 9 deletions(-)
diff --git a/drivers/media/i2c/ccs/ccs-reg-access.c b/drivers/media/i2c/ccs/ccs-reg-access.c
index abec746f3c93..fe6112cba6be 100644
--- a/drivers/media/i2c/ccs/ccs-reg-access.c
+++ b/drivers/media/i2c/ccs/ccs-reg-access.c
@@ -143,14 +143,23 @@ unsigned int ccs_reg_width(u32 reg)
return sizeof(uint8_t);
}
+u32 ccs_reg_conv(struct ccs_sensor *sensor, u32 reg, u32 val)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+
+ if (reg & CCS_FL_FLOAT_IREAL)
+ val = float_to_u32_mul_1000000(client, val);
+
+ return val;
+}
+
/*
* Read a 8/16/32-bit i2c register. The value is returned in 'val'.
* Returns zero if successful, or non-zero otherwise.
*/
static int __ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val,
- bool only8)
+ bool only8, bool conv)
{
- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
unsigned int len = ccs_reg_width(reg);
int rval;
@@ -162,14 +171,16 @@ static int __ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val,
if (rval < 0)
return rval;
- if (reg & CCS_FL_FLOAT_IREAL)
- *val = float_to_u32_mul_1000000(client, *val);
+ if (!conv)
+ return 0;
+
+ *val = ccs_reg_conv(sensor, reg, *val);
return 0;
}
static int ccs_read_addr_raw(struct ccs_sensor *sensor, u32 reg, u32 *val,
- bool force8, bool quirk)
+ bool force8, bool quirk, bool conv)
{
int rval;
@@ -182,22 +193,28 @@ static int ccs_read_addr_raw(struct ccs_sensor *sensor, u32 reg, u32 *val,
return rval;
if (force8)
- return __ccs_read_addr(sensor, reg, val, true);
+ return __ccs_read_addr(sensor, reg, val, true, conv);
}
return __ccs_read_addr(sensor, reg, val,
ccs_needs_quirk(sensor,
- CCS_QUIRK_FLAG_8BIT_READ_ONLY));
+ CCS_QUIRK_FLAG_8BIT_READ_ONLY),
+ conv);
}
int ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val)
{
- return ccs_read_addr_raw(sensor, reg, val, false, true);
+ return ccs_read_addr_raw(sensor, reg, val, false, true, true);
}
int ccs_read_addr_8only(struct ccs_sensor *sensor, u32 reg, u32 *val)
{
- return ccs_read_addr_raw(sensor, reg, val, true, true);
+ return ccs_read_addr_raw(sensor, reg, val, true, true, true);
+}
+
+int ccs_read_addr_noconv(struct ccs_sensor *sensor, u32 reg, u32 *val)
+{
+ return ccs_read_addr_raw(sensor, reg, val, false, true, false);
}
int ccs_write_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 val)
diff --git a/drivers/media/i2c/ccs/ccs-reg-access.h b/drivers/media/i2c/ccs/ccs-reg-access.h
index 9fdf5659ed09..5f6ff9c57698 100644
--- a/drivers/media/i2c/ccs/ccs-reg-access.h
+++ b/drivers/media/i2c/ccs/ccs-reg-access.h
@@ -24,10 +24,12 @@ struct ccs_sensor;
int ccs_read_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 *val);
int ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val);
int ccs_read_addr_8only(struct ccs_sensor *sensor, u32 reg, u32 *val);
+int ccs_read_addr_noconv(struct ccs_sensor *sensor, u32 reg, u32 *val);
int ccs_write_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 val);
int ccs_write_addr(struct ccs_sensor *sensor, u32 reg, u32 val);
unsigned int ccs_reg_width(u32 reg);
+u32 ccs_reg_conv(struct ccs_sensor *sensor, u32 reg, u32 val);
#define ccs_read(sensor, reg_name, val) \
ccs_read_addr(sensor, CCS_R_##reg_name, val)
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 041/106] ccs: Move limit value real to integer conversion from read to access time
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (31 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 040/106] ccs: Make real to integer number conversion optional Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 042/106] ccs: Read ireal numbers correctly Sakari Ailus
` (63 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
Instead of converting the limit values at register read time, do that at
access time instead.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 19 ++++++++++++-------
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index e01a5584b8b0..5b7f142b2432 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -124,6 +124,7 @@ static u32 ccs_get_limit(struct ccs_sensor *sensor,
unsigned int limit, unsigned int offset)
{
void *ptr;
+ u32 val;
int ret;
ret = ccs_limit_ptr(sensor, limit, offset, &ptr);
@@ -132,16 +133,20 @@ static u32 ccs_get_limit(struct ccs_sensor *sensor,
switch (ccs_reg_width(ccs_limits[ccs_limit_offsets[limit].info].reg)) {
case sizeof(u8):
- return *(u8 *)ptr;
+ val = *(u8 *)ptr;
+ break;
case sizeof(u16):
- return *(u16 *)ptr;
+ val = *(u16 *)ptr;
+ break;
case sizeof(u32):
- return *(u32 *)ptr;
+ val = *(u32 *)ptr;
+ break;
+ default:
+ WARN_ON(1);
+ return 0;
}
- WARN_ON(1);
-
- return 0;
+ return ccs_reg_conv(sensor, ccs_limits[limit].reg, val);
}
#define CCS_LIM(sensor, limit) \
@@ -182,7 +187,7 @@ static int ccs_read_all_limits(struct ccs_sensor *sensor)
j++, reg += width, ptr += width) {
u32 val;
- ret = ccs_read_addr(sensor, reg, &val);
+ ret = ccs_read_addr_noconv(sensor, reg, &val);
if (ret)
goto out_err;
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 042/106] ccs: Read ireal numbers correctly
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (32 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 041/106] ccs: Move limit value real to integer conversion from read to access time Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 043/106] smiapp-pll: Rename as ccs-pll Sakari Ailus
` (62 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
Some limit values are available in q16.q16 format, referred to as 32-bit
unsigned ireal in CCS. Read these correctly.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 10 ++--------
drivers/media/i2c/ccs/ccs-reg-access.c | 23 +++++++++++++++++++++--
drivers/media/i2c/ccs/ccs.h | 9 +++++++++
3 files changed, 32 insertions(+), 10 deletions(-)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 5b7f142b2432..cd8978c085d4 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -120,8 +120,8 @@ void ccs_replace_limit(struct ccs_sensor *sensor,
ccs_assign_limit(ptr, ccs_reg_width(linfo->reg), val);
}
-static u32 ccs_get_limit(struct ccs_sensor *sensor,
- unsigned int limit, unsigned int offset)
+u32 ccs_get_limit(struct ccs_sensor *sensor, unsigned int limit,
+ unsigned int offset)
{
void *ptr;
u32 val;
@@ -149,12 +149,6 @@ static u32 ccs_get_limit(struct ccs_sensor *sensor,
return ccs_reg_conv(sensor, ccs_limits[limit].reg, val);
}
-#define CCS_LIM(sensor, limit) \
- ccs_get_limit(sensor, CCS_L_##limit, 0)
-
-#define CCS_LIM_AT(sensor, limit, offset) \
- ccs_get_limit(sensor, CCS_L_##limit, CCS_L_##limit##_OFFSET(offset))
-
static int ccs_read_all_limits(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
diff --git a/drivers/media/i2c/ccs/ccs-reg-access.c b/drivers/media/i2c/ccs/ccs-reg-access.c
index fe6112cba6be..91ccbca11577 100644
--- a/drivers/media/i2c/ccs/ccs-reg-access.c
+++ b/drivers/media/i2c/ccs/ccs-reg-access.c
@@ -15,6 +15,7 @@
#include <linux/i2c.h>
#include "ccs.h"
+#include "ccs-limits.h"
static uint32_t float_to_u32_mul_1000000(struct i2c_client *client,
uint32_t phloat)
@@ -143,12 +144,30 @@ unsigned int ccs_reg_width(u32 reg)
return sizeof(uint8_t);
}
+static u32 ireal32_to_u32_mul_1000000(struct i2c_client *client, u32 val)
+{
+ if (val >> 10 > U32_MAX / 15625) {
+ dev_warn(&client->dev, "value %u overflows!\n", val);
+ return U32_MAX;
+ }
+
+ return ((val >> 10) * 15625) +
+ (val & GENMASK(9, 0)) * 15625 / 1024;
+}
+
u32 ccs_reg_conv(struct ccs_sensor *sensor, u32 reg, u32 val)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- if (reg & CCS_FL_FLOAT_IREAL)
- val = float_to_u32_mul_1000000(client, val);
+ if (reg & CCS_FL_FLOAT_IREAL) {
+ if (CCS_LIM(sensor, CLOCK_CAPA_TYPE_CAPABILITY) &
+ CCS_CLOCK_CAPA_TYPE_CAPABILITY_IREAL)
+ val = ireal32_to_u32_mul_1000000(client, val);
+ else
+ val = float_to_u32_mul_1000000(client, val);
+ } else if (reg & CCS_FL_IREAL) {
+ val = ireal32_to_u32_mul_1000000(client, val);
+ }
return val;
}
diff --git a/drivers/media/i2c/ccs/ccs.h b/drivers/media/i2c/ccs/ccs.h
index cbcd93b519da..f60d1801c469 100644
--- a/drivers/media/i2c/ccs/ccs.h
+++ b/drivers/media/i2c/ccs/ccs.h
@@ -17,6 +17,7 @@
#include <media/v4l2-subdev.h>
#include "ccs-data.h"
+#include "ccs-limits.h"
#include "ccs-quirk.h"
#include "ccs-regs.h"
#include "ccs-reg-access.h"
@@ -50,6 +51,12 @@
#define CCS_DFL_I2C_ADDR (0x20 >> 1) /* Default I2C Address */
#define CCS_ALT_I2C_ADDR (0x6e >> 1) /* Alternate I2C Address */
+#define CCS_LIM(sensor, limit) \
+ ccs_get_limit(sensor, CCS_L_##limit, 0)
+
+#define CCS_LIM_AT(sensor, limit, offset) \
+ ccs_get_limit(sensor, CCS_L_##limit, CCS_L_##limit##_OFFSET(offset))
+
/*
* Sometimes due to board layout considerations the camera module can be
* mounted rotated. The typical rotation used is 180 degrees which can be
@@ -277,5 +284,7 @@ struct ccs_sensor {
void ccs_replace_limit(struct ccs_sensor *sensor,
unsigned int limit, unsigned int offset, u32 val);
+u32 ccs_get_limit(struct ccs_sensor *sensor, unsigned int limit,
+ unsigned int offset);
#endif /* __CCS_H__ */
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 000/106] CCS driver
@ 2020-10-07 8:44 Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (9 more replies)
0 siblings, 10 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media; +Cc: devicetree
Hello everyone,
Here's a set of patches that turn the existing SMIA driver into a MIPI CCS
driver while maintaining SMIA support. A number of bugs in the existing
code are fixed in this set, too.
The changes at this point are primarily focused on dealing with new
mandatory driver features related to PLL configuration (as CCS allows for
much more variation there) and things such as integer conversion from
U16.U16 format instead of float. There are some other new features as well
such as digital gain and support for getting device specific analogue gain
coefficients.
A new feature in CCS is CCS static data which makes it possible to obtain
sensor's capabilities and limits from a file chosen based on sensor
identification. CCS static data is used also for storing MSR registers so
supporting new, CCS compliant devices requires no driver changes.
Note that the library as well as the register definitions are dual
licensed under GNU GPL v2 OR BSD 3-clause licenses for use outside the
Linux kernel.
Also DT bindings are updated accordingly and converted to YAML format.
More information on MIPI CCS can be found here:
<URL:https://www.mipi.org/specifications/camera-command-set>
Comments are welcome.
since v1 (DT bindings):
- Remove DT vendor prefix, use vendor-less compatible string
- Add spec version specific compatible strings together with the generic one
- Add VCore and VIO regulators
- Fix rotation property description
- Use less verbose definition of data-lanes property
- Remove CSI-1 bus; this isn't really there, the old stuff is all CCP2
- Make bus-type a required property
- Use additionalProperties: false on the device
- Fix the example (change compatible string, remove nokia,nvm leftover
property)
- Fix MAINTAINERS
since v1 (driver):
- Generate register and limit definitions from source
- Style fixes in ccs-pll.c
- Use correct MODULE_LICENSE in ccs-pll.c
- Support for VCore and VIO regulators
- Remove extra delays from power-up sequence
- Adapt to parsing changes in v4l2_fwnode_endpoint_alloc_parse(), i.e.
call it just once. This also fixes parsing bus-type-less DT binaries.
- Fix MAINTAINERS
Sakari Ailus (106):
smiapp: Generate CCS register definitions and limits
smiapp: Use CCS register flags
smiapp: Calculate CCS limit offsets and limit buffer size
smiapp: Remove macros for defining registers, merge definitions
smiapp: Add macros for accessing CCS registers
smiapp: Use MIPI CCS version and manufacturer ID information
smiapp: Read CCS limit values
smiapp: Switch to CCS limits
smiapp: Obtain frame descriptor from CCS limits
smiapp: Use CCS limits in reading data format descriptors
smiapp: Use CCS limits in reading binning capabilities
smiapp: Use CCS registers
smiapp: Remove quirk function for writing a single 8-bit register
smiapp: Rename register access functions
smiapp: Internal rename to CCS
smiapp: Differentiate CCS sensors from SMIA in subdev naming
smiapp: Rename as "ccs"
ccs: Remove profile concept
ccs: Give all subdevs a function
dt-bindings: nokia,smia: Fix link-frequencies documentation
dt-bindings: nokia,smia: Make vana-supply optional
dt-bindings: nokia,smia: Remove nokia,nvm-size property
dt-bindings: nokia,smia: Convert to YAML
dt-bindings: nokia,smia: Use better active polarity for reset
dt-bindings: nokia,smia: Amend SMIA bindings with MIPI CCS support
dt-bindings: mipi-ccs: Add bus-type for C-PHY support
ccs: Request for "reset" GPIO
ccs: Add MIPI CCS compatible strings
ccs: Remove the I²C ID table
ccs: Remove remaining support for platform data
ccs: Make hwcfg part of the device specific struct
ccs: Fix obtaining bus information from firmware
ccs: Add CCS static data parser library
ccs: Combine revision number major and minor into one
ccs: Read CCS static data from firmware binaries
ccs: Stop reading arrays after the first zero
ccs: The functions to get compose or crop rectangle never return NULL
ccs: Replace somewhat harsh internal checks based on BUG with WARN_ON
ccs: Refactor register reading a little
ccs: Make real to integer number conversion optional
ccs: Move limit value real to integer conversion from read to access
time
ccs: Read ireal numbers correctly
smiapp-pll: Rename as ccs-pll
ccs-pll: Fix MODULE_LICENSE
ccs: Change my e-mail address
ccs: Add support for manufacturer regs from sensor and module files
ccs: Use static data read-only registers
ccs: Clean up runtime PM usage
ccs: Wrap long lines, unwrap short ones
ccs: Add device compatible identifiers for telling SMIA and CCS apart
ccs: Use longer pre-I²C sleep for CCS compliant devices
ccs: Remove unnecessary delays from power-up sequence
dt-bindings: mipi,ccs: Don't mention vana voltage
dt-bindings: mipi,ccs: Add vcore and vio supplies
ccs: Use all regulators
ccs-pll: Don't use div_u64 to divide a 32-bit number
ccs-pll: Split limits and PLL configuration into front and back parts
ccs-pll: Use correct VT divisor for calculating VT SYS divisor
ccs-pll: End search if there are no better values available
ccs-pll: Remove parallel bus support
ccs-pll: Differentiate between CSI-2 D-PHY and C-PHY
ccs-pll: Move the flags field down, away from 8-bit fields
ccs-pll: Document the structs in the header as well as the function
ccs-pll: Use the BIT macro
ccs-pll: Begin calculation from OP system clock frequency
ccs-pll: Fix condition for pre-PLL divider lower bound
ccs-pll: Avoid overflow in pre-PLL divisor lower bound search
ccs-pll: Fix comment on check against maximum PLL multiplier
ccs-pll: Fix check for PLL multiplier upper bound
ccs-pll: Use explicit 32-bit unsigned type
ccs-pll: Add support for lane speed model
ccs: Add support for lane speed model
ccs-pll: Add support for decoupled OP domain calculation
ccs-pll: Add support for extended input PLL clock divider
ccs-pll: Support two cycles per pixel on OP domain
ccs-pll: Add support flexible OP PLL pixel clock divider
ccs-pll: Add sanity checks
ccs-pll: Add C-PHY support
ccs-pll: Split off VT subtree calculation
ccs-pll: Check for derating and overrating, support non-derating
sensors
ccs-pll: Better separate OP and VT sub-tree calculation
ccs-pll: Print relevant information on PLL tree
ccs-pll: Rework bounds checks
ccs-pll: Make VT divisors 16-bit
ccs-pll: Fix VT post-PLL divisor calculation
ccs-pll: Separate VT divisor limit calculation from the rest
ccs-pll: Add trivial dual PLL support
ccs: Dual PLL support
ccs-pll: Add support for DDR OP system and pixel clocks
ccs: Add support for DDR OP SYS and OP PIX clocks
ccs: Print written register values
ccs-pll: Print pixel rates
ccs: Add support for obtaining C-PHY configuration from firmware
ccs: Add digital gain support
ccs: Add support for old-style SMIA digital gain
ccs: Remove analogue gain field
ccs: Only add analogue gain control if the device supports it
v4l: uapi: Add user control base for CCS controls
v4l: uapi: ccs: Add controls for analogue gain constants
ccs: Add support for analogue gain coefficient controls
v4l: uapi: ccs: Add controls for CCS alternative analogue gain
ccs: Add support for alternate analogue global gain
ccs: Add debug prints for MSR registers
v4l: uapi: ccs: Add CCS controls for shading correction
ccs: Add shading correction and luminance correction level controls
ccs: Add CCS ACPI device ID
.../bindings/media/i2c/mipi-ccs.yaml | 135 +
.../bindings/media/i2c/nokia,smia.txt | 66 -
MAINTAINERS | 21 +-
drivers/media/i2c/Kconfig | 4 +-
drivers/media/i2c/Makefile | 4 +-
drivers/media/i2c/{smiapp-pll.c => ccs-pll.c} | 1012 ++++---
drivers/media/i2c/{smiapp-pll.h => ccs-pll.h} | 196 +-
drivers/media/i2c/{smiapp => ccs}/Kconfig | 9 +-
drivers/media/i2c/{smiapp => ccs}/Makefile | 18 +-
.../{smiapp/smiapp-core.c => ccs/ccs-core.c} | 2426 ++++++++++-------
drivers/media/i2c/ccs/ccs-data-defs.h | 215 ++
drivers/media/i2c/ccs/ccs-data.c | 949 +++++++
drivers/media/i2c/ccs/ccs-data.h | 116 +
drivers/media/i2c/ccs/ccs-os.h | 15 +
.../smiapp-quirk.c => ccs/ccs-quirk.c} | 105 +-
.../smiapp-quirk.h => ccs/ccs-quirk.h} | 54 +-
.../smiapp-regs.c => ccs/ccs-reg-access.c} | 296 +-
.../smiapp-regs.h => ccs/ccs-reg-access.h} | 40 +-
drivers/media/i2c/ccs/ccs-regs.txt | 1041 +++++++
.../media/i2c/{smiapp/smiapp.h => ccs/ccs.h} | 185 +-
drivers/media/i2c/ccs/mk-ccs-regs | 405 +++
.../smiapp-reg.h => ccs/smiapp-reg-defs.h} | 502 +++-
drivers/media/i2c/smiapp/smiapp-limits.c | 118 -
drivers/media/i2c/smiapp/smiapp-limits.h | 114 -
drivers/media/i2c/smiapp/smiapp-reg-defs.h | 489 ----
include/uapi/linux/ccs.h | 21 +
include/uapi/linux/v4l2-controls.h | 6 +
27 files changed, 6166 insertions(+), 2396 deletions(-)
create mode 100644 Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml
delete mode 100644 Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
rename drivers/media/i2c/{smiapp-pll.c => ccs-pll.c} (16%)
rename drivers/media/i2c/{smiapp-pll.h => ccs-pll.h} (18%)
rename drivers/media/i2c/{smiapp => ccs}/Kconfig (48%)
rename drivers/media/i2c/{smiapp => ccs}/Makefile (14%)
rename drivers/media/i2c/{smiapp/smiapp-core.c => ccs/ccs-core.c} (43%)
create mode 100644 drivers/media/i2c/ccs/ccs-data-defs.h
create mode 100644 drivers/media/i2c/ccs/ccs-data.c
create mode 100644 drivers/media/i2c/ccs/ccs-data.h
create mode 100644 drivers/media/i2c/ccs/ccs-os.h
rename drivers/media/i2c/{smiapp/smiapp-quirk.c => ccs/ccs-quirk.c} (63%)
rename drivers/media/i2c/{smiapp/smiapp-quirk.h => ccs/ccs-quirk.h} (53%)
rename drivers/media/i2c/{smiapp/smiapp-regs.c => ccs/ccs-reg-access.c} (37%)
rename drivers/media/i2c/{smiapp/smiapp-regs.h => ccs/ccs-reg-access.h} (16%)
create mode 100644 drivers/media/i2c/ccs/ccs-regs.txt
rename drivers/media/i2c/{smiapp/smiapp.h => ccs/ccs.h} (52%)
create mode 100644 drivers/media/i2c/ccs/mk-ccs-regs
rename drivers/media/i2c/{smiapp/smiapp-reg.h => ccs/smiapp-reg-defs.h} (10%)
delete mode 100644 drivers/media/i2c/smiapp/smiapp-limits.c
delete mode 100644 drivers/media/i2c/smiapp/smiapp-limits.h
delete mode 100644 drivers/media/i2c/smiapp/smiapp-reg-defs.h
create mode 100644 include/uapi/linux/ccs.h
--
2.27.0
^ permalink raw reply [flat|nested] 146+ messages in thread
* [PATCH v2 043/106] smiapp-pll: Rename as ccs-pll
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (33 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 042/106] ccs: Read ireal numbers correctly Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 044/106] ccs-pll: Fix MODULE_LICENSE Sakari Ailus
` (61 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
MIPI CCS replaces SMIA and SMIA++ as the current standard. CCS brings new
features while existing functionality will be supported. Rename the
smiapp-pll as ccs-pll accordingly.
Also add Intel copyright to the files.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
MAINTAINERS | 4 +-
drivers/media/i2c/Kconfig | 2 +-
drivers/media/i2c/Makefile | 2 +-
drivers/media/i2c/{smiapp-pll.c => ccs-pll.c} | 60 +++++++++----------
drivers/media/i2c/{smiapp-pll.h => ccs-pll.h} | 40 ++++++-------
drivers/media/i2c/ccs/Kconfig | 2 +-
drivers/media/i2c/ccs/ccs-core.c | 18 +++---
drivers/media/i2c/ccs/ccs-quirk.c | 2 +-
drivers/media/i2c/ccs/ccs.h | 4 +-
9 files changed, 66 insertions(+), 68 deletions(-)
rename drivers/media/i2c/{smiapp-pll.c => ccs-pll.c} (90%)
rename drivers/media/i2c/{smiapp-pll.h => ccs-pll.h} (68%)
diff --git a/MAINTAINERS b/MAINTAINERS
index 135d41b823a4..b72f666b8b60 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11566,8 +11566,8 @@ L: linux-media@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml
F: drivers/media/i2c/ccs/
-F: drivers/media/i2c/smiapp-pll.c
-F: drivers/media/i2c/smiapp-pll.h
+F: drivers/media/i2c/ccs-pll.c
+F: drivers/media/i2c/ccs-pll.h
F: include/uapi/linux/smiapp.h
MIPS
diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
index 41a8b6189259..4b6fcf13d527 100644
--- a/drivers/media/i2c/Kconfig
+++ b/drivers/media/i2c/Kconfig
@@ -722,7 +722,7 @@ menu "Camera sensor devices"
config VIDEO_APTINA_PLL
tristate
-config VIDEO_SMIAPP_PLL
+config VIDEO_CCS_PLL
tristate
config VIDEO_HI556
diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
index cb0be09e38bd..c716bac3ed4b 100644
--- a/drivers/media/i2c/Makefile
+++ b/drivers/media/i2c/Makefile
@@ -104,7 +104,7 @@ obj-$(CONFIG_VIDEO_S5C73M3) += s5c73m3/
obj-$(CONFIG_VIDEO_ADP1653) += adp1653.o
obj-$(CONFIG_VIDEO_LM3560) += lm3560.o
obj-$(CONFIG_VIDEO_LM3646) += lm3646.o
-obj-$(CONFIG_VIDEO_SMIAPP_PLL) += smiapp-pll.o
+obj-$(CONFIG_VIDEO_CCS_PLL) += ccs-pll.o
obj-$(CONFIG_VIDEO_AK881X) += ak881x.o
obj-$(CONFIG_VIDEO_IR_I2C) += ir-kbd-i2c.o
obj-$(CONFIG_VIDEO_I2C) += video-i2c.o
diff --git a/drivers/media/i2c/smiapp-pll.c b/drivers/media/i2c/ccs-pll.c
similarity index 90%
rename from drivers/media/i2c/smiapp-pll.c
rename to drivers/media/i2c/ccs-pll.c
index 690abe8cbdb2..d2f0f7375f5c 100644
--- a/drivers/media/i2c/smiapp-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -1,9 +1,10 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * drivers/media/i2c/smiapp-pll.c
+ * drivers/media/i2c/ccs-pll.c
*
- * Generic driver for SMIA/SMIA++ compliant camera modules
+ * Generic MIPI CCS/SMIA/SMIA++ PLL calculator
*
+ * Copyright (C) 2020 Intel Corporation
* Copyright (C) 2011--2012 Nokia Corporation
* Contact: Sakari Ailus <sakari.ailus@iki.fi>
*/
@@ -13,7 +14,7 @@
#include <linux/lcm.h>
#include <linux/module.h>
-#include "smiapp-pll.h"
+#include "ccs-pll.h"
/* Return an even number or one. */
static inline uint32_t clk_div_even(uint32_t a)
@@ -50,11 +51,11 @@ static int bounds_check(struct device *dev, uint32_t val,
return -EINVAL;
}
-static void print_pll(struct device *dev, struct smiapp_pll *pll)
+static void print_pll(struct device *dev, struct ccs_pll *pll)
{
dev_dbg(dev, "pre_pll_clk_div\t%u\n", pll->pre_pll_clk_div);
dev_dbg(dev, "pll_multiplier \t%u\n", pll->pll_multiplier);
- if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) {
+ if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)) {
dev_dbg(dev, "op_sys_clk_div \t%u\n", pll->op.sys_clk_div);
dev_dbg(dev, "op_pix_clk_div \t%u\n", pll->op.pix_clk_div);
}
@@ -64,7 +65,7 @@ static void print_pll(struct device *dev, struct smiapp_pll *pll)
dev_dbg(dev, "ext_clk_freq_hz \t%u\n", pll->ext_clk_freq_hz);
dev_dbg(dev, "pll_ip_clk_freq_hz \t%u\n", pll->pll_ip_clk_freq_hz);
dev_dbg(dev, "pll_op_clk_freq_hz \t%u\n", pll->pll_op_clk_freq_hz);
- if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) {
+ if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)) {
dev_dbg(dev, "op_sys_clk_freq_hz \t%u\n",
pll->op.sys_clk_freq_hz);
dev_dbg(dev, "op_pix_clk_freq_hz \t%u\n",
@@ -75,10 +76,9 @@ static void print_pll(struct device *dev, struct smiapp_pll *pll)
}
static int check_all_bounds(struct device *dev,
- const struct smiapp_pll_limits *limits,
- const struct smiapp_pll_branch_limits *op_limits,
- struct smiapp_pll *pll,
- struct smiapp_pll_branch *op_pll)
+ const struct ccs_pll_limits *limits,
+ const struct ccs_pll_branch_limits *op_limits,
+ struct ccs_pll *pll, struct ccs_pll_branch *op_pll)
{
int rval;
@@ -118,7 +118,7 @@ static int check_all_bounds(struct device *dev,
* If there are no OP clocks, the VT clocks are contained in
* the OP clock struct.
*/
- if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)
+ if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)
return rval;
if (!rval)
@@ -148,11 +148,11 @@ static int check_all_bounds(struct device *dev,
*
* @return Zero on success, error code on error.
*/
-static int __smiapp_pll_calculate(
- struct device *dev, const struct smiapp_pll_limits *limits,
- const struct smiapp_pll_branch_limits *op_limits,
- struct smiapp_pll *pll, struct smiapp_pll_branch *op_pll, uint32_t mul,
- uint32_t div, uint32_t lane_op_clock_ratio)
+static int
+__ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits,
+ const struct ccs_pll_branch_limits *op_limits,
+ struct ccs_pll *pll, struct ccs_pll_branch *op_pll,
+ uint32_t mul, uint32_t div, uint32_t lane_op_clock_ratio)
{
uint32_t sys_div;
uint32_t best_pix_div = INT_MAX >> 1;
@@ -252,7 +252,7 @@ static int __smiapp_pll_calculate(
op_pll->pix_clk_freq_hz =
op_pll->sys_clk_freq_hz / op_pll->pix_clk_div;
- if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS) {
+ if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) {
/* No OP clocks --- VT clocks are used instead. */
goto out_skip_vt_calc;
}
@@ -383,12 +383,11 @@ static int __smiapp_pll_calculate(
return check_all_bounds(dev, limits, op_limits, pll, op_pll);
}
-int smiapp_pll_calculate(struct device *dev,
- const struct smiapp_pll_limits *limits,
- struct smiapp_pll *pll)
+int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits,
+ struct ccs_pll *pll)
{
- const struct smiapp_pll_branch_limits *op_limits = &limits->op;
- struct smiapp_pll_branch *op_pll = &pll->op;
+ const struct ccs_pll_branch_limits *op_limits = &limits->op;
+ struct ccs_pll_branch *op_pll = &pll->op;
uint16_t min_pre_pll_clk_div;
uint16_t max_pre_pll_clk_div;
uint32_t lane_op_clock_ratio;
@@ -396,7 +395,7 @@ int smiapp_pll_calculate(struct device *dev,
unsigned int i;
int rval = -EINVAL;
- if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS) {
+ if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) {
/*
* If there's no OP PLL at all, use the VT values
* instead. The OP values are ignored for the rest of
@@ -406,7 +405,7 @@ int smiapp_pll_calculate(struct device *dev,
op_pll = &pll->vt;
}
- if (pll->flags & SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE)
+ if (pll->flags & CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE)
lane_op_clock_ratio = pll->csi2.lanes;
else
lane_op_clock_ratio = 1;
@@ -416,12 +415,12 @@ int smiapp_pll_calculate(struct device *dev,
pll->binning_vertical);
switch (pll->bus_type) {
- case SMIAPP_PLL_BUS_TYPE_CSI2:
+ case CCS_PLL_BUS_TYPE_CSI2:
/* CSI transfers 2 bits per clock per lane; thus times 2 */
pll->pll_op_clk_freq_hz = pll->link_freq * 2
* (pll->csi2.lanes / lane_op_clock_ratio);
break;
- case SMIAPP_PLL_BUS_TYPE_PARALLEL:
+ case CCS_PLL_BUS_TYPE_PARALLEL:
pll->pll_op_clk_freq_hz = pll->link_freq * pll->bits_per_pixel
/ DIV_ROUND_UP(pll->bits_per_pixel,
pll->parallel.bus_width);
@@ -461,9 +460,8 @@ int smiapp_pll_calculate(struct device *dev,
for (pll->pre_pll_clk_div = min_pre_pll_clk_div;
pll->pre_pll_clk_div <= max_pre_pll_clk_div;
pll->pre_pll_clk_div += 2 - (pll->pre_pll_clk_div & 1)) {
- rval = __smiapp_pll_calculate(dev, limits, op_limits, pll,
- op_pll, mul, div,
- lane_op_clock_ratio);
+ rval = __ccs_pll_calculate(dev, limits, op_limits, pll, op_pll,
+ mul, div, lane_op_clock_ratio);
if (rval)
continue;
@@ -475,8 +473,8 @@ int smiapp_pll_calculate(struct device *dev,
return rval;
}
-EXPORT_SYMBOL_GPL(smiapp_pll_calculate);
+EXPORT_SYMBOL_GPL(ccs_pll_calculate);
MODULE_AUTHOR("Sakari Ailus <sakari.ailus@iki.fi>");
-MODULE_DESCRIPTION("Generic SMIA/SMIA++ PLL calculator");
+MODULE_DESCRIPTION("Generic MIPI CCS/SMIA/SMIA++ PLL calculator");
MODULE_LICENSE("GPL");
diff --git a/drivers/media/i2c/smiapp-pll.h b/drivers/media/i2c/ccs-pll.h
similarity index 68%
rename from drivers/media/i2c/smiapp-pll.h
rename to drivers/media/i2c/ccs-pll.h
index bd6902f54539..88d641ee3fa1 100644
--- a/drivers/media/i2c/smiapp-pll.h
+++ b/drivers/media/i2c/ccs-pll.h
@@ -1,32 +1,33 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * drivers/media/i2c/smiapp-pll.h
+ * drivers/media/i2c/ccs-pll.h
*
- * Generic driver for SMIA/SMIA++ compliant camera modules
+ * Generic MIPI CCS/SMIA/SMIA++ PLL calculator
*
+ * Copyright (C) 2020 Intel Corporation
* Copyright (C) 2012 Nokia Corporation
* Contact: Sakari Ailus <sakari.ailus@iki.fi>
*/
-#ifndef SMIAPP_PLL_H
-#define SMIAPP_PLL_H
+#ifndef CCS_PLL_H
+#define CCS_PLL_H
/* CSI-2 or CCP-2 */
-#define SMIAPP_PLL_BUS_TYPE_CSI2 0x00
-#define SMIAPP_PLL_BUS_TYPE_PARALLEL 0x01
+#define CCS_PLL_BUS_TYPE_CSI2 0x00
+#define CCS_PLL_BUS_TYPE_PARALLEL 0x01
/* op pix clock is for all lanes in total normally */
-#define SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0)
-#define SMIAPP_PLL_FLAG_NO_OP_CLOCKS (1 << 1)
+#define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0)
+#define CCS_PLL_FLAG_NO_OP_CLOCKS (1 << 1)
-struct smiapp_pll_branch {
+struct ccs_pll_branch {
uint16_t sys_clk_div;
uint16_t pix_clk_div;
uint32_t sys_clk_freq_hz;
uint32_t pix_clk_freq_hz;
};
-struct smiapp_pll {
+struct ccs_pll {
/* input values */
uint8_t bus_type;
union {
@@ -51,14 +52,14 @@ struct smiapp_pll {
uint16_t pll_multiplier;
uint32_t pll_ip_clk_freq_hz;
uint32_t pll_op_clk_freq_hz;
- struct smiapp_pll_branch vt;
- struct smiapp_pll_branch op;
+ struct ccs_pll_branch vt;
+ struct ccs_pll_branch op;
uint32_t pixel_rate_csi;
uint32_t pixel_rate_pixel_array;
};
-struct smiapp_pll_branch_limits {
+struct ccs_pll_branch_limits {
uint16_t min_sys_clk_div;
uint16_t max_sys_clk_div;
uint32_t min_sys_clk_freq_hz;
@@ -69,7 +70,7 @@ struct smiapp_pll_branch_limits {
uint32_t max_pix_clk_freq_hz;
};
-struct smiapp_pll_limits {
+struct ccs_pll_limits {
/* Strict PLL limits */
uint32_t min_ext_clk_freq_hz;
uint32_t max_ext_clk_freq_hz;
@@ -82,8 +83,8 @@ struct smiapp_pll_limits {
uint32_t min_pll_op_freq_hz;
uint32_t max_pll_op_freq_hz;
- struct smiapp_pll_branch_limits vt;
- struct smiapp_pll_branch_limits op;
+ struct ccs_pll_branch_limits vt;
+ struct ccs_pll_branch_limits op;
/* Other relevant limits */
uint32_t min_line_length_pck_bin;
@@ -92,8 +93,7 @@ struct smiapp_pll_limits {
struct device;
-int smiapp_pll_calculate(struct device *dev,
- const struct smiapp_pll_limits *limits,
- struct smiapp_pll *pll);
+int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits,
+ struct ccs_pll *pll);
-#endif /* SMIAPP_PLL_H */
+#endif /* CCS_PLL_H */
diff --git a/drivers/media/i2c/ccs/Kconfig b/drivers/media/i2c/ccs/Kconfig
index b4f8b10da420..59f35b33ddc1 100644
--- a/drivers/media/i2c/ccs/Kconfig
+++ b/drivers/media/i2c/ccs/Kconfig
@@ -4,7 +4,7 @@ config VIDEO_CCS
depends on I2C && VIDEO_V4L2 && HAVE_CLK
select MEDIA_CONTROLLER
select VIDEO_V4L2_SUBDEV_API
- select VIDEO_SMIAPP_PLL
+ select VIDEO_CCS_PLL
select V4L2_FWNODE
help
This is a generic driver for MIPI CCS, SMIA++ and SMIA compliant
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index cd8978c085d4..4e49195efb5f 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -357,7 +357,7 @@ static int ccs_read_frame_fmt(struct ccs_sensor *sensor)
static int ccs_pll_configure(struct ccs_sensor *sensor)
{
- struct smiapp_pll *pll = &sensor->pll;
+ struct ccs_pll *pll = &sensor->pll;
int rval;
rval = ccs_write(sensor, VT_PIX_CLK_DIV, pll->vt.pix_clk_div);
@@ -380,7 +380,7 @@ static int ccs_pll_configure(struct ccs_sensor *sensor)
rval = ccs_write(sensor, REQUESTED_LINK_RATE,
DIV_ROUND_UP(pll->op.sys_clk_freq_hz,
1000000 / 256 / 256));
- if (rval < 0 || sensor->pll.flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)
+ if (rval < 0 || sensor->pll.flags & CCS_PLL_FLAG_NO_OP_CLOCKS)
return rval;
rval = ccs_write(sensor, OP_PIX_CLK_DIV, pll->op.pix_clk_div);
@@ -390,10 +390,10 @@ static int ccs_pll_configure(struct ccs_sensor *sensor)
return ccs_write(sensor, OP_SYS_CLK_DIV, pll->op.sys_clk_div);
}
-static int ccs_pll_try(struct ccs_sensor *sensor, struct smiapp_pll *pll)
+static int ccs_pll_try(struct ccs_sensor *sensor, struct ccs_pll *pll)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- struct smiapp_pll_limits lim = {
+ struct ccs_pll_limits lim = {
.min_pre_pll_clk_div = CCS_LIM(sensor, MIN_PRE_PLL_CLK_DIV),
.max_pre_pll_clk_div = CCS_LIM(sensor, MAX_PRE_PLL_CLK_DIV),
.min_pll_ip_freq_hz = CCS_LIM(sensor, MIN_PLL_IP_CLK_FREQ_MHZ),
@@ -425,12 +425,12 @@ static int ccs_pll_try(struct ccs_sensor *sensor, struct smiapp_pll *pll)
.min_line_length_pck = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK),
};
- return smiapp_pll_calculate(&client->dev, &lim, pll);
+ return ccs_pll_calculate(&client->dev, &lim, pll);
}
static int ccs_pll_update(struct ccs_sensor *sensor)
{
- struct smiapp_pll *pll = &sensor->pll;
+ struct ccs_pll *pll = &sensor->pll;
int rval;
pll->binning_horizontal = sensor->binning_horizontal;
@@ -823,7 +823,7 @@ static void ccs_free_controls(struct ccs_sensor *sensor)
static int ccs_get_mbus_formats(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- struct smiapp_pll *pll = &sensor->pll;
+ struct ccs_pll *pll = &sensor->pll;
u8 compressed_max_bpp = 0;
unsigned int type, n;
unsigned int i, pixel_order;
@@ -3140,7 +3140,7 @@ static int ccs_probe(struct i2c_client *client)
!CCS_LIM(sensor, MIN_OP_PIX_CLK_DIV) ||
!CCS_LIM(sensor, MAX_OP_PIX_CLK_DIV)) {
/* No OP clock branch */
- sensor->pll.flags |= SMIAPP_PLL_FLAG_NO_OP_CLOCKS;
+ sensor->pll.flags |= CCS_PLL_FLAG_NO_OP_CLOCKS;
} else if (CCS_LIM(sensor, SCALING_CAPABILITY)
!= CCS_SCALING_CAPABILITY_NONE ||
CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY)
@@ -3157,7 +3157,7 @@ static int ccs_probe(struct i2c_client *client)
sensor->scale_m = CCS_LIM(sensor, SCALER_N_MIN);
/* prepare PLL configuration input values */
- sensor->pll.bus_type = SMIAPP_PLL_BUS_TYPE_CSI2;
+ sensor->pll.bus_type = CCS_PLL_BUS_TYPE_CSI2;
sensor->pll.csi2.lanes = sensor->hwcfg.lanes;
sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk;
sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN);
diff --git a/drivers/media/i2c/ccs/ccs-quirk.c b/drivers/media/i2c/ccs/ccs-quirk.c
index 07c5733b4244..8b4fa60044b2 100644
--- a/drivers/media/i2c/ccs/ccs-quirk.c
+++ b/drivers/media/i2c/ccs/ccs-quirk.c
@@ -190,7 +190,7 @@ static int jt8ev1_post_streamoff(struct ccs_sensor *sensor)
static int jt8ev1_init(struct ccs_sensor *sensor)
{
- sensor->pll.flags |= SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE;
+ sensor->pll.flags |= CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE;
return 0;
}
diff --git a/drivers/media/i2c/ccs/ccs.h b/drivers/media/i2c/ccs/ccs.h
index f60d1801c469..c8a9f4ee093e 100644
--- a/drivers/media/i2c/ccs/ccs.h
+++ b/drivers/media/i2c/ccs/ccs.h
@@ -21,7 +21,7 @@
#include "ccs-quirk.h"
#include "ccs-regs.h"
#include "ccs-reg-access.h"
-#include "../smiapp-pll.h"
+#include "../ccs-pll.h"
#include "smiapp-reg-defs.h"
/*
@@ -256,7 +256,7 @@ struct ccs_sensor {
struct ccs_module_info minfo;
- struct smiapp_pll pll;
+ struct ccs_pll pll;
/* Is a default format supported for a given BPP? */
unsigned long *valid_link_freqs;
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 020/106] dt-bindings: nokia,smia: Fix link-frequencies documentation
2020-10-07 8:44 [PATCH v2 000/106] CCS driver Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 021/106] dt-bindings: nokia,smia: Make vana-supply optional Sakari Ailus
` (7 subsequent siblings)
9 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media; +Cc: devicetree
The link-frequencies property belongs to the endpoint, not to the node
representing the device.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Acked-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/media/i2c/nokia,smia.txt | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt b/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
index 10ece8108081..6c45c79ef91f 100644
--- a/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
+++ b/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
@@ -20,8 +20,6 @@ Mandatory properties
dependent).
- clocks: External clock to the sensor
- clock-frequency: Frequency of the external clock to the sensor
-- link-frequencies: List of allowed data link frequencies. An array of
- 64-bit elements.
Optional properties
@@ -39,6 +37,8 @@ Endpoint node mandatory properties
----------------------------------
- data-lanes: <1..n>
+- link-frequencies: List of allowed data link frequencies. An array of
+ 64-bit elements.
Example
@@ -55,11 +55,13 @@ Example
clocks = <&omap3_isp 0>;
clock-frequency = <9600000>;
nokia,nvm-size = <512>; /* 8 * 64 */
- link-frequencies = /bits/ 64 <199200000 210000000 499200000>;
port {
smiapp_ep: endpoint {
data-lanes = <1 2>;
remote-endpoint = <&csi2a_ep>;
+ link-frequencies =
+ /bits/ 64 <199200000 210000000
+ 499200000>;
};
};
};
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 044/106] ccs-pll: Fix MODULE_LICENSE
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (34 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 043/106] smiapp-pll: Rename as ccs-pll Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 045/106] ccs: Change my e-mail address Sakari Ailus
` (60 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
Change MODULE_LICENSE to "GPL v2" as indicated by the SPDX tag.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index d2f0f7375f5c..58f5fe7062ae 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -477,4 +477,4 @@ EXPORT_SYMBOL_GPL(ccs_pll_calculate);
MODULE_AUTHOR("Sakari Ailus <sakari.ailus@iki.fi>");
MODULE_DESCRIPTION("Generic MIPI CCS/SMIA/SMIA++ PLL calculator");
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 021/106] dt-bindings: nokia,smia: Make vana-supply optional
2020-10-07 8:44 [PATCH v2 000/106] CCS driver Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 020/106] dt-bindings: nokia,smia: Fix link-frequencies documentation Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 022/106] dt-bindings: nokia,smia: Remove nokia,nvm-size property Sakari Ailus
` (6 subsequent siblings)
9 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media; +Cc: devicetree
vana-supply is optional in the spec, therefore make it optional in
bindings, too.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/media/i2c/nokia,smia.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt b/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
index 6c45c79ef91f..5ea4f799877b 100644
--- a/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
+++ b/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
@@ -16,8 +16,6 @@ Mandatory properties
- compatible: "nokia,smia"
- reg: I2C address (0x10, or an alternative address)
-- vana-supply: Analogue voltage supply (VANA), typically 2,8 volts (sensor
- dependent).
- clocks: External clock to the sensor
- clock-frequency: Frequency of the external clock to the sensor
@@ -31,6 +29,8 @@ Optional properties
- rotation: Integer property; valid values are 0 (sensor mounted upright)
and 180 (sensor mounted upside down). See
../video-interfaces.txt .
+- vana-supply: Analogue voltage supply (VANA), typically 2,8 volts (sensor
+ dependent).
Endpoint node mandatory properties
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 045/106] ccs: Change my e-mail address
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (35 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 044/106] ccs-pll: Fix MODULE_LICENSE Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 046/106] ccs: Add support for manufacturer regs from sensor and module files Sakari Ailus
` (59 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
Use my @linux.intel.com e-mail address in the CCS driver.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 4 ++--
drivers/media/i2c/ccs-pll.h | 2 +-
drivers/media/i2c/ccs/ccs-core.c | 6 +++---
drivers/media/i2c/ccs/ccs-quirk.c | 2 +-
drivers/media/i2c/ccs/ccs-quirk.h | 2 +-
drivers/media/i2c/ccs/ccs-reg-access.c | 2 +-
drivers/media/i2c/ccs/ccs-reg-access.h | 2 +-
drivers/media/i2c/ccs/ccs.h | 2 +-
8 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index 58f5fe7062ae..0d57bac1599a 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -6,7 +6,7 @@
*
* Copyright (C) 2020 Intel Corporation
* Copyright (C) 2011--2012 Nokia Corporation
- * Contact: Sakari Ailus <sakari.ailus@iki.fi>
+ * Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
*/
#include <linux/device.h>
@@ -475,6 +475,6 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits,
}
EXPORT_SYMBOL_GPL(ccs_pll_calculate);
-MODULE_AUTHOR("Sakari Ailus <sakari.ailus@iki.fi>");
+MODULE_AUTHOR("Sakari Ailus <sakari.ailus@linux.intel.com>");
MODULE_DESCRIPTION("Generic MIPI CCS/SMIA/SMIA++ PLL calculator");
MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h
index 88d641ee3fa1..07f7f9e8a1cc 100644
--- a/drivers/media/i2c/ccs-pll.h
+++ b/drivers/media/i2c/ccs-pll.h
@@ -6,7 +6,7 @@
*
* Copyright (C) 2020 Intel Corporation
* Copyright (C) 2012 Nokia Corporation
- * Contact: Sakari Ailus <sakari.ailus@iki.fi>
+ * Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
*/
#ifndef CCS_PLL_H
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 4e49195efb5f..5d7c5ece578d 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -6,7 +6,7 @@
*
* Copyright (C) 2020 Intel Corporation
* Copyright (C) 2010--2012 Nokia Corporation
- * Contact: Sakari Ailus <sakari.ailus@iki.fi>
+ * Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
*
* Based on smiapp driver by Vimarsh Zutshi
* Based on jt8ev1.c by Vimarsh Zutshi
@@ -1162,7 +1162,7 @@ static int ccs_setup_flash_strobe(struct ccs_sensor *sensor)
* do not change, or if you do at least know what you're
* doing. :-)
*
- * Sakari Ailus <sakari.ailus@iki.fi> 2010-10-25
+ * Sakari Ailus <sakari.ailus@linux.intel.com> 2010-10-25
*
* flash_strobe_length [us] / 10^6 = (tFlash_strobe_width_ctrl
* / EXTCLK freq [Hz]) * flash_strobe_adjustment
@@ -3323,7 +3323,7 @@ static void ccs_module_cleanup(void)
module_init(ccs_module_init);
module_exit(ccs_module_cleanup);
-MODULE_AUTHOR("Sakari Ailus <sakari.ailus@iki.fi>");
+MODULE_AUTHOR("Sakari Ailus <sakari.ailus@linux.intel.com>");
MODULE_DESCRIPTION("Generic MIPI CCS/SMIA/SMIA++ camera sensor driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("smiapp");
diff --git a/drivers/media/i2c/ccs/ccs-quirk.c b/drivers/media/i2c/ccs/ccs-quirk.c
index 8b4fa60044b2..4fe8c6f70579 100644
--- a/drivers/media/i2c/ccs/ccs-quirk.c
+++ b/drivers/media/i2c/ccs/ccs-quirk.c
@@ -6,7 +6,7 @@
*
* Copyright (C) 2020 Intel Corporation
* Copyright (C) 2011--2012 Nokia Corporation
- * Contact: Sakari Ailus <sakari.ailus@iki.fi>
+ * Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
*/
#include <linux/delay.h>
diff --git a/drivers/media/i2c/ccs/ccs-quirk.h b/drivers/media/i2c/ccs/ccs-quirk.h
index 3e7779e2fc4b..6b4ec4beaba0 100644
--- a/drivers/media/i2c/ccs/ccs-quirk.h
+++ b/drivers/media/i2c/ccs/ccs-quirk.h
@@ -6,7 +6,7 @@
*
* Copyright (C) 2020 Intel Corporation
* Copyright (C) 2011--2012 Nokia Corporation
- * Contact: Sakari Ailus <sakari.ailus@iki.fi>
+ * Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
*/
#ifndef __CCS_QUIRK__
diff --git a/drivers/media/i2c/ccs/ccs-reg-access.c b/drivers/media/i2c/ccs/ccs-reg-access.c
index 91ccbca11577..aad2727570ec 100644
--- a/drivers/media/i2c/ccs/ccs-reg-access.c
+++ b/drivers/media/i2c/ccs/ccs-reg-access.c
@@ -6,7 +6,7 @@
*
* Copyright (C) 2020 Intel Corporation
* Copyright (C) 2011--2012 Nokia Corporation
- * Contact: Sakari Ailus <sakari.ailus@iki.fi>
+ * Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
*/
#include <asm/unaligned.h>
diff --git a/drivers/media/i2c/ccs/ccs-reg-access.h b/drivers/media/i2c/ccs/ccs-reg-access.h
index 5f6ff9c57698..cfad2e520fe2 100644
--- a/drivers/media/i2c/ccs/ccs-reg-access.h
+++ b/drivers/media/i2c/ccs/ccs-reg-access.h
@@ -6,7 +6,7 @@
*
* Copyright (C) 2020 Intel Corporation
* Copyright (C) 2011--2012 Nokia Corporation
- * Contact: Sakari Ailus <sakari.ailus@iki.fi>
+ * Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
*/
#ifndef SMIAPP_REGS_H
diff --git a/drivers/media/i2c/ccs/ccs.h b/drivers/media/i2c/ccs/ccs.h
index c8a9f4ee093e..6b07e4143ff0 100644
--- a/drivers/media/i2c/ccs/ccs.h
+++ b/drivers/media/i2c/ccs/ccs.h
@@ -6,7 +6,7 @@
*
* Copyright (C) 2020 Intel Corporation
* Copyright (C) 2010--2012 Nokia Corporation
- * Contact: Sakari Ailus <sakari.ailus@iki.fi>
+ * Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
*/
#ifndef __CCS_H__
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 022/106] dt-bindings: nokia,smia: Remove nokia,nvm-size property
2020-10-07 8:44 [PATCH v2 000/106] CCS driver Sakari Ailus
` (2 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 021/106] dt-bindings: nokia,smia: Make vana-supply optional Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-10-07 16:04 ` Rob Herring
2020-10-07 8:45 ` [PATCH v2 023/106] dt-bindings: nokia,smia: Convert to YAML Sakari Ailus
` (5 subsequent siblings)
9 siblings, 1 reply; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media; +Cc: devicetree
nokia,nvm-size property was removed from the bindings but it was left in
the example. Remove it from the example, too.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
Documentation/devicetree/bindings/media/i2c/nokia,smia.txt | 1 -
1 file changed, 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt b/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
index 5ea4f799877b..5f39a7070c51 100644
--- a/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
+++ b/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
@@ -54,7 +54,6 @@ Example
vana-supply = <&vaux3>;
clocks = <&omap3_isp 0>;
clock-frequency = <9600000>;
- nokia,nvm-size = <512>; /* 8 * 64 */
port {
smiapp_ep: endpoint {
data-lanes = <1 2>;
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 046/106] ccs: Add support for manufacturer regs from sensor and module files
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (36 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 045/106] ccs: Change my e-mail address Sakari Ailus
@ 2020-10-07 8:44 ` Sakari Ailus
2020-11-05 11:34 ` Mauro Carvalho Chehab
2020-10-07 8:45 ` [PATCH v2 047/106] ccs: Use static data read-only registers Sakari Ailus
` (58 subsequent siblings)
96 siblings, 1 reply; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:44 UTC (permalink / raw)
To: linux-media
Write manufacturer specific registers (MSRs) from file to the sensor on
sensor power-on.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 23 +++++++
drivers/media/i2c/ccs/ccs-reg-access.c | 94 ++++++++++++++++++++------
drivers/media/i2c/ccs/ccs-reg-access.h | 2 +
3 files changed, 97 insertions(+), 22 deletions(-)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 5d7c5ece578d..6c2f18abc921 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -1272,6 +1272,21 @@ static int ccs_setup_flash_strobe(struct ccs_sensor *sensor)
* Power management
*/
+static int ccs_write_msr_regs(struct ccs_sensor *sensor)
+{
+ int rval;
+
+ rval = ccs_write_data_regs(sensor,
+ sensor->sdata.sensor_manufacturer_regs,
+ sensor->sdata.num_sensor_manufacturer_regs);
+ if (rval)
+ return rval;
+
+ return ccs_write_data_regs(sensor,
+ sensor->mdata.module_manufacturer_regs,
+ sensor->mdata.num_module_manufacturer_regs);
+}
+
static int ccs_power_on(struct device *dev)
{
struct v4l2_subdev *subdev = dev_get_drvdata(dev);
@@ -1377,6 +1392,10 @@ static int ccs_power_on(struct device *dev)
if (rval < 0)
goto out_cci_addr_fail;
+ rval = ccs_write_msr_regs(sensor);
+ if (rval)
+ goto out_cci_addr_fail;
+
rval = ccs_call_quirk(sensor, post_poweron);
if (rval) {
dev_err(dev, "post_poweron quirks failed\n");
@@ -3205,6 +3224,10 @@ static int ccs_probe(struct i2c_client *client)
if (rval < 0)
goto out_media_entity_cleanup;
+ rval = ccs_write_msr_regs(sensor);
+ if (rval)
+ goto out_media_entity_cleanup;
+
pm_runtime_set_active(&client->dev);
pm_runtime_get_noresume(&client->dev);
pm_runtime_enable(&client->dev);
diff --git a/drivers/media/i2c/ccs/ccs-reg-access.c b/drivers/media/i2c/ccs/ccs-reg-access.c
index aad2727570ec..9fda16b221a7 100644
--- a/drivers/media/i2c/ccs/ccs-reg-access.c
+++ b/drivers/media/i2c/ccs/ccs-reg-access.c
@@ -236,12 +236,38 @@ int ccs_read_addr_noconv(struct ccs_sensor *sensor, u32 reg, u32 *val)
return ccs_read_addr_raw(sensor, reg, val, false, true, false);
}
+static int ccs_write_retry(struct i2c_client *client, struct i2c_msg *msg)
+{
+ unsigned int retries;
+ int r;
+
+ for (retries = 0; retries < 5; retries++) {
+ /*
+ * Due to unknown reason sensor stops responding. This
+ * loop is a temporaty solution until the root cause
+ * is found.
+ */
+ r = i2c_transfer(client->adapter, msg, 1);
+ if (r != 1) {
+ usleep_range(2000, 2000);
+ continue;
+ }
+
+ if (retries)
+ dev_err(&client->dev,
+ "sensor i2c stall encountered. retries: %d\n",
+ retries);
+ return 0;
+ }
+
+ return r;
+}
+
int ccs_write_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 val)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
struct i2c_msg msg;
unsigned char data[6];
- unsigned int retries;
unsigned int len = ccs_reg_width(reg);
int r;
@@ -256,27 +282,11 @@ int ccs_write_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 val)
put_unaligned_be16(CCS_REG_ADDR(reg), data);
put_unaligned_be32(val << (8 * (sizeof(val) - len)), data + 2);
- for (retries = 0; retries < 5; retries++) {
- /*
- * Due to unknown reason sensor stops responding. This
- * loop is a temporaty solution until the root cause
- * is found.
- */
- r = i2c_transfer(client->adapter, &msg, 1);
- if (r == 1) {
- if (retries)
- dev_err(&client->dev,
- "sensor i2c stall encountered. retries: %d\n",
- retries);
- return 0;
- }
-
- usleep_range(2000, 2000);
- }
-
- dev_err(&client->dev,
- "wrote 0x%x to offset 0x%x error %d\n", val,
- CCS_REG_ADDR(reg), r);
+ r = ccs_write_retry(client, &msg);
+ if (r)
+ dev_err(&client->dev,
+ "wrote 0x%x to offset 0x%x error %d\n", val,
+ CCS_REG_ADDR(reg), r);
return r;
}
@@ -297,3 +307,43 @@ int ccs_write_addr(struct ccs_sensor *sensor, u32 reg, u32 val)
return ccs_write_addr_no_quirk(sensor, reg, val);
}
+
+#define MAX_WRITE_LEN 32U
+
+int ccs_write_data_regs(struct ccs_sensor *sensor, struct ccs_reg *regs,
+ size_t num_regs)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ unsigned char buf[2 + MAX_WRITE_LEN];
+ struct i2c_msg msg = {
+ .addr = client->addr,
+ .buf = buf,
+ };
+ size_t i;
+
+ for (i = 0; i < num_regs; i++, regs++) {
+ unsigned char *regdata = regs->value;
+ unsigned int j;
+
+ for (j = 0; j < regs->len;
+ j += msg.len - 2, regdata += msg.len - 2) {
+ int rval;
+
+ msg.len = min(regs->len - j, MAX_WRITE_LEN);
+
+ put_unaligned_be16(regs->addr + j, buf);
+ memcpy(buf + 2, regdata, msg.len);
+ msg.len += 2;
+
+ rval = ccs_write_retry(client, &msg);
+ if (rval) {
+ dev_err(&client->dev,
+ "error writing %u octets to address 0x%4.4x\n",
+ msg.len, regs->addr + j);
+ return rval;
+ }
+ }
+ }
+
+ return 0;
+}
diff --git a/drivers/media/i2c/ccs/ccs-reg-access.h b/drivers/media/i2c/ccs/ccs-reg-access.h
index cfad2e520fe2..78c43f92d99a 100644
--- a/drivers/media/i2c/ccs/ccs-reg-access.h
+++ b/drivers/media/i2c/ccs/ccs-reg-access.h
@@ -27,6 +27,8 @@ int ccs_read_addr_8only(struct ccs_sensor *sensor, u32 reg, u32 *val);
int ccs_read_addr_noconv(struct ccs_sensor *sensor, u32 reg, u32 *val);
int ccs_write_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 val);
int ccs_write_addr(struct ccs_sensor *sensor, u32 reg, u32 val);
+int ccs_write_data_regs(struct ccs_sensor *sensor, struct ccs_reg *regs,
+ size_t num_regs);
unsigned int ccs_reg_width(u32 reg);
u32 ccs_reg_conv(struct ccs_sensor *sensor, u32 reg, u32 val);
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 023/106] dt-bindings: nokia,smia: Convert to YAML
2020-10-07 8:44 [PATCH v2 000/106] CCS driver Sakari Ailus
` (3 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 022/106] dt-bindings: nokia,smia: Remove nokia,nvm-size property Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 16:06 ` Rob Herring
2020-10-07 8:45 ` [PATCH v2 024/106] dt-bindings: nokia,smia: Use better active polarity for reset Sakari Ailus
` (4 subsequent siblings)
9 siblings, 1 reply; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media; +Cc: devicetree
Convert nokia,smia DT bindings to YAML.
Also add explicit license to bindings.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
.../bindings/media/i2c/nokia,smia.txt | 67 -----------
.../bindings/media/i2c/nokia,smia.yaml | 106 ++++++++++++++++++
MAINTAINERS | 2 +-
3 files changed, 107 insertions(+), 68 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
create mode 100644 Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml
diff --git a/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt b/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
deleted file mode 100644
index 5f39a7070c51..000000000000
--- a/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
+++ /dev/null
@@ -1,67 +0,0 @@
-SMIA/SMIA++ sensor
-
-SMIA (Standard Mobile Imaging Architecture) is an image sensor standard
-defined jointly by Nokia and ST. SMIA++, defined by Nokia, is an extension
-of that. These definitions are valid for both types of sensors.
-
-More detailed documentation can be found in
-Documentation/devicetree/bindings/media/video-interfaces.txt .
-
-The device node should contain a "port" node which may contain one or more
-endpoint nodes, in accordance with video interface bindings defined in
-Documentation/devicetree/bindings/media/video-interfaces.txt .
-
-Mandatory properties
---------------------
-
-- compatible: "nokia,smia"
-- reg: I2C address (0x10, or an alternative address)
-- clocks: External clock to the sensor
-- clock-frequency: Frequency of the external clock to the sensor
-
-
-Optional properties
--------------------
-
-- reset-gpios: XSHUTDOWN GPIO
-- flash-leds: See ../video-interfaces.txt
-- lens-focus: See ../video-interfaces.txt
-- rotation: Integer property; valid values are 0 (sensor mounted upright)
- and 180 (sensor mounted upside down). See
- ../video-interfaces.txt .
-- vana-supply: Analogue voltage supply (VANA), typically 2,8 volts (sensor
- dependent).
-
-
-Endpoint node mandatory properties
-----------------------------------
-
-- data-lanes: <1..n>
-- link-frequencies: List of allowed data link frequencies. An array of
- 64-bit elements.
-
-
-Example
--------
-
-&i2c2 {
- clock-frequency = <400000>;
-
- camera-sensor@10 {
- compatible = "nokia,smia";
- reg = <0x10>;
- reset-gpios = <&gpio3 20 0>;
- vana-supply = <&vaux3>;
- clocks = <&omap3_isp 0>;
- clock-frequency = <9600000>;
- port {
- smiapp_ep: endpoint {
- data-lanes = <1 2>;
- remote-endpoint = <&csi2a_ep>;
- link-frequencies =
- /bits/ 64 <199200000 210000000
- 499200000>;
- };
- };
- };
-};
diff --git a/Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml b/Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml
new file mode 100644
index 000000000000..ee552489fa2b
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2014--2020 Intel Corporation
+
+$id: http://devicetree.org/schemas/media/i2c/nokia,smia.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SMIA/SMIA++ sensor
+
+maintainers:
+ - Sakari Ailus <sakari.ailus@linux.intel.com>
+
+description:
+
+ SMIA (Standard Mobile Imaging Architecture) is an image sensor standard
+ defined jointly by Nokia and ST. SMIA++, defined by Nokia, is an extension of
+ that. These definitions are valid for both types of sensors.
+
+ More detailed documentation can be found in
+ Documentation/devicetree/bindings/media/video-interfaces.txt .
+
+properties:
+ compatible:
+ const: nokia,smia
+
+ reg:
+ maxItems: 1
+
+ vana-supply:
+ description: Analogue voltage supply (VANA), typically 2,8 volts (sensor
+ dependent).
+ maxItems: 1
+
+ clocks:
+ description: External clock to the sensor.
+ maxItems: 1
+
+ clock-frequency:
+ description: Frequency of the external clock to the sensor in Hz.
+
+ reset-gpios:
+ description: Reset GPIO. Also commonly called XSHUTDOWN in hardware
+ documentation.
+ maxItems: 1
+
+ flash-leds:
+ description: Flash LED phandles. See ../video-interfaces.txt for details.
+
+ lens-focus:
+ description: Lens focus controller phandles. See ../video-interfaces.txt
+ for details.
+
+ rotation:
+ description: Rotation of the sensor. See ../video-interfaces.txt for
+ details.
+ enum: [ 0, 180 ]
+
+ port:
+ type: object
+ properties:
+ endpoint:
+ type: object
+ properties:
+ link-frequencies:
+ $ref: /schemas/types.yaml#/definitions/uint64-array
+ description: List of allowed data link frequencies.
+ data-lanes:
+ minItems: 1
+ maxItems: 8
+ required:
+ - link-frequencies
+ - data-lanes
+
+required:
+ - compatible
+ - reg
+ - clock-frequency
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clock-frequency = <400000>;
+
+ camera-sensor@10 {
+ compatible = "nokia,smia";
+ reg = <0x10>;
+ reset-gpios = <&gpio3 20 0>;
+ vana-supply = <&vaux3>;
+ clocks = <&omap3_isp 0>;
+ clock-frequency = <9600000>;
+ port {
+ smiapp_ep: endpoint {
+ data-lanes = <1 2>;
+ remote-endpoint = <&csi2a_ep>;
+ link-frequencies = /bits/ 64 <199200000 210000000
+ 499200000>;
+ };
+ };
+ };
+ };
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index f604993cead9..ec99e94e2273 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11564,7 +11564,7 @@ MIPI CCS, SMIA AND SMIA++ IMAGE SENSOR DRIVER
M: Sakari Ailus <sakari.ailus@linux.intel.com>
L: linux-media@vger.kernel.org
S: Maintained
-F: Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
+F: Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml
F: drivers/media/i2c/ccs/
F: drivers/media/i2c/smiapp-pll.c
F: drivers/media/i2c/smiapp-pll.h
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 047/106] ccs: Use static data read-only registers
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (37 preceding siblings ...)
2020-10-07 8:44 ` [PATCH v2 046/106] ccs: Add support for manufacturer regs from sensor and module files Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 048/106] ccs: Clean up runtime PM usage Sakari Ailus
` (57 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Access read-only registers from CCS static data.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-reg-access.c | 64 ++++++++++++++++++++++++--
1 file changed, 60 insertions(+), 4 deletions(-)
diff --git a/drivers/media/i2c/ccs/ccs-reg-access.c b/drivers/media/i2c/ccs/ccs-reg-access.c
index 9fda16b221a7..02af2b0abdaf 100644
--- a/drivers/media/i2c/ccs/ccs-reg-access.c
+++ b/drivers/media/i2c/ccs/ccs-reg-access.c
@@ -198,11 +198,67 @@ static int __ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val,
return 0;
}
+static int __ccs_read_data(struct ccs_reg *regs, size_t num_regs,
+ u32 reg, u32 *val)
+{
+ unsigned int width = ccs_reg_width(reg);
+ size_t i;
+
+ for (i = 0; i < num_regs; i++, regs++) {
+ uint8_t *data;
+
+ if (regs->addr + regs->len < CCS_REG_ADDR(reg) + width)
+ continue;
+
+ if (regs->addr > CCS_REG_ADDR(reg))
+ break;
+
+ data = ®s->value[CCS_REG_ADDR(reg) - regs->addr];
+
+ switch (width) {
+ case sizeof(uint8_t):
+ *val = *data;
+ break;
+ case sizeof(uint16_t):
+ *val = get_unaligned_be16(data);
+ break;
+ case sizeof(uint32_t):
+ *val = get_unaligned_be32(data);
+ break;
+ default:
+ WARN_ON(1);
+ return -EINVAL;
+ }
+
+ return 0;
+ }
+
+ return -ENOENT;
+}
+
+static int ccs_read_data(struct ccs_sensor *sensor, u32 reg, u32 *val)
+{
+ if (!__ccs_read_data(sensor->sdata.sensor_read_only_regs,
+ sensor->sdata.num_sensor_read_only_regs,
+ reg, val))
+ return 0;
+
+ return __ccs_read_data(sensor->mdata.module_read_only_regs,
+ sensor->mdata.num_module_read_only_regs,
+ reg, val);
+}
+
static int ccs_read_addr_raw(struct ccs_sensor *sensor, u32 reg, u32 *val,
- bool force8, bool quirk, bool conv)
+ bool force8, bool quirk, bool conv, bool data)
{
int rval;
+ if (data) {
+ rval = ccs_read_data(sensor, reg, val);
+ if (!rval)
+ return 0;
+ }
+
if (quirk) {
*val = 0;
rval = ccs_call_quirk(sensor, reg_access, false, ®, val);
@@ -223,17 +279,17 @@ static int ccs_read_addr_raw(struct ccs_sensor *sensor, u32 reg, u32 *val,
int ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val)
{
- return ccs_read_addr_raw(sensor, reg, val, false, true, true);
+ return ccs_read_addr_raw(sensor, reg, val, false, true, true, true);
}
int ccs_read_addr_8only(struct ccs_sensor *sensor, u32 reg, u32 *val)
{
- return ccs_read_addr_raw(sensor, reg, val, true, true, true);
+ return ccs_read_addr_raw(sensor, reg, val, true, true, true, true);
}
int ccs_read_addr_noconv(struct ccs_sensor *sensor, u32 reg, u32 *val)
{
- return ccs_read_addr_raw(sensor, reg, val, false, true, false);
+ return ccs_read_addr_raw(sensor, reg, val, false, true, false, true);
}
static int ccs_write_retry(struct i2c_client *client, struct i2c_msg *msg)
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 024/106] dt-bindings: nokia,smia: Use better active polarity for reset
2020-10-07 8:44 [PATCH v2 000/106] CCS driver Sakari Ailus
` (4 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 023/106] dt-bindings: nokia,smia: Convert to YAML Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 025/106] dt-bindings: nokia,smia: Amend SMIA bindings with MIPI CCS support Sakari Ailus
` (3 subsequent siblings)
9 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media; +Cc: devicetree
Generally reset signal is active low on camera sensors. The example had it
high. Make it low, and use GPIO_ACTIVE_LOW in gpio.h for that.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml b/Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml
index ee552489fa2b..47df08338a42 100644
--- a/Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml
+++ b/Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml
@@ -80,6 +80,8 @@ additionalProperties: false
examples:
- |
+ #include <dt-bindings/gpio/gpio.h>
+
i2c2 {
#address-cells = <1>;
#size-cells = <0>;
@@ -89,7 +91,7 @@ examples:
camera-sensor@10 {
compatible = "nokia,smia";
reg = <0x10>;
- reset-gpios = <&gpio3 20 0>;
+ reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
vana-supply = <&vaux3>;
clocks = <&omap3_isp 0>;
clock-frequency = <9600000>;
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 048/106] ccs: Clean up runtime PM usage
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (38 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 047/106] ccs: Use static data read-only registers Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 049/106] ccs: Wrap long lines, unwrap short ones Sakari Ailus
` (56 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
If pm_runtime_get_sync() fails, there's no need to set the device active
again. Also, in the same case to return the usage_count to zero,
pm_runtime_put_noidle() is enough.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 6c2f18abc921..b762f16531df 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -1619,8 +1619,6 @@ static int ccs_pm_get_init(struct ccs_sensor *sensor)
rval = pm_runtime_get_sync(&client->dev);
if (rval < 0) {
- if (rval != -EBUSY && rval != -EAGAIN)
- pm_runtime_set_active(&client->dev);
pm_runtime_put_noidle(&client->dev);
return rval;
@@ -2836,9 +2834,8 @@ static int __maybe_unused ccs_suspend(struct device *dev)
rval = pm_runtime_get_sync(dev);
if (rval < 0) {
- if (rval != -EBUSY && rval != -EAGAIN)
- pm_runtime_set_active(&client->dev);
- pm_runtime_put(dev);
+ pm_runtime_put_noidle(dev);
+
return -EAGAIN;
}
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 025/106] dt-bindings: nokia,smia: Amend SMIA bindings with MIPI CCS support
2020-10-07 8:44 [PATCH v2 000/106] CCS driver Sakari Ailus
` (5 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 024/106] dt-bindings: nokia,smia: Use better active polarity for reset Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 16:07 ` Rob Herring
2020-10-07 8:45 ` [PATCH v2 026/106] dt-bindings: mipi-ccs: Add bus-type for C-PHY support Sakari Ailus
` (2 subsequent siblings)
9 siblings, 1 reply; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media; +Cc: devicetree
Amend the existing SMIA bindings by adding MIPI CCS support, with separate
compatible strings for CCS 1.0 and CCS 1.1. Rename the old bindings
accordingly as CCS is the current standard.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
.../i2c/{nokia,smia.yaml => mipi-ccs.yaml} | 23 ++++++++++++++-----
MAINTAINERS | 2 +-
2 files changed, 18 insertions(+), 7 deletions(-)
rename Documentation/devicetree/bindings/media/i2c/{nokia,smia.yaml => mipi-ccs.yaml} (81%)
diff --git a/Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml b/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml
similarity index 81%
rename from Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml
rename to Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml
index 47df08338a42..a386ee246956 100644
--- a/Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml
+++ b/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml
@@ -1,26 +1,37 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2014--2020 Intel Corporation
-$id: http://devicetree.org/schemas/media/i2c/nokia,smia.yaml#
+$id: http://devicetree.org/schemas/media/i2c/mipi-ccs.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: SMIA/SMIA++ sensor
+title: MIPI CCS, SMIA++ and SMIA compliant camera sensors
maintainers:
- Sakari Ailus <sakari.ailus@linux.intel.com>
description:
+ CCS (Camera Command Set) is a raw Bayer camera sensor standard defined by the
+ MIPI Alliance; see
+ <URL:https://www.mipi.org/specifications/camera-command-set>.
+
SMIA (Standard Mobile Imaging Architecture) is an image sensor standard
defined jointly by Nokia and ST. SMIA++, defined by Nokia, is an extension of
- that. These definitions are valid for both types of sensors.
+ that.
More detailed documentation can be found in
Documentation/devicetree/bindings/media/video-interfaces.txt .
properties:
compatible:
- const: nokia,smia
+ oneOf:
+ - items:
+ - const: mipi-ccs-1.1
+ - const: mipi-ccs
+ - items:
+ - const: mipi-ccs-1.0
+ - const: mipi-ccs
+ - const: nokia,smia
reg:
maxItems: 1
@@ -89,14 +100,14 @@ examples:
clock-frequency = <400000>;
camera-sensor@10 {
- compatible = "nokia,smia";
+ compatible = "mipi-ccs-1.0", "mipi-ccs";
reg = <0x10>;
reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
vana-supply = <&vaux3>;
clocks = <&omap3_isp 0>;
clock-frequency = <9600000>;
port {
- smiapp_ep: endpoint {
+ ccs_ep: endpoint {
data-lanes = <1 2>;
remote-endpoint = <&csi2a_ep>;
link-frequencies = /bits/ 64 <199200000 210000000
diff --git a/MAINTAINERS b/MAINTAINERS
index ec99e94e2273..135d41b823a4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11564,7 +11564,7 @@ MIPI CCS, SMIA AND SMIA++ IMAGE SENSOR DRIVER
M: Sakari Ailus <sakari.ailus@linux.intel.com>
L: linux-media@vger.kernel.org
S: Maintained
-F: Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml
+F: Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml
F: drivers/media/i2c/ccs/
F: drivers/media/i2c/smiapp-pll.c
F: drivers/media/i2c/smiapp-pll.h
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 049/106] ccs: Wrap long lines, unwrap short ones
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (39 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 048/106] ccs: Clean up runtime PM usage Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 050/106] ccs: Add device compatible identifiers for telling SMIA and CCS apart Sakari Ailus
` (55 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Over the years (and renaming) some lines that may well be wrapped ended up
being over 80 characters, likewise there are shorter lines that can be
merged. Do that.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 45 +++++++++++++-------------------
1 file changed, 18 insertions(+), 27 deletions(-)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index b762f16531df..5f1665f08b9f 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -651,8 +651,7 @@ static int ccs_set_ctrl(struct v4l2_ctrl *ctrl)
break;
case V4L2_CID_HBLANK:
rval = ccs_write(sensor, LINE_LENGTH_PCK,
- sensor->pixel_array->crop[
- CCS_PA_PAD_SRC].width
+ sensor->pixel_array->crop[CCS_PA_PAD_SRC].width
+ ctrl->val);
break;
@@ -983,15 +982,13 @@ static void ccs_update_blanking(struct ccs_sensor *sensor)
min = max_t(int,
CCS_LIM(sensor, MIN_FRAME_BLANKING_LINES),
- min_fll -
- sensor->pixel_array->crop[CCS_PA_PAD_SRC].height);
+ min_fll - sensor->pixel_array->crop[CCS_PA_PAD_SRC].height);
max = max_fll - sensor->pixel_array->crop[CCS_PA_PAD_SRC].height;
__v4l2_ctrl_modify_range(vblank, min, max, vblank->step, min);
min = max_t(int,
- min_llp -
- sensor->pixel_array->crop[CCS_PA_PAD_SRC].width,
+ min_llp - sensor->pixel_array->crop[CCS_PA_PAD_SRC].width,
min_lbp);
max = max_llp - sensor->pixel_array->crop[CCS_PA_PAD_SRC].width;
@@ -1778,7 +1775,8 @@ static void ccs_get_crop_compose(struct v4l2_subdev *subdev,
} else {
if (crops) {
for (i = 0; i < subdev->entity.num_pads; i++)
- crops[i] = v4l2_subdev_get_try_crop(subdev, cfg, i);
+ crops[i] = v4l2_subdev_get_try_crop(subdev,
+ cfg, i);
}
if (comps)
*comps = v4l2_subdev_get_try_compose(subdev, cfg,
@@ -1803,8 +1801,7 @@ static void ccs_propagate(struct v4l2_subdev *subdev,
comp->height = crops[CCS_PAD_SINK]->height;
if (which == V4L2_SUBDEV_FORMAT_ACTIVE) {
if (ssd == sensor->scaler) {
- sensor->scale_m =
- CCS_LIM(sensor, SCALER_N_MIN);
+ sensor->scale_m = CCS_LIM(sensor, SCALER_N_MIN);
sensor->scaling_mode =
CCS_SCALING_MODE_NO_SCALING;
} else if (ssd == sensor->binner) {
@@ -2230,9 +2227,11 @@ static int ccs_set_crop(struct v4l2_subdev *subdev,
if (sel->pad == ssd->sink_pad) {
_r.left = 0;
_r.top = 0;
- _r.width = v4l2_subdev_get_try_format(subdev, cfg, sel->pad)
+ _r.width = v4l2_subdev_get_try_format(subdev, cfg,
+ sel->pad)
->width;
- _r.height = v4l2_subdev_get_try_format(subdev, cfg, sel->pad)
+ _r.height = v4l2_subdev_get_try_format(subdev, cfg,
+ sel->pad)
->height;
src_size = &_r;
} else {
@@ -2350,11 +2349,9 @@ static int ccs_set_selection(struct v4l2_subdev *subdev,
sel->r.width = CCS_ALIGN_DIM(sel->r.width, sel->flags);
sel->r.height = CCS_ALIGN_DIM(sel->r.height, sel->flags);
- sel->r.width = max_t(unsigned int,
- CCS_LIM(sensor, MIN_X_OUTPUT_SIZE),
+ sel->r.width = max_t(unsigned int, CCS_LIM(sensor, MIN_X_OUTPUT_SIZE),
sel->r.width);
- sel->r.height = max_t(unsigned int,
- CCS_LIM(sensor, MIN_Y_OUTPUT_SIZE),
+ sel->r.height = max_t(unsigned int, CCS_LIM(sensor, MIN_Y_OUTPUT_SIZE),
sel->r.height);
switch (sel->target) {
@@ -2607,8 +2604,7 @@ static int ccs_identify_module(struct ccs_sensor *sensor)
dev_warn(&client->dev,
"no quirks for this module; let's hope it's fully compliant\n");
- dev_dbg(&client->dev, "the sensor is called %s\n",
- minfo->name);
+ dev_dbg(&client->dev, "the sensor is called %s\n", minfo->name);
return 0;
}
@@ -2628,19 +2624,15 @@ static int ccs_register_subdev(struct ccs_sensor *sensor,
if (!sink_ssd)
return 0;
- rval = media_entity_pads_init(&ssd->sd.entity,
- ssd->npads, ssd->pads);
+ rval = media_entity_pads_init(&ssd->sd.entity, ssd->npads, ssd->pads);
if (rval) {
- dev_err(&client->dev,
- "media_entity_pads_init failed\n");
+ dev_err(&client->dev, "media_entity_pads_init failed\n");
return rval;
}
- rval = v4l2_device_register_subdev(sensor->src->sd.v4l2_dev,
- &ssd->sd);
+ rval = v4l2_device_register_subdev(sensor->src->sd.v4l2_dev, &ssd->sd);
if (rval) {
- dev_err(&client->dev,
- "v4l2_device_register_subdev failed\n");
+ dev_err(&client->dev, "v4l2_device_register_subdev failed\n");
return rval;
}
@@ -2648,8 +2640,7 @@ static int ccs_register_subdev(struct ccs_sensor *sensor,
&sink_ssd->sd.entity, sink_pad,
link_flags);
if (rval) {
- dev_err(&client->dev,
- "media_create_pad_link failed\n");
+ dev_err(&client->dev, "media_create_pad_link failed\n");
v4l2_device_unregister_subdev(&ssd->sd);
return rval;
}
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 026/106] dt-bindings: mipi-ccs: Add bus-type for C-PHY support
2020-10-07 8:44 [PATCH v2 000/106] CCS driver Sakari Ailus
` (6 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 025/106] dt-bindings: nokia,smia: Amend SMIA bindings with MIPI CCS support Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 13:52 ` Rob Herring
2020-10-07 8:45 ` [PATCH v2 053/106] dt-bindings: mipi,ccs: Don't mention vana voltage Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 054/106] dt-bindings: mipi,ccs: Add vcore and vio supplies Sakari Ailus
9 siblings, 1 reply; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media; +Cc: devicetree
The bus-type property is required for C-PHY support. Add it, including
values for CCP2 and CSI-2 D-PHY.
Also require the bus-type property. Effectively all new sensors are MIPI
D-PHY or C-PHY that cannot be told apart without the bus-type property.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
.../devicetree/bindings/media/i2c/mipi-ccs.yaml | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml b/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml
index a386ee246956..b641debcd6a2 100644
--- a/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml
+++ b/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml
@@ -77,9 +77,17 @@ properties:
data-lanes:
minItems: 1
maxItems: 8
+ bus-type:
+ description: The type of the data bus.
+ oneOf:
+ - const: 1 # CSI-2 C-PHY
+ - const: 3 # CCP2
+ - const: 4 # CSI-2 D-PHY
+
required:
- link-frequencies
- data-lanes
+ - bus-type
required:
- compatible
@@ -112,6 +120,7 @@ examples:
remote-endpoint = <&csi2a_ep>;
link-frequencies = /bits/ 64 <199200000 210000000
499200000>;
+ bus-type = <4>;
};
};
};
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 050/106] ccs: Add device compatible identifiers for telling SMIA and CCS apart
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (40 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 049/106] ccs: Wrap long lines, unwrap short ones Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 051/106] ccs: Use longer pre-I²C sleep for CCS compliant devices Sakari Ailus
` (54 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Add device data specific to DT compatible ID to tell SMIA and CCS devices
apart already in power-up.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 20 ++++++++++++++++----
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 5f1665f08b9f..940b5327a388 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -59,6 +59,12 @@ static const struct ccs_module_ident ccs_module_idents[] = {
CCS_IDENT_LQ(0x10, 0x4241, -1, "imx125es", &smiapp_imx125es_quirk),
};
+#define CCS_DEVICE_FLAG_IS_SMIA BIT(0)
+
+struct ccs_device {
+ unsigned char flags;
+};
+
/*
*
* Dynamic Capability Identification
@@ -3276,11 +3282,17 @@ static int ccs_remove(struct i2c_client *client)
return 0;
}
+static const struct ccs_device smia_device = {
+ .flags = CCS_DEVICE_FLAG_IS_SMIA,
+};
+
+static const struct ccs_device ccs_device = {};
+
static const struct of_device_id ccs_of_table[] = {
- { .compatible = "mipi-ccs-1.1" },
- { .compatible = "mipi-ccs-1.0" },
- { .compatible = "mipi-ccs" },
- { .compatible = "nokia,smia" },
+ { .compatible = "mipi-ccs-1.1", .data = &ccs_device },
+ { .compatible = "mipi-ccs-1.0", .data = &ccs_device },
+ { .compatible = "mipi-ccs", .data = &ccs_device },
+ { .compatible = "nokia,smia", .data = &smia_device },
{ },
};
MODULE_DEVICE_TABLE(of, ccs_of_table);
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 053/106] dt-bindings: mipi,ccs: Don't mention vana voltage
2020-10-07 8:44 [PATCH v2 000/106] CCS driver Sakari Ailus
` (7 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 026/106] dt-bindings: mipi-ccs: Add bus-type for C-PHY support Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 16:07 ` Rob Herring
2020-10-07 8:45 ` [PATCH v2 054/106] dt-bindings: mipi,ccs: Add vcore and vio supplies Sakari Ailus
9 siblings, 1 reply; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media; +Cc: devicetree
It was mentioned vana voltage is typically 2,8 volts. This is truly sensor
dependent, and nowadays 2,8 volts is a lot.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml b/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml
index b641debcd6a2..c52b603d946c 100644
--- a/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml
+++ b/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml
@@ -37,8 +37,7 @@ properties:
maxItems: 1
vana-supply:
- description: Analogue voltage supply (VANA), typically 2,8 volts (sensor
- dependent).
+ description: Analogue voltage supply (VANA), sensor dependent.
maxItems: 1
clocks:
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 051/106] ccs: Use longer pre-I²C sleep for CCS compliant devices
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (41 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 050/106] ccs: Add device compatible identifiers for telling SMIA and CCS apart Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 052/106] ccs: Remove unnecessary delays from power-up sequence Sakari Ailus
` (53 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Longer idle period is required on I²C bus before the first transaction
after lifting xshutdown.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 940b5327a388..94661275d599 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -1300,6 +1300,7 @@ static int ccs_power_on(struct device *dev)
*/
struct ccs_sensor *sensor =
container_of(ssd, struct ccs_sensor, ssds[0]);
+ const struct ccs_device *ccsdev = device_get_match_data(dev);
unsigned int sleep;
int rval;
@@ -1320,7 +1321,11 @@ static int ccs_power_on(struct device *dev)
gpiod_set_value(sensor->reset, 0);
gpiod_set_value(sensor->xshutdown, 1);
- sleep = SMIAPP_RESET_DELAY(sensor->hwcfg.ext_clk);
+ if (ccsdev->flags & CCS_DEVICE_FLAG_IS_SMIA)
+ sleep = SMIAPP_RESET_DELAY(sensor->hwcfg.ext_clk);
+ else
+ sleep = 5000;
+
usleep_range(sleep, sleep);
/*
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 054/106] dt-bindings: mipi,ccs: Add vcore and vio supplies
2020-10-07 8:44 [PATCH v2 000/106] CCS driver Sakari Ailus
` (8 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 053/106] dt-bindings: mipi,ccs: Don't mention vana voltage Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 16:08 ` Rob Herring
9 siblings, 1 reply; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media; +Cc: devicetree
Vcore and vio supplies are also part of the spec and used by many sensors.
Do not specify the voltages as they are generally sensor dependent.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml b/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml
index c52b603d946c..029b2dad9ffb 100644
--- a/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml
+++ b/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml
@@ -40,6 +40,14 @@ properties:
description: Analogue voltage supply (VANA), sensor dependent.
maxItems: 1
+ vcore-supply:
+ description: Core voltage supply (VCore), sensor dependent.
+ maxItems: 1
+
+ vio-supply:
+ description: I/O voltage supply (VIO), sensor dependent.
+ maxItems: 1
+
clocks:
description: External clock to the sensor.
maxItems: 1
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 052/106] ccs: Remove unnecessary delays from power-up sequence
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (42 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 051/106] ccs: Use longer pre-I²C sleep for CCS compliant devices Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 055/106] ccs: Use all regulators Sakari Ailus
` (52 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
SMIA nor CCS need these delays; remove them.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 94661275d599..8bf42fc222c1 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -1309,14 +1309,12 @@ static int ccs_power_on(struct device *dev)
dev_err(dev, "failed to enable vana regulator\n");
return rval;
}
- usleep_range(1000, 1000);
rval = clk_prepare_enable(sensor->ext_clk);
if (rval < 0) {
dev_dbg(dev, "failed to enable xclk\n");
goto out_xclk_fail;
}
- usleep_range(1000, 1000);
gpiod_set_value(sensor->reset, 0);
gpiod_set_value(sensor->xshutdown, 1);
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 055/106] ccs: Use all regulators
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (43 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 052/106] ccs: Remove unnecessary delays from power-up sequence Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 056/106] ccs-pll: Don't use div_u64 to divide a 32-bit number Sakari Ailus
` (51 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Use regulators vio and vcore besides vana. The regulators were always
there but on many boards they've been hard wired. Control them explicitly
now.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 30 +++++++++++++++++++++++-------
drivers/media/i2c/ccs/ccs.h | 2 +-
2 files changed, 24 insertions(+), 8 deletions(-)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 8bf42fc222c1..1a466378c1c1 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -65,6 +65,8 @@ struct ccs_device {
unsigned char flags;
};
+static const char * const ccs_regulators[] = { "vcore", "vio", "vana" };
+
/*
*
* Dynamic Capability Identification
@@ -1304,7 +1306,8 @@ static int ccs_power_on(struct device *dev)
unsigned int sleep;
int rval;
- rval = regulator_enable(sensor->vana);
+ rval = regulator_bulk_enable(ARRAY_SIZE(ccs_regulators),
+ sensor->regulators);
if (rval) {
dev_err(dev, "failed to enable vana regulator\n");
return rval;
@@ -1416,7 +1419,8 @@ static int ccs_power_on(struct device *dev)
clk_disable_unprepare(sensor->ext_clk);
out_xclk_fail:
- regulator_disable(sensor->vana);
+ regulator_bulk_disable(ARRAY_SIZE(ccs_regulators),
+ sensor->regulators);
return rval;
}
@@ -1442,7 +1446,8 @@ static int ccs_power_off(struct device *dev)
gpiod_set_value(sensor->xshutdown, 0);
clk_disable_unprepare(sensor->ext_clk);
usleep_range(5000, 5000);
- regulator_disable(sensor->vana);
+ regulator_bulk_disable(ARRAY_SIZE(ccs_regulators),
+ sensor->regulators);
sensor->streaming = false;
return 0;
@@ -2981,10 +2986,21 @@ static int ccs_probe(struct i2c_client *client)
v4l2_i2c_subdev_init(&sensor->src->sd, client, &ccs_ops);
sensor->src->sd.internal_ops = &ccs_internal_src_ops;
- sensor->vana = devm_regulator_get(&client->dev, "vana");
- if (IS_ERR(sensor->vana)) {
- dev_err(&client->dev, "could not get regulator for vana\n");
- return PTR_ERR(sensor->vana);
+ sensor->regulators = devm_kcalloc(&client->dev,
+ ARRAY_SIZE(ccs_regulators),
+ sizeof(*sensor->regulators),
+ GFP_KERNEL);
+ if (!sensor->regulators)
+ return -ENOMEM;
+
+ for (i = 0; i < ARRAY_SIZE(ccs_regulators); i++)
+ sensor->regulators[i].supply = ccs_regulators[i];
+
+ rval = devm_regulator_bulk_get(&client->dev, ARRAY_SIZE(ccs_regulators),
+ sensor->regulators);
+ if (rval) {
+ dev_err(&client->dev, "could not get regulators\n");
+ return rval;
}
sensor->ext_clk = devm_clk_get(&client->dev, NULL);
diff --git a/drivers/media/i2c/ccs/ccs.h b/drivers/media/i2c/ccs/ccs.h
index 6b07e4143ff0..356b87c33405 100644
--- a/drivers/media/i2c/ccs/ccs.h
+++ b/drivers/media/i2c/ccs/ccs.h
@@ -223,7 +223,7 @@ struct ccs_sensor {
struct ccs_subdev *scaler;
struct ccs_subdev *pixel_array;
struct ccs_hwconfig hwcfg;
- struct regulator *vana;
+ struct regulator_bulk_data *regulators;
struct clk *ext_clk;
struct gpio_desc *xshutdown;
struct gpio_desc *reset;
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 056/106] ccs-pll: Don't use div_u64 to divide a 32-bit number
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (44 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 055/106] ccs: Use all regulators Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 057/106] ccs-pll: Split limits and PLL configuration into front and back parts Sakari Ailus
` (50 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
pll->pll_op_clk_freq is a 32-bit number. It does not need div_u64 to
divide it.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index 0d57bac1599a..1cfe6cf7e51c 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -445,7 +445,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits,
min_pre_pll_clk_div, max_pre_pll_clk_div);
i = gcd(pll->pll_op_clk_freq_hz, pll->ext_clk_freq_hz);
- mul = div_u64(pll->pll_op_clk_freq_hz, i);
+ mul = pll->pll_op_clk_freq_hz / i;
div = pll->ext_clk_freq_hz / i;
dev_dbg(dev, "mul %u / div %u\n", mul, div);
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 057/106] ccs-pll: Split limits and PLL configuration into front and back parts
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (45 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 056/106] ccs-pll: Don't use div_u64 to divide a 32-bit number Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 058/106] ccs-pll: Use correct VT divisor for calculating VT SYS divisor Sakari Ailus
` (49 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
The CCS spec supports a lot of variation in the PLL. Split the PLL in
front and back parts to better prepare for supporting it.
Also use CCS compliant naming for IP and OP PLL frequencies (i.e. include
"clk" in the name).
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 282 ++++++++++++++++---------------
drivers/media/i2c/ccs-pll.h | 44 +++--
drivers/media/i2c/ccs/ccs-core.c | 71 ++++----
3 files changed, 209 insertions(+), 188 deletions(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index 1cfe6cf7e51c..b2f0fa14ff92 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -53,65 +53,68 @@ static int bounds_check(struct device *dev, uint32_t val,
static void print_pll(struct device *dev, struct ccs_pll *pll)
{
- dev_dbg(dev, "pre_pll_clk_div\t%u\n", pll->pre_pll_clk_div);
- dev_dbg(dev, "pll_multiplier \t%u\n", pll->pll_multiplier);
+ dev_dbg(dev, "pre_pll_clk_div\t%u\n", pll->vt_fr.pre_pll_clk_div);
+ dev_dbg(dev, "pll_multiplier \t%u\n", pll->vt_fr.pll_multiplier);
if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)) {
- dev_dbg(dev, "op_sys_clk_div \t%u\n", pll->op.sys_clk_div);
- dev_dbg(dev, "op_pix_clk_div \t%u\n", pll->op.pix_clk_div);
+ dev_dbg(dev, "op_sys_clk_div \t%u\n", pll->op_bk.sys_clk_div);
+ dev_dbg(dev, "op_pix_clk_div \t%u\n", pll->op_bk.pix_clk_div);
}
- dev_dbg(dev, "vt_sys_clk_div \t%u\n", pll->vt.sys_clk_div);
- dev_dbg(dev, "vt_pix_clk_div \t%u\n", pll->vt.pix_clk_div);
+ dev_dbg(dev, "vt_sys_clk_div \t%u\n", pll->vt_bk.sys_clk_div);
+ dev_dbg(dev, "vt_pix_clk_div \t%u\n", pll->vt_bk.pix_clk_div);
dev_dbg(dev, "ext_clk_freq_hz \t%u\n", pll->ext_clk_freq_hz);
- dev_dbg(dev, "pll_ip_clk_freq_hz \t%u\n", pll->pll_ip_clk_freq_hz);
- dev_dbg(dev, "pll_op_clk_freq_hz \t%u\n", pll->pll_op_clk_freq_hz);
+ dev_dbg(dev, "pll_ip_clk_freq_hz \t%u\n", pll->vt_fr.pll_ip_clk_freq_hz);
+ dev_dbg(dev, "pll_op_clk_freq_hz \t%u\n", pll->vt_fr.pll_op_clk_freq_hz);
if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)) {
dev_dbg(dev, "op_sys_clk_freq_hz \t%u\n",
- pll->op.sys_clk_freq_hz);
+ pll->op_bk.sys_clk_freq_hz);
dev_dbg(dev, "op_pix_clk_freq_hz \t%u\n",
- pll->op.pix_clk_freq_hz);
+ pll->op_bk.pix_clk_freq_hz);
}
- dev_dbg(dev, "vt_sys_clk_freq_hz \t%u\n", pll->vt.sys_clk_freq_hz);
- dev_dbg(dev, "vt_pix_clk_freq_hz \t%u\n", pll->vt.pix_clk_freq_hz);
+ dev_dbg(dev, "vt_sys_clk_freq_hz \t%u\n", pll->vt_bk.sys_clk_freq_hz);
+ dev_dbg(dev, "vt_pix_clk_freq_hz \t%u\n", pll->vt_bk.pix_clk_freq_hz);
}
static int check_all_bounds(struct device *dev,
- const struct ccs_pll_limits *limits,
- const struct ccs_pll_branch_limits *op_limits,
- struct ccs_pll *pll, struct ccs_pll_branch *op_pll)
+ const struct ccs_pll_limits *lim,
+ const struct ccs_pll_branch_limits_fr *op_lim_fr,
+ const struct ccs_pll_branch_limits_bk *op_lim_bk,
+ struct ccs_pll *pll,
+ struct ccs_pll_branch_fr *op_pll_fr,
+ struct ccs_pll_branch_bk *op_pll_bk)
{
int rval;
- rval = bounds_check(dev, pll->pll_ip_clk_freq_hz,
- limits->min_pll_ip_freq_hz,
- limits->max_pll_ip_freq_hz,
+ rval = bounds_check(dev, op_pll_fr->pll_ip_clk_freq_hz,
+ op_lim_fr->min_pll_ip_clk_freq_hz,
+ op_lim_fr->max_pll_ip_clk_freq_hz,
"pll_ip_clk_freq_hz");
if (!rval)
rval = bounds_check(
- dev, pll->pll_multiplier,
- limits->min_pll_multiplier, limits->max_pll_multiplier,
- "pll_multiplier");
+ dev, op_pll_fr->pll_multiplier,
+ op_lim_fr->min_pll_multiplier,
+ op_lim_fr->max_pll_multiplier, "pll_multiplier");
if (!rval)
rval = bounds_check(
- dev, pll->pll_op_clk_freq_hz,
- limits->min_pll_op_freq_hz, limits->max_pll_op_freq_hz,
- "pll_op_clk_freq_hz");
+ dev, op_pll_fr->pll_op_clk_freq_hz,
+ op_lim_fr->min_pll_op_clk_freq_hz,
+ op_lim_fr->max_pll_op_clk_freq_hz, "pll_op_clk_freq_hz");
if (!rval)
rval = bounds_check(
- dev, op_pll->sys_clk_div,
- op_limits->min_sys_clk_div, op_limits->max_sys_clk_div,
+ dev, op_pll_bk->sys_clk_div,
+ op_lim_bk->min_sys_clk_div, op_lim_bk->max_sys_clk_div,
"op_sys_clk_div");
if (!rval)
rval = bounds_check(
- dev, op_pll->sys_clk_freq_hz,
- op_limits->min_sys_clk_freq_hz,
- op_limits->max_sys_clk_freq_hz,
+ dev, op_pll_bk->sys_clk_freq_hz,
+ op_lim_bk->min_sys_clk_freq_hz,
+ op_lim_bk->max_sys_clk_freq_hz,
"op_sys_clk_freq_hz");
if (!rval)
rval = bounds_check(
- dev, op_pll->pix_clk_freq_hz,
- op_limits->min_pix_clk_freq_hz,
- op_limits->max_pix_clk_freq_hz,
+ dev, op_pll_bk->pix_clk_freq_hz,
+ op_lim_bk->min_pix_clk_freq_hz,
+ op_lim_bk->max_pix_clk_freq_hz,
"op_pix_clk_freq_hz");
/*
@@ -123,15 +126,15 @@ static int check_all_bounds(struct device *dev,
if (!rval)
rval = bounds_check(
- dev, pll->vt.sys_clk_freq_hz,
- limits->vt.min_sys_clk_freq_hz,
- limits->vt.max_sys_clk_freq_hz,
+ dev, pll->vt_bk.sys_clk_freq_hz,
+ lim->vt_bk.min_sys_clk_freq_hz,
+ lim->vt_bk.max_sys_clk_freq_hz,
"vt_sys_clk_freq_hz");
if (!rval)
rval = bounds_check(
- dev, pll->vt.pix_clk_freq_hz,
- limits->vt.min_pix_clk_freq_hz,
- limits->vt.max_pix_clk_freq_hz,
+ dev, pll->vt_bk.pix_clk_freq_hz,
+ lim->vt_bk.min_pix_clk_freq_hz,
+ lim->vt_bk.max_pix_clk_freq_hz,
"vt_pix_clk_freq_hz");
return rval;
@@ -149,10 +152,12 @@ static int check_all_bounds(struct device *dev,
* @return Zero on success, error code on error.
*/
static int
-__ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits,
- const struct ccs_pll_branch_limits *op_limits,
- struct ccs_pll *pll, struct ccs_pll_branch *op_pll,
- uint32_t mul, uint32_t div, uint32_t lane_op_clock_ratio)
+__ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
+ const struct ccs_pll_branch_limits_fr *op_lim_fr,
+ const struct ccs_pll_branch_limits_bk *op_lim_bk,
+ struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr,
+ struct ccs_pll_branch_bk *op_pll_bk, uint32_t mul,
+ uint32_t div, uint32_t lane_op_clock_ratio)
{
uint32_t sys_div;
uint32_t best_pix_div = INT_MAX >> 1;
@@ -173,42 +178,42 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits,
* Get pre_pll_clk_div so that our pll_op_clk_freq_hz won't be
* too high.
*/
- dev_dbg(dev, "pre_pll_clk_div %u\n", pll->pre_pll_clk_div);
+ dev_dbg(dev, "op_pre_pll_clk_div %u\n", op_pll_fr->pre_pll_clk_div);
/* Don't go above max pll multiplier. */
- more_mul_max = limits->max_pll_multiplier / mul;
- dev_dbg(dev, "more_mul_max: max_pll_multiplier check: %u\n",
+ more_mul_max = op_lim_fr->max_pll_multiplier / mul;
+ dev_dbg(dev, "more_mul_max: max_op_pll_multiplier check: %u\n",
more_mul_max);
/* Don't go above max pll op frequency. */
more_mul_max =
min_t(uint32_t,
more_mul_max,
- limits->max_pll_op_freq_hz
- / (pll->ext_clk_freq_hz / pll->pre_pll_clk_div * mul));
- dev_dbg(dev, "more_mul_max: max_pll_op_freq_hz check: %u\n",
+ op_lim_fr->max_pll_op_clk_freq_hz
+ / (pll->ext_clk_freq_hz / op_pll_fr->pre_pll_clk_div * mul));
+ dev_dbg(dev, "more_mul_max: max_pll_op_clk_freq_hz check: %u\n",
more_mul_max);
/* Don't go above the division capability of op sys clock divider. */
more_mul_max = min(more_mul_max,
- op_limits->max_sys_clk_div * pll->pre_pll_clk_div
+ op_lim_bk->max_sys_clk_div * op_pll_fr->pre_pll_clk_div
/ div);
dev_dbg(dev, "more_mul_max: max_op_sys_clk_div check: %u\n",
more_mul_max);
/* Ensure we won't go above min_pll_multiplier. */
more_mul_max = min(more_mul_max,
- DIV_ROUND_UP(limits->max_pll_multiplier, mul));
+ DIV_ROUND_UP(op_lim_fr->max_pll_multiplier, mul));
dev_dbg(dev, "more_mul_max: min_pll_multiplier check: %u\n",
more_mul_max);
- /* Ensure we won't go below min_pll_op_freq_hz. */
- more_mul_min = DIV_ROUND_UP(limits->min_pll_op_freq_hz,
- pll->ext_clk_freq_hz / pll->pre_pll_clk_div
- * mul);
- dev_dbg(dev, "more_mul_min: min_pll_op_freq_hz check: %u\n",
+ /* Ensure we won't go below min_pll_op_clk_freq_hz. */
+ more_mul_min = DIV_ROUND_UP(op_lim_fr->min_pll_op_clk_freq_hz,
+ pll->ext_clk_freq_hz /
+ op_pll_fr->pre_pll_clk_div * mul);
+ dev_dbg(dev, "more_mul_min: min_op_pll_op_clk_freq_hz check: %u\n",
more_mul_min);
/* Ensure we won't go below min_pll_multiplier. */
more_mul_min = max(more_mul_min,
- DIV_ROUND_UP(limits->min_pll_multiplier, mul));
- dev_dbg(dev, "more_mul_min: min_pll_multiplier check: %u\n",
+ DIV_ROUND_UP(op_lim_fr->min_pll_multiplier, mul));
+ dev_dbg(dev, "more_mul_min: min_op_pll_multiplier check: %u\n",
more_mul_min);
if (more_mul_min > more_mul_max) {
@@ -217,9 +222,9 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits,
return -EINVAL;
}
- more_mul_factor = lcm(div, pll->pre_pll_clk_div) / div;
+ more_mul_factor = lcm(div, op_pll_fr->pre_pll_clk_div) / div;
dev_dbg(dev, "more_mul_factor: %u\n", more_mul_factor);
- more_mul_factor = lcm(more_mul_factor, op_limits->min_sys_clk_div);
+ more_mul_factor = lcm(more_mul_factor, op_lim_bk->min_sys_clk_div);
dev_dbg(dev, "more_mul_factor: min_op_sys_clk_div: %d\n",
more_mul_factor);
i = roundup(more_mul_min, more_mul_factor);
@@ -232,25 +237,25 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits,
return -EINVAL;
}
- pll->pll_multiplier = mul * i;
- op_pll->sys_clk_div = div * i / pll->pre_pll_clk_div;
- dev_dbg(dev, "op_sys_clk_div: %u\n", op_pll->sys_clk_div);
+ op_pll_fr->pll_multiplier = mul * i;
+ op_pll_bk->sys_clk_div = div * i / op_pll_fr->pre_pll_clk_div;
+ dev_dbg(dev, "op_sys_clk_div: %u\n", op_pll_bk->sys_clk_div);
- pll->pll_ip_clk_freq_hz = pll->ext_clk_freq_hz
- / pll->pre_pll_clk_div;
+ op_pll_fr->pll_ip_clk_freq_hz = pll->ext_clk_freq_hz
+ / op_pll_fr->pre_pll_clk_div;
- pll->pll_op_clk_freq_hz = pll->pll_ip_clk_freq_hz
- * pll->pll_multiplier;
+ op_pll_fr->pll_op_clk_freq_hz = op_pll_fr->pll_ip_clk_freq_hz
+ * op_pll_fr->pll_multiplier;
/* Derive pll_op_clk_freq_hz. */
- op_pll->sys_clk_freq_hz =
- pll->pll_op_clk_freq_hz / op_pll->sys_clk_div;
+ op_pll_bk->sys_clk_freq_hz =
+ op_pll_fr->pll_op_clk_freq_hz / op_pll_bk->sys_clk_div;
- op_pll->pix_clk_div = pll->bits_per_pixel;
- dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll->pix_clk_div);
+ op_pll_bk->pix_clk_div = pll->bits_per_pixel;
+ dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div);
- op_pll->pix_clk_freq_hz =
- op_pll->sys_clk_freq_hz / op_pll->pix_clk_div;
+ op_pll_bk->pix_clk_freq_hz =
+ op_pll_bk->sys_clk_freq_hz / op_pll_bk->pix_clk_div;
if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) {
/* No OP clocks --- VT clocks are used instead. */
@@ -264,7 +269,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits,
* should run at higher clock rate, so smaller divisor is used
* on video timing side.
*/
- if (limits->min_line_length_pck_bin > limits->min_line_length_pck
+ if (lim->min_line_length_pck_bin > lim->min_line_length_pck
/ pll->binning_horizontal)
vt_op_binning_div = pll->binning_horizontal;
else
@@ -283,28 +288,28 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits,
* Find absolute limits for the factor of vt divider.
*/
dev_dbg(dev, "scale_m: %u\n", pll->scale_m);
- min_vt_div = DIV_ROUND_UP(op_pll->pix_clk_div * op_pll->sys_clk_div
- * pll->scale_n,
+ min_vt_div = DIV_ROUND_UP(op_pll_bk->pix_clk_div
+ * op_pll_bk->sys_clk_div * pll->scale_n,
lane_op_clock_ratio * vt_op_binning_div
* pll->scale_m);
/* Find smallest and biggest allowed vt divisor. */
dev_dbg(dev, "min_vt_div: %u\n", min_vt_div);
min_vt_div = max(min_vt_div,
- DIV_ROUND_UP(pll->pll_op_clk_freq_hz,
- limits->vt.max_pix_clk_freq_hz));
+ DIV_ROUND_UP(op_pll_fr->pll_op_clk_freq_hz,
+ lim->vt_bk.max_pix_clk_freq_hz));
dev_dbg(dev, "min_vt_div: max_vt_pix_clk_freq_hz: %u\n",
min_vt_div);
min_vt_div = max_t(uint32_t, min_vt_div,
- limits->vt.min_pix_clk_div
- * limits->vt.min_sys_clk_div);
+ lim->vt_bk.min_pix_clk_div
+ * lim->vt_bk.min_sys_clk_div);
dev_dbg(dev, "min_vt_div: min_vt_clk_div: %u\n", min_vt_div);
- max_vt_div = limits->vt.max_sys_clk_div * limits->vt.max_pix_clk_div;
+ max_vt_div = lim->vt_bk.max_sys_clk_div * lim->vt_bk.max_pix_clk_div;
dev_dbg(dev, "max_vt_div: %u\n", max_vt_div);
max_vt_div = min(max_vt_div,
- DIV_ROUND_UP(pll->pll_op_clk_freq_hz,
- limits->vt.min_pix_clk_freq_hz));
+ DIV_ROUND_UP(op_pll_fr->pll_op_clk_freq_hz,
+ lim->vt_bk.min_pix_clk_freq_hz));
dev_dbg(dev, "max_vt_div: min_vt_pix_clk_freq_hz: %u\n",
max_vt_div);
@@ -312,28 +317,28 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits,
* Find limitsits for sys_clk_div. Not all values are possible
* with all values of pix_clk_div.
*/
- min_sys_div = limits->vt.min_sys_clk_div;
+ min_sys_div = lim->vt_bk.min_sys_clk_div;
dev_dbg(dev, "min_sys_div: %u\n", min_sys_div);
min_sys_div = max(min_sys_div,
DIV_ROUND_UP(min_vt_div,
- limits->vt.max_pix_clk_div));
+ lim->vt_bk.max_pix_clk_div));
dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", min_sys_div);
min_sys_div = max(min_sys_div,
- pll->pll_op_clk_freq_hz
- / limits->vt.max_sys_clk_freq_hz);
+ op_pll_fr->pll_op_clk_freq_hz
+ / lim->vt_bk.max_sys_clk_freq_hz);
dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", min_sys_div);
min_sys_div = clk_div_even_up(min_sys_div);
dev_dbg(dev, "min_sys_div: one or even: %u\n", min_sys_div);
- max_sys_div = limits->vt.max_sys_clk_div;
+ max_sys_div = lim->vt_bk.max_sys_clk_div;
dev_dbg(dev, "max_sys_div: %u\n", max_sys_div);
max_sys_div = min(max_sys_div,
DIV_ROUND_UP(max_vt_div,
- limits->vt.min_pix_clk_div));
+ lim->vt_bk.min_pix_clk_div));
dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", max_sys_div);
max_sys_div = min(max_sys_div,
- DIV_ROUND_UP(pll->pll_op_clk_freq_hz,
- limits->vt.min_pix_clk_freq_hz));
+ DIV_ROUND_UP(op_pll_fr->pll_op_clk_freq_hz,
+ lim->vt_bk.min_pix_clk_freq_hz));
dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", max_sys_div);
/*
@@ -348,13 +353,13 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits,
sys_div += 2 - (sys_div & 1)) {
uint16_t pix_div = DIV_ROUND_UP(vt_div, sys_div);
- if (pix_div < limits->vt.min_pix_clk_div
- || pix_div > limits->vt.max_pix_clk_div) {
+ if (pix_div < lim->vt_bk.min_pix_clk_div
+ || pix_div > lim->vt_bk.max_pix_clk_div) {
dev_dbg(dev,
"pix_div %u too small or too big (%u--%u)\n",
pix_div,
- limits->vt.min_pix_clk_div,
- limits->vt.max_pix_clk_div);
+ lim->vt_bk.min_pix_clk_div,
+ lim->vt_bk.max_pix_clk_div);
continue;
}
@@ -367,29 +372,32 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits,
break;
}
- pll->vt.sys_clk_div = DIV_ROUND_UP(min_vt_div, best_pix_div);
- pll->vt.pix_clk_div = best_pix_div;
+ pll->vt_bk.sys_clk_div = DIV_ROUND_UP(min_vt_div, best_pix_div);
+ pll->vt_bk.pix_clk_div = best_pix_div;
- pll->vt.sys_clk_freq_hz =
- pll->pll_op_clk_freq_hz / pll->vt.sys_clk_div;
- pll->vt.pix_clk_freq_hz =
- pll->vt.sys_clk_freq_hz / pll->vt.pix_clk_div;
+ pll->vt_bk.sys_clk_freq_hz =
+ op_pll_fr->pll_op_clk_freq_hz / pll->vt_bk.sys_clk_div;
+ pll->vt_bk.pix_clk_freq_hz =
+ pll->vt_bk.sys_clk_freq_hz / pll->vt_bk.pix_clk_div;
out_skip_vt_calc:
pll->pixel_rate_csi =
- op_pll->pix_clk_freq_hz * lane_op_clock_ratio;
- pll->pixel_rate_pixel_array = pll->vt.pix_clk_freq_hz;
+ op_pll_bk->pix_clk_freq_hz * lane_op_clock_ratio;
+ pll->pixel_rate_pixel_array = pll->vt_bk.pix_clk_freq_hz;
- return check_all_bounds(dev, limits, op_limits, pll, op_pll);
+ return check_all_bounds(dev, lim, op_lim_fr, op_lim_bk, pll, op_pll_fr,
+ op_pll_bk);
}
-int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits,
+int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
struct ccs_pll *pll)
{
- const struct ccs_pll_branch_limits *op_limits = &limits->op;
- struct ccs_pll_branch *op_pll = &pll->op;
- uint16_t min_pre_pll_clk_div;
- uint16_t max_pre_pll_clk_div;
+ const struct ccs_pll_branch_limits_fr *op_lim_fr = &lim->vt_fr;
+ const struct ccs_pll_branch_limits_bk *op_lim_bk = &lim->op_bk;
+ struct ccs_pll_branch_fr *op_pll_fr = &pll->vt_fr;
+ struct ccs_pll_branch_bk *op_pll_bk = &pll->op_bk;
+ uint16_t min_op_pre_pll_clk_div;
+ uint16_t max_op_pre_pll_clk_div;
uint32_t lane_op_clock_ratio;
uint32_t mul, div;
unsigned int i;
@@ -401,8 +409,9 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits,
* instead. The OP values are ignored for the rest of
* the PLL calculation.
*/
- op_limits = &limits->vt;
- op_pll = &pll->vt;
+ op_lim_fr = &lim->vt_fr;
+ op_lim_bk = &lim->vt_bk;
+ op_pll_bk = &pll->vt_bk;
}
if (pll->flags & CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE)
@@ -417,11 +426,11 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits,
switch (pll->bus_type) {
case CCS_PLL_BUS_TYPE_CSI2:
/* CSI transfers 2 bits per clock per lane; thus times 2 */
- pll->pll_op_clk_freq_hz = pll->link_freq * 2
+ op_pll_fr->pll_op_clk_freq_hz = pll->link_freq * 2
* (pll->csi2.lanes / lane_op_clock_ratio);
break;
case CCS_PLL_BUS_TYPE_PARALLEL:
- pll->pll_op_clk_freq_hz = pll->link_freq * pll->bits_per_pixel
+ op_pll_fr->pll_op_clk_freq_hz = pll->link_freq * pll->bits_per_pixel
/ DIV_ROUND_UP(pll->bits_per_pixel,
pll->parallel.bus_width);
break;
@@ -429,39 +438,40 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits,
return -EINVAL;
}
- /* Figure out limits for pre-pll divider based on extclk */
- dev_dbg(dev, "min / max pre_pll_clk_div: %u / %u\n",
- limits->min_pre_pll_clk_div, limits->max_pre_pll_clk_div);
- max_pre_pll_clk_div =
- min_t(uint16_t, limits->max_pre_pll_clk_div,
+ /* Figure out limits for OP pre-pll divider based on extclk */
+ dev_dbg(dev, "min / max op_pre_pll_clk_div: %u / %u\n",
+ op_lim_fr->min_pre_pll_clk_div, op_lim_fr->max_pre_pll_clk_div);
+ max_op_pre_pll_clk_div =
+ min_t(uint16_t, op_lim_fr->max_pre_pll_clk_div,
clk_div_even(pll->ext_clk_freq_hz /
- limits->min_pll_ip_freq_hz));
- min_pre_pll_clk_div =
- max_t(uint16_t, limits->min_pre_pll_clk_div,
+ op_lim_fr->min_pll_ip_clk_freq_hz));
+ min_op_pre_pll_clk_div =
+ max_t(uint16_t, op_lim_fr->min_pre_pll_clk_div,
clk_div_even_up(
DIV_ROUND_UP(pll->ext_clk_freq_hz,
- limits->max_pll_ip_freq_hz)));
- dev_dbg(dev, "pre-pll check: min / max pre_pll_clk_div: %u / %u\n",
- min_pre_pll_clk_div, max_pre_pll_clk_div);
+ op_lim_fr->max_pll_ip_clk_freq_hz)));
+ dev_dbg(dev, "pre-pll check: min / max op_pre_pll_clk_div: %u / %u\n",
+ min_op_pre_pll_clk_div, max_op_pre_pll_clk_div);
- i = gcd(pll->pll_op_clk_freq_hz, pll->ext_clk_freq_hz);
- mul = pll->pll_op_clk_freq_hz / i;
+ i = gcd(op_pll_fr->pll_op_clk_freq_hz, pll->ext_clk_freq_hz);
+ mul = op_pll_fr->pll_op_clk_freq_hz / i;
div = pll->ext_clk_freq_hz / i;
dev_dbg(dev, "mul %u / div %u\n", mul, div);
- min_pre_pll_clk_div =
- max_t(uint16_t, min_pre_pll_clk_div,
+ min_op_pre_pll_clk_div =
+ max_t(uint16_t, min_op_pre_pll_clk_div,
clk_div_even_up(
DIV_ROUND_UP(mul * pll->ext_clk_freq_hz,
- limits->max_pll_op_freq_hz)));
- dev_dbg(dev, "pll_op check: min / max pre_pll_clk_div: %u / %u\n",
- min_pre_pll_clk_div, max_pre_pll_clk_div);
-
- for (pll->pre_pll_clk_div = min_pre_pll_clk_div;
- pll->pre_pll_clk_div <= max_pre_pll_clk_div;
- pll->pre_pll_clk_div += 2 - (pll->pre_pll_clk_div & 1)) {
- rval = __ccs_pll_calculate(dev, limits, op_limits, pll, op_pll,
- mul, div, lane_op_clock_ratio);
+ op_lim_fr->max_pll_op_clk_freq_hz)));
+ dev_dbg(dev, "pll_op check: min / max op_pre_pll_clk_div: %u / %u\n",
+ min_op_pre_pll_clk_div, max_op_pre_pll_clk_div);
+
+ for (op_pll_fr->pre_pll_clk_div = min_op_pre_pll_clk_div;
+ op_pll_fr->pre_pll_clk_div <= max_op_pre_pll_clk_div;
+ op_pll_fr->pre_pll_clk_div += 2 - (op_pll_fr->pre_pll_clk_div & 1)) {
+ rval = __ccs_pll_calculate(dev, lim, op_lim_fr, op_lim_bk, pll,
+ op_pll_fr, op_pll_bk, mul, div,
+ lane_op_clock_ratio);
if (rval)
continue;
diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h
index 07f7f9e8a1cc..03b1d8d11423 100644
--- a/drivers/media/i2c/ccs-pll.h
+++ b/drivers/media/i2c/ccs-pll.h
@@ -20,7 +20,14 @@
#define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0)
#define CCS_PLL_FLAG_NO_OP_CLOCKS (1 << 1)
-struct ccs_pll_branch {
+struct ccs_pll_branch_fr {
+ uint16_t pre_pll_clk_div;
+ uint16_t pll_multiplier;
+ uint32_t pll_ip_clk_freq_hz;
+ uint32_t pll_op_clk_freq_hz;
+};
+
+struct ccs_pll_branch_bk {
uint16_t sys_clk_div;
uint16_t pix_clk_div;
uint32_t sys_clk_freq_hz;
@@ -48,18 +55,26 @@ struct ccs_pll {
uint32_t ext_clk_freq_hz;
/* output values */
- uint16_t pre_pll_clk_div;
- uint16_t pll_multiplier;
- uint32_t pll_ip_clk_freq_hz;
- uint32_t pll_op_clk_freq_hz;
- struct ccs_pll_branch vt;
- struct ccs_pll_branch op;
+ struct ccs_pll_branch_fr vt_fr;
+ struct ccs_pll_branch_bk vt_bk;
+ struct ccs_pll_branch_bk op_bk;
uint32_t pixel_rate_csi;
uint32_t pixel_rate_pixel_array;
};
-struct ccs_pll_branch_limits {
+struct ccs_pll_branch_limits_fr {
+ uint16_t min_pre_pll_clk_div;
+ uint16_t max_pre_pll_clk_div;
+ uint32_t min_pll_ip_clk_freq_hz;
+ uint32_t max_pll_ip_clk_freq_hz;
+ uint16_t min_pll_multiplier;
+ uint16_t max_pll_multiplier;
+ uint32_t min_pll_op_clk_freq_hz;
+ uint32_t max_pll_op_clk_freq_hz;
+};
+
+struct ccs_pll_branch_limits_bk {
uint16_t min_sys_clk_div;
uint16_t max_sys_clk_div;
uint32_t min_sys_clk_freq_hz;
@@ -74,17 +89,10 @@ struct ccs_pll_limits {
/* Strict PLL limits */
uint32_t min_ext_clk_freq_hz;
uint32_t max_ext_clk_freq_hz;
- uint16_t min_pre_pll_clk_div;
- uint16_t max_pre_pll_clk_div;
- uint32_t min_pll_ip_freq_hz;
- uint32_t max_pll_ip_freq_hz;
- uint16_t min_pll_multiplier;
- uint16_t max_pll_multiplier;
- uint32_t min_pll_op_freq_hz;
- uint32_t max_pll_op_freq_hz;
- struct ccs_pll_branch_limits vt;
- struct ccs_pll_branch_limits op;
+ struct ccs_pll_branch_limits_fr vt_fr;
+ struct ccs_pll_branch_limits_bk vt_bk;
+ struct ccs_pll_branch_limits_bk op_bk;
/* Other relevant limits */
uint32_t min_line_length_pck_bin;
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 1a466378c1c1..bc86cf0991df 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -368,67 +368,70 @@ static int ccs_pll_configure(struct ccs_sensor *sensor)
struct ccs_pll *pll = &sensor->pll;
int rval;
- rval = ccs_write(sensor, VT_PIX_CLK_DIV, pll->vt.pix_clk_div);
+ rval = ccs_write(sensor, VT_PIX_CLK_DIV, pll->vt_bk.pix_clk_div);
if (rval < 0)
return rval;
- rval = ccs_write(sensor, VT_SYS_CLK_DIV, pll->vt.sys_clk_div);
+ rval = ccs_write(sensor, VT_SYS_CLK_DIV, pll->vt_bk.sys_clk_div);
if (rval < 0)
return rval;
- rval = ccs_write(sensor, PRE_PLL_CLK_DIV, pll->pre_pll_clk_div);
+ rval = ccs_write(sensor, PRE_PLL_CLK_DIV, pll->vt_fr.pre_pll_clk_div);
if (rval < 0)
return rval;
- rval = ccs_write(sensor, PLL_MULTIPLIER, pll->pll_multiplier);
+ rval = ccs_write(sensor, PLL_MULTIPLIER, pll->vt_fr.pll_multiplier);
if (rval < 0)
return rval;
/* Lane op clock ratio does not apply here. */
rval = ccs_write(sensor, REQUESTED_LINK_RATE,
- DIV_ROUND_UP(pll->op.sys_clk_freq_hz,
+ DIV_ROUND_UP(pll->op_bk.sys_clk_freq_hz,
1000000 / 256 / 256));
if (rval < 0 || sensor->pll.flags & CCS_PLL_FLAG_NO_OP_CLOCKS)
return rval;
- rval = ccs_write(sensor, OP_PIX_CLK_DIV, pll->op.pix_clk_div);
+ rval = ccs_write(sensor, OP_PIX_CLK_DIV, pll->op_bk.pix_clk_div);
if (rval < 0)
return rval;
- return ccs_write(sensor, OP_SYS_CLK_DIV, pll->op.sys_clk_div);
+ return ccs_write(sensor, OP_SYS_CLK_DIV, pll->op_bk.sys_clk_div);
}
static int ccs_pll_try(struct ccs_sensor *sensor, struct ccs_pll *pll)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
struct ccs_pll_limits lim = {
- .min_pre_pll_clk_div = CCS_LIM(sensor, MIN_PRE_PLL_CLK_DIV),
- .max_pre_pll_clk_div = CCS_LIM(sensor, MAX_PRE_PLL_CLK_DIV),
- .min_pll_ip_freq_hz = CCS_LIM(sensor, MIN_PLL_IP_CLK_FREQ_MHZ),
- .max_pll_ip_freq_hz = CCS_LIM(sensor, MAX_PLL_IP_CLK_FREQ_MHZ),
- .min_pll_multiplier = CCS_LIM(sensor, MIN_PLL_MULTIPLIER),
- .max_pll_multiplier = CCS_LIM(sensor, MAX_PLL_MULTIPLIER),
- .min_pll_op_freq_hz = CCS_LIM(sensor, MIN_PLL_OP_CLK_FREQ_MHZ),
- .max_pll_op_freq_hz = CCS_LIM(sensor, MAX_PLL_OP_CLK_FREQ_MHZ),
-
- .op.min_sys_clk_div = CCS_LIM(sensor, MIN_OP_SYS_CLK_DIV),
- .op.max_sys_clk_div = CCS_LIM(sensor, MAX_OP_SYS_CLK_DIV),
- .op.min_pix_clk_div = CCS_LIM(sensor, MIN_OP_PIX_CLK_DIV),
- .op.max_pix_clk_div = CCS_LIM(sensor, MAX_OP_PIX_CLK_DIV),
- .op.min_sys_clk_freq_hz = CCS_LIM(sensor, MIN_OP_SYS_CLK_FREQ_MHZ),
- .op.max_sys_clk_freq_hz = CCS_LIM(sensor, MAX_OP_SYS_CLK_FREQ_MHZ),
- .op.min_pix_clk_freq_hz = CCS_LIM(sensor, MIN_OP_PIX_CLK_FREQ_MHZ),
- .op.max_pix_clk_freq_hz = CCS_LIM(sensor, MAX_OP_PIX_CLK_FREQ_MHZ),
-
- .vt.min_sys_clk_div = CCS_LIM(sensor, MIN_VT_SYS_CLK_DIV),
- .vt.max_sys_clk_div = CCS_LIM(sensor, MAX_VT_SYS_CLK_DIV),
- .vt.min_pix_clk_div = CCS_LIM(sensor, MIN_VT_PIX_CLK_DIV),
- .vt.max_pix_clk_div = CCS_LIM(sensor, MAX_VT_PIX_CLK_DIV),
- .vt.min_sys_clk_freq_hz = CCS_LIM(sensor, MIN_VT_SYS_CLK_FREQ_MHZ),
- .vt.max_sys_clk_freq_hz = CCS_LIM(sensor, MAX_VT_SYS_CLK_FREQ_MHZ),
- .vt.min_pix_clk_freq_hz = CCS_LIM(sensor, MIN_VT_PIX_CLK_FREQ_MHZ),
- .vt.max_pix_clk_freq_hz = CCS_LIM(sensor, MAX_VT_PIX_CLK_FREQ_MHZ),
-
+ .vt_fr = {
+ .min_pre_pll_clk_div = CCS_LIM(sensor, MIN_PRE_PLL_CLK_DIV),
+ .max_pre_pll_clk_div = CCS_LIM(sensor, MAX_PRE_PLL_CLK_DIV),
+ .min_pll_ip_clk_freq_hz = CCS_LIM(sensor, MIN_PLL_IP_CLK_FREQ_MHZ),
+ .max_pll_ip_clk_freq_hz = CCS_LIM(sensor, MAX_PLL_IP_CLK_FREQ_MHZ),
+ .min_pll_multiplier = CCS_LIM(sensor, MIN_PLL_MULTIPLIER),
+ .max_pll_multiplier = CCS_LIM(sensor, MAX_PLL_MULTIPLIER),
+ .min_pll_op_clk_freq_hz = CCS_LIM(sensor, MIN_PLL_OP_CLK_FREQ_MHZ),
+ .max_pll_op_clk_freq_hz = CCS_LIM(sensor, MAX_PLL_OP_CLK_FREQ_MHZ),
+ },
+ .op_bk = {
+ .min_sys_clk_div = CCS_LIM(sensor, MIN_OP_SYS_CLK_DIV),
+ .max_sys_clk_div = CCS_LIM(sensor, MAX_OP_SYS_CLK_DIV),
+ .min_pix_clk_div = CCS_LIM(sensor, MIN_OP_PIX_CLK_DIV),
+ .max_pix_clk_div = CCS_LIM(sensor, MAX_OP_PIX_CLK_DIV),
+ .min_sys_clk_freq_hz = CCS_LIM(sensor, MIN_OP_SYS_CLK_FREQ_MHZ),
+ .max_sys_clk_freq_hz = CCS_LIM(sensor, MAX_OP_SYS_CLK_FREQ_MHZ),
+ .min_pix_clk_freq_hz = CCS_LIM(sensor, MIN_OP_PIX_CLK_FREQ_MHZ),
+ .max_pix_clk_freq_hz = CCS_LIM(sensor, MAX_OP_PIX_CLK_FREQ_MHZ),
+ },
+ .vt_bk = {
+ .min_sys_clk_div = CCS_LIM(sensor, MIN_VT_SYS_CLK_DIV),
+ .max_sys_clk_div = CCS_LIM(sensor, MAX_VT_SYS_CLK_DIV),
+ .min_pix_clk_div = CCS_LIM(sensor, MIN_VT_PIX_CLK_DIV),
+ .max_pix_clk_div = CCS_LIM(sensor, MAX_VT_PIX_CLK_DIV),
+ .min_sys_clk_freq_hz = CCS_LIM(sensor, MIN_VT_SYS_CLK_FREQ_MHZ),
+ .max_sys_clk_freq_hz = CCS_LIM(sensor, MAX_VT_SYS_CLK_FREQ_MHZ),
+ .min_pix_clk_freq_hz = CCS_LIM(sensor, MIN_VT_PIX_CLK_FREQ_MHZ),
+ .max_pix_clk_freq_hz = CCS_LIM(sensor, MAX_VT_PIX_CLK_FREQ_MHZ),
+ },
.min_line_length_pck_bin = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK_BIN),
.min_line_length_pck = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK),
};
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 058/106] ccs-pll: Use correct VT divisor for calculating VT SYS divisor
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (46 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 057/106] ccs-pll: Split limits and PLL configuration into front and back parts Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 059/106] ccs-pll: End search if there are no better values available Sakari Ailus
` (48 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Use the correct video timing divisor to calculate the SYS divisor. Instead
of the current value, the minimum was used. This could have resulted in a
too low SYS divisor.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index b2f0fa14ff92..ea0f84fc8a90 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -365,14 +365,14 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
/* Check if this one is better. */
if (pix_div * sys_div
- <= roundup(min_vt_div, best_pix_div))
+ <= roundup(vt_div, best_pix_div))
best_pix_div = pix_div;
}
if (best_pix_div < INT_MAX >> 1)
break;
}
- pll->vt_bk.sys_clk_div = DIV_ROUND_UP(min_vt_div, best_pix_div);
+ pll->vt_bk.sys_clk_div = DIV_ROUND_UP(vt_div, best_pix_div);
pll->vt_bk.pix_clk_div = best_pix_div;
pll->vt_bk.sys_clk_freq_hz =
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 059/106] ccs-pll: End search if there are no better values available
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (47 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 058/106] ccs-pll: Use correct VT divisor for calculating VT SYS divisor Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 060/106] ccs-pll: Remove parallel bus support Sakari Ailus
` (47 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
The VT divisor search can be ended if we've already found the value that
corresponds exactly the total divisor, as there are no better (lower)
values available.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index ea0f84fc8a90..22e29127804a 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -352,6 +352,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
sys_div <= max_sys_div;
sys_div += 2 - (sys_div & 1)) {
uint16_t pix_div = DIV_ROUND_UP(vt_div, sys_div);
+ uint16_t rounded_div;
if (pix_div < lim->vt_bk.min_pix_clk_div
|| pix_div > lim->vt_bk.max_pix_clk_div) {
@@ -363,10 +364,15 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
continue;
}
+ rounded_div = roundup(vt_div, best_pix_div);
+
/* Check if this one is better. */
- if (pix_div * sys_div
- <= roundup(vt_div, best_pix_div))
+ if (pix_div * sys_div <= rounded_div)
best_pix_div = pix_div;
+
+ /* Bail out if we've already found the best value. */
+ if (vt_div == rounded_div)
+ break;
}
if (best_pix_div < INT_MAX >> 1)
break;
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 060/106] ccs-pll: Remove parallel bus support
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (48 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 059/106] ccs-pll: End search if there are no better values available Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 061/106] ccs-pll: Differentiate between CSI-2 D-PHY and C-PHY Sakari Ailus
` (46 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
The parallel bus PLL calculation has no users. Remove it.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 5 -----
drivers/media/i2c/ccs-pll.h | 14 ++++----------
2 files changed, 4 insertions(+), 15 deletions(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index 22e29127804a..da97a2b91717 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -435,11 +435,6 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
op_pll_fr->pll_op_clk_freq_hz = pll->link_freq * 2
* (pll->csi2.lanes / lane_op_clock_ratio);
break;
- case CCS_PLL_BUS_TYPE_PARALLEL:
- op_pll_fr->pll_op_clk_freq_hz = pll->link_freq * pll->bits_per_pixel
- / DIV_ROUND_UP(pll->bits_per_pixel,
- pll->parallel.bus_width);
- break;
default:
return -EINVAL;
}
diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h
index 03b1d8d11423..578c9272688a 100644
--- a/drivers/media/i2c/ccs-pll.h
+++ b/drivers/media/i2c/ccs-pll.h
@@ -13,8 +13,7 @@
#define CCS_PLL_H
/* CSI-2 or CCP-2 */
-#define CCS_PLL_BUS_TYPE_CSI2 0x00
-#define CCS_PLL_BUS_TYPE_PARALLEL 0x01
+#define CCS_PLL_BUS_TYPE_CSI2 0x00
/* op pix clock is for all lanes in total normally */
#define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0)
@@ -37,14 +36,9 @@ struct ccs_pll_branch_bk {
struct ccs_pll {
/* input values */
uint8_t bus_type;
- union {
- struct {
- uint8_t lanes;
- } csi2;
- struct {
- uint8_t bus_width;
- } parallel;
- };
+ struct {
+ uint8_t lanes;
+ } csi2;
unsigned long flags;
uint8_t binning_horizontal;
uint8_t binning_vertical;
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 061/106] ccs-pll: Differentiate between CSI-2 D-PHY and C-PHY
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (49 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 060/106] ccs-pll: Remove parallel bus support Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 062/106] ccs-pll: Move the flags field down, away from 8-bit fields Sakari Ailus
` (45 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Differentiate between CSI-2 D-PHY and C-PHY. This does not yet include
support for C-PHY.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 2 +-
drivers/media/i2c/ccs-pll.h | 3 ++-
drivers/media/i2c/ccs/ccs-core.c | 2 +-
3 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index da97a2b91717..c6435ed0597e 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -430,7 +430,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
pll->binning_vertical);
switch (pll->bus_type) {
- case CCS_PLL_BUS_TYPE_CSI2:
+ case CCS_PLL_BUS_TYPE_CSI2_DPHY:
/* CSI transfers 2 bits per clock per lane; thus times 2 */
op_pll_fr->pll_op_clk_freq_hz = pll->link_freq * 2
* (pll->csi2.lanes / lane_op_clock_ratio);
diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h
index 578c9272688a..d06a80c4fc52 100644
--- a/drivers/media/i2c/ccs-pll.h
+++ b/drivers/media/i2c/ccs-pll.h
@@ -13,7 +13,8 @@
#define CCS_PLL_H
/* CSI-2 or CCP-2 */
-#define CCS_PLL_BUS_TYPE_CSI2 0x00
+#define CCS_PLL_BUS_TYPE_CSI2_DPHY 0x00
+#define CCS_PLL_BUS_TYPE_CSI2_CPHY 0x01
/* op pix clock is for all lanes in total normally */
#define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index bc86cf0991df..2ee972bb4885 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -3192,7 +3192,7 @@ static int ccs_probe(struct i2c_client *client)
sensor->scale_m = CCS_LIM(sensor, SCALER_N_MIN);
/* prepare PLL configuration input values */
- sensor->pll.bus_type = CCS_PLL_BUS_TYPE_CSI2;
+ sensor->pll.bus_type = CCS_PLL_BUS_TYPE_CSI2_DPHY;
sensor->pll.csi2.lanes = sensor->hwcfg.lanes;
sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk;
sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN);
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 062/106] ccs-pll: Move the flags field down, away from 8-bit fields
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (50 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 061/106] ccs-pll: Differentiate between CSI-2 D-PHY and C-PHY Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 063/106] ccs-pll: Document the structs in the header as well as the function Sakari Ailus
` (44 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
This way the struct will use less memory, with better packing and no waste
due to unsigned long.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h
index d06a80c4fc52..1d908b23c934 100644
--- a/drivers/media/i2c/ccs-pll.h
+++ b/drivers/media/i2c/ccs-pll.h
@@ -40,12 +40,12 @@ struct ccs_pll {
struct {
uint8_t lanes;
} csi2;
- unsigned long flags;
uint8_t binning_horizontal;
uint8_t binning_vertical;
uint8_t scale_m;
uint8_t scale_n;
uint8_t bits_per_pixel;
+ uint16_t flags;
uint32_t link_freq;
uint32_t ext_clk_freq_hz;
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 063/106] ccs-pll: Document the structs in the header as well as the function
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (51 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 062/106] ccs-pll: Move the flags field down, away from 8-bit fields Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-11-05 12:18 ` Mauro Carvalho Chehab
2020-10-07 8:45 ` [PATCH v2 064/106] ccs-pll: Use the BIT macro Sakari Ailus
` (43 subsequent siblings)
96 siblings, 1 reply; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
The CCS pll is used by the CCS driver at the moment, but documenting the
interface makes sense. It's non-trivial and the calculator could be used
elsewhere.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.h | 88 +++++++++++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h
index 1d908b23c934..e01359f61476 100644
--- a/drivers/media/i2c/ccs-pll.h
+++ b/drivers/media/i2c/ccs-pll.h
@@ -20,6 +20,16 @@
#define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0)
#define CCS_PLL_FLAG_NO_OP_CLOCKS (1 << 1)
+/**
+ * struct ccs_pll_branch_fr - CCS PLL configuration (front)
+ *
+ * A single branch front-end of the CCS PLL tree.
+ *
+ * @pre_pll_clk_div: Pre-PLL clock divisor
+ * @pll_multiplier: PLL multiplier
+ * @pll_ip_freq_hz: PLL input clock frequency
+ * @pll_op_freq_hz: PLL output clock frequency
+ */
struct ccs_pll_branch_fr {
uint16_t pre_pll_clk_div;
uint16_t pll_multiplier;
@@ -27,6 +37,16 @@ struct ccs_pll_branch_fr {
uint32_t pll_op_clk_freq_hz;
};
+/**
+ * struct ccs_pll_branch_bk - CCS PLL configuration (back)
+ *
+ * A single branch back-end of the CCS PLL tree.
+ *
+ * @sys_clk_div: System clock divider
+ * @pix_clk_div: Pixel clock divider
+ * @sys_clk_freq_hz: System clock frequency
+ * @pix_clk_freq_hz: Pixel clock frequency
+ */
struct ccs_pll_branch_bk {
uint16_t sys_clk_div;
uint16_t pix_clk_div;
@@ -34,6 +54,29 @@ struct ccs_pll_branch_bk {
uint32_t pix_clk_freq_hz;
};
+/**
+ * struct ccs_pll - Full CCS PLL configuration
+ *
+ * All information required to calculate CCS PLL configuration.
+ *
+ * @bus_type: Type of the data bus, CCS_PLL_BUS_TYPE_* (input)
+ * @csi2.lanes: The number of the CSI-2 data lanes (input)
+ * @binning_vertical: Vertical binning factor (input)
+ * @binning_horizontal: Horizontal binning factor (input)
+ * @scale_m: Downscaling factor, M component, [16, max] (input)
+ * @scale_n: Downscaling factor, N component, typically 16 (input)
+ * @bits_per_pixel: Bits per pixel on the output data bus (input)
+ * @flags: CCS_PLL_FLAG_* (input)
+ * @link_freq: Chosen link frequency (input)
+ * @ext_clk_freq_hz: External clock frequency, i.e. the sensor's input clock
+ * (input)
+ * @vt_fr: Video timing front-end configuration (output)
+ * @vt_bk: Video timing back-end configuration (output)
+ * @op_bk: Operational timing back-end configuration (output)
+ * @pixel_rate_csi: Pixel rate on the output data bus (output)
+ * @pixel_rate_pixel_array: Nominal pixel rate in the sensor's pixel array
+ * (output)
+ */
struct ccs_pll {
/* input values */
uint8_t bus_type;
@@ -58,6 +101,18 @@ struct ccs_pll {
uint32_t pixel_rate_pixel_array;
};
+/**
+ * struct ccs_pll_branch_limits_fr - CCS PLL front-end limits
+ *
+ * @min_pre_pll_clk_div: Minimum pre-PLL clock divider
+ * @max_pre_pll_clk_div: Maximum pre-PLL clock divider
+ * @min_pll_ip_freq_hz: Minimum PLL input clock frequency
+ * @max_pll_ip_freq_hz: Maximum PLL input clock frequency
+ * @min_pll_multiplier: Minimum PLL multiplier
+ * @max_pll_multiplier: Maximum PLL multiplier
+ * @min_pll_op_freq_hz: Minimum PLL output clock frequency
+ * @max_pll_op_freq_hz: Maximum PLL output clock frequency
+ */
struct ccs_pll_branch_limits_fr {
uint16_t min_pre_pll_clk_div;
uint16_t max_pre_pll_clk_div;
@@ -69,6 +124,18 @@ struct ccs_pll_branch_limits_fr {
uint32_t max_pll_op_clk_freq_hz;
};
+/**
+ * struct ccs_pll_branch_limits_bk - CCS PLL back-end limits
+ *
+ * @min_sys_clk_div: Minimum system clock divider
+ * @max_sys_clk_div: Maximum system clock divider
+ * @min_sys_clk_freq_hz: Minimum system clock frequency
+ * @max_sys_clk_freq_hz: Maximum system clock frequency
+ * @min_pix_clk_div: Minimum pixel clock divider
+ * @max_pix_clk_div: Maximum pixel clock divider
+ * @min_pix_clk_freq_hz: Minimum pixel clock frequency
+ * @max_pix_clk_freq_hz: Maximum pixel clock frequency
+ */
struct ccs_pll_branch_limits_bk {
uint16_t min_sys_clk_div;
uint16_t max_sys_clk_div;
@@ -80,6 +147,17 @@ struct ccs_pll_branch_limits_bk {
uint32_t max_pix_clk_freq_hz;
};
+/**
+ * struct ccs_pll_limits - CCS PLL limits
+ *
+ * @min_ext_clk_freq_hz: Minimum external clock frequency
+ * @max_ext_clk_freq_hz: Maximum external clock frequency
+ * @vt_fr: Video timing front-end limits
+ * @vt_bk: Video timing back-end limits
+ * @op_bk: Operational timing back-end limits
+ * @min_line_length_pck_bin: Minimum line length in pixels, with binning
+ * @min_line_length_pck: Minimum line length in pixels without binning
+ */
struct ccs_pll_limits {
/* Strict PLL limits */
uint32_t min_ext_clk_freq_hz;
@@ -96,6 +174,16 @@ struct ccs_pll_limits {
struct device;
+/**
+ * ccs_pll_calculate - Calculate CCS PLL configuration based on input parameters
+ *
+ * @dev: Device pointer, used for printing messages
+ * @limits: Limits specific to the sensor
+ * @pll: Given PLL configuration
+ *
+ * Calculate the CCS PLL configuration based on the limits as well as given
+ * device specific, system specific or user configured input data.
+ */
int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits,
struct ccs_pll *pll);
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 064/106] ccs-pll: Use the BIT macro
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (52 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 063/106] ccs-pll: Document the structs in the header as well as the function Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 065/106] ccs-pll: Begin calculation from OP system clock frequency Sakari Ailus
` (42 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Use the BIT macro for setting individual bits.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.h | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h
index e01359f61476..f772ed8ef579 100644
--- a/drivers/media/i2c/ccs-pll.h
+++ b/drivers/media/i2c/ccs-pll.h
@@ -12,13 +12,16 @@
#ifndef CCS_PLL_H
#define CCS_PLL_H
+#include <linux/bits.h>
+
/* CSI-2 or CCP-2 */
#define CCS_PLL_BUS_TYPE_CSI2_DPHY 0x00
#define CCS_PLL_BUS_TYPE_CSI2_CPHY 0x01
+/* Old SMIA and implementation specific flags */
/* op pix clock is for all lanes in total normally */
-#define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0)
-#define CCS_PLL_FLAG_NO_OP_CLOCKS (1 << 1)
+#define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE BIT(0)
+#define CCS_PLL_FLAG_NO_OP_CLOCKS BIT(1)
/**
* struct ccs_pll_branch_fr - CCS PLL configuration (front)
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 065/106] ccs-pll: Begin calculation from OP system clock frequency
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (53 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 064/106] ccs-pll: Use the BIT macro Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 066/106] ccs-pll: Fix condition for pre-PLL divider lower bound Sakari Ailus
` (41 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
The OP system clock frequency defines the CSI-2 bus clock frequency, not
the PLL output clock frequency. Both values were overwritten in the end,
but the wrong limit value was used for the OP system clock frequency,
possibly leading to too high frequencies being used.
Also remove now duplicated calculation of OP system clock frequency later
in the PLL calculator.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index c6435ed0597e..584be36f8c66 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -247,10 +247,6 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
op_pll_fr->pll_op_clk_freq_hz = op_pll_fr->pll_ip_clk_freq_hz
* op_pll_fr->pll_multiplier;
- /* Derive pll_op_clk_freq_hz. */
- op_pll_bk->sys_clk_freq_hz =
- op_pll_fr->pll_op_clk_freq_hz / op_pll_bk->sys_clk_div;
-
op_pll_bk->pix_clk_div = pll->bits_per_pixel;
dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div);
@@ -432,7 +428,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
switch (pll->bus_type) {
case CCS_PLL_BUS_TYPE_CSI2_DPHY:
/* CSI transfers 2 bits per clock per lane; thus times 2 */
- op_pll_fr->pll_op_clk_freq_hz = pll->link_freq * 2
+ op_pll_bk->sys_clk_freq_hz = pll->link_freq * 2
* (pll->csi2.lanes / lane_op_clock_ratio);
break;
default:
@@ -454,8 +450,8 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
dev_dbg(dev, "pre-pll check: min / max op_pre_pll_clk_div: %u / %u\n",
min_op_pre_pll_clk_div, max_op_pre_pll_clk_div);
- i = gcd(op_pll_fr->pll_op_clk_freq_hz, pll->ext_clk_freq_hz);
- mul = op_pll_fr->pll_op_clk_freq_hz / i;
+ i = gcd(op_pll_bk->sys_clk_freq_hz, pll->ext_clk_freq_hz);
+ mul = op_pll_bk->sys_clk_freq_hz / i;
div = pll->ext_clk_freq_hz / i;
dev_dbg(dev, "mul %u / div %u\n", mul, div);
@@ -463,7 +459,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
max_t(uint16_t, min_op_pre_pll_clk_div,
clk_div_even_up(
DIV_ROUND_UP(mul * pll->ext_clk_freq_hz,
- op_lim_fr->max_pll_op_clk_freq_hz)));
+ op_lim_bk->max_sys_clk_freq_hz)));
dev_dbg(dev, "pll_op check: min / max op_pre_pll_clk_div: %u / %u\n",
min_op_pre_pll_clk_div, max_op_pre_pll_clk_div);
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 066/106] ccs-pll: Fix condition for pre-PLL divider lower bound
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (54 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 065/106] ccs-pll: Begin calculation from OP system clock frequency Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 067/106] ccs-pll: Avoid overflow in pre-PLL divisor lower bound search Sakari Ailus
` (40 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
The lower bound of the pre-PLL divider was calculated based on OP SYS
clock frequency which is also affected by the OP SYS clock divider. This
is wrong. The right clock frequency is that of the PLL output clock.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index 584be36f8c66..b45e6b30c528 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -459,7 +459,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
max_t(uint16_t, min_op_pre_pll_clk_div,
clk_div_even_up(
DIV_ROUND_UP(mul * pll->ext_clk_freq_hz,
- op_lim_bk->max_sys_clk_freq_hz)));
+ op_lim_fr->max_pll_op_clk_freq_hz)));
dev_dbg(dev, "pll_op check: min / max op_pre_pll_clk_div: %u / %u\n",
min_op_pre_pll_clk_div, max_op_pre_pll_clk_div);
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 067/106] ccs-pll: Avoid overflow in pre-PLL divisor lower bound search
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (55 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 066/106] ccs-pll: Fix condition for pre-PLL divider lower bound Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 068/106] ccs-pll: Fix comment on check against maximum PLL multiplier Sakari Ailus
` (39 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
The external clock frequency times the PLL multiplier may exceed the value
range of 32-bit unsigned integers. Instead perform the same calculation y
using two divisions.
The result has some potential to be different, but that's ok: this number
is used to limit the range of pre-PLL divisors to find optimal values. So
the effect of the rare case of a different result here would mean an
invalid pre-PLL divisor is tried. That will be found out a little later in
any case.
Also guard against dividing by zero if the external clock frequency is
higher than the maximum OP PLL output clock --- a rather improbable case.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index b45e6b30c528..78897a7c1448 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -40,6 +40,11 @@ static inline uint32_t is_one_or_even(uint32_t a)
return 1;
}
+static inline uint32_t one_or_more(uint32_t a)
+{
+ return a ?: 1;
+}
+
static int bounds_check(struct device *dev, uint32_t val,
uint32_t min, uint32_t max, char *str)
{
@@ -458,8 +463,10 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
min_op_pre_pll_clk_div =
max_t(uint16_t, min_op_pre_pll_clk_div,
clk_div_even_up(
- DIV_ROUND_UP(mul * pll->ext_clk_freq_hz,
- op_lim_fr->max_pll_op_clk_freq_hz)));
+ mul /
+ one_or_more(
+ DIV_ROUND_UP(op_lim_fr->max_pll_op_clk_freq_hz,
+ pll->ext_clk_freq_hz))));
dev_dbg(dev, "pll_op check: min / max op_pre_pll_clk_div: %u / %u\n",
min_op_pre_pll_clk_div, max_op_pre_pll_clk_div);
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 068/106] ccs-pll: Fix comment on check against maximum PLL multiplier
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (56 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 067/106] ccs-pll: Avoid overflow in pre-PLL divisor lower bound search Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 069/106] ccs-pll: Fix check for PLL multiplier upper bound Sakari Ailus
` (38 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
The comment is about minimum PLL multiplier but the related check really
deals with the maximum PLL multiplier.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index 78897a7c1448..f4c41d61e332 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -203,7 +203,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
/ div);
dev_dbg(dev, "more_mul_max: max_op_sys_clk_div check: %u\n",
more_mul_max);
- /* Ensure we won't go above min_pll_multiplier. */
+ /* Ensure we won't go above max_pll_multiplier. */
more_mul_max = min(more_mul_max,
DIV_ROUND_UP(op_lim_fr->max_pll_multiplier, mul));
dev_dbg(dev, "more_mul_max: min_pll_multiplier check: %u\n",
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 069/106] ccs-pll: Fix check for PLL multiplier upper bound
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (57 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 068/106] ccs-pll: Fix comment on check against maximum PLL multiplier Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 070/106] ccs-pll: Use explicit 32-bit unsigned type Sakari Ailus
` (37 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
The additional multiplier (for higher VT timing) of the PLL multiplier was
checked against the upper limit but the result was rounded up, possibly
producing too high additional multiplier. Round down instead to keep
within hardware limits.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index f4c41d61e332..b23e959000a4 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -204,8 +204,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
dev_dbg(dev, "more_mul_max: max_op_sys_clk_div check: %u\n",
more_mul_max);
/* Ensure we won't go above max_pll_multiplier. */
- more_mul_max = min(more_mul_max,
- DIV_ROUND_UP(op_lim_fr->max_pll_multiplier, mul));
+ more_mul_max = min(more_mul_max, op_lim_fr->max_pll_multiplier / mul);
dev_dbg(dev, "more_mul_max: min_pll_multiplier check: %u\n",
more_mul_max);
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 070/106] ccs-pll: Use explicit 32-bit unsigned type
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (58 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 069/106] ccs-pll: Fix check for PLL multiplier upper bound Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 071/106] ccs-pll: Add support for lane speed model Sakari Ailus
` (36 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Use uint32_t instead of unsigned int for a variable that contains
explicitly 32-bit numbers.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index b23e959000a4..d33a2575329c 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -177,7 +177,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
uint32_t more_mul_factor;
uint32_t min_vt_div, max_vt_div, vt_div;
uint32_t min_sys_div, max_sys_div;
- unsigned int i;
+ uint32_t i;
/*
* Get pre_pll_clk_div so that our pll_op_clk_freq_hz won't be
@@ -406,7 +406,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
uint16_t max_op_pre_pll_clk_div;
uint32_t lane_op_clock_ratio;
uint32_t mul, div;
- unsigned int i;
+ uint32_t i;
int rval = -EINVAL;
if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) {
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 071/106] ccs-pll: Add support for lane speed model
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (59 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 070/106] ccs-pll: Use explicit 32-bit unsigned type Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 072/106] ccs: " Sakari Ailus
` (35 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
CCS PLL includes a capability to calculate the VT clocks on per-lane
basis. Add support for this feature.
Move calculation of the pixel rate on the CSI-2 bus early in the function
as everything needed to calculate it is already available.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 36 +++++++++++++++++++++++++-----------
drivers/media/i2c/ccs-pll.h | 6 ++++++
2 files changed, 31 insertions(+), 11 deletions(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index d33a2575329c..9750b49d834a 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -251,11 +251,12 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
op_pll_fr->pll_op_clk_freq_hz = op_pll_fr->pll_ip_clk_freq_hz
* op_pll_fr->pll_multiplier;
- op_pll_bk->pix_clk_div = pll->bits_per_pixel;
- dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div);
-
+ op_pll_bk->pix_clk_div = pll->bits_per_pixel
+ * pll->op_lanes / pll->csi2.lanes;
op_pll_bk->pix_clk_freq_hz =
op_pll_bk->sys_clk_freq_hz / op_pll_bk->pix_clk_div;
+ dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div);
+
if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) {
/* No OP clocks --- VT clocks are used instead. */
@@ -283,15 +284,16 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
* divisors. One must make sure that horizontal blanking is
* enough to accommodate the CSI-2 sync codes.
*
- * Take scaling factor into account as well.
+ * Take scaling factor and number of VT lanes into account as well.
*
* Find absolute limits for the factor of vt divider.
*/
dev_dbg(dev, "scale_m: %u\n", pll->scale_m);
min_vt_div = DIV_ROUND_UP(op_pll_bk->pix_clk_div
- * op_pll_bk->sys_clk_div * pll->scale_n,
- lane_op_clock_ratio * vt_op_binning_div
- * pll->scale_m);
+ * op_pll_bk->sys_clk_div * pll->scale_n
+ * pll->vt_lanes,
+ pll->op_lanes * vt_op_binning_div
+ * pll->scale_m * lane_op_clock_ratio);
/* Find smallest and biggest allowed vt divisor. */
dev_dbg(dev, "min_vt_div: %u\n", min_vt_div);
@@ -387,9 +389,8 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
pll->vt_bk.sys_clk_freq_hz / pll->vt_bk.pix_clk_div;
out_skip_vt_calc:
- pll->pixel_rate_csi =
- op_pll_bk->pix_clk_freq_hz * lane_op_clock_ratio;
- pll->pixel_rate_pixel_array = pll->vt_bk.pix_clk_freq_hz;
+ pll->pixel_rate_pixel_array =
+ pll->vt_bk.pix_clk_freq_hz * pll->vt_lanes;
return check_all_bounds(dev, lim, op_lim_fr, op_lim_bk, pll, op_pll_fr,
op_pll_bk);
@@ -409,6 +410,13 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
uint32_t i;
int rval = -EINVAL;
+ if (!(pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL)) {
+ pll->op_lanes = 1;
+ pll->vt_lanes = 1;
+ }
+ dev_dbg(dev, "vt_lanes: %u\n", pll->vt_lanes);
+ dev_dbg(dev, "op_lanes: %u\n", pll->op_lanes);
+
if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) {
/*
* If there's no OP PLL at all, use the VT values
@@ -433,12 +441,18 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
case CCS_PLL_BUS_TYPE_CSI2_DPHY:
/* CSI transfers 2 bits per clock per lane; thus times 2 */
op_pll_bk->sys_clk_freq_hz = pll->link_freq * 2
- * (pll->csi2.lanes / lane_op_clock_ratio);
+ * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
+ 1 : pll->csi2.lanes) / lane_op_clock_ratio;
break;
default:
return -EINVAL;
}
+ pll->pixel_rate_csi =
+ op_pll_bk->pix_clk_freq_hz
+ * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
+ pll->csi2.lanes : 1) * lane_op_clock_ratio;
+
/* Figure out limits for OP pre-pll divider based on extclk */
dev_dbg(dev, "min / max op_pre_pll_clk_div: %u / %u\n",
op_lim_fr->min_pre_pll_clk_div, op_lim_fr->max_pre_pll_clk_div);
diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h
index f772ed8ef579..57308b8f3a8a 100644
--- a/drivers/media/i2c/ccs-pll.h
+++ b/drivers/media/i2c/ccs-pll.h
@@ -22,6 +22,8 @@
/* op pix clock is for all lanes in total normally */
#define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE BIT(0)
#define CCS_PLL_FLAG_NO_OP_CLOCKS BIT(1)
+/* CCS PLL flags */
+#define CCS_PLL_FLAG_LANE_SPEED_MODEL BIT(2)
/**
* struct ccs_pll_branch_fr - CCS PLL configuration (front)
@@ -63,6 +65,8 @@ struct ccs_pll_branch_bk {
* All information required to calculate CCS PLL configuration.
*
* @bus_type: Type of the data bus, CCS_PLL_BUS_TYPE_* (input)
+ * @op_lanes: Number of operational lanes (input)
+ * @vt_lanes: Number of video timing lanes (input)
* @csi2.lanes: The number of the CSI-2 data lanes (input)
* @binning_vertical: Vertical binning factor (input)
* @binning_horizontal: Horizontal binning factor (input)
@@ -83,6 +87,8 @@ struct ccs_pll_branch_bk {
struct ccs_pll {
/* input values */
uint8_t bus_type;
+ uint8_t op_lanes;
+ uint8_t vt_lanes;
struct {
uint8_t lanes;
} csi2;
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 072/106] ccs: Add support for lane speed model
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (60 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 071/106] ccs-pll: Add support for lane speed model Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 073/106] ccs-pll: Add support for decoupled OP domain calculation Sakari Ailus
` (34 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Convey the relevant PLL flags to the PLL calculator. Also the lane speed
model affects how the link rate is calculated on the CSI-2 bus, as the
rate is total of all lanes.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 2ee972bb4885..8b022f2ea17e 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -387,7 +387,9 @@ static int ccs_pll_configure(struct ccs_sensor *sensor)
/* Lane op clock ratio does not apply here. */
rval = ccs_write(sensor, REQUESTED_LINK_RATE,
DIV_ROUND_UP(pll->op_bk.sys_clk_freq_hz,
- 1000000 / 256 / 256));
+ 1000000 / 256 / 256) *
+ (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
+ sensor->pll.csi2.lanes : 1));
if (rval < 0 || sensor->pll.flags & CCS_PLL_FLAG_NO_OP_CLOCKS)
return rval;
@@ -3194,6 +3196,13 @@ static int ccs_probe(struct i2c_client *client)
/* prepare PLL configuration input values */
sensor->pll.bus_type = CCS_PLL_BUS_TYPE_CSI2_DPHY;
sensor->pll.csi2.lanes = sensor->hwcfg.lanes;
+ if (CCS_LIM(sensor, CLOCK_CALCULATION) &
+ CCS_CLOCK_CALCULATION_LANE_SPEED) {
+ sensor->pll.vt_lanes =
+ CCS_LIM(sensor, NUM_OF_VT_LANES) + 1;
+ sensor->pll.op_lanes = sensor->pll.vt_lanes;
+ sensor->pll.flags |= CCS_PLL_FLAG_LANE_SPEED_MODEL;
+ }
sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk;
sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN);
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 073/106] ccs-pll: Add support for decoupled OP domain calculation
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (61 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 072/106] ccs: " Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 074/106] ccs-pll: Add support for extended input PLL clock divider Sakari Ailus
` (33 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Add support for decoupled OP domain clock calculation. This means that the
number of VT and OP domain clocks are no longer dependent on the number of
CSI-2 lanes in the lane speed mode.
The support also replaces the existing quirk flag to calculate OP domain
clocks per lane.
Also support decoupled OP domain calculation in the CCS driver.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 22 +++++++---------------
drivers/media/i2c/ccs-pll.h | 1 +
drivers/media/i2c/ccs/ccs-core.c | 14 +++++++++++---
drivers/media/i2c/ccs/ccs-quirk.c | 5 ++++-
4 files changed, 23 insertions(+), 19 deletions(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index 9750b49d834a..cb19a36e54df 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -162,7 +162,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
const struct ccs_pll_branch_limits_bk *op_lim_bk,
struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr,
struct ccs_pll_branch_bk *op_pll_bk, uint32_t mul,
- uint32_t div, uint32_t lane_op_clock_ratio)
+ uint32_t div)
{
uint32_t sys_div;
uint32_t best_pix_div = INT_MAX >> 1;
@@ -194,7 +194,8 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
min_t(uint32_t,
more_mul_max,
op_lim_fr->max_pll_op_clk_freq_hz
- / (pll->ext_clk_freq_hz / op_pll_fr->pre_pll_clk_div * mul));
+ / (pll->ext_clk_freq_hz /
+ op_pll_fr->pre_pll_clk_div * mul));
dev_dbg(dev, "more_mul_max: max_pll_op_clk_freq_hz check: %u\n",
more_mul_max);
/* Don't go above the division capability of op sys clock divider. */
@@ -257,7 +258,6 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
op_pll_bk->sys_clk_freq_hz / op_pll_bk->pix_clk_div;
dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div);
-
if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) {
/* No OP clocks --- VT clocks are used instead. */
goto out_skip_vt_calc;
@@ -293,7 +293,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
* op_pll_bk->sys_clk_div * pll->scale_n
* pll->vt_lanes,
pll->op_lanes * vt_op_binning_div
- * pll->scale_m * lane_op_clock_ratio);
+ * pll->scale_m);
/* Find smallest and biggest allowed vt divisor. */
dev_dbg(dev, "min_vt_div: %u\n", min_vt_div);
@@ -405,7 +405,6 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
struct ccs_pll_branch_bk *op_pll_bk = &pll->op_bk;
uint16_t min_op_pre_pll_clk_div;
uint16_t max_op_pre_pll_clk_div;
- uint32_t lane_op_clock_ratio;
uint32_t mul, div;
uint32_t i;
int rval = -EINVAL;
@@ -428,12 +427,6 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
op_pll_bk = &pll->vt_bk;
}
- if (pll->flags & CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE)
- lane_op_clock_ratio = pll->csi2.lanes;
- else
- lane_op_clock_ratio = 1;
- dev_dbg(dev, "lane_op_clock_ratio: %u\n", lane_op_clock_ratio);
-
dev_dbg(dev, "binning: %ux%u\n", pll->binning_horizontal,
pll->binning_vertical);
@@ -442,7 +435,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
/* CSI transfers 2 bits per clock per lane; thus times 2 */
op_pll_bk->sys_clk_freq_hz = pll->link_freq * 2
* (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
- 1 : pll->csi2.lanes) / lane_op_clock_ratio;
+ 1 : pll->csi2.lanes);
break;
default:
return -EINVAL;
@@ -451,7 +444,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
pll->pixel_rate_csi =
op_pll_bk->pix_clk_freq_hz
* (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
- pll->csi2.lanes : 1) * lane_op_clock_ratio;
+ pll->csi2.lanes : 1);
/* Figure out limits for OP pre-pll divider based on extclk */
dev_dbg(dev, "min / max op_pre_pll_clk_div: %u / %u\n",
@@ -487,8 +480,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
op_pll_fr->pre_pll_clk_div <= max_op_pre_pll_clk_div;
op_pll_fr->pre_pll_clk_div += 2 - (op_pll_fr->pre_pll_clk_div & 1)) {
rval = __ccs_pll_calculate(dev, lim, op_lim_fr, op_lim_bk, pll,
- op_pll_fr, op_pll_bk, mul, div,
- lane_op_clock_ratio);
+ op_pll_fr, op_pll_bk, mul, div);
if (rval)
continue;
diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h
index 57308b8f3a8a..165de20af079 100644
--- a/drivers/media/i2c/ccs-pll.h
+++ b/drivers/media/i2c/ccs-pll.h
@@ -24,6 +24,7 @@
#define CCS_PLL_FLAG_NO_OP_CLOCKS BIT(1)
/* CCS PLL flags */
#define CCS_PLL_FLAG_LANE_SPEED_MODEL BIT(2)
+#define CCS_PLL_FLAG_LINK_DECOUPLED BIT(3)
/**
* struct ccs_pll_branch_fr - CCS PLL configuration (front)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 8b022f2ea17e..c3c4f59670e2 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -3198,10 +3198,18 @@ static int ccs_probe(struct i2c_client *client)
sensor->pll.csi2.lanes = sensor->hwcfg.lanes;
if (CCS_LIM(sensor, CLOCK_CALCULATION) &
CCS_CLOCK_CALCULATION_LANE_SPEED) {
- sensor->pll.vt_lanes =
- CCS_LIM(sensor, NUM_OF_VT_LANES) + 1;
- sensor->pll.op_lanes = sensor->pll.vt_lanes;
sensor->pll.flags |= CCS_PLL_FLAG_LANE_SPEED_MODEL;
+ if (CCS_LIM(sensor, CLOCK_CALCULATION) &
+ CCS_CLOCK_CALCULATION_LINK_DECOUPLED) {
+ sensor->pll.vt_lanes =
+ CCS_LIM(sensor, NUM_OF_VT_LANES) + 1;
+ sensor->pll.op_lanes =
+ CCS_LIM(sensor, NUM_OF_OP_LANES) + 1;
+ sensor->pll.flags |= CCS_PLL_FLAG_LINK_DECOUPLED;
+ } else {
+ sensor->pll.vt_lanes = sensor->pll.csi2.lanes;
+ sensor->pll.op_lanes = sensor->pll.csi2.lanes;
+ }
}
sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk;
sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN);
diff --git a/drivers/media/i2c/ccs/ccs-quirk.c b/drivers/media/i2c/ccs/ccs-quirk.c
index 4fe8c6f70579..e3d4c7a275bc 100644
--- a/drivers/media/i2c/ccs/ccs-quirk.c
+++ b/drivers/media/i2c/ccs/ccs-quirk.c
@@ -190,7 +190,10 @@ static int jt8ev1_post_streamoff(struct ccs_sensor *sensor)
static int jt8ev1_init(struct ccs_sensor *sensor)
{
- sensor->pll.flags |= CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE;
+ sensor->pll.flags |= CCS_PLL_FLAG_LANE_SPEED_MODEL |
+ CCS_PLL_FLAG_LINK_DECOUPLED;
+ sensor->pll.vt_lanes = 1;
+ sensor->pll.op_lanes = sensor->pll.csi2.lanes;
return 0;
}
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 074/106] ccs-pll: Add support for extended input PLL clock divider
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (62 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 073/106] ccs-pll: Add support for decoupled OP domain calculation Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 075/106] ccs-pll: Support two cycles per pixel on OP domain Sakari Ailus
` (32 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
CCS allows odd PLL dividers other than 1, granted that the corresponding
capability bit is set. Support this both in the PLL calculator and the CCS
driver.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 4 +++-
drivers/media/i2c/ccs-pll.h | 1 +
drivers/media/i2c/ccs/ccs-core.c | 3 +++
3 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index cb19a36e54df..62939ca5b8e2 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -478,7 +478,9 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
for (op_pll_fr->pre_pll_clk_div = min_op_pre_pll_clk_div;
op_pll_fr->pre_pll_clk_div <= max_op_pre_pll_clk_div;
- op_pll_fr->pre_pll_clk_div += 2 - (op_pll_fr->pre_pll_clk_div & 1)) {
+ op_pll_fr->pre_pll_clk_div +=
+ (pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 :
+ 2 - (op_pll_fr->pre_pll_clk_div & 1)) {
rval = __ccs_pll_calculate(dev, lim, op_lim_fr, op_lim_bk, pll,
op_pll_fr, op_pll_bk, mul, div);
if (rval)
diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h
index 165de20af079..7c2b7a85de6a 100644
--- a/drivers/media/i2c/ccs-pll.h
+++ b/drivers/media/i2c/ccs-pll.h
@@ -25,6 +25,7 @@
/* CCS PLL flags */
#define CCS_PLL_FLAG_LANE_SPEED_MODEL BIT(2)
#define CCS_PLL_FLAG_LINK_DECOUPLED BIT(3)
+#define CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER BIT(4)
/**
* struct ccs_pll_branch_fr - CCS PLL configuration (front)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index c3c4f59670e2..00957568407a 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -3211,6 +3211,9 @@ static int ccs_probe(struct i2c_client *client)
sensor->pll.op_lanes = sensor->pll.csi2.lanes;
}
}
+ if (CCS_LIM(sensor, CLOCK_TREE_PLL_CAPABILITY) &
+ CCS_CLOCK_TREE_PLL_CAPABILITY_EXT_DIVIDER)
+ sensor->pll.flags |= CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER;
sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk;
sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN);
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 075/106] ccs-pll: Support two cycles per pixel on OP domain
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (63 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 074/106] ccs-pll: Add support for extended input PLL clock divider Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 076/106] ccs-pll: Add support flexible OP PLL pixel clock divider Sakari Ailus
` (31 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
The l parameter defines the number of clock cycles to process a single
pixel per OP lane. It is calculated based on a new register
op_bits_per_lane.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 19 +++++++++++++------
drivers/media/i2c/ccs-pll.h | 2 ++
drivers/media/i2c/ccs/ccs-core.c | 1 +
3 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index 62939ca5b8e2..60ab0c043c7a 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -162,7 +162,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
const struct ccs_pll_branch_limits_bk *op_lim_bk,
struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr,
struct ccs_pll_branch_bk *op_pll_bk, uint32_t mul,
- uint32_t div)
+ uint32_t div, uint32_t l)
{
uint32_t sys_div;
uint32_t best_pix_div = INT_MAX >> 1;
@@ -252,10 +252,15 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
op_pll_fr->pll_op_clk_freq_hz = op_pll_fr->pll_ip_clk_freq_hz
* op_pll_fr->pll_multiplier;
- op_pll_bk->pix_clk_div = pll->bits_per_pixel
- * pll->op_lanes / pll->csi2.lanes;
+ if (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL)
+ op_pll_bk->pix_clk_div = pll->bits_per_pixel
+ * pll->op_lanes / pll->csi2.lanes / l;
+ else
+ op_pll_bk->pix_clk_div = pll->bits_per_pixel / l;
+
op_pll_bk->pix_clk_freq_hz =
op_pll_bk->sys_clk_freq_hz / op_pll_bk->pix_clk_div;
+
dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div);
if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) {
@@ -291,7 +296,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
dev_dbg(dev, "scale_m: %u\n", pll->scale_m);
min_vt_div = DIV_ROUND_UP(op_pll_bk->pix_clk_div
* op_pll_bk->sys_clk_div * pll->scale_n
- * pll->vt_lanes,
+ * pll->vt_lanes * l,
pll->op_lanes * vt_op_binning_div
* pll->scale_m);
@@ -406,6 +411,8 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
uint16_t min_op_pre_pll_clk_div;
uint16_t max_op_pre_pll_clk_div;
uint32_t mul, div;
+ uint32_t l = (!pll->op_bits_per_lane ||
+ pll->op_bits_per_lane >= pll->bits_per_pixel) ? 1 : 2;
uint32_t i;
int rval = -EINVAL;
@@ -444,7 +451,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
pll->pixel_rate_csi =
op_pll_bk->pix_clk_freq_hz
* (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
- pll->csi2.lanes : 1);
+ pll->csi2.lanes : 1) / l;
/* Figure out limits for OP pre-pll divider based on extclk */
dev_dbg(dev, "min / max op_pre_pll_clk_div: %u / %u\n",
@@ -482,7 +489,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
(pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 :
2 - (op_pll_fr->pre_pll_clk_div & 1)) {
rval = __ccs_pll_calculate(dev, lim, op_lim_fr, op_lim_bk, pll,
- op_pll_fr, op_pll_bk, mul, div);
+ op_pll_fr, op_pll_bk, mul, div, l);
if (rval)
continue;
diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h
index 7c2b7a85de6a..dd97cd6dca0d 100644
--- a/drivers/media/i2c/ccs-pll.h
+++ b/drivers/media/i2c/ccs-pll.h
@@ -75,6 +75,7 @@ struct ccs_pll_branch_bk {
* @scale_m: Downscaling factor, M component, [16, max] (input)
* @scale_n: Downscaling factor, N component, typically 16 (input)
* @bits_per_pixel: Bits per pixel on the output data bus (input)
+ * @op_bits_per_lane: Number of bits per OP lane (input)
* @flags: CCS_PLL_FLAG_* (input)
* @link_freq: Chosen link frequency (input)
* @ext_clk_freq_hz: External clock frequency, i.e. the sensor's input clock
@@ -99,6 +100,7 @@ struct ccs_pll {
uint8_t scale_m;
uint8_t scale_n;
uint8_t bits_per_pixel;
+ uint8_t op_bits_per_lane;
uint16_t flags;
uint32_t link_freq;
uint32_t ext_clk_freq_hz;
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 00957568407a..8f8bda98b0b7 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -3214,6 +3214,7 @@ static int ccs_probe(struct i2c_client *client)
if (CCS_LIM(sensor, CLOCK_TREE_PLL_CAPABILITY) &
CCS_CLOCK_TREE_PLL_CAPABILITY_EXT_DIVIDER)
sensor->pll.flags |= CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER;
+ sensor->pll.op_bits_per_lane = CCS_LIM(sensor, OP_BITS_PER_LANE);
sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk;
sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN);
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 076/106] ccs-pll: Add support flexible OP PLL pixel clock divider
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (64 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 075/106] ccs-pll: Support two cycles per pixel on OP domain Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 077/106] ccs-pll: Add sanity checks Sakari Ailus
` (30 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Flexible OP PLL pixel clock divider allows a higher OP pixel clock than
what the bus can transfer. This generally makes it easier to select pixel
clock dividers.
This changes how the pixel rate on the bus and minimum VT divisor are
calculated, as the pixel rate is no longer directly determined by the
OP pixel clock and the number of the lanes.
Also add a sanity check for sensors that do not support flexible OP PLL
pixel clock divider. This could have caused the PLL calculator to come up
with an invalid configuration for those devices.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 26 +++++++++++++++++++-------
drivers/media/i2c/ccs-pll.h | 1 +
drivers/media/i2c/ccs/ccs-core.c | 4 +++-
3 files changed, 23 insertions(+), 8 deletions(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index 60ab0c043c7a..e3a6493fd601 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -294,11 +294,11 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
* Find absolute limits for the factor of vt divider.
*/
dev_dbg(dev, "scale_m: %u\n", pll->scale_m);
- min_vt_div = DIV_ROUND_UP(op_pll_bk->pix_clk_div
- * op_pll_bk->sys_clk_div * pll->scale_n
- * pll->vt_lanes * l,
- pll->op_lanes * vt_op_binning_div
- * pll->scale_m);
+ min_vt_div = DIV_ROUND_UP(pll->bits_per_pixel * op_pll_bk->sys_clk_div
+ * pll->scale_n * pll->vt_lanes,
+ (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
+ pll->csi2.lanes : 1)
+ * vt_op_binning_div * pll->scale_m);
/* Find smallest and biggest allowed vt divisor. */
dev_dbg(dev, "min_vt_div: %u\n", min_vt_div);
@@ -420,6 +420,18 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
pll->op_lanes = 1;
pll->vt_lanes = 1;
}
+
+ /*
+ * Make sure op_pix_clk_div will be integer --- unless flexible
+ * op_pix_clk_div is supported
+ */
+ if (!(pll->flags & CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV) &&
+ (pll->bits_per_pixel * pll->op_lanes) % (pll->csi2.lanes * l)) {
+ dev_dbg(dev, "op_pix_clk_div not an integer (bpp %u, op lanes %u, lanes %u, l %u)\n",
+ pll->bits_per_pixel, pll->op_lanes, pll->csi2.lanes, l);
+ return -EINVAL;
+ }
+
dev_dbg(dev, "vt_lanes: %u\n", pll->vt_lanes);
dev_dbg(dev, "op_lanes: %u\n", pll->op_lanes);
@@ -449,9 +461,9 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
}
pll->pixel_rate_csi =
- op_pll_bk->pix_clk_freq_hz
+ op_pll_bk->sys_clk_freq_hz
* (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
- pll->csi2.lanes : 1) / l;
+ pll->csi2.lanes : 1) / pll->bits_per_pixel / l;
/* Figure out limits for OP pre-pll divider based on extclk */
dev_dbg(dev, "min / max op_pre_pll_clk_div: %u / %u\n",
diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h
index dd97cd6dca0d..0c25c5f5d4e4 100644
--- a/drivers/media/i2c/ccs-pll.h
+++ b/drivers/media/i2c/ccs-pll.h
@@ -26,6 +26,7 @@
#define CCS_PLL_FLAG_LANE_SPEED_MODEL BIT(2)
#define CCS_PLL_FLAG_LINK_DECOUPLED BIT(3)
#define CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER BIT(4)
+#define CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV BIT(5)
/**
* struct ccs_pll_branch_fr - CCS PLL configuration (front)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 8f8bda98b0b7..ab6abcf4c1dd 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -30,7 +30,6 @@
#include <media/v4l2-device.h>
#include "ccs.h"
-#include "ccs-limits.h"
#define CCS_ALIGN_DIM(dim, flags) \
((flags) & V4L2_SEL_FLAG_GE \
@@ -3214,6 +3213,9 @@ static int ccs_probe(struct i2c_client *client)
if (CCS_LIM(sensor, CLOCK_TREE_PLL_CAPABILITY) &
CCS_CLOCK_TREE_PLL_CAPABILITY_EXT_DIVIDER)
sensor->pll.flags |= CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER;
+ if (CCS_LIM(sensor, CLOCK_TREE_PLL_CAPABILITY) &
+ CCS_CLOCK_TREE_PLL_CAPABILITY_FLEXIBLE_OP_PIX_CLK_DIV)
+ sensor->pll.flags |= CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV;
sensor->pll.op_bits_per_lane = CCS_LIM(sensor, OP_BITS_PER_LANE);
sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk;
sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN);
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 077/106] ccs-pll: Add sanity checks
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (65 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 076/106] ccs-pll: Add support flexible OP PLL pixel clock divider Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 078/106] ccs-pll: Add C-PHY support Sakari Ailus
` (29 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Add sanity checks for fields that could cause division by zero.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index e3a6493fd601..420d2c4d7b2c 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -421,6 +421,15 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
pll->vt_lanes = 1;
}
+ if (!pll->op_lanes || !pll->vt_lanes || !pll->bits_per_pixel ||
+ !pll->ext_clk_freq_hz || !pll->link_freq || !pll->scale_m ||
+ !op_lim_fr->min_pll_ip_clk_freq_hz ||
+ !op_lim_fr->max_pll_ip_clk_freq_hz ||
+ !op_lim_fr->min_pll_op_clk_freq_hz ||
+ !op_lim_fr->max_pll_op_clk_freq_hz ||
+ !op_lim_bk->max_sys_clk_div || !op_lim_fr->max_pll_multiplier)
+ return -EINVAL;
+
/*
* Make sure op_pix_clk_div will be integer --- unless flexible
* op_pix_clk_div is supported
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 078/106] ccs-pll: Add C-PHY support
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (66 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 077/106] ccs-pll: Add sanity checks Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 079/106] ccs-pll: Split off VT subtree calculation Sakari Ailus
` (28 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Add C-PHY support for the CCS PLL calculator.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 35 ++++++++++++++++++++++++++---------
1 file changed, 26 insertions(+), 9 deletions(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index 420d2c4d7b2c..0fa7c6f67195 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -145,6 +145,10 @@ static int check_all_bounds(struct device *dev,
return rval;
}
+#define CPHY_CONST 7
+#define DPHY_CONST 16
+#define PHY_CONST_DIV 16
+
/*
* Heuristically guess the PLL tree for a given common multiplier and
* divisor. Begin with the operational timing and continue to video
@@ -162,7 +166,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
const struct ccs_pll_branch_limits_bk *op_lim_bk,
struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr,
struct ccs_pll_branch_bk *op_pll_bk, uint32_t mul,
- uint32_t div, uint32_t l)
+ uint32_t div, uint32_t l, bool cphy, uint32_t phy_const)
{
uint32_t sys_div;
uint32_t best_pix_div = INT_MAX >> 1;
@@ -254,9 +258,11 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
if (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL)
op_pll_bk->pix_clk_div = pll->bits_per_pixel
- * pll->op_lanes / pll->csi2.lanes / l;
+ * pll->op_lanes * phy_const
+ / PHY_CONST_DIV / pll->csi2.lanes / l;
else
- op_pll_bk->pix_clk_div = pll->bits_per_pixel / l;
+ op_pll_bk->pix_clk_div =
+ pll->bits_per_pixel * phy_const / PHY_CONST_DIV / l;
op_pll_bk->pix_clk_freq_hz =
op_pll_bk->sys_clk_freq_hz / op_pll_bk->pix_clk_div;
@@ -295,10 +301,11 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
*/
dev_dbg(dev, "scale_m: %u\n", pll->scale_m);
min_vt_div = DIV_ROUND_UP(pll->bits_per_pixel * op_pll_bk->sys_clk_div
- * pll->scale_n * pll->vt_lanes,
+ * pll->scale_n * pll->vt_lanes * phy_const,
(pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
pll->csi2.lanes : 1)
- * vt_op_binning_div * pll->scale_m);
+ * vt_op_binning_div * pll->scale_m
+ * PHY_CONST_DIV);
/* Find smallest and biggest allowed vt divisor. */
dev_dbg(dev, "min_vt_div: %u\n", min_vt_div);
@@ -408,6 +415,8 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
const struct ccs_pll_branch_limits_bk *op_lim_bk = &lim->op_bk;
struct ccs_pll_branch_fr *op_pll_fr = &pll->vt_fr;
struct ccs_pll_branch_bk *op_pll_bk = &pll->op_bk;
+ bool cphy = pll->bus_type == CCS_PLL_BUS_TYPE_CSI2_CPHY;
+ uint32_t phy_const = cphy ? CPHY_CONST : DPHY_CONST;
uint16_t min_op_pre_pll_clk_div;
uint16_t max_op_pre_pll_clk_div;
uint32_t mul, div;
@@ -465,14 +474,21 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
* (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
1 : pll->csi2.lanes);
break;
+ case CCS_PLL_BUS_TYPE_CSI2_CPHY:
+ op_pll_bk->sys_clk_freq_hz =
+ pll->link_freq
+ * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
+ 1 : pll->csi2.lanes);
+ break;
default:
return -EINVAL;
}
pll->pixel_rate_csi =
- op_pll_bk->sys_clk_freq_hz
- * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
- pll->csi2.lanes : 1) / pll->bits_per_pixel / l;
+ div_u64((uint64_t)op_pll_bk->sys_clk_freq_hz
+ * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
+ pll->csi2.lanes : 1) * PHY_CONST_DIV,
+ phy_const * pll->bits_per_pixel * l);
/* Figure out limits for OP pre-pll divider based on extclk */
dev_dbg(dev, "min / max op_pre_pll_clk_div: %u / %u\n",
@@ -510,7 +526,8 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
(pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 :
2 - (op_pll_fr->pre_pll_clk_div & 1)) {
rval = __ccs_pll_calculate(dev, lim, op_lim_fr, op_lim_bk, pll,
- op_pll_fr, op_pll_bk, mul, div, l);
+ op_pll_fr, op_pll_bk, mul, div, l,
+ cphy, phy_const);
if (rval)
continue;
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 079/106] ccs-pll: Split off VT subtree calculation
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (67 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 078/106] ccs-pll: Add C-PHY support Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 080/106] ccs-pll: Check for derating and overrating, support non-derating sensors Sakari Ailus
` (27 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Split off the VT sub clock tree calculation from the rest, into its own
function. Also call the op_pll_fr argument pll_fr, since soon these may
not be OP tree values.
This paves way for additional features in the future such as dual PLL
support.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 255 ++++++++++++++++++------------------
1 file changed, 131 insertions(+), 124 deletions(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index 0fa7c6f67195..3d43e737155f 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -149,130 +149,18 @@ static int check_all_bounds(struct device *dev,
#define DPHY_CONST 16
#define PHY_CONST_DIV 16
-/*
- * Heuristically guess the PLL tree for a given common multiplier and
- * divisor. Begin with the operational timing and continue to video
- * timing once operational timing has been verified.
- *
- * @mul is the PLL multiplier and @div is the common divisor
- * (pre_pll_clk_div and op_sys_clk_div combined). The final PLL
- * multiplier will be a multiple of @mul.
- *
- * @return Zero on success, error code on error.
- */
-static int
-__ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
- const struct ccs_pll_branch_limits_fr *op_lim_fr,
- const struct ccs_pll_branch_limits_bk *op_lim_bk,
- struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr,
- struct ccs_pll_branch_bk *op_pll_bk, uint32_t mul,
- uint32_t div, uint32_t l, bool cphy, uint32_t phy_const)
+static void
+__ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
+ const struct ccs_pll_branch_limits_bk *op_lim_bk,
+ struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr,
+ struct ccs_pll_branch_bk *op_pll_bk, bool cphy,
+ uint32_t phy_const)
{
uint32_t sys_div;
uint32_t best_pix_div = INT_MAX >> 1;
uint32_t vt_op_binning_div;
- /*
- * Higher multipliers (and divisors) are often required than
- * necessitated by the external clock and the output clocks.
- * There are limits for all values in the clock tree. These
- * are the minimum and maximum multiplier for mul.
- */
- uint32_t more_mul_min, more_mul_max;
- uint32_t more_mul_factor;
uint32_t min_vt_div, max_vt_div, vt_div;
uint32_t min_sys_div, max_sys_div;
- uint32_t i;
-
- /*
- * Get pre_pll_clk_div so that our pll_op_clk_freq_hz won't be
- * too high.
- */
- dev_dbg(dev, "op_pre_pll_clk_div %u\n", op_pll_fr->pre_pll_clk_div);
-
- /* Don't go above max pll multiplier. */
- more_mul_max = op_lim_fr->max_pll_multiplier / mul;
- dev_dbg(dev, "more_mul_max: max_op_pll_multiplier check: %u\n",
- more_mul_max);
- /* Don't go above max pll op frequency. */
- more_mul_max =
- min_t(uint32_t,
- more_mul_max,
- op_lim_fr->max_pll_op_clk_freq_hz
- / (pll->ext_clk_freq_hz /
- op_pll_fr->pre_pll_clk_div * mul));
- dev_dbg(dev, "more_mul_max: max_pll_op_clk_freq_hz check: %u\n",
- more_mul_max);
- /* Don't go above the division capability of op sys clock divider. */
- more_mul_max = min(more_mul_max,
- op_lim_bk->max_sys_clk_div * op_pll_fr->pre_pll_clk_div
- / div);
- dev_dbg(dev, "more_mul_max: max_op_sys_clk_div check: %u\n",
- more_mul_max);
- /* Ensure we won't go above max_pll_multiplier. */
- more_mul_max = min(more_mul_max, op_lim_fr->max_pll_multiplier / mul);
- dev_dbg(dev, "more_mul_max: min_pll_multiplier check: %u\n",
- more_mul_max);
-
- /* Ensure we won't go below min_pll_op_clk_freq_hz. */
- more_mul_min = DIV_ROUND_UP(op_lim_fr->min_pll_op_clk_freq_hz,
- pll->ext_clk_freq_hz /
- op_pll_fr->pre_pll_clk_div * mul);
- dev_dbg(dev, "more_mul_min: min_op_pll_op_clk_freq_hz check: %u\n",
- more_mul_min);
- /* Ensure we won't go below min_pll_multiplier. */
- more_mul_min = max(more_mul_min,
- DIV_ROUND_UP(op_lim_fr->min_pll_multiplier, mul));
- dev_dbg(dev, "more_mul_min: min_op_pll_multiplier check: %u\n",
- more_mul_min);
-
- if (more_mul_min > more_mul_max) {
- dev_dbg(dev,
- "unable to compute more_mul_min and more_mul_max\n");
- return -EINVAL;
- }
-
- more_mul_factor = lcm(div, op_pll_fr->pre_pll_clk_div) / div;
- dev_dbg(dev, "more_mul_factor: %u\n", more_mul_factor);
- more_mul_factor = lcm(more_mul_factor, op_lim_bk->min_sys_clk_div);
- dev_dbg(dev, "more_mul_factor: min_op_sys_clk_div: %d\n",
- more_mul_factor);
- i = roundup(more_mul_min, more_mul_factor);
- if (!is_one_or_even(i))
- i <<= 1;
-
- dev_dbg(dev, "final more_mul: %u\n", i);
- if (i > more_mul_max) {
- dev_dbg(dev, "final more_mul is bad, max %u\n", more_mul_max);
- return -EINVAL;
- }
-
- op_pll_fr->pll_multiplier = mul * i;
- op_pll_bk->sys_clk_div = div * i / op_pll_fr->pre_pll_clk_div;
- dev_dbg(dev, "op_sys_clk_div: %u\n", op_pll_bk->sys_clk_div);
-
- op_pll_fr->pll_ip_clk_freq_hz = pll->ext_clk_freq_hz
- / op_pll_fr->pre_pll_clk_div;
-
- op_pll_fr->pll_op_clk_freq_hz = op_pll_fr->pll_ip_clk_freq_hz
- * op_pll_fr->pll_multiplier;
-
- if (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL)
- op_pll_bk->pix_clk_div = pll->bits_per_pixel
- * pll->op_lanes * phy_const
- / PHY_CONST_DIV / pll->csi2.lanes / l;
- else
- op_pll_bk->pix_clk_div =
- pll->bits_per_pixel * phy_const / PHY_CONST_DIV / l;
-
- op_pll_bk->pix_clk_freq_hz =
- op_pll_bk->sys_clk_freq_hz / op_pll_bk->pix_clk_div;
-
- dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div);
-
- if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) {
- /* No OP clocks --- VT clocks are used instead. */
- goto out_skip_vt_calc;
- }
/*
* Some sensors perform analogue binning and some do this
@@ -310,7 +198,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
/* Find smallest and biggest allowed vt divisor. */
dev_dbg(dev, "min_vt_div: %u\n", min_vt_div);
min_vt_div = max(min_vt_div,
- DIV_ROUND_UP(op_pll_fr->pll_op_clk_freq_hz,
+ DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
lim->vt_bk.max_pix_clk_freq_hz));
dev_dbg(dev, "min_vt_div: max_vt_pix_clk_freq_hz: %u\n",
min_vt_div);
@@ -322,7 +210,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
max_vt_div = lim->vt_bk.max_sys_clk_div * lim->vt_bk.max_pix_clk_div;
dev_dbg(dev, "max_vt_div: %u\n", max_vt_div);
max_vt_div = min(max_vt_div,
- DIV_ROUND_UP(op_pll_fr->pll_op_clk_freq_hz,
+ DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
lim->vt_bk.min_pix_clk_freq_hz));
dev_dbg(dev, "max_vt_div: min_vt_pix_clk_freq_hz: %u\n",
max_vt_div);
@@ -338,7 +226,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
lim->vt_bk.max_pix_clk_div));
dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", min_sys_div);
min_sys_div = max(min_sys_div,
- op_pll_fr->pll_op_clk_freq_hz
+ pll_fr->pll_op_clk_freq_hz
/ lim->vt_bk.max_sys_clk_freq_hz);
dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", min_sys_div);
min_sys_div = clk_div_even_up(min_sys_div);
@@ -351,7 +239,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
lim->vt_bk.min_pix_clk_div));
dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", max_sys_div);
max_sys_div = min(max_sys_div,
- DIV_ROUND_UP(op_pll_fr->pll_op_clk_freq_hz,
+ DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
lim->vt_bk.min_pix_clk_freq_hz));
dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", max_sys_div);
@@ -396,11 +284,130 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
pll->vt_bk.pix_clk_div = best_pix_div;
pll->vt_bk.sys_clk_freq_hz =
- op_pll_fr->pll_op_clk_freq_hz / pll->vt_bk.sys_clk_div;
+ pll_fr->pll_op_clk_freq_hz / pll->vt_bk.sys_clk_div;
pll->vt_bk.pix_clk_freq_hz =
pll->vt_bk.sys_clk_freq_hz / pll->vt_bk.pix_clk_div;
+}
+
+/*
+ * Heuristically guess the PLL tree for a given common multiplier and
+ * divisor. Begin with the operational timing and continue to video
+ * timing once operational timing has been verified.
+ *
+ * @mul is the PLL multiplier and @div is the common divisor
+ * (pre_pll_clk_div and op_sys_clk_div combined). The final PLL
+ * multiplier will be a multiple of @mul.
+ *
+ * @return Zero on success, error code on error.
+ */
+static int
+__ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
+ const struct ccs_pll_branch_limits_fr *op_lim_fr,
+ const struct ccs_pll_branch_limits_bk *op_lim_bk,
+ struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr,
+ struct ccs_pll_branch_bk *op_pll_bk, uint32_t mul,
+ uint32_t div, uint32_t l, bool cphy, uint32_t phy_const)
+{
+ /*
+ * Higher multipliers (and divisors) are often required than
+ * necessitated by the external clock and the output clocks.
+ * There are limits for all values in the clock tree. These
+ * are the minimum and maximum multiplier for mul.
+ */
+ uint32_t more_mul_min, more_mul_max;
+ uint32_t more_mul_factor;
+ uint32_t i;
+
+ /*
+ * Get pre_pll_clk_div so that our pll_op_clk_freq_hz won't be
+ * too high.
+ */
+ dev_dbg(dev, "op_pre_pll_clk_div %u\n", op_pll_fr->pre_pll_clk_div);
+
+ /* Don't go above max pll multiplier. */
+ more_mul_max = op_lim_fr->max_pll_multiplier / mul;
+ dev_dbg(dev, "more_mul_max: max_op_pll_multiplier check: %u\n",
+ more_mul_max);
+ /* Don't go above max pll op frequency. */
+ more_mul_max =
+ min_t(uint32_t,
+ more_mul_max,
+ op_lim_fr->max_pll_op_clk_freq_hz
+ / (pll->ext_clk_freq_hz /
+ op_pll_fr->pre_pll_clk_div * mul));
+ dev_dbg(dev, "more_mul_max: max_pll_op_clk_freq_hz check: %u\n",
+ more_mul_max);
+ /* Don't go above the division capability of op sys clock divider. */
+ more_mul_max = min(more_mul_max,
+ op_lim_bk->max_sys_clk_div * op_pll_fr->pre_pll_clk_div
+ / div);
+ dev_dbg(dev, "more_mul_max: max_op_sys_clk_div check: %u\n",
+ more_mul_max);
+ /* Ensure we won't go above max_pll_multiplier. */
+ more_mul_max = min(more_mul_max, op_lim_fr->max_pll_multiplier / mul);
+ dev_dbg(dev, "more_mul_max: min_pll_multiplier check: %u\n",
+ more_mul_max);
+
+ /* Ensure we won't go below min_pll_op_clk_freq_hz. */
+ more_mul_min = DIV_ROUND_UP(op_lim_fr->min_pll_op_clk_freq_hz,
+ pll->ext_clk_freq_hz /
+ op_pll_fr->pre_pll_clk_div * mul);
+ dev_dbg(dev, "more_mul_min: min_op_pll_op_clk_freq_hz check: %u\n",
+ more_mul_min);
+ /* Ensure we won't go below min_pll_multiplier. */
+ more_mul_min = max(more_mul_min,
+ DIV_ROUND_UP(op_lim_fr->min_pll_multiplier, mul));
+ dev_dbg(dev, "more_mul_min: min_op_pll_multiplier check: %u\n",
+ more_mul_min);
+
+ if (more_mul_min > more_mul_max) {
+ dev_dbg(dev,
+ "unable to compute more_mul_min and more_mul_max\n");
+ return -EINVAL;
+ }
+
+ more_mul_factor = lcm(div, op_pll_fr->pre_pll_clk_div) / div;
+ dev_dbg(dev, "more_mul_factor: %u\n", more_mul_factor);
+ more_mul_factor = lcm(more_mul_factor, op_lim_bk->min_sys_clk_div);
+ dev_dbg(dev, "more_mul_factor: min_op_sys_clk_div: %d\n",
+ more_mul_factor);
+ i = roundup(more_mul_min, more_mul_factor);
+ if (!is_one_or_even(i))
+ i <<= 1;
+
+ dev_dbg(dev, "final more_mul: %u\n", i);
+ if (i > more_mul_max) {
+ dev_dbg(dev, "final more_mul is bad, max %u\n", more_mul_max);
+ return -EINVAL;
+ }
+
+ op_pll_fr->pll_multiplier = mul * i;
+ op_pll_bk->sys_clk_div = div * i / op_pll_fr->pre_pll_clk_div;
+ dev_dbg(dev, "op_sys_clk_div: %u\n", op_pll_bk->sys_clk_div);
+
+ op_pll_fr->pll_ip_clk_freq_hz = pll->ext_clk_freq_hz
+ / op_pll_fr->pre_pll_clk_div;
+
+ op_pll_fr->pll_op_clk_freq_hz = op_pll_fr->pll_ip_clk_freq_hz
+ * op_pll_fr->pll_multiplier;
+
+ if (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL)
+ op_pll_bk->pix_clk_div = pll->bits_per_pixel
+ * pll->op_lanes * phy_const
+ / PHY_CONST_DIV / pll->csi2.lanes / l;
+ else
+ op_pll_bk->pix_clk_div =
+ pll->bits_per_pixel * phy_const / PHY_CONST_DIV / l;
+
+ op_pll_bk->pix_clk_freq_hz =
+ op_pll_bk->sys_clk_freq_hz / op_pll_bk->pix_clk_div;
+
+ dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div);
+
+ if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS))
+ __ccs_pll_calculate_vt(dev, lim, op_lim_bk, pll, op_pll_fr,
+ op_pll_bk, cphy, phy_const);
-out_skip_vt_calc:
pll->pixel_rate_pixel_array =
pll->vt_bk.pix_clk_freq_hz * pll->vt_lanes;
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 080/106] ccs-pll: Check for derating and overrating, support non-derating sensors
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (68 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 079/106] ccs-pll: Split off VT subtree calculation Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 081/106] ccs-pll: Better separate OP and VT sub-tree calculation Sakari Ailus
` (26 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Some sensors support derating (VT domain speed faster than OP) or
overrating (VT domain speed slower than OP). While this was supported for
the driver, the hardware support for the feature was never verified. Do
that now, and for those devices without that support, VT and OP speeds
have to match.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 84 +++++++++++++++++++++-----------
drivers/media/i2c/ccs-pll.h | 2 +
drivers/media/i2c/ccs/ccs-core.c | 7 +++
3 files changed, 64 insertions(+), 29 deletions(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index 3d43e737155f..96eb71f16c81 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -142,6 +142,18 @@ static int check_all_bounds(struct device *dev,
lim->vt_bk.max_pix_clk_freq_hz,
"vt_pix_clk_freq_hz");
+ if (!(pll->flags & CCS_PLL_FLAG_FIFO_DERATING) &&
+ pll->pixel_rate_pixel_array > pll->pixel_rate_csi) {
+ dev_dbg(dev, "device does not support derating\n");
+ return -EINVAL;
+ }
+
+ if (!(pll->flags & CCS_PLL_FLAG_FIFO_OVERRATING) &&
+ pll->pixel_rate_pixel_array < pll->pixel_rate_csi) {
+ dev_dbg(dev, "device does not support overrating\n");
+ return -EINVAL;
+ }
+
return rval;
}
@@ -163,37 +175,51 @@ __ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
uint32_t min_sys_div, max_sys_div;
/*
- * Some sensors perform analogue binning and some do this
- * digitally. The ones doing this digitally can be roughly be
- * found out using this formula. The ones doing this digitally
- * should run at higher clock rate, so smaller divisor is used
- * on video timing side.
+ * Find out whether a sensor supports derating. If it does not, VT and
+ * OP domains are required to run at the same pixel rate.
*/
- if (lim->min_line_length_pck_bin > lim->min_line_length_pck
- / pll->binning_horizontal)
- vt_op_binning_div = pll->binning_horizontal;
- else
- vt_op_binning_div = 1;
- dev_dbg(dev, "vt_op_binning_div: %u\n", vt_op_binning_div);
+ if (!(pll->flags & CCS_PLL_FLAG_FIFO_DERATING)) {
+ min_vt_div =
+ op_pll_bk->sys_clk_div * op_pll_bk->pix_clk_div
+ * pll->vt_lanes * phy_const
+ / pll->op_lanes / PHY_CONST_DIV;
+ } else {
+ /*
+ * Some sensors perform analogue binning and some do this
+ * digitally. The ones doing this digitally can be roughly be
+ * found out using this formula. The ones doing this digitally
+ * should run at higher clock rate, so smaller divisor is used
+ * on video timing side.
+ */
+ if (lim->min_line_length_pck_bin > lim->min_line_length_pck
+ / pll->binning_horizontal)
+ vt_op_binning_div = pll->binning_horizontal;
+ else
+ vt_op_binning_div = 1;
+ dev_dbg(dev, "vt_op_binning_div: %u\n", vt_op_binning_div);
- /*
- * Profile 2 supports vt_pix_clk_div E [4, 10]
- *
- * Horizontal binning can be used as a base for difference in
- * divisors. One must make sure that horizontal blanking is
- * enough to accommodate the CSI-2 sync codes.
- *
- * Take scaling factor and number of VT lanes into account as well.
- *
- * Find absolute limits for the factor of vt divider.
- */
- dev_dbg(dev, "scale_m: %u\n", pll->scale_m);
- min_vt_div = DIV_ROUND_UP(pll->bits_per_pixel * op_pll_bk->sys_clk_div
- * pll->scale_n * pll->vt_lanes * phy_const,
- (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
- pll->csi2.lanes : 1)
- * vt_op_binning_div * pll->scale_m
- * PHY_CONST_DIV);
+ /*
+ * Profile 2 supports vt_pix_clk_div E [4, 10]
+ *
+ * Horizontal binning can be used as a base for difference in
+ * divisors. One must make sure that horizontal blanking is
+ * enough to accommodate the CSI-2 sync codes.
+ *
+ * Take scaling factor and number of VT lanes into account as well.
+ *
+ * Find absolute limits for the factor of vt divider.
+ */
+ dev_dbg(dev, "scale_m: %u\n", pll->scale_m);
+ min_vt_div =
+ DIV_ROUND_UP(pll->bits_per_pixel
+ * op_pll_bk->sys_clk_div * pll->scale_n
+ * pll->vt_lanes * phy_const,
+ (pll->flags &
+ CCS_PLL_FLAG_LANE_SPEED_MODEL ?
+ pll->csi2.lanes : 1)
+ * vt_op_binning_div * pll->scale_m
+ * PHY_CONST_DIV);
+ }
/* Find smallest and biggest allowed vt divisor. */
dev_dbg(dev, "min_vt_div: %u\n", min_vt_div);
diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h
index 0c25c5f5d4e4..9ba738ea7006 100644
--- a/drivers/media/i2c/ccs-pll.h
+++ b/drivers/media/i2c/ccs-pll.h
@@ -27,6 +27,8 @@
#define CCS_PLL_FLAG_LINK_DECOUPLED BIT(3)
#define CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER BIT(4)
#define CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV BIT(5)
+#define CCS_PLL_FLAG_FIFO_DERATING BIT(6)
+#define CCS_PLL_FLAG_FIFO_OVERRATING BIT(7)
/**
* struct ccs_pll_branch_fr - CCS PLL configuration (front)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index ab6abcf4c1dd..a169656c4560 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -3216,6 +3216,13 @@ static int ccs_probe(struct i2c_client *client)
if (CCS_LIM(sensor, CLOCK_TREE_PLL_CAPABILITY) &
CCS_CLOCK_TREE_PLL_CAPABILITY_FLEXIBLE_OP_PIX_CLK_DIV)
sensor->pll.flags |= CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV;
+ if (CCS_LIM(sensor, FIFO_SUPPORT_CAPABILITY) &
+ CCS_FIFO_SUPPORT_CAPABILITY_DERATING)
+ sensor->pll.flags |= CCS_PLL_FLAG_FIFO_DERATING;
+ if (CCS_LIM(sensor, FIFO_SUPPORT_CAPABILITY) &
+ CCS_FIFO_SUPPORT_CAPABILITY_DERATING_OVERRATING)
+ sensor->pll.flags |= CCS_PLL_FLAG_FIFO_DERATING |
+ CCS_PLL_FLAG_FIFO_OVERRATING;
sensor->pll.op_bits_per_lane = CCS_LIM(sensor, OP_BITS_PER_LANE);
sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk;
sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN);
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 081/106] ccs-pll: Better separate OP and VT sub-tree calculation
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (69 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 080/106] ccs-pll: Check for derating and overrating, support non-derating sensors Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 082/106] ccs-pll: Print relevant information on PLL tree Sakari Ailus
` (25 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Better separate OP PLL branch calculation from VT branch calculation.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 54 +++++++++++++++++++++----------------
1 file changed, 31 insertions(+), 23 deletions(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index 96eb71f16c81..e879c03a3d3b 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -162,11 +162,11 @@ static int check_all_bounds(struct device *dev,
#define PHY_CONST_DIV 16
static void
-__ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
- const struct ccs_pll_branch_limits_bk *op_lim_bk,
- struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr,
- struct ccs_pll_branch_bk *op_pll_bk, bool cphy,
- uint32_t phy_const)
+ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
+ const struct ccs_pll_branch_limits_bk *op_lim_bk,
+ struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr,
+ struct ccs_pll_branch_bk *op_pll_bk, bool cphy,
+ uint32_t phy_const)
{
uint32_t sys_div;
uint32_t best_pix_div = INT_MAX >> 1;
@@ -174,6 +174,9 @@ __ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
uint32_t min_vt_div, max_vt_div, vt_div;
uint32_t min_sys_div, max_sys_div;
+ if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)
+ goto out_calc_pixel_rate;
+
/*
* Find out whether a sensor supports derating. If it does not, VT and
* OP domains are required to run at the same pixel rate.
@@ -313,6 +316,10 @@ __ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
pll_fr->pll_op_clk_freq_hz / pll->vt_bk.sys_clk_div;
pll->vt_bk.pix_clk_freq_hz =
pll->vt_bk.sys_clk_freq_hz / pll->vt_bk.pix_clk_div;
+
+out_calc_pixel_rate:
+ pll->pixel_rate_pixel_array =
+ pll->vt_bk.pix_clk_freq_hz * pll->vt_lanes;
}
/*
@@ -327,12 +334,12 @@ __ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
* @return Zero on success, error code on error.
*/
static int
-__ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
- const struct ccs_pll_branch_limits_fr *op_lim_fr,
- const struct ccs_pll_branch_limits_bk *op_lim_bk,
- struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr,
- struct ccs_pll_branch_bk *op_pll_bk, uint32_t mul,
- uint32_t div, uint32_t l, bool cphy, uint32_t phy_const)
+ccs_pll_calculate_op(struct device *dev, const struct ccs_pll_limits *lim,
+ const struct ccs_pll_branch_limits_fr *op_lim_fr,
+ const struct ccs_pll_branch_limits_bk *op_lim_bk,
+ struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr,
+ struct ccs_pll_branch_bk *op_pll_bk, uint32_t mul,
+ uint32_t div, uint32_t l, bool cphy, uint32_t phy_const)
{
/*
* Higher multipliers (and divisors) are often required than
@@ -430,15 +437,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div);
- if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS))
- __ccs_pll_calculate_vt(dev, lim, op_lim_bk, pll, op_pll_fr,
- op_pll_bk, cphy, phy_const);
-
- pll->pixel_rate_pixel_array =
- pll->vt_bk.pix_clk_freq_hz * pll->vt_lanes;
-
- return check_all_bounds(dev, lim, op_lim_fr, op_lim_bk, pll, op_pll_fr,
- op_pll_bk);
+ return 0;
}
int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
@@ -558,13 +557,22 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
op_pll_fr->pre_pll_clk_div +=
(pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 :
2 - (op_pll_fr->pre_pll_clk_div & 1)) {
- rval = __ccs_pll_calculate(dev, lim, op_lim_fr, op_lim_bk, pll,
- op_pll_fr, op_pll_bk, mul, div, l,
- cphy, phy_const);
+ rval = ccs_pll_calculate_op(dev, lim, op_lim_fr, op_lim_bk, pll,
+ op_pll_fr, op_pll_bk, mul, div, l,
+ cphy, phy_const);
+ if (rval)
+ continue;
+
+ ccs_pll_calculate_vt(dev, lim, op_lim_bk, pll, op_pll_fr,
+ op_pll_bk, cphy, phy_const);
+
+ rval = check_all_bounds(dev, lim, op_lim_fr, op_lim_bk, pll,
+ op_pll_fr, op_pll_bk);
if (rval)
continue;
print_pll(dev, pll);
+
return 0;
}
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 082/106] ccs-pll: Print relevant information on PLL tree
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (70 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 081/106] ccs-pll: Better separate OP and VT sub-tree calculation Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 083/106] ccs-pll: Rework bounds checks Sakari Ailus
` (24 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Print information on PLL tree configuration based on the flags. This also
adds support for printing dual PLL trees, and better separates between OP
and VT PLL trees.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 85 ++++++++++++++++++++++++++++---------
1 file changed, 66 insertions(+), 19 deletions(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index e879c03a3d3b..43735f6d0bb2 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -56,28 +56,75 @@ static int bounds_check(struct device *dev, uint32_t val,
return -EINVAL;
}
-static void print_pll(struct device *dev, struct ccs_pll *pll)
+#define PLL_OP 1
+#define PLL_VT 2
+
+static const char *pll_string(unsigned int which)
{
- dev_dbg(dev, "pre_pll_clk_div\t%u\n", pll->vt_fr.pre_pll_clk_div);
- dev_dbg(dev, "pll_multiplier \t%u\n", pll->vt_fr.pll_multiplier);
- if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)) {
- dev_dbg(dev, "op_sys_clk_div \t%u\n", pll->op_bk.sys_clk_div);
- dev_dbg(dev, "op_pix_clk_div \t%u\n", pll->op_bk.pix_clk_div);
+ switch (which) {
+ case PLL_OP:
+ return "op";
+ case PLL_VT:
+ return "vt";
}
- dev_dbg(dev, "vt_sys_clk_div \t%u\n", pll->vt_bk.sys_clk_div);
- dev_dbg(dev, "vt_pix_clk_div \t%u\n", pll->vt_bk.pix_clk_div);
-
- dev_dbg(dev, "ext_clk_freq_hz \t%u\n", pll->ext_clk_freq_hz);
- dev_dbg(dev, "pll_ip_clk_freq_hz \t%u\n", pll->vt_fr.pll_ip_clk_freq_hz);
- dev_dbg(dev, "pll_op_clk_freq_hz \t%u\n", pll->vt_fr.pll_op_clk_freq_hz);
- if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)) {
- dev_dbg(dev, "op_sys_clk_freq_hz \t%u\n",
- pll->op_bk.sys_clk_freq_hz);
- dev_dbg(dev, "op_pix_clk_freq_hz \t%u\n",
- pll->op_bk.pix_clk_freq_hz);
+
+ return NULL;
+}
+
+#define PLL_FL(f) CCS_PLL_FLAG_##f
+
+static void print_pll(struct device *dev, struct ccs_pll *pll)
+{
+ const struct {
+ struct ccs_pll_branch_fr *fr;
+ struct ccs_pll_branch_bk *bk;
+ unsigned int which;
+ } branches[] = {
+ { &pll->vt_fr, &pll->vt_bk, PLL_VT },
+ { NULL, &pll->op_bk, PLL_OP }
+ }, *br;
+ unsigned int i;
+
+ dev_dbg(dev, "ext_clk_freq_hz\t\t%u\n", pll->ext_clk_freq_hz);
+
+ for (i = 0, br = branches; i < ARRAY_SIZE(branches); i++, br++) {
+ const char *s = pll_string(br->which);
+
+ if (br->which == PLL_VT) {
+ dev_dbg(dev, "%s_pre_pll_clk_div\t\t%u\n", s,
+ br->fr->pre_pll_clk_div);
+ dev_dbg(dev, "%s_pll_multiplier\t\t%u\n", s,
+ br->fr->pll_multiplier);
+
+ dev_dbg(dev, "%s_pll_ip_clk_freq_hz\t%u\n", s,
+ br->fr->pll_ip_clk_freq_hz);
+ dev_dbg(dev, "%s_pll_op_clk_freq_hz\t%u\n", s,
+ br->fr->pll_op_clk_freq_hz);
+ }
+
+ if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) ||
+ br->which == PLL_VT) {
+ dev_dbg(dev, "%s_sys_clk_div\t\t%u\n", s,
+ br->bk->sys_clk_div);
+ dev_dbg(dev, "%s_pix_clk_div\t\t%u\n", s,
+ br->bk->pix_clk_div);
+
+ dev_dbg(dev, "%s_sys_clk_freq_hz\t%u\n", s,
+ br->bk->sys_clk_freq_hz);
+ dev_dbg(dev, "%s_pix_clk_freq_hz\t%u\n", s,
+ br->bk->pix_clk_freq_hz);
+ }
}
- dev_dbg(dev, "vt_sys_clk_freq_hz \t%u\n", pll->vt_bk.sys_clk_freq_hz);
- dev_dbg(dev, "vt_pix_clk_freq_hz \t%u\n", pll->vt_bk.pix_clk_freq_hz);
+
+ dev_dbg(dev, "flags%s%s%s%s%s%s\n",
+ pll->flags & PLL_FL(LANE_SPEED_MODEL) ? " lane-speed" : "",
+ pll->flags & PLL_FL(LINK_DECOUPLED) ? " link-decoupled" : "",
+ pll->flags & PLL_FL(EXT_IP_PLL_DIVIDER) ?
+ " ext-ip-pll-divider" : "",
+ pll->flags & PLL_FL(FLEXIBLE_OP_PIX_CLK_DIV) ?
+ " flexible-op-pix-div" : "",
+ pll->flags & PLL_FL(FIFO_DERATING) ? " fifo-derating" : "",
+ pll->flags & PLL_FL(FIFO_OVERRATING) ? " fifo-overrating" : "");
}
static int check_all_bounds(struct device *dev,
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 083/106] ccs-pll: Rework bounds checks
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (71 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 082/106] ccs-pll: Print relevant information on PLL tree Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 084/106] ccs-pll: Make VT divisors 16-bit Sakari Ailus
` (23 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Refactor bounds checks so that the caller can decide what to check. This
allows doing the checks early, when the values are available.
This also adds front OP PLL configuration and limits.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 148 ++++++++++++++++++++++--------------
drivers/media/i2c/ccs-pll.h | 2 +
2 files changed, 93 insertions(+), 57 deletions(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index 43735f6d0bb2..a6443589b948 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -46,12 +46,14 @@ static inline uint32_t one_or_more(uint32_t a)
}
static int bounds_check(struct device *dev, uint32_t val,
- uint32_t min, uint32_t max, char *str)
+ uint32_t min, uint32_t max, const char *prefix,
+ char *str)
{
if (val >= min && val <= max)
return 0;
- dev_dbg(dev, "%s out of bounds: %d (%d--%d)\n", str, val, min, max);
+ dev_dbg(dev, "%s_%s out of bounds: %d (%d--%d)\n", prefix,
+ str, val, min, max);
return -EINVAL;
}
@@ -81,7 +83,7 @@ static void print_pll(struct device *dev, struct ccs_pll *pll)
unsigned int which;
} branches[] = {
{ &pll->vt_fr, &pll->vt_bk, PLL_VT },
- { NULL, &pll->op_bk, PLL_OP }
+ { &pll->op_fr, &pll->op_bk, PLL_OP }
}, *br;
unsigned int i;
@@ -127,68 +129,90 @@ static void print_pll(struct device *dev, struct ccs_pll *pll)
pll->flags & PLL_FL(FIFO_OVERRATING) ? " fifo-overrating" : "");
}
-static int check_all_bounds(struct device *dev,
- const struct ccs_pll_limits *lim,
- const struct ccs_pll_branch_limits_fr *op_lim_fr,
- const struct ccs_pll_branch_limits_bk *op_lim_bk,
- struct ccs_pll *pll,
- struct ccs_pll_branch_fr *op_pll_fr,
- struct ccs_pll_branch_bk *op_pll_bk)
+static int check_fr_bounds(struct device *dev,
+ const struct ccs_pll_limits *lim,
+ struct ccs_pll *pll, unsigned int which)
{
+ const struct ccs_pll_branch_limits_fr *lim_fr;
+ struct ccs_pll_branch_fr *pll_fr;
+ const char *s = pll_string(which);
int rval;
- rval = bounds_check(dev, op_pll_fr->pll_ip_clk_freq_hz,
- op_lim_fr->min_pll_ip_clk_freq_hz,
- op_lim_fr->max_pll_ip_clk_freq_hz,
- "pll_ip_clk_freq_hz");
- if (!rval)
- rval = bounds_check(
- dev, op_pll_fr->pll_multiplier,
- op_lim_fr->min_pll_multiplier,
- op_lim_fr->max_pll_multiplier, "pll_multiplier");
- if (!rval)
- rval = bounds_check(
- dev, op_pll_fr->pll_op_clk_freq_hz,
- op_lim_fr->min_pll_op_clk_freq_hz,
- op_lim_fr->max_pll_op_clk_freq_hz, "pll_op_clk_freq_hz");
+ if (which == PLL_OP) {
+ lim_fr = &lim->op_fr;
+ pll_fr = &pll->op_fr;
+ } else {
+ lim_fr = &lim->vt_fr;
+ pll_fr = &pll->vt_fr;
+ }
+
+ rval = bounds_check(dev, pll_fr->pre_pll_clk_div,
+ lim_fr->min_pre_pll_clk_div,
+ lim_fr->max_pre_pll_clk_div, s, "pre_pll_clk_div");
+
if (!rval)
- rval = bounds_check(
- dev, op_pll_bk->sys_clk_div,
- op_lim_bk->min_sys_clk_div, op_lim_bk->max_sys_clk_div,
- "op_sys_clk_div");
+ rval = bounds_check(dev, pll_fr->pll_ip_clk_freq_hz,
+ lim_fr->min_pll_ip_clk_freq_hz,
+ lim_fr->max_pll_ip_clk_freq_hz,
+ s, "pll_ip_clk_freq_hz");
if (!rval)
- rval = bounds_check(
- dev, op_pll_bk->sys_clk_freq_hz,
- op_lim_bk->min_sys_clk_freq_hz,
- op_lim_bk->max_sys_clk_freq_hz,
- "op_sys_clk_freq_hz");
+ rval = bounds_check(dev, pll_fr->pll_multiplier,
+ lim_fr->min_pll_multiplier,
+ lim_fr->max_pll_multiplier,
+ s, "pll_multiplier");
if (!rval)
- rval = bounds_check(
- dev, op_pll_bk->pix_clk_freq_hz,
- op_lim_bk->min_pix_clk_freq_hz,
- op_lim_bk->max_pix_clk_freq_hz,
- "op_pix_clk_freq_hz");
+ rval = bounds_check(dev, pll_fr->pll_op_clk_freq_hz,
+ lim_fr->min_pll_op_clk_freq_hz,
+ lim_fr->max_pll_op_clk_freq_hz,
+ s, "pll_op_clk_freq_hz");
- /*
- * If there are no OP clocks, the VT clocks are contained in
- * the OP clock struct.
- */
- if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)
- return rval;
+ return rval;
+}
+
+static int check_bk_bounds(struct device *dev,
+ const struct ccs_pll_limits *lim,
+ struct ccs_pll *pll, unsigned int which)
+{
+ const struct ccs_pll_branch_limits_bk *lim_bk;
+ struct ccs_pll_branch_bk *pll_bk;
+ const char *s = pll_string(which);
+ int rval;
+
+ if (which == PLL_OP) {
+ if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)
+ return 0;
+ lim_bk = &lim->op_bk;
+ pll_bk = &pll->op_bk;
+ } else {
+ lim_bk = &lim->vt_bk;
+ pll_bk = &pll->vt_bk;
+ }
+
+ rval = bounds_check(dev, pll_bk->sys_clk_div,
+ lim_bk->min_sys_clk_div,
+ lim_bk->max_sys_clk_div, s, "op_sys_clk_div");
+ if (!rval)
+ rval = bounds_check(dev, pll_bk->sys_clk_freq_hz,
+ lim_bk->min_sys_clk_freq_hz,
+ lim_bk->max_sys_clk_freq_hz,
+ s, "sys_clk_freq_hz");
if (!rval)
- rval = bounds_check(
- dev, pll->vt_bk.sys_clk_freq_hz,
- lim->vt_bk.min_sys_clk_freq_hz,
- lim->vt_bk.max_sys_clk_freq_hz,
- "vt_sys_clk_freq_hz");
+ rval = bounds_check(dev, pll_bk->sys_clk_div,
+ lim_bk->min_sys_clk_div,
+ lim_bk->max_sys_clk_div,
+ s, "sys_clk_div");
if (!rval)
- rval = bounds_check(
- dev, pll->vt_bk.pix_clk_freq_hz,
- lim->vt_bk.min_pix_clk_freq_hz,
- lim->vt_bk.max_pix_clk_freq_hz,
- "vt_pix_clk_freq_hz");
+ rval = bounds_check(dev, pll_bk->pix_clk_freq_hz,
+ lim_bk->min_pix_clk_freq_hz,
+ lim_bk->max_pix_clk_freq_hz,
+ s, "pix_clk_freq_hz");
+
+ return rval;
+}
+static int check_ext_bounds(struct device *dev, struct ccs_pll *pll)
+{
if (!(pll->flags & CCS_PLL_FLAG_FIFO_DERATING) &&
pll->pixel_rate_pixel_array > pll->pixel_rate_csi) {
dev_dbg(dev, "device does not support derating\n");
@@ -201,7 +225,7 @@ static int check_all_bounds(struct device *dev,
return -EINVAL;
}
- return rval;
+ return 0;
}
#define CPHY_CONST 7
@@ -610,11 +634,21 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
if (rval)
continue;
+ rval = check_fr_bounds(dev, lim, pll, PLL_VT);
+ if (rval)
+ continue;
+
+ rval = check_bk_bounds(dev, lim, pll, PLL_OP);
+ if (rval)
+ continue;
+
ccs_pll_calculate_vt(dev, lim, op_lim_bk, pll, op_pll_fr,
op_pll_bk, cphy, phy_const);
- rval = check_all_bounds(dev, lim, op_lim_fr, op_lim_bk, pll,
- op_pll_fr, op_pll_bk);
+ rval = check_bk_bounds(dev, lim, pll, PLL_VT);
+ if (rval)
+ continue;
+ rval = check_ext_bounds(dev, pll);
if (rval)
continue;
diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h
index 9ba738ea7006..4fa3d4e459a0 100644
--- a/drivers/media/i2c/ccs-pll.h
+++ b/drivers/media/i2c/ccs-pll.h
@@ -111,6 +111,7 @@ struct ccs_pll {
/* output values */
struct ccs_pll_branch_fr vt_fr;
struct ccs_pll_branch_bk vt_bk;
+ struct ccs_pll_branch_fr op_fr;
struct ccs_pll_branch_bk op_bk;
uint32_t pixel_rate_csi;
@@ -181,6 +182,7 @@ struct ccs_pll_limits {
struct ccs_pll_branch_limits_fr vt_fr;
struct ccs_pll_branch_limits_bk vt_bk;
+ struct ccs_pll_branch_limits_fr op_fr;
struct ccs_pll_branch_limits_bk op_bk;
/* Other relevant limits */
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 084/106] ccs-pll: Make VT divisors 16-bit
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (72 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 083/106] ccs-pll: Rework bounds checks Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 085/106] ccs-pll: Fix VT post-PLL divisor calculation Sakari Ailus
` (22 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Make VT divisors 16-bit unsigned numbers. They don't need 32 bits after
all.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 51 ++++++++++++++++++-------------------
1 file changed, 25 insertions(+), 26 deletions(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index a6443589b948..7512f0313010 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -239,11 +239,11 @@ ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
struct ccs_pll_branch_bk *op_pll_bk, bool cphy,
uint32_t phy_const)
{
- uint32_t sys_div;
- uint32_t best_pix_div = INT_MAX >> 1;
- uint32_t vt_op_binning_div;
- uint32_t min_vt_div, max_vt_div, vt_div;
- uint32_t min_sys_div, max_sys_div;
+ uint16_t sys_div;
+ uint16_t best_pix_div = SHRT_MAX >> 1;
+ uint16_t vt_op_binning_div;
+ uint16_t min_vt_div, max_vt_div, vt_div;
+ uint16_t min_sys_div, max_sys_div;
if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)
goto out_calc_pixel_rate;
@@ -297,20 +297,19 @@ ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
/* Find smallest and biggest allowed vt divisor. */
dev_dbg(dev, "min_vt_div: %u\n", min_vt_div);
- min_vt_div = max(min_vt_div,
- DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
- lim->vt_bk.max_pix_clk_freq_hz));
+ min_vt_div = max_t(uint16_t, min_vt_div,
+ DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
+ lim->vt_bk.max_pix_clk_freq_hz));
dev_dbg(dev, "min_vt_div: max_vt_pix_clk_freq_hz: %u\n",
min_vt_div);
- min_vt_div = max_t(uint32_t, min_vt_div,
- lim->vt_bk.min_pix_clk_div
- * lim->vt_bk.min_sys_clk_div);
+ min_vt_div = max_t(uint16_t, min_vt_div, lim->vt_bk.min_pix_clk_div
+ * lim->vt_bk.min_sys_clk_div);
dev_dbg(dev, "min_vt_div: min_vt_clk_div: %u\n", min_vt_div);
max_vt_div = lim->vt_bk.max_sys_clk_div * lim->vt_bk.max_pix_clk_div;
dev_dbg(dev, "max_vt_div: %u\n", max_vt_div);
- max_vt_div = min(max_vt_div,
- DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
+ max_vt_div = min_t(uint16_t, max_vt_div,
+ DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
lim->vt_bk.min_pix_clk_freq_hz));
dev_dbg(dev, "max_vt_div: min_vt_pix_clk_freq_hz: %u\n",
max_vt_div);
@@ -321,26 +320,26 @@ ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
*/
min_sys_div = lim->vt_bk.min_sys_clk_div;
dev_dbg(dev, "min_sys_div: %u\n", min_sys_div);
- min_sys_div = max(min_sys_div,
- DIV_ROUND_UP(min_vt_div,
- lim->vt_bk.max_pix_clk_div));
+ min_sys_div = max_t(uint16_t, min_sys_div,
+ DIV_ROUND_UP(min_vt_div,
+ lim->vt_bk.max_pix_clk_div));
dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", min_sys_div);
- min_sys_div = max(min_sys_div,
- pll_fr->pll_op_clk_freq_hz
- / lim->vt_bk.max_sys_clk_freq_hz);
+ min_sys_div = max_t(uint16_t, min_sys_div,
+ pll_fr->pll_op_clk_freq_hz
+ / lim->vt_bk.max_sys_clk_freq_hz);
dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", min_sys_div);
min_sys_div = clk_div_even_up(min_sys_div);
dev_dbg(dev, "min_sys_div: one or even: %u\n", min_sys_div);
max_sys_div = lim->vt_bk.max_sys_clk_div;
dev_dbg(dev, "max_sys_div: %u\n", max_sys_div);
- max_sys_div = min(max_sys_div,
- DIV_ROUND_UP(max_vt_div,
- lim->vt_bk.min_pix_clk_div));
+ max_sys_div = min_t(uint16_t, max_sys_div,
+ DIV_ROUND_UP(max_vt_div,
+ lim->vt_bk.min_pix_clk_div));
dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", max_sys_div);
- max_sys_div = min(max_sys_div,
- DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
- lim->vt_bk.min_pix_clk_freq_hz));
+ max_sys_div = min_t(uint16_t, max_sys_div,
+ DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
+ lim->vt_bk.min_pix_clk_freq_hz));
dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", max_sys_div);
/*
@@ -376,7 +375,7 @@ ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
if (vt_div == rounded_div)
break;
}
- if (best_pix_div < INT_MAX >> 1)
+ if (best_pix_div < SHRT_MAX >> 1)
break;
}
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 085/106] ccs-pll: Fix VT post-PLL divisor calculation
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (73 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 084/106] ccs-pll: Make VT divisors 16-bit Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 086/106] ccs-pll: Separate VT divisor limit calculation from the rest Sakari Ailus
` (21 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
The PLL calculator only searched even total divisor values apart from one,
but this is wrong: the total divisor is odd in cases where system divisor
is one. Fix this by including odd total PLL values where system divisor is
one to the search.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index 7512f0313010..4321989b9013 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -347,14 +347,16 @@ ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
* into a value which is not smaller than div, the desired
* divisor.
*/
- for (vt_div = min_vt_div; vt_div <= max_vt_div;
- vt_div += 2 - (vt_div & 1)) {
- for (sys_div = min_sys_div;
- sys_div <= max_sys_div;
+ for (vt_div = min_vt_div; vt_div <= max_vt_div; vt_div++) {
+ uint16_t __max_sys_div = vt_div & 1 ? 1 : max_sys_div;
+
+ for (sys_div = min_sys_div; sys_div <= __max_sys_div;
sys_div += 2 - (sys_div & 1)) {
- uint16_t pix_div = DIV_ROUND_UP(vt_div, sys_div);
+ uint16_t pix_div;
uint16_t rounded_div;
+ pix_div = DIV_ROUND_UP(vt_div, sys_div);
+
if (pix_div < lim->vt_bk.min_pix_clk_div
|| pix_div > lim->vt_bk.max_pix_clk_div) {
dev_dbg(dev,
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 086/106] ccs-pll: Separate VT divisor limit calculation from the rest
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (74 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 085/106] ccs-pll: Fix VT post-PLL divisor calculation Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 087/106] ccs-pll: Add trivial dual PLL support Sakari Ailus
` (20 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Separate VT divisor limit calculation from the rest of the VT PLL branch
calculation. This way it can be used for dual PLL support as well.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 64 +++++++++++++++++++++----------------
1 file changed, 37 insertions(+), 27 deletions(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index 4321989b9013..8b300e786451 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -228,6 +228,41 @@ static int check_ext_bounds(struct device *dev, struct ccs_pll *pll)
return 0;
}
+static void
+ccs_pll_find_vt_sys_div(struct device *dev, const struct ccs_pll_limits *lim,
+ struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr,
+ uint16_t min_vt_div, uint16_t max_vt_div,
+ uint16_t *min_sys_div, uint16_t *max_sys_div)
+{
+ /*
+ * Find limits for sys_clk_div. Not all values are possible with all
+ * values of pix_clk_div.
+ */
+ *min_sys_div = lim->vt_bk.min_sys_clk_div;
+ dev_dbg(dev, "min_sys_div: %u\n", *min_sys_div);
+ *min_sys_div = max_t(uint16_t, *min_sys_div,
+ DIV_ROUND_UP(min_vt_div,
+ lim->vt_bk.max_pix_clk_div));
+ dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", *min_sys_div);
+ *min_sys_div = max_t(uint16_t, *min_sys_div,
+ pll_fr->pll_op_clk_freq_hz
+ / lim->vt_bk.max_sys_clk_freq_hz);
+ dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", *min_sys_div);
+ *min_sys_div = clk_div_even_up(*min_sys_div);
+ dev_dbg(dev, "min_sys_div: one or even: %u\n", *min_sys_div);
+
+ *max_sys_div = lim->vt_bk.max_sys_clk_div;
+ dev_dbg(dev, "max_sys_div: %u\n", *max_sys_div);
+ *max_sys_div = min_t(uint16_t, *max_sys_div,
+ DIV_ROUND_UP(max_vt_div,
+ lim->vt_bk.min_pix_clk_div));
+ dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", *max_sys_div);
+ *max_sys_div = min_t(uint16_t, *max_sys_div,
+ DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
+ lim->vt_bk.min_pix_clk_freq_hz));
+ dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", *max_sys_div);
+}
+
#define CPHY_CONST 7
#define DPHY_CONST 16
#define PHY_CONST_DIV 16
@@ -314,33 +349,8 @@ ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
dev_dbg(dev, "max_vt_div: min_vt_pix_clk_freq_hz: %u\n",
max_vt_div);
- /*
- * Find limitsits for sys_clk_div. Not all values are possible
- * with all values of pix_clk_div.
- */
- min_sys_div = lim->vt_bk.min_sys_clk_div;
- dev_dbg(dev, "min_sys_div: %u\n", min_sys_div);
- min_sys_div = max_t(uint16_t, min_sys_div,
- DIV_ROUND_UP(min_vt_div,
- lim->vt_bk.max_pix_clk_div));
- dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", min_sys_div);
- min_sys_div = max_t(uint16_t, min_sys_div,
- pll_fr->pll_op_clk_freq_hz
- / lim->vt_bk.max_sys_clk_freq_hz);
- dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", min_sys_div);
- min_sys_div = clk_div_even_up(min_sys_div);
- dev_dbg(dev, "min_sys_div: one or even: %u\n", min_sys_div);
-
- max_sys_div = lim->vt_bk.max_sys_clk_div;
- dev_dbg(dev, "max_sys_div: %u\n", max_sys_div);
- max_sys_div = min_t(uint16_t, max_sys_div,
- DIV_ROUND_UP(max_vt_div,
- lim->vt_bk.min_pix_clk_div));
- dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", max_sys_div);
- max_sys_div = min_t(uint16_t, max_sys_div,
- DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
- lim->vt_bk.min_pix_clk_freq_hz));
- dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", max_sys_div);
+ ccs_pll_find_vt_sys_div(dev, lim, pll, pll_fr, min_vt_div,
+ max_vt_div, &min_sys_div, &max_sys_div);
/*
* Find pix_div such that a legal pix_div * sys_div results
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 087/106] ccs-pll: Add trivial dual PLL support
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (75 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 086/106] ccs-pll: Separate VT divisor limit calculation from the rest Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 088/106] ccs: Dual " Sakari Ailus
` (19 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Add support for sensors that have separate VT and OP domain PLLs.
This support is trivial in the sense that it aims for the same VT pixel
rate than that on the CSI-2 bus. The vast majority of sensors is better
supported by higher frequencies in VT domain in binned and possibly scaled
configurations.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 217 ++++++++++++++++++++++++++++++++----
drivers/media/i2c/ccs-pll.h | 1 +
2 files changed, 196 insertions(+), 22 deletions(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index 8b300e786451..91b578a05a98 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -92,7 +92,8 @@ static void print_pll(struct device *dev, struct ccs_pll *pll)
for (i = 0, br = branches; i < ARRAY_SIZE(branches); i++, br++) {
const char *s = pll_string(br->which);
- if (br->which == PLL_VT) {
+ if (pll->flags & CCS_PLL_FLAG_DUAL_PLL ||
+ br->which == PLL_VT) {
dev_dbg(dev, "%s_pre_pll_clk_div\t\t%u\n", s,
br->fr->pre_pll_clk_div);
dev_dbg(dev, "%s_pll_multiplier\t\t%u\n", s,
@@ -118,7 +119,7 @@ static void print_pll(struct device *dev, struct ccs_pll *pll)
}
}
- dev_dbg(dev, "flags%s%s%s%s%s%s\n",
+ dev_dbg(dev, "flags%s%s%s%s%s%s%s\n",
pll->flags & PLL_FL(LANE_SPEED_MODEL) ? " lane-speed" : "",
pll->flags & PLL_FL(LINK_DECOUPLED) ? " link-decoupled" : "",
pll->flags & PLL_FL(EXT_IP_PLL_DIVIDER) ?
@@ -126,7 +127,8 @@ static void print_pll(struct device *dev, struct ccs_pll *pll)
pll->flags & PLL_FL(FLEXIBLE_OP_PIX_CLK_DIV) ?
" flexible-op-pix-div" : "",
pll->flags & PLL_FL(FIFO_DERATING) ? " fifo-derating" : "",
- pll->flags & PLL_FL(FIFO_OVERRATING) ? " fifo-overrating" : "");
+ pll->flags & PLL_FL(FIFO_OVERRATING) ? " fifo-overrating" : "",
+ pll->flags & PLL_FL(DUAL_PLL) ? " dual-pll" : "");
}
static int check_fr_bounds(struct device *dev,
@@ -267,6 +269,152 @@ ccs_pll_find_vt_sys_div(struct device *dev, const struct ccs_pll_limits *lim,
#define DPHY_CONST 16
#define PHY_CONST_DIV 16
+static inline int
+__ccs_pll_calculate_vt_tree(struct device *dev,
+ const struct ccs_pll_limits *lim,
+ struct ccs_pll *pll, uint32_t mul, uint32_t div)
+{
+ const struct ccs_pll_branch_limits_fr *lim_fr = &lim->vt_fr;
+ const struct ccs_pll_branch_limits_bk *lim_bk = &lim->vt_bk;
+ struct ccs_pll_branch_fr *pll_fr = &pll->vt_fr;
+ struct ccs_pll_branch_bk *pll_bk = &pll->vt_bk;
+ uint32_t more_mul;
+ uint16_t best_pix_div = SHRT_MAX >> 1, best_div;
+ uint16_t vt_div, min_sys_div, max_sys_div, sys_div;
+
+ pll_fr->pll_ip_clk_freq_hz =
+ pll->ext_clk_freq_hz / pll_fr->pre_pll_clk_div;
+
+ dev_dbg(dev, "vt_pll_ip_clk_freq_hz %u\n", pll_fr->pll_ip_clk_freq_hz);
+
+ more_mul = one_or_more(DIV_ROUND_UP(lim_fr->min_pll_op_clk_freq_hz,
+ pll_fr->pll_ip_clk_freq_hz * mul));
+
+ dev_dbg(dev, "more_mul: %u\n", more_mul);
+ more_mul *= DIV_ROUND_UP(lim_fr->min_pll_multiplier, mul * more_mul);
+ dev_dbg(dev, "more_mul2: %u\n", more_mul);
+
+ pll_fr->pll_multiplier = mul * more_mul;
+
+ if (pll_fr->pll_multiplier * pll_fr->pll_ip_clk_freq_hz >
+ lim_fr->max_pll_op_clk_freq_hz)
+ return -EINVAL;
+
+ pll_fr->pll_op_clk_freq_hz =
+ pll_fr->pll_ip_clk_freq_hz * pll_fr->pll_multiplier;
+
+ vt_div = div * more_mul;
+
+ ccs_pll_find_vt_sys_div(dev, lim, pll, pll_fr, vt_div, vt_div,
+ &min_sys_div, &max_sys_div);
+
+ max_sys_div = (vt_div & 1) ? 1 : max_sys_div;
+
+ dev_dbg(dev, "vt min/max_sys_div: %u,%u\n", min_sys_div, max_sys_div);
+
+ for (sys_div = min_sys_div; sys_div <= max_sys_div;
+ sys_div += 2 - (sys_div & 1)) {
+ uint16_t pix_div;
+
+ if (vt_div % sys_div)
+ continue;
+
+ pix_div = vt_div / sys_div;
+
+ if (pix_div < lim_bk->min_pix_clk_div ||
+ pix_div > lim_bk->max_pix_clk_div) {
+ dev_dbg(dev,
+ "pix_div %u too small or too big (%u--%u)\n",
+ pix_div,
+ lim_bk->min_pix_clk_div,
+ lim_bk->max_pix_clk_div);
+ continue;
+ }
+
+ if (pix_div * sys_div <= best_div) {
+ best_pix_div = pix_div;
+ best_div = pix_div * sys_div;
+ }
+ }
+ if (best_pix_div == SHRT_MAX >> 1)
+ return -EINVAL;
+
+ pll_bk->sys_clk_div = best_div / best_pix_div;
+ pll_bk->pix_clk_div = best_pix_div;
+
+ pll_bk->sys_clk_freq_hz =
+ pll_fr->pll_op_clk_freq_hz / pll_bk->sys_clk_div;
+ pll_bk->pix_clk_freq_hz =
+ pll_bk->sys_clk_freq_hz / pll_bk->pix_clk_div;
+
+ pll->pixel_rate_pixel_array =
+ pll_bk->pix_clk_freq_hz * pll->vt_lanes;
+
+ return 0;
+}
+
+static int ccs_pll_calculate_vt_tree(struct device *dev,
+ const struct ccs_pll_limits *lim,
+ struct ccs_pll *pll)
+{
+ const struct ccs_pll_branch_limits_fr *lim_fr = &lim->vt_fr;
+ struct ccs_pll_branch_fr *pll_fr = &pll->vt_fr;
+ uint16_t min_pre_pll_clk_div = lim_fr->min_pre_pll_clk_div;
+ uint16_t max_pre_pll_clk_div = lim_fr->max_pre_pll_clk_div;
+ uint32_t pre_mul, pre_div;
+
+ pre_div = gcd(pll->pixel_rate_csi,
+ pll->ext_clk_freq_hz * pll->vt_lanes);
+ pre_mul = pll->pixel_rate_csi / pre_div;
+ pre_div = pll->ext_clk_freq_hz * pll->vt_lanes / pre_div;
+
+ /* Make sure PLL input frequency is within limits */
+ max_pre_pll_clk_div =
+ min_t(uint16_t, max_pre_pll_clk_div,
+ DIV_ROUND_UP(pll->ext_clk_freq_hz,
+ lim_fr->min_pll_ip_clk_freq_hz));
+
+ min_pre_pll_clk_div = max_t(uint16_t, min_pre_pll_clk_div,
+ pll->ext_clk_freq_hz /
+ lim_fr->max_pll_ip_clk_freq_hz);
+
+ dev_dbg(dev, "vt min/max_pre_pll_clk_div: %u,%u\n",
+ min_pre_pll_clk_div, max_pre_pll_clk_div);
+
+ for (pll_fr->pre_pll_clk_div = min_pre_pll_clk_div;
+ pll_fr->pre_pll_clk_div <= max_pre_pll_clk_div;
+ pll_fr->pre_pll_clk_div +=
+ (pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 :
+ 2 - (pll_fr->pre_pll_clk_div & 1)) {
+ uint32_t mul, div;
+ int rval;
+
+ div = gcd(pre_mul * pll_fr->pre_pll_clk_div, pre_div);
+ mul = pre_mul * pll_fr->pre_pll_clk_div / div;
+ div = pre_div / div;
+
+ dev_dbg(dev, "vt pre-div/mul/div: %u,%u,%u\n",
+ pll_fr->pre_pll_clk_div, mul, div);
+
+ rval = __ccs_pll_calculate_vt_tree(dev, lim, pll,
+ mul, div);
+ if (rval)
+ continue;
+
+ rval = check_fr_bounds(dev, lim, pll, PLL_VT);
+ if (rval)
+ continue;
+
+ rval = check_bk_bounds(dev, lim, pll, PLL_VT);
+ if (rval)
+ continue;
+
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
static void
ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
const struct ccs_pll_branch_limits_bk *op_lim_bk,
@@ -525,10 +673,10 @@ ccs_pll_calculate_op(struct device *dev, const struct ccs_pll_limits *lim,
int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
struct ccs_pll *pll)
{
- const struct ccs_pll_branch_limits_fr *op_lim_fr = &lim->vt_fr;
- const struct ccs_pll_branch_limits_bk *op_lim_bk = &lim->op_bk;
- struct ccs_pll_branch_fr *op_pll_fr = &pll->vt_fr;
- struct ccs_pll_branch_bk *op_pll_bk = &pll->op_bk;
+ const struct ccs_pll_branch_limits_fr *op_lim_fr;
+ const struct ccs_pll_branch_limits_bk *op_lim_bk;
+ struct ccs_pll_branch_fr *op_pll_fr;
+ struct ccs_pll_branch_bk *op_pll_bk;
bool cphy = pll->bus_type == CCS_PLL_BUS_TYPE_CSI2_CPHY;
uint32_t phy_const = cphy ? CPHY_CONST : DPHY_CONST;
uint16_t min_op_pre_pll_clk_div;
@@ -544,6 +692,28 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
pll->vt_lanes = 1;
}
+ if (pll->flags & CCS_PLL_FLAG_DUAL_PLL) {
+ op_lim_fr = &lim->op_fr;
+ op_lim_bk = &lim->op_bk;
+ op_pll_fr = &pll->op_fr;
+ op_pll_bk = &pll->op_bk;
+ } else if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) {
+ /*
+ * If there's no OP PLL at all, use the VT values
+ * instead. The OP values are ignored for the rest of
+ * the PLL calculation.
+ */
+ op_lim_fr = &lim->vt_fr;
+ op_lim_bk = &lim->vt_bk;
+ op_pll_fr = &pll->vt_fr;
+ op_pll_bk = &pll->vt_bk;
+ } else {
+ op_lim_fr = &lim->vt_fr;
+ op_lim_bk = &lim->op_bk;
+ op_pll_fr = &pll->vt_fr;
+ op_pll_bk = &pll->op_bk;
+ }
+
if (!pll->op_lanes || !pll->vt_lanes || !pll->bits_per_pixel ||
!pll->ext_clk_freq_hz || !pll->link_freq || !pll->scale_m ||
!op_lim_fr->min_pll_ip_clk_freq_hz ||
@@ -567,17 +737,6 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
dev_dbg(dev, "vt_lanes: %u\n", pll->vt_lanes);
dev_dbg(dev, "op_lanes: %u\n", pll->op_lanes);
- if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) {
- /*
- * If there's no OP PLL at all, use the VT values
- * instead. The OP values are ignored for the rest of
- * the PLL calculation.
- */
- op_lim_fr = &lim->vt_fr;
- op_lim_bk = &lim->vt_bk;
- op_pll_bk = &pll->vt_bk;
- }
-
dev_dbg(dev, "binning: %ux%u\n", pll->binning_horizontal,
pll->binning_vertical);
@@ -653,6 +812,9 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
if (rval)
continue;
+ if (pll->flags & CCS_PLL_FLAG_DUAL_PLL)
+ break;
+
ccs_pll_calculate_vt(dev, lim, op_lim_bk, pll, op_pll_fr,
op_pll_bk, cphy, phy_const);
@@ -663,14 +825,25 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
if (rval)
continue;
- print_pll(dev, pll);
+ break;
+ }
+
+ if (rval) {
+ dev_dbg(dev, "unable to compute pre_pll divisor\n");
- return 0;
+ return rval;
}
- dev_dbg(dev, "unable to compute pre_pll divisor\n");
+ if (pll->flags & CCS_PLL_FLAG_DUAL_PLL) {
+ rval = ccs_pll_calculate_vt_tree(dev, lim, pll);
- return rval;
+ if (rval)
+ return rval;
+ }
+
+ print_pll(dev, pll);
+
+ return 0;
}
EXPORT_SYMBOL_GPL(ccs_pll_calculate);
diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h
index 4fa3d4e459a0..1be8f300c860 100644
--- a/drivers/media/i2c/ccs-pll.h
+++ b/drivers/media/i2c/ccs-pll.h
@@ -29,6 +29,7 @@
#define CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV BIT(5)
#define CCS_PLL_FLAG_FIFO_DERATING BIT(6)
#define CCS_PLL_FLAG_FIFO_OVERRATING BIT(7)
+#define CCS_PLL_FLAG_DUAL_PLL BIT(8)
/**
* struct ccs_pll_branch_fr - CCS PLL configuration (front)
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 088/106] ccs: Dual PLL support
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (76 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 087/106] ccs-pll: Add trivial dual PLL support Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 089/106] ccs-pll: Add support for DDR OP system and pixel clocks Sakari Ailus
` (18 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Add support for sensors that either require dual PLL or support single or
dual PLL but use dual PLL as default.
Use sensor default configuration for sensors that support both modes.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 9 +++++--
drivers/media/i2c/ccs/ccs-core.c | 45 +++++++++++++++++++++++++++++++-
2 files changed, 51 insertions(+), 3 deletions(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index 91b578a05a98..7df7b96e78e6 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -331,7 +331,10 @@ __ccs_pll_calculate_vt_tree(struct device *dev,
continue;
}
- if (pix_div * sys_div <= best_div) {
+ dev_dbg(dev, "sys/pix/best_pix: %u,%u,%u\n", sys_div, pix_div,
+ best_pix_div);
+
+ if (pix_div * sys_div <= best_pix_div) {
best_pix_div = pix_div;
best_div = pix_div * sys_div;
}
@@ -804,7 +807,9 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
if (rval)
continue;
- rval = check_fr_bounds(dev, lim, pll, PLL_VT);
+ rval = check_fr_bounds(dev, lim, pll,
+ pll->flags & CCS_PLL_FLAG_DUAL_PLL ?
+ PLL_OP : PLL_VT);
if (rval)
continue;
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index a169656c4560..b280abb40433 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -396,7 +396,23 @@ static int ccs_pll_configure(struct ccs_sensor *sensor)
if (rval < 0)
return rval;
- return ccs_write(sensor, OP_SYS_CLK_DIV, pll->op_bk.sys_clk_div);
+ rval = ccs_write(sensor, OP_SYS_CLK_DIV, pll->op_bk.sys_clk_div);
+ if (rval < 0)
+ return rval;
+
+ if (!(pll->flags & CCS_PLL_FLAG_DUAL_PLL))
+ return 0;
+
+ rval = ccs_write(sensor, PLL_MODE, CCS_PLL_MODE_DUAL);
+ if (rval < 0)
+ return rval;
+
+ rval = ccs_write(sensor, OP_PRE_PLL_CLK_DIV,
+ pll->op_fr.pre_pll_clk_div);
+ if (rval < 0)
+ return rval;
+
+ return ccs_write(sensor, OP_PLL_MULTIPLIER, pll->op_fr.pll_multiplier);
}
static int ccs_pll_try(struct ccs_sensor *sensor, struct ccs_pll *pll)
@@ -413,6 +429,16 @@ static int ccs_pll_try(struct ccs_sensor *sensor, struct ccs_pll *pll)
.min_pll_op_clk_freq_hz = CCS_LIM(sensor, MIN_PLL_OP_CLK_FREQ_MHZ),
.max_pll_op_clk_freq_hz = CCS_LIM(sensor, MAX_PLL_OP_CLK_FREQ_MHZ),
},
+ .op_fr = {
+ .min_pre_pll_clk_div = CCS_LIM(sensor, MIN_OP_PRE_PLL_CLK_DIV),
+ .max_pre_pll_clk_div = CCS_LIM(sensor, MAX_OP_PRE_PLL_CLK_DIV),
+ .min_pll_ip_clk_freq_hz = CCS_LIM(sensor, MIN_OP_PLL_IP_CLK_FREQ_MHZ),
+ .max_pll_ip_clk_freq_hz = CCS_LIM(sensor, MAX_OP_PLL_IP_CLK_FREQ_MHZ),
+ .min_pll_multiplier = CCS_LIM(sensor, MIN_OP_PLL_MULTIPLIER),
+ .max_pll_multiplier = CCS_LIM(sensor, MAX_OP_PLL_MULTIPLIER),
+ .min_pll_op_clk_freq_hz = CCS_LIM(sensor, MIN_OP_PLL_OP_CLK_FREQ_MHZ),
+ .max_pll_op_clk_freq_hz = CCS_LIM(sensor, MAX_OP_PLL_OP_CLK_FREQ_MHZ),
+ },
.op_bk = {
.min_sys_clk_div = CCS_LIM(sensor, MIN_OP_SYS_CLK_DIV),
.max_sys_clk_div = CCS_LIM(sensor, MAX_OP_SYS_CLK_DIV),
@@ -3223,6 +3249,23 @@ static int ccs_probe(struct i2c_client *client)
CCS_FIFO_SUPPORT_CAPABILITY_DERATING_OVERRATING)
sensor->pll.flags |= CCS_PLL_FLAG_FIFO_DERATING |
CCS_PLL_FLAG_FIFO_OVERRATING;
+ if (CCS_LIM(sensor, CLOCK_TREE_PLL_CAPABILITY) &
+ CCS_CLOCK_TREE_PLL_CAPABILITY_DUAL_PLL) {
+ if (CCS_LIM(sensor, CLOCK_TREE_PLL_CAPABILITY) &
+ CCS_CLOCK_TREE_PLL_CAPABILITY_SINGLE_PLL) {
+ u32 v;
+
+ /* Use sensor default in PLL mode selection */
+ rval = ccs_read(sensor, PLL_MODE, &v);
+ if (rval)
+ goto out_cleanup;
+
+ if (v == CCS_PLL_MODE_DUAL)
+ sensor->pll.flags |= CCS_PLL_FLAG_DUAL_PLL;
+ } else {
+ sensor->pll.flags |= CCS_PLL_FLAG_DUAL_PLL;
+ }
+ }
sensor->pll.op_bits_per_lane = CCS_LIM(sensor, OP_BITS_PER_LANE);
sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk;
sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN);
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 089/106] ccs-pll: Add support for DDR OP system and pixel clocks
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (77 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 088/106] ccs: Dual " Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 090/106] ccs: Add support for DDR OP SYS and OP PIX clocks Sakari Ailus
` (17 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Add support for dual data rate operational system and pixel clocks. This
is implemented using two PLL flags.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 64 +++++++++++++++++++++++++------------
drivers/media/i2c/ccs-pll.h | 2 ++
2 files changed, 46 insertions(+), 20 deletions(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index 7df7b96e78e6..5a0162347777 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -119,7 +119,7 @@ static void print_pll(struct device *dev, struct ccs_pll *pll)
}
}
- dev_dbg(dev, "flags%s%s%s%s%s%s%s\n",
+ dev_dbg(dev, "flags%s%s%s%s%s%s%s%s%s\n",
pll->flags & PLL_FL(LANE_SPEED_MODEL) ? " lane-speed" : "",
pll->flags & PLL_FL(LINK_DECOUPLED) ? " link-decoupled" : "",
pll->flags & PLL_FL(EXT_IP_PLL_DIVIDER) ?
@@ -128,7 +128,19 @@ static void print_pll(struct device *dev, struct ccs_pll *pll)
" flexible-op-pix-div" : "",
pll->flags & PLL_FL(FIFO_DERATING) ? " fifo-derating" : "",
pll->flags & PLL_FL(FIFO_OVERRATING) ? " fifo-overrating" : "",
- pll->flags & PLL_FL(DUAL_PLL) ? " dual-pll" : "");
+ pll->flags & PLL_FL(DUAL_PLL) ? " dual-pll" : "",
+ pll->flags & PLL_FL(OP_SYS_DDR) ? " op-sys-ddr" : "",
+ pll->flags & PLL_FL(OP_PIX_DDR) ? " op-pix-ddr" : "");
+}
+
+static uint32_t op_sys_ddr(uint32_t flags)
+{
+ return flags & CCS_PLL_FLAG_OP_SYS_DDR ? 1 : 0;
+}
+
+static uint32_t op_pix_ddr(uint32_t flags)
+{
+ return flags & CCS_PLL_FLAG_OP_PIX_DDR ? 1 : 0;
}
static int check_fr_bounds(struct device *dev,
@@ -441,8 +453,8 @@ ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
if (!(pll->flags & CCS_PLL_FLAG_FIFO_DERATING)) {
min_vt_div =
op_pll_bk->sys_clk_div * op_pll_bk->pix_clk_div
- * pll->vt_lanes * phy_const
- / pll->op_lanes / PHY_CONST_DIV;
+ * pll->vt_lanes * phy_const / pll->op_lanes
+ / (PHY_CONST_DIV << op_pix_ddr(pll->flags));
} else {
/*
* Some sensors perform analogue binning and some do this
@@ -478,7 +490,7 @@ ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
CCS_PLL_FLAG_LANE_SPEED_MODEL ?
pll->csi2.lanes : 1)
* vt_op_binning_div * pll->scale_m
- * PHY_CONST_DIV);
+ * PHY_CONST_DIV << op_pix_ddr(pll->flags));
}
/* Find smallest and biggest allowed vt divisor. */
@@ -572,7 +584,8 @@ ccs_pll_calculate_op(struct device *dev, const struct ccs_pll_limits *lim,
const struct ccs_pll_branch_limits_bk *op_lim_bk,
struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr,
struct ccs_pll_branch_bk *op_pll_bk, uint32_t mul,
- uint32_t div, uint32_t l, bool cphy, uint32_t phy_const)
+ uint32_t div, uint32_t op_sys_clk_freq_hz_sdr, uint32_t l,
+ bool cphy, uint32_t phy_const)
{
/*
* Higher multipliers (and divisors) are often required than
@@ -658,15 +671,22 @@ ccs_pll_calculate_op(struct device *dev, const struct ccs_pll_limits *lim,
* op_pll_fr->pll_multiplier;
if (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL)
- op_pll_bk->pix_clk_div = pll->bits_per_pixel
- * pll->op_lanes * phy_const
- / PHY_CONST_DIV / pll->csi2.lanes / l;
+ op_pll_bk->pix_clk_div =
+ (pll->bits_per_pixel
+ * pll->op_lanes * (phy_const << op_sys_ddr(pll->flags))
+ / PHY_CONST_DIV / pll->csi2.lanes / l)
+ >> op_pix_ddr(pll->flags);
else
op_pll_bk->pix_clk_div =
- pll->bits_per_pixel * phy_const / PHY_CONST_DIV / l;
+ (pll->bits_per_pixel
+ * (phy_const << op_sys_ddr(pll->flags))
+ / PHY_CONST_DIV / l) >> op_pix_ddr(pll->flags);
op_pll_bk->pix_clk_freq_hz =
- op_pll_bk->sys_clk_freq_hz / op_pll_bk->pix_clk_div;
+ (op_sys_clk_freq_hz_sdr >> op_pix_ddr(pll->flags))
+ / op_pll_bk->pix_clk_div;
+ op_pll_bk->sys_clk_freq_hz =
+ op_sys_clk_freq_hz_sdr >> op_sys_ddr(pll->flags);
dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div);
@@ -682,6 +702,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
struct ccs_pll_branch_bk *op_pll_bk;
bool cphy = pll->bus_type == CCS_PLL_BUS_TYPE_CSI2_CPHY;
uint32_t phy_const = cphy ? CPHY_CONST : DPHY_CONST;
+ uint32_t op_sys_clk_freq_hz_sdr;
uint16_t min_op_pre_pll_clk_div;
uint16_t max_op_pre_pll_clk_div;
uint32_t mul, div;
@@ -731,7 +752,8 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
* op_pix_clk_div is supported
*/
if (!(pll->flags & CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV) &&
- (pll->bits_per_pixel * pll->op_lanes) % (pll->csi2.lanes * l)) {
+ (pll->bits_per_pixel * pll->op_lanes) %
+ (pll->csi2.lanes * l << op_pix_ddr(pll->flags))) {
dev_dbg(dev, "op_pix_clk_div not an integer (bpp %u, op lanes %u, lanes %u, l %u)\n",
pll->bits_per_pixel, pll->op_lanes, pll->csi2.lanes, l);
return -EINVAL;
@@ -746,12 +768,12 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
switch (pll->bus_type) {
case CCS_PLL_BUS_TYPE_CSI2_DPHY:
/* CSI transfers 2 bits per clock per lane; thus times 2 */
- op_pll_bk->sys_clk_freq_hz = pll->link_freq * 2
+ op_sys_clk_freq_hz_sdr = pll->link_freq * 2
* (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
1 : pll->csi2.lanes);
break;
case CCS_PLL_BUS_TYPE_CSI2_CPHY:
- op_pll_bk->sys_clk_freq_hz =
+ op_sys_clk_freq_hz_sdr =
pll->link_freq
* (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
1 : pll->csi2.lanes);
@@ -761,7 +783,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
}
pll->pixel_rate_csi =
- div_u64((uint64_t)op_pll_bk->sys_clk_freq_hz
+ div_u64((uint64_t)op_sys_clk_freq_hz_sdr
* (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
pll->csi2.lanes : 1) * PHY_CONST_DIV,
phy_const * pll->bits_per_pixel * l);
@@ -781,9 +803,10 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
dev_dbg(dev, "pre-pll check: min / max op_pre_pll_clk_div: %u / %u\n",
min_op_pre_pll_clk_div, max_op_pre_pll_clk_div);
- i = gcd(op_pll_bk->sys_clk_freq_hz, pll->ext_clk_freq_hz);
- mul = op_pll_bk->sys_clk_freq_hz / i;
- div = pll->ext_clk_freq_hz / i;
+ i = gcd(op_sys_clk_freq_hz_sdr,
+ pll->ext_clk_freq_hz << op_pix_ddr(pll->flags));
+ mul = op_sys_clk_freq_hz_sdr / i;
+ div = (pll->ext_clk_freq_hz << op_pix_ddr(pll->flags)) / i;
dev_dbg(dev, "mul %u / div %u\n", mul, div);
min_op_pre_pll_clk_div =
@@ -802,8 +825,9 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
(pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 :
2 - (op_pll_fr->pre_pll_clk_div & 1)) {
rval = ccs_pll_calculate_op(dev, lim, op_lim_fr, op_lim_bk, pll,
- op_pll_fr, op_pll_bk, mul, div, l,
- cphy, phy_const);
+ op_pll_fr, op_pll_bk, mul, div,
+ op_sys_clk_freq_hz_sdr, l, cphy,
+ phy_const);
if (rval)
continue;
diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h
index 1be8f300c860..7d1e6e3eaada 100644
--- a/drivers/media/i2c/ccs-pll.h
+++ b/drivers/media/i2c/ccs-pll.h
@@ -30,6 +30,8 @@
#define CCS_PLL_FLAG_FIFO_DERATING BIT(6)
#define CCS_PLL_FLAG_FIFO_OVERRATING BIT(7)
#define CCS_PLL_FLAG_DUAL_PLL BIT(8)
+#define CCS_PLL_FLAG_OP_SYS_DDR BIT(9)
+#define CCS_PLL_FLAG_OP_PIX_DDR BIT(10)
/**
* struct ccs_pll_branch_fr - CCS PLL configuration (front)
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 090/106] ccs: Add support for DDR OP SYS and OP PIX clocks
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (78 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 089/106] ccs-pll: Add support for DDR OP system and pixel clocks Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 091/106] ccs: Print written register values Sakari Ailus
` (16 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Support dual data rate operational system and pixel clocks by conveying
the flags to the PLL calculator and updating how the link rate is
calculated.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index b280abb40433..7a6338a2db4c 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -388,7 +388,8 @@ static int ccs_pll_configure(struct ccs_sensor *sensor)
DIV_ROUND_UP(pll->op_bk.sys_clk_freq_hz,
1000000 / 256 / 256) *
(pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
- sensor->pll.csi2.lanes : 1));
+ sensor->pll.csi2.lanes : 1) <<
+ (pll->flags & CCS_PLL_FLAG_OP_SYS_DDR ? 1 : 0));
if (rval < 0 || sensor->pll.flags & CCS_PLL_FLAG_NO_OP_CLOCKS)
return rval;
@@ -3265,6 +3266,12 @@ static int ccs_probe(struct i2c_client *client)
} else {
sensor->pll.flags |= CCS_PLL_FLAG_DUAL_PLL;
}
+ if (CCS_LIM(sensor, CLOCK_CALCULATION) &
+ CCS_CLOCK_CALCULATION_DUAL_PLL_OP_SYS_DDR)
+ sensor->pll.flags |= CCS_PLL_FLAG_OP_SYS_DDR;
+ if (CCS_LIM(sensor, CLOCK_CALCULATION) &
+ CCS_CLOCK_CALCULATION_DUAL_PLL_OP_PIX_DDR)
+ sensor->pll.flags |= CCS_PLL_FLAG_OP_PIX_DDR;
}
sensor->pll.op_bits_per_lane = CCS_LIM(sensor, OP_BITS_PER_LANE);
sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk;
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 091/106] ccs: Print written register values
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (79 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 090/106] ccs: Add support for DDR OP SYS and OP PIX clocks Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 092/106] ccs-pll: Print pixel rates Sakari Ailus
` (15 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
This helps debugging register writes.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-reg-access.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/media/i2c/ccs/ccs-reg-access.c b/drivers/media/i2c/ccs/ccs-reg-access.c
index 02af2b0abdaf..2025e9ab6e91 100644
--- a/drivers/media/i2c/ccs/ccs-reg-access.c
+++ b/drivers/media/i2c/ccs/ccs-reg-access.c
@@ -338,6 +338,10 @@ int ccs_write_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 val)
put_unaligned_be16(CCS_REG_ADDR(reg), data);
put_unaligned_be32(val << (8 * (sizeof(val) - len)), data + 2);
+ dev_dbg(&client->dev, "writing reg 0x%4.4x value 0x%*.*x (%u)\n",
+ CCS_REG_ADDR(reg), ccs_reg_width(reg) << 1,
+ ccs_reg_width(reg) << 1, val, val);
+
r = ccs_write_retry(client, &msg);
if (r)
dev_err(&client->dev,
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 092/106] ccs-pll: Print pixel rates
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (80 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 091/106] ccs: Print written register values Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 093/106] ccs: Add support for obtaining C-PHY configuration from firmware Sakari Ailus
` (14 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Print pixel rates on CSI-2 bus as well as in pixel array as the variation
allowed in PLL capabilities makes this non-trivial to figure out
otherwise.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs-pll.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index 5a0162347777..eb7b6f01f623 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -119,6 +119,11 @@ static void print_pll(struct device *dev, struct ccs_pll *pll)
}
}
+ dev_dbg(dev, "pixel rate in pixel array:\t%u\n",
+ pll->pixel_rate_pixel_array);
+ dev_dbg(dev, "pixel rate on CSI-2 bus:\t%u\n",
+ pll->pixel_rate_csi);
+
dev_dbg(dev, "flags%s%s%s%s%s%s%s%s%s\n",
pll->flags & PLL_FL(LANE_SPEED_MODEL) ? " lane-speed" : "",
pll->flags & PLL_FL(LINK_DECOUPLED) ? " link-decoupled" : "",
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 093/106] ccs: Add support for obtaining C-PHY configuration from firmware
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (81 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 092/106] ccs-pll: Print pixel rates Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 094/106] ccs: Add digital gain support Sakari Ailus
` (13 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Try parsing the firmware also as C-PHY. Do this only after D-PHY as older
firmware may not explicitly specify bus-type in which case D-PHY is the
default.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 7a6338a2db4c..d1a9a28f29ae 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -2926,6 +2926,10 @@ static int ccs_get_hwconfig(struct ccs_sensor *sensor, struct device *dev)
hwcfg->csi_signalling_mode = CCS_CSI_SIGNALING_MODE_CSI_2_DPHY;
hwcfg->lanes = bus_cfg.bus.mipi_csi2.num_data_lanes;
break;
+ case V4L2_MBUS_CSI2_CPHY:
+ hwcfg->csi_signalling_mode = CCS_CSI_SIGNALING_MODE_CSI_2_CPHY;
+ hwcfg->lanes = bus_cfg.bus.mipi_csi2.num_data_lanes;
+ break;
case V4L2_MBUS_CSI1:
case V4L2_MBUS_CCP2:
hwcfg->csi_signalling_mode = (bus_cfg.bus.mipi_csi1.strobe) ?
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 094/106] ccs: Add digital gain support
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (82 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 093/106] ccs: Add support for obtaining C-PHY configuration from firmware Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 095/106] ccs: Add support for old-style SMIA digital gain Sakari Ailus
` (12 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
CCS supports global (all-component) digital gain. Add support for it.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index d1a9a28f29ae..7975b3900017 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -671,6 +671,11 @@ static int ccs_set_ctrl(struct v4l2_ctrl *ctrl)
case V4L2_CID_ANALOGUE_GAIN:
rval = ccs_write(sensor, ANALOG_GAIN_CODE_GLOBAL, ctrl->val);
+ break;
+
+ case V4L2_CID_DIGITAL_GAIN:
+ rval = ccs_write(sensor, DIGITAL_GAIN_GLOBAL, ctrl->val);
+
break;
case V4L2_CID_EXPOSURE:
rval = ccs_write(sensor, COARSE_INTEGRATION_TIME, ctrl->val);
@@ -740,7 +745,7 @@ static int ccs_init_controls(struct ccs_sensor *sensor)
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
int rval;
- rval = v4l2_ctrl_handler_init(&sensor->pixel_array->ctrl_handler, 12);
+ rval = v4l2_ctrl_handler_init(&sensor->pixel_array->ctrl_handler, 13);
if (rval)
return rval;
@@ -754,6 +759,16 @@ static int ccs_init_controls(struct ccs_sensor *sensor)
max(CCS_LIM(sensor, ANALOG_GAIN_CODE_STEP), 1U),
CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN));
+ if (CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) ==
+ CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL)
+ v4l2_ctrl_new_std(&sensor->pixel_array->ctrl_handler,
+ &ccs_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
+ CCS_LIM(sensor, DIGITAL_GAIN_MIN),
+ CCS_LIM(sensor, DIGITAL_GAIN_MAX),
+ max(CCS_LIM(sensor, DIGITAL_GAIN_STEP_SIZE),
+ 1U),
+ 0x100);
+
/* Exposure limits will be updated soon, use just something here. */
sensor->exposure = v4l2_ctrl_new_std(
&sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 095/106] ccs: Add support for old-style SMIA digital gain
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (83 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 094/106] ccs: Add digital gain support Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 096/106] ccs: Remove analogue gain field Sakari Ailus
` (11 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
SMIA only has per-component digital gain. Add support for it.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 33 +++++++++++++++++++++++--
drivers/media/i2c/ccs/smiapp-reg-defs.h | 2 ++
2 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 7975b3900017..b58cfb308251 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -674,7 +674,34 @@ static int ccs_set_ctrl(struct v4l2_ctrl *ctrl)
break;
case V4L2_CID_DIGITAL_GAIN:
- rval = ccs_write(sensor, DIGITAL_GAIN_GLOBAL, ctrl->val);
+ if (CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) ==
+ CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL) {
+ rval = ccs_write(sensor, DIGITAL_GAIN_GLOBAL,
+ ctrl->val);
+ break;
+ }
+
+ rval = ccs_write_addr(sensor,
+ SMIAPP_REG_U16_DIGITAL_GAIN_GREENR,
+ ctrl->val);
+ if (rval)
+ break;
+
+ rval = ccs_write_addr(sensor,
+ SMIAPP_REG_U16_DIGITAL_GAIN_RED,
+ ctrl->val);
+ if (rval)
+ break;
+
+ rval = ccs_write_addr(sensor,
+ SMIAPP_REG_U16_DIGITAL_GAIN_BLUE,
+ ctrl->val);
+ if (rval)
+ break;
+
+ rval = ccs_write_addr(sensor,
+ SMIAPP_REG_U16_DIGITAL_GAIN_GREENB,
+ ctrl->val);
break;
case V4L2_CID_EXPOSURE:
@@ -760,7 +787,9 @@ static int ccs_init_controls(struct ccs_sensor *sensor)
CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN));
if (CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) ==
- CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL)
+ CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL ||
+ CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) ==
+ SMIAPP_DIGITAL_GAIN_CAPABILITY_PER_CHANNEL)
v4l2_ctrl_new_std(&sensor->pixel_array->ctrl_handler,
&ccs_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
CCS_LIM(sensor, DIGITAL_GAIN_MIN),
diff --git a/drivers/media/i2c/ccs/smiapp-reg-defs.h b/drivers/media/i2c/ccs/smiapp-reg-defs.h
index e80c110ebf3a..177e3e51207a 100644
--- a/drivers/media/i2c/ccs/smiapp-reg-defs.h
+++ b/drivers/media/i2c/ccs/smiapp-reg-defs.h
@@ -535,6 +535,8 @@
#define SMIAPP_DIGITAL_CROP_CAPABILITY_NONE 0
#define SMIAPP_DIGITAL_CROP_CAPABILITY_INPUT_CROP 1
+#define SMIAPP_DIGITAL_GAIN_CAPABILITY_PER_CHANNEL 1
+
#define SMIAPP_BINNING_CAPABILITY_NO 0
#define SMIAPP_BINNING_CAPABILITY_YES 1
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 096/106] ccs: Remove analogue gain field
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (84 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 095/106] ccs: Add support for old-style SMIA digital gain Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 097/106] ccs: Only add analogue gain control if the device supports it Sakari Ailus
` (10 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
The analogue gain control was stored to the device specific struct but was
never used. Remove it.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 13 ++++++-------
drivers/media/i2c/ccs/ccs.h | 1 -
2 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index b58cfb308251..6601ed8e72be 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -778,13 +778,12 @@ static int ccs_init_controls(struct ccs_sensor *sensor)
sensor->pixel_array->ctrl_handler.lock = &sensor->mutex;
- sensor->analog_gain = v4l2_ctrl_new_std(
- &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
- V4L2_CID_ANALOGUE_GAIN,
- CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN),
- CCS_LIM(sensor, ANALOG_GAIN_CODE_MAX),
- max(CCS_LIM(sensor, ANALOG_GAIN_CODE_STEP), 1U),
- CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN));
+ v4l2_ctrl_new_std(&sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
+ V4L2_CID_ANALOGUE_GAIN,
+ CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN),
+ CCS_LIM(sensor, ANALOG_GAIN_CODE_MAX),
+ max(CCS_LIM(sensor, ANALOG_GAIN_CODE_STEP), 1U),
+ CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN));
if (CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) ==
CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL ||
diff --git a/drivers/media/i2c/ccs/ccs.h b/drivers/media/i2c/ccs/ccs.h
index 356b87c33405..9fc3333f6c4e 100644
--- a/drivers/media/i2c/ccs/ccs.h
+++ b/drivers/media/i2c/ccs/ccs.h
@@ -262,7 +262,6 @@ struct ccs_sensor {
unsigned long *valid_link_freqs;
/* Pixel array controls */
- struct v4l2_ctrl *analog_gain;
struct v4l2_ctrl *exposure;
struct v4l2_ctrl *hflip;
struct v4l2_ctrl *vflip;
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 097/106] ccs: Only add analogue gain control if the device supports it
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (85 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 096/106] ccs: Remove analogue gain field Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 098/106] v4l: uapi: Add user control base for CCS controls Sakari Ailus
` (9 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Some devices do not implement analogue gain this way. Only add the control
when a device does have the support.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 6601ed8e72be..d6d6aeceb415 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -778,12 +778,16 @@ static int ccs_init_controls(struct ccs_sensor *sensor)
sensor->pixel_array->ctrl_handler.lock = &sensor->mutex;
- v4l2_ctrl_new_std(&sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
- V4L2_CID_ANALOGUE_GAIN,
- CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN),
- CCS_LIM(sensor, ANALOG_GAIN_CODE_MAX),
- max(CCS_LIM(sensor, ANALOG_GAIN_CODE_STEP), 1U),
- CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN));
+ switch (CCS_LIM(sensor, ANALOG_GAIN_CAPABILITY)) {
+ case CCS_ANALOG_GAIN_CAPABILITY_GLOBAL:
+ v4l2_ctrl_new_std(&sensor->pixel_array->ctrl_handler,
+ &ccs_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
+ CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN),
+ CCS_LIM(sensor, ANALOG_GAIN_CODE_MAX),
+ max(CCS_LIM(sensor, ANALOG_GAIN_CODE_STEP),
+ 1U),
+ CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN));
+ }
if (CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) ==
CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL ||
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 098/106] v4l: uapi: Add user control base for CCS controls
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (86 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 097/106] ccs: Only add analogue gain control if the device supports it Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 099/106] v4l: uapi: ccs: Add controls for analogue gain constants Sakari Ailus
` (8 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Add a control base for CCS controls, and reserve 128 controls. Luckily
these numbers are cheap.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
include/uapi/linux/v4l2-controls.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h
index a184c4939438..a84df4cfd03c 100644
--- a/include/uapi/linux/v4l2-controls.h
+++ b/include/uapi/linux/v4l2-controls.h
@@ -198,6 +198,12 @@ enum v4l2_colorfx {
*/
#define V4L2_CID_USER_ATMEL_ISC_BASE (V4L2_CID_USER_BASE + 0x10c0)
+/*
+ * The base for MIPI CCS driver controls.
+ * We reserve 128 controls for this driver.
+ */
+#define V4L2_CID_USER_CCS_BASE (V4L2_CID_USER_BASE + 0x10e0)
+
/* MPEG-class control IDs */
/* The MPEG controls are applicable to all codec controls
* and the 'MPEG' part of the define is historical */
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 099/106] v4l: uapi: ccs: Add controls for analogue gain constants
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (87 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 098/106] v4l: uapi: Add user control base for CCS controls Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-11-05 12:41 ` Hans Verkuil
2020-11-05 12:56 ` Hans Verkuil
2020-10-07 8:45 ` [PATCH v2 100/106] ccs: Add support for analogue gain coefficient controls Sakari Ailus
` (7 subsequent siblings)
96 siblings, 2 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Add a V4L2 controls for analogue gai constants required to control
analogue gain. The values are device specific and thus need to be obtained
from the driver.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
MAINTAINERS | 1 +
include/uapi/linux/ccs.h | 14 ++++++++++++++
2 files changed, 15 insertions(+)
create mode 100644 include/uapi/linux/ccs.h
diff --git a/MAINTAINERS b/MAINTAINERS
index b72f666b8b60..c173e503b0b7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11569,6 +11569,7 @@ F: drivers/media/i2c/ccs/
F: drivers/media/i2c/ccs-pll.c
F: drivers/media/i2c/ccs-pll.h
F: include/uapi/linux/smiapp.h
+F: include/uapi/linux/ccs.h
MIPS
M: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
diff --git a/include/uapi/linux/ccs.h b/include/uapi/linux/ccs.h
new file mode 100644
index 000000000000..bcdce95955b0
--- /dev/null
+++ b/include/uapi/linux/ccs.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only AND BSD-3-Clause */
+/* Copyright (C) 2020 Intel Corporation */
+
+#ifndef __UAPI_CCS_H__
+#define __UAPI_CCS_H__
+
+#include <linux/videodev2.h>
+
+#define V4L2_CID_CCS_ANALOGUE_GAIN_M0 (V4L2_CID_USER_CCS_BASE + 1)
+#define V4L2_CID_CCS_ANALOGUE_GAIN_C0 (V4L2_CID_USER_CCS_BASE + 2)
+#define V4L2_CID_CCS_ANALOGUE_GAIN_M1 (V4L2_CID_USER_CCS_BASE + 3)
+#define V4L2_CID_CCS_ANALOGUE_GAIN_C1 (V4L2_CID_USER_CCS_BASE + 4)
+
+#endif
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 100/106] ccs: Add support for analogue gain coefficient controls
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (88 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 099/106] v4l: uapi: ccs: Add controls for analogue gain constants Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-11-05 12:46 ` Hans Verkuil
2020-10-07 8:45 ` [PATCH v2 101/106] v4l: uapi: ccs: Add controls for CCS alternative analogue gain Sakari Ailus
` (6 subsequent siblings)
96 siblings, 1 reply; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Add four controls for reading CCS analogue gain coefficients. The
values are constants that are device specific.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 38 ++++++++++++++++++++++++++++++--
1 file changed, 36 insertions(+), 2 deletions(-)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index d6d6aeceb415..2a507b63bafc 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -28,6 +28,7 @@
#include <linux/v4l2-mediabus.h>
#include <media/v4l2-fwnode.h>
#include <media/v4l2-device.h>
+#include <uapi/linux/ccs.h>
#include "ccs.h"
@@ -772,14 +773,46 @@ static int ccs_init_controls(struct ccs_sensor *sensor)
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
int rval;
- rval = v4l2_ctrl_handler_init(&sensor->pixel_array->ctrl_handler, 13);
+ rval = v4l2_ctrl_handler_init(&sensor->pixel_array->ctrl_handler, 17);
if (rval)
return rval;
sensor->pixel_array->ctrl_handler.lock = &sensor->mutex;
switch (CCS_LIM(sensor, ANALOG_GAIN_CAPABILITY)) {
- case CCS_ANALOG_GAIN_CAPABILITY_GLOBAL:
+ case CCS_ANALOG_GAIN_CAPABILITY_GLOBAL: {
+ struct {
+ const char *name;
+ u32 id;
+ s32 value;
+ } const gain_ctrls[] = {
+ { "Analogue Gain m0", V4L2_CID_CCS_ANALOGUE_GAIN_M0,
+ CCS_LIM(sensor, ANALOG_GAIN_M0), },
+ { "Analogue Gain c0", V4L2_CID_CCS_ANALOGUE_GAIN_C0,
+ CCS_LIM(sensor, ANALOG_GAIN_C0), },
+ { "Analogue Gain m1", V4L2_CID_CCS_ANALOGUE_GAIN_M1,
+ CCS_LIM(sensor, ANALOG_GAIN_M1), },
+ { "Analogue Gain c1", V4L2_CID_CCS_ANALOGUE_GAIN_C1,
+ CCS_LIM(sensor, ANALOG_GAIN_C1), },
+ };
+ struct v4l2_ctrl_config ctrl_cfg = {
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .ops = &ccs_ctrl_ops,
+ .flags = V4L2_CTRL_FLAG_READ_ONLY,
+ .step = 1,
+ };
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(gain_ctrls); i++) {
+ ctrl_cfg.name = gain_ctrls[i].name;
+ ctrl_cfg.id = gain_ctrls[i].id;
+ ctrl_cfg.min = ctrl_cfg.max = ctrl_cfg.def =
+ gain_ctrls[i].value;
+
+ v4l2_ctrl_new_custom(&sensor->pixel_array->ctrl_handler,
+ &ctrl_cfg, NULL);
+ }
+
v4l2_ctrl_new_std(&sensor->pixel_array->ctrl_handler,
&ccs_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN),
@@ -788,6 +821,7 @@ static int ccs_init_controls(struct ccs_sensor *sensor)
1U),
CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN));
}
+ }
if (CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) ==
CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL ||
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 101/106] v4l: uapi: ccs: Add controls for CCS alternative analogue gain
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (89 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 100/106] ccs: Add support for analogue gain coefficient controls Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 102/106] ccs: Add support for alternate analogue global gain Sakari Ailus
` (5 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Add two new controls for alternative analogue gain some CCS compliant
camera sensors support.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
include/uapi/linux/ccs.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/uapi/linux/ccs.h b/include/uapi/linux/ccs.h
index bcdce95955b0..f22afa58b446 100644
--- a/include/uapi/linux/ccs.h
+++ b/include/uapi/linux/ccs.h
@@ -10,5 +10,7 @@
#define V4L2_CID_CCS_ANALOGUE_GAIN_C0 (V4L2_CID_USER_CCS_BASE + 2)
#define V4L2_CID_CCS_ANALOGUE_GAIN_M1 (V4L2_CID_USER_CCS_BASE + 3)
#define V4L2_CID_CCS_ANALOGUE_GAIN_C1 (V4L2_CID_USER_CCS_BASE + 4)
+#define V4L2_CID_CCS_ANALOGUE_LINEAR_GAIN (V4L2_CID_USER_CCS_BASE + 5)
+#define V4L2_CID_CCS_ANALOGUE_EXPONENTIAL_GAIN (V4L2_CID_USER_CCS_BASE + 6)
#endif
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 102/106] ccs: Add support for alternate analogue global gain
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (90 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 101/106] v4l: uapi: ccs: Add controls for CCS alternative analogue gain Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 103/106] ccs: Add debug prints for MSR registers Sakari Ailus
` (4 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
The CCS spec defines an alternative implementation for global analogue
gain. Add support for that in the driver.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 55 ++++++++++++++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 2a507b63bafc..0ba06a580951 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -674,6 +674,17 @@ static int ccs_set_ctrl(struct v4l2_ctrl *ctrl)
break;
+ case V4L2_CID_CCS_ANALOGUE_LINEAR_GAIN:
+ rval = ccs_write(sensor, ANALOG_LINEAR_GAIN_GLOBAL, ctrl->val);
+
+ break;
+
+ case V4L2_CID_CCS_ANALOGUE_EXPONENTIAL_GAIN:
+ rval = ccs_write(sensor, ANALOG_EXPONENTIAL_GAIN_GLOBAL,
+ ctrl->val);
+
+ break;
+
case V4L2_CID_DIGITAL_GAIN:
if (CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) ==
CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL) {
@@ -820,6 +831,50 @@ static int ccs_init_controls(struct ccs_sensor *sensor)
max(CCS_LIM(sensor, ANALOG_GAIN_CODE_STEP),
1U),
CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN));
+ }
+ break;
+
+ case CCS_ANALOG_GAIN_CAPABILITY_ALTERNATE_GLOBAL: {
+ struct {
+ const char *name;
+ u32 id;
+ u16 min, max, step;
+ } const gain_ctrls[] = {
+ {
+ "Analogue Linear Gain",
+ V4L2_CID_CCS_ANALOGUE_LINEAR_GAIN,
+ CCS_LIM(sensor, ANALOG_LINEAR_GAIN_MIN),
+ CCS_LIM(sensor, ANALOG_LINEAR_GAIN_MAX),
+ max(CCS_LIM(sensor,
+ ANALOG_LINEAR_GAIN_STEP_SIZE),
+ 1U),
+ },
+ {
+ "Analogue Exponential Gain",
+ V4L2_CID_CCS_ANALOGUE_EXPONENTIAL_GAIN,
+ CCS_LIM(sensor, ANALOG_EXPONENTIAL_GAIN_MIN),
+ CCS_LIM(sensor, ANALOG_EXPONENTIAL_GAIN_MAX),
+ max(CCS_LIM(sensor,
+ ANALOG_EXPONENTIAL_GAIN_STEP_SIZE),
+ 1U),
+ },
+ };
+ struct v4l2_ctrl_config ctrl_cfg = {
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .ops = &ccs_ctrl_ops,
+ };
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(gain_ctrls); i++) {
+ ctrl_cfg.name = gain_ctrls[i].name;
+ ctrl_cfg.min = ctrl_cfg.def = gain_ctrls[i].min;
+ ctrl_cfg.max = gain_ctrls[i].max;
+ ctrl_cfg.step = gain_ctrls[i].step;
+ ctrl_cfg.id = gain_ctrls[i].id;
+
+ v4l2_ctrl_new_custom(&sensor->pixel_array->ctrl_handler,
+ &ctrl_cfg, NULL);
+ }
}
}
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 103/106] ccs: Add debug prints for MSR registers
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (91 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 102/106] ccs: Add support for alternate analogue global gain Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 104/106] v4l: uapi: ccs: Add CCS controls for shading correction Sakari Ailus
` (3 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Also print out MSR registers written to the sensor. This isn't entirely
optimal as the debug strings are produced even if they're not used but
that isn't really a grave issue --- the I²C bus is very slow anyway.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-reg-access.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/media/i2c/ccs/ccs-reg-access.c b/drivers/media/i2c/ccs/ccs-reg-access.c
index 2025e9ab6e91..c600f143a1b9 100644
--- a/drivers/media/i2c/ccs/ccs-reg-access.c
+++ b/drivers/media/i2c/ccs/ccs-reg-access.c
@@ -387,12 +387,20 @@ int ccs_write_data_regs(struct ccs_sensor *sensor, struct ccs_reg *regs,
for (j = 0; j < regs->len;
j += msg.len - 2, regdata += msg.len - 2) {
+ char printbuf[(MAX_WRITE_LEN << 1) + 1 /* nil */] =
+ { 0 };
int rval;
msg.len = min(regs->len - j, MAX_WRITE_LEN);
+ bin2hex(printbuf, regdata, msg.len);
+ dev_dbg(&client->dev,
+ "writing msr reg 0x%4.4x value 0x%s\n",
+ regs->addr + j, printbuf);
+
put_unaligned_be16(regs->addr + j, buf);
memcpy(buf + 2, regdata, msg.len);
+
msg.len += 2;
rval = ccs_write_retry(client, &msg);
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 104/106] v4l: uapi: ccs: Add CCS controls for shading correction
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (92 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 103/106] ccs: Add debug prints for MSR registers Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 105/106] ccs: Add shading correction and luminance correction level controls Sakari Ailus
` (2 subsequent siblings)
96 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Add V4L2 controls for controlling CCS lens shading correction as well as
conveying its capabilities.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
include/uapi/linux/ccs.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/uapi/linux/ccs.h b/include/uapi/linux/ccs.h
index f22afa58b446..877229ce4a36 100644
--- a/include/uapi/linux/ccs.h
+++ b/include/uapi/linux/ccs.h
@@ -12,5 +12,10 @@
#define V4L2_CID_CCS_ANALOGUE_GAIN_C1 (V4L2_CID_USER_CCS_BASE + 4)
#define V4L2_CID_CCS_ANALOGUE_LINEAR_GAIN (V4L2_CID_USER_CCS_BASE + 5)
#define V4L2_CID_CCS_ANALOGUE_EXPONENTIAL_GAIN (V4L2_CID_USER_CCS_BASE + 6)
+#define V4L2_CID_CCS_SHADING_CORRECTION_CAPABILITY (V4L2_CID_USER_CCS_BASE + 7)
+#define V4L2_CCS_SHADING_CORRECTION_COLOUR (1U << 0)
+#define V4L2_CCS_SHADING_CORRECTION_LUMINANCE (1U << 1)
+#define V4L2_CID_CCS_SHADING_CORRECTION (V4L2_CID_USER_CCS_BASE + 8)
+#define V4L2_CID_CCS_LUMINANCE_SHADING_CORRECTION (V4L2_CID_USER_CCS_BASE + 9)
#endif
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 105/106] ccs: Add shading correction and luminance correction level controls
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (93 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 104/106] v4l: uapi: ccs: Add CCS controls for shading correction Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-11-05 12:42 ` Mauro Carvalho Chehab
2020-11-05 13:03 ` Hans Verkuil
2020-10-07 8:45 ` [PATCH v2 106/106] ccs: Add CCS ACPI device ID Sakari Ailus
2020-11-05 7:19 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Mauro Carvalho Chehab
96 siblings, 2 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
Add controls for supporting lens shading correction.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 74 ++++++++++++++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 0ba06a580951..10ed3d01af16 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -757,6 +757,25 @@ static int ccs_set_ctrl(struct v4l2_ctrl *ctrl)
case V4L2_CID_TEST_PATTERN_GREENB:
rval = ccs_write(sensor, TEST_DATA_GREENB, ctrl->val);
+ break;
+ case V4L2_CID_CCS_SHADING_CORRECTION:
+ if (!(CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) &
+ (CCS_SHADING_CORRECTION_CAPABILITY_COLOR_SHADING |
+ CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION)))
+ break;
+
+ rval = ccs_write(sensor, SHADING_CORRECTION_EN,
+ ctrl->val ? CCS_SHADING_CORRECTION_EN_ENABLE :
+ 0);
+
+ break;
+ case V4L2_CID_CCS_LUMINANCE_SHADING_CORRECTION:
+ if (!(CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) &
+ CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION))
+ break;
+
+ rval = ccs_write(sensor, LUMINANCE_CORRECTION_LEVEL, ctrl->val);
+
break;
case V4L2_CID_PIXEL_RATE:
/* For v4l2_ctrl_s_ctrl_int64() used internally. */
@@ -878,6 +897,61 @@ static int ccs_init_controls(struct ccs_sensor *sensor)
}
}
+ if (CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) &
+ CCS_SHADING_CORRECTION_CAPABILITY_COLOR_SHADING) {
+ const struct v4l2_ctrl_config ctrl_cfg = {
+ .name = "Shading Correction",
+ .type = V4L2_CTRL_TYPE_BOOLEAN,
+ .id = V4L2_CID_CCS_SHADING_CORRECTION,
+ .ops = &ccs_ctrl_ops,
+ .max = 1,
+ .step = 1,
+ };
+
+ v4l2_ctrl_new_custom(&sensor->pixel_array->ctrl_handler,
+ &ctrl_cfg, NULL);
+ }
+
+ if (CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) &
+ CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION) {
+ const struct v4l2_ctrl_config ctrl_cfg = {
+ .name = "Luminance Shading Correction",
+ .type = V4L2_CTRL_TYPE_BOOLEAN,
+ .id = V4L2_CID_CCS_LUMINANCE_SHADING_CORRECTION,
+ .ops = &ccs_ctrl_ops,
+ .max = 255,
+ .step = 1,
+ .def = 128,
+ };
+
+ v4l2_ctrl_new_custom(&sensor->pixel_array->ctrl_handler,
+ &ctrl_cfg, NULL);
+ }
+
+ if (CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) &
+ (CCS_SHADING_CORRECTION_CAPABILITY_COLOR_SHADING |
+ CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION)) {
+ u32 val =
+ ((CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) &
+ CCS_SHADING_CORRECTION_CAPABILITY_COLOR_SHADING) ?
+ V4L2_CCS_SHADING_CORRECTION_COLOUR : 0) |
+ ((CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) &
+ CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION) ?
+ V4L2_CCS_SHADING_CORRECTION_LUMINANCE : 0);
+ const struct v4l2_ctrl_config ctrl_cfg = {
+ .name = "Shading Correction Capability",
+ .type = V4L2_CTRL_TYPE_BITMASK,
+ .id = V4L2_CID_CCS_SHADING_CORRECTION_CAPABILITY,
+ .ops = &ccs_ctrl_ops,
+ .max = val,
+ .def = val,
+ .flags = V4L2_CTRL_FLAG_READ_ONLY,
+ };
+
+ v4l2_ctrl_new_custom(&sensor->pixel_array->ctrl_handler,
+ &ctrl_cfg, NULL);
+ }
+
if (CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) ==
CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL ||
CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) ==
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* [PATCH v2 106/106] ccs: Add CCS ACPI device ID
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (94 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 105/106] ccs: Add shading correction and luminance correction level controls Sakari Ailus
@ 2020-10-07 8:45 ` Sakari Ailus
2020-11-05 12:44 ` Mauro Carvalho Chehab
2020-11-05 7:19 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Mauro Carvalho Chehab
96 siblings, 1 reply; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 8:45 UTC (permalink / raw)
To: linux-media
The CCS compliant sensors use device ID "MIPI0200". Use this id for ACPI
device matching.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 10ed3d01af16..297c5373a305 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -3604,6 +3604,12 @@ static const struct ccs_device smia_device = {
static const struct ccs_device ccs_device = {};
+static const struct acpi_device_id ccs_acpi_table[] = {
+ { .id = "MIPI0200", .driver_data = (unsigned long)&ccs_device },
+ { },
+};
+MODULE_DEVICE_TABLE(acpi, ccs_acpi_table);
+
static const struct of_device_id ccs_of_table[] = {
{ .compatible = "mipi-ccs-1.1", .data = &ccs_device },
{ .compatible = "mipi-ccs-1.0", .data = &ccs_device },
@@ -3620,6 +3626,7 @@ static const struct dev_pm_ops ccs_pm_ops = {
static struct i2c_driver ccs_i2c_driver = {
.driver = {
+ .acpi_match_table = ccs_acpi_table,
.of_match_table = ccs_of_table,
.name = CCS_NAME,
.pm = &ccs_pm_ops,
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* Re: [PATCH v2 026/106] dt-bindings: mipi-ccs: Add bus-type for C-PHY support
2020-10-07 8:45 ` [PATCH v2 026/106] dt-bindings: mipi-ccs: Add bus-type for C-PHY support Sakari Ailus
@ 2020-10-07 13:52 ` Rob Herring
2020-10-07 14:46 ` Sakari Ailus
2020-10-07 14:49 ` [PATCH v3 " Sakari Ailus
0 siblings, 2 replies; 146+ messages in thread
From: Rob Herring @ 2020-10-07 13:52 UTC (permalink / raw)
To: Sakari Ailus; +Cc: devicetree, linux-media
On Wed, 07 Oct 2020 11:45:03 +0300, Sakari Ailus wrote:
> The bus-type property is required for C-PHY support. Add it, including
> values for CCP2 and CSI-2 D-PHY.
>
> Also require the bus-type property. Effectively all new sensors are MIPI
> D-PHY or C-PHY that cannot be told apart without the bus-type property.
>
> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> ---
> .../devicetree/bindings/media/i2c/mipi-ccs.yaml | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
My bot found errors running 'make dt_binding_check' on your patch:
Traceback (most recent call last):
File "/usr/local/bin/dt-extract-example", line 45, in <module>
binding = yaml.load(open(args.yamlfile, encoding='utf-8').read())
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/main.py", line 343, in load
return constructor.get_single_data()
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 111, in get_single_data
node = self.composer.get_single_node()
File "_ruamel_yaml.pyx", line 706, in _ruamel_yaml.CParser.get_single_node
File "_ruamel_yaml.pyx", line 724, in _ruamel_yaml.CParser._compose_document
File "_ruamel_yaml.pyx", line 775, in _ruamel_yaml.CParser._compose_node
File "_ruamel_yaml.pyx", line 889, in _ruamel_yaml.CParser._compose_mapping_node
File "_ruamel_yaml.pyx", line 775, in _ruamel_yaml.CParser._compose_node
File "_ruamel_yaml.pyx", line 889, in _ruamel_yaml.CParser._compose_mapping_node
File "_ruamel_yaml.pyx", line 775, in _ruamel_yaml.CParser._compose_node
File "_ruamel_yaml.pyx", line 889, in _ruamel_yaml.CParser._compose_mapping_node
File "_ruamel_yaml.pyx", line 775, in _ruamel_yaml.CParser._compose_node
File "_ruamel_yaml.pyx", line 889, in _ruamel_yaml.CParser._compose_mapping_node
File "_ruamel_yaml.pyx", line 775, in _ruamel_yaml.CParser._compose_node
File "_ruamel_yaml.pyx", line 889, in _ruamel_yaml.CParser._compose_mapping_node
File "_ruamel_yaml.pyx", line 773, in _ruamel_yaml.CParser._compose_node
File "_ruamel_yaml.pyx", line 852, in _ruamel_yaml.CParser._compose_sequence_node
File "_ruamel_yaml.pyx", line 904, in _ruamel_yaml.CParser._parse_next_event
ruamel.yaml.scanner.ScannerError: while scanning a plain scalar
in "<unicode string>", line 89, column 13
found a tab character that violates indentation
in "<unicode string>", line 90, column 1
make[1]: *** [Documentation/devicetree/bindings/Makefile:18: Documentation/devicetree/bindings/media/i2c/mipi-ccs.example.dts] Error 1
make[1]: *** Deleting file 'Documentation/devicetree/bindings/media/i2c/mipi-ccs.example.dts'
make[1]: *** Waiting for unfinished jobs....
./Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml: while scanning a plain scalar
in "<unicode string>", line 89, column 13
found a tab character that violates indentation
in "<unicode string>", line 90, column 1
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml: ignoring, error parsing file
warning: no schema found in file: ./Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml
make: *** [Makefile:1366: dt_binding_check] Error 2
See https://patchwork.ozlabs.org/patch/1377845
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure dt-schema is up to date:
pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 026/106] dt-bindings: mipi-ccs: Add bus-type for C-PHY support
2020-10-07 13:52 ` Rob Herring
@ 2020-10-07 14:46 ` Sakari Ailus
2020-10-07 14:49 ` [PATCH v3 " Sakari Ailus
1 sibling, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 14:46 UTC (permalink / raw)
To: Rob Herring; +Cc: devicetree, linux-media
Hi Rob,
On Wed, Oct 07, 2020 at 08:52:25AM -0500, Rob Herring wrote:
> On Wed, 07 Oct 2020 11:45:03 +0300, Sakari Ailus wrote:
> > The bus-type property is required for C-PHY support. Add it, including
> > values for CCP2 and CSI-2 D-PHY.
> >
> > Also require the bus-type property. Effectively all new sensors are MIPI
> > D-PHY or C-PHY that cannot be told apart without the bus-type property.
> >
> > Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> > ---
> > .../devicetree/bindings/media/i2c/mipi-ccs.yaml | 9 +++++++++
> > 1 file changed, 9 insertions(+)
> >
>
>
> My bot found errors running 'make dt_binding_check' on your patch:
>
> Traceback (most recent call last):
> File "/usr/local/bin/dt-extract-example", line 45, in <module>
> binding = yaml.load(open(args.yamlfile, encoding='utf-8').read())
> File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/main.py", line 343, in load
> return constructor.get_single_data()
> File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 111, in get_single_data
> node = self.composer.get_single_node()
> File "_ruamel_yaml.pyx", line 706, in _ruamel_yaml.CParser.get_single_node
> File "_ruamel_yaml.pyx", line 724, in _ruamel_yaml.CParser._compose_document
> File "_ruamel_yaml.pyx", line 775, in _ruamel_yaml.CParser._compose_node
> File "_ruamel_yaml.pyx", line 889, in _ruamel_yaml.CParser._compose_mapping_node
> File "_ruamel_yaml.pyx", line 775, in _ruamel_yaml.CParser._compose_node
> File "_ruamel_yaml.pyx", line 889, in _ruamel_yaml.CParser._compose_mapping_node
> File "_ruamel_yaml.pyx", line 775, in _ruamel_yaml.CParser._compose_node
> File "_ruamel_yaml.pyx", line 889, in _ruamel_yaml.CParser._compose_mapping_node
> File "_ruamel_yaml.pyx", line 775, in _ruamel_yaml.CParser._compose_node
> File "_ruamel_yaml.pyx", line 889, in _ruamel_yaml.CParser._compose_mapping_node
> File "_ruamel_yaml.pyx", line 775, in _ruamel_yaml.CParser._compose_node
> File "_ruamel_yaml.pyx", line 889, in _ruamel_yaml.CParser._compose_mapping_node
> File "_ruamel_yaml.pyx", line 773, in _ruamel_yaml.CParser._compose_node
> File "_ruamel_yaml.pyx", line 852, in _ruamel_yaml.CParser._compose_sequence_node
> File "_ruamel_yaml.pyx", line 904, in _ruamel_yaml.CParser._parse_next_event
> ruamel.yaml.scanner.ScannerError: while scanning a plain scalar
> in "<unicode string>", line 89, column 13
> found a tab character that violates indentation
> in "<unicode string>", line 90, column 1
> make[1]: *** [Documentation/devicetree/bindings/Makefile:18: Documentation/devicetree/bindings/media/i2c/mipi-ccs.example.dts] Error 1
> make[1]: *** Deleting file 'Documentation/devicetree/bindings/media/i2c/mipi-ccs.example.dts'
> make[1]: *** Waiting for unfinished jobs....
> ./Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml: while scanning a plain scalar
> in "<unicode string>", line 89, column 13
> found a tab character that violates indentation
> in "<unicode string>", line 90, column 1
> /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml: ignoring, error parsing file
> warning: no schema found in file: ./Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml
> make: *** [Makefile:1366: dt_binding_check] Error 2
>
>
> See https://patchwork.ozlabs.org/patch/1377845
>
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure dt-schema is up to date:
>
> pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade
>
> Please check and re-submit.
I tested this but somehow I managed to change it after testing it. :-)
I'll resend in a moment.
--
Kind regards,
Sakari Ailus
^ permalink raw reply [flat|nested] 146+ messages in thread
* [PATCH v3 026/106] dt-bindings: mipi-ccs: Add bus-type for C-PHY support
2020-10-07 13:52 ` Rob Herring
2020-10-07 14:46 ` Sakari Ailus
@ 2020-10-07 14:49 ` Sakari Ailus
2020-10-07 16:24 ` Rob Herring
1 sibling, 1 reply; 146+ messages in thread
From: Sakari Ailus @ 2020-10-07 14:49 UTC (permalink / raw)
To: linux-media; +Cc: devicetree, Rob Herring
The bus-type property is required for C-PHY support. Add it, including
values for CCP2 and CSI-2 D-PHY.
Also require the bus-type property. Effectively all new sensors are MIPI
D-PHY or C-PHY that cannot be told apart without the bus-type property.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
.../devicetree/bindings/media/i2c/mipi-ccs.yaml | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml b/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml
index a386ee246956..1d90767a6196 100644
--- a/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml
+++ b/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml
@@ -77,9 +77,17 @@ properties:
data-lanes:
minItems: 1
maxItems: 8
+ bus-type:
+ description: The type of the data bus.
+ oneOf:
+ - const: 1 # CSI-2 C-PHY
+ - const: 3 # CCP2
+ - const: 4 # CSI-2 D-PHY
+
required:
- link-frequencies
- data-lanes
+ - bus-type
required:
- compatible
@@ -112,6 +120,7 @@ examples:
remote-endpoint = <&csi2a_ep>;
link-frequencies = /bits/ 64 <199200000 210000000
499200000>;
+ bus-type = <4>;
};
};
};
--
2.27.0
^ permalink raw reply related [flat|nested] 146+ messages in thread
* Re: [PATCH v2 022/106] dt-bindings: nokia,smia: Remove nokia,nvm-size property
2020-10-07 8:44 ` [PATCH v2 022/106] dt-bindings: nokia,smia: Remove nokia,nvm-size property Sakari Ailus
@ 2020-10-07 16:04 ` Rob Herring
0 siblings, 0 replies; 146+ messages in thread
From: Rob Herring @ 2020-10-07 16:04 UTC (permalink / raw)
To: Sakari Ailus; +Cc: devicetree, linux-media
On Wed, 07 Oct 2020 11:44:59 +0300, Sakari Ailus wrote:
> nokia,nvm-size property was removed from the bindings but it was left in
> the example. Remove it from the example, too.
>
> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> ---
> Documentation/devicetree/bindings/media/i2c/nokia,smia.txt | 1 -
> 1 file changed, 1 deletion(-)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 023/106] dt-bindings: nokia,smia: Convert to YAML
2020-10-07 8:45 ` [PATCH v2 023/106] dt-bindings: nokia,smia: Convert to YAML Sakari Ailus
@ 2020-10-07 16:06 ` Rob Herring
0 siblings, 0 replies; 146+ messages in thread
From: Rob Herring @ 2020-10-07 16:06 UTC (permalink / raw)
To: Sakari Ailus; +Cc: linux-media, devicetree
On Wed, 07 Oct 2020 11:45:00 +0300, Sakari Ailus wrote:
> Convert nokia,smia DT bindings to YAML.
>
> Also add explicit license to bindings.
>
> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> ---
> .../bindings/media/i2c/nokia,smia.txt | 67 -----------
> .../bindings/media/i2c/nokia,smia.yaml | 106 ++++++++++++++++++
> MAINTAINERS | 2 +-
> 3 files changed, 107 insertions(+), 68 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
> create mode 100644 Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 025/106] dt-bindings: nokia,smia: Amend SMIA bindings with MIPI CCS support
2020-10-07 8:45 ` [PATCH v2 025/106] dt-bindings: nokia,smia: Amend SMIA bindings with MIPI CCS support Sakari Ailus
@ 2020-10-07 16:07 ` Rob Herring
0 siblings, 0 replies; 146+ messages in thread
From: Rob Herring @ 2020-10-07 16:07 UTC (permalink / raw)
To: Sakari Ailus; +Cc: linux-media, devicetree
On Wed, 07 Oct 2020 11:45:02 +0300, Sakari Ailus wrote:
> Amend the existing SMIA bindings by adding MIPI CCS support, with separate
> compatible strings for CCS 1.0 and CCS 1.1. Rename the old bindings
> accordingly as CCS is the current standard.
>
> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> ---
> .../i2c/{nokia,smia.yaml => mipi-ccs.yaml} | 23 ++++++++++++++-----
> MAINTAINERS | 2 +-
> 2 files changed, 18 insertions(+), 7 deletions(-)
> rename Documentation/devicetree/bindings/media/i2c/{nokia,smia.yaml => mipi-ccs.yaml} (81%)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 053/106] dt-bindings: mipi,ccs: Don't mention vana voltage
2020-10-07 8:45 ` [PATCH v2 053/106] dt-bindings: mipi,ccs: Don't mention vana voltage Sakari Ailus
@ 2020-10-07 16:07 ` Rob Herring
0 siblings, 0 replies; 146+ messages in thread
From: Rob Herring @ 2020-10-07 16:07 UTC (permalink / raw)
To: Sakari Ailus; +Cc: devicetree, linux-media
On Wed, 07 Oct 2020 11:45:04 +0300, Sakari Ailus wrote:
> It was mentioned vana voltage is typically 2,8 volts. This is truly sensor
> dependent, and nowadays 2,8 volts is a lot.
>
> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> ---
> Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 054/106] dt-bindings: mipi,ccs: Add vcore and vio supplies
2020-10-07 8:45 ` [PATCH v2 054/106] dt-bindings: mipi,ccs: Add vcore and vio supplies Sakari Ailus
@ 2020-10-07 16:08 ` Rob Herring
0 siblings, 0 replies; 146+ messages in thread
From: Rob Herring @ 2020-10-07 16:08 UTC (permalink / raw)
To: Sakari Ailus; +Cc: linux-media, devicetree
On Wed, 07 Oct 2020 11:45:05 +0300, Sakari Ailus wrote:
> Vcore and vio supplies are also part of the spec and used by many sensors.
> Do not specify the voltages as they are generally sensor dependent.
>
> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> ---
> Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v3 026/106] dt-bindings: mipi-ccs: Add bus-type for C-PHY support
2020-10-07 14:49 ` [PATCH v3 " Sakari Ailus
@ 2020-10-07 16:24 ` Rob Herring
0 siblings, 0 replies; 146+ messages in thread
From: Rob Herring @ 2020-10-07 16:24 UTC (permalink / raw)
To: Sakari Ailus; +Cc: linux-media, devicetree
On Wed, 07 Oct 2020 17:49:37 +0300, Sakari Ailus wrote:
> The bus-type property is required for C-PHY support. Add it, including
> values for CCP2 and CSI-2 D-PHY.
>
> Also require the bus-type property. Effectively all new sensors are MIPI
> D-PHY or C-PHY that cannot be told apart without the bus-type property.
>
> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> ---
> .../devicetree/bindings/media/i2c/mipi-ccs.yaml | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
` (95 preceding siblings ...)
2020-10-07 8:45 ` [PATCH v2 106/106] ccs: Add CCS ACPI device ID Sakari Ailus
@ 2020-11-05 7:19 ` Mauro Carvalho Chehab
2020-11-05 8:01 ` Sakari Ailus
96 siblings, 1 reply; 146+ messages in thread
From: Mauro Carvalho Chehab @ 2020-11-05 7:19 UTC (permalink / raw)
To: Sakari Ailus; +Cc: linux-media
Hi,
Em Wed, 7 Oct 2020 11:44:21 +0300
Sakari Ailus <sakari.ailus@linux.intel.com> escreveu:
> Add register definitions of the MIPI CCS 1.1 standard.
>
> The CCS driver makes extended use of device's capability registers that
> are dependent on CCS version. This involves having an in-memory data
> structure for limit and capability information, creating that data
> structure and accessing it.
>
> The register definitions as well as the definitions of this data structure
> are generated from a text file using a Perl script. Do the generation here
> and so avoid making manual, error-prone changes to the several generated
> files.
I understand the reason behind using a perl script to parse some
text file in order to generate register's definition files,
but I can't see what's the sense of storing the perl script and
such texts together with the Kernel building system, re-generating them
every time.
I mean: register definitions is something that it is supposed to be
stable, and nothing something that will change on every Kernel
compilation.
How often are you expecting changes at ccs-regs.txt?
>
> Also add ccs-os.h header that contains Linux headers to be included.
>
> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> ---
> drivers/media/i2c/smiapp/Makefile | 15 +-
> drivers/media/i2c/smiapp/ccs-os.h | 15 +
> drivers/media/i2c/smiapp/ccs-regs.txt | 1041 +++++++++++++++++++++++++
> drivers/media/i2c/smiapp/mk-ccs-regs | 405 ++++++++++
> 4 files changed, 1475 insertions(+), 1 deletion(-)
> create mode 100644 drivers/media/i2c/smiapp/ccs-os.h
> create mode 100644 drivers/media/i2c/smiapp/ccs-regs.txt
> create mode 100644 drivers/media/i2c/smiapp/mk-ccs-regs
>
> diff --git a/drivers/media/i2c/smiapp/Makefile b/drivers/media/i2c/smiapp/Makefile
> index 86f57a43f8e8..4638d1e14ebc 100644
> --- a/drivers/media/i2c/smiapp/Makefile
> +++ b/drivers/media/i2c/smiapp/Makefile
> @@ -1,6 +1,19 @@
> # SPDX-License-Identifier: GPL-2.0-only
> smiapp-objs += smiapp-core.o smiapp-regs.o \
> - smiapp-quirk.o smiapp-limits.o
> + smiapp-quirk.o smiapp-limits.o \
> + ccs-limits.o
> obj-$(CONFIG_VIDEO_SMIAPP) += smiapp.o
>
> ccflags-y += -I $(srctree)/drivers/media/i2c
> +
> +quiet_cmd_perlgen = PERL $(src)/mk-ccs-regs
> + cmd_perlgen = $(PERL) $(src)/mk-ccs-regs -e $(obj)/ccs-regs.h \
> + -L $(obj)/ccs-limits.h -l $(obj)/ccs-limits.c \
> + -c $(src)/ccs-regs.txt
> +
> +$(obj)/ccs-limits.c: $(src)/ccs-regs.txt
> + $(call cmd,perlgen)
> +
> +$(obj)/ccs-regs.h $(obj)/ccs-limits.h: $(obj)/ccs-limits.c
> +
> +clean-files: $(obj)/ccs-regs.h $(obj)/ccs-limits.h $(obj)/ccs-limits.c
> diff --git a/drivers/media/i2c/smiapp/ccs-os.h b/drivers/media/i2c/smiapp/ccs-os.h
> new file mode 100644
> index 000000000000..f2445733f5d5
> --- /dev/null
> +++ b/drivers/media/i2c/smiapp/ccs-os.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/* Copyright 2020 Intel Corporation */
> +
> +#include <linux/device.h>
> +#include <linux/errno.h>
> +#include <linux/limits.h>
> +#include <linux/mm.h>
> +#include <linux/slab.h>
> +#include <linux/types.h>
> +
> +typedef struct device * printf_ctx;
> +#define os_printf dev_dbg
> +#define os_calloc(size) kvcalloc(1, size, GFP_KERNEL)
> +#define os_free kvfree
> +#define align2 ALIGN
> diff --git a/drivers/media/i2c/smiapp/ccs-regs.txt b/drivers/media/i2c/smiapp/ccs-regs.txt
> new file mode 100644
> index 000000000000..9219b1421334
> --- /dev/null
> +++ b/drivers/media/i2c/smiapp/ccs-regs.txt
> @@ -0,0 +1,1041 @@
> +# Copyright (C) 2019--2020 Intel Corporation
> +# SPDX-License-Identifier: BSD-3-Clause
> +
> +# register rflags
> +# - f field LSB MSB rflags
> +# - e enum value # after a field
> +# - e enum value [LSB MSB]
> +# - b bool bit
> +# - l arg name min max elsize [discontig...]
> +#
> +# rflags
> +# 8, 16, 32 register bits (default is 8)
> +# v1.1 defined in version 1.1
> +# f formula
> +# float_ireal iReal or IEEE 754; 32 bits
> +# ireal unsigned iReal
> +
> +# general status registers
> +module_model_id 0x0000 16
> +module_revision_number_major 0x0002 8
> +frame_count 0x0005 8
> +pixel_order 0x0006 8
> +- e GRBG 0
> +- e RGGB 1
> +- e BGGR 2
> +- e GBRG 3
> +MIPI_CCS_version 0x0007 8
> +- e v1_0 0x10
> +- e v1_1 0x11
> +- f major 4 7
> +- f minor 0 3
> +data_pedestal 0x0008 16
> +module_manufacturer_id 0x000e 16
> +module_revision_number_minor 0x0010 8
> +module_date_year 0x0012 8
> +module_date_month 0x0013 8
> +module_date_day 0x0014 8
> +module_date_phase 0x0015 8
> +- f 0 2
> +- e ts 0
> +- e es 1
> +- e cs 2
> +- e mp 3
> +sensor_model_id 0x0016 16
> +sensor_revision_number 0x0018 8
> +sensor_firmware_version 0x001a 8
> +serial_number 0x001c 32
> +sensor_manufacturer_id 0x0020 16
> +sensor_revision_number_16 0x0022 16
> +
> +# frame format description registers
> +frame_format_model_type 0x0040 8
> +- e 2-byte 1
> +- e 4-byte 2
> +frame_format_model_subtype 0x0041 8
> +- f rows 0 3
> +- f columns 4 7
> +frame_format_descriptor(n) 0x0042 16 f
> +- l n 0 14 2
> +- f pixels 0 11
> +- f pcode 12 15
> +- e embedded 1
> +- e dummy_pixel 2
> +- e black_pixel 3
> +- e dark_pixel 4
> +- e visible_pixel 5
> +- e manuf_specific_0 8
> +- e manuf_specific_1 9
> +- e manuf_specific_2 10
> +- e manuf_specific_3 11
> +- e manuf_specific_4 12
> +- e manuf_specific_5 13
> +- e manuf_specific_6 14
> +frame_format_descriptor_4(n) 0x0060 32 f
> +- l n 0 7 4
> +- f pixels 0 15
> +- f pcode 28 31
> +- e embedded 1
> +- e dummy_pixel 2
> +- e black_pixel 3
> +- e dark_pixel 4
> +- e visible_pixel 5
> +- e manuf_specific_0 8
> +- e manuf_specific_1 9
> +- e manuf_specific_2 10
> +- e manuf_specific_3 11
> +- e manuf_specific_4 12
> +- e manuf_specific_5 13
> +- e manuf_specific_6 14
> +
> +# analog gain description registers
> +analog_gain_capability 0x0080 16
> +- e global 0
> +- e alternate_global 2
> +analog_gain_code_min 0x0084 16
> +analog_gain_code_max 0x0086 16
> +analog_gain_code_step 0x0088 16
> +analog_gain_type 0x008a 16
> +analog_gain_m0 0x008c 16
> +analog_gain_c0 0x008e 16
> +analog_gain_m1 0x0090 16
> +analog_gain_c1 0x0092 16
> +analog_linear_gain_min 0x0094 16 v1.1
> +analog_linear_gain_max 0x0096 16 v1.1
> +analog_linear_gain_step_size 0x0098 16 v1.1
> +analog_exponential_gain_min 0x009a 16 v1.1
> +analog_exponential_gain_max 0x009c 16 v1.1
> +analog_exponential_gain_step_size 0x009e 16 v1.1
> +
> +# data format description registers
> +data_format_model_type 0x00c0 8
> +- e normal 1
> +- e extended 2
> +data_format_model_subtype 0x00c1 8
> +- f rows 0 3
> +- f columns 4 7
> +data_format_descriptor(n) 0x00c2 16 f
> +- l n 0 15 2
> +- f compressed 0 7
> +- f uncompressed 8 15
> +
> +# general set-up registers
> +mode_select 0x0100 8
> +- e software_standby 0
> +- e streaming 1
> +image_orientation 0x0101 8
> +- b horizontal_mirror 0
> +- b vertical_flip 1
> +software_reset 0x0103 8
> +- e off 0
> +- e on 1
> +grouped_parameter_hold 0x0104 8
> +mask_corrupted_frames 0x0105 8
> +- e allow 0
> +- e mask 1
> +fast_standby_ctrl 0x0106 8
> +- e complete_frames 0
> +- e frame_truncation 1
> +CCI_address_ctrl 0x0107 8
> +2nd_CCI_if_ctrl 0x0108 8
> +- b enable 0
> +- b ack 1
> +2nd_CCI_address_ctrl 0x0109 8
> +CSI_channel_identifier 0x0110 8
> +CSI_signaling_mode 0x0111 8
> +- e csi_2_dphy 2
> +- e csi_2_cphy 3
> +CSI_data_format 0x0112 16
> +CSI_lane_mode 0x0114 8
> +DPCM_Frame_DT 0x011d 8
> +Bottom_embedded_data_DT 0x011e 8
> +Bottom_embedded_data_VC 0x011f 8
> +
> +gain_mode 0x0120 8
> +- e global 0
> +- e alternate 1
> +ADC_bit_depth 0x0121 8
> +emb_data_ctrl 0x0122 v1.1
> +- b raw8_packing_for_raw16 0
> +- b raw10_packing_for_raw20 1
> +- b raw12_packing_for_raw24 2
> +
> +GPIO_TRIG_mode 0x0130 8
> +extclk_frequency_mhz 0x0136 16 ireal
> +temp_sensor_ctrl 0x0138 8
> +- b enable 0
> +temp_sensor_mode 0x0139 8
> +temp_sensor_output 0x013a 8
> +
> +# integration time registers
> +fine_integration_time 0x0200 16
> +coarse_integration_time 0x0202 16
> +
> +# analog gain registers
> +analog_gain_code_global 0x0204 16
> +analog_linear_gain_global 0x0206 16 v1.1
> +analog_exponential_gain_global 0x0208 16 v1.1
> +
> +# digital gain registers
> +digital_gain_global 0x020e 16
> +
> +# hdr control registers
> +Short_analog_gain_global 0x0216 16
> +Short_digital_gain_global 0x0218 16
> +
> +HDR_mode 0x0220 8
> +- b enabled 0
> +- b separate_analog_gain 1
> +- b upscaling 2
> +- b reset_sync 3
> +- b timing_mode 4
> +- b exposure_ctrl_direct 5
> +- b separate_digital_gain 6
> +HDR_resolution_reduction 0x0221 8
> +- f row 0 3
> +- f column 4 7
> +Exposure_ratio 0x0222 8
> +HDR_internal_bit_depth 0x0223 8
> +Direct_short_integration_time 0x0224 16
> +Short_analog_linear_gain_global 0x0226 16 v1.1
> +Short_analog_exponential_gain_global 0x0228 16 v1.1
> +
> +# clock set-up registers
> +vt_pix_clk_div 0x0300 16
> +vt_sys_clk_div 0x0302 16
> +pre_pll_clk_div 0x0304 16
> +#vt_pre_pll_clk_div 0x0304 16
> +pll_multiplier 0x0306 16
> +#vt_pll_multiplier 0x0306 16
> +op_pix_clk_div 0x0308 16
> +op_sys_clk_div 0x030a 16
> +op_pre_pll_clk_div 0x030c 16
> +op_pll_multiplier 0x031e 16
> +pll_mode 0x0310 8
> +- f 0 0
> +- e single 0
> +- e dual 1
> +op_pix_clk_div_rev 0x0312 16 v1.1
> +op_sys_clk_div_rev 0x0314 16 v1.1
> +
> +# frame timing registers
> +frame_length_lines 0x0340 16
> +line_length_pck 0x0342 16
> +
> +# image size registers
> +x_addr_start 0x0344 16
> +y_addr_start 0x0346 16
> +x_addr_end 0x0348 16
> +y_addr_end 0x034a 16
> +x_output_size 0x034c 16
> +y_output_size 0x034e 16
> +
> +# timing mode registers
> +Frame_length_ctrl 0x0350 8
> +- b automatic 0
> +Timing_mode_ctrl 0x0352 8
> +- b manual_readout 0
> +- b delayed_exposure 1
> +Start_readout_rs 0x0353 8
> +- b manual_readout_start 0
> +Frame_margin 0x0354 16
> +
> +# sub-sampling registers
> +x_even_inc 0x0380 16
> +x_odd_inc 0x0382 16
> +y_even_inc 0x0384 16
> +y_odd_inc 0x0386 16
> +
> +# monochrome readout registers
> +monochrome_en 0x0390 v1.1
> +- e enabled 0
> +
> +# image scaling registers
> +Scaling_mode 0x0400 16
> +- e no_scaling 0
> +- e horizontal 1
> +scale_m 0x0404 16
> +scale_n 0x0406 16
> +digital_crop_x_offset 0x0408 16
> +digital_crop_y_offset 0x040a 16
> +digital_crop_image_width 0x040c 16
> +digital_crop_image_height 0x040e 16
> +
> +# image compression registers
> +compression_mode 0x0500 16
> +- e none 0
> +- e dpcm_pcm_simple 1
> +
> +# test pattern registers
> +test_pattern_mode 0x0600 16
> +- e none 0
> +- e solid_color 1
> +- e color_bars 2
> +- e fade_to_grey 3
> +- e pn9 4
> +- e color_tile 5
> +test_data_red 0x0602 16
> +test_data_greenR 0x0604 16
> +test_data_blue 0x0606 16
> +test_data_greenB 0x0608 16
> +value_step_size_smooth 0x060a 8
> +value_step_size_quantised 0x060b 8
> +
> +# phy configuration registers
> +tclk_post 0x0800 8
> +ths_prepare 0x0801 8
> +ths_zero_min 0x0802 8
> +ths_trail 0x0803 8
> +tclk_trail_min 0x0804 8
> +tclk_prepare 0x0805 8
> +tclk_zero 0x0806 8
> +tlpx 0x0807 8
> +phy_ctrl 0x0808 8
> +- e auto 0
> +- e UI 1
> +- e manual 2
> +tclk_post_ex 0x080a 16
> +ths_prepare_ex 0x080c 16
> +ths_zero_min_ex 0x080e 16
> +ths_trail_ex 0x0810 16
> +tclk_trail_min_ex 0x0812 16
> +tclk_prepare_ex 0x0814 16
> +tclk_zero_ex 0x0816 16
> +tlpx_ex 0x0818 16
> +
> +# link rate register
> +requested_link_rate 0x0820 32 u16.16
> +
> +# equalization control registers
> +DPHY_equalization_mode 0x0824 8 v1.1
> +- b eq2 0
> +PHY_equalization_ctrl 0x0825 8 v1.1
> +- b enable 0
> +
> +# d-phy preamble control registers
> +DPHY_preamble_ctrl 0x0826 8 v1.1
> +- b enable 0
> +DPHY_preamble_length 0x0826 8 v1.1
> +
> +# d-phy spread spectrum control registers
> +PHY_SSC_ctrl 0x0828 8 v1.1
> +- b enable 0
> +
> +# manual lp control register
> +manual_LP_ctrl 0x0829 8 v1.1
> +- b enable 0
> +
> +# additional phy configuration registers
> +twakeup 0x082a v1.1
> +tinit 0x082b v1.1
> +ths_exit 0x082c v1.1
> +ths_exit_ex 0x082e 16 v1.1
> +
> +# phy calibration configuration registers
> +PHY_periodic_calibration_ctrl 0x0830 8
> +- b frame_blanking 0
> +PHY_periodic_calibration_interval 0x0831 8
> +PHY_init_calibration_ctrl 0x0832 8
> +- b stream_start 0
> +DPHY_calibration_mode 0x0833 8 v1.1
> +- b also_alternate 0
> +CPHY_calibration_mode 0x0834 8 v1.1
> +- e format_1 0
> +- e format_2 1
> +- e format_3 2
> +t3_calpreamble_length 0x0835 8 v1.1
> +t3_calpreamble_length_per 0x0836 8 v1.1
> +t3_calaltseq_length 0x0837 8 v1.1
> +t3_calaltseq_length_per 0x0838 8 v1.1
> +FM2_init_seed 0x083a 16 v1.1
> +t3_caludefseq_length 0x083c 16 v1.1
> +t3_caludefseq_length_per 0x083e 16 v1.1
> +
> +# c-phy manual control registers
> +TGR_Preamble_Length 0x0841 8
> +- b preamable_prog_seq 7
> +- f begin_preamble_length 0 5
> +TGR_Post_Length 0x0842 8
> +- f post_length 0 4
> +TGR_Preamble_Prog_Sequence(n2) 0x0843
> +- l n2 0 6 1
> +- f symbol_n_1 3 5
> +- f symbol_n 0 2
> +t3_prepare 0x084e 16
> +t3_lpx 0x0850 16
> +
> +# alps control register
> +ALPS_ctrl 0x085a 8
> +- b lvlp_dphy 0
> +- b lvlp_cphy 1
> +- b alp_cphy 2
> +
> +# lrte control registers
> +TX_REG_CSI_EPD_EN_SSP_cphy 0x0860 16
> +TX_REG_CSI_EPD_OP_SLP_cphy 0x0862 16
> +TX_REG_CSI_EPD_EN_SSP_dphy 0x0864 16
> +TX_REG_CSI_EPD_OP_SLP_dphy 0x0866 16
> +TX_REG_CSI_EPD_MISC_OPTION_cphy 0x0868 v1.1
> +TX_REG_CSI_EPD_MISC_OPTION_dphy 0x0869 v1.1
> +
> +# scrambling control registers
> +Scrambling_ctrl 0x0870
> +- b enabled 0
> +- f 2 3
> +- e 1_seed_cphy 0
> +- e 4_seed_cphy 3
> +lane_seed_value(seed, lane) 0x0872 16
> +- l seed 0 3 0x10
> +- l lane 0 7 0x2
> +
> +# usl control registers
> +TX_USL_REV_ENTRY 0x08c0 16 v1.1
> +TX_USL_REV_Clock_Counter 0x08c2 16 v1.1
> +TX_USL_REV_LP_Counter 0x08c4 16 v1.1
> +TX_USL_REV_Frame_Counter 0x08c6 16 v1.1
> +TX_USL_REV_Chronological_Timer 0x08c8 16 v1.1
> +TX_USL_FWD_ENTRY 0x08ca 16 v1.1
> +TX_USL_GPIO 0x08cc 16 v1.1
> +TX_USL_Operation 0x08ce 16 v1.1
> +- b reset 0
> +TX_USL_ALP_ctrl 0x08d0 16 v1.1
> +- b clock_pause 0
> +TX_USL_APP_BTA_ACK_TIMEOUT 0x08d2 16 v1.1
> +TX_USL_SNS_BTA_ACK_TIMEOUT 0x08d2 16 v1.1
> +USL_Clock_Mode_d_ctrl 0x08d2 v1.1
> +- b cont_clock_standby 0
> +- b cont_clock_vblank 1
> +- b cont_clock_hblank 2
> +
> +# binning configuration registers
> +binning_mode 0x0900 8
> +binning_type 0x0901 8
> +binning_weighting 0x0902 8
> +
> +# data transfer interface registers
> +data_transfer_if_1_ctrl 0x0a00 8
> +- b enable 0
> +- b write 1
> +- b clear_error 2
> +data_transfer_if_1_status 0x0a01 8
> +- b read_if_ready 0
> +- b write_if_ready 1
> +- b data_corrupted 2
> +- b improper_if_usage 3
> +data_transfer_if_1_page_select 0x0a02 8
> +data_transfer_if_1_data(p) 0x0a04 8 f
> +- l p 0 63 1
> +
> +# image processing and sensor correction configuration registers
> +shading_correction_en 0x0b00 8
> +- b enable 0
> +luminance_correction_level 0x0b01 8
> +green_imbalance_filter_en 0x0b02 8
> +- b enable 0
> +mapped_defect_correct_en 0x0b05 8
> +- b enable 0
> +single_defect_correct_en 0x0b06 8
> +- b enable 0
> +dynamic_couplet_correct_en 0x0b08 8
> +- b enable 0
> +combined_defect_correct_en 0x0b0a 8
> +- b enable 0
> +module_specific_correction_en 0x0b0c 8
> +- b enable 0
> +dynamic_triplet_defect_correct_en 0x0b13 8
> +- b enable 0
> +NF_ctrl 0x0b15 8
> +- b luma 0
> +- b chroma 1
> +- b combined 2
> +
> +# optical black pixel readout registers
> +OB_readout_control 0x0b30 8
> +- b enable 0
> +- b interleaving 1
> +OB_virtual_channel 0x0b31 8
> +OB_DT 0x0b32 8
> +OB_data_format 0x0b33 8
> +
> +# color temperature feedback registers
> +color_temperature 0x0b8c 16
> +absolute_gain_greenr 0x0b8e 16
> +absolute_gain_red 0x0b90 16
> +absolute_gain_blue 0x0b92 16
> +absolute_gain_greenb 0x0b94 16
> +
> +# cfa conversion registers
> +CFA_conversion_ctrl 0x0ba0 v1.1
> +- b bayer_conversion_enable 0
> +
> +# flash strobe and sa strobe control registers
> +flash_strobe_adjustment 0x0c12 8
> +flash_strobe_start_point 0x0c14 16
> +tflash_strobe_delay_rs_ctrl 0x0c16 16
> +tflash_strobe_width_high_rs_ctrl 0x0c18 16
> +flash_mode_rs 0x0c1a 8
> +- b continuous 0
> +- b truncate 1
> +- b async 3
> +flash_trigger_rs 0x0c1b 8
> +flash_status 0x0c1c 8
> +- b retimed 0
> +sa_strobe_mode 0x0c1d 8
> +- b continuous 0
> +- b truncate 1
> +- b async 3
> +- b adjust_edge 4
> +sa_strobe_start_point 0x0c1e 16
> +tsa_strobe_delay_ctrl 0x0c20 16
> +tsa_strobe_width_ctrl 0x0c22 16
> +sa_strobe_trigger 0x0c24 8
> +sa_strobe_status 0x0c25 8
> +- b retimed 0
> +tSA_strobe_re_delay_ctrl 0x0c30 16
> +tSA_strobe_fe_delay_ctrl 0x0c32 16
> +
> +# pdaf control registers
> +PDAF_ctrl 0x0d00 16
> +- b enable 0
> +- b processed 1
> +- b interleaved 2
> +- b visible_pdaf_correction 3
> +PDAF_VC 0x0d02 8
> +PDAF_DT 0x0d03 8
> +pd_x_addr_start 0x0d04 16
> +pd_y_addr_start 0x0d06 16
> +pd_x_addr_end 0x0d08 16
> +pd_y_addr_end 0x0d0a 16
> +
> +# bracketing interface configuration registers
> +bracketing_LUT_ctrl 0x0e00 8
> +bracketing_LUT_mode 0x0e01 8
> +- b continue_streaming 0
> +- b loop_mode 1
> +bracketing_LUT_entry_ctrl 0x0e02 8
> +bracketing_LUT_frame(n) 0x0e10 v1.1 f
> +- l n 0 0xef 1
> +
> +# integration time and gain parameter limit registers
> +integration_time_capability 0x1000 16
> +- b fine 0
> +coarse_integration_time_min 0x1004 16
> +coarse_integration_time_max_margin 0x1006 16
> +fine_integration_time_min 0x1008 16
> +fine_integration_time_max_margin 0x100a 16
> +
> +# digital gain parameter limit registers
> +digital_gain_capability 0x1081
> +- e none 0
> +- e global 2
> +digital_gain_min 0x1084 16
> +digital_gain_max 0x1086 16
> +digital_gain_step_size 0x1088 16
> +
> +# data pedestal capability registers
> +Pedestal_capability 0x10e0 8 v1.1
> +
> +# adc capability registers
> +ADC_capability 0x10f0 8
> +- b bit_depth_ctrl 0
> +ADC_bit_depth_capability 0x10f4 32 v1.1
> +
> +# video timing parameter limit registers
> +min_ext_clk_freq_mhz 0x1100 32 float_ireal
> +max_ext_clk_freq_mhz 0x1104 32 float_ireal
> +min_pre_pll_clk_div 0x1108 16
> +# min_vt_pre_pll_clk_div 0x1108 16
> +max_pre_pll_clk_div 0x110a 16
> +# max_vt_pre_pll_clk_div 0x110a 16
> +min_pll_ip_clk_freq_mhz 0x110c 32 float_ireal
> +# min_vt_pll_ip_clk_freq_mhz 0x110c 32 float_ireal
> +max_pll_ip_clk_freq_mhz 0x1110 32 float_ireal
> +# max_vt_pll_ip_clk_freq_mhz 0x1110 32 float_ireal
> +min_pll_multiplier 0x1114 16
> +# min_vt_pll_multiplier 0x1114 16
> +max_pll_multiplier 0x1116 16
> +# max_vt_pll_multiplier 0x1116 16
> +min_pll_op_clk_freq_mhz 0x1118 32 float_ireal
> +max_pll_op_clk_freq_mhz 0x111c 32 float_ireal
> +
> +# video timing set-up capability registers
> +min_vt_sys_clk_div 0x1120 16
> +max_vt_sys_clk_div 0x1122 16
> +min_vt_sys_clk_freq_mhz 0x1124 32 float_ireal
> +max_vt_sys_clk_freq_mhz 0x1128 32 float_ireal
> +min_vt_pix_clk_freq_mhz 0x112c 32 float_ireal
> +max_vt_pix_clk_freq_mhz 0x1130 32 float_ireal
> +min_vt_pix_clk_div 0x1134 16
> +max_vt_pix_clk_div 0x1136 16
> +clock_calculation 0x1138
> +- b lane_speed 0
> +- b link_decoupled 1
> +- b dual_pll_op_sys_ddr 2
> +- b dual_pll_op_pix_ddr 3
> +num_of_vt_lanes 0x1139
> +num_of_op_lanes 0x113a
> +op_bits_per_lane 0x113b 8 v1.1
> +
> +# frame timing parameter limits
> +min_frame_length_lines 0x1140 16
> +max_frame_length_lines 0x1142 16
> +min_line_length_pck 0x1144 16
> +max_line_length_pck 0x1146 16
> +min_line_blanking_pck 0x1148 16
> +min_frame_blanking_lines 0x114a 16
> +min_line_length_pck_step_size 0x114c
> +timing_mode_capability 0x114d
> +- b auto_frame_length 0
> +- b rolling_shutter_manual_readout 2
> +- b delayed_exposure_start 3
> +- b manual_exposure_embedded_data 4
> +frame_margin_max_value 0x114e 16
> +frame_margin_min_value 0x1150
> +gain_delay_type 0x1151
> +- e fixed 0
> +- e variable 1
> +
> +# output clock set-up capability registers
> +min_op_sys_clk_div 0x1160 16
> +max_op_sys_clk_div 0x1162 16
> +min_op_sys_clk_freq_mhz 0x1164 32 float_ireal
> +max_op_sys_clk_freq_mhz 0x1168 32 float_ireal
> +min_op_pix_clk_div 0x116c 16
> +max_op_pix_clk_div 0x116e 16
> +min_op_pix_clk_freq_mhz 0x1170 32 float_ireal
> +max_op_pix_clk_freq_mhz 0x1174 32 float_ireal
> +
> +# image size parameter limit registers
> +x_addr_min 0x1180 16
> +y_addr_min 0x1182 16
> +x_addr_max 0x1184 16
> +y_addr_max 0x1186 16
> +min_x_output_size 0x1188 16
> +min_y_output_size 0x118a 16
> +max_x_output_size 0x118c 16
> +max_y_output_size 0x118e 16
> +
> +x_addr_start_div_constant 0x1190 v1.1
> +y_addr_start_div_constant 0x1191 v1.1
> +x_addr_end_div_constant 0x1192 v1.1
> +y_addr_end_div_constant 0x1193 v1.1
> +x_size_div 0x1194 v1.1
> +y_size_div 0x1195 v1.1
> +x_output_div 0x1196 v1.1
> +y_output_div 0x1197 v1.1
> +non_flexible_resolution_support 0x1198 v1.1
> +- b new_pix_addr 0
> +- b new_output_res 1
> +- b output_crop_no_pad 2
> +- b output_size_lane_dep 3
> +
> +min_op_pre_pll_clk_div 0x11a0 16
> +max_op_pre_pll_clk_div 0x11a2 16
> +min_op_pll_ip_clk_freq_mhz 0x11a4 32 float_ireal
> +max_op_pll_ip_clk_freq_mhz 0x11a8 32 float_ireal
> +min_op_pll_multiplier 0x11ac 16
> +max_op_pll_multiplier 0x11ae 16
> +min_op_pll_op_clk_freq_mhz 0x11b0 32 float_ireal
> +max_op_pll_op_clk_freq_mhz 0x11b4 32 float_ireal
> +clock_tree_pll_capability 0x11b8 8
> +- b dual_pll 0
> +- b single_pll 1
> +- b ext_divider 2
> +- b flexible_op_pix_clk_div 3
> +clock_capa_type_capability 0x11b9 v1.1
> +- b ireal 0
> +
> +# sub-sampling parameters limit registers
> +min_even_inc 0x11c0 16
> +min_odd_inc 0x11c2 16
> +max_even_inc 0x11c4 16
> +max_odd_inc 0x11c6 16
> +aux_subsamp_capability 0x11c8 v1.1
> +- b factor_power_of_2 1
> +aux_subsamp_mono_capability 0x11c9 v1.1
> +- b factor_power_of_2 1
> +monochrome_capability 0x11ca v1.1
> +- e inc_odd 0
> +- e inc_even 1
> +pixel_readout_capability 0x11cb v1.1
> +- e bayer 0
> +- e monochrome 1
> +- e bayer_and_mono 2
> +min_even_inc_mono 0x11cc 16 v1.1
> +max_even_inc_mono 0x11ce 16 v1.1
> +min_odd_inc_mono 0x11d0 16 v1.1
> +max_odd_inc_mono 0x11d2 16 v1.1
> +min_even_inc_bc2 0x11d4 16 v1.1
> +max_even_inc_bc2 0x11d6 16 v1.1
> +min_odd_inc_bc2 0x11d8 16 v1.1
> +max_odd_inc_bc2 0x11da 16 v1.1
> +min_even_inc_mono_bc2 0x11dc 16 v1.1
> +max_even_inc_mono_bc2 0x11de 16 v1.1
> +min_odd_inc_mono_bc2 0x11f0 16 v1.1
> +max_odd_inc_mono_bc2 0x11f2 16 v1.1
> +
> +# image scaling limit parameters
> +scaling_capability 0x1200 16
> +- e none 0
> +- e horizontal 1
> +- e reserved 2
> +scaler_m_min 0x1204 16
> +scaler_m_max 0x1206 16
> +scaler_n_min 0x1208 16
> +scaler_n_max 0x120a 16
> +digital_crop_capability 0x120e
> +- e none 0
> +- e input_crop 1
> +
> +# hdr limit registers
> +hdr_capability_1 0x1210
> +- b 2x2_binning 0
> +- b combined_analog_gain 1
> +- b separate_analog_gain 2
> +- b upscaling 3
> +- b reset_sync 4
> +- b direct_short_exp_timing 5
> +- b direct_short_exp_synthesis 6
> +min_hdr_bit_depth 0x1211
> +hdr_resolution_sub_types 0x1212
> +hdr_resolution_sub_type(n) 0x1213
> +- l n 0 1 1
> +- f row 0 3
> +- f column 4 7
> +hdr_capability_2 0x121b
> +- b combined_digital_gain 0
> +- b separate_digital_gain 1
> +- b timing_mode 3
> +- b synthesis_mode 4
> +max_hdr_bit_depth 0x121c
> +
> +# usl capability register
> +usl_support_capability 0x1230 v1.1
> +- b clock_tree 0
> +- b rev_clock_tree 1
> +- b rev_clock_calc 2
> +usl_clock_mode_d_capability 0x1231 v1.1
> +- b cont_clock_standby 0
> +- b cont_clock_vblank 1
> +- b cont_clock_hblank 2
> +- b noncont_clock_standby 3
> +- b noncont_clock_vblank 4
> +- b noncont_clock_hblank 5
> +min_op_sys_clk_div_rev 0x1234 v1.1
> +max_op_sys_clk_div_rev 0x1236 v1.1
> +min_op_pix_clk_div_rev 0x1238 v1.1
> +max_op_pix_clk_div_rev 0x123a v1.1
> +min_op_sys_clk_freq_rev_mhz 0x123c 32 v1.1 float_ireal
> +max_op_sys_clk_freq_rev_mhz 0x1240 32 v1.1 float_ireal
> +min_op_pix_clk_freq_rev_mhz 0x1244 32 v1.1 float_ireal
> +max_op_pix_clk_freq_rev_mhz 0x1248 32 v1.1 float_ireal
> +max_bitrate_rev_d_mode_mbps 0x124c 32 v1.1 ireal
> +max_symrate_rev_c_mode_msps 0x1250 32 v1.1 ireal
> +
> +# image compression capability registers
> +compression_capability 0x1300
> +- b dpcm_pcm_simple 0
> +
> +# test mode capability registers
> +test_mode_capability 0x1310 16
> +- b solid_color 0
> +- b color_bars 1
> +- b fade_to_grey 2
> +- b pn9 3
> +- b color_tile 5
> +pn9_data_format1 0x1312
> +pn9_data_format2 0x1313
> +pn9_data_format3 0x1314
> +pn9_data_format4 0x1315
> +pn9_misc_capability 0x1316
> +- f num_pixels 0 2
> +- b compression 3
> +test_pattern_capability 0x1317 v1.1
> +- b no_repeat 1
> +pattern_size_div_m1 0x1318 v1.1
> +
> +# fifo capability registers
> +fifo_support_capability 0x1502
> +- e none 0
> +- e derating 1
> +- e derating_overrating 2
> +
> +# csi-2 capability registers
> +phy_ctrl_capability 0x1600
> +- b auto_phy_ctl 0
> +- b ui_phy_ctl 1
> +- b dphy_time_ui_reg_1_ctl 2
> +- b dphy_time_ui_reg_2_ctl 3
> +- b dphy_time_ctl 4
> +- b dphy_ext_time_ui_reg_1_ctl 5
> +- b dphy_ext_time_ui_reg_2_ctl 6
> +- b dphy_ext_time_ctl 7
> +csi_dphy_lane_mode_capability 0x1601
> +- b 1_lane 0
> +- b 2_lane 1
> +- b 3_lane 2
> +- b 4_lane 3
> +- b 5_lane 4
> +- b 6_lane 5
> +- b 7_lane 6
> +- b 8_lane 7
> +csi_signaling_mode_capability 0x1602
> +- b csi_dphy 2
> +- b csi_cphy 3
> +fast_standby_capability 0x1603
> +- e no_frame_truncation 0
> +- e frame_truncation 1
> +csi_address_control_capability 0x1604
> +- b cci_addr_change 0
> +- b 2nd_cci_addr 1
> +- b sw_changeable_2nd_cci_addr 2
> +data_type_capability 0x1605
> +- b dpcm_programmable 0
> +- b bottom_embedded_dt_programmable 1
> +- b bottom_embedded_vc_programmable 2
> +- b ext_vc_range 3
> +csi_cphy_lane_mode_capability 0x1606
> +- b 1_lane 0
> +- b 2_lane 1
> +- b 3_lane 2
> +- b 4_lane 3
> +- b 5_lane 4
> +- b 6_lane 5
> +- b 7_lane 6
> +- b 8_lane 7
> +emb_data_capability 0x1607 v1.1
> +- b two_bytes_per_raw16 0
> +- b two_bytes_per_raw20 1
> +- b two_bytes_per_raw24 2
> +- b no_one_byte_per_raw16 3
> +- b no_one_byte_per_raw20 4
> +- b no_one_byte_per_raw24 5
> +max_per_lane_bitrate_lane_d_mode_mbps(n) 0x1608 32 ireal
> +- l n 0 7 4 4,0x32
> +temp_sensor_capability 0x1618
> +- b supported 0
> +- b CCS_format 1
> +- b reset_0x80 2
> +max_per_lane_bitrate_lane_c_mode_mbps(n) 0x161a 32 ireal
> +- l n 0 7 4 4,0x30
> +dphy_equalization_capability 0x162b
> +- b equalization_ctrl 0
> +- b eq1 1
> +- b eq2 2
> +cphy_equalization_capability 0x162c
> +- b equalization_ctrl 0
> +dphy_preamble_capability 0x162d
> +- b preamble_seq_ctrl 0
> +dphy_ssc_capability 0x162e
> +- b supported 0
> +cphy_calibration_capability 0x162f
> +- b manual 0
> +- b manual_streaming 1
> +- b format_1_ctrl 2
> +- b format_2_ctrl 3
> +- b format_3_ctrl 4
> +dphy_calibration_capability 0x1630
> +- b manual 0
> +- b manual_streaming 1
> +- b alternate_seq 2
> +phy_ctrl_capability_2 0x1631
> +- b tgr_length 0
> +- b tgr_preamble_prog_seq 1
> +- b extra_cphy_manual_timing 2
> +- b clock_based_manual_cdphy 3
> +- b clock_based_manual_dphy 4
> +- b clock_based_manual_cphy 5
> +- b manual_lp_dphy 6
> +- b manual_lp_cphy 7
> +lrte_cphy_capability 0x1632
> +- b pdq_short 0
> +- b spacer_short 1
> +- b pdq_long 2
> +- b spacer_long 3
> +- b spacer_no_pdq 4
> +lrte_dphy_capability 0x1633
> +- b pdq_short_opt1 0
> +- b spacer_short_opt1 1
> +- b pdq_long_opt1 2
> +- b spacer_long_opt1 3
> +- b spacer_short_opt2 4
> +- b spacer_long_opt2 5
> +- b spacer_no_pdq_opt1 6
> +- b spacer_variable_opt2 7
> +alps_capability_dphy 0x1634
> +- e lvlp_not_supported 0 0x3
> +- e lvlp_supported 1 0x3
> +- e controllable_lvlp 2 0x3
> +alps_capability_cphy 0x1635
> +- e lvlp_not_supported 0 0x3
> +- e lvlp_supported 1 0x3
> +- e controllable_lvlp 2 0x3
> +- e alp_not_supported 0xc 0xc
> +- e alp_supported 0xd 0xc
> +- e controllable_alp 0xe 0xc
> +scrambling_capability 0x1636
> +- b scrambling_supported 0
> +- f max_seeds_per_lane_c 1 2
> +- e 1 0
> +- e 4 3
> +- f num_seed_regs 3 5
> +- e 0 0
> +- e 1 1
> +- e 4 4
> +- b num_seed_per_lane 6
> +dphy_manual_constant 0x1637
> +cphy_manual_constant 0x1638
> +CSI2_interface_capability_misc 0x1639 v1.1
> +- b eotp_short_pkt_opt2 0
> +PHY_ctrl_capability_3 0x165c v1.1
> +- b dphy_timing_not_multiple 0
> +- b dphy_min_timing_value_1 1
> +- b twakeup_supported 2
> +- b tinit_supported 3
> +- b ths_exit_supported 4
> +- b cphy_timing_not_multiple 5
> +- b cphy_min_timing_value_1 6
> +dphy_sf 0x165d v1.1
> +cphy_sf 0x165e v1.1
> +- f twakeup 0 3
> +- f tinit 4 7
> +dphy_limits_1 0x165f v1.1
> +- f ths_prepare 0 3
> +- f ths_zero 4 7
> +dphy_limits_2 0x1660 v1.1
> +- f ths_trail 0 3
> +- f tclk_trail_min 4 7
> +dphy_limits_3 0x1661 v1.1
> +- f tclk_prepare 0 3
> +- f tclk_zero 4 7
> +dphy_limits_4 0x1662 v1.1
> +- f tclk_post 0 3
> +- f tlpx 4 7
> +dphy_limits_5 0x1663 v1.1
> +- f ths_exit 0 3
> +- f twakeup 4 7
> +dphy_limits_6 0x1664 v1.1
> +- f tinit 0 3
> +cphy_limits_1 0x1665 v1.1
> +- f t3_prepare_max 0 3
> +- f t3_lpx_max 4 7
> +cphy_limits_2 0x1666 v1.1
> +- f ths_exit_max 0 3
> +- f twakeup_max 4 7
> +cphy_limits_3 0x1667 v1.1
> +- f tinit_max 0 3
> +
> +# binning capability registers
> +min_frame_length_lines_bin 0x1700 16
> +max_frame_length_lines_bin 0x1702 16
> +min_line_length_pck_bin 0x1704 16
> +max_line_length_pck_bin 0x1706 16
> +min_line_blanking_pck_bin 0x1708 16
> +fine_integration_time_min_bin 0x170a 16
> +fine_integration_time_max_margin_bin 0x170c 16
> +binning_capability 0x1710
> +- e unsupported 0
> +- e binning_then_subsampling 1
> +- e subsampling_then_binning 2
> +binning_weighting_capability 0x1711
> +- b averaged 0
> +- b summed 1
> +- b bayer_corrected 2
> +- b module_specific_weight 3
> +binning_sub_types 0x1712
> +binning_sub_type(n) 0x1713
> +- l n 0 63 1
> +- f row 0 3
> +- f column 4 7
> +binning_weighting_mono_capability 0x1771 v1.1
> +- b averaged 0
> +- b summed 1
> +- b bayer_corrected 2
> +- b module_specific_weight 3
> +binning_sub_types_mono 0x1772 v1.1
> +binning_sub_type_mono(n) 0x1773 v1.1 f
> +- l n 0 63 1
> +
> +# data transfer interface capability registers
> +data_transfer_if_capability 0x1800
> +- b supported 0
> +- b polling 2
> +
> +# sensor correction capability registers
> +shading_correction_capability 0x1900
> +- b color_shading 0
> +- b luminance_correction 1
> +green_imbalance_capability 0x1901
> +- b supported 0
> +module_specific_correction_capability 0x1903
> +defect_correction_capability 0x1904 16
> +- b mapped_defect 0
> +- b dynamic_couplet 2
> +- b dynamic_single 5
> +- b combined_dynamic 8
> +defect_correction_capability_2 0x1906 16
> +- b dynamic_triplet 3
> +nf_capability 0x1908
> +- b luma 0
> +- b chroma 1
> +- b combined 2
> +
> +# optical black readout capability registers
> +ob_readout_capability 0x1980
> +- b controllable_readout 0
> +- b visible_pixel_readout 1
> +- b different_vc_readout 2
> +- b different_dt_readout 3
> +- b prog_data_format 4
> +
> +# color feedback capability registers
> +color_feedback_capability 0x1987
> +- b kelvin 0
> +- b awb_gain 1
> +
> +# cfa pattern capability registers
> +CFA_pattern_capability 0x1990 v1.1
> +- e bayer 0
> +- e monochrome 1
> +- e 4x4_quad_bayer 2
> +- e vendor_specific 3
> +CFA_pattern_conversion_capability 0x1991 v1.1
> +- b bayer 0
> +
> +# timer capability registers
> +flash_mode_capability 0x1a02
> +- b single_strobe 0
> +sa_strobe_mode_capability 0x1a03
> +- b fixed_width 0
> +- b edge_ctrl 1
> +
> +# soft reset capability registers
> +reset_max_delay 0x1a10 v1.1
> +reset_min_time 0x1a11 v1.1
> +
> +# pdaf capability registers
> +pdaf_capability_1 0x1b80
> +- b supported 0
> +- b processed_bottom_embedded 1
> +- b processed_interleaved 2
> +- b raw_bottom_embedded 3
> +- b raw_interleaved 4
> +- b visible_pdaf_correction 5
> +- b vc_interleaving 6
> +- b dt_interleaving 7
> +pdaf_capability_2 0x1b81
> +- b ROI 0
> +- b after_digital_crop 1
> +- b ctrl_retimed 2
> +
> +# bracketing interface capability registers
> +bracketing_lut_capability_1 0x1c00
> +- b coarse_integration 0
> +- b global_analog_gain 1
> +- b flash 4
> +- b global_digital_gain 5
> +- b alternate_global_analog_gain 6
> +bracketing_lut_capability_2 0x1c01
> +- b single_bracketing_mode 0
> +- b looped_bracketing_mode 1
> +bracketing_lut_size 0x1c02
> diff --git a/drivers/media/i2c/smiapp/mk-ccs-regs b/drivers/media/i2c/smiapp/mk-ccs-regs
> new file mode 100644
> index 000000000000..b345d4122ea2
> --- /dev/null
> +++ b/drivers/media/i2c/smiapp/mk-ccs-regs
> @@ -0,0 +1,405 @@
> +#!/usr/bin/perl -w
> +#
> +# Copyright (C) 2019--2020 Intel Corporation
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
> +
> +use Getopt::Long qw(:config no_ignore_case);
> +use File::Basename;
> +
> +my $ccsregs = "ccs-regs.txt";
> +my $header;
> +my $regarray;
> +my $limitc;
> +my $limith;
> +my $help;
> +
> +GetOptions("ccsregs|c=s" => \$ccsregs,
> + "header|e=s" => \$header,
> + "regarray|r=s" => \$regarray,
> + "limitc|l=s" => \$limitc,
> + "limith|L=s" => \$limith,
> + "help|h" => \$help) or die "can't parse options";
> +
> +$help = 1 if ! defined $header || ! defined $limitc || ! defined $limith;
> +
> +if (defined $help) {
> + print <<EOH
> +$0 - Create CCS register definitions for C
> +
> +usage: $0 -c ccs-regs.txt -h header -r regarray -l limit-c -L limit-header
> +
> + -c ccs register file
> + -e header file name
> + -r register description array file name
> + -l limit and capability array file name
> + -L limit and capability header file name
> +EOH
> + ;
> + exit 0;
> +}
> +
> +open(my $R, "< $ccsregs") or die "can't open $ccsregs";
> +
> +open(my $H, "> $header") or die "can't open $header";
> +my $A;
> +if (defined $regarray) {
> + open($A, "> $regarray") or die "can't open $regarray";
> +}
> +open(my $LC, "> $limitc") or die "can't open $limitc";
> +open(my $LH, "> $limith") or die "can't open $limith";
> +
> +my %this;
> +
> +sub is_limit_reg($) {
> + my $addr = hex $_[0];
> +
> + return 0 if $addr < 0x40; # weed out status registers
> + return 0 if $addr >= 0x100 && $addr < 0xfff; # weed out configuration registers
> +
> + return 1;
> +}
> +
> +my $uc_header = basename uc $header;
> +$uc_header =~ s/[^A-Z0-9]/_/g;
> +
> +my $copyright = "/* Copyright (C) 2019--2020 Intel Corporation */\n";
> +my $license = "SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause";
> +
> +for my $fh ($A, $LC) {
> + print $fh "// $license\n$copyright\n" if defined $fh;
> +}
> +
> +for my $fh ($H, $LH) {
> + print $fh "/* $license */\n$copyright\n";
> +}
> +
> +print $H <<EOF
> +#ifndef __${uc_header}__
> +#define __${uc_header}__
> +
> +#define CCS_FL_BASE 16
> +#define CCS_FL_16BIT (1U << CCS_FL_BASE)
> +#define CCS_FL_32BIT (1U << (CCS_FL_BASE + 1))
> +#define CCS_FL_FLOAT_IREAL (1U << (CCS_FL_BASE + 2))
> +#define CCS_FL_IREAL (1U << (CCS_FL_BASE + 3))
> +
> +#define CCS_R_ADDR(r) ((r) & 0xffff)
> +
> +EOF
> + ;
> +
> +print $A <<EOF
> +#include <stdint.h>
> +#include <stdio.h>
> +#include "ccs-extra.h"
> +#include "ccs-regs.h"
> +
> +EOF
> + if defined $A;
> +
> +my $uc_limith = basename uc $limith;
> +$uc_limith =~ s/[^A-Z0-9]/_/g;
> +
> +print $LH <<EOF
> +#ifndef __${uc_limith}__
> +#define __${uc_limith}__
> +
> +#include "ccs-os.h"
> +
> +struct ccs_limit {
> + uint32_t reg;
> + uint16_t size;
> + uint16_t flags;
> + const char *name;
> +};
> +
> +#define CCS_L_FL_SAME_REG (1U << 0)
> +
> +extern const struct ccs_limit ccs_limits[];
> +
> +EOF
> + ;
> +
> +print $LC <<EOF
> +#include "ccs-limits.h"
> +#include "ccs-regs.h"
> +
> +const struct ccs_limit ccs_limits[] = {
> +EOF
> + ;
> +
> +my $limitcount = 0;
> +my $argdescs;
> +my $reglist = "const struct ccs_reg_desc ccs_reg_desc[] = {\n";
> +
> +sub name_split($$) {
> + my ($name, $addr) = @_;
> + my $args;
> +
> + $name =~ /([^\(]+?)(\(.*)/;
> + ($name, $args) = ($1, $2);
> + $args = [split /,\s*/, $args];
> + foreach my $t (@$args) {
> + $t =~ s/[\(\)]//g;
> + $t =~ s/\//\\\//g;
> + }
> +
> + return ($name, $addr, $args);
> +}
> +
> +sub tabconv($) {
> + $_ = shift;
> +
> + my @l = split "\n", $_;
> +
> + map {
> + s/ {8,8}/\t/g;
> + s/\t\K +//;
> + } @l;
> +
> + return (join "\n", @l) . "\n";
> +}
> +
> +sub elem_size(@) {
> + my @flags = @_;
> +
> + return 2 if grep /^16$/, @flags;
> + return 4 if grep /^32$/, @flags;
> + return 1;
> +}
> +
> +sub arr_size($) {
> + my $this = $_[0];
> + my $size = $this->{elsize};
> + my $h = $this->{argparams};
> +
> + foreach my $arg (@{$this->{args}}) {
> + my $apref = $h->{$arg};
> +
> + $size *= $apref->{max} - $apref->{min} + 1;
> + }
> +
> + return $size;
> +}
> +
> +sub print_args($$$) {
> + my ($this, $postfix, $is_same_reg) = @_;
> + my ($args, $argparams, $name) =
> + ($this->{args}, $this->{argparams}, $this->{name});
> + my $varname = "ccs_reg_arg_" . (lc $name) . $postfix;
> + my @mins;
> + my @sorted_args = @{$this->{sorted_args}};
> + my $lim_arg;
> + my $size = arr_size($this);
> +
> + $argdescs .= "static const struct ccs_reg_arg " . $varname . "[] = {\n";
> +
> + foreach my $sorted_arg (@sorted_args) {
> + push @mins, $argparams->{$sorted_arg}->{min};
> + }
> +
> + foreach my $sorted_arg (@sorted_args) {
> + my $h = $argparams->{$sorted_arg};
> +
> + $argdescs .= "\t{ \"$sorted_arg\", $h->{min}, $h->{max}, $h->{elsize} },\n";
> +
> + $lim_arg .= defined $lim_arg ? ", $h->{min}" : "$h->{min}";
> + }
> +
> + $argdescs .= "};\n\n";
> +
> + $reglist .= "\t{ CCS_R_" . (uc $name) . "(" . (join ",", (@mins)) .
> + "), $size, sizeof($varname) / sizeof(*$varname)," .
> + " \"" . (lc $name) . "\", $varname },\n";
> +
> + print $LC tabconv sprintf "\t{ CCS_R_" . (uc $name) . "($lim_arg), " .
> + $size . ", " . ($is_same_reg ? "CCS_L_FL_SAME_REG" : "0") .
> + ", \"$name" . (defined $this->{discontig} ? " $lim_arg" : "") . "\" },\n"
> + if is_limit_reg $this->{base_addr};
> +}
> +
> +my $hdr_data;
> +
> +while (<$R>) {
> + chop;
> + s/^\s*//;
> + next if /^[#;]/ || /^$/;
> + if (s/^-\s*//) {
> + if (s/^b\s*//) {
> + my ($bit, $addr) = split /\t+/;
> + $bit = uc $bit;
> + $hdr_data .= sprintf "#define %-62s %s", "CCS_" . (uc ${this{name}}) ."_$bit", "(1U << $addr)\n";
> + } elsif (s/^f\s*//) {
> + s/[,\.-]/_/g;
> + my @a = split /\s+/;
> + my ($msb, $lsb, $this_field) = reverse @a;
> + @a = ( { "name" => "SHIFT", "addr" => $lsb, "fmt" => "%uU", },
> + { "name" => "MASK", "addr" => (1 << ($msb + 1)) - 1 - ((1 << $lsb) - 1), "fmt" => "0x%" . join(".", ($this{"elsize"} >> 2) x 2) . "x" } );
> + $this{"field"} = $this_field;
> + foreach my $ar (@a) {
> + #print $ar->{fmt}."\n";
> + $hdr_data .= sprintf "#define %-62s " . $ar->{"fmt"} . "\n", "CCS_" . (uc $this{"name"}) . (defined $this_field ? "_" . uc $this_field : "") . "_" . $ar->{"name"}, $ar->{"addr"} . "\n";
> + }
> + } elsif (s/^e\s*//) {
> + s/[,\.-]/_/g;
> + my ($enum, $addr) = split /\s+/;
> + $enum = uc $enum;
> + $hdr_data .= sprintf "#define %-62s %s", "CCS_" . (uc ${this{name}}) . (defined $this{"field"} ? "_" . uc $this{"field"} : "") ."_$enum", $addr . ($addr =~ /0x/i ? "" : "U") . "\n";
> + } elsif (s/^l\s*//) {
> + my ($arg, $min, $max, $elsize, @discontig) = split /\s+/;
> + my $size;
> +
> + foreach my $num ($min, $max) {
> + $num = hex $num if $num =~ /0x/i;
> + }
> +
> + $hdr_data .= sprintf "#define %-62s %s", "CCS_LIM_" . (uc ${this{name}} . "_MIN_$arg"), $min . ($min =~ /0x/i ? "" : "U") . "\n";
> + $hdr_data .= sprintf "#define %-62s %s", "CCS_LIM_" . (uc ${this{name}} . "_MAX_$arg"), $max . ($max =~ /0x/i ? "" : "U") . "\n";
> +
> + my $h = $this{argparams};
> +
> + $h->{$arg} = { "min" => $min,
> + "max" => $max,
> + "elsize" => $elsize =~ /^0x/ ? hex $elsize : $elsize,
> + "discontig" => \@discontig };
> +
> + $this{discontig} = $arg if @discontig;
> +
> + next if $#{$this{args}} + 1 != scalar keys %{$this{argparams}};
> +
> + my $reg_formula = "($this{addr}";
> + my $lim_formula;
> +
> + foreach my $arg (@{$this{args}}) {
> + my $d = $h->{$arg}->{discontig};
> + my $times = $h->{$arg}->{elsize} != 1 ?
> + " * " . $h->{$arg}->{elsize} : "";
> +
> + if (@$d) {
> + my ($lim, $offset) = split /,/, $d->[0];
> +
> + $reg_formula .= " + (($arg) < $lim ? ($arg)$times : $offset + (($arg) - $lim)$times)";
> + } else {
> + $reg_formula .= " + ($arg)$times";
> + }
> +
> + $lim_formula .= (defined $lim_formula ? " + " : "") . "($arg)$times";
> + }
> +
> + $reg_formula .= ")\n";
> + $lim_formula =~ s/^\(([a-z0-9]+)\)$/$1/i;
> +
> + print $H tabconv sprintf("#define %-62s %s", "CCS_R_" . (uc $this{name}) .
> + $this{arglist}, $reg_formula);
> +
> + print $H tabconv $hdr_data;
> + undef $hdr_data;
> +
> + # Sort arguments in descending order by size
> + @{$this{sorted_args}} = sort {
> + $h->{$a}->{elsize} <= $h->{$b}->{elsize}
> + } @{$this{args}};
> +
> + if (defined $this{discontig}) {
> + my $da = $this{argparams}->{$this{discontig}};
> + my ($first_discontig) = split /,/, $da->{discontig}->[0];
> + my $max = $da->{max};
> +
> + $da->{max} = $first_discontig - 1;
> + print_args(\%this, "", 0);
> +
> + $da->{min} = $da->{max} + 1;
> + $da->{max} = $max;
> + print_args(\%this, $first_discontig, 1);
> + } else {
> + print_args(\%this, "", 0);
> + }
> +
> + next unless is_limit_reg $this{base_addr};
> +
> + print $LH tabconv sprintf "#define %-63s%s\n",
> + "CCS_L_" . (uc $this{name}) . "_OFFSET(" .
> + (join ", ", @{$this{args}}) . ")", "($lim_formula)";
> + }
> +
> + if (! @{$this{args}}) {
> + print $H tabconv($hdr_data);
> + undef $hdr_data;
> + }
> +
> + next;
> + }
> +
> + my ($name, $addr, @flags) = split /\t+/, $_;
> + my $args = [];
> +
> + my $sp;
> +
> + ($name, $addr, $args) = name_split($name, $addr) if /\(.*\)/;
> +
> + $name =~ s/[,\.-]/_/g;
> +
> + my $flagstring = "";
> + my $size = elem_size(@flags);
> + $flagstring .= "| CCS_FL_16BIT " if $size eq "2";
> + $flagstring .= "| CCS_FL_32BIT " if $size eq "4";
> + $flagstring .= "| CCS_FL_FLOAT_IREAL " if grep /^float_ireal$/, @flags;
> + $flagstring .= "| CCS_FL_IREAL " if grep /^ireal$/, @flags;
> + $flagstring =~ s/^\| //;
> + $flagstring =~ s/ $//;
> + $flagstring = "($flagstring)" if $flagstring =~ /\|/;
> + my $base_addr = $addr;
> + $addr = "($addr | $flagstring)" if $flagstring ne "";
> +
> + my $arglist = @$args ? "(" . (join ", ", @$args) . ")" : "";
> + $hdr_data .= sprintf "#define %-62s %s\n", "CCS_R_" . (uc $name), $addr
> + if !@$args;
> +
> + $name =~ s/\(.*//;
> +
> + %this = ( name => $name,
> + addr => $addr,
> + base_addr => $base_addr,
> + argparams => {},
> + args => $args,
> + arglist => $arglist,
> + elsize => $size,
> + );
> +
> + if (!@$args) {
> + $reglist .= "\t{ CCS_R_" . (uc $name) . ", 1, 0, \"" . (lc $name) . "\", NULL },\n";
> + print $H tabconv $hdr_data;
> + undef $hdr_data;
> +
> + print $LC tabconv sprintf "\t{ CCS_R_" . (uc $name) . ", " .
> + $this{elsize} . ", 0, \"$name\" },\n"
> + if is_limit_reg $this{base_addr};
> + }
> +
> + print $LH tabconv sprintf "#define %-63s%s\n",
> + "CCS_L_" . (uc $this{name}), $limitcount++
> + if is_limit_reg $this{base_addr};
> +}
> +
> +if (defined $A) {
> + print $A $argdescs, $reglist;
> +
> + print $A "\t{ 0 }\n";
> +
> + print $A "};\n";
> +}
> +
> +print $H "\n#endif /* __${uc_header}__ */\n";
> +
> +print $LH tabconv sprintf "#define %-63s%s\n", "CCS_L_LAST", $limitcount;
> +
> +print $LH "\n#endif /* __${uc_limith}__ */\n";
> +
> +print $LC "\t{ 0 } /* Guardian */\n";
> +print $LC "};\n";
> +
> +close($R);
> +close($H);
> +close($A) if defined $A;
> +close($LC);
> +close($LH);
Thanks,
Mauro
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 003/106] smiapp: Calculate CCS limit offsets and limit buffer size
2020-10-07 8:44 ` [PATCH v2 003/106] smiapp: Calculate CCS limit offsets and limit buffer size Sakari Ailus
@ 2020-11-05 7:43 ` Mauro Carvalho Chehab
2020-11-05 7:58 ` Mauro Carvalho Chehab
0 siblings, 1 reply; 146+ messages in thread
From: Mauro Carvalho Chehab @ 2020-11-05 7:43 UTC (permalink / raw)
To: Sakari Ailus; +Cc: linux-media
Em Wed, 7 Oct 2020 11:44:23 +0300
Sakari Ailus <sakari.ailus@linux.intel.com> escreveu:
> Calculate the limit offsets and the size of the limit buffer. CCS limits
> are read into this buffer, and the offsets are helpful in accessing the
> information in it.
>
> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> ---
> drivers/media/i2c/smiapp/smiapp-core.c | 40 +++++++++++++++++++++++++-
> 1 file changed, 39 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c
> index 105ef29152e8..47e983e9cd87 100644
> --- a/drivers/media/i2c/smiapp/smiapp-core.c
> +++ b/drivers/media/i2c/smiapp/smiapp-core.c
> @@ -27,6 +27,7 @@
> #include <media/v4l2-fwnode.h>
> #include <media/v4l2-device.h>
>
> +#include "ccs-limits.h"
> #include "smiapp.h"
>
> #define SMIAPP_ALIGN_DIM(dim, flags) \
> @@ -34,6 +35,11 @@
> ? ALIGN((dim), 2) \
> : (dim) & ~1)
>
> +struct ccs_limit_offset {
> + u16 lim;
> + u16 info;
> +} ccs_limit_offsets[CCS_L_LAST + 1];
> +
Hmm... that sounds weird.
As you're declaring the struct inside smiapp-core.c, this
should be static...
> /*
> * smiapp_module_idents - supported camera modules
> */
> @@ -3166,7 +3172,39 @@ static struct i2c_driver smiapp_i2c_driver = {
> .id_table = smiapp_id_table,
> };
>
> -module_i2c_driver(smiapp_i2c_driver);
> +static int smiapp_module_init(void)
> +{
> + unsigned int i, l;
> +
> + for (i = 0, l = 0; ccs_limits[i].size && l < CCS_L_LAST; i++) {
> + if (!(ccs_limits[i].flags & CCS_L_FL_SAME_REG)) {
> + ccs_limit_offsets[l + 1].lim =
> + ALIGN(ccs_limit_offsets[l].lim +
> + ccs_limits[i].size,
> + ccs_reg_width(ccs_limits[i + 1].reg));
> + ccs_limit_offsets[l].info = i;
> + l++;
> + } else {
> + ccs_limit_offsets[l].lim += ccs_limits[i].size;
> + }
> + }
> +
> + if (WARN_ON(ccs_limits[i].size))
> + return -EINVAL;
... yet, this is the only place where this is used.
It sounds to me that you should move the var to be inside this function,
e. g. changing the above to:
struct ccs_limit_offset {
u16 lim;
u16 info;
};
static int smiapp_module_init(void)
{
struct ccs_limit_offset ccs_limit_offsets[CCS_L_LAST + 1];
unsigned int i, l;
> +
> + if (WARN_ON(l != CCS_L_LAST))
> + return -EINVAL;
> +
> + return i2c_register_driver(THIS_MODULE, &smiapp_i2c_driver);
> +}
> +
> +static void smiapp_module_cleanup(void)
> +{
> + i2c_del_driver(&smiapp_i2c_driver);
> +}
> +
> +module_init(smiapp_module_init);
> +module_exit(smiapp_module_cleanup);
>
> MODULE_AUTHOR("Sakari Ailus <sakari.ailus@iki.fi>");
> MODULE_DESCRIPTION("Generic SMIA/SMIA++ camera module driver");
Thanks,
Mauro
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 003/106] smiapp: Calculate CCS limit offsets and limit buffer size
2020-11-05 7:43 ` Mauro Carvalho Chehab
@ 2020-11-05 7:58 ` Mauro Carvalho Chehab
2020-11-05 8:01 ` Sakari Ailus
0 siblings, 1 reply; 146+ messages in thread
From: Mauro Carvalho Chehab @ 2020-11-05 7:58 UTC (permalink / raw)
To: Sakari Ailus; +Cc: linux-media
Em Thu, 5 Nov 2020 08:43:38 +0100
Mauro Carvalho Chehab <mchehab+huawei@kernel.org> escreveu:
> Em Wed, 7 Oct 2020 11:44:23 +0300
> Sakari Ailus <sakari.ailus@linux.intel.com> escreveu:
>
> > Calculate the limit offsets and the size of the limit buffer. CCS limits
> > are read into this buffer, and the offsets are helpful in accessing the
> > information in it.
> >
> > Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> > ---
> > drivers/media/i2c/smiapp/smiapp-core.c | 40 +++++++++++++++++++++++++-
> > 1 file changed, 39 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c
> > index 105ef29152e8..47e983e9cd87 100644
> > --- a/drivers/media/i2c/smiapp/smiapp-core.c
> > +++ b/drivers/media/i2c/smiapp/smiapp-core.c
> > @@ -27,6 +27,7 @@
> > #include <media/v4l2-fwnode.h>
> > #include <media/v4l2-device.h>
> >
> > +#include "ccs-limits.h"
> > #include "smiapp.h"
> >
> > #define SMIAPP_ALIGN_DIM(dim, flags) \
> > @@ -34,6 +35,11 @@
> > ? ALIGN((dim), 2) \
> > : (dim) & ~1)
> >
> > +struct ccs_limit_offset {
> > + u16 lim;
> > + u16 info;
> > +} ccs_limit_offsets[CCS_L_LAST + 1];
> > +
>
> Hmm... that sounds weird.
>
> As you're declaring the struct inside smiapp-core.c, this
> should be static...
>
> > /*
> > * smiapp_module_idents - supported camera modules
> > */
> > @@ -3166,7 +3172,39 @@ static struct i2c_driver smiapp_i2c_driver = {
> > .id_table = smiapp_id_table,
> > };
> >
> > -module_i2c_driver(smiapp_i2c_driver);
> > +static int smiapp_module_init(void)
> > +{
> > + unsigned int i, l;
> > +
> > + for (i = 0, l = 0; ccs_limits[i].size && l < CCS_L_LAST; i++) {
> > + if (!(ccs_limits[i].flags & CCS_L_FL_SAME_REG)) {
> > + ccs_limit_offsets[l + 1].lim =
> > + ALIGN(ccs_limit_offsets[l].lim +
> > + ccs_limits[i].size,
> > + ccs_reg_width(ccs_limits[i + 1].reg));
> > + ccs_limit_offsets[l].info = i;
> > + l++;
> > + } else {
> > + ccs_limit_offsets[l].lim += ccs_limits[i].size;
> > + }
> > + }
> > +
> > + if (WARN_ON(ccs_limits[i].size))
> > + return -EINVAL;
>
> ... yet, this is the only place where this is used.
>
> It sounds to me that you should move the var to be inside this function,
>
> e. g. changing the above to:
>
> struct ccs_limit_offset {
> u16 lim;
> u16 info;
> };
>
> static int smiapp_module_init(void)
> {
> struct ccs_limit_offset ccs_limit_offsets[CCS_L_LAST + 1];
> unsigned int i, l;
Ok, it sounds that you start using this on patch 007/106.
So, it sounds that you should just need to add "static" to its definition.
>
>
> > +
> > + if (WARN_ON(l != CCS_L_LAST))
> > + return -EINVAL;
> > +
> > + return i2c_register_driver(THIS_MODULE, &smiapp_i2c_driver);
> > +}
> > +
> > +static void smiapp_module_cleanup(void)
> > +{
> > + i2c_del_driver(&smiapp_i2c_driver);
> > +}
> > +
> > +module_init(smiapp_module_init);
> > +module_exit(smiapp_module_cleanup);
> >
> > MODULE_AUTHOR("Sakari Ailus <sakari.ailus@iki.fi>");
> > MODULE_DESCRIPTION("Generic SMIA/SMIA++ camera module driver");
>
>
>
> Thanks,
> Mauro
Thanks,
Mauro
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits
2020-11-05 7:19 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Mauro Carvalho Chehab
@ 2020-11-05 8:01 ` Sakari Ailus
2020-11-05 9:04 ` Mauro Carvalho Chehab
0 siblings, 1 reply; 146+ messages in thread
From: Sakari Ailus @ 2020-11-05 8:01 UTC (permalink / raw)
To: Mauro Carvalho Chehab; +Cc: linux-media
Hi Mauro,
Thank you for the review.
On Thu, Nov 05, 2020 at 08:19:50AM +0100, Mauro Carvalho Chehab wrote:
> Hi,
>
> Em Wed, 7 Oct 2020 11:44:21 +0300
> Sakari Ailus <sakari.ailus@linux.intel.com> escreveu:
>
> > Add register definitions of the MIPI CCS 1.1 standard.
> >
> > The CCS driver makes extended use of device's capability registers that
> > are dependent on CCS version. This involves having an in-memory data
> > structure for limit and capability information, creating that data
> > structure and accessing it.
> >
> > The register definitions as well as the definitions of this data structure
> > are generated from a text file using a Perl script. Do the generation here
> > and so avoid making manual, error-prone changes to the several generated
> > files.
>
> I understand the reason behind using a perl script to parse some
> text file in order to generate register's definition files,
> but I can't see what's the sense of storing the perl script and
> such texts together with the Kernel building system, re-generating them
> every time.
>
> I mean: register definitions is something that it is supposed to be
> stable, and nothing something that will change on every Kernel
> compilation.
>
> How often are you expecting changes at ccs-regs.txt?
When there's a new version of the standard, or a bug is found. At least. So
not very often.
After pushing the set to a branch in my linuxtv.org tree, I also noticed
that some architectures are built by kbuild bot without Perl interpreter
being present. This suggests that Perl is not currently universally
required for building the kernel albeit there seems to be some PowerPC
hardware (?) related driver needing it to be built.
I was thinking of putting the files produced by the script into a new patch
and leaving the script and the text file in the directory. The files would
be rebuilt when a specific environment variable is set. This would in line
with what crypto drivers are doing.
--
Kind regards,
Sakari Ailus
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 003/106] smiapp: Calculate CCS limit offsets and limit buffer size
2020-11-05 7:58 ` Mauro Carvalho Chehab
@ 2020-11-05 8:01 ` Sakari Ailus
0 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-11-05 8:01 UTC (permalink / raw)
To: Mauro Carvalho Chehab; +Cc: linux-media
Hi Mauro,
On Thu, Nov 05, 2020 at 08:58:59AM +0100, Mauro Carvalho Chehab wrote:
> > static int smiapp_module_init(void)
> > {
> > struct ccs_limit_offset ccs_limit_offsets[CCS_L_LAST + 1];
> > unsigned int i, l;
>
>
> Ok, it sounds that you start using this on patch 007/106.
>
> So, it sounds that you should just need to add "static" to its definition.
Agreed, I'll add that for v3.
--
Sakari Ailus
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits
2020-11-05 8:01 ` Sakari Ailus
@ 2020-11-05 9:04 ` Mauro Carvalho Chehab
0 siblings, 0 replies; 146+ messages in thread
From: Mauro Carvalho Chehab @ 2020-11-05 9:04 UTC (permalink / raw)
To: Sakari Ailus; +Cc: linux-media
Em Thu, 5 Nov 2020 10:01:05 +0200
Sakari Ailus <sakari.ailus@linux.intel.com> escreveu:
> Hi Mauro,
>
> Thank you for the review.
>
> On Thu, Nov 05, 2020 at 08:19:50AM +0100, Mauro Carvalho Chehab wrote:
> > Hi,
> >
> > Em Wed, 7 Oct 2020 11:44:21 +0300
> > Sakari Ailus <sakari.ailus@linux.intel.com> escreveu:
> >
> > > Add register definitions of the MIPI CCS 1.1 standard.
> > >
> > > The CCS driver makes extended use of device's capability registers that
> > > are dependent on CCS version. This involves having an in-memory data
> > > structure for limit and capability information, creating that data
> > > structure and accessing it.
> > >
> > > The register definitions as well as the definitions of this data structure
> > > are generated from a text file using a Perl script. Do the generation here
> > > and so avoid making manual, error-prone changes to the several generated
> > > files.
> >
> > I understand the reason behind using a perl script to parse some
> > text file in order to generate register's definition files,
> > but I can't see what's the sense of storing the perl script and
> > such texts together with the Kernel building system, re-generating them
> > every time.
> >
> > I mean: register definitions is something that it is supposed to be
> > stable, and nothing something that will change on every Kernel
> > compilation.
> >
> > How often are you expecting changes at ccs-regs.txt?
>
> When there's a new version of the standard, or a bug is found. At least. So
> not very often.
So, it should likely take a couple of years before any changes on it.
> After pushing the set to a branch in my linuxtv.org tree, I also noticed
> that some architectures are built by kbuild bot without Perl interpreter
> being present.
Well, kbuild bot is doing the wrong thing here: it means that it is not
testing documentation - as building it requires perl ;-)
> This suggests that Perl is not currently universally
> required for building the kernel albeit there seems to be some PowerPC
> hardware (?) related driver needing it to be built.
I doubt that Perl is a requirement for building the Kernel itself.
Adding such requirement could cause troubles on some embedded distros,
like Yocto, OpenWrt, etc, whose have a distinct toolchain that needs
to be compiled on some early step.
If this were something that would require dynamic changes on every
single compilation, it would make sense to add such extra dependency,
but this is not the case here.
> I was thinking of putting the files produced by the script into a new patch
> and leaving the script and the text file in the directory. The files would
> be rebuilt when a specific environment variable is set. This would in line
> with what crypto drivers are doing.
I would, instead, place the script and instructions about how to use
it inside Documentation/driver-api/media.
Thanks,
Mauro
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 029/106] ccs: Remove the I²C ID table
2020-10-07 8:44 ` [PATCH v2 029/106] ccs: Remove the I²C ID table Sakari Ailus
@ 2020-11-05 9:34 ` Mauro Carvalho Chehab
2020-11-18 22:15 ` Sakari Ailus
0 siblings, 1 reply; 146+ messages in thread
From: Mauro Carvalho Chehab @ 2020-11-05 9:34 UTC (permalink / raw)
To: Sakari Ailus; +Cc: linux-media
Em Wed, 7 Oct 2020 11:44:42 +0300
Sakari Ailus <sakari.ailus@linux.intel.com> escreveu:
> The I²C ID table is no longer needed; remove it.
Why not? Please provide more information.
In summary, please change the description in order to answer the
following questions:
For OF-based drivers, removing I2C probing won't cause any harm,
as the patch is keeping css_of_able, but wouldn't it affect other
drivers that could, for example, be using ACPI, instead?
Or is this driver incompatible with other probing methods?
>
> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> ---
> drivers/media/i2c/ccs/ccs-core.c | 7 -------
> 1 file changed, 7 deletions(-)
>
> diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
> index e348f55c62a6..660d5ab2c89d 100644
> --- a/drivers/media/i2c/ccs/ccs-core.c
> +++ b/drivers/media/i2c/ccs/ccs-core.c
> @@ -3244,12 +3244,6 @@ static const struct of_device_id ccs_of_table[] = {
> };
> MODULE_DEVICE_TABLE(of, ccs_of_table);
>
> -static const struct i2c_device_id ccs_id_table[] = {
> - { SMIAPP_NAME, 0 },
> - { },
> -};
> -MODULE_DEVICE_TABLE(i2c, ccs_id_table);
> -
> static const struct dev_pm_ops ccs_pm_ops = {
> SET_SYSTEM_SLEEP_PM_OPS(ccs_suspend, ccs_resume)
> SET_RUNTIME_PM_OPS(ccs_power_off, ccs_power_on, NULL)
> @@ -3263,7 +3257,6 @@ static struct i2c_driver ccs_i2c_driver = {
> },
> .probe_new = ccs_probe,
> .remove = ccs_remove,
> - .id_table = ccs_id_table,
> };
>
> static int ccs_module_init(void)
Thanks,
Mauro
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 033/106] ccs: Add CCS static data parser library
2020-10-07 8:44 ` [PATCH v2 033/106] ccs: Add CCS static data parser library Sakari Ailus
@ 2020-11-05 10:50 ` Mauro Carvalho Chehab
2020-11-05 11:18 ` Sakari Ailus
0 siblings, 1 reply; 146+ messages in thread
From: Mauro Carvalho Chehab @ 2020-11-05 10:50 UTC (permalink / raw)
To: Sakari Ailus; +Cc: linux-media
Em Wed, 7 Oct 2020 11:44:46 +0300
Sakari Ailus <sakari.ailus@linux.intel.com> escreveu:
> Add a parser library for parsing the CCS static data format.
>
> The library may be also compiled in user space as the format has uses also
> in the user space. Therefore it is dual licensed under the 3-clause BSD
> license as well.
>
> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> ---
> drivers/media/i2c/ccs/Makefile | 2 +-
> drivers/media/i2c/ccs/ccs-data-defs.h | 215 ++++++
> drivers/media/i2c/ccs/ccs-data.c | 949 ++++++++++++++++++++++++++
> drivers/media/i2c/ccs/ccs-data.h | 116 ++++
> 4 files changed, 1281 insertions(+), 1 deletion(-)
> create mode 100644 drivers/media/i2c/ccs/ccs-data-defs.h
> create mode 100644 drivers/media/i2c/ccs/ccs-data.c
> create mode 100644 drivers/media/i2c/ccs/ccs-data.h
>
> diff --git a/drivers/media/i2c/ccs/Makefile b/drivers/media/i2c/ccs/Makefile
> index 0f3d11b86dad..2f97b22460f1 100644
> --- a/drivers/media/i2c/ccs/Makefile
> +++ b/drivers/media/i2c/ccs/Makefile
> @@ -1,6 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0-only
> ccs-objs += ccs-core.o ccs-reg-access.o \
> - ccs-quirk.o ccs-limits.o
> + ccs-quirk.o ccs-limits.o ccs-data.o
> obj-$(CONFIG_VIDEO_CCS) += ccs.o
>
> ccflags-y += -I $(srctree)/drivers/media/i2c
> diff --git a/drivers/media/i2c/ccs/ccs-data-defs.h b/drivers/media/i2c/ccs/ccs-data-defs.h
> new file mode 100644
> index 000000000000..ffc5154d2c66
> --- /dev/null
> +++ b/drivers/media/i2c/ccs/ccs-data-defs.h
> @@ -0,0 +1,215 @@
> +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
> +/* Copyright 2019--2020 Intel Corporation */
> +
> +#ifndef __CCS_DATA_DEFS_H__
> +#define __CCS_DATA_DEFS_H__
> +
> +#include "ccs-data.h"
> +
> +#define CCS_STATIC_DATA_VERSION 0
> +
> +enum __ccs_data_length_specifier_id {
> + CCS_DATA_LENGTH_SPECIFIER_1 = 0,
> + CCS_DATA_LENGTH_SPECIFIER_2 = 1,
> + CCS_DATA_LENGTH_SPECIFIER_3 = 2
> +};
> +#define CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT 6
> +
> +struct __ccs_data_length_specifier {
> + uint8_t length;
> +} __attribute__((packed));
> +
> +struct __ccs_data_length_specifier2 {
> + uint8_t length[2];
> +} __attribute__((packed));
> +
> +struct __ccs_data_length_specifier3 {
> + uint8_t length[3];
> +} __attribute__((packed));
> +
> +struct __ccs_data_block {
> + uint8_t id;
> + struct __ccs_data_length_specifier length;
> +} __attribute__((packed));
> +
> +#define CCS_DATA_BLOCK_HEADER_ID_VERSION_SHIFT 5
> +
> +struct __ccs_data_block3 {
> + uint8_t id;
> + struct __ccs_data_length_specifier2 length;
> +} __attribute__((packed));
> +
> +struct __ccs_data_block4 {
> + uint8_t id;
> + struct __ccs_data_length_specifier3 length;
> +} __attribute__((packed));
> +
> +enum __ccs_data_block_id {
> + CCS_DATA_BLOCK_ID_DUMMY = 1,
> + CCS_DATA_BLOCK_ID_DATA_VERSION = 2,
> + CCS_DATA_BLOCK_ID_SENSOR_READ_ONLY_REGS = 3,
> + CCS_DATA_BLOCK_ID_MODULE_READ_ONLY_REGS = 4,
> + CCS_DATA_BLOCK_ID_SENSOR_MANUFACTURER_REGS = 5,
> + CCS_DATA_BLOCK_ID_MODULE_MANUFACTURER_REGS = 6,
> + CCS_DATA_BLOCK_ID_SENSOR_RULE_BASED_BLOCK = 32,
> + CCS_DATA_BLOCK_ID_MODULE_RULE_BASED_BLOCK = 33,
> + CCS_DATA_BLOCK_ID_SENSOR_PDAF_PIXEL_LOCATION = 36,
> + CCS_DATA_BLOCK_ID_MODULE_PDAF_PIXEL_LOCATION = 37,
> + CCS_DATA_BLOCK_ID_LICENSE = 40,
> + CCS_DATA_BLOCK_ID_END = 127,
> +};
> +
> +struct __ccs_data_block_version {
> + uint8_t static_data_version_major[2];
> + uint8_t static_data_version_minor[2];
> + uint8_t year[2];
> + uint8_t month;
> + uint8_t day;
> +} __attribute__((packed));
> +
> +struct __ccs_data_block_regs {
> + uint8_t reg_len;
> +} __attribute__((packed));
> +
> +#define CCS_DATA_BLOCK_REGS_ADDR_MASK 0x07
> +#define CCS_DATA_BLOCK_REGS_LEN_SHIFT 3
> +#define CCS_DATA_BLOCK_REGS_LEN_MASK 0x38
> +#define CCS_DATA_BLOCK_REGS_SEL_SHIFT 6
> +enum ccs_data_block_regs_sel {
> + CCS_DATA_BLOCK_REGS_SEL_REGS = 0,
> + CCS_DATA_BLOCK_REGS_SEL_REGS2 = 1,
> + CCS_DATA_BLOCK_REGS_SEL_REGS3 = 2,
> +};
> +
> +struct __ccs_data_block_regs2 {
> + uint8_t reg_len;
> + uint8_t addr;
> +} __attribute__((packed));
> +
> +#define CCS_DATA_BLOCK_REGS_2_ADDR_MASK 0x01
> +#define CCS_DATA_BLOCK_REGS_2_LEN_SHIFT 1
> +#define CCS_DATA_BLOCK_REGS_2_LEN_MASK 0x3e
> +
> +struct __ccs_data_block_regs3 {
> + uint8_t reg_len;
> + uint8_t addr[2];
> +} __attribute__((packed));
> +
> +#define CCS_DATA_BLOCK_REGS_3_LEN_MASK 0x3f
> +
> +enum __ccs_data_ffd_pixelcode {
> + CCS_DATA_BLOCK_FFD_PIXELCODE_EMBEDDED = 1,
> + CCS_DATA_BLOCK_FFD_PIXELCODE_DUMMY = 2,
> + CCS_DATA_BLOCK_FFD_PIXELCODE_BLACK = 3,
> + CCS_DATA_BLOCK_FFD_PIXELCODE_DARK = 4,
> + CCS_DATA_BLOCK_FFD_PIXELCODE_VISIBLE = 5,
> + CCS_DATA_BLOCK_FFD_PIXELCODE_MS_0 = 8,
> + CCS_DATA_BLOCK_FFD_PIXELCODE_MS_1 = 9,
> + CCS_DATA_BLOCK_FFD_PIXELCODE_MS_2 = 10,
> + CCS_DATA_BLOCK_FFD_PIXELCODE_MS_3 = 11,
> + CCS_DATA_BLOCK_FFD_PIXELCODE_MS_4 = 12,
> + CCS_DATA_BLOCK_FFD_PIXELCODE_MS_5 = 13,
> + CCS_DATA_BLOCK_FFD_PIXELCODE_MS_6 = 14,
> + CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_OB = 16,
> + CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_OB = 17,
> + CCS_DATA_BLOCK_FFD_PIXELCODE_LEFT_OB = 18,
> + CCS_DATA_BLOCK_FFD_PIXELCODE_RIGHT_OB = 19,
> + CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_LEFT_OB = 20,
> + CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_RIGHT_OB = 21,
> + CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_LEFT_OB = 22,
> + CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_RIGHT_OB = 23,
> + CCS_DATA_BLOCK_FFD_PIXELCODE_TOTAL = 24,
> + CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_PDAF = 32,
> + CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_PDAF = 33,
> + CCS_DATA_BLOCK_FFD_PIXELCODE_LEFT_PDAF = 34,
> + CCS_DATA_BLOCK_FFD_PIXELCODE_RIGHT_PDAF = 35,
> + CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_LEFT_PDAF = 36,
> + CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_RIGHT_PDAF = 37,
> + CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_LEFT_PDAF = 38,
> + CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_RIGHT_PDAF = 39,
> + CCS_DATA_BLOCK_FFD_PIXELCODE_SEPARATED_PDAF = 40,
> + CCS_DATA_BLOCK_FFD_PIXELCODE_ORIGINAL_ORDER_PDAF = 41,
> + CCS_DATA_BLOCK_FFD_PIXELCODE_VENDOR_PDAF = 41,
> +};
> +
> +struct __ccs_data_block_ffd_entry {
> + uint8_t pixelcode;
> + uint8_t reserved;
> + uint8_t value[2];
> +} __attribute__((packed));
> +
> +struct __ccs_data_block_ffd {
> + uint8_t num_column_descs;
> + uint8_t num_row_descs;
> +} __attribute__((packed));
> +
> +enum __ccs_data_block_rule_id {
> + CCS_DATA_BLOCK_RULE_ID_IF = 1,
> + CCS_DATA_BLOCK_RULE_ID_READ_ONLY_REGS = 2,
> + CCS_DATA_BLOCK_RULE_ID_FFD = 3,
> + CCS_DATA_BLOCK_RULE_ID_MSR = 4,
> + CCS_DATA_BLOCK_RULE_ID_PDAF_READOUT = 5,
> +};
> +
> +struct __ccs_data_block_rule_if {
> + uint8_t addr[2];
> + uint8_t value;
> + uint8_t mask;
> +} __attribute__((packed));
> +
> +enum __ccs_data_block_pdaf_readout_order{
> + CCS_DATA_BLOCK_PDAF_READOUT_ORDER_ORIGINAL = 1,
> + CCS_DATA_BLOCK_PDAF_READOUT_ORDER_SEPARATE_WITHIN_LINE = 2,
> + CCS_DATA_BLOCK_PDAF_READOUT_ORDER_SEPARATE_TYPES_SEPARATE_LINES = 3,
> +};
> +
> +struct __ccs_data_block_pdaf_readout {
> + uint8_t pdaf_readout_info_reserved;
> + uint8_t pdaf_readout_info_order;
> +} __attribute__((packed));
> +
> +struct __ccs_data_block_pdaf_pix_loc_block_desc {
> + uint8_t block_type_id;
> + uint8_t repeat_x[2];
> +} __attribute__((packed));
> +
> +struct __ccs_data_block_pdaf_pix_loc_block_desc_group {
> + uint8_t num_block_descs[2];
> + uint8_t repeat_y;
> +} __attribute__((packed));
> +
> +enum __ccs_data_block_pdaf_pix_loc_pixel_type {
> + CCS_DATA_PDAF_PIXEL_TYPE_LEFT_SEPARATED = 0,
> + CCS_DATA_PDAF_PIXEL_TYPE_RIGHT_SEPARATED = 1,
> + CCS_DATA_PDAF_PIXEL_TYPE_TOP_SEPARATED = 2,
> + CCS_DATA_PDAF_PIXEL_TYPE_BOTTOM_SEPARATED = 3,
> + CCS_DATA_PDAF_PIXEL_TYPE_LEFT_SIDE_BY_SIDE = 4,
> + CCS_DATA_PDAF_PIXEL_TYPE_RIGHT_SIDE_BY_SIDE = 5,
> + CCS_DATA_PDAF_PIXEL_TYPE_TOP_SIDE_BY_SIDE = 6,
> + CCS_DATA_PDAF_PIXEL_TYPE_BOTTOM_SIDE_BY_SIDE = 7,
> + CCS_DATA_PDAF_PIXEL_TYPE_TOP_LEFT = 8,
> + CCS_DATA_PDAF_PIXEL_TYPE_TOP_RIGHT = 9,
> + CCS_DATA_PDAF_PIXEL_TYPE_BOTTOM_LEFT = 10,
> + CCS_DATA_PDAF_PIXEL_TYPE_BOTTOM_RIGHT = 11,
> +};
> +
> +struct __ccs_data_block_pdaf_pix_loc_pixel_desc {
> + uint8_t pixel_type;
> + uint8_t small_offset_x;
> + uint8_t small_offset_y;
> +} __attribute__((packed));
> +
> +struct __ccs_data_block_pdaf_pix_loc {
> + uint8_t main_offset_x[2];
> + uint8_t main_offset_y[2];
> + uint8_t global_pdaf_type;
> + uint8_t block_width;
> + uint8_t block_height;
> + uint8_t num_block_desc_groups[2];
> +} __attribute__((packed));
> +
> +struct __ccs_data_block_end {
> + uint8_t crc[4];
> +} __attribute__((packed));
> +
> +#endif /* __CCS_DATA_DEFS_H__ */
Nitpick: why all the above struct/enums start with "__"?
> diff --git a/drivers/media/i2c/ccs/ccs-data.c b/drivers/media/i2c/ccs/ccs-data.c
> new file mode 100644
> index 000000000000..16aeeee45936
> --- /dev/null
> +++ b/drivers/media/i2c/ccs/ccs-data.c
> @@ -0,0 +1,949 @@
> +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
> +/* Copyright 2019--2020 Intel Corporation */
> +
> +#include "ccs-os.h"
> +
> +#include "ccs-data-defs.h"
> +
> +struct bin_container {
> + void *base;
> + void *now;
> + void *end;
> + size_t size;
> +};
> +
> +static uint32_t u8_arr_to_u32(const uint8_t *arr, unsigned int size)
> +{
> + unsigned int i;
> + uint32_t value = arr[0];
> +
> + for (i = 1; i < size; i++) {
> + value <<= 8;
> + value += arr[i];
> + }
> +
> + return value;
> +}
Why don't you use, instead, the macros inside
include/linux/byteorder/generic.h? It sounds that there's just one
place where this helper function seems to make some sense.
> +
> +static void *bin_alloc(struct bin_container *bin, size_t len)
> +{
> + void *ptr;
> +
> + len = align2(len, 8);
> +
> + if (bin->end - bin->now < len)
> + return NULL;
> +
> + ptr = bin->now;
> + bin->now += len;
> +
> + return ptr;
> +}
> +
> +static void bin_reserve(struct bin_container *bin, size_t len)
> +{
> + bin->size += align2(len, 8);
> +}
> +
> +static int bin_backing_alloc(struct bin_container *bin)
> +{
> + bin->base = bin->now = os_calloc(bin->size);
> + if (!bin->base)
> + return -ENOMEM;
> +
> + bin->end = bin->base + bin->size;
> +
> + return 0;
> +}
> +
> +#define is_contained(var, endp) \
> + (sizeof(*var) <= (endp) - (void *)(var))
> +#define has_headroom(ptr, headroom, endp) \
> + ((headroom) <= (endp) - (void *)(ptr))
> +#define is_contained_with_headroom(var, headroom, endp) \
> + (sizeof(*var) + (headroom) <= (endp) - (void *)(var))
> +
> +static int
> +ccs_data_parse_length_specifier(const struct __ccs_data_length_specifier *__len,
> + size_t *__hlen, size_t *__plen,
> + const void *endp)
> +{
> + size_t hlen, plen;
> +
> + if (!is_contained(__len, endp))
> + return -ENODATA;
> +
> + switch (__len->length >> CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT) {
> + case CCS_DATA_LENGTH_SPECIFIER_1:
> + hlen = sizeof(*__len);
> + plen = __len->length &
> + ((1 << CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT) - 1);
> + break;
> +
> + case CCS_DATA_LENGTH_SPECIFIER_2: {
> + struct __ccs_data_length_specifier2 *__len2 = (void *)__len;
> +
> + if (!is_contained(__len2, endp))
> + return -ENODATA;
> +
> + hlen = sizeof(*__len2);
> + plen = ((size_t)
> + (__len2->length[0] &
> + ((1 << CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT) - 1))
> + << 8) + __len2->length[1];
> + break;
> + }
> + case CCS_DATA_LENGTH_SPECIFIER_3: {
> + struct __ccs_data_length_specifier3 *__len3 = (void *)__len;
> +
> + if (!is_contained(__len3, endp))
> + return -ENODATA;
> +
> + hlen = sizeof(*__len3);
> + plen = ((size_t)
> + (__len3->length[0] &
> + ((1 << CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT) - 1))
> + << 16) + u8_arr_to_u32(&__len3->length[1],
> + sizeof(__len3->length) - 1);
That perhaps is the only place where the macro might make some sense,
but still it just makes the above code more obscure.
It sounds to me that the logic would be clearer if you write the logic
there directly. Maybe something similar to:
plen = (__len3->length[0] & (1 << CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT) - 1))) << 16;
plen += __be16_to_cpu(&__len3->length[1]);
(I'm assuming that length has 24 bits on the above).
Btw, no matter on what case, the first 6 bits are encoded the same
way. So, maybe you could do something like this:
plen = (__len3->length[0] & (1 << CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT) - 1)));
switch (__len->length >> CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT) {
case CCS_DATA_LENGTH_SPECIFIER_1:
...
break;
case CCS_DATA_LENGTH_SPECIFIER_2: {
...
plen = (plen << 8) + __len2->length[1];
break;
}
case CCS_DATA_LENGTH_SPECIFIER_3: {
...
plen = (plen << 16) + __be16_to_cpu(&__len3->length[1]);
break;
In order to make easier for people to understand about how this is encoded.
> + }
> + default:
> + return -EINVAL;
> + }
> +
> + if (!has_headroom(__len, hlen + plen, endp))
> + return -ENODATA;
> +
> + *__hlen = hlen;
> + *__plen = plen;
> +
> + return 0;
> +}
> +
> +static uint8_t
> +ccs_data_parse_format_version(const struct __ccs_data_block *block)
> +{
> + return block->id >> CCS_DATA_BLOCK_HEADER_ID_VERSION_SHIFT;
> +}
> +
> +static uint8_t ccs_data_parse_block_id(const struct __ccs_data_block *block,
> + bool is_first)
> +{
> + if (!is_first)
> + return block->id;
> +
> + return block->id & ((1 << CCS_DATA_BLOCK_HEADER_ID_VERSION_SHIFT) - 1);
> +}
> +
> +static int ccs_data_parse_version(struct bin_container *bin,
> + struct ccs_data_container *ccsdata,
> + const void *payload, const void *endp)
> +{
> + const struct __ccs_data_block_version *v = payload;
> + struct ccs_data_block_version *vv;
> +
> + if (v + 1 != endp)
> + return -ENODATA;
> +
> + if (!bin->base) {
> + bin_reserve(bin, sizeof(*ccsdata->version));
> + return 0;
> + }
> +
> + ccsdata->version = bin_alloc(bin, sizeof(*ccsdata->version));
> + if (!ccsdata->version)
> + return -ENOMEM;
> +
> + vv = ccsdata->version;
> + vv->version_major = u8_arr_to_u32(v->static_data_version_major, 2);
> + vv->version_minor = u8_arr_to_u32(v->static_data_version_minor, 2);
> + vv->date_year = u8_arr_to_u32(v->year, 2);
Please use the right endiannes macro here - I guess it is be16_to_cpu(), right)?
> + vv->date_month = v->month;
> + vv->date_day = v->day;
> +
> + return 0;
> +}
> +
> +static void print_ccs_data_version(printf_ctx fh,
> + struct ccs_data_block_version *v)
> +{
> + os_printf(fh,
> + "static data version %4.4x.%4.4x, date %4.4u-%2.2u-%2.2u\n",
> + v->version_major, v->version_minor,
> + v->date_year, v->date_month, v->date_day);
Oh, no! yet another printf macro defined somewhere...
I missed this on patch 001/106:
+typedef struct device * printf_ctx;
+#define os_printf dev_dbg
Please don't do that!
It is a way clearer if you do, instead:
static void print_ccs_data_version(struct device *dev,
struct ccs_data_block_version *v)
{
dev_dbg(dev,
"static data version %4.4x.%4.4x, date %4.4u-%2.2u-%2.2u\n",
v->version_major, v->version_minor,
v->date_year, v->date_month, v->date_day);
}
Please also do that at the other parts of the driver that use those.
> +}
> +
> +static int ccs_data_block_parse_header(const struct __ccs_data_block *block,
> + bool is_first, unsigned int *__block_id,
> + const void **payload,
> + const struct __ccs_data_block **next_block,
> + const void *endp, printf_ctx fh,
> + bool verbose)
> +{
> + size_t plen, hlen;
> + uint8_t block_id;
> + int rval;
> +
> + if (!is_contained(block, endp))
> + return -ENODATA;
> +
> + rval = ccs_data_parse_length_specifier(&block->length, &hlen, &plen,
> + endp);
> + if (rval < 0)
> + return rval;
> +
> + block_id = ccs_data_parse_block_id(block, is_first);
> +
> + if (verbose)
> + os_printf(fh,
> + "Block ID 0x%2.2x, header length %zu, payload length %zu\n",
> + block_id, hlen, plen);
Why do you need to check for verbose? This is already usind dev_dbg(),
so it needs to be already enabled via dynamic printk. No need to have a
driver-specific var to also enable it.
Just get rid of "verbose" here and on all other places inside this driver
for good.
> +
> + if (!has_headroom(&block->length, hlen + plen, endp))
> + return -ENODATA;
> +
> + if (__block_id)
> + *__block_id = block_id;
> +
> + if (payload)
> + *payload = (void *)&block->length + hlen;
> +
> + if (next_block)
> + *next_block = (void *)&block->length + hlen + plen;
> +
> + return 0;
> +}
> +
> +static int ccs_data_parse_regs(struct bin_container *bin,
> + struct ccs_reg **__regs,
> + size_t *__num_regs, const void *payload,
> + const void *endp, printf_ctx fh)
> +{
> + struct ccs_reg *regs_base, *regs;
> + size_t num_regs = 0;
> + uint16_t addr = 0;
> +
> + if (bin->base && __regs) {
> + regs = regs_base = bin_alloc(bin, sizeof(*regs) * *__num_regs);
> + if (!regs)
> + return -ENOMEM;
> + }
> +
> + while (payload < endp && num_regs < INT_MAX) {
> + const struct __ccs_data_block_regs *r = payload;
> + size_t len;
> + const void *data;
> +
> + if (!is_contained(r, endp))
> + return -ENODATA;
> +
> + switch (r->reg_len >> CCS_DATA_BLOCK_REGS_SEL_SHIFT) {
> + case CCS_DATA_BLOCK_REGS_SEL_REGS:
> + addr += r->reg_len & CCS_DATA_BLOCK_REGS_ADDR_MASK;
> + len = ((r->reg_len & CCS_DATA_BLOCK_REGS_LEN_MASK)
> + >> CCS_DATA_BLOCK_REGS_LEN_SHIFT) + 1;
> +
> + if (!is_contained_with_headroom(r, len, endp))
> + return -ENODATA;
> +
> + data = r + 1;
> + break;
> + case CCS_DATA_BLOCK_REGS_SEL_REGS2: {
> + const struct __ccs_data_block_regs2 *r2 = payload;
> +
> + if (!is_contained(r2, endp))
> + return -ENODATA;
> +
> + addr += ((uint16_t)(r2->reg_len &
> + CCS_DATA_BLOCK_REGS_2_ADDR_MASK) << 8)
> + + r2->addr;
Same as before: please use endiannes macros for all such conversions.
> + len = ((r2->reg_len & CCS_DATA_BLOCK_REGS_2_LEN_MASK)
> + >> CCS_DATA_BLOCK_REGS_2_LEN_SHIFT) + 1;
> +
> + if (!is_contained_with_headroom(r2, len, endp))
> + return -ENODATA;
> +
> + data = r2 + 1;
> + break;
> + }
> + case CCS_DATA_BLOCK_REGS_SEL_REGS3: {
> + const struct __ccs_data_block_regs3 *r3 = payload;
> +
> + if (!is_contained(r3, endp))
> + return -ENODATA;
> +
> + addr = u8_arr_to_u32(r3->addr, sizeof(r3->addr));
Please use the right endiannes macro here.
> + len = (r3->reg_len & CCS_DATA_BLOCK_REGS_3_LEN_MASK) + 1;
> +
> + if (!is_contained_with_headroom(r3, len, endp))
> + return -ENODATA;
> +
> + data = r3 + 1;
> + break;
> + }
> + default:
> + return -EINVAL;
> + }
> +
> + num_regs++;
> +
> + if (!bin->base) {
> + bin_reserve(bin, len);
> + } else if (__regs) {
> + regs->addr = addr;
> + regs->len = len;
> + regs->value = bin_alloc(bin, len);
> + if (!regs->value)
> + return -ENOMEM;
> +
> + memcpy(regs->value, data, len);
> + regs++;
> + }
> +
> + addr += len;
> + payload = data + len;
> + }
> +
> + if (!bin->base)
> + bin_reserve(bin, sizeof(*regs) * num_regs);
> +
> + if (__num_regs)
> + *__num_regs = num_regs;
> +
> + if (bin->base && __regs)
> + *__regs = regs_base;
> +
> + return 0;
> +}
> +
> +static int ccs_data_parse_reg_rules(struct bin_container *bin,
> + struct ccs_reg **__regs,
> + size_t *__num_regs,
> + const void *payload,
> + const void *endp, printf_ctx fh)
> +{
> + int rval;
> +
> + if (!bin->base)
> + return ccs_data_parse_regs(bin, NULL, NULL, payload, endp, fh);
> +
> + rval = ccs_data_parse_regs(bin, NULL, __num_regs, payload, endp, fh);
> + if (rval)
> + return rval;
> +
> + return ccs_data_parse_regs(bin, __regs, __num_regs, payload, endp,
> + fh);
> +}
> +
> +static void assign_ffd_entry(struct ccs_frame_format_desc *desc,
> + const struct __ccs_data_block_ffd_entry *ent)
> +{
> + desc->pixelcode = ent->pixelcode;
> + desc->value = u8_arr_to_u32(ent->value, sizeof(ent->value));
Please use the right endiannes macro here.
> +}
> +
> +static int ccs_data_parse_ffd(struct bin_container *bin,
> + struct ccs_frame_format_descs **ffd,
> + const void *payload,
> + const void *endp, printf_ctx fh)
> +{
> + const struct __ccs_data_block_ffd *__ffd = payload;
> + const struct __ccs_data_block_ffd_entry *__entry;
> + unsigned int i;
> +
> + if (!is_contained(__ffd, endp))
> + return -ENODATA;
> +
> + if ((void *)__ffd + sizeof(*__ffd) +
> + ((uint32_t)__ffd->num_column_descs +
> + (uint32_t)__ffd->num_row_descs) *
> + sizeof(struct __ccs_data_block_ffd_entry) != endp)
> + return -ENODATA;
> +
> + if (!bin->base) {
> + bin_reserve(bin, sizeof(**ffd));
> + bin_reserve(bin, __ffd->num_column_descs *
> + sizeof(struct ccs_frame_format_desc));
> + bin_reserve(bin, __ffd->num_row_descs *
> + sizeof(struct ccs_frame_format_desc));
> +
> + return 0;
> + }
> +
> + *ffd = bin_alloc(bin, sizeof(**ffd));
> + if (!*ffd)
> + return -ENOMEM;
> +
> + (*ffd)->num_column_descs = __ffd->num_column_descs;
> + (*ffd)->num_row_descs = __ffd->num_row_descs;
> + __entry = (void *)(__ffd + 1);
> +
> + (*ffd)->column_descs = bin_alloc(bin, __ffd->num_column_descs *
> + sizeof(*(*ffd)->column_descs));
> + if (!(*ffd)->column_descs)
> + return -ENOMEM;
> +
> + for (i = 0; i < __ffd->num_column_descs; i++, __entry++)
> + assign_ffd_entry(&(*ffd)->column_descs[i], __entry);
> +
> + (*ffd)->row_descs = bin_alloc(bin, __ffd->num_row_descs *
> + sizeof(*(*ffd)->row_descs));
> + if (!(*ffd)->row_descs)
> + return -ENOMEM;
> +
> + for (i = 0; i < __ffd->num_row_descs; i++, __entry++)
> + assign_ffd_entry(&(*ffd)->row_descs[i], __entry);
> +
> + if (__entry != endp)
> + return -EPROTO;
> +
> + return 0;
> +}
> +
> +static int ccs_data_parse_pdaf_readout(struct bin_container *bin,
> + struct ccs_pdaf_readout **pdaf_readout,
> + const void *payload,
> + const void *endp, printf_ctx fh)
> +{
> + const struct __ccs_data_block_pdaf_readout *__pdaf = payload;
> +
> + if (!is_contained(__pdaf, endp))
> + return -ENODATA;
> +
> + if (!bin->base) {
> + bin_reserve(bin, sizeof(**pdaf_readout));
> + } else {
> + *pdaf_readout = bin_alloc(bin, sizeof(**pdaf_readout));
> + if (!*pdaf_readout)
> + return -ENOMEM;
> +
> + (*pdaf_readout)->pdaf_readout_info_order =
> + __pdaf->pdaf_readout_info_order;
> + }
> +
> + return ccs_data_parse_ffd(bin, !bin->base ? NULL : &(*pdaf_readout)->ffd,
> + __pdaf + 1, endp, fh);
> +}
> +
> +static int ccs_data_parse_rules(struct bin_container *bin,
> + struct ccs_rule **__rules,
> + size_t *__num_rules, const void *payload,
> + const void *endp, printf_ctx fh)
> +{
> + struct ccs_rule *rules_base, *rules = NULL, *next_rule;
> + size_t num_rules = 0;
> + const void *__next_rule = payload;
> + int rval;
> +
> + if (bin->base) {
> + rules_base = next_rule =
> + bin_alloc(bin, sizeof(*rules) * *__num_rules);
> + if (!rules_base)
> + return -ENOMEM;
> + }
> +
> + while (__next_rule < endp) {
> + size_t rule_hlen, rule_plen, rule_plen2;
> + const uint8_t *__rule_type;
> + const void *rule_payload;
> +
> + /* Size of a single rule */
> + rval = ccs_data_parse_length_specifier(__next_rule, &rule_hlen,
> + &rule_plen, endp);
> +
> + if (rval < 0)
> + return rval;
> +
> + __rule_type = __next_rule + rule_hlen;
> +
> + if (!is_contained(__rule_type, endp))
> + return -ENODATA;
> +
> + rule_payload = __rule_type + 1;
> + rule_plen2 = rule_plen - sizeof(*__rule_type);
> +
> + switch (*__rule_type) {
> + case CCS_DATA_BLOCK_RULE_ID_IF: {
> + const struct __ccs_data_block_rule_if *__if_rules =
> + rule_payload;
> + const size_t __num_if_rules =
> + rule_plen2 / sizeof(*__if_rules);
> + struct ccs_if_rule *if_rule;
> +
> + if (!has_headroom(__if_rules,
> + sizeof(*__if_rules) * __num_if_rules,
> + rule_payload + rule_plen2))
> + return -ENODATA;
> +
> + /* Also check there is no extra data */
> + if (__if_rules + __num_if_rules !=
> + rule_payload + rule_plen2)
> + return -EINVAL;
> +
> + if (!bin->base) {
> + bin_reserve(bin,
> + sizeof(*if_rule) *
> + __num_if_rules);
> + num_rules++;
> + } else {
> + unsigned int i;
> +
> + rules = next_rule;
> + next_rule++;
> +
> + if_rule = bin_alloc(bin,
> + sizeof(*if_rule) *
> + __num_if_rules);
> + if (!if_rule)
> + return -ENOMEM;
> +
> + for (i = 0; i < __num_if_rules; i++) {
> + if_rule[i].addr =
> + u8_arr_to_u32(
> + __if_rules[i].addr,
> + sizeof(__if_rules[i].
> + addr));
Please use the right endiannes macro here.
> + if_rule[i].value = __if_rules[i].value;
> + if_rule[i].mask = __if_rules[i].mask;
> + }
> +
> + rules->if_rules = if_rule;
> + rules->num_if_rules = __num_if_rules;
> + }
> + break;
> + }
> + case CCS_DATA_BLOCK_RULE_ID_READ_ONLY_REGS:
> + rval = ccs_data_parse_reg_rules(bin, &rules->read_only_regs,
> + &rules->num_read_only_regs,
> + rule_payload,
> + rule_payload + rule_plen2,
> + fh);
> + if (rval)
> + return rval;
> + break;
> + case CCS_DATA_BLOCK_RULE_ID_FFD:
> + rval = ccs_data_parse_ffd(bin, &rules->frame_format,
> + rule_payload,
> + rule_payload + rule_plen2,
> + fh);
> + if (rval)
> + return rval;
> + break;
> + case CCS_DATA_BLOCK_RULE_ID_MSR:
> + rval = ccs_data_parse_reg_rules(bin,
> + &rules->manufacturer_regs,
> + &rules->num_manufacturer_regs,
> + rule_payload,
> + rule_payload + rule_plen2,
> + fh);
> + if (rval)
> + return rval;
> + break;
> + case CCS_DATA_BLOCK_RULE_ID_PDAF_READOUT:
> + rval = ccs_data_parse_pdaf_readout(bin,
> + &rules->pdaf_readout,
> + rule_payload,
> + rule_payload + rule_plen2,
> + fh);
> + if (rval)
> + return rval;
> + break;
> + default:
> + os_printf(fh,
> + "Don't know how to handle rule type %u!\n",
> + *__rule_type);
> + return -EINVAL;
> + }
> + __next_rule = __next_rule + rule_hlen + rule_plen;
> + }
> +
> + if (!bin->base) {
> + bin_reserve(bin, sizeof(*rules) * num_rules);
> + *__num_rules = num_rules;
> + } else {
> + *__rules = rules_base;
> + }
> +
> + return 0;
> +}
> +
> +static int ccs_data_parse_pdaf(struct bin_container *bin, struct ccs_pdaf_pix_loc **pdaf,
> + const void *payload, const void *endp,
> + printf_ctx fh)
> +{
> + const struct __ccs_data_block_pdaf_pix_loc *__pdaf = payload;
> + const struct __ccs_data_block_pdaf_pix_loc_block_desc_group *__bdesc_group;
> + const struct __ccs_data_block_pdaf_pix_loc_pixel_desc *__pixel_desc;
> + unsigned int i;
> + uint16_t num_block_desc_groups;
> + uint8_t max_block_type_id = 0;
> + const uint8_t *__num_pixel_descs;
> +
> + if (!is_contained(__pdaf, endp))
> + return -ENODATA;
> +
> + if (bin->base) {
> + *pdaf = bin_alloc(bin, sizeof(**pdaf));
> + if (!*pdaf)
> + return -ENOMEM;
> + } else {
> + bin_reserve(bin, sizeof(**pdaf));
> + }
> +
> + num_block_desc_groups =
> + u8_arr_to_u32(__pdaf->num_block_desc_groups,
> + sizeof(__pdaf->num_block_desc_groups));
Please use the right endiannes macro here.
> +
> + if (bin->base) {
> + (*pdaf)->main_offset_x =
> + u8_arr_to_u32(__pdaf->main_offset_x,
> + sizeof(__pdaf->main_offset_x));
> + (*pdaf)->main_offset_y =
> + u8_arr_to_u32(__pdaf->main_offset_y,
> + sizeof(__pdaf->main_offset_y));
Please use the right endiannes macro here.
> + (*pdaf)->global_pdaf_type = __pdaf->global_pdaf_type;
> + (*pdaf)->block_width = __pdaf->block_width;
> + (*pdaf)->block_height = __pdaf->block_height;
> + (*pdaf)->num_block_desc_groups = num_block_desc_groups;
> + }
> +
> + __bdesc_group = (const void *)(__pdaf + 1);
> +
> + if (bin->base) {
> + (*pdaf)->block_desc_groups =
> + bin_alloc(bin,
> + sizeof(struct ccs_pdaf_pix_loc_block_desc_group) *
> + num_block_desc_groups);
> + if (!(*pdaf)->block_desc_groups)
> + return -ENOMEM;
> + } else {
> + bin_reserve(bin, sizeof(struct ccs_pdaf_pix_loc_block_desc_group) *
> + num_block_desc_groups);
> + }
> +
> + for (i = 0; i < num_block_desc_groups; i++) {
> + const struct __ccs_data_block_pdaf_pix_loc_block_desc *__bdesc;
> + uint16_t num_block_descs;
> + unsigned int j;
> +
> + if (!is_contained(__bdesc_group, endp))
> + return -ENODATA;
> +
> + num_block_descs =
> + u8_arr_to_u32(__bdesc_group->num_block_descs,
> + sizeof(__bdesc_group->num_block_descs));
Please use the right endiannes macro here.
> +
> + if (bin->base) {
> + (*pdaf)->block_desc_groups[i].repeat_y =
> + __bdesc_group->repeat_y;
> + (*pdaf)->block_desc_groups[i].num_block_descs =
> + num_block_descs;
> + }
> +
> + __bdesc = (const void *)(__bdesc_group + 1);
> +
> + if (bin->base) {
> + (*pdaf)->block_desc_groups[i].block_descs =
> + bin_alloc(bin,
> + sizeof(struct ccs_pdaf_pix_loc_block_desc) *
> + num_block_descs);
> + if (!(*pdaf)->block_desc_groups[i].block_descs)
> + return -ENOMEM;
> + } else {
> + bin_reserve(bin, sizeof(struct ccs_pdaf_pix_loc_block_desc) *
> + num_block_descs);
> + }
> +
> + for (j = 0; j < num_block_descs; j++, __bdesc++) {
> + struct ccs_pdaf_pix_loc_block_desc *bdesc;
> +
> + if (!is_contained(__bdesc, endp))
> + return -ENODATA;
> +
> + if (max_block_type_id <= __bdesc->block_type_id)
> + max_block_type_id = __bdesc->block_type_id + 1;
> +
> + if (!bin->base)
> + continue;
> +
> + bdesc = &(*pdaf)->block_desc_groups[i].block_descs[j];
> +
> + bdesc->repeat_x = u8_arr_to_u32(
> + __bdesc->repeat_x,
> + sizeof(__bdesc->repeat_x));
Please use the right endiannes macro here.
> +
> + if (__bdesc->block_type_id >= num_block_descs)
> + return -EINVAL;
> +
> + bdesc->block_type_id = __bdesc->block_type_id;
> + }
> +
> + __bdesc_group = (const void *)__bdesc;
> + }
> +
> + __num_pixel_descs = (const void *)__bdesc_group;
> +
> + if (bin->base) {
> + (*pdaf)->pixel_desc_groups =
> + bin_alloc(bin,
> + sizeof(struct ccs_pdaf_pix_loc_pixel_desc_group) *
> + max_block_type_id);
> + if (!(*pdaf)->pixel_desc_groups)
> + return -ENOMEM;
> + (*pdaf)->num_pixel_desc_grups = max_block_type_id;
> + } else {
> + bin_reserve(bin, sizeof(struct ccs_pdaf_pix_loc_pixel_desc_group) *
> + max_block_type_id);
> + }
> +
> + for (i = 0; i < max_block_type_id; i++) {
> + struct ccs_pdaf_pix_loc_pixel_desc_group *pdgroup;
> + unsigned int j;
> +
> + if (!is_contained(__num_pixel_descs, endp))
> + return -ENODATA;
> +
> + if (bin->base) {
> + pdgroup = &(*pdaf)->pixel_desc_groups[i];
> + pdgroup->descs =
> + bin_alloc(bin,
> + sizeof(struct ccs_pdaf_pix_loc_pixel_desc) *
> + *__num_pixel_descs);
> + if (!pdgroup->descs)
> + return -ENOMEM;
> + pdgroup->num_descs = *__num_pixel_descs;
> + } else {
> + bin_reserve(bin, sizeof(struct ccs_pdaf_pix_loc_pixel_desc) *
> + *__num_pixel_descs);
> + }
> +
> + __pixel_desc = (const void *)(__num_pixel_descs + 1);
> +
> + for (j = 0; j < *__num_pixel_descs; j++, __pixel_desc++) {
> + struct ccs_pdaf_pix_loc_pixel_desc *pdesc;
> +
> + if (!is_contained(__pixel_desc, endp))
> + return -ENODATA;
> +
> + if (!bin->base)
> + continue;
> +
> + pdesc = &pdgroup->descs[j];
> + pdesc->pixel_type = __pixel_desc->pixel_type;
> + pdesc->small_offset_x = __pixel_desc->small_offset_x;
> + pdesc->small_offset_y = __pixel_desc->small_offset_y;
> + }
> +
> + __num_pixel_descs = (const void *)(__pixel_desc + 1);
> + }
> +
> + return 0;
> +}
> +
> +static int ccs_data_parse_license(struct bin_container *bin,
> + char **__license,
> + size_t *__license_length,
> + const void *payload, const void *endp)
> +{
> + size_t size = endp - payload;
> + char *license;
> +
> + if (!bin->base) {
> + bin_reserve(bin, size);
> + return 0;
> + }
> +
> + license = bin_alloc(bin, size);
> + if (!license)
> + return -ENOMEM;
> +
> + memcpy(license, payload, size);
> +
> + *__license = license;
> + *__license_length = size;
> +
> + return 0;
> +}
> +
> +static int ccs_data_parse_end(bool *end, const void *payload, const void *endp,
> + printf_ctx fh)
> +{
> + const struct __ccs_data_block_end *__end = payload;
> +
> + if (__end + 1 != endp) {
> + os_printf(fh, "Invalid end block length %u\n",
> + (unsigned int)(endp - payload));
> + return -ENODATA;
> + }
> +
> + *end = true;
> +
> + return 0;
> +}
> +
> +static int __ccs_data_parse(struct bin_container *bin,
> + struct ccs_data_container *ccsdata,
> + const void *data, size_t len, printf_ctx fh,
> + bool verbose)
> +{
> + const struct __ccs_data_block *block = data;
> + const struct __ccs_data_block *endp = data + len;
> + unsigned int version;
> + bool is_first = true;
> + int rval;
> +
> + version = ccs_data_parse_format_version(block);
> + if (version != CCS_STATIC_DATA_VERSION) {
> + os_printf(fh, "Don't know how to handle version %u\n", version);
> + return -EINVAL;
> + }
> +
> + if (verbose)
> + os_printf(fh, "Parsing CCS static data version %u\n", version);
> +
> + if (!bin->base)
> + *ccsdata = (struct ccs_data_container){ 0 };
> +
> + while (block < endp) {
> + const struct __ccs_data_block *next_block;
> + unsigned int block_id;
> + const void *payload;
> +
> + rval = ccs_data_block_parse_header(block, is_first, &block_id,
> + &payload, &next_block, endp,
> + fh,
> + bin->base ? false : verbose);
> +
> + if (rval < 0)
> + return rval;
> +
> + switch (block_id) {
> + case CCS_DATA_BLOCK_ID_DUMMY:
> + break;
> + case CCS_DATA_BLOCK_ID_DATA_VERSION:
> + rval = ccs_data_parse_version(bin, ccsdata, payload,
> + next_block);
> + if (rval < 0)
> + return rval;
> + break;
> + case CCS_DATA_BLOCK_ID_SENSOR_READ_ONLY_REGS:
> + rval = ccs_data_parse_regs(
> + bin, &ccsdata->sensor_read_only_regs,
> + &ccsdata->num_sensor_read_only_regs, payload,
> + next_block, fh);
> + if (rval < 0)
> + return rval;
> + break;
> + case CCS_DATA_BLOCK_ID_SENSOR_MANUFACTURER_REGS:
> + rval = ccs_data_parse_regs(
> + bin, &ccsdata->sensor_manufacturer_regs,
> + &ccsdata->num_sensor_manufacturer_regs, payload,
> + next_block, fh);
> + if (rval < 0)
> + return rval;
> + break;
> + case CCS_DATA_BLOCK_ID_MODULE_READ_ONLY_REGS:
> + rval = ccs_data_parse_regs(
> + bin, &ccsdata->module_read_only_regs,
> + &ccsdata->num_module_read_only_regs, payload,
> + next_block, fh);
> + if (rval < 0)
> + return rval;
> + break;
> + case CCS_DATA_BLOCK_ID_MODULE_MANUFACTURER_REGS:
> + rval = ccs_data_parse_regs(
> + bin, &ccsdata->module_manufacturer_regs,
> + &ccsdata->num_module_manufacturer_regs, payload,
> + next_block, fh);
> + if (rval < 0)
> + return rval;
> + break;
> + case CCS_DATA_BLOCK_ID_SENSOR_PDAF_PIXEL_LOCATION:
> + rval = ccs_data_parse_pdaf(bin, &ccsdata->sensor_pdaf,
> + payload, next_block, fh);
> + if (rval < 0)
> + return rval;
> + break;
> + case CCS_DATA_BLOCK_ID_MODULE_PDAF_PIXEL_LOCATION:
> + rval = ccs_data_parse_pdaf(bin, &ccsdata->module_pdaf,
> + payload, next_block, fh);
> + if (rval < 0)
> + return rval;
> + break;
> + case CCS_DATA_BLOCK_ID_SENSOR_RULE_BASED_BLOCK:
> + rval = ccs_data_parse_rules(
> + bin, &ccsdata->sensor_rules,
> + &ccsdata->num_sensor_rules, payload, next_block,
> + fh);
> + if (rval < 0)
> + return rval;
> + break;
> + case CCS_DATA_BLOCK_ID_MODULE_RULE_BASED_BLOCK:
> + rval = ccs_data_parse_rules(
> + bin, &ccsdata->module_rules,
> + &ccsdata->num_module_rules, payload, next_block,
> + fh);
> + if (rval < 0)
> + return rval;
> + break;
> + case CCS_DATA_BLOCK_ID_LICENSE:
> + rval = ccs_data_parse_license(bin, &ccsdata->license,
> + &ccsdata->license_length,
> + payload, next_block);
> + if (rval < 0)
> + return rval;
> + break;
> + case CCS_DATA_BLOCK_ID_END:
> + rval = ccs_data_parse_end(&ccsdata->end, payload,
> + next_block, fh);
> + if (rval < 0)
> + return rval;
> + break;
> + default:
> + os_printf(fh, "WARNING: not handling block ID 0x%2.2x\n",
> + block_id);
> + }
> +
> + block = next_block;
> + is_first = false;
> + }
> +
> + return 0;
> +}
> +
> +int ccs_data_parse(struct ccs_data_container *ccsdata,
> + const void *data, size_t len, printf_ctx fh, bool verbose)
> +{
> + struct bin_container bin = { 0 };
> + int rval;
> +
> + rval = __ccs_data_parse(&bin, ccsdata, data, len, fh, verbose);
> + if (rval)
> + return rval;
> +
> + rval = bin_backing_alloc(&bin);
> + if (rval)
> + return rval;
> +
> + rval = __ccs_data_parse(&bin, ccsdata, data, len, fh, false);
> + if (rval)
> + goto out_free;
> +
> + if (verbose && ccsdata->version)
> + print_ccs_data_version(fh, ccsdata->version);
> +
> + if (bin.now != bin.end) {
> + rval = -EPROTO;
> + os_printf(fh, "parsing mismatch; base %p; now %p; end %p\n",
> + bin.base, bin.now, bin.end);
> + goto out_free;
> + }
> +
> + ccsdata->backing = bin.base;
> +
> + return 0;
> +
> +out_free:
> + os_free(bin.base);
> +
> + return rval;
> +}
> diff --git a/drivers/media/i2c/ccs/ccs-data.h b/drivers/media/i2c/ccs/ccs-data.h
> new file mode 100644
> index 000000000000..1dfc697fccdf
> --- /dev/null
> +++ b/drivers/media/i2c/ccs/ccs-data.h
> @@ -0,0 +1,116 @@
> +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
> +/* Copyright 2019--2020 Intel Corporation */
> +
> +#ifndef __CCS_DATA_H__
> +#define __CCS_DATA_H__
> +
> +#include "ccs-os.h"
> +
> +struct ccs_data_block_version {
> + uint16_t version_major;
> + uint16_t version_minor;
> + uint16_t date_year;
> + uint8_t date_month;
> + uint8_t date_day;
> +};
> +
> +struct ccs_reg {
> + uint16_t addr;
> + uint16_t len;
> + uint8_t *value;
> +};
> +
> +struct ccs_if_rule {
> + uint16_t addr;
> + uint8_t value;
> + uint8_t mask;
> +};
> +
> +struct ccs_frame_format_desc {
> + uint8_t pixelcode;
> + uint16_t value;
> +};
> +
> +struct ccs_frame_format_descs {
> + uint8_t num_column_descs;
> + uint8_t num_row_descs;
> + struct ccs_frame_format_desc *column_descs;
> + struct ccs_frame_format_desc *row_descs;
> +};
> +
> +struct ccs_pdaf_readout {
> + uint8_t pdaf_readout_info_order;
> + struct ccs_frame_format_descs *ffd;
> +};
> +
> +struct ccs_rule {
> + size_t num_if_rules;
> + struct ccs_if_rule *if_rules;
> + size_t num_read_only_regs;
> + struct ccs_reg *read_only_regs;
> + size_t num_manufacturer_regs;
> + struct ccs_reg *manufacturer_regs;
> + struct ccs_frame_format_descs *frame_format;
> + struct ccs_pdaf_readout *pdaf_readout;
> +};
> +
> +struct ccs_pdaf_pix_loc_block_desc {
> + uint8_t block_type_id;
> + uint16_t repeat_x;
> +};
> +
> +struct ccs_pdaf_pix_loc_block_desc_group {
> + uint8_t repeat_y;
> + uint16_t num_block_descs;
> + struct ccs_pdaf_pix_loc_block_desc *block_descs;
> +};
> +
> +struct ccs_pdaf_pix_loc_pixel_desc {
> + uint8_t pixel_type;
> + uint8_t small_offset_x;
> + uint8_t small_offset_y;
> +};
> +
> +struct ccs_pdaf_pix_loc_pixel_desc_group {
> + uint8_t num_descs;
> + struct ccs_pdaf_pix_loc_pixel_desc *descs;
> +};
> +
> +struct ccs_pdaf_pix_loc {
> + uint16_t main_offset_x;
> + uint16_t main_offset_y;
> + uint8_t global_pdaf_type;
> + uint8_t block_width;
> + uint8_t block_height;
> + uint16_t num_block_desc_groups;
> + struct ccs_pdaf_pix_loc_block_desc_group *block_desc_groups;
> + uint8_t num_pixel_desc_grups;
> + struct ccs_pdaf_pix_loc_pixel_desc_group *pixel_desc_groups;
> +};
> +
> +struct ccs_data_container {
> + struct ccs_data_block_version *version;
> + size_t num_sensor_read_only_regs;
> + struct ccs_reg *sensor_read_only_regs;
> + size_t num_sensor_manufacturer_regs;
> + struct ccs_reg *sensor_manufacturer_regs;
> + size_t num_sensor_rules;
> + struct ccs_rule *sensor_rules;
> + size_t num_module_read_only_regs;
> + struct ccs_reg *module_read_only_regs;
> + size_t num_module_manufacturer_regs;
> + struct ccs_reg *module_manufacturer_regs;
> + size_t num_module_rules;
> + struct ccs_rule *module_rules;
> + struct ccs_pdaf_pix_loc *sensor_pdaf;
> + struct ccs_pdaf_pix_loc *module_pdaf;
> + size_t license_length;
> + char *license;
> + bool end;
> + void *backing;
> +};
> +
> +int ccs_data_parse(struct ccs_data_container *ccsdata, const void *data,
> + size_t len, printf_ctx fh, bool verbose);
> +
> +#endif /* __CCS_DATA_H__ */
Thanks,
Mauro
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 035/106] ccs: Read CCS static data from firmware binaries
2020-10-07 8:44 ` [PATCH v2 035/106] ccs: Read CCS static data from firmware binaries Sakari Ailus
@ 2020-11-05 10:56 ` Mauro Carvalho Chehab
0 siblings, 0 replies; 146+ messages in thread
From: Mauro Carvalho Chehab @ 2020-11-05 10:56 UTC (permalink / raw)
To: Sakari Ailus; +Cc: linux-media
Em Wed, 7 Oct 2020 11:44:48 +0300
Sakari Ailus <sakari.ailus@linux.intel.com> escreveu:
> Read the CCS static data for sensors and modules. The files are expected
> to be found in "ccs" directory.
>
> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> ---
> drivers/media/i2c/ccs/ccs-core.c | 30 ++++++++++++++++++++++++++++++
> drivers/media/i2c/ccs/ccs.h | 2 ++
> 2 files changed, 32 insertions(+)
>
> diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
> index 34e86ddbb06a..0cc6e7423f26 100644
> --- a/drivers/media/i2c/ccs/ccs-core.c
> +++ b/drivers/media/i2c/ccs/ccs-core.c
> @@ -16,6 +16,7 @@
> #include <linux/clk.h>
> #include <linux/delay.h>
> #include <linux/device.h>
> +#include <linux/firmware.h>
> #include <linux/gpio.h>
> #include <linux/gpio/consumer.h>
> #include <linux/module.h>
> @@ -2947,6 +2948,8 @@ static int ccs_get_hwconfig(struct ccs_sensor *sensor, struct device *dev)
> static int ccs_probe(struct i2c_client *client)
> {
> struct ccs_sensor *sensor;
> + const struct firmware *fw;
> + char filename[40];
> unsigned int i;
> int rval;
>
> @@ -3036,6 +3039,31 @@ static int ccs_probe(struct i2c_client *client)
> goto out_power_off;
> }
>
> + WARN_ON(snprintf(filename, sizeof(filename),
> + "ccs/ccs-sensor-%4.4x-%4.4x-%4.4x.fw",
> + sensor->minfo.sensor_mipi_manufacturer_id,
> + sensor->minfo.sensor_model_id,
> + sensor->minfo.sensor_revision_number) >=
> + sizeof(filename));
Nitpick: better to do something like:
int len;
len = snprintf(filename, sizeof(filename),
"ccs/ccs-sensor-%4.4x-%4.4x-%4.4x.fw",
sensor->minfo.sensor_mipi_manufacturer_id,
sensor->minfo.sensor_model_id,
sensor->minfo.sensor_revision_number);
if (WARN_ON(len >= sizeof(filename))
return -ENOMEM;
> + rval = request_firmware(&fw, filename, &client->dev);
> + if (!rval) {
> + ccs_data_parse(&sensor->sdata, fw->data, fw->size, &client->dev,
> + true);
> + release_firmware(fw);
> + }
> +
> + WARN_ON(snprintf(filename, sizeof(filename),
> + "ccs/ccs-module-%4.4x-%4.4x-%4.4x.fw",
> + sensor->minfo.mipi_manufacturer_id,
> + sensor->minfo.model_id,
> + sensor->minfo.revision_number) >= sizeof(filename));
Same here.
> + rval = request_firmware(&fw, filename, &client->dev);
> + if (!rval) {
> + ccs_data_parse(&sensor->mdata, fw->data, fw->size, &client->dev,
> + true);
> + release_firmware(fw);
> + }
> +
> rval = ccs_read_all_limits(sensor);
> if (rval)
> goto out_power_off;
> @@ -3232,6 +3260,8 @@ static int ccs_remove(struct i2c_client *client)
> ccs_cleanup(sensor);
> mutex_destroy(&sensor->mutex);
> kfree(sensor->ccs_limits);
> + kvfree(sensor->sdata.backing);
> + kvfree(sensor->mdata.backing);
>
> return 0;
> }
> diff --git a/drivers/media/i2c/ccs/ccs.h b/drivers/media/i2c/ccs/ccs.h
> index ad2ff5a74424..cbcd93b519da 100644
> --- a/drivers/media/i2c/ccs/ccs.h
> +++ b/drivers/media/i2c/ccs/ccs.h
> @@ -16,6 +16,7 @@
> #include <media/v4l2-ctrls.h>
> #include <media/v4l2-subdev.h>
>
> +#include "ccs-data.h"
> #include "ccs-quirk.h"
> #include "ccs-regs.h"
> #include "ccs-reg-access.h"
> @@ -227,6 +228,7 @@ struct ccs_sensor {
> const struct ccs_csi_data_format *internal_csi_format;
> u32 default_mbus_frame_fmts;
> int default_pixel_order;
> + struct ccs_data_container sdata, mdata;
>
> u8 binning_horizontal;
> u8 binning_vertical;
Thanks,
Mauro
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 033/106] ccs: Add CCS static data parser library
2020-11-05 10:50 ` Mauro Carvalho Chehab
@ 2020-11-05 11:18 ` Sakari Ailus
2020-11-05 12:53 ` Mauro Carvalho Chehab
0 siblings, 1 reply; 146+ messages in thread
From: Sakari Ailus @ 2020-11-05 11:18 UTC (permalink / raw)
To: Mauro Carvalho Chehab; +Cc: linux-media
Hi Mauro,
Thanks for the review.
On Thu, Nov 05, 2020 at 11:50:32AM +0100, Mauro Carvalho Chehab wrote:
...
> > +struct __ccs_data_block_end {
> > + uint8_t crc[4];
> > +} __attribute__((packed));
> > +
> > +#endif /* __CCS_DATA_DEFS_H__ */
>
> Nitpick: why all the above struct/enums start with "__"?
We have two sets of data structure: those that are related to the binary
file format (these, so they're packed) as well as the in-kernel
representation. So I've used the underscores to designate these are the
binary format ones. They're only used in ccs-data.c.
--
Kind regards,
Sakari Ailus
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 046/106] ccs: Add support for manufacturer regs from sensor and module files
2020-10-07 8:44 ` [PATCH v2 046/106] ccs: Add support for manufacturer regs from sensor and module files Sakari Ailus
@ 2020-11-05 11:34 ` Mauro Carvalho Chehab
2020-11-05 11:56 ` Sakari Ailus
0 siblings, 1 reply; 146+ messages in thread
From: Mauro Carvalho Chehab @ 2020-11-05 11:34 UTC (permalink / raw)
To: Sakari Ailus; +Cc: linux-media
Em Wed, 7 Oct 2020 11:44:59 +0300
Sakari Ailus <sakari.ailus@linux.intel.com> escreveu:
> Write manufacturer specific registers (MSRs) from file to the sensor on
> sensor power-on.
>
> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> ---
> drivers/media/i2c/ccs/ccs-core.c | 23 +++++++
> drivers/media/i2c/ccs/ccs-reg-access.c | 94 ++++++++++++++++++++------
> drivers/media/i2c/ccs/ccs-reg-access.h | 2 +
> 3 files changed, 97 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
> index 5d7c5ece578d..6c2f18abc921 100644
> --- a/drivers/media/i2c/ccs/ccs-core.c
> +++ b/drivers/media/i2c/ccs/ccs-core.c
> @@ -1272,6 +1272,21 @@ static int ccs_setup_flash_strobe(struct ccs_sensor *sensor)
> * Power management
> */
>
> +static int ccs_write_msr_regs(struct ccs_sensor *sensor)
> +{
> + int rval;
> +
> + rval = ccs_write_data_regs(sensor,
> + sensor->sdata.sensor_manufacturer_regs,
> + sensor->sdata.num_sensor_manufacturer_regs);
> + if (rval)
> + return rval;
> +
> + return ccs_write_data_regs(sensor,
> + sensor->mdata.module_manufacturer_regs,
> + sensor->mdata.num_module_manufacturer_regs);
> +}
> +
> static int ccs_power_on(struct device *dev)
> {
> struct v4l2_subdev *subdev = dev_get_drvdata(dev);
> @@ -1377,6 +1392,10 @@ static int ccs_power_on(struct device *dev)
> if (rval < 0)
> goto out_cci_addr_fail;
>
> + rval = ccs_write_msr_regs(sensor);
> + if (rval)
> + goto out_cci_addr_fail;
> +
> rval = ccs_call_quirk(sensor, post_poweron);
> if (rval) {
> dev_err(dev, "post_poweron quirks failed\n");
> @@ -3205,6 +3224,10 @@ static int ccs_probe(struct i2c_client *client)
> if (rval < 0)
> goto out_media_entity_cleanup;
>
> + rval = ccs_write_msr_regs(sensor);
> + if (rval)
> + goto out_media_entity_cleanup;
> +
> pm_runtime_set_active(&client->dev);
> pm_runtime_get_noresume(&client->dev);
> pm_runtime_enable(&client->dev);
> diff --git a/drivers/media/i2c/ccs/ccs-reg-access.c b/drivers/media/i2c/ccs/ccs-reg-access.c
> index aad2727570ec..9fda16b221a7 100644
> --- a/drivers/media/i2c/ccs/ccs-reg-access.c
> +++ b/drivers/media/i2c/ccs/ccs-reg-access.c
> @@ -236,12 +236,38 @@ int ccs_read_addr_noconv(struct ccs_sensor *sensor, u32 reg, u32 *val)
> return ccs_read_addr_raw(sensor, reg, val, false, true, false);
> }
>
> +static int ccs_write_retry(struct i2c_client *client, struct i2c_msg *msg)
> +{
> + unsigned int retries;
> + int r;
> +
> + for (retries = 0; retries < 5; retries++) {
> + /*
> + * Due to unknown reason sensor stops responding. This
> + * loop is a temporaty solution until the root cause
> + * is found.
> + */
> + r = i2c_transfer(client->adapter, msg, 1);
> + if (r != 1) {
> + usleep_range(2000, 2000);
Huh? Does it need to sleep precisely for 2000 us?
> + continue;
> + }
> +
> + if (retries)
> + dev_err(&client->dev,
> + "sensor i2c stall encountered. retries: %d\n",
> + retries);
> + return 0;
> + }
> +
> + return r;
> +}
> +
> int ccs_write_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 val)
> {
> struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
> struct i2c_msg msg;
> unsigned char data[6];
> - unsigned int retries;
> unsigned int len = ccs_reg_width(reg);
> int r;
>
> @@ -256,27 +282,11 @@ int ccs_write_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 val)
> put_unaligned_be16(CCS_REG_ADDR(reg), data);
> put_unaligned_be32(val << (8 * (sizeof(val) - len)), data + 2);
>
> - for (retries = 0; retries < 5; retries++) {
> - /*
> - * Due to unknown reason sensor stops responding. This
> - * loop is a temporaty solution until the root cause
> - * is found.
> - */
> - r = i2c_transfer(client->adapter, &msg, 1);
> - if (r == 1) {
> - if (retries)
> - dev_err(&client->dev,
> - "sensor i2c stall encountered. retries: %d\n",
> - retries);
> - return 0;
> - }
> -
> - usleep_range(2000, 2000);
> - }
> -
> - dev_err(&client->dev,
> - "wrote 0x%x to offset 0x%x error %d\n", val,
> - CCS_REG_ADDR(reg), r);
> + r = ccs_write_retry(client, &msg);
> + if (r)
> + dev_err(&client->dev,
> + "wrote 0x%x to offset 0x%x error %d\n", val,
> + CCS_REG_ADDR(reg), r);
>
> return r;
> }
> @@ -297,3 +307,43 @@ int ccs_write_addr(struct ccs_sensor *sensor, u32 reg, u32 val)
>
> return ccs_write_addr_no_quirk(sensor, reg, val);
> }
> +
> +#define MAX_WRITE_LEN 32U
> +
> +int ccs_write_data_regs(struct ccs_sensor *sensor, struct ccs_reg *regs,
> + size_t num_regs)
> +{
> + struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
> + unsigned char buf[2 + MAX_WRITE_LEN];
> + struct i2c_msg msg = {
> + .addr = client->addr,
> + .buf = buf,
> + };
> + size_t i;
> +
> + for (i = 0; i < num_regs; i++, regs++) {
> + unsigned char *regdata = regs->value;
> + unsigned int j;
> +
> + for (j = 0; j < regs->len;
> + j += msg.len - 2, regdata += msg.len - 2) {
> + int rval;
> +
> + msg.len = min(regs->len - j, MAX_WRITE_LEN);
> +
> + put_unaligned_be16(regs->addr + j, buf);
> + memcpy(buf + 2, regdata, msg.len);
> + msg.len += 2;
> +
> + rval = ccs_write_retry(client, &msg);
> + if (rval) {
> + dev_err(&client->dev,
> + "error writing %u octets to address 0x%4.4x\n",
> + msg.len, regs->addr + j);
> + return rval;
> + }
> + }
> + }
> +
> + return 0;
> +}
> diff --git a/drivers/media/i2c/ccs/ccs-reg-access.h b/drivers/media/i2c/ccs/ccs-reg-access.h
> index cfad2e520fe2..78c43f92d99a 100644
> --- a/drivers/media/i2c/ccs/ccs-reg-access.h
> +++ b/drivers/media/i2c/ccs/ccs-reg-access.h
> @@ -27,6 +27,8 @@ int ccs_read_addr_8only(struct ccs_sensor *sensor, u32 reg, u32 *val);
> int ccs_read_addr_noconv(struct ccs_sensor *sensor, u32 reg, u32 *val);
> int ccs_write_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 val);
> int ccs_write_addr(struct ccs_sensor *sensor, u32 reg, u32 val);
> +int ccs_write_data_regs(struct ccs_sensor *sensor, struct ccs_reg *regs,
> + size_t num_regs);
>
> unsigned int ccs_reg_width(u32 reg);
> u32 ccs_reg_conv(struct ccs_sensor *sensor, u32 reg, u32 val);
Thanks,
Mauro
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 046/106] ccs: Add support for manufacturer regs from sensor and module files
2020-11-05 11:34 ` Mauro Carvalho Chehab
@ 2020-11-05 11:56 ` Sakari Ailus
2020-11-05 12:46 ` Mauro Carvalho Chehab
0 siblings, 1 reply; 146+ messages in thread
From: Sakari Ailus @ 2020-11-05 11:56 UTC (permalink / raw)
To: Mauro Carvalho Chehab; +Cc: linux-media
Hi Mauro,
Thanks for the review.
On Thu, Nov 05, 2020 at 12:34:13PM +0100, Mauro Carvalho Chehab wrote:
> Em Wed, 7 Oct 2020 11:44:59 +0300
> Sakari Ailus <sakari.ailus@linux.intel.com> escreveu:
...
> > diff --git a/drivers/media/i2c/ccs/ccs-reg-access.c b/drivers/media/i2c/ccs/ccs-reg-access.c
> > index aad2727570ec..9fda16b221a7 100644
> > --- a/drivers/media/i2c/ccs/ccs-reg-access.c
> > +++ b/drivers/media/i2c/ccs/ccs-reg-access.c
> > @@ -236,12 +236,38 @@ int ccs_read_addr_noconv(struct ccs_sensor *sensor, u32 reg, u32 *val)
> > return ccs_read_addr_raw(sensor, reg, val, false, true, false);
> > }
> >
> > +static int ccs_write_retry(struct i2c_client *client, struct i2c_msg *msg)
> > +{
> > + unsigned int retries;
> > + int r;
> > +
> > + for (retries = 0; retries < 5; retries++) {
> > + /*
> > + * Due to unknown reason sensor stops responding. This
> > + * loop is a temporaty solution until the root cause
> > + * is found.
> > + */
> > + r = i2c_transfer(client->adapter, msg, 1);
> > + if (r != 1) {
> > + usleep_range(2000, 2000);
>
> Huh? Does it need to sleep precisely for 2000 us?
I believe this one does not, indeed. I'll make it a range, but add a
separate patch for it as this patch just moves the code form one place to
another.
--
Sakari Ailus
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 063/106] ccs-pll: Document the structs in the header as well as the function
2020-10-07 8:45 ` [PATCH v2 063/106] ccs-pll: Document the structs in the header as well as the function Sakari Ailus
@ 2020-11-05 12:18 ` Mauro Carvalho Chehab
2020-12-02 18:02 ` Sakari Ailus
0 siblings, 1 reply; 146+ messages in thread
From: Mauro Carvalho Chehab @ 2020-11-05 12:18 UTC (permalink / raw)
To: Sakari Ailus; +Cc: linux-media
Em Wed, 7 Oct 2020 11:45:14 +0300
Sakari Ailus <sakari.ailus@linux.intel.com> escreveu:
> The CCS pll is used by the CCS driver at the moment, but documenting the
> interface makes sense. It's non-trivial and the calculator could be used
> elsewhere.
LFTM.
It could make sense to add a .. kernel-doc:: markup at the documentation
somewhere.
Regards,
Mauro
>
> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> ---
> drivers/media/i2c/ccs-pll.h | 88 +++++++++++++++++++++++++++++++++++++
> 1 file changed, 88 insertions(+)
>
> diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h
> index 1d908b23c934..e01359f61476 100644
> --- a/drivers/media/i2c/ccs-pll.h
> +++ b/drivers/media/i2c/ccs-pll.h
> @@ -20,6 +20,16 @@
> #define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0)
> #define CCS_PLL_FLAG_NO_OP_CLOCKS (1 << 1)
>
> +/**
> + * struct ccs_pll_branch_fr - CCS PLL configuration (front)
> + *
> + * A single branch front-end of the CCS PLL tree.
> + *
> + * @pre_pll_clk_div: Pre-PLL clock divisor
> + * @pll_multiplier: PLL multiplier
> + * @pll_ip_freq_hz: PLL input clock frequency
> + * @pll_op_freq_hz: PLL output clock frequency
> + */
> struct ccs_pll_branch_fr {
> uint16_t pre_pll_clk_div;
> uint16_t pll_multiplier;
> @@ -27,6 +37,16 @@ struct ccs_pll_branch_fr {
> uint32_t pll_op_clk_freq_hz;
> };
>
> +/**
> + * struct ccs_pll_branch_bk - CCS PLL configuration (back)
> + *
> + * A single branch back-end of the CCS PLL tree.
> + *
> + * @sys_clk_div: System clock divider
> + * @pix_clk_div: Pixel clock divider
> + * @sys_clk_freq_hz: System clock frequency
> + * @pix_clk_freq_hz: Pixel clock frequency
> + */
> struct ccs_pll_branch_bk {
> uint16_t sys_clk_div;
> uint16_t pix_clk_div;
> @@ -34,6 +54,29 @@ struct ccs_pll_branch_bk {
> uint32_t pix_clk_freq_hz;
> };
>
> +/**
> + * struct ccs_pll - Full CCS PLL configuration
> + *
> + * All information required to calculate CCS PLL configuration.
> + *
> + * @bus_type: Type of the data bus, CCS_PLL_BUS_TYPE_* (input)
> + * @csi2.lanes: The number of the CSI-2 data lanes (input)
> + * @binning_vertical: Vertical binning factor (input)
> + * @binning_horizontal: Horizontal binning factor (input)
> + * @scale_m: Downscaling factor, M component, [16, max] (input)
> + * @scale_n: Downscaling factor, N component, typically 16 (input)
> + * @bits_per_pixel: Bits per pixel on the output data bus (input)
> + * @flags: CCS_PLL_FLAG_* (input)
> + * @link_freq: Chosen link frequency (input)
> + * @ext_clk_freq_hz: External clock frequency, i.e. the sensor's input clock
> + * (input)
> + * @vt_fr: Video timing front-end configuration (output)
> + * @vt_bk: Video timing back-end configuration (output)
> + * @op_bk: Operational timing back-end configuration (output)
> + * @pixel_rate_csi: Pixel rate on the output data bus (output)
> + * @pixel_rate_pixel_array: Nominal pixel rate in the sensor's pixel array
> + * (output)
> + */
> struct ccs_pll {
> /* input values */
> uint8_t bus_type;
> @@ -58,6 +101,18 @@ struct ccs_pll {
> uint32_t pixel_rate_pixel_array;
> };
>
> +/**
> + * struct ccs_pll_branch_limits_fr - CCS PLL front-end limits
> + *
> + * @min_pre_pll_clk_div: Minimum pre-PLL clock divider
> + * @max_pre_pll_clk_div: Maximum pre-PLL clock divider
> + * @min_pll_ip_freq_hz: Minimum PLL input clock frequency
> + * @max_pll_ip_freq_hz: Maximum PLL input clock frequency
> + * @min_pll_multiplier: Minimum PLL multiplier
> + * @max_pll_multiplier: Maximum PLL multiplier
> + * @min_pll_op_freq_hz: Minimum PLL output clock frequency
> + * @max_pll_op_freq_hz: Maximum PLL output clock frequency
> + */
> struct ccs_pll_branch_limits_fr {
> uint16_t min_pre_pll_clk_div;
> uint16_t max_pre_pll_clk_div;
> @@ -69,6 +124,18 @@ struct ccs_pll_branch_limits_fr {
> uint32_t max_pll_op_clk_freq_hz;
> };
>
> +/**
> + * struct ccs_pll_branch_limits_bk - CCS PLL back-end limits
> + *
> + * @min_sys_clk_div: Minimum system clock divider
> + * @max_sys_clk_div: Maximum system clock divider
> + * @min_sys_clk_freq_hz: Minimum system clock frequency
> + * @max_sys_clk_freq_hz: Maximum system clock frequency
> + * @min_pix_clk_div: Minimum pixel clock divider
> + * @max_pix_clk_div: Maximum pixel clock divider
> + * @min_pix_clk_freq_hz: Minimum pixel clock frequency
> + * @max_pix_clk_freq_hz: Maximum pixel clock frequency
> + */
> struct ccs_pll_branch_limits_bk {
> uint16_t min_sys_clk_div;
> uint16_t max_sys_clk_div;
> @@ -80,6 +147,17 @@ struct ccs_pll_branch_limits_bk {
> uint32_t max_pix_clk_freq_hz;
> };
>
> +/**
> + * struct ccs_pll_limits - CCS PLL limits
> + *
> + * @min_ext_clk_freq_hz: Minimum external clock frequency
> + * @max_ext_clk_freq_hz: Maximum external clock frequency
> + * @vt_fr: Video timing front-end limits
> + * @vt_bk: Video timing back-end limits
> + * @op_bk: Operational timing back-end limits
> + * @min_line_length_pck_bin: Minimum line length in pixels, with binning
> + * @min_line_length_pck: Minimum line length in pixels without binning
> + */
> struct ccs_pll_limits {
> /* Strict PLL limits */
> uint32_t min_ext_clk_freq_hz;
> @@ -96,6 +174,16 @@ struct ccs_pll_limits {
>
> struct device;
>
> +/**
> + * ccs_pll_calculate - Calculate CCS PLL configuration based on input parameters
> + *
> + * @dev: Device pointer, used for printing messages
> + * @limits: Limits specific to the sensor
> + * @pll: Given PLL configuration
> + *
> + * Calculate the CCS PLL configuration based on the limits as well as given
> + * device specific, system specific or user configured input data.
> + */
> int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits,
> struct ccs_pll *pll);
>
Thanks,
Mauro
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 099/106] v4l: uapi: ccs: Add controls for analogue gain constants
2020-10-07 8:45 ` [PATCH v2 099/106] v4l: uapi: ccs: Add controls for analogue gain constants Sakari Ailus
@ 2020-11-05 12:41 ` Hans Verkuil
2020-11-05 12:47 ` Sakari Ailus
2020-11-05 12:56 ` Hans Verkuil
1 sibling, 1 reply; 146+ messages in thread
From: Hans Verkuil @ 2020-11-05 12:41 UTC (permalink / raw)
To: Sakari Ailus, linux-media
On 07/10/2020 10:45, Sakari Ailus wrote:
> Add a V4L2 controls for analogue gai constants required to control
gai -> gain
> analogue gain. The values are device specific and thus need to be obtained
> from the driver.
>
> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> ---
> MAINTAINERS | 1 +
> include/uapi/linux/ccs.h | 14 ++++++++++++++
> 2 files changed, 15 insertions(+)
> create mode 100644 include/uapi/linux/ccs.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index b72f666b8b60..c173e503b0b7 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -11569,6 +11569,7 @@ F: drivers/media/i2c/ccs/
> F: drivers/media/i2c/ccs-pll.c
> F: drivers/media/i2c/ccs-pll.h
> F: include/uapi/linux/smiapp.h
> +F: include/uapi/linux/ccs.h
>
> MIPS
> M: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> diff --git a/include/uapi/linux/ccs.h b/include/uapi/linux/ccs.h
> new file mode 100644
> index 000000000000..bcdce95955b0
> --- /dev/null
> +++ b/include/uapi/linux/ccs.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: GPL-2.0-only AND BSD-3-Clause */
> +/* Copyright (C) 2020 Intel Corporation */
> +
> +#ifndef __UAPI_CCS_H__
> +#define __UAPI_CCS_H__
> +
> +#include <linux/videodev2.h>
> +
> +#define V4L2_CID_CCS_ANALOGUE_GAIN_M0 (V4L2_CID_USER_CCS_BASE + 1)
> +#define V4L2_CID_CCS_ANALOGUE_GAIN_C0 (V4L2_CID_USER_CCS_BASE + 2)
> +#define V4L2_CID_CCS_ANALOGUE_GAIN_M1 (V4L2_CID_USER_CCS_BASE + 3)
> +#define V4L2_CID_CCS_ANALOGUE_GAIN_C1 (V4L2_CID_USER_CCS_BASE + 4)
Please document these controls. Ditto for the later patches that add more
of these controls.
This header is a good place to put the documentation.
Regards,
Hans
> +
> +#endif
>
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 105/106] ccs: Add shading correction and luminance correction level controls
2020-10-07 8:45 ` [PATCH v2 105/106] ccs: Add shading correction and luminance correction level controls Sakari Ailus
@ 2020-11-05 12:42 ` Mauro Carvalho Chehab
2020-11-05 16:29 ` Sakari Ailus
2020-11-05 13:03 ` Hans Verkuil
1 sibling, 1 reply; 146+ messages in thread
From: Mauro Carvalho Chehab @ 2020-11-05 12:42 UTC (permalink / raw)
To: Sakari Ailus; +Cc: linux-media, Hans Verkuil
Em Wed, 7 Oct 2020 11:45:56 +0300
Sakari Ailus <sakari.ailus@linux.intel.com> escreveu:
> Add controls for supporting lens shading correction.
>
> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
For patches 098 to 105, we should at least have those new controls
documented at the uAPI documents.
I'm not convinced yet that we shouldn't instead place them inside
V4L2_CTRL_CLASS_CAMERA.
As those are part of a MIPI standard, I won't doubt that sooner or
later, other drivers may need them.
Regards,
Mauro
> ---
> drivers/media/i2c/ccs/ccs-core.c | 74 ++++++++++++++++++++++++++++++++
> 1 file changed, 74 insertions(+)
>
> diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
> index 0ba06a580951..10ed3d01af16 100644
> --- a/drivers/media/i2c/ccs/ccs-core.c
> +++ b/drivers/media/i2c/ccs/ccs-core.c
> @@ -757,6 +757,25 @@ static int ccs_set_ctrl(struct v4l2_ctrl *ctrl)
> case V4L2_CID_TEST_PATTERN_GREENB:
> rval = ccs_write(sensor, TEST_DATA_GREENB, ctrl->val);
>
> + break;
> + case V4L2_CID_CCS_SHADING_CORRECTION:
> + if (!(CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) &
> + (CCS_SHADING_CORRECTION_CAPABILITY_COLOR_SHADING |
> + CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION)))
> + break;
> +
> + rval = ccs_write(sensor, SHADING_CORRECTION_EN,
> + ctrl->val ? CCS_SHADING_CORRECTION_EN_ENABLE :
> + 0);
> +
> + break;
> + case V4L2_CID_CCS_LUMINANCE_SHADING_CORRECTION:
> + if (!(CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) &
> + CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION))
> + break;
> +
> + rval = ccs_write(sensor, LUMINANCE_CORRECTION_LEVEL, ctrl->val);
> +
> break;
> case V4L2_CID_PIXEL_RATE:
> /* For v4l2_ctrl_s_ctrl_int64() used internally. */
> @@ -878,6 +897,61 @@ static int ccs_init_controls(struct ccs_sensor *sensor)
> }
> }
>
> + if (CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) &
> + CCS_SHADING_CORRECTION_CAPABILITY_COLOR_SHADING) {
> + const struct v4l2_ctrl_config ctrl_cfg = {
> + .name = "Shading Correction",
> + .type = V4L2_CTRL_TYPE_BOOLEAN,
> + .id = V4L2_CID_CCS_SHADING_CORRECTION,
> + .ops = &ccs_ctrl_ops,
> + .max = 1,
> + .step = 1,
> + };
> +
> + v4l2_ctrl_new_custom(&sensor->pixel_array->ctrl_handler,
> + &ctrl_cfg, NULL);
> + }
> +
> + if (CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) &
> + CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION) {
> + const struct v4l2_ctrl_config ctrl_cfg = {
> + .name = "Luminance Shading Correction",
> + .type = V4L2_CTRL_TYPE_BOOLEAN,
> + .id = V4L2_CID_CCS_LUMINANCE_SHADING_CORRECTION,
> + .ops = &ccs_ctrl_ops,
> + .max = 255,
> + .step = 1,
> + .def = 128,
> + };
> +
> + v4l2_ctrl_new_custom(&sensor->pixel_array->ctrl_handler,
> + &ctrl_cfg, NULL);
> + }
> +
> + if (CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) &
> + (CCS_SHADING_CORRECTION_CAPABILITY_COLOR_SHADING |
> + CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION)) {
> + u32 val =
> + ((CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) &
> + CCS_SHADING_CORRECTION_CAPABILITY_COLOR_SHADING) ?
> + V4L2_CCS_SHADING_CORRECTION_COLOUR : 0) |
> + ((CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) &
> + CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION) ?
> + V4L2_CCS_SHADING_CORRECTION_LUMINANCE : 0);
> + const struct v4l2_ctrl_config ctrl_cfg = {
> + .name = "Shading Correction Capability",
> + .type = V4L2_CTRL_TYPE_BITMASK,
> + .id = V4L2_CID_CCS_SHADING_CORRECTION_CAPABILITY,
> + .ops = &ccs_ctrl_ops,
> + .max = val,
> + .def = val,
> + .flags = V4L2_CTRL_FLAG_READ_ONLY,
> + };
> +
> + v4l2_ctrl_new_custom(&sensor->pixel_array->ctrl_handler,
> + &ctrl_cfg, NULL);
> + }
> +
> if (CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) ==
> CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL ||
> CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) ==
Thanks,
Mauro
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 106/106] ccs: Add CCS ACPI device ID
2020-10-07 8:45 ` [PATCH v2 106/106] ccs: Add CCS ACPI device ID Sakari Ailus
@ 2020-11-05 12:44 ` Mauro Carvalho Chehab
0 siblings, 0 replies; 146+ messages in thread
From: Mauro Carvalho Chehab @ 2020-11-05 12:44 UTC (permalink / raw)
To: Sakari Ailus; +Cc: linux-media
Em Wed, 7 Oct 2020 11:45:57 +0300
Sakari Ailus <sakari.ailus@linux.intel.com> escreveu:
> The CCS compliant sensors use device ID "MIPI0200". Use this id for ACPI
> device matching.
Better to place this patch before the one dropping I2C table, as it
helps to understand why you dropped the I2C table.
>
> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> ---
> drivers/media/i2c/ccs/ccs-core.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
> index 10ed3d01af16..297c5373a305 100644
> --- a/drivers/media/i2c/ccs/ccs-core.c
> +++ b/drivers/media/i2c/ccs/ccs-core.c
> @@ -3604,6 +3604,12 @@ static const struct ccs_device smia_device = {
>
> static const struct ccs_device ccs_device = {};
>
> +static const struct acpi_device_id ccs_acpi_table[] = {
> + { .id = "MIPI0200", .driver_data = (unsigned long)&ccs_device },
> + { },
> +};
> +MODULE_DEVICE_TABLE(acpi, ccs_acpi_table);
> +
> static const struct of_device_id ccs_of_table[] = {
> { .compatible = "mipi-ccs-1.1", .data = &ccs_device },
> { .compatible = "mipi-ccs-1.0", .data = &ccs_device },
> @@ -3620,6 +3626,7 @@ static const struct dev_pm_ops ccs_pm_ops = {
>
> static struct i2c_driver ccs_i2c_driver = {
> .driver = {
> + .acpi_match_table = ccs_acpi_table,
> .of_match_table = ccs_of_table,
> .name = CCS_NAME,
> .pm = &ccs_pm_ops,
Thanks,
Mauro
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 046/106] ccs: Add support for manufacturer regs from sensor and module files
2020-11-05 11:56 ` Sakari Ailus
@ 2020-11-05 12:46 ` Mauro Carvalho Chehab
0 siblings, 0 replies; 146+ messages in thread
From: Mauro Carvalho Chehab @ 2020-11-05 12:46 UTC (permalink / raw)
To: Sakari Ailus; +Cc: linux-media
Em Thu, 5 Nov 2020 13:56:01 +0200
Sakari Ailus <sakari.ailus@linux.intel.com> escreveu:
> Hi Mauro,
>
> Thanks for the review.
>
> On Thu, Nov 05, 2020 at 12:34:13PM +0100, Mauro Carvalho Chehab wrote:
> > Em Wed, 7 Oct 2020 11:44:59 +0300
> > Sakari Ailus <sakari.ailus@linux.intel.com> escreveu:
>
> ...
>
> > > diff --git a/drivers/media/i2c/ccs/ccs-reg-access.c b/drivers/media/i2c/ccs/ccs-reg-access.c
> > > index aad2727570ec..9fda16b221a7 100644
> > > --- a/drivers/media/i2c/ccs/ccs-reg-access.c
> > > +++ b/drivers/media/i2c/ccs/ccs-reg-access.c
> > > @@ -236,12 +236,38 @@ int ccs_read_addr_noconv(struct ccs_sensor *sensor, u32 reg, u32 *val)
> > > return ccs_read_addr_raw(sensor, reg, val, false, true, false);
> > > }
> > >
> > > +static int ccs_write_retry(struct i2c_client *client, struct i2c_msg *msg)
> > > +{
> > > + unsigned int retries;
> > > + int r;
> > > +
> > > + for (retries = 0; retries < 5; retries++) {
> > > + /*
> > > + * Due to unknown reason sensor stops responding. This
> > > + * loop is a temporaty solution until the root cause
> > > + * is found.
> > > + */
> > > + r = i2c_transfer(client->adapter, msg, 1);
> > > + if (r != 1) {
> > > + usleep_range(2000, 2000);
> >
> > Huh? Does it need to sleep precisely for 2000 us?
>
> I believe this one does not, indeed. I'll make it a range, but add a
> separate patch for it as this patch just moves the code form one place to
> another.
Ok.
>
Thanks,
Mauro
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 100/106] ccs: Add support for analogue gain coefficient controls
2020-10-07 8:45 ` [PATCH v2 100/106] ccs: Add support for analogue gain coefficient controls Sakari Ailus
@ 2020-11-05 12:46 ` Hans Verkuil
2020-11-05 12:50 ` Hans Verkuil
2020-11-05 12:55 ` Sakari Ailus
0 siblings, 2 replies; 146+ messages in thread
From: Hans Verkuil @ 2020-11-05 12:46 UTC (permalink / raw)
To: Sakari Ailus, linux-media
On 07/10/2020 10:45, Sakari Ailus wrote:
> Add four controls for reading CCS analogue gain coefficients. The
> values are constants that are device specific.
>
> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> ---
> drivers/media/i2c/ccs/ccs-core.c | 38 ++++++++++++++++++++++++++++++--
> 1 file changed, 36 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
> index d6d6aeceb415..2a507b63bafc 100644
> --- a/drivers/media/i2c/ccs/ccs-core.c
> +++ b/drivers/media/i2c/ccs/ccs-core.c
> @@ -28,6 +28,7 @@
> #include <linux/v4l2-mediabus.h>
> #include <media/v4l2-fwnode.h>
> #include <media/v4l2-device.h>
> +#include <uapi/linux/ccs.h>
>
> #include "ccs.h"
>
> @@ -772,14 +773,46 @@ static int ccs_init_controls(struct ccs_sensor *sensor)
> struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
> int rval;
>
> - rval = v4l2_ctrl_handler_init(&sensor->pixel_array->ctrl_handler, 13);
> + rval = v4l2_ctrl_handler_init(&sensor->pixel_array->ctrl_handler, 17);
> if (rval)
> return rval;
>
> sensor->pixel_array->ctrl_handler.lock = &sensor->mutex;
>
> switch (CCS_LIM(sensor, ANALOG_GAIN_CAPABILITY)) {
> - case CCS_ANALOG_GAIN_CAPABILITY_GLOBAL:
> + case CCS_ANALOG_GAIN_CAPABILITY_GLOBAL: {
> + struct {
Can this be static?
> + const char *name;
> + u32 id;
> + s32 value;
> + } const gain_ctrls[] = {
> + { "Analogue Gain m0", V4L2_CID_CCS_ANALOGUE_GAIN_M0,
Why lower case 'm0/1' and 'c0/1'? It looks odd.
> + CCS_LIM(sensor, ANALOG_GAIN_M0), },
> + { "Analogue Gain c0", V4L2_CID_CCS_ANALOGUE_GAIN_C0,
> + CCS_LIM(sensor, ANALOG_GAIN_C0), },
> + { "Analogue Gain m1", V4L2_CID_CCS_ANALOGUE_GAIN_M1,
> + CCS_LIM(sensor, ANALOG_GAIN_M1), },
> + { "Analogue Gain c1", V4L2_CID_CCS_ANALOGUE_GAIN_C1,
> + CCS_LIM(sensor, ANALOG_GAIN_C1), },
> + };
> + struct v4l2_ctrl_config ctrl_cfg = {
> + .type = V4L2_CTRL_TYPE_INTEGER,
> + .ops = &ccs_ctrl_ops,
> + .flags = V4L2_CTRL_FLAG_READ_ONLY,
> + .step = 1,
> + };
This looks a bit weird. Most drivers just define each control separately in
a static const struct v4l2_ctrl_config, then add them with v4l2_ctrl_new_custom.
Now the control definition data is split up in two data structures.
It's not wrong, it is just non-standard, and a bit harder to review.
> + unsigned int i;
> +
> + for (i = 0; i < ARRAY_SIZE(gain_ctrls); i++) {
> + ctrl_cfg.name = gain_ctrls[i].name;
> + ctrl_cfg.id = gain_ctrls[i].id;
> + ctrl_cfg.min = ctrl_cfg.max = ctrl_cfg.def =
> + gain_ctrls[i].value;
> +
> + v4l2_ctrl_new_custom(&sensor->pixel_array->ctrl_handler,
> + &ctrl_cfg, NULL);
> + }
> +
> v4l2_ctrl_new_std(&sensor->pixel_array->ctrl_handler,
> &ccs_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
> CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN),
> @@ -788,6 +821,7 @@ static int ccs_init_controls(struct ccs_sensor *sensor)
> 1U),
> CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN));
> }
> + }
>
> if (CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) ==
> CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL ||
>
Regards,
Hans
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 099/106] v4l: uapi: ccs: Add controls for analogue gain constants
2020-11-05 12:41 ` Hans Verkuil
@ 2020-11-05 12:47 ` Sakari Ailus
0 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-11-05 12:47 UTC (permalink / raw)
To: Hans Verkuil; +Cc: linux-media
Hi Hans,
On Thu, Nov 05, 2020 at 01:41:55PM +0100, Hans Verkuil wrote:
> On 07/10/2020 10:45, Sakari Ailus wrote:
> > Add a V4L2 controls for analogue gai constants required to control
>
> gai -> gain
>
> > analogue gain. The values are device specific and thus need to be obtained
> > from the driver.
> >
> > Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> > ---
> > MAINTAINERS | 1 +
> > include/uapi/linux/ccs.h | 14 ++++++++++++++
> > 2 files changed, 15 insertions(+)
> > create mode 100644 include/uapi/linux/ccs.h
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index b72f666b8b60..c173e503b0b7 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -11569,6 +11569,7 @@ F: drivers/media/i2c/ccs/
> > F: drivers/media/i2c/ccs-pll.c
> > F: drivers/media/i2c/ccs-pll.h
> > F: include/uapi/linux/smiapp.h
> > +F: include/uapi/linux/ccs.h
> >
> > MIPS
> > M: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> > diff --git a/include/uapi/linux/ccs.h b/include/uapi/linux/ccs.h
> > new file mode 100644
> > index 000000000000..bcdce95955b0
> > --- /dev/null
> > +++ b/include/uapi/linux/ccs.h
> > @@ -0,0 +1,14 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only AND BSD-3-Clause */
> > +/* Copyright (C) 2020 Intel Corporation */
> > +
> > +#ifndef __UAPI_CCS_H__
> > +#define __UAPI_CCS_H__
> > +
> > +#include <linux/videodev2.h>
> > +
> > +#define V4L2_CID_CCS_ANALOGUE_GAIN_M0 (V4L2_CID_USER_CCS_BASE + 1)
> > +#define V4L2_CID_CCS_ANALOGUE_GAIN_C0 (V4L2_CID_USER_CCS_BASE + 2)
> > +#define V4L2_CID_CCS_ANALOGUE_GAIN_M1 (V4L2_CID_USER_CCS_BASE + 3)
> > +#define V4L2_CID_CCS_ANALOGUE_GAIN_C1 (V4L2_CID_USER_CCS_BASE + 4)
>
> Please document these controls. Ditto for the later patches that add more
> of these controls.
>
> This header is a good place to put the documentation.
Yes, I'll add that for v3.
--
Sakari Ailus
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 100/106] ccs: Add support for analogue gain coefficient controls
2020-11-05 12:46 ` Hans Verkuil
@ 2020-11-05 12:50 ` Hans Verkuil
2020-11-05 12:55 ` Sakari Ailus
1 sibling, 0 replies; 146+ messages in thread
From: Hans Verkuil @ 2020-11-05 12:50 UTC (permalink / raw)
To: Sakari Ailus, linux-media
On 05/11/2020 13:46, Hans Verkuil wrote:
> On 07/10/2020 10:45, Sakari Ailus wrote:
>> Add four controls for reading CCS analogue gain coefficients. The
>> values are constants that are device specific.
>>
>> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
>> ---
>> drivers/media/i2c/ccs/ccs-core.c | 38 ++++++++++++++++++++++++++++++--
>> 1 file changed, 36 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
>> index d6d6aeceb415..2a507b63bafc 100644
>> --- a/drivers/media/i2c/ccs/ccs-core.c
>> +++ b/drivers/media/i2c/ccs/ccs-core.c
>> @@ -28,6 +28,7 @@
>> #include <linux/v4l2-mediabus.h>
>> #include <media/v4l2-fwnode.h>
>> #include <media/v4l2-device.h>
>> +#include <uapi/linux/ccs.h>
>>
>> #include "ccs.h"
>>
>> @@ -772,14 +773,46 @@ static int ccs_init_controls(struct ccs_sensor *sensor)
>> struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
>> int rval;
>>
>> - rval = v4l2_ctrl_handler_init(&sensor->pixel_array->ctrl_handler, 13);
>> + rval = v4l2_ctrl_handler_init(&sensor->pixel_array->ctrl_handler, 17);
>> if (rval)
>> return rval;
>>
>> sensor->pixel_array->ctrl_handler.lock = &sensor->mutex;
>>
>> switch (CCS_LIM(sensor, ANALOG_GAIN_CAPABILITY)) {
>> - case CCS_ANALOG_GAIN_CAPABILITY_GLOBAL:
>> + case CCS_ANALOG_GAIN_CAPABILITY_GLOBAL: {
>> + struct {
>
> Can this be static?
Ah, no. The value is sensor dependent. Sorry, ignore this.
>
>> + const char *name;
>> + u32 id;
>> + s32 value;
>> + } const gain_ctrls[] = {
>> + { "Analogue Gain m0", V4L2_CID_CCS_ANALOGUE_GAIN_M0,
>
> Why lower case 'm0/1' and 'c0/1'? It looks odd.
>
>> + CCS_LIM(sensor, ANALOG_GAIN_M0), },
>> + { "Analogue Gain c0", V4L2_CID_CCS_ANALOGUE_GAIN_C0,
>> + CCS_LIM(sensor, ANALOG_GAIN_C0), },
>> + { "Analogue Gain m1", V4L2_CID_CCS_ANALOGUE_GAIN_M1,
>> + CCS_LIM(sensor, ANALOG_GAIN_M1), },
>> + { "Analogue Gain c1", V4L2_CID_CCS_ANALOGUE_GAIN_C1,
>> + CCS_LIM(sensor, ANALOG_GAIN_C1), },
>> + };
>> + struct v4l2_ctrl_config ctrl_cfg = {
>> + .type = V4L2_CTRL_TYPE_INTEGER,
>> + .ops = &ccs_ctrl_ops,
>> + .flags = V4L2_CTRL_FLAG_READ_ONLY,
>> + .step = 1,
>> + };
>
> This looks a bit weird. Most drivers just define each control separately in
> a static const struct v4l2_ctrl_config, then add them with v4l2_ctrl_new_custom.
>
> Now the control definition data is split up in two data structures.
>
> It's not wrong, it is just non-standard, and a bit harder to review.
Ignore this as well, it's because some values aren't constant.
Regards,
Hans
>
>> + unsigned int i;
>> +
>> + for (i = 0; i < ARRAY_SIZE(gain_ctrls); i++) {
>> + ctrl_cfg.name = gain_ctrls[i].name;
>> + ctrl_cfg.id = gain_ctrls[i].id;
>> + ctrl_cfg.min = ctrl_cfg.max = ctrl_cfg.def =
>> + gain_ctrls[i].value;
>> +
>> + v4l2_ctrl_new_custom(&sensor->pixel_array->ctrl_handler,
>> + &ctrl_cfg, NULL);
>> + }
>> +
>> v4l2_ctrl_new_std(&sensor->pixel_array->ctrl_handler,
>> &ccs_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
>> CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN),
>> @@ -788,6 +821,7 @@ static int ccs_init_controls(struct ccs_sensor *sensor)
>> 1U),
>> CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN));
>> }
>> + }
>>
>> if (CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) ==
>> CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL ||
>>
>
> Regards,
>
> Hans
>
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 033/106] ccs: Add CCS static data parser library
2020-11-05 11:18 ` Sakari Ailus
@ 2020-11-05 12:53 ` Mauro Carvalho Chehab
2020-11-16 12:05 ` Sakari Ailus
0 siblings, 1 reply; 146+ messages in thread
From: Mauro Carvalho Chehab @ 2020-11-05 12:53 UTC (permalink / raw)
To: Sakari Ailus; +Cc: linux-media
Em Thu, 5 Nov 2020 13:18:07 +0200
Sakari Ailus <sakari.ailus@linux.intel.com> escreveu:
> Hi Mauro,
>
> Thanks for the review.
>
> On Thu, Nov 05, 2020 at 11:50:32AM +0100, Mauro Carvalho Chehab wrote:
>
> ...
>
> > > +struct __ccs_data_block_end {
> > > + uint8_t crc[4];
> > > +} __attribute__((packed));
> > > +
> > > +#endif /* __CCS_DATA_DEFS_H__ */
> >
> > Nitpick: why all the above struct/enums start with "__"?
>
> We have two sets of data structure: those that are related to the binary
> file format (these, so they're packed) as well as the in-kernel
> representation. So I've used the underscores to designate these are the
> binary format ones. They're only used in ccs-data.c.
>
Ok for me, but, IMHO, you should document it somewhere about such
convention.
Thanks,
Mauro
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 100/106] ccs: Add support for analogue gain coefficient controls
2020-11-05 12:46 ` Hans Verkuil
2020-11-05 12:50 ` Hans Verkuil
@ 2020-11-05 12:55 ` Sakari Ailus
1 sibling, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-11-05 12:55 UTC (permalink / raw)
To: Hans Verkuil; +Cc: linux-media
Hi Hans,
Thank you for the review!
On Thu, Nov 05, 2020 at 01:46:46PM +0100, Hans Verkuil wrote:
> On 07/10/2020 10:45, Sakari Ailus wrote:
> > Add four controls for reading CCS analogue gain coefficients. The
> > values are constants that are device specific.
> >
> > Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> > ---
> > drivers/media/i2c/ccs/ccs-core.c | 38 ++++++++++++++++++++++++++++++--
> > 1 file changed, 36 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
> > index d6d6aeceb415..2a507b63bafc 100644
> > --- a/drivers/media/i2c/ccs/ccs-core.c
> > +++ b/drivers/media/i2c/ccs/ccs-core.c
> > @@ -28,6 +28,7 @@
> > #include <linux/v4l2-mediabus.h>
> > #include <media/v4l2-fwnode.h>
> > #include <media/v4l2-device.h>
> > +#include <uapi/linux/ccs.h>
> >
> > #include "ccs.h"
> >
> > @@ -772,14 +773,46 @@ static int ccs_init_controls(struct ccs_sensor *sensor)
> > struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
> > int rval;
> >
> > - rval = v4l2_ctrl_handler_init(&sensor->pixel_array->ctrl_handler, 13);
> > + rval = v4l2_ctrl_handler_init(&sensor->pixel_array->ctrl_handler, 17);
> > if (rval)
> > return rval;
> >
> > sensor->pixel_array->ctrl_handler.lock = &sensor->mutex;
> >
> > switch (CCS_LIM(sensor, ANALOG_GAIN_CAPABILITY)) {
> > - case CCS_ANALOG_GAIN_CAPABILITY_GLOBAL:
> > + case CCS_ANALOG_GAIN_CAPABILITY_GLOBAL: {
> > + struct {
>
> Can this be static?
CCS_LIM(sensor, ...) translates to a value that is specific to a given
model of a camera sensor, it's not a constant.
>
> > + const char *name;
> > + u32 id;
> > + s32 value;
> > + } const gain_ctrls[] = {
> > + { "Analogue Gain m0", V4L2_CID_CCS_ANALOGUE_GAIN_M0,
>
> Why lower case 'm0/1' and 'c0/1'? It looks odd.
The spec uses lower case to refer to [cm][01].
I can use upper case if you prefer though.
>
> > + CCS_LIM(sensor, ANALOG_GAIN_M0), },
> > + { "Analogue Gain c0", V4L2_CID_CCS_ANALOGUE_GAIN_C0,
> > + CCS_LIM(sensor, ANALOG_GAIN_C0), },
> > + { "Analogue Gain m1", V4L2_CID_CCS_ANALOGUE_GAIN_M1,
> > + CCS_LIM(sensor, ANALOG_GAIN_M1), },
> > + { "Analogue Gain c1", V4L2_CID_CCS_ANALOGUE_GAIN_C1,
> > + CCS_LIM(sensor, ANALOG_GAIN_C1), },
> > + };
> > + struct v4l2_ctrl_config ctrl_cfg = {
> > + .type = V4L2_CTRL_TYPE_INTEGER,
> > + .ops = &ccs_ctrl_ops,
> > + .flags = V4L2_CTRL_FLAG_READ_ONLY,
> > + .step = 1,
> > + };
>
> This looks a bit weird. Most drivers just define each control separately in
> a static const struct v4l2_ctrl_config, then add them with v4l2_ctrl_new_custom.
>
> Now the control definition data is split up in two data structures.
>
> It's not wrong, it is just non-standard, and a bit harder to review.
>
> > + unsigned int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(gain_ctrls); i++) {
> > + ctrl_cfg.name = gain_ctrls[i].name;
> > + ctrl_cfg.id = gain_ctrls[i].id;
> > + ctrl_cfg.min = ctrl_cfg.max = ctrl_cfg.def =
> > + gain_ctrls[i].value;
> > +
> > + v4l2_ctrl_new_custom(&sensor->pixel_array->ctrl_handler,
> > + &ctrl_cfg, NULL);
> > + }
> > +
> > v4l2_ctrl_new_std(&sensor->pixel_array->ctrl_handler,
> > &ccs_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
> > CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN),
> > @@ -788,6 +821,7 @@ static int ccs_init_controls(struct ccs_sensor *sensor)
> > 1U),
> > CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN));
> > }
> > + }
> >
> > if (CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) ==
> > CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL ||
> >
>
--
Regards,
Sakari Ailus
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 099/106] v4l: uapi: ccs: Add controls for analogue gain constants
2020-10-07 8:45 ` [PATCH v2 099/106] v4l: uapi: ccs: Add controls for analogue gain constants Sakari Ailus
2020-11-05 12:41 ` Hans Verkuil
@ 2020-11-05 12:56 ` Hans Verkuil
2020-11-05 12:58 ` Sakari Ailus
1 sibling, 1 reply; 146+ messages in thread
From: Hans Verkuil @ 2020-11-05 12:56 UTC (permalink / raw)
To: Sakari Ailus, linux-media
On 07/10/2020 10:45, Sakari Ailus wrote:
> Add a V4L2 controls for analogue gai constants required to control
> analogue gain. The values are device specific and thus need to be obtained
> from the driver.
>
> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> ---
> MAINTAINERS | 1 +
> include/uapi/linux/ccs.h | 14 ++++++++++++++
> 2 files changed, 15 insertions(+)
> create mode 100644 include/uapi/linux/ccs.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index b72f666b8b60..c173e503b0b7 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -11569,6 +11569,7 @@ F: drivers/media/i2c/ccs/
> F: drivers/media/i2c/ccs-pll.c
> F: drivers/media/i2c/ccs-pll.h
> F: include/uapi/linux/smiapp.h
> +F: include/uapi/linux/ccs.h
>
> MIPS
> M: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> diff --git a/include/uapi/linux/ccs.h b/include/uapi/linux/ccs.h
> new file mode 100644
> index 000000000000..bcdce95955b0
> --- /dev/null
> +++ b/include/uapi/linux/ccs.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: GPL-2.0-only AND BSD-3-Clause */
> +/* Copyright (C) 2020 Intel Corporation */
> +
> +#ifndef __UAPI_CCS_H__
> +#define __UAPI_CCS_H__
What does CCS stand for? Provide a reference to the standard as well.
Just looking at this header doesn't give you any clue as to what it
related to.
Regards,
Hans
> +
> +#include <linux/videodev2.h>
> +
> +#define V4L2_CID_CCS_ANALOGUE_GAIN_M0 (V4L2_CID_USER_CCS_BASE + 1)
> +#define V4L2_CID_CCS_ANALOGUE_GAIN_C0 (V4L2_CID_USER_CCS_BASE + 2)
> +#define V4L2_CID_CCS_ANALOGUE_GAIN_M1 (V4L2_CID_USER_CCS_BASE + 3)
> +#define V4L2_CID_CCS_ANALOGUE_GAIN_C1 (V4L2_CID_USER_CCS_BASE + 4)
> +
> +#endif
>
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 099/106] v4l: uapi: ccs: Add controls for analogue gain constants
2020-11-05 12:56 ` Hans Verkuil
@ 2020-11-05 12:58 ` Sakari Ailus
0 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-11-05 12:58 UTC (permalink / raw)
To: Hans Verkuil; +Cc: linux-media
Hi Hans,
On Thu, Nov 05, 2020 at 01:56:02PM +0100, Hans Verkuil wrote:
> On 07/10/2020 10:45, Sakari Ailus wrote:
> > Add a V4L2 controls for analogue gai constants required to control
> > analogue gain. The values are device specific and thus need to be obtained
> > from the driver.
> >
> > Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> > ---
> > MAINTAINERS | 1 +
> > include/uapi/linux/ccs.h | 14 ++++++++++++++
> > 2 files changed, 15 insertions(+)
> > create mode 100644 include/uapi/linux/ccs.h
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index b72f666b8b60..c173e503b0b7 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -11569,6 +11569,7 @@ F: drivers/media/i2c/ccs/
> > F: drivers/media/i2c/ccs-pll.c
> > F: drivers/media/i2c/ccs-pll.h
> > F: include/uapi/linux/smiapp.h
> > +F: include/uapi/linux/ccs.h
> >
> > MIPS
> > M: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> > diff --git a/include/uapi/linux/ccs.h b/include/uapi/linux/ccs.h
> > new file mode 100644
> > index 000000000000..bcdce95955b0
> > --- /dev/null
> > +++ b/include/uapi/linux/ccs.h
> > @@ -0,0 +1,14 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only AND BSD-3-Clause */
> > +/* Copyright (C) 2020 Intel Corporation */
> > +
> > +#ifndef __UAPI_CCS_H__
> > +#define __UAPI_CCS_H__
>
> What does CCS stand for? Provide a reference to the standard as well.
>
> Just looking at this header doesn't give you any clue as to what it
> related to.
I'll add references to driver documentation I'm about to write to address
Mauro's review comments. CCS stands for Camera Command Set.
The spec can be found here:
<URL:https://www.mipi.org/specifications/camera-command-set>
--
Regards,
Sakari Ailus
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 105/106] ccs: Add shading correction and luminance correction level controls
2020-10-07 8:45 ` [PATCH v2 105/106] ccs: Add shading correction and luminance correction level controls Sakari Ailus
2020-11-05 12:42 ` Mauro Carvalho Chehab
@ 2020-11-05 13:03 ` Hans Verkuil
2020-11-16 13:50 ` Sakari Ailus
1 sibling, 1 reply; 146+ messages in thread
From: Hans Verkuil @ 2020-11-05 13:03 UTC (permalink / raw)
To: Sakari Ailus, linux-media
On 07/10/2020 10:45, Sakari Ailus wrote:
> Add controls for supporting lens shading correction.
>
> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> ---
> drivers/media/i2c/ccs/ccs-core.c | 74 ++++++++++++++++++++++++++++++++
> 1 file changed, 74 insertions(+)
>
> diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
> index 0ba06a580951..10ed3d01af16 100644
> --- a/drivers/media/i2c/ccs/ccs-core.c
> +++ b/drivers/media/i2c/ccs/ccs-core.c
> @@ -757,6 +757,25 @@ static int ccs_set_ctrl(struct v4l2_ctrl *ctrl)
> case V4L2_CID_TEST_PATTERN_GREENB:
> rval = ccs_write(sensor, TEST_DATA_GREENB, ctrl->val);
>
> + break;
> + case V4L2_CID_CCS_SHADING_CORRECTION:
> + if (!(CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) &
> + (CCS_SHADING_CORRECTION_CAPABILITY_COLOR_SHADING |
> + CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION)))
> + break;
> +
> + rval = ccs_write(sensor, SHADING_CORRECTION_EN,
> + ctrl->val ? CCS_SHADING_CORRECTION_EN_ENABLE :
> + 0);
> +
> + break;
> + case V4L2_CID_CCS_LUMINANCE_SHADING_CORRECTION:
> + if (!(CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) &
> + CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION))
> + break;
> +
> + rval = ccs_write(sensor, LUMINANCE_CORRECTION_LEVEL, ctrl->val);
> +
> break;
> case V4L2_CID_PIXEL_RATE:
> /* For v4l2_ctrl_s_ctrl_int64() used internally. */
> @@ -878,6 +897,61 @@ static int ccs_init_controls(struct ccs_sensor *sensor)
> }
> }
>
> + if (CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) &
> + CCS_SHADING_CORRECTION_CAPABILITY_COLOR_SHADING) {
> + const struct v4l2_ctrl_config ctrl_cfg = {
Can be static.
> + .name = "Shading Correction",
Should this perhaps be called "Chroma Shading Correction"? Since there is a luminance
shading correction as well...
Since these controls are all CCS specific, should the names of these controls begin
with "CCS "? (Not just the controls in this patch, but also from previous patches).
> + .type = V4L2_CTRL_TYPE_BOOLEAN,
> + .id = V4L2_CID_CCS_SHADING_CORRECTION,
> + .ops = &ccs_ctrl_ops,
> + .max = 1,
> + .step = 1,
> + };
> +
> + v4l2_ctrl_new_custom(&sensor->pixel_array->ctrl_handler,
> + &ctrl_cfg, NULL);
> + }
> +
> + if (CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) &
> + CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION) {
> + const struct v4l2_ctrl_config ctrl_cfg = {
Can be static.
> + .name = "Luminance Shading Correction",
> + .type = V4L2_CTRL_TYPE_BOOLEAN,
> + .id = V4L2_CID_CCS_LUMINANCE_SHADING_CORRECTION,
> + .ops = &ccs_ctrl_ops,
> + .max = 255,
> + .step = 1,
> + .def = 128,
> + };
> +
> + v4l2_ctrl_new_custom(&sensor->pixel_array->ctrl_handler,
> + &ctrl_cfg, NULL);
> + }
> +
> + if (CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) &
> + (CCS_SHADING_CORRECTION_CAPABILITY_COLOR_SHADING |
> + CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION)) {
> + u32 val =
> + ((CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) &
> + CCS_SHADING_CORRECTION_CAPABILITY_COLOR_SHADING) ?
> + V4L2_CCS_SHADING_CORRECTION_COLOUR : 0) |
> + ((CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) &
> + CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION) ?
> + V4L2_CCS_SHADING_CORRECTION_LUMINANCE : 0);
> + const struct v4l2_ctrl_config ctrl_cfg = {
> + .name = "Shading Correction Capability",
> + .type = V4L2_CTRL_TYPE_BITMASK,
> + .id = V4L2_CID_CCS_SHADING_CORRECTION_CAPABILITY,
> + .ops = &ccs_ctrl_ops,
> + .max = val,
> + .def = val,
> + .flags = V4L2_CTRL_FLAG_READ_ONLY,
> + };
Is this needed? If e.g. V4L2_CCS_SHADING_CORRECTION_COLOUR is not supported,
then the V4L2_CID_CCS_SHADING_CORRECTION control is simply not created.
So calling VIDIOC_QUERYCTRL would simply fail and so indicate that this
capability is not present.
If it really is needed, then having two bool controls makes more sense
because a bitmask is less intuitive.
Regards,
Hans
> +
> + v4l2_ctrl_new_custom(&sensor->pixel_array->ctrl_handler,
> + &ctrl_cfg, NULL);
> + }
> +
> if (CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) ==
> CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL ||
> CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) ==
>
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 105/106] ccs: Add shading correction and luminance correction level controls
2020-11-05 12:42 ` Mauro Carvalho Chehab
@ 2020-11-05 16:29 ` Sakari Ailus
0 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-11-05 16:29 UTC (permalink / raw)
To: Mauro Carvalho Chehab; +Cc: linux-media, Hans Verkuil
Hi Mauro,
Thanks for the review comments.
On Thu, Nov 05, 2020 at 01:42:43PM +0100, Mauro Carvalho Chehab wrote:
> Em Wed, 7 Oct 2020 11:45:56 +0300
> Sakari Ailus <sakari.ailus@linux.intel.com> escreveu:
>
> > Add controls for supporting lens shading correction.
> >
> > Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
>
> For patches 098 to 105, we should at least have those new controls
> documented at the uAPI documents.
Agreed.
>
> I'm not convinced yet that we shouldn't instead place them inside
> V4L2_CTRL_CLASS_CAMERA.
>
> As those are part of a MIPI standard, I won't doubt that sooner or
> later, other drivers may need them.
They are part of a MIPI standard, but that standard defines a control
interface for camera sensors which this driver uses. I don't see a need to
implement other drivers for devices this driver already supports.
Note that while MIPI standards are originally centered around cross-chip
busses, the functionality that is being controlled here is entirely local
to the device.
Quite a few of the controls are still somehow specific to the device.
That said, the same analogue gain model is very likely present on a range
of devices even though they are not CCS (or SMIA) compatible, for
historical reasons. Perhaps these could be actually made a single array
control in the camera control class, with indices defined for the different
factors.
--
Kind regards,
Sakari Ailus
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 033/106] ccs: Add CCS static data parser library
2020-11-05 12:53 ` Mauro Carvalho Chehab
@ 2020-11-16 12:05 ` Sakari Ailus
0 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-11-16 12:05 UTC (permalink / raw)
To: Mauro Carvalho Chehab; +Cc: linux-media
On Thu, Nov 05, 2020 at 01:53:50PM +0100, Mauro Carvalho Chehab wrote:
> Em Thu, 5 Nov 2020 13:18:07 +0200
> Sakari Ailus <sakari.ailus@linux.intel.com> escreveu:
>
> > Hi Mauro,
> >
> > Thanks for the review.
> >
> > On Thu, Nov 05, 2020 at 11:50:32AM +0100, Mauro Carvalho Chehab wrote:
> >
> > ...
> >
> > > > +struct __ccs_data_block_end {
> > > > + uint8_t crc[4];
> > > > +} __attribute__((packed));
> > > > +
> > > > +#endif /* __CCS_DATA_DEFS_H__ */
> > >
> > > Nitpick: why all the above struct/enums start with "__"?
> >
> > We have two sets of data structure: those that are related to the binary
> > file format (these, so they're packed) as well as the in-kernel
> > representation. So I've used the underscores to designate these are the
> > binary format ones. They're only used in ccs-data.c.
> >
>
> Ok for me, but, IMHO, you should document it somewhere about such
> convention.
I've added descriptions to the two headers that contain the definitions.
That might not hurt elsewhere either, at least for the added files.
--
Sakari Ailus
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 105/106] ccs: Add shading correction and luminance correction level controls
2020-11-05 13:03 ` Hans Verkuil
@ 2020-11-16 13:50 ` Sakari Ailus
0 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-11-16 13:50 UTC (permalink / raw)
To: Hans Verkuil; +Cc: linux-media
Hi Hans,
On Thu, Nov 05, 2020 at 02:03:37PM +0100, Hans Verkuil wrote:
> On 07/10/2020 10:45, Sakari Ailus wrote:
...
> > + .name = "Luminance Shading Correction",
> > + .type = V4L2_CTRL_TYPE_BOOLEAN,
> > + .id = V4L2_CID_CCS_LUMINANCE_SHADING_CORRECTION,
> > + .ops = &ccs_ctrl_ops,
> > + .max = 255,
> > + .step = 1,
> > + .def = 128,
> > + };
> > +
> > + v4l2_ctrl_new_custom(&sensor->pixel_array->ctrl_handler,
> > + &ctrl_cfg, NULL);
> > + }
> > +
> > + if (CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) &
> > + (CCS_SHADING_CORRECTION_CAPABILITY_COLOR_SHADING |
> > + CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION)) {
> > + u32 val =
> > + ((CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) &
> > + CCS_SHADING_CORRECTION_CAPABILITY_COLOR_SHADING) ?
> > + V4L2_CCS_SHADING_CORRECTION_COLOUR : 0) |
> > + ((CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) &
> > + CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION) ?
> > + V4L2_CCS_SHADING_CORRECTION_LUMINANCE : 0);
> > + const struct v4l2_ctrl_config ctrl_cfg = {
> > + .name = "Shading Correction Capability",
> > + .type = V4L2_CTRL_TYPE_BITMASK,
> > + .id = V4L2_CID_CCS_SHADING_CORRECTION_CAPABILITY,
> > + .ops = &ccs_ctrl_ops,
> > + .max = val,
> > + .def = val,
> > + .flags = V4L2_CTRL_FLAG_READ_ONLY,
> > + };
>
> Is this needed? If e.g. V4L2_CCS_SHADING_CORRECTION_COLOUR is not supported,
> then the V4L2_CID_CCS_SHADING_CORRECTION control is simply not created.
> So calling VIDIOC_QUERYCTRL would simply fail and so indicate that this
> capability is not present.
>
> If it really is needed, then having two bool controls makes more sense
> because a bitmask is less intuitive.
The CCS shading correction support has two capabilities but one bit to
control both. Another (luminance correction) has the correction level
(buggy in this patch, I'll fix for v4), so two controls aren't enough to
tell what is being corrected; is it colour shading or not? Luminance
correction level support is revealed by the luminance correction level
control as well.
So I guess you could also have a boolean control to tell colour correction
is supported.
I guess could also just omit the capability control now and see if someone
needs it. I'd expect this to be rarely needed information.
--
Kind regards,
Sakari Ailus
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 029/106] ccs: Remove the I²C ID table
2020-11-05 9:34 ` Mauro Carvalho Chehab
@ 2020-11-18 22:15 ` Sakari Ailus
0 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-11-18 22:15 UTC (permalink / raw)
To: Mauro Carvalho Chehab; +Cc: linux-media
Hi Mauro,
On Thu, Nov 05, 2020 at 10:34:45AM +0100, Mauro Carvalho Chehab wrote:
> Em Wed, 7 Oct 2020 11:44:42 +0300
> Sakari Ailus <sakari.ailus@linux.intel.com> escreveu:
>
> > The I²C ID table is no longer needed; remove it.
>
> Why not? Please provide more information.
>
> In summary, please change the description in order to answer the
> following questions:
>
> For OF-based drivers, removing I2C probing won't cause any harm,
> as the patch is keeping css_of_able, but wouldn't it affect other
> drivers that could, for example, be using ACPI, instead?
>
> Or is this driver incompatible with other probing methods?
ACPI doesn't need this anymore. It did though.
Platform data support has been (gradually) removed so I believe this can be
removed, too. If someone can show it has a purpose, I don't have objections
to reverting this later either.
--
Regards,
Sakari Ailus
^ permalink raw reply [flat|nested] 146+ messages in thread
* Re: [PATCH v2 063/106] ccs-pll: Document the structs in the header as well as the function
2020-11-05 12:18 ` Mauro Carvalho Chehab
@ 2020-12-02 18:02 ` Sakari Ailus
0 siblings, 0 replies; 146+ messages in thread
From: Sakari Ailus @ 2020-12-02 18:02 UTC (permalink / raw)
To: Mauro Carvalho Chehab; +Cc: linux-media
Hi Mauro,
On Thu, Nov 05, 2020 at 01:18:45PM +0100, Mauro Carvalho Chehab wrote:
> Em Wed, 7 Oct 2020 11:45:14 +0300
> Sakari Ailus <sakari.ailus@linux.intel.com> escreveu:
>
> > The CCS pll is used by the CCS driver at the moment, but documenting the
> > interface makes sense. It's non-trivial and the calculator could be used
> > elsewhere.
>
> LFTM.
>
> It could make sense to add a .. kernel-doc:: markup at the documentation
> somewhere.
Thanks for the comments.
I've added additional patch later in the set to add this to the
documentation build.
--
Sakari Ailus
^ permalink raw reply [flat|nested] 146+ messages in thread
end of thread, other threads:[~2020-12-02 18:04 UTC | newest]
Thread overview: 146+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-10-07 8:44 [PATCH v2 000/106] CCS driver Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 002/106] smiapp: Use CCS register flags Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 003/106] smiapp: Calculate CCS limit offsets and limit buffer size Sakari Ailus
2020-11-05 7:43 ` Mauro Carvalho Chehab
2020-11-05 7:58 ` Mauro Carvalho Chehab
2020-11-05 8:01 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 004/106] smiapp: Remove macros for defining registers, merge definitions Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 005/106] smiapp: Add macros for accessing CCS registers Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 006/106] smiapp: Use MIPI CCS version and manufacturer ID information Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 007/106] smiapp: Read CCS limit values Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 008/106] smiapp: Switch to CCS limits Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 009/106] smiapp: Obtain frame descriptor from " Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 010/106] smiapp: Use CCS limits in reading data format descriptors Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 011/106] smiapp: Use CCS limits in reading binning capabilities Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 012/106] smiapp: Use CCS registers Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 013/106] smiapp: Remove quirk function for writing a single 8-bit register Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 014/106] smiapp: Rename register access functions Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 015/106] smiapp: Internal rename to CCS Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 016/106] smiapp: Differentiate CCS sensors from SMIA in subdev naming Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 017/106] smiapp: Rename as "ccs" Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 018/106] ccs: Remove profile concept Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 019/106] ccs: Give all subdevs a function Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 027/106] ccs: Request for "reset" GPIO Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 028/106] ccs: Add MIPI CCS compatible strings Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 029/106] ccs: Remove the I²C ID table Sakari Ailus
2020-11-05 9:34 ` Mauro Carvalho Chehab
2020-11-18 22:15 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 030/106] ccs: Remove remaining support for platform data Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 031/106] ccs: Make hwcfg part of the device specific struct Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 032/106] ccs: Fix obtaining bus information from firmware Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 033/106] ccs: Add CCS static data parser library Sakari Ailus
2020-11-05 10:50 ` Mauro Carvalho Chehab
2020-11-05 11:18 ` Sakari Ailus
2020-11-05 12:53 ` Mauro Carvalho Chehab
2020-11-16 12:05 ` Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 034/106] ccs: Combine revision number major and minor into one Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 035/106] ccs: Read CCS static data from firmware binaries Sakari Ailus
2020-11-05 10:56 ` Mauro Carvalho Chehab
2020-10-07 8:44 ` [PATCH v2 036/106] ccs: Stop reading arrays after the first zero Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 037/106] ccs: The functions to get compose or crop rectangle never return NULL Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 038/106] ccs: Replace somewhat harsh internal checks based on BUG with WARN_ON Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 039/106] ccs: Refactor register reading a little Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 040/106] ccs: Make real to integer number conversion optional Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 041/106] ccs: Move limit value real to integer conversion from read to access time Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 042/106] ccs: Read ireal numbers correctly Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 043/106] smiapp-pll: Rename as ccs-pll Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 044/106] ccs-pll: Fix MODULE_LICENSE Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 045/106] ccs: Change my e-mail address Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 046/106] ccs: Add support for manufacturer regs from sensor and module files Sakari Ailus
2020-11-05 11:34 ` Mauro Carvalho Chehab
2020-11-05 11:56 ` Sakari Ailus
2020-11-05 12:46 ` Mauro Carvalho Chehab
2020-10-07 8:45 ` [PATCH v2 047/106] ccs: Use static data read-only registers Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 048/106] ccs: Clean up runtime PM usage Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 049/106] ccs: Wrap long lines, unwrap short ones Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 050/106] ccs: Add device compatible identifiers for telling SMIA and CCS apart Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 051/106] ccs: Use longer pre-I²C sleep for CCS compliant devices Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 052/106] ccs: Remove unnecessary delays from power-up sequence Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 055/106] ccs: Use all regulators Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 056/106] ccs-pll: Don't use div_u64 to divide a 32-bit number Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 057/106] ccs-pll: Split limits and PLL configuration into front and back parts Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 058/106] ccs-pll: Use correct VT divisor for calculating VT SYS divisor Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 059/106] ccs-pll: End search if there are no better values available Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 060/106] ccs-pll: Remove parallel bus support Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 061/106] ccs-pll: Differentiate between CSI-2 D-PHY and C-PHY Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 062/106] ccs-pll: Move the flags field down, away from 8-bit fields Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 063/106] ccs-pll: Document the structs in the header as well as the function Sakari Ailus
2020-11-05 12:18 ` Mauro Carvalho Chehab
2020-12-02 18:02 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 064/106] ccs-pll: Use the BIT macro Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 065/106] ccs-pll: Begin calculation from OP system clock frequency Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 066/106] ccs-pll: Fix condition for pre-PLL divider lower bound Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 067/106] ccs-pll: Avoid overflow in pre-PLL divisor lower bound search Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 068/106] ccs-pll: Fix comment on check against maximum PLL multiplier Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 069/106] ccs-pll: Fix check for PLL multiplier upper bound Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 070/106] ccs-pll: Use explicit 32-bit unsigned type Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 071/106] ccs-pll: Add support for lane speed model Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 072/106] ccs: " Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 073/106] ccs-pll: Add support for decoupled OP domain calculation Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 074/106] ccs-pll: Add support for extended input PLL clock divider Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 075/106] ccs-pll: Support two cycles per pixel on OP domain Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 076/106] ccs-pll: Add support flexible OP PLL pixel clock divider Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 077/106] ccs-pll: Add sanity checks Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 078/106] ccs-pll: Add C-PHY support Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 079/106] ccs-pll: Split off VT subtree calculation Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 080/106] ccs-pll: Check for derating and overrating, support non-derating sensors Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 081/106] ccs-pll: Better separate OP and VT sub-tree calculation Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 082/106] ccs-pll: Print relevant information on PLL tree Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 083/106] ccs-pll: Rework bounds checks Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 084/106] ccs-pll: Make VT divisors 16-bit Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 085/106] ccs-pll: Fix VT post-PLL divisor calculation Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 086/106] ccs-pll: Separate VT divisor limit calculation from the rest Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 087/106] ccs-pll: Add trivial dual PLL support Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 088/106] ccs: Dual " Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 089/106] ccs-pll: Add support for DDR OP system and pixel clocks Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 090/106] ccs: Add support for DDR OP SYS and OP PIX clocks Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 091/106] ccs: Print written register values Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 092/106] ccs-pll: Print pixel rates Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 093/106] ccs: Add support for obtaining C-PHY configuration from firmware Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 094/106] ccs: Add digital gain support Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 095/106] ccs: Add support for old-style SMIA digital gain Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 096/106] ccs: Remove analogue gain field Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 097/106] ccs: Only add analogue gain control if the device supports it Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 098/106] v4l: uapi: Add user control base for CCS controls Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 099/106] v4l: uapi: ccs: Add controls for analogue gain constants Sakari Ailus
2020-11-05 12:41 ` Hans Verkuil
2020-11-05 12:47 ` Sakari Ailus
2020-11-05 12:56 ` Hans Verkuil
2020-11-05 12:58 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 100/106] ccs: Add support for analogue gain coefficient controls Sakari Ailus
2020-11-05 12:46 ` Hans Verkuil
2020-11-05 12:50 ` Hans Verkuil
2020-11-05 12:55 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 101/106] v4l: uapi: ccs: Add controls for CCS alternative analogue gain Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 102/106] ccs: Add support for alternate analogue global gain Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 103/106] ccs: Add debug prints for MSR registers Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 104/106] v4l: uapi: ccs: Add CCS controls for shading correction Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 105/106] ccs: Add shading correction and luminance correction level controls Sakari Ailus
2020-11-05 12:42 ` Mauro Carvalho Chehab
2020-11-05 16:29 ` Sakari Ailus
2020-11-05 13:03 ` Hans Verkuil
2020-11-16 13:50 ` Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 106/106] ccs: Add CCS ACPI device ID Sakari Ailus
2020-11-05 12:44 ` Mauro Carvalho Chehab
2020-11-05 7:19 ` [PATCH v2 001/106] smiapp: Generate CCS register definitions and limits Mauro Carvalho Chehab
2020-11-05 8:01 ` Sakari Ailus
2020-11-05 9:04 ` Mauro Carvalho Chehab
2020-10-07 8:44 ` [PATCH v2 020/106] dt-bindings: nokia,smia: Fix link-frequencies documentation Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 021/106] dt-bindings: nokia,smia: Make vana-supply optional Sakari Ailus
2020-10-07 8:44 ` [PATCH v2 022/106] dt-bindings: nokia,smia: Remove nokia,nvm-size property Sakari Ailus
2020-10-07 16:04 ` Rob Herring
2020-10-07 8:45 ` [PATCH v2 023/106] dt-bindings: nokia,smia: Convert to YAML Sakari Ailus
2020-10-07 16:06 ` Rob Herring
2020-10-07 8:45 ` [PATCH v2 024/106] dt-bindings: nokia,smia: Use better active polarity for reset Sakari Ailus
2020-10-07 8:45 ` [PATCH v2 025/106] dt-bindings: nokia,smia: Amend SMIA bindings with MIPI CCS support Sakari Ailus
2020-10-07 16:07 ` Rob Herring
2020-10-07 8:45 ` [PATCH v2 026/106] dt-bindings: mipi-ccs: Add bus-type for C-PHY support Sakari Ailus
2020-10-07 13:52 ` Rob Herring
2020-10-07 14:46 ` Sakari Ailus
2020-10-07 14:49 ` [PATCH v3 " Sakari Ailus
2020-10-07 16:24 ` Rob Herring
2020-10-07 8:45 ` [PATCH v2 053/106] dt-bindings: mipi,ccs: Don't mention vana voltage Sakari Ailus
2020-10-07 16:07 ` Rob Herring
2020-10-07 8:45 ` [PATCH v2 054/106] dt-bindings: mipi,ccs: Add vcore and vio supplies Sakari Ailus
2020-10-07 16:08 ` Rob Herring
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.