From: Yifei Jiang <jiangyifei@huawei.com> To: <qemu-devel@nongnu.org>, <qemu-riscv@nongnu.org> Cc: zhang.zhanghailiang@huawei.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, victor.zhangxiaofeng@huawei.com, richard.henderson@linaro.org, Yifei Jiang <jiangyifei@huawei.com>, Alistair.Francis@wdc.com, yinyipeng1@huawei.com, palmer@dabbelt.com, wu.wubin@huawei.com, dengkai1@huawei.com Subject: [PATCH V2 2/5] target/riscv: Add PMP state description Date: Sat, 10 Oct 2020 16:06:20 +0800 [thread overview] Message-ID: <20201010080623.768-3-jiangyifei@huawei.com> (raw) In-Reply-To: <20201010080623.768-1-jiangyifei@huawei.com> In the case of supporting PMP feature, add PMP state description to vmstate_riscv_cpu. 'vmstate_pmp_addr' and 'num_rules' could be regenerated by pmp_update_rule(). But there exists the problem of updating num_rules repeatedly in pmp_update_rule(). So here extracts pmp_update_rule_addr() and pmp_update_rule_nums() to update 'vmstate_pmp_addr' and 'num_rules' respectively. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> --- target/riscv/machine.c | 50 ++++++++++++++++++++++++++++++++++++++++++ target/riscv/pmp.c | 29 ++++++++++++++---------- target/riscv/pmp.h | 2 ++ 3 files changed, 70 insertions(+), 11 deletions(-) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index af2828a80a..8fffd2db3f 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -22,6 +22,52 @@ #include "sysemu/kvm.h" #include "migration/cpu.h" +static bool pmp_needed(void *opaque) +{ + RISCVCPU *cpu = opaque; + CPURISCVState *env = &cpu->env; + + return riscv_feature(env, RISCV_FEATURE_PMP); +} + +static int pmp_post_load(void *opaque, int version_id) +{ + RISCVCPU *cpu = opaque; + CPURISCVState *env = &cpu->env; + int i; + + for (i = 0; i < MAX_RISCV_PMPS; i++) { + pmp_update_rule_addr(env, i); + } + pmp_update_rule_nums(env); + + return 0; +} + +static const VMStateDescription vmstate_pmp_entry = { + .name = "cpu/pmp/entry", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINTTL(addr_reg, pmp_entry_t), + VMSTATE_UINT8(cfg_reg, pmp_entry_t), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_pmp = { + .name = "cpu/pmp", + .version_id = 1, + .minimum_version_id = 1, + .needed = pmp_needed, + .post_load = pmp_post_load, + .fields = (VMStateField[]) { + VMSTATE_STRUCT_ARRAY(env.pmp_state.pmp, RISCVCPU, MAX_RISCV_PMPS, + 0, vmstate_pmp_entry, pmp_entry_t), + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_riscv_cpu = { .name = "cpu", .version_id = 1, @@ -73,5 +119,9 @@ const VMStateDescription vmstate_riscv_cpu = { VMSTATE_UINTTL(env.mstatush, RISCVCPU), #endif VMSTATE_END_OF_LIST() + }, + .subsections = (const VMStateDescription * []) { + &vmstate_pmp, + NULL } }; diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index c394e867f8..2eda8e1e2f 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -136,18 +136,8 @@ static void pmp_decode_napot(target_ulong a, target_ulong *sa, target_ulong *ea) } } - -/* Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea' - * end address values. - * This function is called relatively infrequently whereas the check that - * an address is within a pmp rule is called often, so optimise that one - */ -static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index) +void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index) { - int i; - - env->pmp_state.num_rules = 0; - uint8_t this_cfg = env->pmp_state.pmp[pmp_index].cfg_reg; target_ulong this_addr = env->pmp_state.pmp[pmp_index].addr_reg; target_ulong prev_addr = 0u; @@ -186,7 +176,13 @@ static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index) env->pmp_state.addr[pmp_index].sa = sa; env->pmp_state.addr[pmp_index].ea = ea; +} +void pmp_update_rule_nums(CPURISCVState *env) +{ + int i; + + env->pmp_state.num_rules = 0; for (i = 0; i < MAX_RISCV_PMPS; i++) { const uint8_t a_field = pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg); @@ -196,6 +192,17 @@ static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index) } } +/* Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea' + * end address values. + * This function is called relatively infrequently whereas the check that + * an address is within a pmp rule is called often, so optimise that one + */ +static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index) +{ + pmp_update_rule_addr(env, pmp_index); + pmp_update_rule_nums(env); +} + static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr) { int result = 0; diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h index 6a8f072871..6c6b4c9bef 100644 --- a/target/riscv/pmp.h +++ b/target/riscv/pmp.h @@ -62,5 +62,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, target_ulong size, pmp_priv_t priv, target_ulong mode); bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa, target_ulong *tlb_size); +void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index); +void pmp_update_rule_nums(CPURISCVState *env); #endif -- 2.19.1
WARNING: multiple messages have this Message-ID (diff)
From: Yifei Jiang <jiangyifei@huawei.com> To: <qemu-devel@nongnu.org>, <qemu-riscv@nongnu.org> Cc: <palmer@dabbelt.com>, <Alistair.Francis@wdc.com>, <sagark@eecs.berkeley.edu>, <kbastian@mail.uni-paderborn.de>, <richard.henderson@linaro.org>, <victor.zhangxiaofeng@huawei.com>, <wu.wubin@huawei.com>, <zhang.zhanghailiang@huawei.com>, <dengkai1@huawei.com>, <yinyipeng1@huawei.com>, Yifei Jiang <jiangyifei@huawei.com> Subject: [PATCH V2 2/5] target/riscv: Add PMP state description Date: Sat, 10 Oct 2020 16:06:20 +0800 [thread overview] Message-ID: <20201010080623.768-3-jiangyifei@huawei.com> (raw) In-Reply-To: <20201010080623.768-1-jiangyifei@huawei.com> In the case of supporting PMP feature, add PMP state description to vmstate_riscv_cpu. 'vmstate_pmp_addr' and 'num_rules' could be regenerated by pmp_update_rule(). But there exists the problem of updating num_rules repeatedly in pmp_update_rule(). So here extracts pmp_update_rule_addr() and pmp_update_rule_nums() to update 'vmstate_pmp_addr' and 'num_rules' respectively. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> --- target/riscv/machine.c | 50 ++++++++++++++++++++++++++++++++++++++++++ target/riscv/pmp.c | 29 ++++++++++++++---------- target/riscv/pmp.h | 2 ++ 3 files changed, 70 insertions(+), 11 deletions(-) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index af2828a80a..8fffd2db3f 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -22,6 +22,52 @@ #include "sysemu/kvm.h" #include "migration/cpu.h" +static bool pmp_needed(void *opaque) +{ + RISCVCPU *cpu = opaque; + CPURISCVState *env = &cpu->env; + + return riscv_feature(env, RISCV_FEATURE_PMP); +} + +static int pmp_post_load(void *opaque, int version_id) +{ + RISCVCPU *cpu = opaque; + CPURISCVState *env = &cpu->env; + int i; + + for (i = 0; i < MAX_RISCV_PMPS; i++) { + pmp_update_rule_addr(env, i); + } + pmp_update_rule_nums(env); + + return 0; +} + +static const VMStateDescription vmstate_pmp_entry = { + .name = "cpu/pmp/entry", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINTTL(addr_reg, pmp_entry_t), + VMSTATE_UINT8(cfg_reg, pmp_entry_t), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_pmp = { + .name = "cpu/pmp", + .version_id = 1, + .minimum_version_id = 1, + .needed = pmp_needed, + .post_load = pmp_post_load, + .fields = (VMStateField[]) { + VMSTATE_STRUCT_ARRAY(env.pmp_state.pmp, RISCVCPU, MAX_RISCV_PMPS, + 0, vmstate_pmp_entry, pmp_entry_t), + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_riscv_cpu = { .name = "cpu", .version_id = 1, @@ -73,5 +119,9 @@ const VMStateDescription vmstate_riscv_cpu = { VMSTATE_UINTTL(env.mstatush, RISCVCPU), #endif VMSTATE_END_OF_LIST() + }, + .subsections = (const VMStateDescription * []) { + &vmstate_pmp, + NULL } }; diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index c394e867f8..2eda8e1e2f 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -136,18 +136,8 @@ static void pmp_decode_napot(target_ulong a, target_ulong *sa, target_ulong *ea) } } - -/* Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea' - * end address values. - * This function is called relatively infrequently whereas the check that - * an address is within a pmp rule is called often, so optimise that one - */ -static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index) +void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index) { - int i; - - env->pmp_state.num_rules = 0; - uint8_t this_cfg = env->pmp_state.pmp[pmp_index].cfg_reg; target_ulong this_addr = env->pmp_state.pmp[pmp_index].addr_reg; target_ulong prev_addr = 0u; @@ -186,7 +176,13 @@ static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index) env->pmp_state.addr[pmp_index].sa = sa; env->pmp_state.addr[pmp_index].ea = ea; +} +void pmp_update_rule_nums(CPURISCVState *env) +{ + int i; + + env->pmp_state.num_rules = 0; for (i = 0; i < MAX_RISCV_PMPS; i++) { const uint8_t a_field = pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg); @@ -196,6 +192,17 @@ static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index) } } +/* Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea' + * end address values. + * This function is called relatively infrequently whereas the check that + * an address is within a pmp rule is called often, so optimise that one + */ +static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index) +{ + pmp_update_rule_addr(env, pmp_index); + pmp_update_rule_nums(env); +} + static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr) { int result = 0; diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h index 6a8f072871..6c6b4c9bef 100644 --- a/target/riscv/pmp.h +++ b/target/riscv/pmp.h @@ -62,5 +62,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, target_ulong size, pmp_priv_t priv, target_ulong mode); bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa, target_ulong *tlb_size); +void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index); +void pmp_update_rule_nums(CPURISCVState *env); #endif -- 2.19.1
next prev parent reply other threads:[~2020-10-10 8:26 UTC|newest] Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-10-10 8:06 [PATCH V2 0/5] Support RISC-V migration Yifei Jiang 2020-10-10 8:06 ` Yifei Jiang 2020-10-10 8:06 ` [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU Yifei Jiang 2020-10-10 8:06 ` Yifei Jiang 2020-10-10 13:23 ` Richard Henderson 2020-10-10 13:23 ` Richard Henderson 2020-10-14 10:21 ` Jiangyifei 2020-10-14 10:21 ` Jiangyifei 2020-10-14 15:45 ` Richard Henderson 2020-10-14 15:45 ` Richard Henderson 2020-10-14 19:12 ` Alistair Francis 2020-10-14 19:12 ` Alistair Francis 2020-10-15 2:03 ` Jiangyifei 2020-10-15 2:03 ` Jiangyifei 2020-10-10 8:06 ` Yifei Jiang [this message] 2020-10-10 8:06 ` [PATCH V2 2/5] target/riscv: Add PMP state description Yifei Jiang 2020-10-10 8:06 ` [PATCH V2 3/5] target/riscv: Add H extension " Yifei Jiang 2020-10-10 8:06 ` Yifei Jiang 2020-10-10 8:06 ` [PATCH V2 4/5] target/riscv: Add V " Yifei Jiang 2020-10-10 8:06 ` Yifei Jiang 2020-10-10 8:06 ` [PATCH V2 5/5] target/riscv: Add sifive_plic vmstate Yifei Jiang 2020-10-10 8:06 ` Yifei Jiang
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