From: Jiangyifei <jiangyifei@huawei.com>
To: Alistair Francis <alistair23@gmail.com>,
Richard Henderson <richard.henderson@linaro.org>
Cc: "qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>,
Zhanghailiang <zhang.zhanghailiang@huawei.com>,
"sagark@eecs.berkeley.edu" <sagark@eecs.berkeley.edu>,
"kbastian@mail.uni-paderborn.de" <kbastian@mail.uni-paderborn.de>,
"Zhangxiaofeng \(F\)" <victor.zhangxiaofeng@huawei.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"Alistair.Francis@wdc.com" <Alistair.Francis@wdc.com>,
yinyipeng <yinyipeng1@huawei.com>,
"palmer@dabbelt.com" <palmer@dabbelt.com>,
"Wubin \(H\)" <wu.wubin@huawei.com>,
"dengkai \(A\)" <dengkai1@huawei.com>
Subject: RE: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU
Date: Thu, 15 Oct 2020 02:03:39 +0000 [thread overview]
Message-ID: <476a5e7d98994bbca642ea8aa4cd141a@huawei.com> (raw)
In-Reply-To: <CAKmqyKPcK9jKCF4VrVsSuPMpTJXjkOdhmRc0jPqkFVyRLA1qUQ@mail.gmail.com>
> -----Original Message-----
> From: Alistair Francis [mailto:alistair23@gmail.com]
> Sent: Thursday, October 15, 2020 3:12 AM
> To: Richard Henderson <richard.henderson@linaro.org>
> Cc: Jiangyifei <jiangyifei@huawei.com>; qemu-devel@nongnu.org;
> qemu-riscv@nongnu.org; Zhanghailiang <zhang.zhanghailiang@huawei.com>;
> sagark@eecs.berkeley.edu; kbastian@mail.uni-paderborn.de; Zhangxiaofeng
> (F) <victor.zhangxiaofeng@huawei.com>; Alistair.Francis@wdc.com; yinyipeng
> <yinyipeng1@huawei.com>; palmer@dabbelt.com; Wubin (H)
> <wu.wubin@huawei.com>; dengkai (A) <dengkai1@huawei.com>
> Subject: Re: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU
>
> On Wed, Oct 14, 2020 at 8:45 AM Richard Henderson
> <richard.henderson@linaro.org> wrote:
> >
> > On 10/14/20 3:21 AM, Jiangyifei wrote:
> > >> Would this be a good time to expand mstatus to uint64_t instead of
> > >> target_ulong so that it can be saved as one unit and reduce some
> > >> ifdefs in the code base?
> > >>
> > >> Similarly with some of the other status registers that are two
> > >> halved for riscv32.
> > >
> > > I agree with you that it should be rearranged.
> > > But I hope this series will focus on achieving migration.
> > > Can I send another patch to rearrange it later?
> >
> > Well, that changes the bit layout for migration.
> > While we could bump the version number, it seemed easier to change the
> > representation first.
>
> +1 it would be great to consolidate these.
>
> Alistair
>
OK. I will change this in the next series.
Yifei
> >
> >
> > r~
> >
WARNING: multiple messages have this Message-ID (diff)
From: Jiangyifei <jiangyifei@huawei.com>
To: Alistair Francis <alistair23@gmail.com>,
Richard Henderson <richard.henderson@linaro.org>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>,
Zhanghailiang <zhang.zhanghailiang@huawei.com>,
"sagark@eecs.berkeley.edu" <sagark@eecs.berkeley.edu>,
"kbastian@mail.uni-paderborn.de" <kbastian@mail.uni-paderborn.de>,
"Zhangxiaofeng (F)" <victor.zhangxiaofeng@huawei.com>,
"Alistair.Francis@wdc.com" <Alistair.Francis@wdc.com>,
yinyipeng <yinyipeng1@huawei.com>,
"palmer@dabbelt.com" <palmer@dabbelt.com>,
"Wubin (H)" <wu.wubin@huawei.com>,
"dengkai (A)" <dengkai1@huawei.com>
Subject: RE: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU
Date: Thu, 15 Oct 2020 02:03:39 +0000 [thread overview]
Message-ID: <476a5e7d98994bbca642ea8aa4cd141a@huawei.com> (raw)
In-Reply-To: <CAKmqyKPcK9jKCF4VrVsSuPMpTJXjkOdhmRc0jPqkFVyRLA1qUQ@mail.gmail.com>
> -----Original Message-----
> From: Alistair Francis [mailto:alistair23@gmail.com]
> Sent: Thursday, October 15, 2020 3:12 AM
> To: Richard Henderson <richard.henderson@linaro.org>
> Cc: Jiangyifei <jiangyifei@huawei.com>; qemu-devel@nongnu.org;
> qemu-riscv@nongnu.org; Zhanghailiang <zhang.zhanghailiang@huawei.com>;
> sagark@eecs.berkeley.edu; kbastian@mail.uni-paderborn.de; Zhangxiaofeng
> (F) <victor.zhangxiaofeng@huawei.com>; Alistair.Francis@wdc.com; yinyipeng
> <yinyipeng1@huawei.com>; palmer@dabbelt.com; Wubin (H)
> <wu.wubin@huawei.com>; dengkai (A) <dengkai1@huawei.com>
> Subject: Re: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU
>
> On Wed, Oct 14, 2020 at 8:45 AM Richard Henderson
> <richard.henderson@linaro.org> wrote:
> >
> > On 10/14/20 3:21 AM, Jiangyifei wrote:
> > >> Would this be a good time to expand mstatus to uint64_t instead of
> > >> target_ulong so that it can be saved as one unit and reduce some
> > >> ifdefs in the code base?
> > >>
> > >> Similarly with some of the other status registers that are two
> > >> halved for riscv32.
> > >
> > > I agree with you that it should be rearranged.
> > > But I hope this series will focus on achieving migration.
> > > Can I send another patch to rearrange it later?
> >
> > Well, that changes the bit layout for migration.
> > While we could bump the version number, it seemed easier to change the
> > representation first.
>
> +1 it would be great to consolidate these.
>
> Alistair
>
OK. I will change this in the next series.
Yifei
> >
> >
> > r~
> >
next prev parent reply other threads:[~2020-10-15 2:05 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-10 8:06 [PATCH V2 0/5] Support RISC-V migration Yifei Jiang
2020-10-10 8:06 ` Yifei Jiang
2020-10-10 8:06 ` [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU Yifei Jiang
2020-10-10 8:06 ` Yifei Jiang
2020-10-10 13:23 ` Richard Henderson
2020-10-10 13:23 ` Richard Henderson
2020-10-14 10:21 ` Jiangyifei
2020-10-14 10:21 ` Jiangyifei
2020-10-14 15:45 ` Richard Henderson
2020-10-14 15:45 ` Richard Henderson
2020-10-14 19:12 ` Alistair Francis
2020-10-14 19:12 ` Alistair Francis
2020-10-15 2:03 ` Jiangyifei [this message]
2020-10-15 2:03 ` Jiangyifei
2020-10-10 8:06 ` [PATCH V2 2/5] target/riscv: Add PMP state description Yifei Jiang
2020-10-10 8:06 ` Yifei Jiang
2020-10-10 8:06 ` [PATCH V2 3/5] target/riscv: Add H extension " Yifei Jiang
2020-10-10 8:06 ` Yifei Jiang
2020-10-10 8:06 ` [PATCH V2 4/5] target/riscv: Add V " Yifei Jiang
2020-10-10 8:06 ` Yifei Jiang
2020-10-10 8:06 ` [PATCH V2 5/5] target/riscv: Add sifive_plic vmstate Yifei Jiang
2020-10-10 8:06 ` Yifei Jiang
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