* [PATCH 0/4] Renesas RZ/G2x enable RPC clocks
@ 2020-10-16 12:17 Lad Prabhakar
2020-10-16 12:17 ` [PATCH 1/4] clk: renesas: rcar-gen3: Add support to pass custom RPCSRC div table Lad Prabhakar
` (3 more replies)
0 siblings, 4 replies; 10+ messages in thread
From: Lad Prabhakar @ 2020-10-16 12:17 UTC (permalink / raw)
To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd,
linux-renesas-soc, linux-clk
Cc: linux-kernel, Biju Das, Prabhakar, Lad Prabhakar
Hi All,
This patch series enables RPC clocks on RZ/G2x SoC's.
This series applies on top of [1].
[1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/
renesas-drivers.git/log/?h=renesas-clk-for-v5.11
Cheers,
Prabhakar
Biju Das (2):
clk: renesas: r8a774a1: Add RPC clocks
clk: renesas: r8a774b1: Add RPC clocks
Lad Prabhakar (2):
clk: renesas: rcar-gen3: Add support to pass custom RPCSRC div table
clk: renesas: r8a774c0: Add RPC clocks
drivers/clk/renesas/r8a774a1-cpg-mssr.c | 8 ++++++++
drivers/clk/renesas/r8a774b1-cpg-mssr.c | 8 ++++++++
drivers/clk/renesas/r8a774c0-cpg-mssr.c | 14 ++++++++++++++
drivers/clk/renesas/rcar-gen3-cpg.c | 2 ++
drivers/clk/renesas/renesas-cpg-mssr.h | 6 ++++++
5 files changed, 38 insertions(+)
--
2.17.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 1/4] clk: renesas: rcar-gen3: Add support to pass custom RPCSRC div table
2020-10-16 12:17 [PATCH 0/4] Renesas RZ/G2x enable RPC clocks Lad Prabhakar
@ 2020-10-16 12:17 ` Lad Prabhakar
2020-10-16 12:17 ` [PATCH 2/4] clk: renesas: r8a774a1: Add RPC clocks Lad Prabhakar
` (2 subsequent siblings)
3 siblings, 0 replies; 10+ messages in thread
From: Lad Prabhakar @ 2020-10-16 12:17 UTC (permalink / raw)
To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd,
linux-renesas-soc, linux-clk
Cc: linux-kernel, Biju Das, Prabhakar, Lad Prabhakar
RPCSRC div table is SoC specific and is not common for all R-Car Gen3
devices, with the current implementation in rcar-gen3-cpg not all the
SoC's are covered.
To handle such case introduce a new member cpg_rpcsrc_div_table in
priv structure so that we pass SoC specific div table for RPCSRC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/renesas/rcar-gen3-cpg.c | 2 ++
drivers/clk/renesas/renesas-cpg-mssr.h | 6 ++++++
2 files changed, 8 insertions(+)
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index 488f8b3980c5..cdfcd108d1a3 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -693,6 +693,8 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
return clk_register_divider_table(NULL, core->name,
__clk_get_name(parent), 0,
base + CPG_RPCCKCR, 3, 2, 0,
+ info->cpg_rpcsrc_div_table ?
+ info->cpg_rpcsrc_div_table :
cpg_rpcsrc_div_table,
&cpg_lock);
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index f369b06c903b..3b0a70c59e04 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -8,6 +8,8 @@
#ifndef __CLK_RENESAS_CPG_MSSR_H__
#define __CLK_RENESAS_CPG_MSSR_H__
+#include <linux/clk-provider.h>
+
/*
* Definitions of CPG Core Clocks
*
@@ -116,6 +118,8 @@ enum clk_reg_layout {
* Management, in addition to Module Clocks
* @num_core_pm_clks: Number of entries in core_pm_clks[]
*
+ * @cpg_rpcsrc_div_table: DIV table for RPCSRC
+ *
* @init: Optional callback to perform SoC-specific initialization
* @cpg_clk_register: Optional callback to handle special Core Clock types
*/
@@ -147,6 +151,8 @@ struct cpg_mssr_info {
const unsigned int *core_pm_clks;
unsigned int num_core_pm_clks;
+ const struct clk_div_table *cpg_rpcsrc_div_table;
+
/* Callbacks */
int (*init)(struct device *dev);
struct clk *(*cpg_clk_register)(struct device *dev,
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/4] clk: renesas: r8a774a1: Add RPC clocks
2020-10-16 12:17 [PATCH 0/4] Renesas RZ/G2x enable RPC clocks Lad Prabhakar
2020-10-16 12:17 ` [PATCH 1/4] clk: renesas: rcar-gen3: Add support to pass custom RPCSRC div table Lad Prabhakar
@ 2020-10-16 12:17 ` Lad Prabhakar
2020-10-22 13:29 ` Geert Uytterhoeven
2020-10-16 12:17 ` [PATCH 3/4] clk: renesas: r8a774b1: " Lad Prabhakar
2020-10-16 12:17 ` [PATCH 4/4] clk: renesas: r8a774c0: " Lad Prabhakar
3 siblings, 1 reply; 10+ messages in thread
From: Lad Prabhakar @ 2020-10-16 12:17 UTC (permalink / raw)
To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd,
linux-renesas-soc, linux-clk
Cc: linux-kernel, Biju Das, Prabhakar, Lad Prabhakar
From: Biju Das <biju.das.jz@bp.renesas.com>
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
as well as the RPC-IF module clock, in the RZ/G2M (R8A774A1) CPG/MSSR
driver.
Inspired by commit 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks").
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/clk/renesas/r8a774a1-cpg-mssr.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
index fd54b9f625da..4a43ebec7d5e 100644
--- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -41,6 +41,7 @@ enum clk_ids {
CLK_S2,
CLK_S3,
CLK_SDSRC,
+ CLK_RPCSRC,
CLK_RINT,
/* Module Clocks */
@@ -67,6 +68,12 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
+ DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
+
+ DEF_BASE("rpc", R8A774A1_CLK_RPC, CLK_TYPE_GEN3_RPC,
+ CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A774A1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
+ R8A774A1_CLK_RPC),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
@@ -200,6 +207,7 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
DEF_MOD("can-fd", 914, R8A774A1_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A774A1_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A774A1_CLK_S3D4),
+ DEF_MOD("rpc-if", 917, R8A774A1_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A774A1_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A774A1_CLK_S0D6),
DEF_MOD("i2c-dvfs", 926, R8A774A1_CLK_CP),
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 3/4] clk: renesas: r8a774b1: Add RPC clocks
2020-10-16 12:17 [PATCH 0/4] Renesas RZ/G2x enable RPC clocks Lad Prabhakar
2020-10-16 12:17 ` [PATCH 1/4] clk: renesas: rcar-gen3: Add support to pass custom RPCSRC div table Lad Prabhakar
2020-10-16 12:17 ` [PATCH 2/4] clk: renesas: r8a774a1: Add RPC clocks Lad Prabhakar
@ 2020-10-16 12:17 ` Lad Prabhakar
2020-10-22 13:31 ` Geert Uytterhoeven
2020-10-16 12:17 ` [PATCH 4/4] clk: renesas: r8a774c0: " Lad Prabhakar
3 siblings, 1 reply; 10+ messages in thread
From: Lad Prabhakar @ 2020-10-16 12:17 UTC (permalink / raw)
To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd,
linux-renesas-soc, linux-clk
Cc: linux-kernel, Biju Das, Prabhakar, Lad Prabhakar
From: Biju Das <biju.das.jz@bp.renesas.com>
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
as well as the RPC-IF module clock, in the RZ/G2N (R8A774B1) CPG/MSSR
driver.
Inspired by commit 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks").
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/clk/renesas/r8a774b1-cpg-mssr.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
index f436691271ec..6f04c40fe237 100644
--- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
@@ -40,6 +40,7 @@ enum clk_ids {
CLK_S2,
CLK_S3,
CLK_SDSRC,
+ CLK_RPCSRC,
CLK_RINT,
/* Module Clocks */
@@ -65,6 +66,12 @@ static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = {
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
+ DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
+
+ DEF_BASE("rpc", R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC,
+ CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
+ R8A774B1_CLK_RPC),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
@@ -196,6 +203,7 @@ static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = {
DEF_MOD("can-fd", 914, R8A774B1_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A774B1_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A774B1_CLK_S3D4),
+ DEF_MOD("rpc-if", 917, R8A774B1_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A774B1_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A774B1_CLK_S0D6),
DEF_MOD("i2c-dvfs", 926, R8A774B1_CLK_CP),
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 4/4] clk: renesas: r8a774c0: Add RPC clocks
2020-10-16 12:17 [PATCH 0/4] Renesas RZ/G2x enable RPC clocks Lad Prabhakar
` (2 preceding siblings ...)
2020-10-16 12:17 ` [PATCH 3/4] clk: renesas: r8a774b1: " Lad Prabhakar
@ 2020-10-16 12:17 ` Lad Prabhakar
2020-10-22 14:09 ` Geert Uytterhoeven
3 siblings, 1 reply; 10+ messages in thread
From: Lad Prabhakar @ 2020-10-16 12:17 UTC (permalink / raw)
To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd,
linux-renesas-soc, linux-clk
Cc: linux-kernel, Biju Das, Prabhakar, Lad Prabhakar
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
as well as the RPC-IF module clock, in the RZ/G2E (R8A774C0) CPG/MSSR
driver.
Inspired by commit 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks").
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/renesas/r8a774c0-cpg-mssr.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
index 9fc9fa9e531a..1615b31c32ee 100644
--- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
@@ -44,6 +44,7 @@ enum clk_ids {
CLK_S2,
CLK_S3,
CLK_SDSRC,
+ CLK_RPCSRC,
CLK_RINT,
CLK_OCO,
@@ -73,6 +74,12 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = {
DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
+ DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
+
+ DEF_BASE("rpc", R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC,
+ CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
+ R8A774C0_CLK_RPC),
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
@@ -199,6 +206,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
DEF_MOD("can-fd", 914, R8A774C0_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A774C0_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A774C0_CLK_S3D4),
+ DEF_MOD("rpc-if", 917, R8A774C0_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A774C0_CLK_S3D2),
DEF_MOD("i2c5", 919, R8A774C0_CLK_S3D2),
DEF_MOD("i2c-dvfs", 926, R8A774C0_CLK_CP),
@@ -275,6 +283,10 @@ static int __init r8a774c0_cpg_mssr_init(struct device *dev)
return rcar_gen3_cpg_init(cpg_pll_config, 0, cpg_mode);
}
+static const struct clk_div_table cpg_rpcsrc_div_table[] = {
+ { 0, 5 }, { 1, 3 }, { 2, 8 }, {3, 2}, {0, 0},
+};
+
const struct cpg_mssr_info r8a774c0_cpg_mssr_info __initconst = {
/* Core Clocks */
.core_clks = r8a774c0_core_clks,
@@ -287,6 +299,8 @@ const struct cpg_mssr_info r8a774c0_cpg_mssr_info __initconst = {
.num_mod_clks = ARRAY_SIZE(r8a774c0_mod_clks),
.num_hw_mod_clks = 12 * 32,
+ .cpg_rpcsrc_div_table = cpg_rpcsrc_div_table,
+
/* Critical Module Clocks */
.crit_mod_clks = r8a774c0_crit_mod_clks,
.num_crit_mod_clks = ARRAY_SIZE(r8a774c0_crit_mod_clks),
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 2/4] clk: renesas: r8a774a1: Add RPC clocks
2020-10-16 12:17 ` [PATCH 2/4] clk: renesas: r8a774a1: Add RPC clocks Lad Prabhakar
@ 2020-10-22 13:29 ` Geert Uytterhoeven
0 siblings, 0 replies; 10+ messages in thread
From: Geert Uytterhoeven @ 2020-10-22 13:29 UTC (permalink / raw)
To: Lad Prabhakar
Cc: Michael Turquette, Stephen Boyd, Linux-Renesas, linux-clk,
Linux Kernel Mailing List, Biju Das, Prabhakar
On Fri, Oct 16, 2020 at 2:17 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
> as well as the RPC-IF module clock, in the RZ/G2M (R8A774A1) CPG/MSSR
> driver.
>
> Inspired by commit 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks").
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v5.11.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 3/4] clk: renesas: r8a774b1: Add RPC clocks
2020-10-16 12:17 ` [PATCH 3/4] clk: renesas: r8a774b1: " Lad Prabhakar
@ 2020-10-22 13:31 ` Geert Uytterhoeven
0 siblings, 0 replies; 10+ messages in thread
From: Geert Uytterhoeven @ 2020-10-22 13:31 UTC (permalink / raw)
To: Lad Prabhakar
Cc: Michael Turquette, Stephen Boyd, Linux-Renesas, linux-clk,
Linux Kernel Mailing List, Biju Das, Prabhakar
On Fri, Oct 16, 2020 at 2:17 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
> as well as the RPC-IF module clock, in the RZ/G2N (R8A774B1) CPG/MSSR
> driver.
>
> Inspired by commit 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks").
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v5.11.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 4/4] clk: renesas: r8a774c0: Add RPC clocks
2020-10-16 12:17 ` [PATCH 4/4] clk: renesas: r8a774c0: " Lad Prabhakar
@ 2020-10-22 14:09 ` Geert Uytterhoeven
2020-10-23 11:05 ` Lad, Prabhakar
0 siblings, 1 reply; 10+ messages in thread
From: Geert Uytterhoeven @ 2020-10-22 14:09 UTC (permalink / raw)
To: Lad Prabhakar
Cc: Michael Turquette, Stephen Boyd, Linux-Renesas, linux-clk,
Linux Kernel Mailing List, Biju Das, Prabhakar
Hi Prabhakar,
On Fri, Oct 16, 2020 at 2:17 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
> as well as the RPC-IF module clock, in the RZ/G2E (R8A774C0) CPG/MSSR
> driver.
>
> Inspired by commit 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks").
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Thanks for your patch!
> --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> @@ -73,6 +74,12 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = {
> DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
> DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
> DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
> + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
> +
> + DEF_BASE("rpc", R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC,
> + CLK_RPCSRC),
> + DEF_BASE("rpcd2", R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
> + R8A774C0_CLK_RPC),
>
> DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
>
> @@ -275,6 +283,10 @@ static int __init r8a774c0_cpg_mssr_init(struct device *dev)
> return rcar_gen3_cpg_init(cpg_pll_config, 0, cpg_mode);
> }
>
> +static const struct clk_div_table cpg_rpcsrc_div_table[] = {
> + { 0, 5 }, { 1, 3 }, { 2, 8 }, {3, 2}, {0, 0},
> +};
The above models RPCSRC as a clock generated by dividing PLL1 by either
5, 3, 8, or 2. This does not match the hardware user's manual, which
states that RPCSRC is either PLL1 divided by 5 or 3, or PLL0 divided by
8 or 2.
I think you need a new clock type (CLK_TYPE_GEN3E_RPCSRC, as it applies
to RZ/G2E, and R-Car E3?), which registers a composite clock consisting
of a mux and divider. This is a bit similar to the RPC/RPCD2 clocks,
which are composite clocks consisting of a divider and a gate.
Note that R-Car D3 is similar, except that PLL0 is divided by 5 or 2, which
means yet another clock type (and div_table).
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 4/4] clk: renesas: r8a774c0: Add RPC clocks
2020-10-22 14:09 ` Geert Uytterhoeven
@ 2020-10-23 11:05 ` Lad, Prabhakar
2020-10-23 12:42 ` Geert Uytterhoeven
0 siblings, 1 reply; 10+ messages in thread
From: Lad, Prabhakar @ 2020-10-23 11:05 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Lad Prabhakar, Michael Turquette, Stephen Boyd, Linux-Renesas,
linux-clk, Linux Kernel Mailing List, Biju Das
Hi Geert,
Thank you for the review.
On Thu, Oct 22, 2020 at 3:09 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Fri, Oct 16, 2020 at 2:17 PM Lad Prabhakar
> <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
> > as well as the RPC-IF module clock, in the RZ/G2E (R8A774C0) CPG/MSSR
> > driver.
> >
> > Inspired by commit 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks").
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> > +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> > @@ -73,6 +74,12 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = {
> > DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
> > DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
> > DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
> > + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
> > +
> > + DEF_BASE("rpc", R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC,
> > + CLK_RPCSRC),
> > + DEF_BASE("rpcd2", R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
> > + R8A774C0_CLK_RPC),
> >
> > DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
> >
>
> > @@ -275,6 +283,10 @@ static int __init r8a774c0_cpg_mssr_init(struct device *dev)
> > return rcar_gen3_cpg_init(cpg_pll_config, 0, cpg_mode);
> > }
> >
> > +static const struct clk_div_table cpg_rpcsrc_div_table[] = {
> > + { 0, 5 }, { 1, 3 }, { 2, 8 }, {3, 2}, {0, 0},
> > +};
>
> The above models RPCSRC as a clock generated by dividing PLL1 by either
> 5, 3, 8, or 2. This does not match the hardware user's manual, which
> states that RPCSRC is either PLL1 divided by 5 or 3, or PLL0 divided by
> 8 or 2.
>
Oops I completely missed that.
But as per the manual (R-Car manual Rev.2.20) which I am referring to
5, 3 and 2 are sourced from PLL1 and 5/8 (ie D3/E3) are sourced from
PLL0.
> I think you need a new clock type (CLK_TYPE_GEN3E_RPCSRC, as it applies
> to RZ/G2E, and R-Car E3?), which registers a composite clock consisting
> of a mux and divider. This is a bit similar to the RPC/RPCD2 clocks,
> which are composite clocks consisting of a divider and a gate.
>
atm rcar_gen3_cpg_clk_register() only supports single parent, so if I
am getting it right you mean I need to add two separate entries for
RPSRC one with PLL0 and one with PLL1 ?
> Note that R-Car D3 is similar, except that PLL0 is divided by 5 or 2, which
> means yet another clock type (and div_table).
>
I'm a bit confused here for D3 PLL0 is divided by 5 (n=5) ?
Cheers,
Prabhakar
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 4/4] clk: renesas: r8a774c0: Add RPC clocks
2020-10-23 11:05 ` Lad, Prabhakar
@ 2020-10-23 12:42 ` Geert Uytterhoeven
0 siblings, 0 replies; 10+ messages in thread
From: Geert Uytterhoeven @ 2020-10-23 12:42 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Lad Prabhakar, Michael Turquette, Stephen Boyd, Linux-Renesas,
linux-clk, Linux Kernel Mailing List, Biju Das
Hi Prabhakar,
On Fri, Oct 23, 2020 at 1:06 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Thu, Oct 22, 2020 at 3:09 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Fri, Oct 16, 2020 at 2:17 PM Lad Prabhakar
> > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > > Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
> > > as well as the RPC-IF module clock, in the RZ/G2E (R8A774C0) CPG/MSSR
> > > driver.
> > >
> > > Inspired by commit 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks").
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Thanks for your patch!
> >
> > > --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> > > +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> > > @@ -73,6 +74,12 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = {
> > > DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
> > > DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
> > > DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
> > > + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
> > > +
> > > + DEF_BASE("rpc", R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC,
> > > + CLK_RPCSRC),
> > > + DEF_BASE("rpcd2", R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
> > > + R8A774C0_CLK_RPC),
> > >
> > > DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
> > >
> >
> > > @@ -275,6 +283,10 @@ static int __init r8a774c0_cpg_mssr_init(struct device *dev)
> > > return rcar_gen3_cpg_init(cpg_pll_config, 0, cpg_mode);
> > > }
> > >
> > > +static const struct clk_div_table cpg_rpcsrc_div_table[] = {
> > > + { 0, 5 }, { 1, 3 }, { 2, 8 }, {3, 2}, {0, 0},
> > > +};
> >
> > The above models RPCSRC as a clock generated by dividing PLL1 by either
> > 5, 3, 8, or 2. This does not match the hardware user's manual, which
> > states that RPCSRC is either PLL1 divided by 5 or 3, or PLL0 divided by
> > 8 or 2.
> >
> Oops I completely missed that.
>
> But as per the manual (R-Car manual Rev.2.20) which I am referring to
> 5, 3 and 2 are sourced from PLL1 and 5/8 (ie D3/E3) are sourced from
> PLL0.
True, I misread the clocksource of the last entry.
> > I think you need a new clock type (CLK_TYPE_GEN3E_RPCSRC, as it applies
> > to RZ/G2E, and R-Car E3?), which registers a composite clock consisting
> > of a mux and divider. This is a bit similar to the RPC/RPCD2 clocks,
> > which are composite clocks consisting of a divider and a gate.
> >
> atm rcar_gen3_cpg_clk_register() only supports single parent, so if I
> am getting it right you mean I need to add two separate entries for
> RPSRC one with PLL0 and one with PLL1 ?
You can encode a second parent in the high halfword, cfr. what
CLK_TYPE_GEN3_MDSEL and CLK_TYPE_GEN3_RCKSEL.
Note to myself: convert cpg_core_clk to a union, to make encoding
and decoding easier.
> > Note that R-Car D3 is similar, except that PLL0 is divided by 5 or 2, which
> > means yet another clock type (and div_table).
> >
> I'm a bit confused here for D3 PLL0 is divided by 5 (n=5) ?
Sorry, same misreading as above.
Have a nice weekend!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2020-10-23 12:42 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-10-16 12:17 [PATCH 0/4] Renesas RZ/G2x enable RPC clocks Lad Prabhakar
2020-10-16 12:17 ` [PATCH 1/4] clk: renesas: rcar-gen3: Add support to pass custom RPCSRC div table Lad Prabhakar
2020-10-16 12:17 ` [PATCH 2/4] clk: renesas: r8a774a1: Add RPC clocks Lad Prabhakar
2020-10-22 13:29 ` Geert Uytterhoeven
2020-10-16 12:17 ` [PATCH 3/4] clk: renesas: r8a774b1: " Lad Prabhakar
2020-10-22 13:31 ` Geert Uytterhoeven
2020-10-16 12:17 ` [PATCH 4/4] clk: renesas: r8a774c0: " Lad Prabhakar
2020-10-22 14:09 ` Geert Uytterhoeven
2020-10-23 11:05 ` Lad, Prabhakar
2020-10-23 12:42 ` Geert Uytterhoeven
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