* [PATCH v8 0/2] Add file-backed and write-once features to OTP
@ 2020-10-20 3:37 ` Green Wan
0 siblings, 0 replies; 8+ messages in thread
From: Green Wan @ 2020-10-20 3:37 UTC (permalink / raw)
Cc: alistair23, bmeng.cn, qemu-riscv, qemu-devel, green.wan
patch [1/2] - add write function and wrire-once feature
patch [2/2] - add file backend support
Test Steps: (should work even only 1/2 is applied)
1) Follow instructions to prepare fw_payload - https://github.com/riscv/opensbi/blob/master/docs/platform/sifive_fu540.md
a) build 1-round opensbi
$ cd opensbi
$ OBJCOPY=riscv64-buildroot-linux-gnu-objcopy \
LD=riscv64-buildroot-linux-gnu-ld \
CC=riscv64-buildroot-linux-gnu-gcc \
make PLATFORM=sifive/fu540
b) build u-boot
# Make sure the 'CONFIG_SIFIVE_OTP=y' is set
$ cd u-boot
$ OPENSBI=/xxx/opensbi/build/platform/sifive/fu540/firmware/fw_dynamic.bin \
ARCH=riscv \
CROSS_COMPILE=riscv64-buildroot-linux-gnu- \
make
c) generate fw_payload.elf
$ cd opensbi
$ OBJCOPY=riscv64-buildroot-linux-gnu-objcopy \
LD=riscv64-buildroot-linux-gnu-ld \
CC=riscv64-buildroot-linux-gnu-gcc \
make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=/xxx/u-boot/u-boot.bin
2) Apply uboot test patch - http://patchwork.ozlabs.org/project/uboot/patch/1602657292-82815-1-git-send-email-bmeng.cn@gmail.com/
Rebuild u-boot and fw_payload.elf
3) Generate empty otp image. (skip this if only 1/2 is applied.)
$ dd if=/dev/zero of=./otp.img bs=1k count=16
4) run qemu with fw_payload.elf
$ qemu-system-riscv64 -M sifive_u -m 256M -nographic -bios none \
-kernel ../opensbi/build/platform/sifive/fu540/firmware/fw_payload.elf \
-d guest_errors -drive if=none,format=raw,file=otp.img
5) (uboot otp driver should do some read/write already) Run read/write in u-boot
# dump mem before test
=> md 80200000 10
80200000: 84ae822a 00061297 7642b283 10529073 *.........Bvs.R.
80200010: 10401073 031b52c1 13134010 71330153 s.@..R...@..S.3q
80200020: 850a0053 28c0b0ef 812a81aa 00062297 S......(..*.."..
80200030: 94c2b283 a92f4905 16630862 22970209 .....I/.b.c...."
=> md 80400000 10
80400000: 00000000 00000000 00000000 00000000 ................
80400010: 00000000 00000000 00000000 00000000 ................
80400020: 00000000 00000000 00000000 00000000 ................
80400030: 00000000 00000000 00000000 00000000 ................
# check read function and see if serial is set
=> misc read otp@10070000 3f0 80400000 10
=> md 80400000 10
80400000: 00000001 fffffffe 00000000 00000000 ................
80400010: 00000000 00000000 00000000 00000000 ................
80400020: 00000000 00000000 00000000 00000000 ................
80400030: 00000000 00000000 00000000 00000000 ................
# check write function
=> misc write otp@10070000 0 80200000 10
=> misc read otp@10070000 0 80400000 10
=> md 80400000 10
80400000: 84ae822a 00061297 7642b283 10529073 *.........Bvs.R.
80400010: 00000000 00000000 00000000 00000000 ................
80400020: 00000000 00000000 00000000 00000000 ................
80400030: 00000000 00000000 00000000 00000000 ................
=>
Changelogs:
v6 to v7:
- Rebase to the latest and move debug message patch
from patch [2/2] to [1/2]
- Remove RFC tag and add credit
v6 to v7:
- Fix bug in MACRO, SET_FUSEARRAY_BIT.
- Add serial initialization in sifive_u_otp_reset().
- revise write-once error message.
v5 to v6:
- Rebase to latest. (sifive_u_otp.* are moved to hw/misc)
- Put the example command to commit message.
- Refine errp handle when check backend drive.
- Remove unnecessary debug message.
v4 to v5:
- Change the patch order
- Add write operation to update pdin to fuse[] bit by bit
- Fix wrong protection for offset 0x0~0x38
- Add SIFIVE_U_OTP_PWE_EN definition
- Refine access macro for fuse[] and fuse_wo[]
Summary of Patches
- First patch is to add write opertion to update pdin data to fuse[] bit
by bit. Add 'write-once' feature to block second write to same bit of
the OTP memory.
- Second patch is to add file-backed implementation to allow users to use
'-drive' to assign an OTP raw image file. OTP image file must be bigger
than 16K.
For example, '-drive if=none,format=raw,file=otp.img'
Testing
- Tested on sifive_u for both qemu and u-boot.
Green Wan (2):
hw/misc/sifive_u_otp: Add write function and write-once protection
hw/misc/sifive_u_otp: Add backend drive support
hw/misc/sifive_u_otp.c | 95 +++++++++++++++++++++++++++++++++-
include/hw/misc/sifive_u_otp.h | 5 ++
2 files changed, 99 insertions(+), 1 deletion(-)
--
2.17.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v8 0/2] Add file-backed and write-once features to OTP
@ 2020-10-20 3:37 ` Green Wan
0 siblings, 0 replies; 8+ messages in thread
From: Green Wan @ 2020-10-20 3:37 UTC (permalink / raw)
Cc: qemu-devel, qemu-riscv, bmeng.cn, alistair23, green.wan
patch [1/2] - add write function and wrire-once feature
patch [2/2] - add file backend support
Test Steps: (should work even only 1/2 is applied)
1) Follow instructions to prepare fw_payload - https://github.com/riscv/opensbi/blob/master/docs/platform/sifive_fu540.md
a) build 1-round opensbi
$ cd opensbi
$ OBJCOPY=riscv64-buildroot-linux-gnu-objcopy \
LD=riscv64-buildroot-linux-gnu-ld \
CC=riscv64-buildroot-linux-gnu-gcc \
make PLATFORM=sifive/fu540
b) build u-boot
# Make sure the 'CONFIG_SIFIVE_OTP=y' is set
$ cd u-boot
$ OPENSBI=/xxx/opensbi/build/platform/sifive/fu540/firmware/fw_dynamic.bin \
ARCH=riscv \
CROSS_COMPILE=riscv64-buildroot-linux-gnu- \
make
c) generate fw_payload.elf
$ cd opensbi
$ OBJCOPY=riscv64-buildroot-linux-gnu-objcopy \
LD=riscv64-buildroot-linux-gnu-ld \
CC=riscv64-buildroot-linux-gnu-gcc \
make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=/xxx/u-boot/u-boot.bin
2) Apply uboot test patch - http://patchwork.ozlabs.org/project/uboot/patch/1602657292-82815-1-git-send-email-bmeng.cn@gmail.com/
Rebuild u-boot and fw_payload.elf
3) Generate empty otp image. (skip this if only 1/2 is applied.)
$ dd if=/dev/zero of=./otp.img bs=1k count=16
4) run qemu with fw_payload.elf
$ qemu-system-riscv64 -M sifive_u -m 256M -nographic -bios none \
-kernel ../opensbi/build/platform/sifive/fu540/firmware/fw_payload.elf \
-d guest_errors -drive if=none,format=raw,file=otp.img
5) (uboot otp driver should do some read/write already) Run read/write in u-boot
# dump mem before test
=> md 80200000 10
80200000: 84ae822a 00061297 7642b283 10529073 *.........Bvs.R.
80200010: 10401073 031b52c1 13134010 71330153 s.@..R...@..S.3q
80200020: 850a0053 28c0b0ef 812a81aa 00062297 S......(..*.."..
80200030: 94c2b283 a92f4905 16630862 22970209 .....I/.b.c...."
=> md 80400000 10
80400000: 00000000 00000000 00000000 00000000 ................
80400010: 00000000 00000000 00000000 00000000 ................
80400020: 00000000 00000000 00000000 00000000 ................
80400030: 00000000 00000000 00000000 00000000 ................
# check read function and see if serial is set
=> misc read otp@10070000 3f0 80400000 10
=> md 80400000 10
80400000: 00000001 fffffffe 00000000 00000000 ................
80400010: 00000000 00000000 00000000 00000000 ................
80400020: 00000000 00000000 00000000 00000000 ................
80400030: 00000000 00000000 00000000 00000000 ................
# check write function
=> misc write otp@10070000 0 80200000 10
=> misc read otp@10070000 0 80400000 10
=> md 80400000 10
80400000: 84ae822a 00061297 7642b283 10529073 *.........Bvs.R.
80400010: 00000000 00000000 00000000 00000000 ................
80400020: 00000000 00000000 00000000 00000000 ................
80400030: 00000000 00000000 00000000 00000000 ................
=>
Changelogs:
v6 to v7:
- Rebase to the latest and move debug message patch
from patch [2/2] to [1/2]
- Remove RFC tag and add credit
v6 to v7:
- Fix bug in MACRO, SET_FUSEARRAY_BIT.
- Add serial initialization in sifive_u_otp_reset().
- revise write-once error message.
v5 to v6:
- Rebase to latest. (sifive_u_otp.* are moved to hw/misc)
- Put the example command to commit message.
- Refine errp handle when check backend drive.
- Remove unnecessary debug message.
v4 to v5:
- Change the patch order
- Add write operation to update pdin to fuse[] bit by bit
- Fix wrong protection for offset 0x0~0x38
- Add SIFIVE_U_OTP_PWE_EN definition
- Refine access macro for fuse[] and fuse_wo[]
Summary of Patches
- First patch is to add write opertion to update pdin data to fuse[] bit
by bit. Add 'write-once' feature to block second write to same bit of
the OTP memory.
- Second patch is to add file-backed implementation to allow users to use
'-drive' to assign an OTP raw image file. OTP image file must be bigger
than 16K.
For example, '-drive if=none,format=raw,file=otp.img'
Testing
- Tested on sifive_u for both qemu and u-boot.
Green Wan (2):
hw/misc/sifive_u_otp: Add write function and write-once protection
hw/misc/sifive_u_otp: Add backend drive support
hw/misc/sifive_u_otp.c | 95 +++++++++++++++++++++++++++++++++-
include/hw/misc/sifive_u_otp.h | 5 ++
2 files changed, 99 insertions(+), 1 deletion(-)
--
2.17.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v8 1/2] hw/misc/sifive_u_otp: Add write function and write-once protection
2020-10-20 3:37 ` Green Wan
@ 2020-10-20 3:37 ` Green Wan
-1 siblings, 0 replies; 8+ messages in thread
From: Green Wan @ 2020-10-20 3:37 UTC (permalink / raw)
Cc: alistair23, bmeng.cn, qemu-riscv, qemu-devel, green.wan
- Add write operation to update fuse data bit when PWE bit is on.
- Add array, fuse_wo, to store the 'written' status for all bits
of OTP to block the write operation.
Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
---
hw/misc/sifive_u_otp.c | 30 +++++++++++++++++++++++++++++-
include/hw/misc/sifive_u_otp.h | 3 +++
2 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
index c2f3c8e129..b9238d64cb 100644
--- a/hw/misc/sifive_u_otp.c
+++ b/hw/misc/sifive_u_otp.c
@@ -25,6 +25,14 @@
#include "qemu/module.h"
#include "hw/misc/sifive_u_otp.h"
+#define WRITTEN_BIT_ON 0x1
+
+#define SET_FUSEARRAY_BIT(map, i, off, bit) \
+ map[i] = bit ? (map[i] | bit << off) : (map[i] & ~(0x1 << off))
+
+#define GET_FUSEARRAY_BIT(map, i, off) \
+ ((map[i] >> off) & 0x1)
+
static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size)
{
SiFiveUOTPState *s = opaque;
@@ -123,7 +131,24 @@ static void sifive_u_otp_write(void *opaque, hwaddr addr,
s->ptrim = val32;
break;
case SIFIVE_U_OTP_PWE:
- s->pwe = val32;
+ s->pwe = val32 & SIFIVE_U_OTP_PWE_EN;
+
+ /* PWE is enabled. Ignore PAS=1 (no redundancy cell) */
+ if (s->pwe && !s->pas) {
+ if (GET_FUSEARRAY_BIT(s->fuse_wo, s->pa, s->paio)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "write once error: idx<%u>, bit<%u>\n",
+ s->pa, s->paio);
+ break;
+ }
+
+ /* write bit data */
+ SET_FUSEARRAY_BIT(s->fuse, s->pa, s->paio, s->pdin);
+
+ /* update written bit */
+ SET_FUSEARRAY_BIT(s->fuse_wo, s->pa, s->paio, WRITTEN_BIT_ON);
+ }
+
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx
@@ -165,6 +190,9 @@ static void sifive_u_otp_reset(DeviceState *dev)
/* Make a valid content of serial number */
s->fuse[SIFIVE_U_OTP_SERIAL_ADDR] = s->serial;
s->fuse[SIFIVE_U_OTP_SERIAL_ADDR + 1] = ~(s->serial);
+
+ /* Initialize write-once map */
+ memset(s->fuse_wo, 0x00, sizeof(s->fuse_wo));
}
static void sifive_u_otp_class_init(ObjectClass *klass, void *data)
diff --git a/include/hw/misc/sifive_u_otp.h b/include/hw/misc/sifive_u_otp.h
index 82c9176c8f..ebffbc1fa5 100644
--- a/include/hw/misc/sifive_u_otp.h
+++ b/include/hw/misc/sifive_u_otp.h
@@ -36,6 +36,8 @@
#define SIFIVE_U_OTP_PTRIM 0x34
#define SIFIVE_U_OTP_PWE 0x38
+#define SIFIVE_U_OTP_PWE_EN (1 << 0)
+
#define SIFIVE_U_OTP_PCE_EN (1 << 0)
#define SIFIVE_U_OTP_PDSTB_EN (1 << 0)
@@ -75,6 +77,7 @@ struct SiFiveUOTPState {
uint32_t ptrim;
uint32_t pwe;
uint32_t fuse[SIFIVE_U_OTP_NUM_FUSES];
+ uint32_t fuse_wo[SIFIVE_U_OTP_NUM_FUSES];
/* config */
uint32_t serial;
};
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v8 1/2] hw/misc/sifive_u_otp: Add write function and write-once protection
@ 2020-10-20 3:37 ` Green Wan
0 siblings, 0 replies; 8+ messages in thread
From: Green Wan @ 2020-10-20 3:37 UTC (permalink / raw)
Cc: qemu-devel, qemu-riscv, bmeng.cn, alistair23, green.wan
- Add write operation to update fuse data bit when PWE bit is on.
- Add array, fuse_wo, to store the 'written' status for all bits
of OTP to block the write operation.
Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
---
hw/misc/sifive_u_otp.c | 30 +++++++++++++++++++++++++++++-
include/hw/misc/sifive_u_otp.h | 3 +++
2 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
index c2f3c8e129..b9238d64cb 100644
--- a/hw/misc/sifive_u_otp.c
+++ b/hw/misc/sifive_u_otp.c
@@ -25,6 +25,14 @@
#include "qemu/module.h"
#include "hw/misc/sifive_u_otp.h"
+#define WRITTEN_BIT_ON 0x1
+
+#define SET_FUSEARRAY_BIT(map, i, off, bit) \
+ map[i] = bit ? (map[i] | bit << off) : (map[i] & ~(0x1 << off))
+
+#define GET_FUSEARRAY_BIT(map, i, off) \
+ ((map[i] >> off) & 0x1)
+
static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size)
{
SiFiveUOTPState *s = opaque;
@@ -123,7 +131,24 @@ static void sifive_u_otp_write(void *opaque, hwaddr addr,
s->ptrim = val32;
break;
case SIFIVE_U_OTP_PWE:
- s->pwe = val32;
+ s->pwe = val32 & SIFIVE_U_OTP_PWE_EN;
+
+ /* PWE is enabled. Ignore PAS=1 (no redundancy cell) */
+ if (s->pwe && !s->pas) {
+ if (GET_FUSEARRAY_BIT(s->fuse_wo, s->pa, s->paio)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "write once error: idx<%u>, bit<%u>\n",
+ s->pa, s->paio);
+ break;
+ }
+
+ /* write bit data */
+ SET_FUSEARRAY_BIT(s->fuse, s->pa, s->paio, s->pdin);
+
+ /* update written bit */
+ SET_FUSEARRAY_BIT(s->fuse_wo, s->pa, s->paio, WRITTEN_BIT_ON);
+ }
+
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx
@@ -165,6 +190,9 @@ static void sifive_u_otp_reset(DeviceState *dev)
/* Make a valid content of serial number */
s->fuse[SIFIVE_U_OTP_SERIAL_ADDR] = s->serial;
s->fuse[SIFIVE_U_OTP_SERIAL_ADDR + 1] = ~(s->serial);
+
+ /* Initialize write-once map */
+ memset(s->fuse_wo, 0x00, sizeof(s->fuse_wo));
}
static void sifive_u_otp_class_init(ObjectClass *klass, void *data)
diff --git a/include/hw/misc/sifive_u_otp.h b/include/hw/misc/sifive_u_otp.h
index 82c9176c8f..ebffbc1fa5 100644
--- a/include/hw/misc/sifive_u_otp.h
+++ b/include/hw/misc/sifive_u_otp.h
@@ -36,6 +36,8 @@
#define SIFIVE_U_OTP_PTRIM 0x34
#define SIFIVE_U_OTP_PWE 0x38
+#define SIFIVE_U_OTP_PWE_EN (1 << 0)
+
#define SIFIVE_U_OTP_PCE_EN (1 << 0)
#define SIFIVE_U_OTP_PDSTB_EN (1 << 0)
@@ -75,6 +77,7 @@ struct SiFiveUOTPState {
uint32_t ptrim;
uint32_t pwe;
uint32_t fuse[SIFIVE_U_OTP_NUM_FUSES];
+ uint32_t fuse_wo[SIFIVE_U_OTP_NUM_FUSES];
/* config */
uint32_t serial;
};
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v8 2/2] hw/misc/sifive_u_otp: Add backend drive support
2020-10-20 3:37 ` Green Wan
@ 2020-10-20 3:37 ` Green Wan
-1 siblings, 0 replies; 8+ messages in thread
From: Green Wan @ 2020-10-20 3:37 UTC (permalink / raw)
Cc: alistair23, bmeng.cn, qemu-riscv, qemu-devel, green.wan
Add '-drive' support to OTP device. Allow users to assign a raw file
as OTP image.
test commands for 16k otp.img filled with zero:
$ dd if=/dev/zero of=./otp.img bs=1k count=16
$ ./qemu-system-riscv64 -M sifive_u -m 256M -nographic -bios none \
-kernel ../opensbi/build/platform/sifive/fu540/firmware/fw_payload.elf \
-d guest_errors -drive if=none,format=raw,file=otp.img
Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
---
hw/misc/sifive_u_otp.c | 65 ++++++++++++++++++++++++++++++++++
include/hw/misc/sifive_u_otp.h | 2 ++
2 files changed, 67 insertions(+)
diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
index b9238d64cb..60066375ab 100644
--- a/hw/misc/sifive_u_otp.c
+++ b/hw/misc/sifive_u_otp.c
@@ -19,11 +19,14 @@
*/
#include "qemu/osdep.h"
+#include "qapi/error.h"
#include "hw/qdev-properties.h"
#include "hw/sysbus.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "hw/misc/sifive_u_otp.h"
+#include "sysemu/blockdev.h"
+#include "sysemu/block-backend.h"
#define WRITTEN_BIT_ON 0x1
@@ -54,6 +57,16 @@ static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size)
if ((s->pce & SIFIVE_U_OTP_PCE_EN) &&
(s->pdstb & SIFIVE_U_OTP_PDSTB_EN) &&
(s->ptrim & SIFIVE_U_OTP_PTRIM_EN)) {
+
+ /* read from backend */
+ if (s->blk) {
+ int32_t buf;
+
+ blk_pread(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD, &buf,
+ SIFIVE_U_OTP_FUSE_WORD);
+ return buf;
+ }
+
return s->fuse[s->pa & SIFIVE_U_OTP_PA_MASK];
} else {
return 0xff;
@@ -145,6 +158,12 @@ static void sifive_u_otp_write(void *opaque, hwaddr addr,
/* write bit data */
SET_FUSEARRAY_BIT(s->fuse, s->pa, s->paio, s->pdin);
+ /* write to backend */
+ if (s->blk) {
+ blk_pwrite(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD,
+ &s->fuse[s->pa], SIFIVE_U_OTP_FUSE_WORD, 0);
+ }
+
/* update written bit */
SET_FUSEARRAY_BIT(s->fuse_wo, s->pa, s->paio, WRITTEN_BIT_ON);
}
@@ -168,16 +187,48 @@ static const MemoryRegionOps sifive_u_otp_ops = {
static Property sifive_u_otp_properties[] = {
DEFINE_PROP_UINT32("serial", SiFiveUOTPState, serial, 0),
+ DEFINE_PROP_DRIVE("drive", SiFiveUOTPState, blk),
DEFINE_PROP_END_OF_LIST(),
};
static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
{
SiFiveUOTPState *s = SIFIVE_U_OTP(dev);
+ DriveInfo *dinfo;
memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_u_otp_ops, s,
TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
+
+ dinfo = drive_get_next(IF_NONE);
+ if (dinfo) {
+ int ret;
+ uint64_t perm;
+ int filesize;
+ BlockBackend *blk;
+
+ blk = blk_by_legacy_dinfo(dinfo);
+ filesize = SIFIVE_U_OTP_NUM_FUSES * SIFIVE_U_OTP_FUSE_WORD;
+ if (blk_getlength(blk) < filesize) {
+ error_setg(errp, "OTP drive size < 16K");
+ return;
+ }
+
+ qdev_prop_set_drive_err(dev, "drive", blk, errp);
+
+ if (s->blk) {
+ perm = BLK_PERM_CONSISTENT_READ |
+ (blk_is_read_only(s->blk) ? 0 : BLK_PERM_WRITE);
+ ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp);
+ if (ret < 0) {
+ return;
+ }
+
+ if (blk_pread(s->blk, 0, s->fuse, filesize) != filesize) {
+ error_setg(errp, "failed to read the initial flash content");
+ }
+ }
+ }
}
static void sifive_u_otp_reset(DeviceState *dev)
@@ -191,6 +242,20 @@ static void sifive_u_otp_reset(DeviceState *dev)
s->fuse[SIFIVE_U_OTP_SERIAL_ADDR] = s->serial;
s->fuse[SIFIVE_U_OTP_SERIAL_ADDR + 1] = ~(s->serial);
+ if (s->blk) {
+ /* Put serial number to backend as well*/
+ uint32_t serial_data;
+ int index = SIFIVE_U_OTP_SERIAL_ADDR;
+
+ serial_data = s->serial;
+ blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD,
+ &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0);
+
+ serial_data = ~(s->serial);
+ blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD,
+ &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0);
+ }
+
/* Initialize write-once map */
memset(s->fuse_wo, 0x00, sizeof(s->fuse_wo));
}
diff --git a/include/hw/misc/sifive_u_otp.h b/include/hw/misc/sifive_u_otp.h
index ebffbc1fa5..5d0d7df455 100644
--- a/include/hw/misc/sifive_u_otp.h
+++ b/include/hw/misc/sifive_u_otp.h
@@ -46,6 +46,7 @@
#define SIFIVE_U_OTP_PA_MASK 0xfff
#define SIFIVE_U_OTP_NUM_FUSES 0x1000
+#define SIFIVE_U_OTP_FUSE_WORD 4
#define SIFIVE_U_OTP_SERIAL_ADDR 0xfc
#define SIFIVE_U_OTP_REG_SIZE 0x1000
@@ -80,6 +81,7 @@ struct SiFiveUOTPState {
uint32_t fuse_wo[SIFIVE_U_OTP_NUM_FUSES];
/* config */
uint32_t serial;
+ BlockBackend *blk;
};
#endif /* HW_SIFIVE_U_OTP_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v8 2/2] hw/misc/sifive_u_otp: Add backend drive support
@ 2020-10-20 3:37 ` Green Wan
0 siblings, 0 replies; 8+ messages in thread
From: Green Wan @ 2020-10-20 3:37 UTC (permalink / raw)
Cc: qemu-devel, qemu-riscv, bmeng.cn, alistair23, green.wan
Add '-drive' support to OTP device. Allow users to assign a raw file
as OTP image.
test commands for 16k otp.img filled with zero:
$ dd if=/dev/zero of=./otp.img bs=1k count=16
$ ./qemu-system-riscv64 -M sifive_u -m 256M -nographic -bios none \
-kernel ../opensbi/build/platform/sifive/fu540/firmware/fw_payload.elf \
-d guest_errors -drive if=none,format=raw,file=otp.img
Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
---
hw/misc/sifive_u_otp.c | 65 ++++++++++++++++++++++++++++++++++
include/hw/misc/sifive_u_otp.h | 2 ++
2 files changed, 67 insertions(+)
diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
index b9238d64cb..60066375ab 100644
--- a/hw/misc/sifive_u_otp.c
+++ b/hw/misc/sifive_u_otp.c
@@ -19,11 +19,14 @@
*/
#include "qemu/osdep.h"
+#include "qapi/error.h"
#include "hw/qdev-properties.h"
#include "hw/sysbus.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "hw/misc/sifive_u_otp.h"
+#include "sysemu/blockdev.h"
+#include "sysemu/block-backend.h"
#define WRITTEN_BIT_ON 0x1
@@ -54,6 +57,16 @@ static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size)
if ((s->pce & SIFIVE_U_OTP_PCE_EN) &&
(s->pdstb & SIFIVE_U_OTP_PDSTB_EN) &&
(s->ptrim & SIFIVE_U_OTP_PTRIM_EN)) {
+
+ /* read from backend */
+ if (s->blk) {
+ int32_t buf;
+
+ blk_pread(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD, &buf,
+ SIFIVE_U_OTP_FUSE_WORD);
+ return buf;
+ }
+
return s->fuse[s->pa & SIFIVE_U_OTP_PA_MASK];
} else {
return 0xff;
@@ -145,6 +158,12 @@ static void sifive_u_otp_write(void *opaque, hwaddr addr,
/* write bit data */
SET_FUSEARRAY_BIT(s->fuse, s->pa, s->paio, s->pdin);
+ /* write to backend */
+ if (s->blk) {
+ blk_pwrite(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD,
+ &s->fuse[s->pa], SIFIVE_U_OTP_FUSE_WORD, 0);
+ }
+
/* update written bit */
SET_FUSEARRAY_BIT(s->fuse_wo, s->pa, s->paio, WRITTEN_BIT_ON);
}
@@ -168,16 +187,48 @@ static const MemoryRegionOps sifive_u_otp_ops = {
static Property sifive_u_otp_properties[] = {
DEFINE_PROP_UINT32("serial", SiFiveUOTPState, serial, 0),
+ DEFINE_PROP_DRIVE("drive", SiFiveUOTPState, blk),
DEFINE_PROP_END_OF_LIST(),
};
static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
{
SiFiveUOTPState *s = SIFIVE_U_OTP(dev);
+ DriveInfo *dinfo;
memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_u_otp_ops, s,
TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
+
+ dinfo = drive_get_next(IF_NONE);
+ if (dinfo) {
+ int ret;
+ uint64_t perm;
+ int filesize;
+ BlockBackend *blk;
+
+ blk = blk_by_legacy_dinfo(dinfo);
+ filesize = SIFIVE_U_OTP_NUM_FUSES * SIFIVE_U_OTP_FUSE_WORD;
+ if (blk_getlength(blk) < filesize) {
+ error_setg(errp, "OTP drive size < 16K");
+ return;
+ }
+
+ qdev_prop_set_drive_err(dev, "drive", blk, errp);
+
+ if (s->blk) {
+ perm = BLK_PERM_CONSISTENT_READ |
+ (blk_is_read_only(s->blk) ? 0 : BLK_PERM_WRITE);
+ ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp);
+ if (ret < 0) {
+ return;
+ }
+
+ if (blk_pread(s->blk, 0, s->fuse, filesize) != filesize) {
+ error_setg(errp, "failed to read the initial flash content");
+ }
+ }
+ }
}
static void sifive_u_otp_reset(DeviceState *dev)
@@ -191,6 +242,20 @@ static void sifive_u_otp_reset(DeviceState *dev)
s->fuse[SIFIVE_U_OTP_SERIAL_ADDR] = s->serial;
s->fuse[SIFIVE_U_OTP_SERIAL_ADDR + 1] = ~(s->serial);
+ if (s->blk) {
+ /* Put serial number to backend as well*/
+ uint32_t serial_data;
+ int index = SIFIVE_U_OTP_SERIAL_ADDR;
+
+ serial_data = s->serial;
+ blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD,
+ &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0);
+
+ serial_data = ~(s->serial);
+ blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD,
+ &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0);
+ }
+
/* Initialize write-once map */
memset(s->fuse_wo, 0x00, sizeof(s->fuse_wo));
}
diff --git a/include/hw/misc/sifive_u_otp.h b/include/hw/misc/sifive_u_otp.h
index ebffbc1fa5..5d0d7df455 100644
--- a/include/hw/misc/sifive_u_otp.h
+++ b/include/hw/misc/sifive_u_otp.h
@@ -46,6 +46,7 @@
#define SIFIVE_U_OTP_PA_MASK 0xfff
#define SIFIVE_U_OTP_NUM_FUSES 0x1000
+#define SIFIVE_U_OTP_FUSE_WORD 4
#define SIFIVE_U_OTP_SERIAL_ADDR 0xfc
#define SIFIVE_U_OTP_REG_SIZE 0x1000
@@ -80,6 +81,7 @@ struct SiFiveUOTPState {
uint32_t fuse_wo[SIFIVE_U_OTP_NUM_FUSES];
/* config */
uint32_t serial;
+ BlockBackend *blk;
};
#endif /* HW_SIFIVE_U_OTP_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v8 2/2] hw/misc/sifive_u_otp: Add backend drive support
2020-10-20 3:37 ` Green Wan
@ 2020-10-22 18:30 ` Alistair Francis
-1 siblings, 0 replies; 8+ messages in thread
From: Alistair Francis @ 2020-10-22 18:30 UTC (permalink / raw)
To: Green Wan; +Cc: Bin Meng, open list:RISC-V, qemu-devel@nongnu.org Developers
On Mon, Oct 19, 2020 at 8:37 PM Green Wan <green.wan@sifive.com> wrote:
>
> Add '-drive' support to OTP device. Allow users to assign a raw file
> as OTP image.
>
> test commands for 16k otp.img filled with zero:
>
> $ dd if=/dev/zero of=./otp.img bs=1k count=16
> $ ./qemu-system-riscv64 -M sifive_u -m 256M -nographic -bios none \
> -kernel ../opensbi/build/platform/sifive/fu540/firmware/fw_payload.elf \
> -d guest_errors -drive if=none,format=raw,file=otp.img
>
> Signed-off-by: Green Wan <green.wan@sifive.com>
> Reviewed-by: Bin Meng <bin.meng@windriver.com>
> Tested-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/misc/sifive_u_otp.c | 65 ++++++++++++++++++++++++++++++++++
> include/hw/misc/sifive_u_otp.h | 2 ++
> 2 files changed, 67 insertions(+)
>
> diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
> index b9238d64cb..60066375ab 100644
> --- a/hw/misc/sifive_u_otp.c
> +++ b/hw/misc/sifive_u_otp.c
> @@ -19,11 +19,14 @@
> */
>
> #include "qemu/osdep.h"
> +#include "qapi/error.h"
> #include "hw/qdev-properties.h"
> #include "hw/sysbus.h"
> #include "qemu/log.h"
> #include "qemu/module.h"
> #include "hw/misc/sifive_u_otp.h"
> +#include "sysemu/blockdev.h"
> +#include "sysemu/block-backend.h"
>
> #define WRITTEN_BIT_ON 0x1
>
> @@ -54,6 +57,16 @@ static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size)
> if ((s->pce & SIFIVE_U_OTP_PCE_EN) &&
> (s->pdstb & SIFIVE_U_OTP_PDSTB_EN) &&
> (s->ptrim & SIFIVE_U_OTP_PTRIM_EN)) {
> +
> + /* read from backend */
> + if (s->blk) {
> + int32_t buf;
> +
> + blk_pread(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD, &buf,
> + SIFIVE_U_OTP_FUSE_WORD);
> + return buf;
> + }
> +
> return s->fuse[s->pa & SIFIVE_U_OTP_PA_MASK];
> } else {
> return 0xff;
> @@ -145,6 +158,12 @@ static void sifive_u_otp_write(void *opaque, hwaddr addr,
> /* write bit data */
> SET_FUSEARRAY_BIT(s->fuse, s->pa, s->paio, s->pdin);
>
> + /* write to backend */
> + if (s->blk) {
> + blk_pwrite(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD,
> + &s->fuse[s->pa], SIFIVE_U_OTP_FUSE_WORD, 0);
> + }
> +
> /* update written bit */
> SET_FUSEARRAY_BIT(s->fuse_wo, s->pa, s->paio, WRITTEN_BIT_ON);
> }
> @@ -168,16 +187,48 @@ static const MemoryRegionOps sifive_u_otp_ops = {
>
> static Property sifive_u_otp_properties[] = {
> DEFINE_PROP_UINT32("serial", SiFiveUOTPState, serial, 0),
> + DEFINE_PROP_DRIVE("drive", SiFiveUOTPState, blk),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
> {
> SiFiveUOTPState *s = SIFIVE_U_OTP(dev);
> + DriveInfo *dinfo;
>
> memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_u_otp_ops, s,
> TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE);
> sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
> +
> + dinfo = drive_get_next(IF_NONE);
> + if (dinfo) {
> + int ret;
> + uint64_t perm;
> + int filesize;
> + BlockBackend *blk;
> +
> + blk = blk_by_legacy_dinfo(dinfo);
> + filesize = SIFIVE_U_OTP_NUM_FUSES * SIFIVE_U_OTP_FUSE_WORD;
> + if (blk_getlength(blk) < filesize) {
> + error_setg(errp, "OTP drive size < 16K");
> + return;
> + }
> +
> + qdev_prop_set_drive_err(dev, "drive", blk, errp);
> +
> + if (s->blk) {
> + perm = BLK_PERM_CONSISTENT_READ |
> + (blk_is_read_only(s->blk) ? 0 : BLK_PERM_WRITE);
> + ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp);
> + if (ret < 0) {
> + return;
> + }
> +
> + if (blk_pread(s->blk, 0, s->fuse, filesize) != filesize) {
> + error_setg(errp, "failed to read the initial flash content");
> + }
> + }
> + }
> }
>
> static void sifive_u_otp_reset(DeviceState *dev)
> @@ -191,6 +242,20 @@ static void sifive_u_otp_reset(DeviceState *dev)
> s->fuse[SIFIVE_U_OTP_SERIAL_ADDR] = s->serial;
> s->fuse[SIFIVE_U_OTP_SERIAL_ADDR + 1] = ~(s->serial);
>
> + if (s->blk) {
> + /* Put serial number to backend as well*/
> + uint32_t serial_data;
> + int index = SIFIVE_U_OTP_SERIAL_ADDR;
> +
> + serial_data = s->serial;
> + blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD,
> + &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0);
> +
> + serial_data = ~(s->serial);
> + blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD,
> + &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0);
> + }
> +
> /* Initialize write-once map */
> memset(s->fuse_wo, 0x00, sizeof(s->fuse_wo));
> }
> diff --git a/include/hw/misc/sifive_u_otp.h b/include/hw/misc/sifive_u_otp.h
> index ebffbc1fa5..5d0d7df455 100644
> --- a/include/hw/misc/sifive_u_otp.h
> +++ b/include/hw/misc/sifive_u_otp.h
> @@ -46,6 +46,7 @@
>
> #define SIFIVE_U_OTP_PA_MASK 0xfff
> #define SIFIVE_U_OTP_NUM_FUSES 0x1000
> +#define SIFIVE_U_OTP_FUSE_WORD 4
> #define SIFIVE_U_OTP_SERIAL_ADDR 0xfc
>
> #define SIFIVE_U_OTP_REG_SIZE 0x1000
> @@ -80,6 +81,7 @@ struct SiFiveUOTPState {
> uint32_t fuse_wo[SIFIVE_U_OTP_NUM_FUSES];
> /* config */
> uint32_t serial;
> + BlockBackend *blk;
> };
>
> #endif /* HW_SIFIVE_U_OTP_H */
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v8 2/2] hw/misc/sifive_u_otp: Add backend drive support
@ 2020-10-22 18:30 ` Alistair Francis
0 siblings, 0 replies; 8+ messages in thread
From: Alistair Francis @ 2020-10-22 18:30 UTC (permalink / raw)
To: Green Wan; +Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Bin Meng
On Mon, Oct 19, 2020 at 8:37 PM Green Wan <green.wan@sifive.com> wrote:
>
> Add '-drive' support to OTP device. Allow users to assign a raw file
> as OTP image.
>
> test commands for 16k otp.img filled with zero:
>
> $ dd if=/dev/zero of=./otp.img bs=1k count=16
> $ ./qemu-system-riscv64 -M sifive_u -m 256M -nographic -bios none \
> -kernel ../opensbi/build/platform/sifive/fu540/firmware/fw_payload.elf \
> -d guest_errors -drive if=none,format=raw,file=otp.img
>
> Signed-off-by: Green Wan <green.wan@sifive.com>
> Reviewed-by: Bin Meng <bin.meng@windriver.com>
> Tested-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/misc/sifive_u_otp.c | 65 ++++++++++++++++++++++++++++++++++
> include/hw/misc/sifive_u_otp.h | 2 ++
> 2 files changed, 67 insertions(+)
>
> diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
> index b9238d64cb..60066375ab 100644
> --- a/hw/misc/sifive_u_otp.c
> +++ b/hw/misc/sifive_u_otp.c
> @@ -19,11 +19,14 @@
> */
>
> #include "qemu/osdep.h"
> +#include "qapi/error.h"
> #include "hw/qdev-properties.h"
> #include "hw/sysbus.h"
> #include "qemu/log.h"
> #include "qemu/module.h"
> #include "hw/misc/sifive_u_otp.h"
> +#include "sysemu/blockdev.h"
> +#include "sysemu/block-backend.h"
>
> #define WRITTEN_BIT_ON 0x1
>
> @@ -54,6 +57,16 @@ static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size)
> if ((s->pce & SIFIVE_U_OTP_PCE_EN) &&
> (s->pdstb & SIFIVE_U_OTP_PDSTB_EN) &&
> (s->ptrim & SIFIVE_U_OTP_PTRIM_EN)) {
> +
> + /* read from backend */
> + if (s->blk) {
> + int32_t buf;
> +
> + blk_pread(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD, &buf,
> + SIFIVE_U_OTP_FUSE_WORD);
> + return buf;
> + }
> +
> return s->fuse[s->pa & SIFIVE_U_OTP_PA_MASK];
> } else {
> return 0xff;
> @@ -145,6 +158,12 @@ static void sifive_u_otp_write(void *opaque, hwaddr addr,
> /* write bit data */
> SET_FUSEARRAY_BIT(s->fuse, s->pa, s->paio, s->pdin);
>
> + /* write to backend */
> + if (s->blk) {
> + blk_pwrite(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD,
> + &s->fuse[s->pa], SIFIVE_U_OTP_FUSE_WORD, 0);
> + }
> +
> /* update written bit */
> SET_FUSEARRAY_BIT(s->fuse_wo, s->pa, s->paio, WRITTEN_BIT_ON);
> }
> @@ -168,16 +187,48 @@ static const MemoryRegionOps sifive_u_otp_ops = {
>
> static Property sifive_u_otp_properties[] = {
> DEFINE_PROP_UINT32("serial", SiFiveUOTPState, serial, 0),
> + DEFINE_PROP_DRIVE("drive", SiFiveUOTPState, blk),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
> {
> SiFiveUOTPState *s = SIFIVE_U_OTP(dev);
> + DriveInfo *dinfo;
>
> memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_u_otp_ops, s,
> TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE);
> sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
> +
> + dinfo = drive_get_next(IF_NONE);
> + if (dinfo) {
> + int ret;
> + uint64_t perm;
> + int filesize;
> + BlockBackend *blk;
> +
> + blk = blk_by_legacy_dinfo(dinfo);
> + filesize = SIFIVE_U_OTP_NUM_FUSES * SIFIVE_U_OTP_FUSE_WORD;
> + if (blk_getlength(blk) < filesize) {
> + error_setg(errp, "OTP drive size < 16K");
> + return;
> + }
> +
> + qdev_prop_set_drive_err(dev, "drive", blk, errp);
> +
> + if (s->blk) {
> + perm = BLK_PERM_CONSISTENT_READ |
> + (blk_is_read_only(s->blk) ? 0 : BLK_PERM_WRITE);
> + ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp);
> + if (ret < 0) {
> + return;
> + }
> +
> + if (blk_pread(s->blk, 0, s->fuse, filesize) != filesize) {
> + error_setg(errp, "failed to read the initial flash content");
> + }
> + }
> + }
> }
>
> static void sifive_u_otp_reset(DeviceState *dev)
> @@ -191,6 +242,20 @@ static void sifive_u_otp_reset(DeviceState *dev)
> s->fuse[SIFIVE_U_OTP_SERIAL_ADDR] = s->serial;
> s->fuse[SIFIVE_U_OTP_SERIAL_ADDR + 1] = ~(s->serial);
>
> + if (s->blk) {
> + /* Put serial number to backend as well*/
> + uint32_t serial_data;
> + int index = SIFIVE_U_OTP_SERIAL_ADDR;
> +
> + serial_data = s->serial;
> + blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD,
> + &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0);
> +
> + serial_data = ~(s->serial);
> + blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD,
> + &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0);
> + }
> +
> /* Initialize write-once map */
> memset(s->fuse_wo, 0x00, sizeof(s->fuse_wo));
> }
> diff --git a/include/hw/misc/sifive_u_otp.h b/include/hw/misc/sifive_u_otp.h
> index ebffbc1fa5..5d0d7df455 100644
> --- a/include/hw/misc/sifive_u_otp.h
> +++ b/include/hw/misc/sifive_u_otp.h
> @@ -46,6 +46,7 @@
>
> #define SIFIVE_U_OTP_PA_MASK 0xfff
> #define SIFIVE_U_OTP_NUM_FUSES 0x1000
> +#define SIFIVE_U_OTP_FUSE_WORD 4
> #define SIFIVE_U_OTP_SERIAL_ADDR 0xfc
>
> #define SIFIVE_U_OTP_REG_SIZE 0x1000
> @@ -80,6 +81,7 @@ struct SiFiveUOTPState {
> uint32_t fuse_wo[SIFIVE_U_OTP_NUM_FUSES];
> /* config */
> uint32_t serial;
> + BlockBackend *blk;
> };
>
> #endif /* HW_SIFIVE_U_OTP_H */
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 8+ messages in thread
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2020-10-20 3:37 [PATCH v8 0/2] Add file-backed and write-once features to OTP Green Wan
2020-10-20 3:37 ` Green Wan
2020-10-20 3:37 ` [PATCH v8 1/2] hw/misc/sifive_u_otp: Add write function and write-once protection Green Wan
2020-10-20 3:37 ` Green Wan
2020-10-20 3:37 ` [PATCH v8 2/2] hw/misc/sifive_u_otp: Add backend drive support Green Wan
2020-10-20 3:37 ` Green Wan
2020-10-22 18:30 ` Alistair Francis
2020-10-22 18:30 ` Alistair Francis
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