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From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To: "Z.q. Hou" <zhiqiang.hou@nxp.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>,
	Bjorn Helgaas <helgaas@kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"robh@kernel.org" <robh@kernel.org>,
	"bhelgaas@google.com" <bhelgaas@google.com>,
	"gustavo.pimentel@synopsys.com" <gustavo.pimentel@synopsys.com>
Subject: Re: [PATCH] PCI: dwc: Added link up check in map_bus of dw_child_pcie_ops
Date: Tue, 20 Oct 2020 10:55:27 +0100	[thread overview]
Message-ID: <20201020095527.GA21814@e121166-lin.cambridge.arm.com> (raw)
In-Reply-To: <HE1PR0402MB337161161D04C34247C1D876841F0@HE1PR0402MB3371.eurprd04.prod.outlook.com>

On Tue, Oct 20, 2020 at 02:13:13AM +0000, Z.q. Hou wrote:

[...]

> > > For NXP Layerscape platforms (the ls1028a and ls2088a are also NXP
> > Layerscape platform), as the error response to AXI/AHB was enabled, it will
> > get UR error and trigger SError on AXI bus when it accesses a non-existent
> > BDF on a link down bus. I'm not clear about how it happens on dra7xxx and
> > imx6, since they doesn't enable the error response to AXI/AHB.
> > 
> > That's exactly the case with DRA7xx as the error response is enabled by
> > default in the platform integration.
> 
> Got feedback from the imx6 owner that imx6 like the dra7xx has the
> error response enabled by default.  Now it's clear that the problem on
> all these platforms is the same.

On IMX6, enabled by default and read-only ? Or it can be changed ? What's
the plan for layerscape on this matter ?

Lorenzo

  parent reply	other threads:[~2020-10-20  9:55 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-16  5:41 [PATCH] PCI: dwc: Added link up check in map_bus of dw_child_pcie_ops Zhiqiang Hou
2020-09-16 20:28 ` Rob Herring
2020-09-18 11:02   ` Z.q. Hou
2020-09-18 11:14     ` Michael Walle
2020-09-21 14:48       ` Z.q. Hou
2020-09-18 12:47     ` Bjorn Helgaas
2020-09-21 16:31       ` Z.q. Hou
2020-09-18 15:27     ` Rob Herring
2020-09-24  4:24       ` Z.q. Hou
2020-09-28  9:39         ` Lorenzo Pieralisi
2020-09-29  4:05           ` Z.q. Hou
2020-09-29 15:24             ` Gustavo Pimentel
2020-09-29 17:11               ` Rob Herring
2020-09-30 13:22                 ` Kishon Vijay Abraham I
2020-09-30 15:01                   ` Rob Herring
2020-10-01 13:32                     ` Kishon Vijay Abraham I
2020-10-01 16:46                       ` Michael Walle
2020-10-02  9:29                         ` Naresh Kamboju
2020-10-08 14:46                           ` Naresh Kamboju
2020-10-08 15:12                             ` Rob Herring
2020-10-08 16:51                               ` Naresh Kamboju
2020-10-08 15:08                       ` Lorenzo Pieralisi
2020-10-12 16:31                         ` Kishon Vijay Abraham I
2020-10-12  4:41                       ` Z.q. Hou
2020-10-19 16:13                         ` Lorenzo Pieralisi
2020-10-20  8:07                           ` Kishon Vijay Abraham I
2020-10-12  4:22                 ` Z.q. Hou
2020-10-20  9:48       ` Lorenzo Pieralisi
2020-10-13  9:15 ` Lorenzo Pieralisi
2020-10-14 11:13 ` Lorenzo Pieralisi
2020-10-14 12:37   ` Rob Herring
2020-10-15 22:47 ` Bjorn Helgaas
2020-10-16 11:59   ` Lorenzo Pieralisi
2020-10-19  5:24   ` Z.q. Hou
2020-10-19  5:41     ` Kishon Vijay Abraham I
2020-10-20  2:13       ` Z.q. Hou
2020-10-20  9:12         ` Lorenzo Pieralisi
2020-10-20  9:55         ` Lorenzo Pieralisi [this message]
2020-10-21  8:47           ` Z.q. Hou
2020-10-22  6:20             ` Richard Zhu
2020-10-19 16:26   ` Lorenzo Pieralisi
2020-10-20 10:19   ` Lorenzo Pieralisi

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