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From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org,
	Catalin Marinas <catalin.marinas@arm.com>,
	Marc Zyngier <maz@kernel.org>,
	Peter Zijlstra <peterz@infradead.org>,
	Morten Rasmussen <morten.rasmussen@arm.com>,
	Qais Yousef <qais.yousef@arm.com>,
	Suren Baghdasaryan <surenb@google.com>,
	kernel-team@android.com
Subject: Re: [PATCH 5/6] arm64: Advertise CPUs capable of running 32-bit applcations in sysfs
Date: Wed, 28 Oct 2020 09:37:46 +0100	[thread overview]
Message-ID: <20201028083746.GA1854746@kroah.com> (raw)
In-Reply-To: <20201027215118.27003-6-will@kernel.org>

On Tue, Oct 27, 2020 at 09:51:17PM +0000, Will Deacon wrote:
> Since 32-bit applications will be killed if they are caught trying to
> execute on a 64-bit-only CPU in a mismatched system, advertise the set
> of 32-bit capable CPUs to userspace in sysfs.
> 
> Signed-off-by: Will Deacon <will@kernel.org>
> ---
>  .../ABI/testing/sysfs-devices-system-cpu      |  8 ++++++++
>  arch/arm64/kernel/cpufeature.c                | 19 +++++++++++++++++++
>  2 files changed, 27 insertions(+)
> 
> diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu
> index b555df825447..19893fb8e870 100644
> --- a/Documentation/ABI/testing/sysfs-devices-system-cpu
> +++ b/Documentation/ABI/testing/sysfs-devices-system-cpu
> @@ -472,6 +472,14 @@ Description:	AArch64 CPU registers
>  		'identification' directory exposes the CPU ID registers for
>  		 identifying model and revision of the CPU.
>  
> +What:		/sys/devices/system/cpu/aarch32_el0
> +Date:		October 2020
> +Contact:	Linux ARM Kernel Mailing list <linux-arm-kernel@lists.infradead.org>
> +Description:	Identifies the subset of CPUs in the system that can execute
> +		AArch32 (32-bit ARM) applications. If absent, then all or none
> +		of the CPUs can execute AArch32 applications and execve() will
> +		behave accordingly.

How is this value represented?  A hint here would be nice.

> +
>  What:		/sys/devices/system/cpu/cpu#/cpu_capacity
>  Date:		December 2016
>  Contact:	Linux kernel mailing list <linux-kernel@vger.kernel.org>
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 2e2219cbd54c..9f29d4d1ef7e 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -67,6 +67,7 @@
>  #include <linux/crash_dump.h>
>  #include <linux/sort.h>
>  #include <linux/stop_machine.h>
> +#include <linux/sysfs.h>
>  #include <linux/types.h>
>  #include <linux/mm.h>
>  #include <linux/cpu.h>
> @@ -1236,6 +1237,24 @@ bool system_has_mismatched_32bit_el0(void)
>  	return fld == ID_AA64PFR0_EL0_64BIT_ONLY;
>  }
>  
> +static ssize_t aarch32_el0_show(struct kobject *kobj,
> +				struct kobj_attribute *attr, char *buf)
> +{
> +	const struct cpumask *mask = system_32bit_el0_cpumask();
> +	return sprintf(buf, "%*pbl\n", cpumask_pr_args(mask));

sysfs_emit()?

And a blank line to make checkpatch.pl happy :)

> +}
> +static const struct kobj_attribute aarch32_el0_attr = __ATTR_RO(aarch32_el0);

DEVICE_ATTR_RO()?

> +
> +static int __init aarch32_el0_sysfs_init(void)
> +{
> +	if (!__allow_mismatched_32bit_el0)
> +		return 0;
> +
> +	return sysfs_create_file(&cpu_subsys.dev_root->kobj,
> +				 &aarch32_el0_attr.attr);

device_create_file() please, dev_root is a struct device, no need to
"thunk" down to a "raw" sysfs call.

thanks,

greg k-h

WARNING: multiple messages have this Message-ID (diff)
From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To: Will Deacon <will@kernel.org>
Cc: linux-arch@vger.kernel.org, kernel-team@android.com,
	Peter Zijlstra <peterz@infradead.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Qais Yousef <qais.yousef@arm.com>, Marc Zyngier <maz@kernel.org>,
	Suren Baghdasaryan <surenb@google.com>,
	Morten Rasmussen <morten.rasmussen@arm.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 5/6] arm64: Advertise CPUs capable of running 32-bit applcations in sysfs
Date: Wed, 28 Oct 2020 09:37:46 +0100	[thread overview]
Message-ID: <20201028083746.GA1854746@kroah.com> (raw)
In-Reply-To: <20201027215118.27003-6-will@kernel.org>

On Tue, Oct 27, 2020 at 09:51:17PM +0000, Will Deacon wrote:
> Since 32-bit applications will be killed if they are caught trying to
> execute on a 64-bit-only CPU in a mismatched system, advertise the set
> of 32-bit capable CPUs to userspace in sysfs.
> 
> Signed-off-by: Will Deacon <will@kernel.org>
> ---
>  .../ABI/testing/sysfs-devices-system-cpu      |  8 ++++++++
>  arch/arm64/kernel/cpufeature.c                | 19 +++++++++++++++++++
>  2 files changed, 27 insertions(+)
> 
> diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu
> index b555df825447..19893fb8e870 100644
> --- a/Documentation/ABI/testing/sysfs-devices-system-cpu
> +++ b/Documentation/ABI/testing/sysfs-devices-system-cpu
> @@ -472,6 +472,14 @@ Description:	AArch64 CPU registers
>  		'identification' directory exposes the CPU ID registers for
>  		 identifying model and revision of the CPU.
>  
> +What:		/sys/devices/system/cpu/aarch32_el0
> +Date:		October 2020
> +Contact:	Linux ARM Kernel Mailing list <linux-arm-kernel@lists.infradead.org>
> +Description:	Identifies the subset of CPUs in the system that can execute
> +		AArch32 (32-bit ARM) applications. If absent, then all or none
> +		of the CPUs can execute AArch32 applications and execve() will
> +		behave accordingly.

How is this value represented?  A hint here would be nice.

> +
>  What:		/sys/devices/system/cpu/cpu#/cpu_capacity
>  Date:		December 2016
>  Contact:	Linux kernel mailing list <linux-kernel@vger.kernel.org>
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 2e2219cbd54c..9f29d4d1ef7e 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -67,6 +67,7 @@
>  #include <linux/crash_dump.h>
>  #include <linux/sort.h>
>  #include <linux/stop_machine.h>
> +#include <linux/sysfs.h>
>  #include <linux/types.h>
>  #include <linux/mm.h>
>  #include <linux/cpu.h>
> @@ -1236,6 +1237,24 @@ bool system_has_mismatched_32bit_el0(void)
>  	return fld == ID_AA64PFR0_EL0_64BIT_ONLY;
>  }
>  
> +static ssize_t aarch32_el0_show(struct kobject *kobj,
> +				struct kobj_attribute *attr, char *buf)
> +{
> +	const struct cpumask *mask = system_32bit_el0_cpumask();
> +	return sprintf(buf, "%*pbl\n", cpumask_pr_args(mask));

sysfs_emit()?

And a blank line to make checkpatch.pl happy :)

> +}
> +static const struct kobj_attribute aarch32_el0_attr = __ATTR_RO(aarch32_el0);

DEVICE_ATTR_RO()?

> +
> +static int __init aarch32_el0_sysfs_init(void)
> +{
> +	if (!__allow_mismatched_32bit_el0)
> +		return 0;
> +
> +	return sysfs_create_file(&cpu_subsys.dev_root->kobj,
> +				 &aarch32_el0_attr.attr);

device_create_file() please, dev_root is a struct device, no need to
"thunk" down to a "raw" sysfs call.

thanks,

greg k-h

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2020-10-29  1:01 UTC|newest]

Thread overview: 96+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-27 21:51 [PATCH 0/6] An alternative series for asymmetric AArch32 systems Will Deacon
2020-10-27 21:51 ` Will Deacon
2020-10-27 21:51 ` [PATCH 1/6] KVM: arm64: Handle Asymmetric " Will Deacon
2020-10-27 21:51   ` Will Deacon
2020-10-27 21:51 ` [PATCH 2/6] arm64: Allow mismatched 32-bit EL0 support Will Deacon
2020-10-27 21:51   ` Will Deacon
2020-10-28 11:12   ` Catalin Marinas
2020-10-28 11:12     ` Catalin Marinas
2020-10-28 11:17     ` Will Deacon
2020-10-28 11:17       ` Will Deacon
2020-10-28 11:22       ` Catalin Marinas
2020-10-28 11:22         ` Catalin Marinas
2020-10-28 11:23         ` Will Deacon
2020-10-28 11:23           ` Will Deacon
2020-10-28 11:49           ` Catalin Marinas
2020-10-28 11:49             ` Catalin Marinas
2020-10-28 12:40             ` Will Deacon
2020-10-28 12:40               ` Will Deacon
2020-10-28 18:56               ` Catalin Marinas
2020-10-28 18:56                 ` Catalin Marinas
2020-10-29 22:20                 ` Will Deacon
2020-10-29 22:20                   ` Will Deacon
2020-10-30 11:18                   ` Catalin Marinas
2020-10-30 11:18                     ` Catalin Marinas
2020-10-30 16:13                     ` Will Deacon
2020-10-30 16:13                       ` Will Deacon
2020-11-02 11:44                       ` Catalin Marinas
2020-11-02 11:44                         ` Catalin Marinas
2020-11-05 21:38                         ` Will Deacon
2020-11-05 21:38                           ` Will Deacon
2020-11-06 12:54                           ` Qais Yousef
2020-11-06 12:54                             ` Qais Yousef
2020-11-06 13:00                             ` Will Deacon
2020-11-06 13:00                               ` Will Deacon
2020-11-06 14:48                               ` Qais Yousef
2020-11-06 14:48                                 ` Qais Yousef
2020-11-09 13:52                                 ` Will Deacon
2020-11-09 13:52                                   ` Will Deacon
2020-11-11 16:27                                   ` Qais Yousef
2020-11-11 16:27                                     ` Qais Yousef
2020-11-12 10:24                                     ` Will Deacon
2020-11-12 10:24                                       ` Will Deacon
2020-11-12 11:55                                       ` Qais Yousef
2020-11-12 11:55                                         ` Qais Yousef
2020-11-12 16:49                                         ` Qais Yousef
2020-11-12 16:49                                           ` Qais Yousef
2020-11-12 17:06                                           ` Marc Zyngier
2020-11-12 17:06                                             ` Marc Zyngier
2020-11-12 17:36                                             ` Qais Yousef
2020-11-12 17:36                                               ` Qais Yousef
2020-11-12 17:44                                               ` Will Deacon
2020-11-12 17:44                                                 ` Will Deacon
2020-11-12 17:36                                           ` Will Deacon
2020-11-12 17:36                                             ` Will Deacon
2020-11-13 10:45                                             ` Qais Yousef
2020-11-13 10:45                                               ` Qais Yousef
2020-11-06 14:30                           ` Catalin Marinas
2020-11-06 14:30                             ` Catalin Marinas
2020-10-28 11:18   ` Catalin Marinas
2020-10-28 11:18     ` Catalin Marinas
2020-10-28 11:21     ` Will Deacon
2020-10-28 11:21       ` Will Deacon
2020-10-27 21:51 ` [PATCH 3/6] KVM: arm64: Kill 32-bit vCPUs on systems with mismatched " Will Deacon
2020-10-27 21:51   ` Will Deacon
2020-10-27 21:51 ` [PATCH 4/6] arm64: Kill 32-bit applications scheduled on 64-bit-only CPUs Will Deacon
2020-10-27 21:51   ` Will Deacon
2020-10-28 12:10   ` Catalin Marinas
2020-10-28 12:10     ` Catalin Marinas
2020-10-28 12:36     ` Will Deacon
2020-10-28 12:36       ` Will Deacon
2020-10-27 21:51 ` [PATCH 5/6] arm64: Advertise CPUs capable of running 32-bit applcations in sysfs Will Deacon
2020-10-27 21:51   ` Will Deacon
2020-10-28  8:37   ` Greg Kroah-Hartman [this message]
2020-10-28  8:37     ` Greg Kroah-Hartman
2020-10-28  9:51     ` Will Deacon
2020-10-28  9:51       ` Will Deacon
2020-10-28 12:15   ` Catalin Marinas
2020-10-28 12:15     ` Catalin Marinas
2020-10-28 12:27     ` Will Deacon
2020-10-28 12:27       ` Will Deacon
2020-10-28 15:14       ` Catalin Marinas
2020-10-28 15:14         ` Catalin Marinas
2020-10-28 15:35         ` Will Deacon
2020-10-28 15:35           ` Will Deacon
2020-10-27 21:51 ` [PATCH 6/6] arm64: Hook up cmdline parameter to allow mismatched 32-bit EL0 Will Deacon
2020-10-27 21:51   ` Will Deacon
2020-10-29 18:42 ` [PATCH 0/6] An alternative series for asymmetric AArch32 systems Suren Baghdasaryan
2020-10-29 18:42   ` Suren Baghdasaryan
2020-10-29 22:17   ` Will Deacon
2020-10-29 22:17     ` Will Deacon
2020-10-30 16:16 ` Marc Zyngier
2020-10-30 16:16   ` Marc Zyngier
2020-10-30 16:24   ` Will Deacon
2020-10-30 16:24     ` Will Deacon
2020-10-30 17:04     ` Marc Zyngier
2020-10-30 17:04       ` Marc Zyngier

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