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* [PULL 00/18] riscv-to-apply queue
@ 2020-10-29 14:13 Alistair Francis
  2020-10-29 14:13 ` [PULL 01/18] hw/riscv: sifive_u: Allow passing custom DTB Alistair Francis
                   ` (18 more replies)
  0 siblings, 19 replies; 21+ messages in thread
From: Alistair Francis @ 2020-10-29 14:13 UTC (permalink / raw)
  To: qemu-devel, peter.maydell; +Cc: alistair23, Alistair Francis

The following changes since commit c0444009147aa935d52d5acfc6b70094bb42b0dd:

  Merge remote-tracking branch 'remotes/armbru/tags/pull-qmp-2020-10-27' into staging (2020-10-29 10:03:32 +0000)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20201029

for you to fetch changes up to e041badcd4ac644a67f02f8765095a5ff7a24d47:

  hw/riscv: microchip_pfsoc: Hook the I2C1 controller (2020-10-29 07:11:14 -0700)

----------------------------------------------------------------
This series adds support for migration to RISC-V QEMU and expands the
Microchip PFSoC to allow unmodified HSS and Linux boots.

----------------------------------------------------------------
Anup Patel (2):
      hw/riscv: sifive_u: Allow passing custom DTB
      hw/riscv: virt: Allow passing custom DTB

Bin Meng (10):
      hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps
      hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support
      hw/riscv: microchip_pfsoc: Connect DDR memory controller modules
      hw/misc: Add Microchip PolarFire SoC IOSCB module support
      hw/riscv: microchip_pfsoc: Connect the IOSCB module
      hw/misc: Add Microchip PolarFire SoC SYSREG module support
      hw/riscv: microchip_pfsoc: Connect the SYSREG module
      hw/riscv: microchip_pfsoc: Map the reserved memory at address 0
      hw/riscv: microchip_pfsoc: Correct DDR memory map
      hw/riscv: microchip_pfsoc: Hook the I2C1 controller

Yifei Jiang (6):
      target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit
      target/riscv: Add basic vmstate description of CPU
      target/riscv: Add PMP state description
      target/riscv: Add H extension state description
      target/riscv: Add V extension state description
      target/riscv: Add sifive_plic vmstate

 include/hw/intc/sifive_plic.h       |   1 +
 include/hw/misc/mchp_pfsoc_dmc.h    |  56 +++++++++
 include/hw/misc/mchp_pfsoc_ioscb.h  |  50 ++++++++
 include/hw/misc/mchp_pfsoc_sysreg.h |  39 ++++++
 include/hw/riscv/microchip_pfsoc.h  |  18 ++-
 target/riscv/cpu.h                  |  24 ++--
 target/riscv/cpu_bits.h             |  19 +--
 target/riscv/internals.h            |   4 +
 target/riscv/pmp.h                  |   2 +
 hw/intc/sifive_plic.c               |  26 +++-
 hw/misc/mchp_pfsoc_dmc.c            | 216 ++++++++++++++++++++++++++++++++
 hw/misc/mchp_pfsoc_ioscb.c          | 242 ++++++++++++++++++++++++++++++++++++
 hw/misc/mchp_pfsoc_sysreg.c         |  99 +++++++++++++++
 hw/riscv/microchip_pfsoc.c          | 123 +++++++++++++++---
 hw/riscv/sifive_u.c                 |  28 +++--
 hw/riscv/virt.c                     |  27 ++--
 target/riscv/cpu.c                  |  16 +--
 target/riscv/cpu_helper.c           |  35 ++----
 target/riscv/csr.c                  |  18 +--
 target/riscv/machine.c              | 196 +++++++++++++++++++++++++++++
 target/riscv/op_helper.c            |  11 +-
 target/riscv/pmp.c                  |  29 +++--
 MAINTAINERS                         |   6 +
 hw/misc/Kconfig                     |   9 ++
 hw/misc/meson.build                 |   3 +
 hw/riscv/Kconfig                    |   3 +
 target/riscv/meson.build            |   3 +-
 27 files changed, 1177 insertions(+), 126 deletions(-)
 create mode 100644 include/hw/misc/mchp_pfsoc_dmc.h
 create mode 100644 include/hw/misc/mchp_pfsoc_ioscb.h
 create mode 100644 include/hw/misc/mchp_pfsoc_sysreg.h
 create mode 100644 hw/misc/mchp_pfsoc_dmc.c
 create mode 100644 hw/misc/mchp_pfsoc_ioscb.c
 create mode 100644 hw/misc/mchp_pfsoc_sysreg.c
 create mode 100644 target/riscv/machine.c


^ permalink raw reply	[flat|nested] 21+ messages in thread
end of thread, other threads:[~2020-11-01 16:27 UTC | newest]

Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-10-29 14:13 [PULL 00/18] riscv-to-apply queue Alistair Francis
2020-10-29 14:13 ` [PULL 01/18] hw/riscv: sifive_u: Allow passing custom DTB Alistair Francis
2020-10-29 14:13 ` [PULL 02/18] hw/riscv: virt: " Alistair Francis
2020-10-29 14:13 ` [PULL 03/18] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit Alistair Francis
2020-10-29 14:13 ` [PULL 04/18] target/riscv: Add basic vmstate description of CPU Alistair Francis
2020-10-29 14:13 ` [PULL 05/18] target/riscv: Add PMP state description Alistair Francis
2020-10-29 14:13 ` [PULL 06/18] target/riscv: Add H extension " Alistair Francis
2020-10-29 14:13 ` [PULL 07/18] target/riscv: Add V " Alistair Francis
2020-10-29 14:13 ` [PULL 08/18] target/riscv: Add sifive_plic vmstate Alistair Francis
2020-10-29 14:13 ` [PULL 09/18] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps Alistair Francis
2020-10-29 14:13 ` [PULL 10/18] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support Alistair Francis
2020-10-29 14:13 ` [PULL 11/18] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules Alistair Francis
2020-10-29 14:13 ` [PULL 12/18] hw/misc: Add Microchip PolarFire SoC IOSCB module support Alistair Francis
2020-10-29 14:13 ` [PULL 13/18] hw/riscv: microchip_pfsoc: Connect the IOSCB module Alistair Francis
2020-10-29 14:13 ` [PULL 14/18] hw/misc: Add Microchip PolarFire SoC SYSREG module support Alistair Francis
2020-10-29 14:13 ` [PULL 15/18] hw/riscv: microchip_pfsoc: Connect the SYSREG module Alistair Francis
2020-10-29 14:13 ` [PULL 16/18] hw/riscv: microchip_pfsoc: Map the reserved memory at address 0 Alistair Francis
2020-10-29 14:13 ` [PULL 17/18] hw/riscv: microchip_pfsoc: Correct DDR memory map Alistair Francis
2020-10-29 14:13 ` [PULL 18/18] hw/riscv: microchip_pfsoc: Hook the I2C1 controller Alistair Francis
2020-11-01 14:02 ` [PULL 00/18] riscv-to-apply queue Peter Maydell
2020-11-01 16:27   ` Bin Meng

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