* [Intel-gfx] [PATCH v4 00/16] HDCP 2.2 and HDCP 1.4 Gen12 DP MST support
@ 2020-10-27 16:41 ` Anshuman Gupta
0 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:41 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula, seanpaul
This is v4 version to test with IGT https://patchwork.freedesktop.org/series/82987/
This has addressed the review comments from Uma.
It has been also tested manually with IGT above series.
[PATCH v4 10/16] misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len
has an Ack from Tomas to merge it via drm-intel.
[PATCH v4 11/16] drm/hdcp: Max MST content streams
has an Ack from drm-misc maintainer to merge it via dm-intel.
Test-with: 20201023100709.5211-2-karthik.b.s@intel.com
Anshuman Gupta (16):
drm/i915/hdcp: Update CP property in update_pipe
drm/i915/hdcp: Get conn while content_type changed
drm/i915/hotplug: Handle CP_IRQ for DP-MST
drm/i915/hdcp: DP MST transcoder for link and stream
drm/i915/hdcp: Move HDCP enc status timeout to header
drm/i915/hdcp: HDCP stream encryption support
drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support
drm/i915/hdcp: Pass dig_port to intel_hdcp_init
drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port
misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len
drm/hdcp: Max MST content streams
drm/i915/hdcp: MST streams support in hdcp port_data
drm/i915/hdcp: Pass connector to check_2_2_link
drm/i915/hdcp: Add HDCP 2.2 stream register
drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks
drm/i915/hdcp: Enable HDCP 2.2 MST support
drivers/gpu/drm/i915/display/intel_ddi.c | 14 +-
drivers/gpu/drm/i915/display/intel_ddi.h | 6 +-
.../drm/i915/display/intel_display_types.h | 20 +-
drivers/gpu/drm/i915/display/intel_dp.c | 14 +-
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 167 ++++++++--
drivers/gpu/drm/i915/display/intel_dp_mst.c | 12 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 285 ++++++++++++++----
drivers/gpu/drm/i915/display/intel_hdcp.h | 8 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 19 +-
drivers/gpu/drm/i915/i915_reg.h | 31 ++
drivers/misc/mei/hdcp/mei_hdcp.c | 3 +-
include/drm/drm_hdcp.h | 8 +-
12 files changed, 466 insertions(+), 121 deletions(-)
--
2.26.2
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^ permalink raw reply [flat|nested] 111+ messages in thread
* [PATCH v4 01/16] drm/i915/hdcp: Update CP property in update_pipe
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
@ 2020-10-27 16:41 ` Anshuman Gupta
-1 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:41 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: jani.nikula, uma.shankar, seanpaul, Anshuman Gupta, juston.li
When crtc state need_modeset is true it is not necessary
it is going to be a real modeset, it can turns to be a
fastset instead of modeset.
This turns content protection property to be DESIRED and hdcp
update_pipe left with property to be in DESIRED state but
actual hdcp->value was ENABLED.
This issue is caught with DP MST setup, where we have multiple
connector in same DP_MST topology. When disabling HDCP on one of
DP MST connector leads to set the crtc state need_modeset to true
for all other crtc driving the other DP-MST topology connectors.
This turns up other DP MST connectors CP property to be DESIRED
despite the actual hdcp->value is ENABLED.
Above scenario fails the DP MST HDCP IGT test, disabling HDCP on
one MST stream should not cause to disable HDCP on another MST
stream on same DP MST topology.
v2:
Fix WARN_ON(connector->base.registration_state == DRM_CONNECTOR_REGISTERED)
v3:
Commit log improvement. [Uma]
Added a comment before scheduling prop_work. [Uma]
Fixes: 33f9a623bfc6 ("drm/i915/hdcp: Update CP as per the kernel internal state")
Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index b2a4bbcfdcd2..eee8263405b9 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -2221,6 +2221,14 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state,
desired_and_not_enabled =
hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED;
mutex_unlock(&hdcp->mutex);
+ /*
+ * If HDCP already ENABLED and CP property is DESIRED, schedule
+ * prop_work to update correct CP property to user space.
+ */
+ if (!desired_and_not_enabled && !content_protection_type_changed) {
+ drm_connector_get(&connector->base);
+ schedule_work(&hdcp->prop_work);
+ }
}
if (desired_and_not_enabled || content_protection_type_changed)
--
2.26.2
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^ permalink raw reply related [flat|nested] 111+ messages in thread* [Intel-gfx] [PATCH v4 01/16] drm/i915/hdcp: Update CP property in update_pipe
@ 2020-10-27 16:41 ` Anshuman Gupta
0 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:41 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula, seanpaul
When crtc state need_modeset is true it is not necessary
it is going to be a real modeset, it can turns to be a
fastset instead of modeset.
This turns content protection property to be DESIRED and hdcp
update_pipe left with property to be in DESIRED state but
actual hdcp->value was ENABLED.
This issue is caught with DP MST setup, where we have multiple
connector in same DP_MST topology. When disabling HDCP on one of
DP MST connector leads to set the crtc state need_modeset to true
for all other crtc driving the other DP-MST topology connectors.
This turns up other DP MST connectors CP property to be DESIRED
despite the actual hdcp->value is ENABLED.
Above scenario fails the DP MST HDCP IGT test, disabling HDCP on
one MST stream should not cause to disable HDCP on another MST
stream on same DP MST topology.
v2:
Fix WARN_ON(connector->base.registration_state == DRM_CONNECTOR_REGISTERED)
v3:
Commit log improvement. [Uma]
Added a comment before scheduling prop_work. [Uma]
Fixes: 33f9a623bfc6 ("drm/i915/hdcp: Update CP as per the kernel internal state")
Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index b2a4bbcfdcd2..eee8263405b9 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -2221,6 +2221,14 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state,
desired_and_not_enabled =
hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED;
mutex_unlock(&hdcp->mutex);
+ /*
+ * If HDCP already ENABLED and CP property is DESIRED, schedule
+ * prop_work to update correct CP property to user space.
+ */
+ if (!desired_and_not_enabled && !content_protection_type_changed) {
+ drm_connector_get(&connector->base);
+ schedule_work(&hdcp->prop_work);
+ }
}
if (desired_and_not_enabled || content_protection_type_changed)
--
2.26.2
_______________________________________________
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^ permalink raw reply related [flat|nested] 111+ messages in thread* RE: [PATCH v4 01/16] drm/i915/hdcp: Update CP property in update_pipe
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
@ 2020-11-02 7:45 ` Shankar, Uma
-1 siblings, 0 replies; 111+ messages in thread
From: Shankar, Uma @ 2020-11-02 7:45 UTC (permalink / raw)
To: Gupta, Anshuman, intel-gfx, dri-devel
Cc: Nikula, Jani, seanpaul, Li, Juston, Gupta, Anshuman
> -----Original Message-----
> From: Anshuman Gupta <anshuman.gupta@intel.com>
> Sent: Tuesday, October 27, 2020 10:12 PM
> To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: seanpaul@chromium.org; Nikula, Jani <jani.nikula@intel.com>; C,
> Ramalingam <ramalingam.c@intel.com>; Li, Juston <juston.li@intel.com>;
> Shankar, Uma <uma.shankar@intel.com>; Gupta, Anshuman
> <anshuman.gupta@intel.com>
> Subject: [PATCH v4 01/16] drm/i915/hdcp: Update CP property in update_pipe
>
> When crtc state need_modeset is true it is not necessary it is going to be a real
> modeset, it can turns to be a fastset instead of modeset.
> This turns content protection property to be DESIRED and hdcp update_pipe left
> with property to be in DESIRED state but actual hdcp->value was ENABLED.
>
> This issue is caught with DP MST setup, where we have multiple connector in
> same DP_MST topology. When disabling HDCP on one of DP MST connector leads
> to set the crtc state need_modeset to true for all other crtc driving the other DP-
> MST topology connectors.
> This turns up other DP MST connectors CP property to be DESIRED despite the
> actual hdcp->value is ENABLED.
> Above scenario fails the DP MST HDCP IGT test, disabling HDCP on one MST
> stream should not cause to disable HDCP on another MST stream on same DP
> MST topology.
>
> v2:
> Fix WARN_ON(connector->base.registration_state ==
> DRM_CONNECTOR_REGISTERED)
> v3:
> Commit log improvement. [Uma]
> Added a comment before scheduling prop_work. [Uma]
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Fixes: 33f9a623bfc6 ("drm/i915/hdcp: Update CP as per the kernel internal
> state")
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index b2a4bbcfdcd2..eee8263405b9 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -2221,6 +2221,14 @@ void intel_hdcp_update_pipe(struct
> intel_atomic_state *state,
> desired_and_not_enabled =
> hdcp->value !=
> DRM_MODE_CONTENT_PROTECTION_ENABLED;
> mutex_unlock(&hdcp->mutex);
> + /*
> + * If HDCP already ENABLED and CP property is DESIRED, schedule
> + * prop_work to update correct CP property to user space.
> + */
> + if (!desired_and_not_enabled &&
> !content_protection_type_changed) {
> + drm_connector_get(&connector->base);
> + schedule_work(&hdcp->prop_work);
> + }
> }
>
> if (desired_and_not_enabled || content_protection_type_changed)
> --
> 2.26.2
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 01/16] drm/i915/hdcp: Update CP property in update_pipe
@ 2020-11-02 7:45 ` Shankar, Uma
0 siblings, 0 replies; 111+ messages in thread
From: Shankar, Uma @ 2020-11-02 7:45 UTC (permalink / raw)
To: Gupta, Anshuman, intel-gfx, dri-devel; +Cc: Nikula, Jani, seanpaul
> -----Original Message-----
> From: Anshuman Gupta <anshuman.gupta@intel.com>
> Sent: Tuesday, October 27, 2020 10:12 PM
> To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: seanpaul@chromium.org; Nikula, Jani <jani.nikula@intel.com>; C,
> Ramalingam <ramalingam.c@intel.com>; Li, Juston <juston.li@intel.com>;
> Shankar, Uma <uma.shankar@intel.com>; Gupta, Anshuman
> <anshuman.gupta@intel.com>
> Subject: [PATCH v4 01/16] drm/i915/hdcp: Update CP property in update_pipe
>
> When crtc state need_modeset is true it is not necessary it is going to be a real
> modeset, it can turns to be a fastset instead of modeset.
> This turns content protection property to be DESIRED and hdcp update_pipe left
> with property to be in DESIRED state but actual hdcp->value was ENABLED.
>
> This issue is caught with DP MST setup, where we have multiple connector in
> same DP_MST topology. When disabling HDCP on one of DP MST connector leads
> to set the crtc state need_modeset to true for all other crtc driving the other DP-
> MST topology connectors.
> This turns up other DP MST connectors CP property to be DESIRED despite the
> actual hdcp->value is ENABLED.
> Above scenario fails the DP MST HDCP IGT test, disabling HDCP on one MST
> stream should not cause to disable HDCP on another MST stream on same DP
> MST topology.
>
> v2:
> Fix WARN_ON(connector->base.registration_state ==
> DRM_CONNECTOR_REGISTERED)
> v3:
> Commit log improvement. [Uma]
> Added a comment before scheduling prop_work. [Uma]
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Fixes: 33f9a623bfc6 ("drm/i915/hdcp: Update CP as per the kernel internal
> state")
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index b2a4bbcfdcd2..eee8263405b9 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -2221,6 +2221,14 @@ void intel_hdcp_update_pipe(struct
> intel_atomic_state *state,
> desired_and_not_enabled =
> hdcp->value !=
> DRM_MODE_CONTENT_PROTECTION_ENABLED;
> mutex_unlock(&hdcp->mutex);
> + /*
> + * If HDCP already ENABLED and CP property is DESIRED, schedule
> + * prop_work to update correct CP property to user space.
> + */
> + if (!desired_and_not_enabled &&
> !content_protection_type_changed) {
> + drm_connector_get(&connector->base);
> + schedule_work(&hdcp->prop_work);
> + }
> }
>
> if (desired_and_not_enabled || content_protection_type_changed)
> --
> 2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v4 01/16] drm/i915/hdcp: Update CP property in update_pipe
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
@ 2020-11-05 13:18 ` Ramalingam C
-1 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-05 13:18 UTC (permalink / raw)
To: Anshuman Gupta
Cc: jani.nikula, intel-gfx, dri-devel, uma.shankar, seanpaul, juston.li
On 2020-10-27 at 22:11:53 +0530, Anshuman Gupta wrote:
> When crtc state need_modeset is true it is not necessary
> it is going to be a real modeset, it can turns to be a
> fastset instead of modeset.
> This turns content protection property to be DESIRED and hdcp
> update_pipe left with property to be in DESIRED state but
> actual hdcp->value was ENABLED.
>
> This issue is caught with DP MST setup, where we have multiple
> connector in same DP_MST topology. When disabling HDCP on one of
> DP MST connector leads to set the crtc state need_modeset to true
> for all other crtc driving the other DP-MST topology connectors.
> This turns up other DP MST connectors CP property to be DESIRED
> despite the actual hdcp->value is ENABLED.
> Above scenario fails the DP MST HDCP IGT test, disabling HDCP on
> one MST stream should not cause to disable HDCP on another MST
> stream on same DP MST topology.
>
> v2:
> Fix WARN_ON(connector->base.registration_state == DRM_CONNECTOR_REGISTERED)
> v3:
> Commit log improvement. [Uma]
> Added a comment before scheduling prop_work. [Uma]
>
> Fixes: 33f9a623bfc6 ("drm/i915/hdcp: Update CP as per the kernel internal state")
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index b2a4bbcfdcd2..eee8263405b9 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -2221,6 +2221,14 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state,
> desired_and_not_enabled =
> hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED;
> mutex_unlock(&hdcp->mutex);
> + /*
> + * If HDCP already ENABLED and CP property is DESIRED, schedule
> + * prop_work to update correct CP property to user space.
> + */
> + if (!desired_and_not_enabled && !content_protection_type_changed) {
> + drm_connector_get(&connector->base);
Sorry for late review.
why do we need this? and where do we release the connector ref?
-Ram
> + schedule_work(&hdcp->prop_work);
> + }
> }
>
> if (desired_and_not_enabled || content_protection_type_changed)
> --
> 2.26.2
>
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^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 01/16] drm/i915/hdcp: Update CP property in update_pipe
@ 2020-11-05 13:18 ` Ramalingam C
0 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-05 13:18 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: jani.nikula, intel-gfx, dri-devel, seanpaul
On 2020-10-27 at 22:11:53 +0530, Anshuman Gupta wrote:
> When crtc state need_modeset is true it is not necessary
> it is going to be a real modeset, it can turns to be a
> fastset instead of modeset.
> This turns content protection property to be DESIRED and hdcp
> update_pipe left with property to be in DESIRED state but
> actual hdcp->value was ENABLED.
>
> This issue is caught with DP MST setup, where we have multiple
> connector in same DP_MST topology. When disabling HDCP on one of
> DP MST connector leads to set the crtc state need_modeset to true
> for all other crtc driving the other DP-MST topology connectors.
> This turns up other DP MST connectors CP property to be DESIRED
> despite the actual hdcp->value is ENABLED.
> Above scenario fails the DP MST HDCP IGT test, disabling HDCP on
> one MST stream should not cause to disable HDCP on another MST
> stream on same DP MST topology.
>
> v2:
> Fix WARN_ON(connector->base.registration_state == DRM_CONNECTOR_REGISTERED)
> v3:
> Commit log improvement. [Uma]
> Added a comment before scheduling prop_work. [Uma]
>
> Fixes: 33f9a623bfc6 ("drm/i915/hdcp: Update CP as per the kernel internal state")
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index b2a4bbcfdcd2..eee8263405b9 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -2221,6 +2221,14 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state,
> desired_and_not_enabled =
> hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED;
> mutex_unlock(&hdcp->mutex);
> + /*
> + * If HDCP already ENABLED and CP property is DESIRED, schedule
> + * prop_work to update correct CP property to user space.
> + */
> + if (!desired_and_not_enabled && !content_protection_type_changed) {
> + drm_connector_get(&connector->base);
Sorry for late review.
why do we need this? and where do we release the connector ref?
-Ram
> + schedule_work(&hdcp->prop_work);
> + }
> }
>
> if (desired_and_not_enabled || content_protection_type_changed)
> --
> 2.26.2
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 01/16] drm/i915/hdcp: Update CP property in update_pipe
2020-11-05 13:18 ` [Intel-gfx] " Ramalingam C
@ 2020-11-05 13:21 ` Ramalingam C
-1 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-05 13:21 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: jani.nikula, intel-gfx, seanpaul, dri-devel
On 2020-11-05 at 18:48:02 +0530, Ramalingam C wrote:
> On 2020-10-27 at 22:11:53 +0530, Anshuman Gupta wrote:
> > When crtc state need_modeset is true it is not necessary
> > it is going to be a real modeset, it can turns to be a
> > fastset instead of modeset.
> > This turns content protection property to be DESIRED and hdcp
> > update_pipe left with property to be in DESIRED state but
> > actual hdcp->value was ENABLED.
> >
> > This issue is caught with DP MST setup, where we have multiple
> > connector in same DP_MST topology. When disabling HDCP on one of
> > DP MST connector leads to set the crtc state need_modeset to true
> > for all other crtc driving the other DP-MST topology connectors.
> > This turns up other DP MST connectors CP property to be DESIRED
> > despite the actual hdcp->value is ENABLED.
> > Above scenario fails the DP MST HDCP IGT test, disabling HDCP on
> > one MST stream should not cause to disable HDCP on another MST
> > stream on same DP MST topology.
> >
> > v2:
> > Fix WARN_ON(connector->base.registration_state == DRM_CONNECTOR_REGISTERED)
> > v3:
> > Commit log improvement. [Uma]
> > Added a comment before scheduling prop_work. [Uma]
> >
> > Fixes: 33f9a623bfc6 ("drm/i915/hdcp: Update CP as per the kernel internal state")
> > Cc: Ramalingam C <ramalingam.c@intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index b2a4bbcfdcd2..eee8263405b9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -2221,6 +2221,14 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state,
> > desired_and_not_enabled =
> > hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED;
> > mutex_unlock(&hdcp->mutex);
> > + /*
> > + * If HDCP already ENABLED and CP property is DESIRED, schedule
> > + * prop_work to update correct CP property to user space.
> > + */
> > + if (!desired_and_not_enabled && !content_protection_type_changed) {
> > + drm_connector_get(&connector->base);
> Sorry for late review.
>
> why do we need this? and where do we release the connector ref?
ignore it seems like prop work is expecting the caller to get ref.
In that case in intel_hdcp_update_pipe() previous scheduling of
prop_work needs to take a ref. Missing?
-Ram
>
> -Ram
> > + schedule_work(&hdcp->prop_work);
> > + }
> > }
> >
> > if (desired_and_not_enabled || content_protection_type_changed)
> > --
> > 2.26.2
> >
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 01/16] drm/i915/hdcp: Update CP property in update_pipe
@ 2020-11-05 13:21 ` Ramalingam C
0 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-05 13:21 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: jani.nikula, intel-gfx, seanpaul, dri-devel
On 2020-11-05 at 18:48:02 +0530, Ramalingam C wrote:
> On 2020-10-27 at 22:11:53 +0530, Anshuman Gupta wrote:
> > When crtc state need_modeset is true it is not necessary
> > it is going to be a real modeset, it can turns to be a
> > fastset instead of modeset.
> > This turns content protection property to be DESIRED and hdcp
> > update_pipe left with property to be in DESIRED state but
> > actual hdcp->value was ENABLED.
> >
> > This issue is caught with DP MST setup, where we have multiple
> > connector in same DP_MST topology. When disabling HDCP on one of
> > DP MST connector leads to set the crtc state need_modeset to true
> > for all other crtc driving the other DP-MST topology connectors.
> > This turns up other DP MST connectors CP property to be DESIRED
> > despite the actual hdcp->value is ENABLED.
> > Above scenario fails the DP MST HDCP IGT test, disabling HDCP on
> > one MST stream should not cause to disable HDCP on another MST
> > stream on same DP MST topology.
> >
> > v2:
> > Fix WARN_ON(connector->base.registration_state == DRM_CONNECTOR_REGISTERED)
> > v3:
> > Commit log improvement. [Uma]
> > Added a comment before scheduling prop_work. [Uma]
> >
> > Fixes: 33f9a623bfc6 ("drm/i915/hdcp: Update CP as per the kernel internal state")
> > Cc: Ramalingam C <ramalingam.c@intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index b2a4bbcfdcd2..eee8263405b9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -2221,6 +2221,14 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state,
> > desired_and_not_enabled =
> > hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED;
> > mutex_unlock(&hdcp->mutex);
> > + /*
> > + * If HDCP already ENABLED and CP property is DESIRED, schedule
> > + * prop_work to update correct CP property to user space.
> > + */
> > + if (!desired_and_not_enabled && !content_protection_type_changed) {
> > + drm_connector_get(&connector->base);
> Sorry for late review.
>
> why do we need this? and where do we release the connector ref?
ignore it seems like prop work is expecting the caller to get ref.
In that case in intel_hdcp_update_pipe() previous scheduling of
prop_work needs to take a ref. Missing?
-Ram
>
> -Ram
> > + schedule_work(&hdcp->prop_work);
> > + }
> > }
> >
> > if (desired_and_not_enabled || content_protection_type_changed)
> > --
> > 2.26.2
> >
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 01/16] drm/i915/hdcp: Update CP property in update_pipe
2020-11-05 13:21 ` Ramalingam C
@ 2020-11-05 13:26 ` Ramalingam C
-1 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-05 13:26 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: jani.nikula, intel-gfx, seanpaul, dri-devel
On 2020-11-05 at 18:51:57 +0530, Ramalingam C wrote:
> On 2020-11-05 at 18:48:02 +0530, Ramalingam C wrote:
> > On 2020-10-27 at 22:11:53 +0530, Anshuman Gupta wrote:
> > > When crtc state need_modeset is true it is not necessary
> > > it is going to be a real modeset, it can turns to be a
> > > fastset instead of modeset.
> > > This turns content protection property to be DESIRED and hdcp
> > > update_pipe left with property to be in DESIRED state but
> > > actual hdcp->value was ENABLED.
> > >
> > > This issue is caught with DP MST setup, where we have multiple
> > > connector in same DP_MST topology. When disabling HDCP on one of
> > > DP MST connector leads to set the crtc state need_modeset to true
> > > for all other crtc driving the other DP-MST topology connectors.
> > > This turns up other DP MST connectors CP property to be DESIRED
> > > despite the actual hdcp->value is ENABLED.
> > > Above scenario fails the DP MST HDCP IGT test, disabling HDCP on
> > > one MST stream should not cause to disable HDCP on another MST
> > > stream on same DP MST topology.
> > >
> > > v2:
> > > Fix WARN_ON(connector->base.registration_state == DRM_CONNECTOR_REGISTERED)
> > > v3:
> > > Commit log improvement. [Uma]
> > > Added a comment before scheduling prop_work. [Uma]
> > >
> > > Fixes: 33f9a623bfc6 ("drm/i915/hdcp: Update CP as per the kernel internal state")
> > > Cc: Ramalingam C <ramalingam.c@intel.com>
> > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_hdcp.c | 8 ++++++++
> > > 1 file changed, 8 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > index b2a4bbcfdcd2..eee8263405b9 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > @@ -2221,6 +2221,14 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state,
> > > desired_and_not_enabled =
> > > hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED;
> > > mutex_unlock(&hdcp->mutex);
> > > + /*
> > > + * If HDCP already ENABLED and CP property is DESIRED, schedule
> > > + * prop_work to update correct CP property to user space.
> > > + */
> > > + if (!desired_and_not_enabled && !content_protection_type_changed) {
> > > + drm_connector_get(&connector->base);
> > Sorry for late review.
> >
> > why do we need this? and where do we release the connector ref?
> ignore it seems like prop work is expecting the caller to get ref.
> In that case in intel_hdcp_update_pipe() previous scheduling of
> prop_work needs to take a ref. Missing?
Got the answer from the next patch.
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
>
> -Ram
> >
> > -Ram
> > > + schedule_work(&hdcp->prop_work);
> > > + }
> > > }
> > >
> > > if (desired_and_not_enabled || content_protection_type_changed)
> > > --
> > > 2.26.2
> > >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 01/16] drm/i915/hdcp: Update CP property in update_pipe
@ 2020-11-05 13:26 ` Ramalingam C
0 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-05 13:26 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: jani.nikula, intel-gfx, seanpaul, dri-devel
On 2020-11-05 at 18:51:57 +0530, Ramalingam C wrote:
> On 2020-11-05 at 18:48:02 +0530, Ramalingam C wrote:
> > On 2020-10-27 at 22:11:53 +0530, Anshuman Gupta wrote:
> > > When crtc state need_modeset is true it is not necessary
> > > it is going to be a real modeset, it can turns to be a
> > > fastset instead of modeset.
> > > This turns content protection property to be DESIRED and hdcp
> > > update_pipe left with property to be in DESIRED state but
> > > actual hdcp->value was ENABLED.
> > >
> > > This issue is caught with DP MST setup, where we have multiple
> > > connector in same DP_MST topology. When disabling HDCP on one of
> > > DP MST connector leads to set the crtc state need_modeset to true
> > > for all other crtc driving the other DP-MST topology connectors.
> > > This turns up other DP MST connectors CP property to be DESIRED
> > > despite the actual hdcp->value is ENABLED.
> > > Above scenario fails the DP MST HDCP IGT test, disabling HDCP on
> > > one MST stream should not cause to disable HDCP on another MST
> > > stream on same DP MST topology.
> > >
> > > v2:
> > > Fix WARN_ON(connector->base.registration_state == DRM_CONNECTOR_REGISTERED)
> > > v3:
> > > Commit log improvement. [Uma]
> > > Added a comment before scheduling prop_work. [Uma]
> > >
> > > Fixes: 33f9a623bfc6 ("drm/i915/hdcp: Update CP as per the kernel internal state")
> > > Cc: Ramalingam C <ramalingam.c@intel.com>
> > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_hdcp.c | 8 ++++++++
> > > 1 file changed, 8 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > index b2a4bbcfdcd2..eee8263405b9 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > @@ -2221,6 +2221,14 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state,
> > > desired_and_not_enabled =
> > > hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED;
> > > mutex_unlock(&hdcp->mutex);
> > > + /*
> > > + * If HDCP already ENABLED and CP property is DESIRED, schedule
> > > + * prop_work to update correct CP property to user space.
> > > + */
> > > + if (!desired_and_not_enabled && !content_protection_type_changed) {
> > > + drm_connector_get(&connector->base);
> > Sorry for late review.
> >
> > why do we need this? and where do we release the connector ref?
> ignore it seems like prop work is expecting the caller to get ref.
> In that case in intel_hdcp_update_pipe() previous scheduling of
> prop_work needs to take a ref. Missing?
Got the answer from the next patch.
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
>
> -Ram
> >
> > -Ram
> > > + schedule_work(&hdcp->prop_work);
> > > + }
> > > }
> > >
> > > if (desired_and_not_enabled || content_protection_type_changed)
> > > --
> > > 2.26.2
> > >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread
* [PATCH v4 02/16] drm/i915/hdcp: Get conn while content_type changed
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
@ 2020-10-27 16:41 ` Anshuman Gupta
-1 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:41 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: jani.nikula, uma.shankar, seanpaul, Anshuman Gupta, juston.li
Get DRM connector reference count while scheduling a prop work
to avoid any possible destroy of DRM connector when it is in
DRM_CONNECTOR_REGISTERED state.
Fixes: a6597faa2d59 ("drm/i915: Protect workers against disappearing connectors")
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index eee8263405b9..b9d8825e2bb1 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -2210,6 +2210,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state,
if (content_protection_type_changed) {
mutex_lock(&hdcp->mutex);
hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
+ drm_connector_get(&connector->base);
schedule_work(&hdcp->prop_work);
mutex_unlock(&hdcp->mutex);
}
--
2.26.2
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 111+ messages in thread* [Intel-gfx] [PATCH v4 02/16] drm/i915/hdcp: Get conn while content_type changed
@ 2020-10-27 16:41 ` Anshuman Gupta
0 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:41 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula, seanpaul
Get DRM connector reference count while scheduling a prop work
to avoid any possible destroy of DRM connector when it is in
DRM_CONNECTOR_REGISTERED state.
Fixes: a6597faa2d59 ("drm/i915: Protect workers against disappearing connectors")
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index eee8263405b9..b9d8825e2bb1 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -2210,6 +2210,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state,
if (content_protection_type_changed) {
mutex_lock(&hdcp->mutex);
hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
+ drm_connector_get(&connector->base);
schedule_work(&hdcp->prop_work);
mutex_unlock(&hdcp->mutex);
}
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 111+ messages in thread* RE: [PATCH v4 02/16] drm/i915/hdcp: Get conn while content_type changed
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
@ 2020-11-02 7:45 ` Shankar, Uma
-1 siblings, 0 replies; 111+ messages in thread
From: Shankar, Uma @ 2020-11-02 7:45 UTC (permalink / raw)
To: Gupta, Anshuman, intel-gfx, dri-devel
Cc: Nikula, Jani, seanpaul, Li, Juston, Gupta, Anshuman
> -----Original Message-----
> From: Anshuman Gupta <anshuman.gupta@intel.com>
> Sent: Tuesday, October 27, 2020 10:12 PM
> To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: seanpaul@chromium.org; Nikula, Jani <jani.nikula@intel.com>; C,
> Ramalingam <ramalingam.c@intel.com>; Li, Juston <juston.li@intel.com>;
> Shankar, Uma <uma.shankar@intel.com>; Gupta, Anshuman
> <anshuman.gupta@intel.com>
> Subject: [PATCH v4 02/16] drm/i915/hdcp: Get conn while content_type changed
>
> Get DRM connector reference count while scheduling a prop work to avoid any
> possible destroy of DRM connector when it is in DRM_CONNECTOR_REGISTERED
> state.
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Fixes: a6597faa2d59 ("drm/i915: Protect workers against disappearing
> connectors")
> Cc: Sean Paul <seanpaul@chromium.org>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index eee8263405b9..b9d8825e2bb1 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -2210,6 +2210,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state
> *state,
> if (content_protection_type_changed) {
> mutex_lock(&hdcp->mutex);
> hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
> + drm_connector_get(&connector->base);
> schedule_work(&hdcp->prop_work);
> mutex_unlock(&hdcp->mutex);
> }
> --
> 2.26.2
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 02/16] drm/i915/hdcp: Get conn while content_type changed
@ 2020-11-02 7:45 ` Shankar, Uma
0 siblings, 0 replies; 111+ messages in thread
From: Shankar, Uma @ 2020-11-02 7:45 UTC (permalink / raw)
To: Gupta, Anshuman, intel-gfx, dri-devel; +Cc: Nikula, Jani, seanpaul
> -----Original Message-----
> From: Anshuman Gupta <anshuman.gupta@intel.com>
> Sent: Tuesday, October 27, 2020 10:12 PM
> To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: seanpaul@chromium.org; Nikula, Jani <jani.nikula@intel.com>; C,
> Ramalingam <ramalingam.c@intel.com>; Li, Juston <juston.li@intel.com>;
> Shankar, Uma <uma.shankar@intel.com>; Gupta, Anshuman
> <anshuman.gupta@intel.com>
> Subject: [PATCH v4 02/16] drm/i915/hdcp: Get conn while content_type changed
>
> Get DRM connector reference count while scheduling a prop work to avoid any
> possible destroy of DRM connector when it is in DRM_CONNECTOR_REGISTERED
> state.
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Fixes: a6597faa2d59 ("drm/i915: Protect workers against disappearing
> connectors")
> Cc: Sean Paul <seanpaul@chromium.org>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index eee8263405b9..b9d8825e2bb1 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -2210,6 +2210,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state
> *state,
> if (content_protection_type_changed) {
> mutex_lock(&hdcp->mutex);
> hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
> + drm_connector_get(&connector->base);
> schedule_work(&hdcp->prop_work);
> mutex_unlock(&hdcp->mutex);
> }
> --
> 2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v4 02/16] drm/i915/hdcp: Get conn while content_type changed
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
@ 2020-11-05 13:23 ` Ramalingam C
-1 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-05 13:23 UTC (permalink / raw)
To: Anshuman Gupta
Cc: jani.nikula, intel-gfx, dri-devel, uma.shankar, seanpaul, juston.li
On 2020-10-27 at 22:11:54 +0530, Anshuman Gupta wrote:
> Get DRM connector reference count while scheduling a prop work
> to avoid any possible destroy of DRM connector when it is in
> DRM_CONNECTOR_REGISTERED state.
>
> Fixes: a6597faa2d59 ("drm/i915: Protect workers against disappearing connectors")
> Cc: Sean Paul <seanpaul@chromium.org>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index eee8263405b9..b9d8825e2bb1 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -2210,6 +2210,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state,
> if (content_protection_type_changed) {
> mutex_lock(&hdcp->mutex);
> hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
> + drm_connector_get(&connector->base);
haa... just commented about missing of this get ref in previous patch.
ignore it.
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
-Ram
> schedule_work(&hdcp->prop_work);
> mutex_unlock(&hdcp->mutex);
> }
> --
> 2.26.2
>
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^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 02/16] drm/i915/hdcp: Get conn while content_type changed
@ 2020-11-05 13:23 ` Ramalingam C
0 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-05 13:23 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: jani.nikula, intel-gfx, dri-devel, seanpaul
On 2020-10-27 at 22:11:54 +0530, Anshuman Gupta wrote:
> Get DRM connector reference count while scheduling a prop work
> to avoid any possible destroy of DRM connector when it is in
> DRM_CONNECTOR_REGISTERED state.
>
> Fixes: a6597faa2d59 ("drm/i915: Protect workers against disappearing connectors")
> Cc: Sean Paul <seanpaul@chromium.org>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index eee8263405b9..b9d8825e2bb1 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -2210,6 +2210,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state,
> if (content_protection_type_changed) {
> mutex_lock(&hdcp->mutex);
> hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
> + drm_connector_get(&connector->base);
haa... just commented about missing of this get ref in previous patch.
ignore it.
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
-Ram
> schedule_work(&hdcp->prop_work);
> mutex_unlock(&hdcp->mutex);
> }
> --
> 2.26.2
>
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread
* [PATCH v4 03/16] drm/i915/hotplug: Handle CP_IRQ for DP-MST
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
@ 2020-10-27 16:41 ` Anshuman Gupta
-1 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:41 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: jani.nikula, uma.shankar, seanpaul, Anshuman Gupta, juston.li
Handle CP_IRQ in DEVICE_SERVICE_IRQ_VECTOR_ESI0
It requires to call intel_hdcp_handle_cp_irq() in case
of CP_IRQ is triggered by a sink in DP-MST topology.
Cc: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 818daab252f3..21c6c9828cd7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5657,6 +5657,17 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
"Could not write test response to sink\n");
}
+static void
+intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, bool *handled)
+{
+ drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, handled);
+
+ if (esi[1] & DP_CP_IRQ) {
+ intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
+ *handled = true;
+ }
+}
+
/**
* intel_dp_check_mst_status - service any pending MST interrupts, check link status
* @intel_dp: Intel DP struct
@@ -5701,7 +5712,8 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp)
drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
- drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
+ intel_dp_mst_hpd_irq(intel_dp, esi, &handled);
+
if (!handled)
break;
--
2.26.2
_______________________________________________
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^ permalink raw reply related [flat|nested] 111+ messages in thread* [Intel-gfx] [PATCH v4 03/16] drm/i915/hotplug: Handle CP_IRQ for DP-MST
@ 2020-10-27 16:41 ` Anshuman Gupta
0 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:41 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula, seanpaul
Handle CP_IRQ in DEVICE_SERVICE_IRQ_VECTOR_ESI0
It requires to call intel_hdcp_handle_cp_irq() in case
of CP_IRQ is triggered by a sink in DP-MST topology.
Cc: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 818daab252f3..21c6c9828cd7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5657,6 +5657,17 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
"Could not write test response to sink\n");
}
+static void
+intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, bool *handled)
+{
+ drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, handled);
+
+ if (esi[1] & DP_CP_IRQ) {
+ intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
+ *handled = true;
+ }
+}
+
/**
* intel_dp_check_mst_status - service any pending MST interrupts, check link status
* @intel_dp: Intel DP struct
@@ -5701,7 +5712,8 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp)
drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
- drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
+ intel_dp_mst_hpd_irq(intel_dp, esi, &handled);
+
if (!handled)
break;
--
2.26.2
_______________________________________________
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^ permalink raw reply related [flat|nested] 111+ messages in thread* Re: [PATCH v4 03/16] drm/i915/hotplug: Handle CP_IRQ for DP-MST
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
@ 2020-11-06 12:00 ` Ramalingam C
-1 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-06 12:00 UTC (permalink / raw)
To: Anshuman Gupta
Cc: jani.nikula, intel-gfx, dri-devel, uma.shankar, seanpaul, juston.li
On 2020-10-27 at 22:11:55 +0530, Anshuman Gupta wrote:
> Handle CP_IRQ in DEVICE_SERVICE_IRQ_VECTOR_ESI0
> It requires to call intel_hdcp_handle_cp_irq() in case
> of CP_IRQ is triggered by a sink in DP-MST topology.
>
> Cc: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 818daab252f3..21c6c9828cd7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5657,6 +5657,17 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
> "Could not write test response to sink\n");
> }
>
> +static void
> +intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, bool *handled)
> +{
> + drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, handled);
> +
> + if (esi[1] & DP_CP_IRQ) {
> + intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
> + *handled = true;
> + }
> +}
> +
> /**
> * intel_dp_check_mst_status - service any pending MST interrupts, check link status
> * @intel_dp: Intel DP struct
> @@ -5701,7 +5712,8 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp)
>
> drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
>
> - drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
> + intel_dp_mst_hpd_irq(intel_dp, esi, &handled);
> +
> if (!handled)
> break;
>
> --
> 2.26.2
>
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 03/16] drm/i915/hotplug: Handle CP_IRQ for DP-MST
@ 2020-11-06 12:00 ` Ramalingam C
0 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-06 12:00 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: jani.nikula, intel-gfx, dri-devel, seanpaul
On 2020-10-27 at 22:11:55 +0530, Anshuman Gupta wrote:
> Handle CP_IRQ in DEVICE_SERVICE_IRQ_VECTOR_ESI0
> It requires to call intel_hdcp_handle_cp_irq() in case
> of CP_IRQ is triggered by a sink in DP-MST topology.
>
> Cc: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 818daab252f3..21c6c9828cd7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5657,6 +5657,17 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
> "Could not write test response to sink\n");
> }
>
> +static void
> +intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, bool *handled)
> +{
> + drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, handled);
> +
> + if (esi[1] & DP_CP_IRQ) {
> + intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
> + *handled = true;
> + }
> +}
> +
> /**
> * intel_dp_check_mst_status - service any pending MST interrupts, check link status
> * @intel_dp: Intel DP struct
> @@ -5701,7 +5712,8 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp)
>
> drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
>
> - drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
> + intel_dp_mst_hpd_irq(intel_dp, esi, &handled);
> +
> if (!handled)
> break;
>
> --
> 2.26.2
>
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^ permalink raw reply [flat|nested] 111+ messages in thread
* [PATCH v4 04/16] drm/i915/hdcp: DP MST transcoder for link and stream
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
@ 2020-10-27 16:41 ` Anshuman Gupta
-1 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:41 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: jani.nikula, uma.shankar, seanpaul, Anshuman Gupta, juston.li
Gen12 has H/W delta with respect to HDCP{1.x,2.x} display engine
instances lies in Transcoder instead of DDI as in Gen11.
This requires hdcp driver to use mst_master_transcoder for link
authentication and stream transcoder for stream encryption
separately.
This will be used for both HDCP 1.4 and HDCP 2.2 over DP MST
on Gen12.
Cc: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
.../gpu/drm/i915/display/intel_display_types.h | 2 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 15 +++++++++++----
drivers/gpu/drm/i915/display/intel_hdcp.h | 2 +-
5 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 63380b166c25..9fce623e951e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4059,7 +4059,7 @@ static void intel_enable_ddi(struct intel_atomic_state *state,
if (conn_state->content_protection ==
DRM_MODE_CONTENT_PROTECTION_DESIRED)
intel_hdcp_enable(to_intel_connector(conn_state->connector),
- crtc_state->cpu_transcoder,
+ crtc_state,
(u8)conn_state->hdcp_content_type);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index f6f0626649e0..c47124a679b6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -432,6 +432,8 @@ struct intel_hdcp {
* Hence caching the transcoder here.
*/
enum transcoder cpu_transcoder;
+ /* Only used for DP MST stream encryption */
+ enum transcoder stream_transcoder;
};
struct intel_connector {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index c8fcec4d0788..16865b200062 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -568,7 +568,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
if (conn_state->content_protection ==
DRM_MODE_CONTENT_PROTECTION_DESIRED)
intel_hdcp_enable(to_intel_connector(conn_state->connector),
- pipe_config->cpu_transcoder,
+ pipe_config,
(u8)conn_state->hdcp_content_type);
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index b9d8825e2bb1..fc5de48456ad 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -2095,7 +2095,7 @@ int intel_hdcp_init(struct intel_connector *connector,
}
int intel_hdcp_enable(struct intel_connector *connector,
- enum transcoder cpu_transcoder, u8 content_type)
+ const struct intel_crtc_state *pipe_config, u8 content_type)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
@@ -2111,10 +2111,17 @@ int intel_hdcp_enable(struct intel_connector *connector,
drm_WARN_ON(&dev_priv->drm,
hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED);
hdcp->content_type = content_type;
- hdcp->cpu_transcoder = cpu_transcoder;
+
+ if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) {
+ hdcp->cpu_transcoder = pipe_config->mst_master_transcoder;
+ hdcp->stream_transcoder = pipe_config->cpu_transcoder;
+ } else {
+ hdcp->cpu_transcoder = pipe_config->cpu_transcoder;
+ hdcp->stream_transcoder = INVALID_TRANSCODER;
+ }
if (INTEL_GEN(dev_priv) >= 12)
- hdcp->port_data.fw_tc = intel_get_mei_fw_tc(cpu_transcoder);
+ hdcp->port_data.fw_tc = intel_get_mei_fw_tc(hdcp->cpu_transcoder);
/*
* Considering that HDCP2.2 is more secure than HDCP1.4, If the setup
@@ -2234,7 +2241,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state,
if (desired_and_not_enabled || content_protection_type_changed)
intel_hdcp_enable(connector,
- crtc_state->cpu_transcoder,
+ crtc_state,
(u8)conn_state->hdcp_content_type);
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h
index 1bbf5b67ed0a..bc51c1e9b481 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.h
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
@@ -25,7 +25,7 @@ void intel_hdcp_atomic_check(struct drm_connector *connector,
int intel_hdcp_init(struct intel_connector *connector, enum port port,
const struct intel_hdcp_shim *hdcp_shim);
int intel_hdcp_enable(struct intel_connector *connector,
- enum transcoder cpu_transcoder, u8 content_type);
+ const struct intel_crtc_state *pipe_config, u8 content_type);
int intel_hdcp_disable(struct intel_connector *connector);
void intel_hdcp_update_pipe(struct intel_atomic_state *state,
struct intel_encoder *encoder,
--
2.26.2
_______________________________________________
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^ permalink raw reply related [flat|nested] 111+ messages in thread* [Intel-gfx] [PATCH v4 04/16] drm/i915/hdcp: DP MST transcoder for link and stream
@ 2020-10-27 16:41 ` Anshuman Gupta
0 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:41 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula, seanpaul
Gen12 has H/W delta with respect to HDCP{1.x,2.x} display engine
instances lies in Transcoder instead of DDI as in Gen11.
This requires hdcp driver to use mst_master_transcoder for link
authentication and stream transcoder for stream encryption
separately.
This will be used for both HDCP 1.4 and HDCP 2.2 over DP MST
on Gen12.
Cc: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
.../gpu/drm/i915/display/intel_display_types.h | 2 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 15 +++++++++++----
drivers/gpu/drm/i915/display/intel_hdcp.h | 2 +-
5 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 63380b166c25..9fce623e951e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4059,7 +4059,7 @@ static void intel_enable_ddi(struct intel_atomic_state *state,
if (conn_state->content_protection ==
DRM_MODE_CONTENT_PROTECTION_DESIRED)
intel_hdcp_enable(to_intel_connector(conn_state->connector),
- crtc_state->cpu_transcoder,
+ crtc_state,
(u8)conn_state->hdcp_content_type);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index f6f0626649e0..c47124a679b6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -432,6 +432,8 @@ struct intel_hdcp {
* Hence caching the transcoder here.
*/
enum transcoder cpu_transcoder;
+ /* Only used for DP MST stream encryption */
+ enum transcoder stream_transcoder;
};
struct intel_connector {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index c8fcec4d0788..16865b200062 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -568,7 +568,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
if (conn_state->content_protection ==
DRM_MODE_CONTENT_PROTECTION_DESIRED)
intel_hdcp_enable(to_intel_connector(conn_state->connector),
- pipe_config->cpu_transcoder,
+ pipe_config,
(u8)conn_state->hdcp_content_type);
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index b9d8825e2bb1..fc5de48456ad 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -2095,7 +2095,7 @@ int intel_hdcp_init(struct intel_connector *connector,
}
int intel_hdcp_enable(struct intel_connector *connector,
- enum transcoder cpu_transcoder, u8 content_type)
+ const struct intel_crtc_state *pipe_config, u8 content_type)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
@@ -2111,10 +2111,17 @@ int intel_hdcp_enable(struct intel_connector *connector,
drm_WARN_ON(&dev_priv->drm,
hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED);
hdcp->content_type = content_type;
- hdcp->cpu_transcoder = cpu_transcoder;
+
+ if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) {
+ hdcp->cpu_transcoder = pipe_config->mst_master_transcoder;
+ hdcp->stream_transcoder = pipe_config->cpu_transcoder;
+ } else {
+ hdcp->cpu_transcoder = pipe_config->cpu_transcoder;
+ hdcp->stream_transcoder = INVALID_TRANSCODER;
+ }
if (INTEL_GEN(dev_priv) >= 12)
- hdcp->port_data.fw_tc = intel_get_mei_fw_tc(cpu_transcoder);
+ hdcp->port_data.fw_tc = intel_get_mei_fw_tc(hdcp->cpu_transcoder);
/*
* Considering that HDCP2.2 is more secure than HDCP1.4, If the setup
@@ -2234,7 +2241,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state,
if (desired_and_not_enabled || content_protection_type_changed)
intel_hdcp_enable(connector,
- crtc_state->cpu_transcoder,
+ crtc_state,
(u8)conn_state->hdcp_content_type);
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h
index 1bbf5b67ed0a..bc51c1e9b481 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.h
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
@@ -25,7 +25,7 @@ void intel_hdcp_atomic_check(struct drm_connector *connector,
int intel_hdcp_init(struct intel_connector *connector, enum port port,
const struct intel_hdcp_shim *hdcp_shim);
int intel_hdcp_enable(struct intel_connector *connector,
- enum transcoder cpu_transcoder, u8 content_type);
+ const struct intel_crtc_state *pipe_config, u8 content_type);
int intel_hdcp_disable(struct intel_connector *connector);
void intel_hdcp_update_pipe(struct intel_atomic_state *state,
struct intel_encoder *encoder,
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 111+ messages in thread* Re: [PATCH v4 04/16] drm/i915/hdcp: DP MST transcoder for link and stream
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
@ 2020-11-05 13:52 ` Ramalingam C
-1 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-05 13:52 UTC (permalink / raw)
To: Anshuman Gupta
Cc: jani.nikula, intel-gfx, dri-devel, uma.shankar, seanpaul, juston.li
On 2020-10-27 at 22:11:56 +0530, Anshuman Gupta wrote:
> Gen12 has H/W delta with respect to HDCP{1.x,2.x} display engine
> instances lies in Transcoder instead of DDI as in Gen11.
>
> This requires hdcp driver to use mst_master_transcoder for link
> authentication and stream transcoder for stream encryption
> separately.
>
> This will be used for both HDCP 1.4 and HDCP 2.2 over DP MST
> on Gen12.
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
> .../gpu/drm/i915/display/intel_display_types.h | 2 ++
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
> drivers/gpu/drm/i915/display/intel_hdcp.c | 15 +++++++++++----
> drivers/gpu/drm/i915/display/intel_hdcp.h | 2 +-
> 5 files changed, 16 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 63380b166c25..9fce623e951e 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4059,7 +4059,7 @@ static void intel_enable_ddi(struct intel_atomic_state *state,
> if (conn_state->content_protection ==
> DRM_MODE_CONTENT_PROTECTION_DESIRED)
> intel_hdcp_enable(to_intel_connector(conn_state->connector),
> - crtc_state->cpu_transcoder,
> + crtc_state,
> (u8)conn_state->hdcp_content_type);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index f6f0626649e0..c47124a679b6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -432,6 +432,8 @@ struct intel_hdcp {
> * Hence caching the transcoder here.
> */
> enum transcoder cpu_transcoder;
> + /* Only used for DP MST stream encryption */
> + enum transcoder stream_transcoder;
> };
>
> struct intel_connector {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index c8fcec4d0788..16865b200062 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -568,7 +568,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
> if (conn_state->content_protection ==
> DRM_MODE_CONTENT_PROTECTION_DESIRED)
> intel_hdcp_enable(to_intel_connector(conn_state->connector),
> - pipe_config->cpu_transcoder,
> + pipe_config,
> (u8)conn_state->hdcp_content_type);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index b9d8825e2bb1..fc5de48456ad 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -2095,7 +2095,7 @@ int intel_hdcp_init(struct intel_connector *connector,
> }
>
> int intel_hdcp_enable(struct intel_connector *connector,
> - enum transcoder cpu_transcoder, u8 content_type)
> + const struct intel_crtc_state *pipe_config, u8 content_type)
> {
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> @@ -2111,10 +2111,17 @@ int intel_hdcp_enable(struct intel_connector *connector,
> drm_WARN_ON(&dev_priv->drm,
> hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED);
> hdcp->content_type = content_type;
> - hdcp->cpu_transcoder = cpu_transcoder;
> +
> + if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) {
> + hdcp->cpu_transcoder = pipe_config->mst_master_transcoder;
> + hdcp->stream_transcoder = pipe_config->cpu_transcoder;
> + } else {
> + hdcp->cpu_transcoder = pipe_config->cpu_transcoder;
> + hdcp->stream_transcoder = INVALID_TRANSCODER;
> + }
>
> if (INTEL_GEN(dev_priv) >= 12)
> - hdcp->port_data.fw_tc = intel_get_mei_fw_tc(cpu_transcoder);
> + hdcp->port_data.fw_tc = intel_get_mei_fw_tc(hdcp->cpu_transcoder);
>
> /*
> * Considering that HDCP2.2 is more secure than HDCP1.4, If the setup
> @@ -2234,7 +2241,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state,
>
> if (desired_and_not_enabled || content_protection_type_changed)
> intel_hdcp_enable(connector,
> - crtc_state->cpu_transcoder,
> + crtc_state,
> (u8)conn_state->hdcp_content_type);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h
> index 1bbf5b67ed0a..bc51c1e9b481 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.h
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
> @@ -25,7 +25,7 @@ void intel_hdcp_atomic_check(struct drm_connector *connector,
> int intel_hdcp_init(struct intel_connector *connector, enum port port,
> const struct intel_hdcp_shim *hdcp_shim);
> int intel_hdcp_enable(struct intel_connector *connector,
> - enum transcoder cpu_transcoder, u8 content_type);
> + const struct intel_crtc_state *pipe_config, u8 content_type);
> int intel_hdcp_disable(struct intel_connector *connector);
> void intel_hdcp_update_pipe(struct intel_atomic_state *state,
> struct intel_encoder *encoder,
> --
> 2.26.2
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 04/16] drm/i915/hdcp: DP MST transcoder for link and stream
@ 2020-11-05 13:52 ` Ramalingam C
0 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-05 13:52 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: jani.nikula, intel-gfx, dri-devel, seanpaul
On 2020-10-27 at 22:11:56 +0530, Anshuman Gupta wrote:
> Gen12 has H/W delta with respect to HDCP{1.x,2.x} display engine
> instances lies in Transcoder instead of DDI as in Gen11.
>
> This requires hdcp driver to use mst_master_transcoder for link
> authentication and stream transcoder for stream encryption
> separately.
>
> This will be used for both HDCP 1.4 and HDCP 2.2 over DP MST
> on Gen12.
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
> .../gpu/drm/i915/display/intel_display_types.h | 2 ++
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
> drivers/gpu/drm/i915/display/intel_hdcp.c | 15 +++++++++++----
> drivers/gpu/drm/i915/display/intel_hdcp.h | 2 +-
> 5 files changed, 16 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 63380b166c25..9fce623e951e 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4059,7 +4059,7 @@ static void intel_enable_ddi(struct intel_atomic_state *state,
> if (conn_state->content_protection ==
> DRM_MODE_CONTENT_PROTECTION_DESIRED)
> intel_hdcp_enable(to_intel_connector(conn_state->connector),
> - crtc_state->cpu_transcoder,
> + crtc_state,
> (u8)conn_state->hdcp_content_type);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index f6f0626649e0..c47124a679b6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -432,6 +432,8 @@ struct intel_hdcp {
> * Hence caching the transcoder here.
> */
> enum transcoder cpu_transcoder;
> + /* Only used for DP MST stream encryption */
> + enum transcoder stream_transcoder;
> };
>
> struct intel_connector {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index c8fcec4d0788..16865b200062 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -568,7 +568,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
> if (conn_state->content_protection ==
> DRM_MODE_CONTENT_PROTECTION_DESIRED)
> intel_hdcp_enable(to_intel_connector(conn_state->connector),
> - pipe_config->cpu_transcoder,
> + pipe_config,
> (u8)conn_state->hdcp_content_type);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index b9d8825e2bb1..fc5de48456ad 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -2095,7 +2095,7 @@ int intel_hdcp_init(struct intel_connector *connector,
> }
>
> int intel_hdcp_enable(struct intel_connector *connector,
> - enum transcoder cpu_transcoder, u8 content_type)
> + const struct intel_crtc_state *pipe_config, u8 content_type)
> {
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> @@ -2111,10 +2111,17 @@ int intel_hdcp_enable(struct intel_connector *connector,
> drm_WARN_ON(&dev_priv->drm,
> hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED);
> hdcp->content_type = content_type;
> - hdcp->cpu_transcoder = cpu_transcoder;
> +
> + if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) {
> + hdcp->cpu_transcoder = pipe_config->mst_master_transcoder;
> + hdcp->stream_transcoder = pipe_config->cpu_transcoder;
> + } else {
> + hdcp->cpu_transcoder = pipe_config->cpu_transcoder;
> + hdcp->stream_transcoder = INVALID_TRANSCODER;
> + }
>
> if (INTEL_GEN(dev_priv) >= 12)
> - hdcp->port_data.fw_tc = intel_get_mei_fw_tc(cpu_transcoder);
> + hdcp->port_data.fw_tc = intel_get_mei_fw_tc(hdcp->cpu_transcoder);
>
> /*
> * Considering that HDCP2.2 is more secure than HDCP1.4, If the setup
> @@ -2234,7 +2241,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state,
>
> if (desired_and_not_enabled || content_protection_type_changed)
> intel_hdcp_enable(connector,
> - crtc_state->cpu_transcoder,
> + crtc_state,
> (u8)conn_state->hdcp_content_type);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h
> index 1bbf5b67ed0a..bc51c1e9b481 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.h
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
> @@ -25,7 +25,7 @@ void intel_hdcp_atomic_check(struct drm_connector *connector,
> int intel_hdcp_init(struct intel_connector *connector, enum port port,
> const struct intel_hdcp_shim *hdcp_shim);
> int intel_hdcp_enable(struct intel_connector *connector,
> - enum transcoder cpu_transcoder, u8 content_type);
> + const struct intel_crtc_state *pipe_config, u8 content_type);
> int intel_hdcp_disable(struct intel_connector *connector);
> void intel_hdcp_update_pipe(struct intel_atomic_state *state,
> struct intel_encoder *encoder,
> --
> 2.26.2
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread
* [PATCH v4 05/16] drm/i915/hdcp: Move HDCP enc status timeout to header
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
@ 2020-10-27 16:41 ` Anshuman Gupta
-1 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:41 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: jani.nikula, uma.shankar, seanpaul, Anshuman Gupta, juston.li
DP MST stream encryption status requires time of a link frame
in order to change its status, but as there were some HDCP
encryption timeout observed earlier, it is safer to use
ENCRYPT_STATUS_CHANGE_TIMEOUT_MS timeout for stream status too,
it requires to move the macro to a header.
It will be used by both HDCP{1.x,2.x} stream status timeout.
Related: 'commit 7e90e8d0c0ea ("drm/i915: Increase timeout for Encrypt
status change")'
Cc: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 9 ++++-----
drivers/gpu/drm/i915/display/intel_hdcp.h | 2 ++
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index fc5de48456ad..0322a83c151d 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -23,7 +23,6 @@
#include "intel_connector.h"
#define KEY_LOAD_TRIES 5
-#define ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
#define HDCP2_LC_RETRY_CNT 3
static
@@ -762,7 +761,7 @@ static int intel_hdcp_auth(struct intel_connector *connector)
if (intel_de_wait_for_set(dev_priv,
HDCP_STATUS(dev_priv, cpu_transcoder, port),
HDCP_STATUS_ENC,
- ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
drm_err(&dev_priv->drm, "Timed out waiting for encryption\n");
return -ETIMEDOUT;
}
@@ -809,7 +808,7 @@ static int _intel_hdcp_disable(struct intel_connector *connector)
intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port), 0);
if (intel_de_wait_for_clear(dev_priv,
HDCP_STATUS(dev_priv, cpu_transcoder, port),
- ~0, ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ ~0, HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
drm_err(&dev_priv->drm,
"Failed to disable HDCP, timeout clearing status\n");
return -ETIMEDOUT;
@@ -1641,7 +1640,7 @@ static int hdcp2_enable_encryption(struct intel_connector *connector)
HDCP2_STATUS(dev_priv, cpu_transcoder,
port),
LINK_ENCRYPTION_STATUS,
- ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
return ret;
}
@@ -1665,7 +1664,7 @@ static int hdcp2_disable_encryption(struct intel_connector *connector)
HDCP2_STATUS(dev_priv, cpu_transcoder,
port),
LINK_ENCRYPTION_STATUS,
- ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
if (ret == -ETIMEDOUT)
drm_dbg_kms(&dev_priv->drm, "Disable Encryption Timedout");
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h
index bc51c1e9b481..b912a3a0f5b8 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.h
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
@@ -8,6 +8,8 @@
#include <linux/types.h>
+#define HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
+
struct drm_connector;
struct drm_connector_state;
struct drm_i915_private;
--
2.26.2
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 111+ messages in thread* [Intel-gfx] [PATCH v4 05/16] drm/i915/hdcp: Move HDCP enc status timeout to header
@ 2020-10-27 16:41 ` Anshuman Gupta
0 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:41 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula, seanpaul
DP MST stream encryption status requires time of a link frame
in order to change its status, but as there were some HDCP
encryption timeout observed earlier, it is safer to use
ENCRYPT_STATUS_CHANGE_TIMEOUT_MS timeout for stream status too,
it requires to move the macro to a header.
It will be used by both HDCP{1.x,2.x} stream status timeout.
Related: 'commit 7e90e8d0c0ea ("drm/i915: Increase timeout for Encrypt
status change")'
Cc: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 9 ++++-----
drivers/gpu/drm/i915/display/intel_hdcp.h | 2 ++
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index fc5de48456ad..0322a83c151d 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -23,7 +23,6 @@
#include "intel_connector.h"
#define KEY_LOAD_TRIES 5
-#define ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
#define HDCP2_LC_RETRY_CNT 3
static
@@ -762,7 +761,7 @@ static int intel_hdcp_auth(struct intel_connector *connector)
if (intel_de_wait_for_set(dev_priv,
HDCP_STATUS(dev_priv, cpu_transcoder, port),
HDCP_STATUS_ENC,
- ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
drm_err(&dev_priv->drm, "Timed out waiting for encryption\n");
return -ETIMEDOUT;
}
@@ -809,7 +808,7 @@ static int _intel_hdcp_disable(struct intel_connector *connector)
intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port), 0);
if (intel_de_wait_for_clear(dev_priv,
HDCP_STATUS(dev_priv, cpu_transcoder, port),
- ~0, ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ ~0, HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
drm_err(&dev_priv->drm,
"Failed to disable HDCP, timeout clearing status\n");
return -ETIMEDOUT;
@@ -1641,7 +1640,7 @@ static int hdcp2_enable_encryption(struct intel_connector *connector)
HDCP2_STATUS(dev_priv, cpu_transcoder,
port),
LINK_ENCRYPTION_STATUS,
- ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
return ret;
}
@@ -1665,7 +1664,7 @@ static int hdcp2_disable_encryption(struct intel_connector *connector)
HDCP2_STATUS(dev_priv, cpu_transcoder,
port),
LINK_ENCRYPTION_STATUS,
- ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
if (ret == -ETIMEDOUT)
drm_dbg_kms(&dev_priv->drm, "Disable Encryption Timedout");
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h
index bc51c1e9b481..b912a3a0f5b8 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.h
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
@@ -8,6 +8,8 @@
#include <linux/types.h>
+#define HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
+
struct drm_connector;
struct drm_connector_state;
struct drm_i915_private;
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 111+ messages in thread* Re: [PATCH v4 05/16] drm/i915/hdcp: Move HDCP enc status timeout to header
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
@ 2020-11-05 13:57 ` Ramalingam C
-1 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-05 13:57 UTC (permalink / raw)
To: Anshuman Gupta
Cc: jani.nikula, intel-gfx, dri-devel, uma.shankar, seanpaul, juston.li
On 2020-10-27 at 22:11:57 +0530, Anshuman Gupta wrote:
> DP MST stream encryption status requires time of a link frame
> in order to change its status, but as there were some HDCP
> encryption timeout observed earlier, it is safer to use
> ENCRYPT_STATUS_CHANGE_TIMEOUT_MS timeout for stream status too,
> it requires to move the macro to a header.
> It will be used by both HDCP{1.x,2.x} stream status timeout.
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
>
> Related: 'commit 7e90e8d0c0ea ("drm/i915: Increase timeout for Encrypt
> status change")'
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 9 ++++-----
> drivers/gpu/drm/i915/display/intel_hdcp.h | 2 ++
> 2 files changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index fc5de48456ad..0322a83c151d 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -23,7 +23,6 @@
> #include "intel_connector.h"
>
> #define KEY_LOAD_TRIES 5
> -#define ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
> #define HDCP2_LC_RETRY_CNT 3
>
> static
> @@ -762,7 +761,7 @@ static int intel_hdcp_auth(struct intel_connector *connector)
> if (intel_de_wait_for_set(dev_priv,
> HDCP_STATUS(dev_priv, cpu_transcoder, port),
> HDCP_STATUS_ENC,
> - ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> + HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> drm_err(&dev_priv->drm, "Timed out waiting for encryption\n");
> return -ETIMEDOUT;
> }
> @@ -809,7 +808,7 @@ static int _intel_hdcp_disable(struct intel_connector *connector)
> intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port), 0);
> if (intel_de_wait_for_clear(dev_priv,
> HDCP_STATUS(dev_priv, cpu_transcoder, port),
> - ~0, ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> + ~0, HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> drm_err(&dev_priv->drm,
> "Failed to disable HDCP, timeout clearing status\n");
> return -ETIMEDOUT;
> @@ -1641,7 +1640,7 @@ static int hdcp2_enable_encryption(struct intel_connector *connector)
> HDCP2_STATUS(dev_priv, cpu_transcoder,
> port),
> LINK_ENCRYPTION_STATUS,
> - ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
> + HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
>
> return ret;
> }
> @@ -1665,7 +1664,7 @@ static int hdcp2_disable_encryption(struct intel_connector *connector)
> HDCP2_STATUS(dev_priv, cpu_transcoder,
> port),
> LINK_ENCRYPTION_STATUS,
> - ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
> + HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
> if (ret == -ETIMEDOUT)
> drm_dbg_kms(&dev_priv->drm, "Disable Encryption Timedout");
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h
> index bc51c1e9b481..b912a3a0f5b8 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.h
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
> @@ -8,6 +8,8 @@
>
> #include <linux/types.h>
>
> +#define HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
> +
> struct drm_connector;
> struct drm_connector_state;
> struct drm_i915_private;
> --
> 2.26.2
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 05/16] drm/i915/hdcp: Move HDCP enc status timeout to header
@ 2020-11-05 13:57 ` Ramalingam C
0 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-05 13:57 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: jani.nikula, intel-gfx, dri-devel, seanpaul
On 2020-10-27 at 22:11:57 +0530, Anshuman Gupta wrote:
> DP MST stream encryption status requires time of a link frame
> in order to change its status, but as there were some HDCP
> encryption timeout observed earlier, it is safer to use
> ENCRYPT_STATUS_CHANGE_TIMEOUT_MS timeout for stream status too,
> it requires to move the macro to a header.
> It will be used by both HDCP{1.x,2.x} stream status timeout.
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
>
> Related: 'commit 7e90e8d0c0ea ("drm/i915: Increase timeout for Encrypt
> status change")'
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 9 ++++-----
> drivers/gpu/drm/i915/display/intel_hdcp.h | 2 ++
> 2 files changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index fc5de48456ad..0322a83c151d 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -23,7 +23,6 @@
> #include "intel_connector.h"
>
> #define KEY_LOAD_TRIES 5
> -#define ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
> #define HDCP2_LC_RETRY_CNT 3
>
> static
> @@ -762,7 +761,7 @@ static int intel_hdcp_auth(struct intel_connector *connector)
> if (intel_de_wait_for_set(dev_priv,
> HDCP_STATUS(dev_priv, cpu_transcoder, port),
> HDCP_STATUS_ENC,
> - ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> + HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> drm_err(&dev_priv->drm, "Timed out waiting for encryption\n");
> return -ETIMEDOUT;
> }
> @@ -809,7 +808,7 @@ static int _intel_hdcp_disable(struct intel_connector *connector)
> intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port), 0);
> if (intel_de_wait_for_clear(dev_priv,
> HDCP_STATUS(dev_priv, cpu_transcoder, port),
> - ~0, ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> + ~0, HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> drm_err(&dev_priv->drm,
> "Failed to disable HDCP, timeout clearing status\n");
> return -ETIMEDOUT;
> @@ -1641,7 +1640,7 @@ static int hdcp2_enable_encryption(struct intel_connector *connector)
> HDCP2_STATUS(dev_priv, cpu_transcoder,
> port),
> LINK_ENCRYPTION_STATUS,
> - ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
> + HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
>
> return ret;
> }
> @@ -1665,7 +1664,7 @@ static int hdcp2_disable_encryption(struct intel_connector *connector)
> HDCP2_STATUS(dev_priv, cpu_transcoder,
> port),
> LINK_ENCRYPTION_STATUS,
> - ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
> + HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
> if (ret == -ETIMEDOUT)
> drm_dbg_kms(&dev_priv->drm, "Disable Encryption Timedout");
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h
> index bc51c1e9b481..b912a3a0f5b8 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.h
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
> @@ -8,6 +8,8 @@
>
> #include <linux/types.h>
>
> +#define HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
> +
> struct drm_connector;
> struct drm_connector_state;
> struct drm_i915_private;
> --
> 2.26.2
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread
* [PATCH v4 06/16] drm/i915/hdcp: HDCP stream encryption support
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
@ 2020-10-27 16:41 ` Anshuman Gupta
-1 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:41 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: jani.nikula, uma.shankar, seanpaul, Anshuman Gupta, juston.li
Both HDCP_{1.x,2.x} requires to select/deselect Multistream HDCP bit
in TRANS_DDI_FUNC_CTL in order to enable/disable stream HDCP
encryption over DP MST Transport Link.
HDCP 1.4 stream encryption requires to validate the stream encryption
status in HDCP_STATUS_{TRANSCODER,PORT} register driving that link
in order to enable/disable the stream encryption.
Both of above requirement are same for all Gen with respect to
B.Spec Documentation.
v2:
Cosmetic changes function name, error msg print and
stream typo fixes. [Uma]
Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 10 +--
drivers/gpu/drm/i915/display/intel_ddi.h | 6 +-
.../drm/i915/display/intel_display_types.h | 4 +
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 80 ++++++++++++++++---
drivers/gpu/drm/i915/display/intel_hdmi.c | 14 ++--
drivers/gpu/drm/i915/i915_reg.h | 1 +
6 files changed, 90 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 9fce623e951e..779603a38cfc 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1948,9 +1948,9 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
}
}
-int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
- enum transcoder cpu_transcoder,
- bool enable)
+int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
+ enum transcoder cpu_transcoder,
+ bool enable, u32 hdcp_mask)
{
struct drm_device *dev = intel_encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -1965,9 +1965,9 @@ int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
if (enable)
- tmp |= TRANS_DDI_HDCP_SIGNALLING;
+ tmp |= hdcp_mask;
else
- tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
+ tmp &= ~hdcp_mask;
intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp);
intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
index dcc711cfe4fe..a4dd815c0000 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -50,9 +50,9 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
u32 ddi_signal_levels(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
-int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
- enum transcoder cpu_transcoder,
- bool enable);
+int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
+ enum transcoder cpu_transcoder,
+ bool enable, u32 hdcp_mask);
void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
#endif /* __INTEL_DDI_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index c47124a679b6..59b8fc21e3e8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -339,6 +339,10 @@ struct intel_hdcp_shim {
enum transcoder cpu_transcoder,
bool enable);
+ /* Enable/Disable stream encryption on DP MST Transport Link */
+ int (*stream_encryption)(struct intel_digital_port *dig_port,
+ bool enable);
+
/* Ensures the link is still protected */
bool (*check_link)(struct intel_digital_port *dig_port,
struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 03424d20e9f7..6dcbfaffd2c5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -16,6 +16,30 @@
#include "intel_dp.h"
#include "intel_hdcp.h"
+static unsigned int transcoder_to_stream_enc_status(enum transcoder cpu_transcoder)
+{
+ u32 stream_enc_mask;
+
+ switch (cpu_transcoder) {
+ case TRANSCODER_A:
+ stream_enc_mask = HDCP_STATUS_STREAM_A_ENC;
+ break;
+ case TRANSCODER_B:
+ stream_enc_mask = HDCP_STATUS_STREAM_B_ENC;
+ break;
+ case TRANSCODER_C:
+ stream_enc_mask = HDCP_STATUS_STREAM_C_ENC;
+ break;
+ case TRANSCODER_D:
+ stream_enc_mask = HDCP_STATUS_STREAM_D_ENC;
+ break;
+ default:
+ stream_enc_mask = 0;
+ }
+
+ return stream_enc_mask;
+}
+
static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
{
long ret;
@@ -622,24 +646,57 @@ static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
};
static int
-intel_dp_mst_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
- enum transcoder cpu_transcoder,
- bool enable)
+intel_dp_mst_toggle_hdcp_stream_select(struct intel_digital_port *dig_port,
+ bool enable)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_dp *dp = &dig_port->dp;
+ struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
int ret;
- if (!enable)
- usleep_range(6, 60); /* Bspec says >= 6us */
-
- ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base,
- cpu_transcoder, enable);
+ ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
+ hdcp->stream_transcoder, enable,
+ TRANS_DDI_HDCP_SELECT);
if (ret)
- drm_dbg_kms(&i915->drm, "%s HDCP signalling failed (%d)\n",
- enable ? "Enable" : "Disable", ret);
+ drm_err(&i915->drm, "%s HDCP stream select failed (%d)\n",
+ enable ? "Enable" : "Disable", ret);
return ret;
}
+static int
+intel_dp_mst_hdcp_stream_encryption(struct intel_digital_port *dig_port,
+ bool enable)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_dp *dp = &dig_port->dp;
+ struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
+ enum port port = dig_port->base.port;
+ enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
+ u32 stream_enc_status;
+ int ret;
+
+ ret = intel_dp_mst_toggle_hdcp_stream_select(dig_port, enable);
+ if (ret)
+ return ret;
+
+ stream_enc_status = transcoder_to_stream_enc_status(hdcp->stream_transcoder);
+ if (!stream_enc_status)
+ return -EINVAL;
+
+ /* Wait for encryption confirmation */
+ if (intel_de_wait_for_register(i915,
+ HDCP_STATUS(i915, cpu_transcoder, port),
+ stream_enc_status,
+ enable ? stream_enc_status : 0,
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ drm_err(&i915->drm, "Timed out waiting for stream encryption %s\n",
+ enable ? "enabled" : "disabled");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
static
bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
struct intel_connector *connector)
@@ -673,7 +730,8 @@ static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
.read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
.read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
.read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
- .toggle_signalling = intel_dp_mst_hdcp_toggle_signalling,
+ .toggle_signalling = intel_dp_hdcp_toggle_signalling,
+ .stream_encryption = intel_dp_mst_hdcp_stream_encryption,
.check_link = intel_dp_mst_hdcp_check_link,
.hdcp_capable = intel_dp_hdcp_capable,
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index f90838bc74fb..f58469226694 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1495,15 +1495,16 @@ static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
usleep_range(25, 50);
}
- ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
- false);
+ ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
+ false, TRANS_DDI_HDCP_SIGNALLING);
if (ret) {
drm_err(&dev_priv->drm,
"Disable HDCP signalling failed (%d)\n", ret);
return ret;
}
- ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
- true);
+
+ ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
+ true, TRANS_DDI_HDCP_SIGNALLING);
if (ret) {
drm_err(&dev_priv->drm,
"Enable HDCP signalling failed (%d)\n", ret);
@@ -1526,8 +1527,9 @@ int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
if (!enable)
usleep_range(6, 60); /* Bspec says >= 6us */
- ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
- enable);
+ ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
+ cpu_transcoder, enable,
+ TRANS_DDI_HDCP_SIGNALLING);
if (ret) {
drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n",
enable ? "Enable" : "Disable", ret);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8b021f77cb1f..77461cde6549 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9982,6 +9982,7 @@ enum skl_power_gate {
#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
#define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
+#define TRANS_DDI_HDCP_SELECT REG_BIT(5)
#define TRANS_DDI_BFI_ENABLE (1 << 4)
#define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
#define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
--
2.26.2
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 111+ messages in thread* [Intel-gfx] [PATCH v4 06/16] drm/i915/hdcp: HDCP stream encryption support
@ 2020-10-27 16:41 ` Anshuman Gupta
0 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:41 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula, seanpaul
Both HDCP_{1.x,2.x} requires to select/deselect Multistream HDCP bit
in TRANS_DDI_FUNC_CTL in order to enable/disable stream HDCP
encryption over DP MST Transport Link.
HDCP 1.4 stream encryption requires to validate the stream encryption
status in HDCP_STATUS_{TRANSCODER,PORT} register driving that link
in order to enable/disable the stream encryption.
Both of above requirement are same for all Gen with respect to
B.Spec Documentation.
v2:
Cosmetic changes function name, error msg print and
stream typo fixes. [Uma]
Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 10 +--
drivers/gpu/drm/i915/display/intel_ddi.h | 6 +-
.../drm/i915/display/intel_display_types.h | 4 +
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 80 ++++++++++++++++---
drivers/gpu/drm/i915/display/intel_hdmi.c | 14 ++--
drivers/gpu/drm/i915/i915_reg.h | 1 +
6 files changed, 90 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 9fce623e951e..779603a38cfc 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1948,9 +1948,9 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
}
}
-int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
- enum transcoder cpu_transcoder,
- bool enable)
+int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
+ enum transcoder cpu_transcoder,
+ bool enable, u32 hdcp_mask)
{
struct drm_device *dev = intel_encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -1965,9 +1965,9 @@ int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
if (enable)
- tmp |= TRANS_DDI_HDCP_SIGNALLING;
+ tmp |= hdcp_mask;
else
- tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
+ tmp &= ~hdcp_mask;
intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp);
intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
index dcc711cfe4fe..a4dd815c0000 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -50,9 +50,9 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
u32 ddi_signal_levels(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
-int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
- enum transcoder cpu_transcoder,
- bool enable);
+int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
+ enum transcoder cpu_transcoder,
+ bool enable, u32 hdcp_mask);
void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
#endif /* __INTEL_DDI_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index c47124a679b6..59b8fc21e3e8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -339,6 +339,10 @@ struct intel_hdcp_shim {
enum transcoder cpu_transcoder,
bool enable);
+ /* Enable/Disable stream encryption on DP MST Transport Link */
+ int (*stream_encryption)(struct intel_digital_port *dig_port,
+ bool enable);
+
/* Ensures the link is still protected */
bool (*check_link)(struct intel_digital_port *dig_port,
struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 03424d20e9f7..6dcbfaffd2c5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -16,6 +16,30 @@
#include "intel_dp.h"
#include "intel_hdcp.h"
+static unsigned int transcoder_to_stream_enc_status(enum transcoder cpu_transcoder)
+{
+ u32 stream_enc_mask;
+
+ switch (cpu_transcoder) {
+ case TRANSCODER_A:
+ stream_enc_mask = HDCP_STATUS_STREAM_A_ENC;
+ break;
+ case TRANSCODER_B:
+ stream_enc_mask = HDCP_STATUS_STREAM_B_ENC;
+ break;
+ case TRANSCODER_C:
+ stream_enc_mask = HDCP_STATUS_STREAM_C_ENC;
+ break;
+ case TRANSCODER_D:
+ stream_enc_mask = HDCP_STATUS_STREAM_D_ENC;
+ break;
+ default:
+ stream_enc_mask = 0;
+ }
+
+ return stream_enc_mask;
+}
+
static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
{
long ret;
@@ -622,24 +646,57 @@ static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
};
static int
-intel_dp_mst_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
- enum transcoder cpu_transcoder,
- bool enable)
+intel_dp_mst_toggle_hdcp_stream_select(struct intel_digital_port *dig_port,
+ bool enable)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_dp *dp = &dig_port->dp;
+ struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
int ret;
- if (!enable)
- usleep_range(6, 60); /* Bspec says >= 6us */
-
- ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base,
- cpu_transcoder, enable);
+ ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
+ hdcp->stream_transcoder, enable,
+ TRANS_DDI_HDCP_SELECT);
if (ret)
- drm_dbg_kms(&i915->drm, "%s HDCP signalling failed (%d)\n",
- enable ? "Enable" : "Disable", ret);
+ drm_err(&i915->drm, "%s HDCP stream select failed (%d)\n",
+ enable ? "Enable" : "Disable", ret);
return ret;
}
+static int
+intel_dp_mst_hdcp_stream_encryption(struct intel_digital_port *dig_port,
+ bool enable)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_dp *dp = &dig_port->dp;
+ struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
+ enum port port = dig_port->base.port;
+ enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
+ u32 stream_enc_status;
+ int ret;
+
+ ret = intel_dp_mst_toggle_hdcp_stream_select(dig_port, enable);
+ if (ret)
+ return ret;
+
+ stream_enc_status = transcoder_to_stream_enc_status(hdcp->stream_transcoder);
+ if (!stream_enc_status)
+ return -EINVAL;
+
+ /* Wait for encryption confirmation */
+ if (intel_de_wait_for_register(i915,
+ HDCP_STATUS(i915, cpu_transcoder, port),
+ stream_enc_status,
+ enable ? stream_enc_status : 0,
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ drm_err(&i915->drm, "Timed out waiting for stream encryption %s\n",
+ enable ? "enabled" : "disabled");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
static
bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
struct intel_connector *connector)
@@ -673,7 +730,8 @@ static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
.read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
.read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
.read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
- .toggle_signalling = intel_dp_mst_hdcp_toggle_signalling,
+ .toggle_signalling = intel_dp_hdcp_toggle_signalling,
+ .stream_encryption = intel_dp_mst_hdcp_stream_encryption,
.check_link = intel_dp_mst_hdcp_check_link,
.hdcp_capable = intel_dp_hdcp_capable,
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index f90838bc74fb..f58469226694 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1495,15 +1495,16 @@ static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
usleep_range(25, 50);
}
- ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
- false);
+ ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
+ false, TRANS_DDI_HDCP_SIGNALLING);
if (ret) {
drm_err(&dev_priv->drm,
"Disable HDCP signalling failed (%d)\n", ret);
return ret;
}
- ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
- true);
+
+ ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
+ true, TRANS_DDI_HDCP_SIGNALLING);
if (ret) {
drm_err(&dev_priv->drm,
"Enable HDCP signalling failed (%d)\n", ret);
@@ -1526,8 +1527,9 @@ int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
if (!enable)
usleep_range(6, 60); /* Bspec says >= 6us */
- ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
- enable);
+ ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
+ cpu_transcoder, enable,
+ TRANS_DDI_HDCP_SIGNALLING);
if (ret) {
drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n",
enable ? "Enable" : "Disable", ret);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8b021f77cb1f..77461cde6549 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9982,6 +9982,7 @@ enum skl_power_gate {
#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
#define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
+#define TRANS_DDI_HDCP_SELECT REG_BIT(5)
#define TRANS_DDI_BFI_ENABLE (1 << 4)
#define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
#define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 111+ messages in thread* RE: [PATCH v4 06/16] drm/i915/hdcp: HDCP stream encryption support
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
@ 2020-11-02 7:47 ` Shankar, Uma
-1 siblings, 0 replies; 111+ messages in thread
From: Shankar, Uma @ 2020-11-02 7:47 UTC (permalink / raw)
To: Gupta, Anshuman, intel-gfx, dri-devel
Cc: Nikula, Jani, seanpaul, Li, Juston, Gupta, Anshuman
> -----Original Message-----
> From: Anshuman Gupta <anshuman.gupta@intel.com>
> Sent: Tuesday, October 27, 2020 10:12 PM
> To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: seanpaul@chromium.org; Nikula, Jani <jani.nikula@intel.com>; C,
> Ramalingam <ramalingam.c@intel.com>; Li, Juston <juston.li@intel.com>;
> Shankar, Uma <uma.shankar@intel.com>; Gupta, Anshuman
> <anshuman.gupta@intel.com>
> Subject: [PATCH v4 06/16] drm/i915/hdcp: HDCP stream encryption support
>
> Both HDCP_{1.x,2.x} requires to select/deselect Multistream HDCP bit in
> TRANS_DDI_FUNC_CTL in order to enable/disable stream HDCP encryption over
> DP MST Transport Link.
>
> HDCP 1.4 stream encryption requires to validate the stream encryption status in
> HDCP_STATUS_{TRANSCODER,PORT} register driving that link in order to
> enable/disable the stream encryption.
>
> Both of above requirement are same for all Gen with respect to B.Spec
> Documentation.
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> v2:
> Cosmetic changes function name, error msg print and stream typo fixes. [Uma]
>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 10 +--
> drivers/gpu/drm/i915/display/intel_ddi.h | 6 +-
> .../drm/i915/display/intel_display_types.h | 4 +
> drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 80 ++++++++++++++++---
> drivers/gpu/drm/i915/display/intel_hdmi.c | 14 ++--
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 6 files changed, 90 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 9fce623e951e..779603a38cfc 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1948,9 +1948,9 @@ void intel_ddi_disable_transcoder_func(const struct
> intel_crtc_state *crtc_state
> }
> }
>
> -int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
> - enum transcoder cpu_transcoder,
> - bool enable)
> +int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
> + enum transcoder cpu_transcoder,
> + bool enable, u32 hdcp_mask)
> {
> struct drm_device *dev = intel_encoder->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev); @@ -1965,9 +1965,9
> @@ int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
>
> tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
> if (enable)
> - tmp |= TRANS_DDI_HDCP_SIGNALLING;
> + tmp |= hdcp_mask;
> else
> - tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
> + tmp &= ~hdcp_mask;
> intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp);
> intel_display_power_put(dev_priv, intel_encoder->power_domain,
> wakeref);
> return ret;
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h
> b/drivers/gpu/drm/i915/display/intel_ddi.h
> index dcc711cfe4fe..a4dd815c0000 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.h
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.h
> @@ -50,9 +50,9 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state);
> u32 ddi_signal_levels(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state); -int
> intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
> - enum transcoder cpu_transcoder,
> - bool enable);
> +int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
> + enum transcoder cpu_transcoder,
> + bool enable, u32 hdcp_mask);
> void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
>
> #endif /* __INTEL_DDI_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index c47124a679b6..59b8fc21e3e8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -339,6 +339,10 @@ struct intel_hdcp_shim {
> enum transcoder cpu_transcoder,
> bool enable);
>
> + /* Enable/Disable stream encryption on DP MST Transport Link */
> + int (*stream_encryption)(struct intel_digital_port *dig_port,
> + bool enable);
> +
> /* Ensures the link is still protected */
> bool (*check_link)(struct intel_digital_port *dig_port,
> struct intel_connector *connector); diff --git
> a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> index 03424d20e9f7..6dcbfaffd2c5 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> @@ -16,6 +16,30 @@
> #include "intel_dp.h"
> #include "intel_hdcp.h"
>
> +static unsigned int transcoder_to_stream_enc_status(enum transcoder
> +cpu_transcoder) {
> + u32 stream_enc_mask;
> +
> + switch (cpu_transcoder) {
> + case TRANSCODER_A:
> + stream_enc_mask = HDCP_STATUS_STREAM_A_ENC;
> + break;
> + case TRANSCODER_B:
> + stream_enc_mask = HDCP_STATUS_STREAM_B_ENC;
> + break;
> + case TRANSCODER_C:
> + stream_enc_mask = HDCP_STATUS_STREAM_C_ENC;
> + break;
> + case TRANSCODER_D:
> + stream_enc_mask = HDCP_STATUS_STREAM_D_ENC;
> + break;
> + default:
> + stream_enc_mask = 0;
> + }
> +
> + return stream_enc_mask;
> +}
> +
> static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
> {
> long ret;
> @@ -622,24 +646,57 @@ static const struct intel_hdcp_shim
> intel_dp_hdcp_shim = { };
>
> static int
> -intel_dp_mst_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
> - enum transcoder cpu_transcoder,
> - bool enable)
> +intel_dp_mst_toggle_hdcp_stream_select(struct intel_digital_port *dig_port,
> + bool enable)
> {
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + struct intel_dp *dp = &dig_port->dp;
> + struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
> int ret;
>
> - if (!enable)
> - usleep_range(6, 60); /* Bspec says >= 6us */
> -
> - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base,
> - cpu_transcoder, enable);
> + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
> + hdcp->stream_transcoder, enable,
> + TRANS_DDI_HDCP_SELECT);
> if (ret)
> - drm_dbg_kms(&i915->drm, "%s HDCP signalling failed (%d)\n",
> - enable ? "Enable" : "Disable", ret);
> + drm_err(&i915->drm, "%s HDCP stream select failed (%d)\n",
> + enable ? "Enable" : "Disable", ret);
> return ret;
> }
>
> +static int
> +intel_dp_mst_hdcp_stream_encryption(struct intel_digital_port *dig_port,
> + bool enable)
> +{
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + struct intel_dp *dp = &dig_port->dp;
> + struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
> + enum port port = dig_port->base.port;
> + enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
> + u32 stream_enc_status;
> + int ret;
> +
> + ret = intel_dp_mst_toggle_hdcp_stream_select(dig_port, enable);
> + if (ret)
> + return ret;
> +
> + stream_enc_status = transcoder_to_stream_enc_status(hdcp-
> >stream_transcoder);
> + if (!stream_enc_status)
> + return -EINVAL;
> +
> + /* Wait for encryption confirmation */
> + if (intel_de_wait_for_register(i915,
> + HDCP_STATUS(i915, cpu_transcoder, port),
> + stream_enc_status,
> + enable ? stream_enc_status : 0,
> +
> HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> + drm_err(&i915->drm, "Timed out waiting for stream encryption
> %s\n",
> + enable ? "enabled" : "disabled");
> + return -ETIMEDOUT;
> + }
> +
> + return 0;
> +}
> +
> static
> bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
> struct intel_connector *connector) @@ -673,7
> +730,8 @@ static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
> .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
> .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
> .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
> - .toggle_signalling = intel_dp_mst_hdcp_toggle_signalling,
> + .toggle_signalling = intel_dp_hdcp_toggle_signalling,
> + .stream_encryption = intel_dp_mst_hdcp_stream_encryption,
> .check_link = intel_dp_mst_hdcp_check_link,
> .hdcp_capable = intel_dp_hdcp_capable,
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index f90838bc74fb..f58469226694 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -1495,15 +1495,16 @@ static int kbl_repositioning_enc_en_signal(struct
> intel_connector *connector,
> usleep_range(25, 50);
> }
>
> - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
> - false);
> + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
> + false, TRANS_DDI_HDCP_SIGNALLING);
> if (ret) {
> drm_err(&dev_priv->drm,
> "Disable HDCP signalling failed (%d)\n", ret);
> return ret;
> }
> - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
> - true);
> +
> + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
> + true, TRANS_DDI_HDCP_SIGNALLING);
> if (ret) {
> drm_err(&dev_priv->drm,
> "Enable HDCP signalling failed (%d)\n", ret); @@ -1526,8
> +1527,9 @@ int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port
> *dig_port,
> if (!enable)
> usleep_range(6, 60); /* Bspec says >= 6us */
>
> - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
> - enable);
> + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
> + cpu_transcoder, enable,
> + TRANS_DDI_HDCP_SIGNALLING);
> if (ret) {
> drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n",
> enable ? "Enable" : "Disable", ret); diff --git
> a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index
> 8b021f77cb1f..77461cde6549 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9982,6 +9982,7 @@ enum skl_power_gate {
> #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
> #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7) #define
> TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
> +#define TRANS_DDI_HDCP_SELECT REG_BIT(5)
> #define TRANS_DDI_BFI_ENABLE (1 << 4)
> #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
> #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
> --
> 2.26.2
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 06/16] drm/i915/hdcp: HDCP stream encryption support
@ 2020-11-02 7:47 ` Shankar, Uma
0 siblings, 0 replies; 111+ messages in thread
From: Shankar, Uma @ 2020-11-02 7:47 UTC (permalink / raw)
To: Gupta, Anshuman, intel-gfx, dri-devel; +Cc: Nikula, Jani, seanpaul
> -----Original Message-----
> From: Anshuman Gupta <anshuman.gupta@intel.com>
> Sent: Tuesday, October 27, 2020 10:12 PM
> To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: seanpaul@chromium.org; Nikula, Jani <jani.nikula@intel.com>; C,
> Ramalingam <ramalingam.c@intel.com>; Li, Juston <juston.li@intel.com>;
> Shankar, Uma <uma.shankar@intel.com>; Gupta, Anshuman
> <anshuman.gupta@intel.com>
> Subject: [PATCH v4 06/16] drm/i915/hdcp: HDCP stream encryption support
>
> Both HDCP_{1.x,2.x} requires to select/deselect Multistream HDCP bit in
> TRANS_DDI_FUNC_CTL in order to enable/disable stream HDCP encryption over
> DP MST Transport Link.
>
> HDCP 1.4 stream encryption requires to validate the stream encryption status in
> HDCP_STATUS_{TRANSCODER,PORT} register driving that link in order to
> enable/disable the stream encryption.
>
> Both of above requirement are same for all Gen with respect to B.Spec
> Documentation.
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> v2:
> Cosmetic changes function name, error msg print and stream typo fixes. [Uma]
>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 10 +--
> drivers/gpu/drm/i915/display/intel_ddi.h | 6 +-
> .../drm/i915/display/intel_display_types.h | 4 +
> drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 80 ++++++++++++++++---
> drivers/gpu/drm/i915/display/intel_hdmi.c | 14 ++--
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 6 files changed, 90 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 9fce623e951e..779603a38cfc 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1948,9 +1948,9 @@ void intel_ddi_disable_transcoder_func(const struct
> intel_crtc_state *crtc_state
> }
> }
>
> -int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
> - enum transcoder cpu_transcoder,
> - bool enable)
> +int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
> + enum transcoder cpu_transcoder,
> + bool enable, u32 hdcp_mask)
> {
> struct drm_device *dev = intel_encoder->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev); @@ -1965,9 +1965,9
> @@ int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
>
> tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
> if (enable)
> - tmp |= TRANS_DDI_HDCP_SIGNALLING;
> + tmp |= hdcp_mask;
> else
> - tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
> + tmp &= ~hdcp_mask;
> intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp);
> intel_display_power_put(dev_priv, intel_encoder->power_domain,
> wakeref);
> return ret;
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h
> b/drivers/gpu/drm/i915/display/intel_ddi.h
> index dcc711cfe4fe..a4dd815c0000 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.h
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.h
> @@ -50,9 +50,9 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state);
> u32 ddi_signal_levels(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state); -int
> intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
> - enum transcoder cpu_transcoder,
> - bool enable);
> +int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
> + enum transcoder cpu_transcoder,
> + bool enable, u32 hdcp_mask);
> void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
>
> #endif /* __INTEL_DDI_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index c47124a679b6..59b8fc21e3e8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -339,6 +339,10 @@ struct intel_hdcp_shim {
> enum transcoder cpu_transcoder,
> bool enable);
>
> + /* Enable/Disable stream encryption on DP MST Transport Link */
> + int (*stream_encryption)(struct intel_digital_port *dig_port,
> + bool enable);
> +
> /* Ensures the link is still protected */
> bool (*check_link)(struct intel_digital_port *dig_port,
> struct intel_connector *connector); diff --git
> a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> index 03424d20e9f7..6dcbfaffd2c5 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> @@ -16,6 +16,30 @@
> #include "intel_dp.h"
> #include "intel_hdcp.h"
>
> +static unsigned int transcoder_to_stream_enc_status(enum transcoder
> +cpu_transcoder) {
> + u32 stream_enc_mask;
> +
> + switch (cpu_transcoder) {
> + case TRANSCODER_A:
> + stream_enc_mask = HDCP_STATUS_STREAM_A_ENC;
> + break;
> + case TRANSCODER_B:
> + stream_enc_mask = HDCP_STATUS_STREAM_B_ENC;
> + break;
> + case TRANSCODER_C:
> + stream_enc_mask = HDCP_STATUS_STREAM_C_ENC;
> + break;
> + case TRANSCODER_D:
> + stream_enc_mask = HDCP_STATUS_STREAM_D_ENC;
> + break;
> + default:
> + stream_enc_mask = 0;
> + }
> +
> + return stream_enc_mask;
> +}
> +
> static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
> {
> long ret;
> @@ -622,24 +646,57 @@ static const struct intel_hdcp_shim
> intel_dp_hdcp_shim = { };
>
> static int
> -intel_dp_mst_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
> - enum transcoder cpu_transcoder,
> - bool enable)
> +intel_dp_mst_toggle_hdcp_stream_select(struct intel_digital_port *dig_port,
> + bool enable)
> {
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + struct intel_dp *dp = &dig_port->dp;
> + struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
> int ret;
>
> - if (!enable)
> - usleep_range(6, 60); /* Bspec says >= 6us */
> -
> - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base,
> - cpu_transcoder, enable);
> + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
> + hdcp->stream_transcoder, enable,
> + TRANS_DDI_HDCP_SELECT);
> if (ret)
> - drm_dbg_kms(&i915->drm, "%s HDCP signalling failed (%d)\n",
> - enable ? "Enable" : "Disable", ret);
> + drm_err(&i915->drm, "%s HDCP stream select failed (%d)\n",
> + enable ? "Enable" : "Disable", ret);
> return ret;
> }
>
> +static int
> +intel_dp_mst_hdcp_stream_encryption(struct intel_digital_port *dig_port,
> + bool enable)
> +{
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + struct intel_dp *dp = &dig_port->dp;
> + struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
> + enum port port = dig_port->base.port;
> + enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
> + u32 stream_enc_status;
> + int ret;
> +
> + ret = intel_dp_mst_toggle_hdcp_stream_select(dig_port, enable);
> + if (ret)
> + return ret;
> +
> + stream_enc_status = transcoder_to_stream_enc_status(hdcp-
> >stream_transcoder);
> + if (!stream_enc_status)
> + return -EINVAL;
> +
> + /* Wait for encryption confirmation */
> + if (intel_de_wait_for_register(i915,
> + HDCP_STATUS(i915, cpu_transcoder, port),
> + stream_enc_status,
> + enable ? stream_enc_status : 0,
> +
> HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> + drm_err(&i915->drm, "Timed out waiting for stream encryption
> %s\n",
> + enable ? "enabled" : "disabled");
> + return -ETIMEDOUT;
> + }
> +
> + return 0;
> +}
> +
> static
> bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
> struct intel_connector *connector) @@ -673,7
> +730,8 @@ static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
> .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
> .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
> .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
> - .toggle_signalling = intel_dp_mst_hdcp_toggle_signalling,
> + .toggle_signalling = intel_dp_hdcp_toggle_signalling,
> + .stream_encryption = intel_dp_mst_hdcp_stream_encryption,
> .check_link = intel_dp_mst_hdcp_check_link,
> .hdcp_capable = intel_dp_hdcp_capable,
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index f90838bc74fb..f58469226694 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -1495,15 +1495,16 @@ static int kbl_repositioning_enc_en_signal(struct
> intel_connector *connector,
> usleep_range(25, 50);
> }
>
> - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
> - false);
> + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
> + false, TRANS_DDI_HDCP_SIGNALLING);
> if (ret) {
> drm_err(&dev_priv->drm,
> "Disable HDCP signalling failed (%d)\n", ret);
> return ret;
> }
> - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
> - true);
> +
> + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
> + true, TRANS_DDI_HDCP_SIGNALLING);
> if (ret) {
> drm_err(&dev_priv->drm,
> "Enable HDCP signalling failed (%d)\n", ret); @@ -1526,8
> +1527,9 @@ int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port
> *dig_port,
> if (!enable)
> usleep_range(6, 60); /* Bspec says >= 6us */
>
> - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
> - enable);
> + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
> + cpu_transcoder, enable,
> + TRANS_DDI_HDCP_SIGNALLING);
> if (ret) {
> drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n",
> enable ? "Enable" : "Disable", ret); diff --git
> a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index
> 8b021f77cb1f..77461cde6549 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9982,6 +9982,7 @@ enum skl_power_gate {
> #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
> #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7) #define
> TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
> +#define TRANS_DDI_HDCP_SELECT REG_BIT(5)
> #define TRANS_DDI_BFI_ENABLE (1 << 4)
> #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
> #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
> --
> 2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v4 06/16] drm/i915/hdcp: HDCP stream encryption support
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
@ 2020-11-05 15:34 ` Ramalingam C
-1 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-05 15:34 UTC (permalink / raw)
To: Anshuman Gupta
Cc: jani.nikula, intel-gfx, dri-devel, uma.shankar, seanpaul, juston.li
On 2020-10-27 at 22:11:58 +0530, Anshuman Gupta wrote:
> Both HDCP_{1.x,2.x} requires to select/deselect Multistream HDCP bit
> in TRANS_DDI_FUNC_CTL in order to enable/disable stream HDCP
> encryption over DP MST Transport Link.
>
> HDCP 1.4 stream encryption requires to validate the stream encryption
> status in HDCP_STATUS_{TRANSCODER,PORT} register driving that link
> in order to enable/disable the stream encryption.
>
> Both of above requirement are same for all Gen with respect to
> B.Spec Documentation.
>
> v2:
> Cosmetic changes function name, error msg print and
> stream typo fixes. [Uma]
>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 10 +--
> drivers/gpu/drm/i915/display/intel_ddi.h | 6 +-
> .../drm/i915/display/intel_display_types.h | 4 +
> drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 80 ++++++++++++++++---
> drivers/gpu/drm/i915/display/intel_hdmi.c | 14 ++--
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 6 files changed, 90 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 9fce623e951e..779603a38cfc 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1948,9 +1948,9 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
> }
> }
>
> -int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
> - enum transcoder cpu_transcoder,
> - bool enable)
> +int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
> + enum transcoder cpu_transcoder,
> + bool enable, u32 hdcp_mask)
> {
> struct drm_device *dev = intel_encoder->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -1965,9 +1965,9 @@ int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
>
> tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
> if (enable)
> - tmp |= TRANS_DDI_HDCP_SIGNALLING;
> + tmp |= hdcp_mask;
> else
> - tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
> + tmp &= ~hdcp_mask;
> intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp);
> intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
> return ret;
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
> index dcc711cfe4fe..a4dd815c0000 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.h
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.h
> @@ -50,9 +50,9 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state);
> u32 ddi_signal_levels(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state);
> -int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
> - enum transcoder cpu_transcoder,
> - bool enable);
> +int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
> + enum transcoder cpu_transcoder,
> + bool enable, u32 hdcp_mask);
> void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
>
> #endif /* __INTEL_DDI_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index c47124a679b6..59b8fc21e3e8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -339,6 +339,10 @@ struct intel_hdcp_shim {
> enum transcoder cpu_transcoder,
> bool enable);
>
> + /* Enable/Disable stream encryption on DP MST Transport Link */
> + int (*stream_encryption)(struct intel_digital_port *dig_port,
> + bool enable);
> +
> /* Ensures the link is still protected */
> bool (*check_link)(struct intel_digital_port *dig_port,
> struct intel_connector *connector);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> index 03424d20e9f7..6dcbfaffd2c5 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> @@ -16,6 +16,30 @@
> #include "intel_dp.h"
> #include "intel_hdcp.h"
>
> +static unsigned int transcoder_to_stream_enc_status(enum transcoder cpu_transcoder)
> +{
> + u32 stream_enc_mask;
> +
> + switch (cpu_transcoder) {
> + case TRANSCODER_A:
> + stream_enc_mask = HDCP_STATUS_STREAM_A_ENC;
> + break;
> + case TRANSCODER_B:
> + stream_enc_mask = HDCP_STATUS_STREAM_B_ENC;
> + break;
> + case TRANSCODER_C:
> + stream_enc_mask = HDCP_STATUS_STREAM_C_ENC;
> + break;
> + case TRANSCODER_D:
> + stream_enc_mask = HDCP_STATUS_STREAM_D_ENC;
> + break;
> + default:
> + stream_enc_mask = 0;
> + }
> +
> + return stream_enc_mask;
> +}
> +
> static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
> {
> long ret;
> @@ -622,24 +646,57 @@ static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
> };
>
> static int
> -intel_dp_mst_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
> - enum transcoder cpu_transcoder,
> - bool enable)
> +intel_dp_mst_toggle_hdcp_stream_select(struct intel_digital_port *dig_port,
> + bool enable)
> {
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + struct intel_dp *dp = &dig_port->dp;
> + struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
> int ret;
>
> - if (!enable)
> - usleep_range(6, 60); /* Bspec says >= 6us */
Any reason why this is removed from disable path? Or i am missing the
movement?
-Ram
> -
> - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base,
> - cpu_transcoder, enable);
> + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
> + hdcp->stream_transcoder, enable,
> + TRANS_DDI_HDCP_SELECT);
> if (ret)
> - drm_dbg_kms(&i915->drm, "%s HDCP signalling failed (%d)\n",
> - enable ? "Enable" : "Disable", ret);
> + drm_err(&i915->drm, "%s HDCP stream select failed (%d)\n",
> + enable ? "Enable" : "Disable", ret);
> return ret;
> }
>
> +static int
> +intel_dp_mst_hdcp_stream_encryption(struct intel_digital_port *dig_port,
> + bool enable)
> +{
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + struct intel_dp *dp = &dig_port->dp;
> + struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
> + enum port port = dig_port->base.port;
> + enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
> + u32 stream_enc_status;
> + int ret;
> +
> + ret = intel_dp_mst_toggle_hdcp_stream_select(dig_port, enable);
> + if (ret)
> + return ret;
> +
> + stream_enc_status = transcoder_to_stream_enc_status(hdcp->stream_transcoder);
> + if (!stream_enc_status)
> + return -EINVAL;
> +
> + /* Wait for encryption confirmation */
> + if (intel_de_wait_for_register(i915,
> + HDCP_STATUS(i915, cpu_transcoder, port),
> + stream_enc_status,
> + enable ? stream_enc_status : 0,
> + HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> + drm_err(&i915->drm, "Timed out waiting for stream encryption %s\n",
> + enable ? "enabled" : "disabled");
> + return -ETIMEDOUT;
> + }
> +
> + return 0;
> +}
> +
> static
> bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
> struct intel_connector *connector)
> @@ -673,7 +730,8 @@ static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
> .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
> .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
> .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
> - .toggle_signalling = intel_dp_mst_hdcp_toggle_signalling,
> + .toggle_signalling = intel_dp_hdcp_toggle_signalling,
> + .stream_encryption = intel_dp_mst_hdcp_stream_encryption,
> .check_link = intel_dp_mst_hdcp_check_link,
> .hdcp_capable = intel_dp_hdcp_capable,
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index f90838bc74fb..f58469226694 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -1495,15 +1495,16 @@ static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
> usleep_range(25, 50);
> }
>
> - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
> - false);
> + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
> + false, TRANS_DDI_HDCP_SIGNALLING);
> if (ret) {
> drm_err(&dev_priv->drm,
> "Disable HDCP signalling failed (%d)\n", ret);
> return ret;
> }
> - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
> - true);
> +
> + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
> + true, TRANS_DDI_HDCP_SIGNALLING);
> if (ret) {
> drm_err(&dev_priv->drm,
> "Enable HDCP signalling failed (%d)\n", ret);
> @@ -1526,8 +1527,9 @@ int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
> if (!enable)
> usleep_range(6, 60); /* Bspec says >= 6us */
>
> - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
> - enable);
> + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
> + cpu_transcoder, enable,
> + TRANS_DDI_HDCP_SIGNALLING);
> if (ret) {
> drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n",
> enable ? "Enable" : "Disable", ret);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8b021f77cb1f..77461cde6549 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9982,6 +9982,7 @@ enum skl_power_gate {
> #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
> #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
> #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
> +#define TRANS_DDI_HDCP_SELECT REG_BIT(5)
> #define TRANS_DDI_BFI_ENABLE (1 << 4)
> #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
> #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
> --
> 2.26.2
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 06/16] drm/i915/hdcp: HDCP stream encryption support
@ 2020-11-05 15:34 ` Ramalingam C
0 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-05 15:34 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: jani.nikula, intel-gfx, dri-devel, seanpaul
On 2020-10-27 at 22:11:58 +0530, Anshuman Gupta wrote:
> Both HDCP_{1.x,2.x} requires to select/deselect Multistream HDCP bit
> in TRANS_DDI_FUNC_CTL in order to enable/disable stream HDCP
> encryption over DP MST Transport Link.
>
> HDCP 1.4 stream encryption requires to validate the stream encryption
> status in HDCP_STATUS_{TRANSCODER,PORT} register driving that link
> in order to enable/disable the stream encryption.
>
> Both of above requirement are same for all Gen with respect to
> B.Spec Documentation.
>
> v2:
> Cosmetic changes function name, error msg print and
> stream typo fixes. [Uma]
>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 10 +--
> drivers/gpu/drm/i915/display/intel_ddi.h | 6 +-
> .../drm/i915/display/intel_display_types.h | 4 +
> drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 80 ++++++++++++++++---
> drivers/gpu/drm/i915/display/intel_hdmi.c | 14 ++--
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 6 files changed, 90 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 9fce623e951e..779603a38cfc 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1948,9 +1948,9 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
> }
> }
>
> -int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
> - enum transcoder cpu_transcoder,
> - bool enable)
> +int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
> + enum transcoder cpu_transcoder,
> + bool enable, u32 hdcp_mask)
> {
> struct drm_device *dev = intel_encoder->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -1965,9 +1965,9 @@ int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
>
> tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
> if (enable)
> - tmp |= TRANS_DDI_HDCP_SIGNALLING;
> + tmp |= hdcp_mask;
> else
> - tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
> + tmp &= ~hdcp_mask;
> intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp);
> intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
> return ret;
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
> index dcc711cfe4fe..a4dd815c0000 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.h
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.h
> @@ -50,9 +50,9 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state);
> u32 ddi_signal_levels(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state);
> -int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
> - enum transcoder cpu_transcoder,
> - bool enable);
> +int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
> + enum transcoder cpu_transcoder,
> + bool enable, u32 hdcp_mask);
> void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
>
> #endif /* __INTEL_DDI_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index c47124a679b6..59b8fc21e3e8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -339,6 +339,10 @@ struct intel_hdcp_shim {
> enum transcoder cpu_transcoder,
> bool enable);
>
> + /* Enable/Disable stream encryption on DP MST Transport Link */
> + int (*stream_encryption)(struct intel_digital_port *dig_port,
> + bool enable);
> +
> /* Ensures the link is still protected */
> bool (*check_link)(struct intel_digital_port *dig_port,
> struct intel_connector *connector);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> index 03424d20e9f7..6dcbfaffd2c5 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> @@ -16,6 +16,30 @@
> #include "intel_dp.h"
> #include "intel_hdcp.h"
>
> +static unsigned int transcoder_to_stream_enc_status(enum transcoder cpu_transcoder)
> +{
> + u32 stream_enc_mask;
> +
> + switch (cpu_transcoder) {
> + case TRANSCODER_A:
> + stream_enc_mask = HDCP_STATUS_STREAM_A_ENC;
> + break;
> + case TRANSCODER_B:
> + stream_enc_mask = HDCP_STATUS_STREAM_B_ENC;
> + break;
> + case TRANSCODER_C:
> + stream_enc_mask = HDCP_STATUS_STREAM_C_ENC;
> + break;
> + case TRANSCODER_D:
> + stream_enc_mask = HDCP_STATUS_STREAM_D_ENC;
> + break;
> + default:
> + stream_enc_mask = 0;
> + }
> +
> + return stream_enc_mask;
> +}
> +
> static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
> {
> long ret;
> @@ -622,24 +646,57 @@ static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
> };
>
> static int
> -intel_dp_mst_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
> - enum transcoder cpu_transcoder,
> - bool enable)
> +intel_dp_mst_toggle_hdcp_stream_select(struct intel_digital_port *dig_port,
> + bool enable)
> {
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + struct intel_dp *dp = &dig_port->dp;
> + struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
> int ret;
>
> - if (!enable)
> - usleep_range(6, 60); /* Bspec says >= 6us */
Any reason why this is removed from disable path? Or i am missing the
movement?
-Ram
> -
> - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base,
> - cpu_transcoder, enable);
> + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
> + hdcp->stream_transcoder, enable,
> + TRANS_DDI_HDCP_SELECT);
> if (ret)
> - drm_dbg_kms(&i915->drm, "%s HDCP signalling failed (%d)\n",
> - enable ? "Enable" : "Disable", ret);
> + drm_err(&i915->drm, "%s HDCP stream select failed (%d)\n",
> + enable ? "Enable" : "Disable", ret);
> return ret;
> }
>
> +static int
> +intel_dp_mst_hdcp_stream_encryption(struct intel_digital_port *dig_port,
> + bool enable)
> +{
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + struct intel_dp *dp = &dig_port->dp;
> + struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
> + enum port port = dig_port->base.port;
> + enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
> + u32 stream_enc_status;
> + int ret;
> +
> + ret = intel_dp_mst_toggle_hdcp_stream_select(dig_port, enable);
> + if (ret)
> + return ret;
> +
> + stream_enc_status = transcoder_to_stream_enc_status(hdcp->stream_transcoder);
> + if (!stream_enc_status)
> + return -EINVAL;
> +
> + /* Wait for encryption confirmation */
> + if (intel_de_wait_for_register(i915,
> + HDCP_STATUS(i915, cpu_transcoder, port),
> + stream_enc_status,
> + enable ? stream_enc_status : 0,
> + HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> + drm_err(&i915->drm, "Timed out waiting for stream encryption %s\n",
> + enable ? "enabled" : "disabled");
> + return -ETIMEDOUT;
> + }
> +
> + return 0;
> +}
> +
> static
> bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
> struct intel_connector *connector)
> @@ -673,7 +730,8 @@ static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
> .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
> .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
> .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
> - .toggle_signalling = intel_dp_mst_hdcp_toggle_signalling,
> + .toggle_signalling = intel_dp_hdcp_toggle_signalling,
> + .stream_encryption = intel_dp_mst_hdcp_stream_encryption,
> .check_link = intel_dp_mst_hdcp_check_link,
> .hdcp_capable = intel_dp_hdcp_capable,
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index f90838bc74fb..f58469226694 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -1495,15 +1495,16 @@ static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
> usleep_range(25, 50);
> }
>
> - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
> - false);
> + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
> + false, TRANS_DDI_HDCP_SIGNALLING);
> if (ret) {
> drm_err(&dev_priv->drm,
> "Disable HDCP signalling failed (%d)\n", ret);
> return ret;
> }
> - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
> - true);
> +
> + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
> + true, TRANS_DDI_HDCP_SIGNALLING);
> if (ret) {
> drm_err(&dev_priv->drm,
> "Enable HDCP signalling failed (%d)\n", ret);
> @@ -1526,8 +1527,9 @@ int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
> if (!enable)
> usleep_range(6, 60); /* Bspec says >= 6us */
>
> - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
> - enable);
> + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
> + cpu_transcoder, enable,
> + TRANS_DDI_HDCP_SIGNALLING);
> if (ret) {
> drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n",
> enable ? "Enable" : "Disable", ret);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8b021f77cb1f..77461cde6549 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9982,6 +9982,7 @@ enum skl_power_gate {
> #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
> #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
> #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
> +#define TRANS_DDI_HDCP_SELECT REG_BIT(5)
> #define TRANS_DDI_BFI_ENABLE (1 << 4)
> #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
> #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
> --
> 2.26.2
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [PATCH v4 06/16] drm/i915/hdcp: HDCP stream encryption support
2020-11-05 15:34 ` [Intel-gfx] " Ramalingam C
@ 2020-11-06 5:22 ` Anshuman Gupta
-1 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-11-06 5:22 UTC (permalink / raw)
To: Ramalingam C
Cc: jani.nikula, intel-gfx, dri-devel, uma.shankar, seanpaul, juston.li
On 2020-11-05 at 21:04:03 +0530, Ramalingam C wrote:
> On 2020-10-27 at 22:11:58 +0530, Anshuman Gupta wrote:
> > Both HDCP_{1.x,2.x} requires to select/deselect Multistream HDCP bit
> > in TRANS_DDI_FUNC_CTL in order to enable/disable stream HDCP
> > encryption over DP MST Transport Link.
> >
> > HDCP 1.4 stream encryption requires to validate the stream encryption
> > status in HDCP_STATUS_{TRANSCODER,PORT} register driving that link
> > in order to enable/disable the stream encryption.
> >
> > Both of above requirement are same for all Gen with respect to
> > B.Spec Documentation.
> >
> > v2:
> > Cosmetic changes function name, error msg print and
> > stream typo fixes. [Uma]
> >
> > Cc: Ramalingam C <ramalingam.c@intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 10 +--
> > drivers/gpu/drm/i915/display/intel_ddi.h | 6 +-
> > .../drm/i915/display/intel_display_types.h | 4 +
> > drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 80 ++++++++++++++++---
> > drivers/gpu/drm/i915/display/intel_hdmi.c | 14 ++--
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > 6 files changed, 90 insertions(+), 25 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 9fce623e951e..779603a38cfc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -1948,9 +1948,9 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
> > }
> > }
> >
> > -int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
> > - enum transcoder cpu_transcoder,
> > - bool enable)
> > +int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
> > + enum transcoder cpu_transcoder,
> > + bool enable, u32 hdcp_mask)
> > {
> > struct drm_device *dev = intel_encoder->base.dev;
> > struct drm_i915_private *dev_priv = to_i915(dev);
> > @@ -1965,9 +1965,9 @@ int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
> >
> > tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
> > if (enable)
> > - tmp |= TRANS_DDI_HDCP_SIGNALLING;
> > + tmp |= hdcp_mask;
> > else
> > - tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
> > + tmp &= ~hdcp_mask;
> > intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp);
> > intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
> > return ret;
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
> > index dcc711cfe4fe..a4dd815c0000 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.h
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.h
> > @@ -50,9 +50,9 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp,
> > const struct intel_crtc_state *crtc_state);
> > u32 ddi_signal_levels(struct intel_dp *intel_dp,
> > const struct intel_crtc_state *crtc_state);
> > -int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
> > - enum transcoder cpu_transcoder,
> > - bool enable);
> > +int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
> > + enum transcoder cpu_transcoder,
> > + bool enable, u32 hdcp_mask);
> > void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
> >
> > #endif /* __INTEL_DDI_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index c47124a679b6..59b8fc21e3e8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -339,6 +339,10 @@ struct intel_hdcp_shim {
> > enum transcoder cpu_transcoder,
> > bool enable);
> >
> > + /* Enable/Disable stream encryption on DP MST Transport Link */
> > + int (*stream_encryption)(struct intel_digital_port *dig_port,
> > + bool enable);
> > +
> > /* Ensures the link is still protected */
> > bool (*check_link)(struct intel_digital_port *dig_port,
> > struct intel_connector *connector);
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > index 03424d20e9f7..6dcbfaffd2c5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > @@ -16,6 +16,30 @@
> > #include "intel_dp.h"
> > #include "intel_hdcp.h"
> >
> > +static unsigned int transcoder_to_stream_enc_status(enum transcoder cpu_transcoder)
> > +{
> > + u32 stream_enc_mask;
> > +
> > + switch (cpu_transcoder) {
> > + case TRANSCODER_A:
> > + stream_enc_mask = HDCP_STATUS_STREAM_A_ENC;
> > + break;
> > + case TRANSCODER_B:
> > + stream_enc_mask = HDCP_STATUS_STREAM_B_ENC;
> > + break;
> > + case TRANSCODER_C:
> > + stream_enc_mask = HDCP_STATUS_STREAM_C_ENC;
> > + break;
> > + case TRANSCODER_D:
> > + stream_enc_mask = HDCP_STATUS_STREAM_D_ENC;
> > + break;
> > + default:
> > + stream_enc_mask = 0;
> > + }
> > +
> > + return stream_enc_mask;
> > +}
> > +
> > static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
> > {
> > long ret;
> > @@ -622,24 +646,57 @@ static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
> > };
> >
> > static int
> > -intel_dp_mst_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
> > - enum transcoder cpu_transcoder,
> > - bool enable)
> > +intel_dp_mst_toggle_hdcp_stream_select(struct intel_digital_port *dig_port,
> > + bool enable)
> > {
> > struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > + struct intel_dp *dp = &dig_port->dp;
> > + struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
> > int ret;
> >
> > - if (!enable)
> > - usleep_range(6, 60); /* Bspec says >= 6us */
> Any reason why this is removed from disable path? Or i am missing the
> movement?
It is required for HDMI when disabling HDCP signalling, not for HDCP
stream select.
According to B.Spec
"If using HDMI or DVI, wait for at least 6 microseconds after the previous step, then disable HDCP signaling in the Transcoder DDI Function Control register."
Thanks,
Anshuman Gupta.
>
> -Ram
> > -
> > - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base,
> > - cpu_transcoder, enable);
> > + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
> > + hdcp->stream_transcoder, enable,
> > + TRANS_DDI_HDCP_SELECT);
> > if (ret)
> > - drm_dbg_kms(&i915->drm, "%s HDCP signalling failed (%d)\n",
> > - enable ? "Enable" : "Disable", ret);
> > + drm_err(&i915->drm, "%s HDCP stream select failed (%d)\n",
> > + enable ? "Enable" : "Disable", ret);
> > return ret;
> > }
> >
> > +static int
> > +intel_dp_mst_hdcp_stream_encryption(struct intel_digital_port *dig_port,
> > + bool enable)
> > +{
> > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > + struct intel_dp *dp = &dig_port->dp;
> > + struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
> > + enum port port = dig_port->base.port;
> > + enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
> > + u32 stream_enc_status;
> > + int ret;
> > +
> > + ret = intel_dp_mst_toggle_hdcp_stream_select(dig_port, enable);
> > + if (ret)
> > + return ret;
> > +
> > + stream_enc_status = transcoder_to_stream_enc_status(hdcp->stream_transcoder);
> > + if (!stream_enc_status)
> > + return -EINVAL;
> > +
> > + /* Wait for encryption confirmation */
> > + if (intel_de_wait_for_register(i915,
> > + HDCP_STATUS(i915, cpu_transcoder, port),
> > + stream_enc_status,
> > + enable ? stream_enc_status : 0,
> > + HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> > + drm_err(&i915->drm, "Timed out waiting for stream encryption %s\n",
> > + enable ? "enabled" : "disabled");
> > + return -ETIMEDOUT;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > static
> > bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
> > struct intel_connector *connector)
> > @@ -673,7 +730,8 @@ static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
> > .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
> > .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
> > .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
> > - .toggle_signalling = intel_dp_mst_hdcp_toggle_signalling,
> > + .toggle_signalling = intel_dp_hdcp_toggle_signalling,
> > + .stream_encryption = intel_dp_mst_hdcp_stream_encryption,
> > .check_link = intel_dp_mst_hdcp_check_link,
> > .hdcp_capable = intel_dp_hdcp_capable,
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > index f90838bc74fb..f58469226694 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > @@ -1495,15 +1495,16 @@ static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
> > usleep_range(25, 50);
> > }
> >
> > - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
> > - false);
> > + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
> > + false, TRANS_DDI_HDCP_SIGNALLING);
> > if (ret) {
> > drm_err(&dev_priv->drm,
> > "Disable HDCP signalling failed (%d)\n", ret);
> > return ret;
> > }
> > - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
> > - true);
> > +
> > + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
> > + true, TRANS_DDI_HDCP_SIGNALLING);
> > if (ret) {
> > drm_err(&dev_priv->drm,
> > "Enable HDCP signalling failed (%d)\n", ret);
> > @@ -1526,8 +1527,9 @@ int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
> > if (!enable)
> > usleep_range(6, 60); /* Bspec says >= 6us */
> >
> > - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
> > - enable);
> > + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
> > + cpu_transcoder, enable,
> > + TRANS_DDI_HDCP_SIGNALLING);
> > if (ret) {
> > drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n",
> > enable ? "Enable" : "Disable", ret);
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 8b021f77cb1f..77461cde6549 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -9982,6 +9982,7 @@ enum skl_power_gate {
> > #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
> > #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
> > #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
> > +#define TRANS_DDI_HDCP_SELECT REG_BIT(5)
> > #define TRANS_DDI_BFI_ENABLE (1 << 4)
> > #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
> > #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
> > --
> > 2.26.2
> >
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 06/16] drm/i915/hdcp: HDCP stream encryption support
@ 2020-11-06 5:22 ` Anshuman Gupta
0 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-11-06 5:22 UTC (permalink / raw)
To: Ramalingam C; +Cc: jani.nikula, intel-gfx, dri-devel, seanpaul
On 2020-11-05 at 21:04:03 +0530, Ramalingam C wrote:
> On 2020-10-27 at 22:11:58 +0530, Anshuman Gupta wrote:
> > Both HDCP_{1.x,2.x} requires to select/deselect Multistream HDCP bit
> > in TRANS_DDI_FUNC_CTL in order to enable/disable stream HDCP
> > encryption over DP MST Transport Link.
> >
> > HDCP 1.4 stream encryption requires to validate the stream encryption
> > status in HDCP_STATUS_{TRANSCODER,PORT} register driving that link
> > in order to enable/disable the stream encryption.
> >
> > Both of above requirement are same for all Gen with respect to
> > B.Spec Documentation.
> >
> > v2:
> > Cosmetic changes function name, error msg print and
> > stream typo fixes. [Uma]
> >
> > Cc: Ramalingam C <ramalingam.c@intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 10 +--
> > drivers/gpu/drm/i915/display/intel_ddi.h | 6 +-
> > .../drm/i915/display/intel_display_types.h | 4 +
> > drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 80 ++++++++++++++++---
> > drivers/gpu/drm/i915/display/intel_hdmi.c | 14 ++--
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > 6 files changed, 90 insertions(+), 25 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 9fce623e951e..779603a38cfc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -1948,9 +1948,9 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
> > }
> > }
> >
> > -int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
> > - enum transcoder cpu_transcoder,
> > - bool enable)
> > +int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
> > + enum transcoder cpu_transcoder,
> > + bool enable, u32 hdcp_mask)
> > {
> > struct drm_device *dev = intel_encoder->base.dev;
> > struct drm_i915_private *dev_priv = to_i915(dev);
> > @@ -1965,9 +1965,9 @@ int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
> >
> > tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
> > if (enable)
> > - tmp |= TRANS_DDI_HDCP_SIGNALLING;
> > + tmp |= hdcp_mask;
> > else
> > - tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
> > + tmp &= ~hdcp_mask;
> > intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp);
> > intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
> > return ret;
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
> > index dcc711cfe4fe..a4dd815c0000 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.h
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.h
> > @@ -50,9 +50,9 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp,
> > const struct intel_crtc_state *crtc_state);
> > u32 ddi_signal_levels(struct intel_dp *intel_dp,
> > const struct intel_crtc_state *crtc_state);
> > -int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
> > - enum transcoder cpu_transcoder,
> > - bool enable);
> > +int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
> > + enum transcoder cpu_transcoder,
> > + bool enable, u32 hdcp_mask);
> > void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
> >
> > #endif /* __INTEL_DDI_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index c47124a679b6..59b8fc21e3e8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -339,6 +339,10 @@ struct intel_hdcp_shim {
> > enum transcoder cpu_transcoder,
> > bool enable);
> >
> > + /* Enable/Disable stream encryption on DP MST Transport Link */
> > + int (*stream_encryption)(struct intel_digital_port *dig_port,
> > + bool enable);
> > +
> > /* Ensures the link is still protected */
> > bool (*check_link)(struct intel_digital_port *dig_port,
> > struct intel_connector *connector);
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > index 03424d20e9f7..6dcbfaffd2c5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > @@ -16,6 +16,30 @@
> > #include "intel_dp.h"
> > #include "intel_hdcp.h"
> >
> > +static unsigned int transcoder_to_stream_enc_status(enum transcoder cpu_transcoder)
> > +{
> > + u32 stream_enc_mask;
> > +
> > + switch (cpu_transcoder) {
> > + case TRANSCODER_A:
> > + stream_enc_mask = HDCP_STATUS_STREAM_A_ENC;
> > + break;
> > + case TRANSCODER_B:
> > + stream_enc_mask = HDCP_STATUS_STREAM_B_ENC;
> > + break;
> > + case TRANSCODER_C:
> > + stream_enc_mask = HDCP_STATUS_STREAM_C_ENC;
> > + break;
> > + case TRANSCODER_D:
> > + stream_enc_mask = HDCP_STATUS_STREAM_D_ENC;
> > + break;
> > + default:
> > + stream_enc_mask = 0;
> > + }
> > +
> > + return stream_enc_mask;
> > +}
> > +
> > static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
> > {
> > long ret;
> > @@ -622,24 +646,57 @@ static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
> > };
> >
> > static int
> > -intel_dp_mst_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
> > - enum transcoder cpu_transcoder,
> > - bool enable)
> > +intel_dp_mst_toggle_hdcp_stream_select(struct intel_digital_port *dig_port,
> > + bool enable)
> > {
> > struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > + struct intel_dp *dp = &dig_port->dp;
> > + struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
> > int ret;
> >
> > - if (!enable)
> > - usleep_range(6, 60); /* Bspec says >= 6us */
> Any reason why this is removed from disable path? Or i am missing the
> movement?
It is required for HDMI when disabling HDCP signalling, not for HDCP
stream select.
According to B.Spec
"If using HDMI or DVI, wait for at least 6 microseconds after the previous step, then disable HDCP signaling in the Transcoder DDI Function Control register."
Thanks,
Anshuman Gupta.
>
> -Ram
> > -
> > - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base,
> > - cpu_transcoder, enable);
> > + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
> > + hdcp->stream_transcoder, enable,
> > + TRANS_DDI_HDCP_SELECT);
> > if (ret)
> > - drm_dbg_kms(&i915->drm, "%s HDCP signalling failed (%d)\n",
> > - enable ? "Enable" : "Disable", ret);
> > + drm_err(&i915->drm, "%s HDCP stream select failed (%d)\n",
> > + enable ? "Enable" : "Disable", ret);
> > return ret;
> > }
> >
> > +static int
> > +intel_dp_mst_hdcp_stream_encryption(struct intel_digital_port *dig_port,
> > + bool enable)
> > +{
> > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > + struct intel_dp *dp = &dig_port->dp;
> > + struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
> > + enum port port = dig_port->base.port;
> > + enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
> > + u32 stream_enc_status;
> > + int ret;
> > +
> > + ret = intel_dp_mst_toggle_hdcp_stream_select(dig_port, enable);
> > + if (ret)
> > + return ret;
> > +
> > + stream_enc_status = transcoder_to_stream_enc_status(hdcp->stream_transcoder);
> > + if (!stream_enc_status)
> > + return -EINVAL;
> > +
> > + /* Wait for encryption confirmation */
> > + if (intel_de_wait_for_register(i915,
> > + HDCP_STATUS(i915, cpu_transcoder, port),
> > + stream_enc_status,
> > + enable ? stream_enc_status : 0,
> > + HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> > + drm_err(&i915->drm, "Timed out waiting for stream encryption %s\n",
> > + enable ? "enabled" : "disabled");
> > + return -ETIMEDOUT;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > static
> > bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
> > struct intel_connector *connector)
> > @@ -673,7 +730,8 @@ static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
> > .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
> > .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
> > .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
> > - .toggle_signalling = intel_dp_mst_hdcp_toggle_signalling,
> > + .toggle_signalling = intel_dp_hdcp_toggle_signalling,
> > + .stream_encryption = intel_dp_mst_hdcp_stream_encryption,
> > .check_link = intel_dp_mst_hdcp_check_link,
> > .hdcp_capable = intel_dp_hdcp_capable,
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > index f90838bc74fb..f58469226694 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > @@ -1495,15 +1495,16 @@ static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
> > usleep_range(25, 50);
> > }
> >
> > - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
> > - false);
> > + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
> > + false, TRANS_DDI_HDCP_SIGNALLING);
> > if (ret) {
> > drm_err(&dev_priv->drm,
> > "Disable HDCP signalling failed (%d)\n", ret);
> > return ret;
> > }
> > - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
> > - true);
> > +
> > + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
> > + true, TRANS_DDI_HDCP_SIGNALLING);
> > if (ret) {
> > drm_err(&dev_priv->drm,
> > "Enable HDCP signalling failed (%d)\n", ret);
> > @@ -1526,8 +1527,9 @@ int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
> > if (!enable)
> > usleep_range(6, 60); /* Bspec says >= 6us */
> >
> > - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
> > - enable);
> > + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
> > + cpu_transcoder, enable,
> > + TRANS_DDI_HDCP_SIGNALLING);
> > if (ret) {
> > drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n",
> > enable ? "Enable" : "Disable", ret);
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 8b021f77cb1f..77461cde6549 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -9982,6 +9982,7 @@ enum skl_power_gate {
> > #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
> > #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
> > #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
> > +#define TRANS_DDI_HDCP_SELECT REG_BIT(5)
> > #define TRANS_DDI_BFI_ENABLE (1 << 4)
> > #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
> > #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
> > --
> > 2.26.2
> >
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [PATCH v4 06/16] drm/i915/hdcp: HDCP stream encryption support
2020-11-06 5:22 ` [Intel-gfx] " Anshuman Gupta
@ 2020-11-06 7:52 ` Ramalingam C
-1 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-06 7:52 UTC (permalink / raw)
To: Anshuman Gupta
Cc: jani.nikula, intel-gfx, dri-devel, uma.shankar, seanpaul, juston.li
On 2020-11-06 at 10:52:03 +0530, Anshuman Gupta wrote:
> On 2020-11-05 at 21:04:03 +0530, Ramalingam C wrote:
> > On 2020-10-27 at 22:11:58 +0530, Anshuman Gupta wrote:
> > > Both HDCP_{1.x,2.x} requires to select/deselect Multistream HDCP bit
> > > in TRANS_DDI_FUNC_CTL in order to enable/disable stream HDCP
> > > encryption over DP MST Transport Link.
> > >
> > > HDCP 1.4 stream encryption requires to validate the stream encryption
> > > status in HDCP_STATUS_{TRANSCODER,PORT} register driving that link
> > > in order to enable/disable the stream encryption.
> > >
> > > Both of above requirement are same for all Gen with respect to
> > > B.Spec Documentation.
> > >
> > > v2:
> > > Cosmetic changes function name, error msg print and
> > > stream typo fixes. [Uma]
> > >
> > > Cc: Ramalingam C <ramalingam.c@intel.com>
> > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_ddi.c | 10 +--
> > > drivers/gpu/drm/i915/display/intel_ddi.h | 6 +-
> > > .../drm/i915/display/intel_display_types.h | 4 +
> > > drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 80 ++++++++++++++++---
> > > drivers/gpu/drm/i915/display/intel_hdmi.c | 14 ++--
> > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > 6 files changed, 90 insertions(+), 25 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > index 9fce623e951e..779603a38cfc 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > @@ -1948,9 +1948,9 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
> > > }
> > > }
> > >
> > > -int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
> > > - enum transcoder cpu_transcoder,
> > > - bool enable)
> > > +int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
> > > + enum transcoder cpu_transcoder,
> > > + bool enable, u32 hdcp_mask)
> > > {
> > > struct drm_device *dev = intel_encoder->base.dev;
> > > struct drm_i915_private *dev_priv = to_i915(dev);
> > > @@ -1965,9 +1965,9 @@ int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
> > >
> > > tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
> > > if (enable)
> > > - tmp |= TRANS_DDI_HDCP_SIGNALLING;
> > > + tmp |= hdcp_mask;
> > > else
> > > - tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
> > > + tmp &= ~hdcp_mask;
> > > intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp);
> > > intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
> > > return ret;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
> > > index dcc711cfe4fe..a4dd815c0000 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.h
> > > @@ -50,9 +50,9 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp,
> > > const struct intel_crtc_state *crtc_state);
> > > u32 ddi_signal_levels(struct intel_dp *intel_dp,
> > > const struct intel_crtc_state *crtc_state);
> > > -int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
> > > - enum transcoder cpu_transcoder,
> > > - bool enable);
> > > +int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
> > > + enum transcoder cpu_transcoder,
> > > + bool enable, u32 hdcp_mask);
> > > void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
> > >
> > > #endif /* __INTEL_DDI_H__ */
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index c47124a679b6..59b8fc21e3e8 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -339,6 +339,10 @@ struct intel_hdcp_shim {
> > > enum transcoder cpu_transcoder,
> > > bool enable);
> > >
> > > + /* Enable/Disable stream encryption on DP MST Transport Link */
> > > + int (*stream_encryption)(struct intel_digital_port *dig_port,
> > > + bool enable);
> > > +
> > > /* Ensures the link is still protected */
> > > bool (*check_link)(struct intel_digital_port *dig_port,
> > > struct intel_connector *connector);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > > index 03424d20e9f7..6dcbfaffd2c5 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > > @@ -16,6 +16,30 @@
> > > #include "intel_dp.h"
> > > #include "intel_hdcp.h"
> > >
> > > +static unsigned int transcoder_to_stream_enc_status(enum transcoder cpu_transcoder)
> > > +{
> > > + u32 stream_enc_mask;
> > > +
> > > + switch (cpu_transcoder) {
> > > + case TRANSCODER_A:
> > > + stream_enc_mask = HDCP_STATUS_STREAM_A_ENC;
> > > + break;
> > > + case TRANSCODER_B:
> > > + stream_enc_mask = HDCP_STATUS_STREAM_B_ENC;
> > > + break;
> > > + case TRANSCODER_C:
> > > + stream_enc_mask = HDCP_STATUS_STREAM_C_ENC;
> > > + break;
> > > + case TRANSCODER_D:
> > > + stream_enc_mask = HDCP_STATUS_STREAM_D_ENC;
> > > + break;
> > > + default:
> > > + stream_enc_mask = 0;
> > > + }
> > > +
> > > + return stream_enc_mask;
> > > +}
> > > +
> > > static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
> > > {
> > > long ret;
> > > @@ -622,24 +646,57 @@ static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
> > > };
> > >
> > > static int
> > > -intel_dp_mst_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
> > > - enum transcoder cpu_transcoder,
> > > - bool enable)
> > > +intel_dp_mst_toggle_hdcp_stream_select(struct intel_digital_port *dig_port,
> > > + bool enable)
> > > {
> > > struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > > + struct intel_dp *dp = &dig_port->dp;
> > > + struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
> > > int ret;
> > >
> > > - if (!enable)
> > > - usleep_range(6, 60); /* Bspec says >= 6us */
> > Any reason why this is removed from disable path? Or i am missing the
> > movement?
> It is required for HDMI when disabling HDCP signalling, not for HDCP
> stream select.
> According to B.Spec
> "If using HDMI or DVI, wait for at least 6 microseconds after the previous step, then disable HDCP signaling in the Transcoder DDI Function Control register."
Ok.
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
> Thanks,
> Anshuman Gupta.
> >
> > -Ram
> > > -
> > > - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base,
> > > - cpu_transcoder, enable);
> > > + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
> > > + hdcp->stream_transcoder, enable,
> > > + TRANS_DDI_HDCP_SELECT);
> > > if (ret)
> > > - drm_dbg_kms(&i915->drm, "%s HDCP signalling failed (%d)\n",
> > > - enable ? "Enable" : "Disable", ret);
> > > + drm_err(&i915->drm, "%s HDCP stream select failed (%d)\n",
> > > + enable ? "Enable" : "Disable", ret);
> > > return ret;
> > > }
> > >
> > > +static int
> > > +intel_dp_mst_hdcp_stream_encryption(struct intel_digital_port *dig_port,
> > > + bool enable)
> > > +{
> > > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > > + struct intel_dp *dp = &dig_port->dp;
> > > + struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
> > > + enum port port = dig_port->base.port;
> > > + enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
> > > + u32 stream_enc_status;
> > > + int ret;
> > > +
> > > + ret = intel_dp_mst_toggle_hdcp_stream_select(dig_port, enable);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + stream_enc_status = transcoder_to_stream_enc_status(hdcp->stream_transcoder);
> > > + if (!stream_enc_status)
> > > + return -EINVAL;
> > > +
> > > + /* Wait for encryption confirmation */
> > > + if (intel_de_wait_for_register(i915,
> > > + HDCP_STATUS(i915, cpu_transcoder, port),
> > > + stream_enc_status,
> > > + enable ? stream_enc_status : 0,
> > > + HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> > > + drm_err(&i915->drm, "Timed out waiting for stream encryption %s\n",
> > > + enable ? "enabled" : "disabled");
> > > + return -ETIMEDOUT;
> > > + }
> > > +
> > > + return 0;
> > > +}
> > > +
> > > static
> > > bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
> > > struct intel_connector *connector)
> > > @@ -673,7 +730,8 @@ static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
> > > .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
> > > .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
> > > .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
> > > - .toggle_signalling = intel_dp_mst_hdcp_toggle_signalling,
> > > + .toggle_signalling = intel_dp_hdcp_toggle_signalling,
> > > + .stream_encryption = intel_dp_mst_hdcp_stream_encryption,
> > > .check_link = intel_dp_mst_hdcp_check_link,
> > > .hdcp_capable = intel_dp_hdcp_capable,
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > > index f90838bc74fb..f58469226694 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > > @@ -1495,15 +1495,16 @@ static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
> > > usleep_range(25, 50);
> > > }
> > >
> > > - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
> > > - false);
> > > + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
> > > + false, TRANS_DDI_HDCP_SIGNALLING);
> > > if (ret) {
> > > drm_err(&dev_priv->drm,
> > > "Disable HDCP signalling failed (%d)\n", ret);
> > > return ret;
> > > }
> > > - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
> > > - true);
> > > +
> > > + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
> > > + true, TRANS_DDI_HDCP_SIGNALLING);
> > > if (ret) {
> > > drm_err(&dev_priv->drm,
> > > "Enable HDCP signalling failed (%d)\n", ret);
> > > @@ -1526,8 +1527,9 @@ int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
> > > if (!enable)
> > > usleep_range(6, 60); /* Bspec says >= 6us */
> > >
> > > - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
> > > - enable);
> > > + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
> > > + cpu_transcoder, enable,
> > > + TRANS_DDI_HDCP_SIGNALLING);
> > > if (ret) {
> > > drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n",
> > > enable ? "Enable" : "Disable", ret);
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 8b021f77cb1f..77461cde6549 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -9982,6 +9982,7 @@ enum skl_power_gate {
> > > #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
> > > #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
> > > #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
> > > +#define TRANS_DDI_HDCP_SELECT REG_BIT(5)
> > > #define TRANS_DDI_BFI_ENABLE (1 << 4)
> > > #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
> > > #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
> > > --
> > > 2.26.2
> > >
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^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 06/16] drm/i915/hdcp: HDCP stream encryption support
@ 2020-11-06 7:52 ` Ramalingam C
0 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-06 7:52 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: jani.nikula, intel-gfx, dri-devel, seanpaul
On 2020-11-06 at 10:52:03 +0530, Anshuman Gupta wrote:
> On 2020-11-05 at 21:04:03 +0530, Ramalingam C wrote:
> > On 2020-10-27 at 22:11:58 +0530, Anshuman Gupta wrote:
> > > Both HDCP_{1.x,2.x} requires to select/deselect Multistream HDCP bit
> > > in TRANS_DDI_FUNC_CTL in order to enable/disable stream HDCP
> > > encryption over DP MST Transport Link.
> > >
> > > HDCP 1.4 stream encryption requires to validate the stream encryption
> > > status in HDCP_STATUS_{TRANSCODER,PORT} register driving that link
> > > in order to enable/disable the stream encryption.
> > >
> > > Both of above requirement are same for all Gen with respect to
> > > B.Spec Documentation.
> > >
> > > v2:
> > > Cosmetic changes function name, error msg print and
> > > stream typo fixes. [Uma]
> > >
> > > Cc: Ramalingam C <ramalingam.c@intel.com>
> > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_ddi.c | 10 +--
> > > drivers/gpu/drm/i915/display/intel_ddi.h | 6 +-
> > > .../drm/i915/display/intel_display_types.h | 4 +
> > > drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 80 ++++++++++++++++---
> > > drivers/gpu/drm/i915/display/intel_hdmi.c | 14 ++--
> > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > 6 files changed, 90 insertions(+), 25 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > index 9fce623e951e..779603a38cfc 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > @@ -1948,9 +1948,9 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
> > > }
> > > }
> > >
> > > -int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
> > > - enum transcoder cpu_transcoder,
> > > - bool enable)
> > > +int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
> > > + enum transcoder cpu_transcoder,
> > > + bool enable, u32 hdcp_mask)
> > > {
> > > struct drm_device *dev = intel_encoder->base.dev;
> > > struct drm_i915_private *dev_priv = to_i915(dev);
> > > @@ -1965,9 +1965,9 @@ int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
> > >
> > > tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
> > > if (enable)
> > > - tmp |= TRANS_DDI_HDCP_SIGNALLING;
> > > + tmp |= hdcp_mask;
> > > else
> > > - tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
> > > + tmp &= ~hdcp_mask;
> > > intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp);
> > > intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
> > > return ret;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
> > > index dcc711cfe4fe..a4dd815c0000 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.h
> > > @@ -50,9 +50,9 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp,
> > > const struct intel_crtc_state *crtc_state);
> > > u32 ddi_signal_levels(struct intel_dp *intel_dp,
> > > const struct intel_crtc_state *crtc_state);
> > > -int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
> > > - enum transcoder cpu_transcoder,
> > > - bool enable);
> > > +int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
> > > + enum transcoder cpu_transcoder,
> > > + bool enable, u32 hdcp_mask);
> > > void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
> > >
> > > #endif /* __INTEL_DDI_H__ */
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index c47124a679b6..59b8fc21e3e8 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -339,6 +339,10 @@ struct intel_hdcp_shim {
> > > enum transcoder cpu_transcoder,
> > > bool enable);
> > >
> > > + /* Enable/Disable stream encryption on DP MST Transport Link */
> > > + int (*stream_encryption)(struct intel_digital_port *dig_port,
> > > + bool enable);
> > > +
> > > /* Ensures the link is still protected */
> > > bool (*check_link)(struct intel_digital_port *dig_port,
> > > struct intel_connector *connector);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > > index 03424d20e9f7..6dcbfaffd2c5 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > > @@ -16,6 +16,30 @@
> > > #include "intel_dp.h"
> > > #include "intel_hdcp.h"
> > >
> > > +static unsigned int transcoder_to_stream_enc_status(enum transcoder cpu_transcoder)
> > > +{
> > > + u32 stream_enc_mask;
> > > +
> > > + switch (cpu_transcoder) {
> > > + case TRANSCODER_A:
> > > + stream_enc_mask = HDCP_STATUS_STREAM_A_ENC;
> > > + break;
> > > + case TRANSCODER_B:
> > > + stream_enc_mask = HDCP_STATUS_STREAM_B_ENC;
> > > + break;
> > > + case TRANSCODER_C:
> > > + stream_enc_mask = HDCP_STATUS_STREAM_C_ENC;
> > > + break;
> > > + case TRANSCODER_D:
> > > + stream_enc_mask = HDCP_STATUS_STREAM_D_ENC;
> > > + break;
> > > + default:
> > > + stream_enc_mask = 0;
> > > + }
> > > +
> > > + return stream_enc_mask;
> > > +}
> > > +
> > > static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
> > > {
> > > long ret;
> > > @@ -622,24 +646,57 @@ static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
> > > };
> > >
> > > static int
> > > -intel_dp_mst_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
> > > - enum transcoder cpu_transcoder,
> > > - bool enable)
> > > +intel_dp_mst_toggle_hdcp_stream_select(struct intel_digital_port *dig_port,
> > > + bool enable)
> > > {
> > > struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > > + struct intel_dp *dp = &dig_port->dp;
> > > + struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
> > > int ret;
> > >
> > > - if (!enable)
> > > - usleep_range(6, 60); /* Bspec says >= 6us */
> > Any reason why this is removed from disable path? Or i am missing the
> > movement?
> It is required for HDMI when disabling HDCP signalling, not for HDCP
> stream select.
> According to B.Spec
> "If using HDMI or DVI, wait for at least 6 microseconds after the previous step, then disable HDCP signaling in the Transcoder DDI Function Control register."
Ok.
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
> Thanks,
> Anshuman Gupta.
> >
> > -Ram
> > > -
> > > - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base,
> > > - cpu_transcoder, enable);
> > > + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
> > > + hdcp->stream_transcoder, enable,
> > > + TRANS_DDI_HDCP_SELECT);
> > > if (ret)
> > > - drm_dbg_kms(&i915->drm, "%s HDCP signalling failed (%d)\n",
> > > - enable ? "Enable" : "Disable", ret);
> > > + drm_err(&i915->drm, "%s HDCP stream select failed (%d)\n",
> > > + enable ? "Enable" : "Disable", ret);
> > > return ret;
> > > }
> > >
> > > +static int
> > > +intel_dp_mst_hdcp_stream_encryption(struct intel_digital_port *dig_port,
> > > + bool enable)
> > > +{
> > > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > > + struct intel_dp *dp = &dig_port->dp;
> > > + struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
> > > + enum port port = dig_port->base.port;
> > > + enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
> > > + u32 stream_enc_status;
> > > + int ret;
> > > +
> > > + ret = intel_dp_mst_toggle_hdcp_stream_select(dig_port, enable);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + stream_enc_status = transcoder_to_stream_enc_status(hdcp->stream_transcoder);
> > > + if (!stream_enc_status)
> > > + return -EINVAL;
> > > +
> > > + /* Wait for encryption confirmation */
> > > + if (intel_de_wait_for_register(i915,
> > > + HDCP_STATUS(i915, cpu_transcoder, port),
> > > + stream_enc_status,
> > > + enable ? stream_enc_status : 0,
> > > + HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> > > + drm_err(&i915->drm, "Timed out waiting for stream encryption %s\n",
> > > + enable ? "enabled" : "disabled");
> > > + return -ETIMEDOUT;
> > > + }
> > > +
> > > + return 0;
> > > +}
> > > +
> > > static
> > > bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
> > > struct intel_connector *connector)
> > > @@ -673,7 +730,8 @@ static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
> > > .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
> > > .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
> > > .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
> > > - .toggle_signalling = intel_dp_mst_hdcp_toggle_signalling,
> > > + .toggle_signalling = intel_dp_hdcp_toggle_signalling,
> > > + .stream_encryption = intel_dp_mst_hdcp_stream_encryption,
> > > .check_link = intel_dp_mst_hdcp_check_link,
> > > .hdcp_capable = intel_dp_hdcp_capable,
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > > index f90838bc74fb..f58469226694 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > > @@ -1495,15 +1495,16 @@ static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
> > > usleep_range(25, 50);
> > > }
> > >
> > > - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
> > > - false);
> > > + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
> > > + false, TRANS_DDI_HDCP_SIGNALLING);
> > > if (ret) {
> > > drm_err(&dev_priv->drm,
> > > "Disable HDCP signalling failed (%d)\n", ret);
> > > return ret;
> > > }
> > > - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
> > > - true);
> > > +
> > > + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
> > > + true, TRANS_DDI_HDCP_SIGNALLING);
> > > if (ret) {
> > > drm_err(&dev_priv->drm,
> > > "Enable HDCP signalling failed (%d)\n", ret);
> > > @@ -1526,8 +1527,9 @@ int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
> > > if (!enable)
> > > usleep_range(6, 60); /* Bspec says >= 6us */
> > >
> > > - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
> > > - enable);
> > > + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
> > > + cpu_transcoder, enable,
> > > + TRANS_DDI_HDCP_SIGNALLING);
> > > if (ret) {
> > > drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n",
> > > enable ? "Enable" : "Disable", ret);
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 8b021f77cb1f..77461cde6549 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -9982,6 +9982,7 @@ enum skl_power_gate {
> > > #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
> > > #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
> > > #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
> > > +#define TRANS_DDI_HDCP_SELECT REG_BIT(5)
> > > #define TRANS_DDI_BFI_ENABLE (1 << 4)
> > > #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
> > > #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
> > > --
> > > 2.26.2
> > >
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread
* [PATCH v4 07/16] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
@ 2020-10-27 16:41 ` Anshuman Gupta
-1 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:41 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: jani.nikula, uma.shankar, seanpaul, Anshuman Gupta, juston.li
Enable HDCP 1.4 over DP MST for Gen12.
This also enable the stream encryption support for
older generations, which was missing earlier.
v2:
- Added debug print for stream encryption.
- Disable the hdcp on port after disabling last stream
encryption.
v3:
- Cosmetic change, removed the value less comment. [Uma]
Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++---
drivers/gpu/drm/i915/display/intel_hdcp.c | 43 ++++++++++++++-------
2 files changed, 32 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 16865b200062..f00e12fc83e8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -826,13 +826,9 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
intel_attach_force_audio_property(connector);
intel_attach_broadcast_rgb_property(connector);
-
- /* TODO: Figure out how to make HDCP work on GEN12+ */
- if (INTEL_GEN(dev_priv) < 12) {
- ret = intel_dp_init_hdcp(dig_port, intel_connector);
- if (ret)
- DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
- }
+ ret = intel_dp_init_hdcp(dig_port, intel_connector);
+ if (ret)
+ drm_dbg_kms(&dev_priv->drm, "HDCP init failed, skipping.\n");
/*
* Reuse the prop from the SST connector because we're
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 0322a83c151d..937af4aeaac2 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -612,7 +612,12 @@ int intel_hdcp_auth_downstream(struct intel_connector *connector)
return ret;
}
-/* Implements Part 1 of the HDCP authorization procedure */
+/*
+ * Implements Part 1 of the HDCP authorization procedure.
+ * Authentication Part 1 steps for Multi-stream DisplayPort.
+ * Step 1. Auth Part 1 sequence on the driving MST Trasport Link.
+ * Step 2. Enable encryption for each stream that requires encryption.
+ */
static int intel_hdcp_auth(struct intel_connector *connector)
{
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
@@ -766,10 +771,16 @@ static int intel_hdcp_auth(struct intel_connector *connector)
return -ETIMEDOUT;
}
- /*
- * XXX: If we have MST-connected devices, we need to enable encryption
- * on those as well.
- */
+ /* DP MST Auth Part 1 Step 2.a and Step 2.b */
+ if (shim->stream_encryption) {
+ ret = shim->stream_encryption(dig_port, true);
+ if (ret) {
+ drm_err(&dev_priv->drm, "Failed to enable HDCP 1.4 stream enc\n");
+ return ret;
+ }
+ drm_dbg_kms(&dev_priv->drm, "HDCP 1.4 tras %s stream encrypted\n",
+ transcoder_name(hdcp->stream_transcoder));
+ }
if (repeater_present)
return intel_hdcp_auth_downstream(connector);
@@ -791,18 +802,22 @@ static int _intel_hdcp_disable(struct intel_connector *connector)
drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP is being disabled...\n",
connector->base.name, connector->base.base.id);
+ if (hdcp->shim->stream_encryption) {
+ ret = hdcp->shim->stream_encryption(dig_port, false);
+ if (ret) {
+ drm_err(&dev_priv->drm, "Failed to disable HDCP 1.4 stream enc\n");
+ return ret;
+ }
+ drm_dbg_kms(&dev_priv->drm, "HDCP 1.4 trans %s stream encryption disabled\n",
+ transcoder_name(hdcp->stream_transcoder));
+ }
+
/*
- * If there are other connectors on this port using HDCP, don't disable
- * it. Instead, toggle the HDCP signalling off on that particular
- * connector/pipe and exit.
+ * If there are other connectors on this port using HDCP, don't disable it.
+ * Repeat steps 1-2 for each stream that no longer requires encryption.
*/
- if (dig_port->num_hdcp_streams > 0) {
- ret = hdcp->shim->toggle_signalling(dig_port,
- cpu_transcoder, false);
- if (ret)
- DRM_ERROR("Failed to disable HDCP signalling\n");
+ if (dig_port->num_hdcp_streams > 0)
return ret;
- }
hdcp->hdcp_encrypted = false;
intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port), 0);
--
2.26.2
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 111+ messages in thread* [Intel-gfx] [PATCH v4 07/16] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support
@ 2020-10-27 16:41 ` Anshuman Gupta
0 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:41 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula, seanpaul
Enable HDCP 1.4 over DP MST for Gen12.
This also enable the stream encryption support for
older generations, which was missing earlier.
v2:
- Added debug print for stream encryption.
- Disable the hdcp on port after disabling last stream
encryption.
v3:
- Cosmetic change, removed the value less comment. [Uma]
Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++---
drivers/gpu/drm/i915/display/intel_hdcp.c | 43 ++++++++++++++-------
2 files changed, 32 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 16865b200062..f00e12fc83e8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -826,13 +826,9 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
intel_attach_force_audio_property(connector);
intel_attach_broadcast_rgb_property(connector);
-
- /* TODO: Figure out how to make HDCP work on GEN12+ */
- if (INTEL_GEN(dev_priv) < 12) {
- ret = intel_dp_init_hdcp(dig_port, intel_connector);
- if (ret)
- DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
- }
+ ret = intel_dp_init_hdcp(dig_port, intel_connector);
+ if (ret)
+ drm_dbg_kms(&dev_priv->drm, "HDCP init failed, skipping.\n");
/*
* Reuse the prop from the SST connector because we're
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 0322a83c151d..937af4aeaac2 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -612,7 +612,12 @@ int intel_hdcp_auth_downstream(struct intel_connector *connector)
return ret;
}
-/* Implements Part 1 of the HDCP authorization procedure */
+/*
+ * Implements Part 1 of the HDCP authorization procedure.
+ * Authentication Part 1 steps for Multi-stream DisplayPort.
+ * Step 1. Auth Part 1 sequence on the driving MST Trasport Link.
+ * Step 2. Enable encryption for each stream that requires encryption.
+ */
static int intel_hdcp_auth(struct intel_connector *connector)
{
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
@@ -766,10 +771,16 @@ static int intel_hdcp_auth(struct intel_connector *connector)
return -ETIMEDOUT;
}
- /*
- * XXX: If we have MST-connected devices, we need to enable encryption
- * on those as well.
- */
+ /* DP MST Auth Part 1 Step 2.a and Step 2.b */
+ if (shim->stream_encryption) {
+ ret = shim->stream_encryption(dig_port, true);
+ if (ret) {
+ drm_err(&dev_priv->drm, "Failed to enable HDCP 1.4 stream enc\n");
+ return ret;
+ }
+ drm_dbg_kms(&dev_priv->drm, "HDCP 1.4 tras %s stream encrypted\n",
+ transcoder_name(hdcp->stream_transcoder));
+ }
if (repeater_present)
return intel_hdcp_auth_downstream(connector);
@@ -791,18 +802,22 @@ static int _intel_hdcp_disable(struct intel_connector *connector)
drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP is being disabled...\n",
connector->base.name, connector->base.base.id);
+ if (hdcp->shim->stream_encryption) {
+ ret = hdcp->shim->stream_encryption(dig_port, false);
+ if (ret) {
+ drm_err(&dev_priv->drm, "Failed to disable HDCP 1.4 stream enc\n");
+ return ret;
+ }
+ drm_dbg_kms(&dev_priv->drm, "HDCP 1.4 trans %s stream encryption disabled\n",
+ transcoder_name(hdcp->stream_transcoder));
+ }
+
/*
- * If there are other connectors on this port using HDCP, don't disable
- * it. Instead, toggle the HDCP signalling off on that particular
- * connector/pipe and exit.
+ * If there are other connectors on this port using HDCP, don't disable it.
+ * Repeat steps 1-2 for each stream that no longer requires encryption.
*/
- if (dig_port->num_hdcp_streams > 0) {
- ret = hdcp->shim->toggle_signalling(dig_port,
- cpu_transcoder, false);
- if (ret)
- DRM_ERROR("Failed to disable HDCP signalling\n");
+ if (dig_port->num_hdcp_streams > 0)
return ret;
- }
hdcp->hdcp_encrypted = false;
intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port), 0);
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 111+ messages in thread* RE: [PATCH v4 07/16] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
@ 2020-11-02 7:47 ` Shankar, Uma
-1 siblings, 0 replies; 111+ messages in thread
From: Shankar, Uma @ 2020-11-02 7:47 UTC (permalink / raw)
To: Gupta, Anshuman, intel-gfx, dri-devel
Cc: Nikula, Jani, seanpaul, Li, Juston, Gupta, Anshuman
> -----Original Message-----
> From: Anshuman Gupta <anshuman.gupta@intel.com>
> Sent: Tuesday, October 27, 2020 10:12 PM
> To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: seanpaul@chromium.org; Nikula, Jani <jani.nikula@intel.com>; C,
> Ramalingam <ramalingam.c@intel.com>; Li, Juston <juston.li@intel.com>;
> Shankar, Uma <uma.shankar@intel.com>; Gupta, Anshuman
> <anshuman.gupta@intel.com>
> Subject: [PATCH v4 07/16] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST
> support
>
> Enable HDCP 1.4 over DP MST for Gen12.
> This also enable the stream encryption support for older generations, which was
> missing earlier.
>
> v2:
> - Added debug print for stream encryption.
> - Disable the hdcp on port after disabling last stream
> encryption.
> v3:
> - Cosmetic change, removed the value less comment. [Uma]
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 43 ++++++++++++++-------
> 2 files changed, 32 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 16865b200062..f00e12fc83e8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -826,13 +826,9 @@ static struct drm_connector
> *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
> intel_attach_force_audio_property(connector);
> intel_attach_broadcast_rgb_property(connector);
>
> -
> - /* TODO: Figure out how to make HDCP work on GEN12+ */
> - if (INTEL_GEN(dev_priv) < 12) {
> - ret = intel_dp_init_hdcp(dig_port, intel_connector);
> - if (ret)
> - DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
> - }
> + ret = intel_dp_init_hdcp(dig_port, intel_connector);
> + if (ret)
> + drm_dbg_kms(&dev_priv->drm, "HDCP init failed, skipping.\n");
>
> /*
> * Reuse the prop from the SST connector because we're diff --git
> a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 0322a83c151d..937af4aeaac2 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -612,7 +612,12 @@ int intel_hdcp_auth_downstream(struct intel_connector
> *connector)
> return ret;
> }
>
> -/* Implements Part 1 of the HDCP authorization procedure */
> +/*
> + * Implements Part 1 of the HDCP authorization procedure.
> + * Authentication Part 1 steps for Multi-stream DisplayPort.
> + * Step 1. Auth Part 1 sequence on the driving MST Trasport Link.
> + * Step 2. Enable encryption for each stream that requires encryption.
> + */
> static int intel_hdcp_auth(struct intel_connector *connector) {
> struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> @@ -766,10 +771,16 @@ static int intel_hdcp_auth(struct intel_connector
> *connector)
> return -ETIMEDOUT;
> }
>
> - /*
> - * XXX: If we have MST-connected devices, we need to enable encryption
> - * on those as well.
> - */
> + /* DP MST Auth Part 1 Step 2.a and Step 2.b */
> + if (shim->stream_encryption) {
> + ret = shim->stream_encryption(dig_port, true);
> + if (ret) {
> + drm_err(&dev_priv->drm, "Failed to enable HDCP 1.4
> stream enc\n");
> + return ret;
> + }
> + drm_dbg_kms(&dev_priv->drm, "HDCP 1.4 tras %s stream
> encrypted\n",
> + transcoder_name(hdcp->stream_transcoder));
> + }
>
> if (repeater_present)
> return intel_hdcp_auth_downstream(connector);
> @@ -791,18 +802,22 @@ static int _intel_hdcp_disable(struct intel_connector
> *connector)
> drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP is being disabled...\n",
> connector->base.name, connector->base.base.id);
>
> + if (hdcp->shim->stream_encryption) {
> + ret = hdcp->shim->stream_encryption(dig_port, false);
> + if (ret) {
> + drm_err(&dev_priv->drm, "Failed to disable HDCP 1.4
> stream enc\n");
> + return ret;
> + }
> + drm_dbg_kms(&dev_priv->drm, "HDCP 1.4 trans %s stream
> encryption disabled\n",
> + transcoder_name(hdcp->stream_transcoder));
> + }
> +
> /*
> - * If there are other connectors on this port using HDCP, don't disable
> - * it. Instead, toggle the HDCP signalling off on that particular
> - * connector/pipe and exit.
> + * If there are other connectors on this port using HDCP, don't disable it.
> + * Repeat steps 1-2 for each stream that no longer requires encryption.
> */
> - if (dig_port->num_hdcp_streams > 0) {
> - ret = hdcp->shim->toggle_signalling(dig_port,
> - cpu_transcoder, false);
> - if (ret)
> - DRM_ERROR("Failed to disable HDCP signalling\n");
> + if (dig_port->num_hdcp_streams > 0)
> return ret;
> - }
>
> hdcp->hdcp_encrypted = false;
> intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port), 0);
> --
> 2.26.2
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 07/16] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support
@ 2020-11-02 7:47 ` Shankar, Uma
0 siblings, 0 replies; 111+ messages in thread
From: Shankar, Uma @ 2020-11-02 7:47 UTC (permalink / raw)
To: Gupta, Anshuman, intel-gfx, dri-devel; +Cc: Nikula, Jani, seanpaul
> -----Original Message-----
> From: Anshuman Gupta <anshuman.gupta@intel.com>
> Sent: Tuesday, October 27, 2020 10:12 PM
> To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: seanpaul@chromium.org; Nikula, Jani <jani.nikula@intel.com>; C,
> Ramalingam <ramalingam.c@intel.com>; Li, Juston <juston.li@intel.com>;
> Shankar, Uma <uma.shankar@intel.com>; Gupta, Anshuman
> <anshuman.gupta@intel.com>
> Subject: [PATCH v4 07/16] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST
> support
>
> Enable HDCP 1.4 over DP MST for Gen12.
> This also enable the stream encryption support for older generations, which was
> missing earlier.
>
> v2:
> - Added debug print for stream encryption.
> - Disable the hdcp on port after disabling last stream
> encryption.
> v3:
> - Cosmetic change, removed the value less comment. [Uma]
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 43 ++++++++++++++-------
> 2 files changed, 32 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 16865b200062..f00e12fc83e8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -826,13 +826,9 @@ static struct drm_connector
> *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
> intel_attach_force_audio_property(connector);
> intel_attach_broadcast_rgb_property(connector);
>
> -
> - /* TODO: Figure out how to make HDCP work on GEN12+ */
> - if (INTEL_GEN(dev_priv) < 12) {
> - ret = intel_dp_init_hdcp(dig_port, intel_connector);
> - if (ret)
> - DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
> - }
> + ret = intel_dp_init_hdcp(dig_port, intel_connector);
> + if (ret)
> + drm_dbg_kms(&dev_priv->drm, "HDCP init failed, skipping.\n");
>
> /*
> * Reuse the prop from the SST connector because we're diff --git
> a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 0322a83c151d..937af4aeaac2 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -612,7 +612,12 @@ int intel_hdcp_auth_downstream(struct intel_connector
> *connector)
> return ret;
> }
>
> -/* Implements Part 1 of the HDCP authorization procedure */
> +/*
> + * Implements Part 1 of the HDCP authorization procedure.
> + * Authentication Part 1 steps for Multi-stream DisplayPort.
> + * Step 1. Auth Part 1 sequence on the driving MST Trasport Link.
> + * Step 2. Enable encryption for each stream that requires encryption.
> + */
> static int intel_hdcp_auth(struct intel_connector *connector) {
> struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> @@ -766,10 +771,16 @@ static int intel_hdcp_auth(struct intel_connector
> *connector)
> return -ETIMEDOUT;
> }
>
> - /*
> - * XXX: If we have MST-connected devices, we need to enable encryption
> - * on those as well.
> - */
> + /* DP MST Auth Part 1 Step 2.a and Step 2.b */
> + if (shim->stream_encryption) {
> + ret = shim->stream_encryption(dig_port, true);
> + if (ret) {
> + drm_err(&dev_priv->drm, "Failed to enable HDCP 1.4
> stream enc\n");
> + return ret;
> + }
> + drm_dbg_kms(&dev_priv->drm, "HDCP 1.4 tras %s stream
> encrypted\n",
> + transcoder_name(hdcp->stream_transcoder));
> + }
>
> if (repeater_present)
> return intel_hdcp_auth_downstream(connector);
> @@ -791,18 +802,22 @@ static int _intel_hdcp_disable(struct intel_connector
> *connector)
> drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP is being disabled...\n",
> connector->base.name, connector->base.base.id);
>
> + if (hdcp->shim->stream_encryption) {
> + ret = hdcp->shim->stream_encryption(dig_port, false);
> + if (ret) {
> + drm_err(&dev_priv->drm, "Failed to disable HDCP 1.4
> stream enc\n");
> + return ret;
> + }
> + drm_dbg_kms(&dev_priv->drm, "HDCP 1.4 trans %s stream
> encryption disabled\n",
> + transcoder_name(hdcp->stream_transcoder));
> + }
> +
> /*
> - * If there are other connectors on this port using HDCP, don't disable
> - * it. Instead, toggle the HDCP signalling off on that particular
> - * connector/pipe and exit.
> + * If there are other connectors on this port using HDCP, don't disable it.
> + * Repeat steps 1-2 for each stream that no longer requires encryption.
> */
> - if (dig_port->num_hdcp_streams > 0) {
> - ret = hdcp->shim->toggle_signalling(dig_port,
> - cpu_transcoder, false);
> - if (ret)
> - DRM_ERROR("Failed to disable HDCP signalling\n");
> + if (dig_port->num_hdcp_streams > 0)
> return ret;
> - }
>
> hdcp->hdcp_encrypted = false;
> intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port), 0);
> --
> 2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v4 07/16] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
@ 2020-11-05 15:41 ` Ramalingam C
-1 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-05 15:41 UTC (permalink / raw)
To: Anshuman Gupta
Cc: jani.nikula, intel-gfx, dri-devel, uma.shankar, seanpaul, juston.li
On 2020-10-27 at 22:11:59 +0530, Anshuman Gupta wrote:
> Enable HDCP 1.4 over DP MST for Gen12.
> This also enable the stream encryption support for
> older generations, which was missing earlier.
It will be nice to have them in separate patches.
-Ram
>
> v2:
> - Added debug print for stream encryption.
> - Disable the hdcp on port after disabling last stream
> encryption.
> v3:
> - Cosmetic change, removed the value less comment. [Uma]
>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 43 ++++++++++++++-------
> 2 files changed, 32 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 16865b200062..f00e12fc83e8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -826,13 +826,9 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
> intel_attach_force_audio_property(connector);
> intel_attach_broadcast_rgb_property(connector);
>
> -
> - /* TODO: Figure out how to make HDCP work on GEN12+ */
> - if (INTEL_GEN(dev_priv) < 12) {
> - ret = intel_dp_init_hdcp(dig_port, intel_connector);
> - if (ret)
> - DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
> - }
> + ret = intel_dp_init_hdcp(dig_port, intel_connector);
> + if (ret)
> + drm_dbg_kms(&dev_priv->drm, "HDCP init failed, skipping.\n");
>
> /*
> * Reuse the prop from the SST connector because we're
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 0322a83c151d..937af4aeaac2 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -612,7 +612,12 @@ int intel_hdcp_auth_downstream(struct intel_connector *connector)
> return ret;
> }
>
> -/* Implements Part 1 of the HDCP authorization procedure */
> +/*
> + * Implements Part 1 of the HDCP authorization procedure.
> + * Authentication Part 1 steps for Multi-stream DisplayPort.
> + * Step 1. Auth Part 1 sequence on the driving MST Trasport Link.
> + * Step 2. Enable encryption for each stream that requires encryption.
> + */
> static int intel_hdcp_auth(struct intel_connector *connector)
> {
> struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> @@ -766,10 +771,16 @@ static int intel_hdcp_auth(struct intel_connector *connector)
> return -ETIMEDOUT;
> }
>
> - /*
> - * XXX: If we have MST-connected devices, we need to enable encryption
> - * on those as well.
> - */
> + /* DP MST Auth Part 1 Step 2.a and Step 2.b */
> + if (shim->stream_encryption) {
> + ret = shim->stream_encryption(dig_port, true);
> + if (ret) {
> + drm_err(&dev_priv->drm, "Failed to enable HDCP 1.4 stream enc\n");
> + return ret;
> + }
> + drm_dbg_kms(&dev_priv->drm, "HDCP 1.4 tras %s stream encrypted\n",
> + transcoder_name(hdcp->stream_transcoder));
> + }
>
> if (repeater_present)
> return intel_hdcp_auth_downstream(connector);
> @@ -791,18 +802,22 @@ static int _intel_hdcp_disable(struct intel_connector *connector)
> drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP is being disabled...\n",
> connector->base.name, connector->base.base.id);
>
> + if (hdcp->shim->stream_encryption) {
> + ret = hdcp->shim->stream_encryption(dig_port, false);
> + if (ret) {
> + drm_err(&dev_priv->drm, "Failed to disable HDCP 1.4 stream enc\n");
> + return ret;
> + }
> + drm_dbg_kms(&dev_priv->drm, "HDCP 1.4 trans %s stream encryption disabled\n",
> + transcoder_name(hdcp->stream_transcoder));
> + }
> +
> /*
> - * If there are other connectors on this port using HDCP, don't disable
> - * it. Instead, toggle the HDCP signalling off on that particular
> - * connector/pipe and exit.
> + * If there are other connectors on this port using HDCP, don't disable it.
> + * Repeat steps 1-2 for each stream that no longer requires encryption.
> */
> - if (dig_port->num_hdcp_streams > 0) {
> - ret = hdcp->shim->toggle_signalling(dig_port,
> - cpu_transcoder, false);
> - if (ret)
> - DRM_ERROR("Failed to disable HDCP signalling\n");
> + if (dig_port->num_hdcp_streams > 0)
> return ret;
> - }
>
> hdcp->hdcp_encrypted = false;
> intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port), 0);
> --
> 2.26.2
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 07/16] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support
@ 2020-11-05 15:41 ` Ramalingam C
0 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-05 15:41 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: jani.nikula, intel-gfx, dri-devel, seanpaul
On 2020-10-27 at 22:11:59 +0530, Anshuman Gupta wrote:
> Enable HDCP 1.4 over DP MST for Gen12.
> This also enable the stream encryption support for
> older generations, which was missing earlier.
It will be nice to have them in separate patches.
-Ram
>
> v2:
> - Added debug print for stream encryption.
> - Disable the hdcp on port after disabling last stream
> encryption.
> v3:
> - Cosmetic change, removed the value less comment. [Uma]
>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 43 ++++++++++++++-------
> 2 files changed, 32 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 16865b200062..f00e12fc83e8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -826,13 +826,9 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
> intel_attach_force_audio_property(connector);
> intel_attach_broadcast_rgb_property(connector);
>
> -
> - /* TODO: Figure out how to make HDCP work on GEN12+ */
> - if (INTEL_GEN(dev_priv) < 12) {
> - ret = intel_dp_init_hdcp(dig_port, intel_connector);
> - if (ret)
> - DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
> - }
> + ret = intel_dp_init_hdcp(dig_port, intel_connector);
> + if (ret)
> + drm_dbg_kms(&dev_priv->drm, "HDCP init failed, skipping.\n");
>
> /*
> * Reuse the prop from the SST connector because we're
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 0322a83c151d..937af4aeaac2 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -612,7 +612,12 @@ int intel_hdcp_auth_downstream(struct intel_connector *connector)
> return ret;
> }
>
> -/* Implements Part 1 of the HDCP authorization procedure */
> +/*
> + * Implements Part 1 of the HDCP authorization procedure.
> + * Authentication Part 1 steps for Multi-stream DisplayPort.
> + * Step 1. Auth Part 1 sequence on the driving MST Trasport Link.
> + * Step 2. Enable encryption for each stream that requires encryption.
> + */
> static int intel_hdcp_auth(struct intel_connector *connector)
> {
> struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> @@ -766,10 +771,16 @@ static int intel_hdcp_auth(struct intel_connector *connector)
> return -ETIMEDOUT;
> }
>
> - /*
> - * XXX: If we have MST-connected devices, we need to enable encryption
> - * on those as well.
> - */
> + /* DP MST Auth Part 1 Step 2.a and Step 2.b */
> + if (shim->stream_encryption) {
> + ret = shim->stream_encryption(dig_port, true);
> + if (ret) {
> + drm_err(&dev_priv->drm, "Failed to enable HDCP 1.4 stream enc\n");
> + return ret;
> + }
> + drm_dbg_kms(&dev_priv->drm, "HDCP 1.4 tras %s stream encrypted\n",
> + transcoder_name(hdcp->stream_transcoder));
> + }
>
> if (repeater_present)
> return intel_hdcp_auth_downstream(connector);
> @@ -791,18 +802,22 @@ static int _intel_hdcp_disable(struct intel_connector *connector)
> drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP is being disabled...\n",
> connector->base.name, connector->base.base.id);
>
> + if (hdcp->shim->stream_encryption) {
> + ret = hdcp->shim->stream_encryption(dig_port, false);
> + if (ret) {
> + drm_err(&dev_priv->drm, "Failed to disable HDCP 1.4 stream enc\n");
> + return ret;
> + }
> + drm_dbg_kms(&dev_priv->drm, "HDCP 1.4 trans %s stream encryption disabled\n",
> + transcoder_name(hdcp->stream_transcoder));
> + }
> +
> /*
> - * If there are other connectors on this port using HDCP, don't disable
> - * it. Instead, toggle the HDCP signalling off on that particular
> - * connector/pipe and exit.
> + * If there are other connectors on this port using HDCP, don't disable it.
> + * Repeat steps 1-2 for each stream that no longer requires encryption.
> */
> - if (dig_port->num_hdcp_streams > 0) {
> - ret = hdcp->shim->toggle_signalling(dig_port,
> - cpu_transcoder, false);
> - if (ret)
> - DRM_ERROR("Failed to disable HDCP signalling\n");
> + if (dig_port->num_hdcp_streams > 0)
> return ret;
> - }
>
> hdcp->hdcp_encrypted = false;
> intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port), 0);
> --
> 2.26.2
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [PATCH v4 07/16] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support
2020-11-05 15:41 ` [Intel-gfx] " Ramalingam C
@ 2020-11-06 6:36 ` Anshuman Gupta
-1 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-11-06 6:36 UTC (permalink / raw)
To: Ramalingam C
Cc: jani.nikula, intel-gfx, dri-devel, uma.shankar, seanpaul, juston.li
On 2020-11-05 at 21:11:52 +0530, Ramalingam C wrote:
> On 2020-10-27 at 22:11:59 +0530, Anshuman Gupta wrote:
> > Enable HDCP 1.4 over DP MST for Gen12.
> > This also enable the stream encryption support for
> > older generations, which was missing earlier.
> It will be nice to have them in separate patches.
Thanks for review comment.
Sure i will refactor a separate patch for this.
Thanks,
Anshuman Gupta
>
> -Ram
> >
> > v2:
> > - Added debug print for stream encryption.
> > - Disable the hdcp on port after disabling last stream
> > encryption.
> > v3:
> > - Cosmetic change, removed the value less comment. [Uma]
> >
> > Cc: Ramalingam C <ramalingam.c@intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++---
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 43 ++++++++++++++-------
> > 2 files changed, 32 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index 16865b200062..f00e12fc83e8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -826,13 +826,9 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
> > intel_attach_force_audio_property(connector);
> > intel_attach_broadcast_rgb_property(connector);
> >
> > -
> > - /* TODO: Figure out how to make HDCP work on GEN12+ */
> > - if (INTEL_GEN(dev_priv) < 12) {
> > - ret = intel_dp_init_hdcp(dig_port, intel_connector);
> > - if (ret)
> > - DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
> > - }
> > + ret = intel_dp_init_hdcp(dig_port, intel_connector);
> > + if (ret)
> > + drm_dbg_kms(&dev_priv->drm, "HDCP init failed, skipping.\n");
> >
> > /*
> > * Reuse the prop from the SST connector because we're
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index 0322a83c151d..937af4aeaac2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -612,7 +612,12 @@ int intel_hdcp_auth_downstream(struct intel_connector *connector)
> > return ret;
> > }
> >
> > -/* Implements Part 1 of the HDCP authorization procedure */
> > +/*
> > + * Implements Part 1 of the HDCP authorization procedure.
> > + * Authentication Part 1 steps for Multi-stream DisplayPort.
> > + * Step 1. Auth Part 1 sequence on the driving MST Trasport Link.
> > + * Step 2. Enable encryption for each stream that requires encryption.
> > + */
> > static int intel_hdcp_auth(struct intel_connector *connector)
> > {
> > struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> > @@ -766,10 +771,16 @@ static int intel_hdcp_auth(struct intel_connector *connector)
> > return -ETIMEDOUT;
> > }
> >
> > - /*
> > - * XXX: If we have MST-connected devices, we need to enable encryption
> > - * on those as well.
> > - */
> > + /* DP MST Auth Part 1 Step 2.a and Step 2.b */
> > + if (shim->stream_encryption) {
> > + ret = shim->stream_encryption(dig_port, true);
> > + if (ret) {
> > + drm_err(&dev_priv->drm, "Failed to enable HDCP 1.4 stream enc\n");
> > + return ret;
> > + }
> > + drm_dbg_kms(&dev_priv->drm, "HDCP 1.4 tras %s stream encrypted\n",
> > + transcoder_name(hdcp->stream_transcoder));
> > + }
> >
> > if (repeater_present)
> > return intel_hdcp_auth_downstream(connector);
> > @@ -791,18 +802,22 @@ static int _intel_hdcp_disable(struct intel_connector *connector)
> > drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP is being disabled...\n",
> > connector->base.name, connector->base.base.id);
> >
> > + if (hdcp->shim->stream_encryption) {
> > + ret = hdcp->shim->stream_encryption(dig_port, false);
> > + if (ret) {
> > + drm_err(&dev_priv->drm, "Failed to disable HDCP 1.4 stream enc\n");
> > + return ret;
> > + }
> > + drm_dbg_kms(&dev_priv->drm, "HDCP 1.4 trans %s stream encryption disabled\n",
> > + transcoder_name(hdcp->stream_transcoder));
> > + }
> > +
> > /*
> > - * If there are other connectors on this port using HDCP, don't disable
> > - * it. Instead, toggle the HDCP signalling off on that particular
> > - * connector/pipe and exit.
> > + * If there are other connectors on this port using HDCP, don't disable it.
> > + * Repeat steps 1-2 for each stream that no longer requires encryption.
> > */
> > - if (dig_port->num_hdcp_streams > 0) {
> > - ret = hdcp->shim->toggle_signalling(dig_port,
> > - cpu_transcoder, false);
> > - if (ret)
> > - DRM_ERROR("Failed to disable HDCP signalling\n");
> > + if (dig_port->num_hdcp_streams > 0)
> > return ret;
> > - }
> >
> > hdcp->hdcp_encrypted = false;
> > intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port), 0);
> > --
> > 2.26.2
> >
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 07/16] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support
@ 2020-11-06 6:36 ` Anshuman Gupta
0 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-11-06 6:36 UTC (permalink / raw)
To: Ramalingam C; +Cc: jani.nikula, intel-gfx, dri-devel, seanpaul
On 2020-11-05 at 21:11:52 +0530, Ramalingam C wrote:
> On 2020-10-27 at 22:11:59 +0530, Anshuman Gupta wrote:
> > Enable HDCP 1.4 over DP MST for Gen12.
> > This also enable the stream encryption support for
> > older generations, which was missing earlier.
> It will be nice to have them in separate patches.
Thanks for review comment.
Sure i will refactor a separate patch for this.
Thanks,
Anshuman Gupta
>
> -Ram
> >
> > v2:
> > - Added debug print for stream encryption.
> > - Disable the hdcp on port after disabling last stream
> > encryption.
> > v3:
> > - Cosmetic change, removed the value less comment. [Uma]
> >
> > Cc: Ramalingam C <ramalingam.c@intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++---
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 43 ++++++++++++++-------
> > 2 files changed, 32 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index 16865b200062..f00e12fc83e8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -826,13 +826,9 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
> > intel_attach_force_audio_property(connector);
> > intel_attach_broadcast_rgb_property(connector);
> >
> > -
> > - /* TODO: Figure out how to make HDCP work on GEN12+ */
> > - if (INTEL_GEN(dev_priv) < 12) {
> > - ret = intel_dp_init_hdcp(dig_port, intel_connector);
> > - if (ret)
> > - DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
> > - }
> > + ret = intel_dp_init_hdcp(dig_port, intel_connector);
> > + if (ret)
> > + drm_dbg_kms(&dev_priv->drm, "HDCP init failed, skipping.\n");
> >
> > /*
> > * Reuse the prop from the SST connector because we're
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index 0322a83c151d..937af4aeaac2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -612,7 +612,12 @@ int intel_hdcp_auth_downstream(struct intel_connector *connector)
> > return ret;
> > }
> >
> > -/* Implements Part 1 of the HDCP authorization procedure */
> > +/*
> > + * Implements Part 1 of the HDCP authorization procedure.
> > + * Authentication Part 1 steps for Multi-stream DisplayPort.
> > + * Step 1. Auth Part 1 sequence on the driving MST Trasport Link.
> > + * Step 2. Enable encryption for each stream that requires encryption.
> > + */
> > static int intel_hdcp_auth(struct intel_connector *connector)
> > {
> > struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> > @@ -766,10 +771,16 @@ static int intel_hdcp_auth(struct intel_connector *connector)
> > return -ETIMEDOUT;
> > }
> >
> > - /*
> > - * XXX: If we have MST-connected devices, we need to enable encryption
> > - * on those as well.
> > - */
> > + /* DP MST Auth Part 1 Step 2.a and Step 2.b */
> > + if (shim->stream_encryption) {
> > + ret = shim->stream_encryption(dig_port, true);
> > + if (ret) {
> > + drm_err(&dev_priv->drm, "Failed to enable HDCP 1.4 stream enc\n");
> > + return ret;
> > + }
> > + drm_dbg_kms(&dev_priv->drm, "HDCP 1.4 tras %s stream encrypted\n",
> > + transcoder_name(hdcp->stream_transcoder));
> > + }
> >
> > if (repeater_present)
> > return intel_hdcp_auth_downstream(connector);
> > @@ -791,18 +802,22 @@ static int _intel_hdcp_disable(struct intel_connector *connector)
> > drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP is being disabled...\n",
> > connector->base.name, connector->base.base.id);
> >
> > + if (hdcp->shim->stream_encryption) {
> > + ret = hdcp->shim->stream_encryption(dig_port, false);
> > + if (ret) {
> > + drm_err(&dev_priv->drm, "Failed to disable HDCP 1.4 stream enc\n");
> > + return ret;
> > + }
> > + drm_dbg_kms(&dev_priv->drm, "HDCP 1.4 trans %s stream encryption disabled\n",
> > + transcoder_name(hdcp->stream_transcoder));
> > + }
> > +
> > /*
> > - * If there are other connectors on this port using HDCP, don't disable
> > - * it. Instead, toggle the HDCP signalling off on that particular
> > - * connector/pipe and exit.
> > + * If there are other connectors on this port using HDCP, don't disable it.
> > + * Repeat steps 1-2 for each stream that no longer requires encryption.
> > */
> > - if (dig_port->num_hdcp_streams > 0) {
> > - ret = hdcp->shim->toggle_signalling(dig_port,
> > - cpu_transcoder, false);
> > - if (ret)
> > - DRM_ERROR("Failed to disable HDCP signalling\n");
> > + if (dig_port->num_hdcp_streams > 0)
> > return ret;
> > - }
> >
> > hdcp->hdcp_encrypted = false;
> > intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port), 0);
> > --
> > 2.26.2
> >
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread
* [PATCH v4 08/16] drm/i915/hdcp: Pass dig_port to intel_hdcp_init
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
@ 2020-10-27 16:42 ` Anshuman Gupta
-1 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:42 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: jani.nikula, uma.shankar, seanpaul, Anshuman Gupta, juston.li
Pass dig_port as an argument to intel_hdcp_init()
and intel_hdcp2_init().
This will be required for HDCP 2.2 stream encryption.
Cc: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 4 ++--
drivers/gpu/drm/i915/display/intel_hdcp.c | 12 +++++++-----
drivers/gpu/drm/i915/display/intel_hdcp.h | 4 +++-
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
4 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 6dcbfaffd2c5..591b68e5de48 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -751,10 +751,10 @@ int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
return 0;
if (intel_connector->mst_port)
- return intel_hdcp_init(intel_connector, port,
+ return intel_hdcp_init(intel_connector, dig_port,
&intel_dp_mst_hdcp_shim);
else if (!intel_dp_is_edp(intel_dp))
- return intel_hdcp_init(intel_connector, port,
+ return intel_hdcp_init(intel_connector, dig_port,
&intel_dp_hdcp_shim);
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 937af4aeaac2..b0f47687bc59 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1982,12 +1982,13 @@ static enum mei_fw_tc intel_get_mei_fw_tc(enum transcoder cpu_transcoder)
}
static int initialize_hdcp_port_data(struct intel_connector *connector,
- enum port port,
+ struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *shim)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
struct hdcp_port_data *data = &hdcp->port_data;
+ enum port port = dig_port->base.port;
if (INTEL_GEN(dev_priv) < 12)
data->fw_ddi = intel_get_mei_fw_ddi_index(port);
@@ -2060,14 +2061,15 @@ void intel_hdcp_component_init(struct drm_i915_private *dev_priv)
}
}
-static void intel_hdcp2_init(struct intel_connector *connector, enum port port,
+static void intel_hdcp2_init(struct intel_connector *connector,
+ struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *shim)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
int ret;
- ret = initialize_hdcp_port_data(connector, port, shim);
+ ret = initialize_hdcp_port_data(connector, dig_port, shim);
if (ret) {
drm_dbg_kms(&i915->drm, "Mei hdcp data init failed\n");
return;
@@ -2077,7 +2079,7 @@ static void intel_hdcp2_init(struct intel_connector *connector, enum port port,
}
int intel_hdcp_init(struct intel_connector *connector,
- enum port port,
+ struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *shim)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
@@ -2088,7 +2090,7 @@ int intel_hdcp_init(struct intel_connector *connector,
return -EINVAL;
if (is_hdcp2_supported(dev_priv) && !connector->mst_port)
- intel_hdcp2_init(connector, port, shim);
+ intel_hdcp2_init(connector, dig_port, shim);
ret =
drm_connector_attach_content_protection_property(&connector->base,
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h
index b912a3a0f5b8..8f53b0c7fe5c 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.h
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
@@ -18,13 +18,15 @@ struct intel_connector;
struct intel_crtc_state;
struct intel_encoder;
struct intel_hdcp_shim;
+struct intel_digital_port;
enum port;
enum transcoder;
void intel_hdcp_atomic_check(struct drm_connector *connector,
struct drm_connector_state *old_state,
struct drm_connector_state *new_state);
-int intel_hdcp_init(struct intel_connector *connector, enum port port,
+int intel_hdcp_init(struct intel_connector *connector,
+ struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *hdcp_shim);
int intel_hdcp_enable(struct intel_connector *connector,
const struct intel_crtc_state *pipe_config, u8 content_type);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index f58469226694..0788de04711b 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3302,7 +3302,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
intel_hdmi->attached_connector = intel_connector;
if (is_hdcp_supported(dev_priv, port)) {
- int ret = intel_hdcp_init(intel_connector, port,
+ int ret = intel_hdcp_init(intel_connector, dig_port,
&intel_hdmi_hdcp_shim);
if (ret)
drm_dbg_kms(&dev_priv->drm,
--
2.26.2
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 111+ messages in thread* [Intel-gfx] [PATCH v4 08/16] drm/i915/hdcp: Pass dig_port to intel_hdcp_init
@ 2020-10-27 16:42 ` Anshuman Gupta
0 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:42 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula, seanpaul
Pass dig_port as an argument to intel_hdcp_init()
and intel_hdcp2_init().
This will be required for HDCP 2.2 stream encryption.
Cc: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 4 ++--
drivers/gpu/drm/i915/display/intel_hdcp.c | 12 +++++++-----
drivers/gpu/drm/i915/display/intel_hdcp.h | 4 +++-
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
4 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 6dcbfaffd2c5..591b68e5de48 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -751,10 +751,10 @@ int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
return 0;
if (intel_connector->mst_port)
- return intel_hdcp_init(intel_connector, port,
+ return intel_hdcp_init(intel_connector, dig_port,
&intel_dp_mst_hdcp_shim);
else if (!intel_dp_is_edp(intel_dp))
- return intel_hdcp_init(intel_connector, port,
+ return intel_hdcp_init(intel_connector, dig_port,
&intel_dp_hdcp_shim);
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 937af4aeaac2..b0f47687bc59 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1982,12 +1982,13 @@ static enum mei_fw_tc intel_get_mei_fw_tc(enum transcoder cpu_transcoder)
}
static int initialize_hdcp_port_data(struct intel_connector *connector,
- enum port port,
+ struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *shim)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
struct hdcp_port_data *data = &hdcp->port_data;
+ enum port port = dig_port->base.port;
if (INTEL_GEN(dev_priv) < 12)
data->fw_ddi = intel_get_mei_fw_ddi_index(port);
@@ -2060,14 +2061,15 @@ void intel_hdcp_component_init(struct drm_i915_private *dev_priv)
}
}
-static void intel_hdcp2_init(struct intel_connector *connector, enum port port,
+static void intel_hdcp2_init(struct intel_connector *connector,
+ struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *shim)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
int ret;
- ret = initialize_hdcp_port_data(connector, port, shim);
+ ret = initialize_hdcp_port_data(connector, dig_port, shim);
if (ret) {
drm_dbg_kms(&i915->drm, "Mei hdcp data init failed\n");
return;
@@ -2077,7 +2079,7 @@ static void intel_hdcp2_init(struct intel_connector *connector, enum port port,
}
int intel_hdcp_init(struct intel_connector *connector,
- enum port port,
+ struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *shim)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
@@ -2088,7 +2090,7 @@ int intel_hdcp_init(struct intel_connector *connector,
return -EINVAL;
if (is_hdcp2_supported(dev_priv) && !connector->mst_port)
- intel_hdcp2_init(connector, port, shim);
+ intel_hdcp2_init(connector, dig_port, shim);
ret =
drm_connector_attach_content_protection_property(&connector->base,
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h
index b912a3a0f5b8..8f53b0c7fe5c 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.h
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
@@ -18,13 +18,15 @@ struct intel_connector;
struct intel_crtc_state;
struct intel_encoder;
struct intel_hdcp_shim;
+struct intel_digital_port;
enum port;
enum transcoder;
void intel_hdcp_atomic_check(struct drm_connector *connector,
struct drm_connector_state *old_state,
struct drm_connector_state *new_state);
-int intel_hdcp_init(struct intel_connector *connector, enum port port,
+int intel_hdcp_init(struct intel_connector *connector,
+ struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *hdcp_shim);
int intel_hdcp_enable(struct intel_connector *connector,
const struct intel_crtc_state *pipe_config, u8 content_type);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index f58469226694..0788de04711b 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3302,7 +3302,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
intel_hdmi->attached_connector = intel_connector;
if (is_hdcp_supported(dev_priv, port)) {
- int ret = intel_hdcp_init(intel_connector, port,
+ int ret = intel_hdcp_init(intel_connector, dig_port,
&intel_hdmi_hdcp_shim);
if (ret)
drm_dbg_kms(&dev_priv->drm,
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 111+ messages in thread* Re: [PATCH v4 08/16] drm/i915/hdcp: Pass dig_port to intel_hdcp_init
2020-10-27 16:42 ` [Intel-gfx] " Anshuman Gupta
@ 2020-11-05 16:39 ` Ramalingam C
-1 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-05 16:39 UTC (permalink / raw)
To: Anshuman Gupta
Cc: jani.nikula, intel-gfx, dri-devel, uma.shankar, seanpaul, juston.li
On 2020-10-27 at 22:12:00 +0530, Anshuman Gupta wrote:
> Pass dig_port as an argument to intel_hdcp_init()
> and intel_hdcp2_init().
> This will be required for HDCP 2.2 stream encryption.
>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 4 ++--
> drivers/gpu/drm/i915/display/intel_hdcp.c | 12 +++++++-----
> drivers/gpu/drm/i915/display/intel_hdcp.h | 4 +++-
> drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
> 4 files changed, 13 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> index 6dcbfaffd2c5..591b68e5de48 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> @@ -751,10 +751,10 @@ int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
> return 0;
>
> if (intel_connector->mst_port)
> - return intel_hdcp_init(intel_connector, port,
> + return intel_hdcp_init(intel_connector, dig_port,
cant we retrieve the dig_port from connector?
-Ram
> &intel_dp_mst_hdcp_shim);
> else if (!intel_dp_is_edp(intel_dp))
> - return intel_hdcp_init(intel_connector, port,
> + return intel_hdcp_init(intel_connector, dig_port,
> &intel_dp_hdcp_shim);
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 937af4aeaac2..b0f47687bc59 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -1982,12 +1982,13 @@ static enum mei_fw_tc intel_get_mei_fw_tc(enum transcoder cpu_transcoder)
> }
>
> static int initialize_hdcp_port_data(struct intel_connector *connector,
> - enum port port,
> + struct intel_digital_port *dig_port,
> const struct intel_hdcp_shim *shim)
> {
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct intel_hdcp *hdcp = &connector->hdcp;
> struct hdcp_port_data *data = &hdcp->port_data;
> + enum port port = dig_port->base.port;
>
> if (INTEL_GEN(dev_priv) < 12)
> data->fw_ddi = intel_get_mei_fw_ddi_index(port);
> @@ -2060,14 +2061,15 @@ void intel_hdcp_component_init(struct drm_i915_private *dev_priv)
> }
> }
>
> -static void intel_hdcp2_init(struct intel_connector *connector, enum port port,
> +static void intel_hdcp2_init(struct intel_connector *connector,
> + struct intel_digital_port *dig_port,
> const struct intel_hdcp_shim *shim)
> {
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> struct intel_hdcp *hdcp = &connector->hdcp;
> int ret;
>
> - ret = initialize_hdcp_port_data(connector, port, shim);
> + ret = initialize_hdcp_port_data(connector, dig_port, shim);
> if (ret) {
> drm_dbg_kms(&i915->drm, "Mei hdcp data init failed\n");
> return;
> @@ -2077,7 +2079,7 @@ static void intel_hdcp2_init(struct intel_connector *connector, enum port port,
> }
>
> int intel_hdcp_init(struct intel_connector *connector,
> - enum port port,
> + struct intel_digital_port *dig_port,
> const struct intel_hdcp_shim *shim)
> {
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> @@ -2088,7 +2090,7 @@ int intel_hdcp_init(struct intel_connector *connector,
> return -EINVAL;
>
> if (is_hdcp2_supported(dev_priv) && !connector->mst_port)
> - intel_hdcp2_init(connector, port, shim);
> + intel_hdcp2_init(connector, dig_port, shim);
>
> ret =
> drm_connector_attach_content_protection_property(&connector->base,
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h
> index b912a3a0f5b8..8f53b0c7fe5c 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.h
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
> @@ -18,13 +18,15 @@ struct intel_connector;
> struct intel_crtc_state;
> struct intel_encoder;
> struct intel_hdcp_shim;
> +struct intel_digital_port;
> enum port;
> enum transcoder;
>
> void intel_hdcp_atomic_check(struct drm_connector *connector,
> struct drm_connector_state *old_state,
> struct drm_connector_state *new_state);
> -int intel_hdcp_init(struct intel_connector *connector, enum port port,
> +int intel_hdcp_init(struct intel_connector *connector,
> + struct intel_digital_port *dig_port,
> const struct intel_hdcp_shim *hdcp_shim);
> int intel_hdcp_enable(struct intel_connector *connector,
> const struct intel_crtc_state *pipe_config, u8 content_type);
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index f58469226694..0788de04711b 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -3302,7 +3302,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
> intel_hdmi->attached_connector = intel_connector;
>
> if (is_hdcp_supported(dev_priv, port)) {
> - int ret = intel_hdcp_init(intel_connector, port,
> + int ret = intel_hdcp_init(intel_connector, dig_port,
> &intel_hdmi_hdcp_shim);
> if (ret)
> drm_dbg_kms(&dev_priv->drm,
> --
> 2.26.2
>
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 08/16] drm/i915/hdcp: Pass dig_port to intel_hdcp_init
@ 2020-11-05 16:39 ` Ramalingam C
0 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-05 16:39 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: jani.nikula, intel-gfx, dri-devel, seanpaul
On 2020-10-27 at 22:12:00 +0530, Anshuman Gupta wrote:
> Pass dig_port as an argument to intel_hdcp_init()
> and intel_hdcp2_init().
> This will be required for HDCP 2.2 stream encryption.
>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 4 ++--
> drivers/gpu/drm/i915/display/intel_hdcp.c | 12 +++++++-----
> drivers/gpu/drm/i915/display/intel_hdcp.h | 4 +++-
> drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
> 4 files changed, 13 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> index 6dcbfaffd2c5..591b68e5de48 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> @@ -751,10 +751,10 @@ int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
> return 0;
>
> if (intel_connector->mst_port)
> - return intel_hdcp_init(intel_connector, port,
> + return intel_hdcp_init(intel_connector, dig_port,
cant we retrieve the dig_port from connector?
-Ram
> &intel_dp_mst_hdcp_shim);
> else if (!intel_dp_is_edp(intel_dp))
> - return intel_hdcp_init(intel_connector, port,
> + return intel_hdcp_init(intel_connector, dig_port,
> &intel_dp_hdcp_shim);
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 937af4aeaac2..b0f47687bc59 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -1982,12 +1982,13 @@ static enum mei_fw_tc intel_get_mei_fw_tc(enum transcoder cpu_transcoder)
> }
>
> static int initialize_hdcp_port_data(struct intel_connector *connector,
> - enum port port,
> + struct intel_digital_port *dig_port,
> const struct intel_hdcp_shim *shim)
> {
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct intel_hdcp *hdcp = &connector->hdcp;
> struct hdcp_port_data *data = &hdcp->port_data;
> + enum port port = dig_port->base.port;
>
> if (INTEL_GEN(dev_priv) < 12)
> data->fw_ddi = intel_get_mei_fw_ddi_index(port);
> @@ -2060,14 +2061,15 @@ void intel_hdcp_component_init(struct drm_i915_private *dev_priv)
> }
> }
>
> -static void intel_hdcp2_init(struct intel_connector *connector, enum port port,
> +static void intel_hdcp2_init(struct intel_connector *connector,
> + struct intel_digital_port *dig_port,
> const struct intel_hdcp_shim *shim)
> {
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> struct intel_hdcp *hdcp = &connector->hdcp;
> int ret;
>
> - ret = initialize_hdcp_port_data(connector, port, shim);
> + ret = initialize_hdcp_port_data(connector, dig_port, shim);
> if (ret) {
> drm_dbg_kms(&i915->drm, "Mei hdcp data init failed\n");
> return;
> @@ -2077,7 +2079,7 @@ static void intel_hdcp2_init(struct intel_connector *connector, enum port port,
> }
>
> int intel_hdcp_init(struct intel_connector *connector,
> - enum port port,
> + struct intel_digital_port *dig_port,
> const struct intel_hdcp_shim *shim)
> {
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> @@ -2088,7 +2090,7 @@ int intel_hdcp_init(struct intel_connector *connector,
> return -EINVAL;
>
> if (is_hdcp2_supported(dev_priv) && !connector->mst_port)
> - intel_hdcp2_init(connector, port, shim);
> + intel_hdcp2_init(connector, dig_port, shim);
>
> ret =
> drm_connector_attach_content_protection_property(&connector->base,
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h
> index b912a3a0f5b8..8f53b0c7fe5c 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.h
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
> @@ -18,13 +18,15 @@ struct intel_connector;
> struct intel_crtc_state;
> struct intel_encoder;
> struct intel_hdcp_shim;
> +struct intel_digital_port;
> enum port;
> enum transcoder;
>
> void intel_hdcp_atomic_check(struct drm_connector *connector,
> struct drm_connector_state *old_state,
> struct drm_connector_state *new_state);
> -int intel_hdcp_init(struct intel_connector *connector, enum port port,
> +int intel_hdcp_init(struct intel_connector *connector,
> + struct intel_digital_port *dig_port,
> const struct intel_hdcp_shim *hdcp_shim);
> int intel_hdcp_enable(struct intel_connector *connector,
> const struct intel_crtc_state *pipe_config, u8 content_type);
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index f58469226694..0788de04711b 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -3302,7 +3302,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
> intel_hdmi->attached_connector = intel_connector;
>
> if (is_hdcp_supported(dev_priv, port)) {
> - int ret = intel_hdcp_init(intel_connector, port,
> + int ret = intel_hdcp_init(intel_connector, dig_port,
> &intel_hdmi_hdcp_shim);
> if (ret)
> drm_dbg_kms(&dev_priv->drm,
> --
> 2.26.2
>
_______________________________________________
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^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [PATCH v4 08/16] drm/i915/hdcp: Pass dig_port to intel_hdcp_init
2020-11-05 16:39 ` [Intel-gfx] " Ramalingam C
@ 2020-11-06 4:50 ` Anshuman Gupta
-1 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-11-06 4:50 UTC (permalink / raw)
To: Ramalingam C
Cc: jani.nikula, intel-gfx, dri-devel, uma.shankar, seanpaul, juston.li
On 2020-11-05 at 22:09:12 +0530, Ramalingam C wrote:
> On 2020-10-27 at 22:12:00 +0530, Anshuman Gupta wrote:
> > Pass dig_port as an argument to intel_hdcp_init()
> > and intel_hdcp2_init().
> > This will be required for HDCP 2.2 stream encryption.
> >
> > Cc: Ramalingam C <ramalingam.c@intel.com>
> > Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 4 ++--
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 12 +++++++-----
> > drivers/gpu/drm/i915/display/intel_hdcp.h | 4 +++-
> > drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
> > 4 files changed, 13 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > index 6dcbfaffd2c5..591b68e5de48 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > @@ -751,10 +751,10 @@ int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
> > return 0;
> >
> > if (intel_connector->mst_port)
> > - return intel_hdcp_init(intel_connector, port,
> > + return intel_hdcp_init(intel_connector, dig_port,
> cant we retrieve the dig_port from connector?
No, actually intel_hdcp_init get called for DP MST in atomic check phase,
in atomic check phase DP MST connector->encoder is not initialize yet,
it initialize with DP MST encoder in commit phase.
so using intel_attached_dig_port(connector) results in OOPS in intel_hdcp_init().
Thanks,
Anshuman Gupta.
>
> -Ram
> > &intel_dp_mst_hdcp_shim);
> > else if (!intel_dp_is_edp(intel_dp))
> > - return intel_hdcp_init(intel_connector, port,
> > + return intel_hdcp_init(intel_connector, dig_port,
> > &intel_dp_hdcp_shim);
> >
> > return 0;
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index 937af4aeaac2..b0f47687bc59 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -1982,12 +1982,13 @@ static enum mei_fw_tc intel_get_mei_fw_tc(enum transcoder cpu_transcoder)
> > }
> >
> > static int initialize_hdcp_port_data(struct intel_connector *connector,
> > - enum port port,
> > + struct intel_digital_port *dig_port,
> > const struct intel_hdcp_shim *shim)
> > {
> > struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > struct intel_hdcp *hdcp = &connector->hdcp;
> > struct hdcp_port_data *data = &hdcp->port_data;
> > + enum port port = dig_port->base.port;
> >
> > if (INTEL_GEN(dev_priv) < 12)
> > data->fw_ddi = intel_get_mei_fw_ddi_index(port);
> > @@ -2060,14 +2061,15 @@ void intel_hdcp_component_init(struct drm_i915_private *dev_priv)
> > }
> > }
> >
> > -static void intel_hdcp2_init(struct intel_connector *connector, enum port port,
> > +static void intel_hdcp2_init(struct intel_connector *connector,
> > + struct intel_digital_port *dig_port,
> > const struct intel_hdcp_shim *shim)
> > {
> > struct drm_i915_private *i915 = to_i915(connector->base.dev);
> > struct intel_hdcp *hdcp = &connector->hdcp;
> > int ret;
> >
> > - ret = initialize_hdcp_port_data(connector, port, shim);
> > + ret = initialize_hdcp_port_data(connector, dig_port, shim);
> > if (ret) {
> > drm_dbg_kms(&i915->drm, "Mei hdcp data init failed\n");
> > return;
> > @@ -2077,7 +2079,7 @@ static void intel_hdcp2_init(struct intel_connector *connector, enum port port,
> > }
> >
> > int intel_hdcp_init(struct intel_connector *connector,
> > - enum port port,
> > + struct intel_digital_port *dig_port,
> > const struct intel_hdcp_shim *shim)
> > {
> > struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > @@ -2088,7 +2090,7 @@ int intel_hdcp_init(struct intel_connector *connector,
> > return -EINVAL;
> >
> > if (is_hdcp2_supported(dev_priv) && !connector->mst_port)
> > - intel_hdcp2_init(connector, port, shim);
> > + intel_hdcp2_init(connector, dig_port, shim);
> >
> > ret =
> > drm_connector_attach_content_protection_property(&connector->base,
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h
> > index b912a3a0f5b8..8f53b0c7fe5c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.h
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
> > @@ -18,13 +18,15 @@ struct intel_connector;
> > struct intel_crtc_state;
> > struct intel_encoder;
> > struct intel_hdcp_shim;
> > +struct intel_digital_port;
> > enum port;
> > enum transcoder;
> >
> > void intel_hdcp_atomic_check(struct drm_connector *connector,
> > struct drm_connector_state *old_state,
> > struct drm_connector_state *new_state);
> > -int intel_hdcp_init(struct intel_connector *connector, enum port port,
> > +int intel_hdcp_init(struct intel_connector *connector,
> > + struct intel_digital_port *dig_port,
> > const struct intel_hdcp_shim *hdcp_shim);
> > int intel_hdcp_enable(struct intel_connector *connector,
> > const struct intel_crtc_state *pipe_config, u8 content_type);
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > index f58469226694..0788de04711b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > @@ -3302,7 +3302,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
> > intel_hdmi->attached_connector = intel_connector;
> >
> > if (is_hdcp_supported(dev_priv, port)) {
> > - int ret = intel_hdcp_init(intel_connector, port,
> > + int ret = intel_hdcp_init(intel_connector, dig_port,
> > &intel_hdmi_hdcp_shim);
> > if (ret)
> > drm_dbg_kms(&dev_priv->drm,
> > --
> > 2.26.2
> >
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^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 08/16] drm/i915/hdcp: Pass dig_port to intel_hdcp_init
@ 2020-11-06 4:50 ` Anshuman Gupta
0 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-11-06 4:50 UTC (permalink / raw)
To: Ramalingam C; +Cc: jani.nikula, intel-gfx, dri-devel, seanpaul
On 2020-11-05 at 22:09:12 +0530, Ramalingam C wrote:
> On 2020-10-27 at 22:12:00 +0530, Anshuman Gupta wrote:
> > Pass dig_port as an argument to intel_hdcp_init()
> > and intel_hdcp2_init().
> > This will be required for HDCP 2.2 stream encryption.
> >
> > Cc: Ramalingam C <ramalingam.c@intel.com>
> > Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 4 ++--
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 12 +++++++-----
> > drivers/gpu/drm/i915/display/intel_hdcp.h | 4 +++-
> > drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
> > 4 files changed, 13 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > index 6dcbfaffd2c5..591b68e5de48 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > @@ -751,10 +751,10 @@ int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
> > return 0;
> >
> > if (intel_connector->mst_port)
> > - return intel_hdcp_init(intel_connector, port,
> > + return intel_hdcp_init(intel_connector, dig_port,
> cant we retrieve the dig_port from connector?
No, actually intel_hdcp_init get called for DP MST in atomic check phase,
in atomic check phase DP MST connector->encoder is not initialize yet,
it initialize with DP MST encoder in commit phase.
so using intel_attached_dig_port(connector) results in OOPS in intel_hdcp_init().
Thanks,
Anshuman Gupta.
>
> -Ram
> > &intel_dp_mst_hdcp_shim);
> > else if (!intel_dp_is_edp(intel_dp))
> > - return intel_hdcp_init(intel_connector, port,
> > + return intel_hdcp_init(intel_connector, dig_port,
> > &intel_dp_hdcp_shim);
> >
> > return 0;
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index 937af4aeaac2..b0f47687bc59 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -1982,12 +1982,13 @@ static enum mei_fw_tc intel_get_mei_fw_tc(enum transcoder cpu_transcoder)
> > }
> >
> > static int initialize_hdcp_port_data(struct intel_connector *connector,
> > - enum port port,
> > + struct intel_digital_port *dig_port,
> > const struct intel_hdcp_shim *shim)
> > {
> > struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > struct intel_hdcp *hdcp = &connector->hdcp;
> > struct hdcp_port_data *data = &hdcp->port_data;
> > + enum port port = dig_port->base.port;
> >
> > if (INTEL_GEN(dev_priv) < 12)
> > data->fw_ddi = intel_get_mei_fw_ddi_index(port);
> > @@ -2060,14 +2061,15 @@ void intel_hdcp_component_init(struct drm_i915_private *dev_priv)
> > }
> > }
> >
> > -static void intel_hdcp2_init(struct intel_connector *connector, enum port port,
> > +static void intel_hdcp2_init(struct intel_connector *connector,
> > + struct intel_digital_port *dig_port,
> > const struct intel_hdcp_shim *shim)
> > {
> > struct drm_i915_private *i915 = to_i915(connector->base.dev);
> > struct intel_hdcp *hdcp = &connector->hdcp;
> > int ret;
> >
> > - ret = initialize_hdcp_port_data(connector, port, shim);
> > + ret = initialize_hdcp_port_data(connector, dig_port, shim);
> > if (ret) {
> > drm_dbg_kms(&i915->drm, "Mei hdcp data init failed\n");
> > return;
> > @@ -2077,7 +2079,7 @@ static void intel_hdcp2_init(struct intel_connector *connector, enum port port,
> > }
> >
> > int intel_hdcp_init(struct intel_connector *connector,
> > - enum port port,
> > + struct intel_digital_port *dig_port,
> > const struct intel_hdcp_shim *shim)
> > {
> > struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > @@ -2088,7 +2090,7 @@ int intel_hdcp_init(struct intel_connector *connector,
> > return -EINVAL;
> >
> > if (is_hdcp2_supported(dev_priv) && !connector->mst_port)
> > - intel_hdcp2_init(connector, port, shim);
> > + intel_hdcp2_init(connector, dig_port, shim);
> >
> > ret =
> > drm_connector_attach_content_protection_property(&connector->base,
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h
> > index b912a3a0f5b8..8f53b0c7fe5c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.h
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
> > @@ -18,13 +18,15 @@ struct intel_connector;
> > struct intel_crtc_state;
> > struct intel_encoder;
> > struct intel_hdcp_shim;
> > +struct intel_digital_port;
> > enum port;
> > enum transcoder;
> >
> > void intel_hdcp_atomic_check(struct drm_connector *connector,
> > struct drm_connector_state *old_state,
> > struct drm_connector_state *new_state);
> > -int intel_hdcp_init(struct intel_connector *connector, enum port port,
> > +int intel_hdcp_init(struct intel_connector *connector,
> > + struct intel_digital_port *dig_port,
> > const struct intel_hdcp_shim *hdcp_shim);
> > int intel_hdcp_enable(struct intel_connector *connector,
> > const struct intel_crtc_state *pipe_config, u8 content_type);
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > index f58469226694..0788de04711b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > @@ -3302,7 +3302,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
> > intel_hdmi->attached_connector = intel_connector;
> >
> > if (is_hdcp_supported(dev_priv, port)) {
> > - int ret = intel_hdcp_init(intel_connector, port,
> > + int ret = intel_hdcp_init(intel_connector, dig_port,
> > &intel_hdmi_hdcp_shim);
> > if (ret)
> > drm_dbg_kms(&dev_priv->drm,
> > --
> > 2.26.2
> >
_______________________________________________
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^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [PATCH v4 08/16] drm/i915/hdcp: Pass dig_port to intel_hdcp_init
2020-11-06 4:50 ` [Intel-gfx] " Anshuman Gupta
@ 2020-11-06 7:48 ` Ramalingam C
-1 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-06 7:48 UTC (permalink / raw)
To: Anshuman Gupta
Cc: jani.nikula, intel-gfx, dri-devel, uma.shankar, seanpaul, juston.li
On 2020-11-06 at 10:20:35 +0530, Anshuman Gupta wrote:
> On 2020-11-05 at 22:09:12 +0530, Ramalingam C wrote:
> > On 2020-10-27 at 22:12:00 +0530, Anshuman Gupta wrote:
> > > Pass dig_port as an argument to intel_hdcp_init()
> > > and intel_hdcp2_init().
> > > This will be required for HDCP 2.2 stream encryption.
> > >
> > > Cc: Ramalingam C <ramalingam.c@intel.com>
> > > Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 4 ++--
> > > drivers/gpu/drm/i915/display/intel_hdcp.c | 12 +++++++-----
> > > drivers/gpu/drm/i915/display/intel_hdcp.h | 4 +++-
> > > drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
> > > 4 files changed, 13 insertions(+), 9 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > > index 6dcbfaffd2c5..591b68e5de48 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > > @@ -751,10 +751,10 @@ int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
> > > return 0;
> > >
> > > if (intel_connector->mst_port)
> > > - return intel_hdcp_init(intel_connector, port,
> > > + return intel_hdcp_init(intel_connector, dig_port,
> > cant we retrieve the dig_port from connector?
> No, actually intel_hdcp_init get called for DP MST in atomic check phase,
> in atomic check phase DP MST connector->encoder is not initialize yet,
> it initialize with DP MST encoder in commit phase.
> so using intel_attached_dig_port(connector) results in OOPS in intel_hdcp_init().
Oh ok. Otherwise LGTM
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
> Thanks,
> Anshuman Gupta.
> >
> > -Ram
> > > &intel_dp_mst_hdcp_shim);
> > > else if (!intel_dp_is_edp(intel_dp))
> > > - return intel_hdcp_init(intel_connector, port,
> > > + return intel_hdcp_init(intel_connector, dig_port,
> > > &intel_dp_hdcp_shim);
> > >
> > > return 0;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > index 937af4aeaac2..b0f47687bc59 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > @@ -1982,12 +1982,13 @@ static enum mei_fw_tc intel_get_mei_fw_tc(enum transcoder cpu_transcoder)
> > > }
> > >
> > > static int initialize_hdcp_port_data(struct intel_connector *connector,
> > > - enum port port,
> > > + struct intel_digital_port *dig_port,
> > > const struct intel_hdcp_shim *shim)
> > > {
> > > struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > > struct intel_hdcp *hdcp = &connector->hdcp;
> > > struct hdcp_port_data *data = &hdcp->port_data;
> > > + enum port port = dig_port->base.port;
> > >
> > > if (INTEL_GEN(dev_priv) < 12)
> > > data->fw_ddi = intel_get_mei_fw_ddi_index(port);
> > > @@ -2060,14 +2061,15 @@ void intel_hdcp_component_init(struct drm_i915_private *dev_priv)
> > > }
> > > }
> > >
> > > -static void intel_hdcp2_init(struct intel_connector *connector, enum port port,
> > > +static void intel_hdcp2_init(struct intel_connector *connector,
> > > + struct intel_digital_port *dig_port,
> > > const struct intel_hdcp_shim *shim)
> > > {
> > > struct drm_i915_private *i915 = to_i915(connector->base.dev);
> > > struct intel_hdcp *hdcp = &connector->hdcp;
> > > int ret;
> > >
> > > - ret = initialize_hdcp_port_data(connector, port, shim);
> > > + ret = initialize_hdcp_port_data(connector, dig_port, shim);
> > > if (ret) {
> > > drm_dbg_kms(&i915->drm, "Mei hdcp data init failed\n");
> > > return;
> > > @@ -2077,7 +2079,7 @@ static void intel_hdcp2_init(struct intel_connector *connector, enum port port,
> > > }
> > >
> > > int intel_hdcp_init(struct intel_connector *connector,
> > > - enum port port,
> > > + struct intel_digital_port *dig_port,
> > > const struct intel_hdcp_shim *shim)
> > > {
> > > struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > > @@ -2088,7 +2090,7 @@ int intel_hdcp_init(struct intel_connector *connector,
> > > return -EINVAL;
> > >
> > > if (is_hdcp2_supported(dev_priv) && !connector->mst_port)
> > > - intel_hdcp2_init(connector, port, shim);
> > > + intel_hdcp2_init(connector, dig_port, shim);
> > >
> > > ret =
> > > drm_connector_attach_content_protection_property(&connector->base,
> > > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h
> > > index b912a3a0f5b8..8f53b0c7fe5c 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_hdcp.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
> > > @@ -18,13 +18,15 @@ struct intel_connector;
> > > struct intel_crtc_state;
> > > struct intel_encoder;
> > > struct intel_hdcp_shim;
> > > +struct intel_digital_port;
> > > enum port;
> > > enum transcoder;
> > >
> > > void intel_hdcp_atomic_check(struct drm_connector *connector,
> > > struct drm_connector_state *old_state,
> > > struct drm_connector_state *new_state);
> > > -int intel_hdcp_init(struct intel_connector *connector, enum port port,
> > > +int intel_hdcp_init(struct intel_connector *connector,
> > > + struct intel_digital_port *dig_port,
> > > const struct intel_hdcp_shim *hdcp_shim);
> > > int intel_hdcp_enable(struct intel_connector *connector,
> > > const struct intel_crtc_state *pipe_config, u8 content_type);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > > index f58469226694..0788de04711b 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > > @@ -3302,7 +3302,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
> > > intel_hdmi->attached_connector = intel_connector;
> > >
> > > if (is_hdcp_supported(dev_priv, port)) {
> > > - int ret = intel_hdcp_init(intel_connector, port,
> > > + int ret = intel_hdcp_init(intel_connector, dig_port,
> > > &intel_hdmi_hdcp_shim);
> > > if (ret)
> > > drm_dbg_kms(&dev_priv->drm,
> > > --
> > > 2.26.2
> > >
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 08/16] drm/i915/hdcp: Pass dig_port to intel_hdcp_init
@ 2020-11-06 7:48 ` Ramalingam C
0 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-06 7:48 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: jani.nikula, intel-gfx, dri-devel, seanpaul
On 2020-11-06 at 10:20:35 +0530, Anshuman Gupta wrote:
> On 2020-11-05 at 22:09:12 +0530, Ramalingam C wrote:
> > On 2020-10-27 at 22:12:00 +0530, Anshuman Gupta wrote:
> > > Pass dig_port as an argument to intel_hdcp_init()
> > > and intel_hdcp2_init().
> > > This will be required for HDCP 2.2 stream encryption.
> > >
> > > Cc: Ramalingam C <ramalingam.c@intel.com>
> > > Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 4 ++--
> > > drivers/gpu/drm/i915/display/intel_hdcp.c | 12 +++++++-----
> > > drivers/gpu/drm/i915/display/intel_hdcp.h | 4 +++-
> > > drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
> > > 4 files changed, 13 insertions(+), 9 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > > index 6dcbfaffd2c5..591b68e5de48 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > > @@ -751,10 +751,10 @@ int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
> > > return 0;
> > >
> > > if (intel_connector->mst_port)
> > > - return intel_hdcp_init(intel_connector, port,
> > > + return intel_hdcp_init(intel_connector, dig_port,
> > cant we retrieve the dig_port from connector?
> No, actually intel_hdcp_init get called for DP MST in atomic check phase,
> in atomic check phase DP MST connector->encoder is not initialize yet,
> it initialize with DP MST encoder in commit phase.
> so using intel_attached_dig_port(connector) results in OOPS in intel_hdcp_init().
Oh ok. Otherwise LGTM
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
> Thanks,
> Anshuman Gupta.
> >
> > -Ram
> > > &intel_dp_mst_hdcp_shim);
> > > else if (!intel_dp_is_edp(intel_dp))
> > > - return intel_hdcp_init(intel_connector, port,
> > > + return intel_hdcp_init(intel_connector, dig_port,
> > > &intel_dp_hdcp_shim);
> > >
> > > return 0;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > index 937af4aeaac2..b0f47687bc59 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > @@ -1982,12 +1982,13 @@ static enum mei_fw_tc intel_get_mei_fw_tc(enum transcoder cpu_transcoder)
> > > }
> > >
> > > static int initialize_hdcp_port_data(struct intel_connector *connector,
> > > - enum port port,
> > > + struct intel_digital_port *dig_port,
> > > const struct intel_hdcp_shim *shim)
> > > {
> > > struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > > struct intel_hdcp *hdcp = &connector->hdcp;
> > > struct hdcp_port_data *data = &hdcp->port_data;
> > > + enum port port = dig_port->base.port;
> > >
> > > if (INTEL_GEN(dev_priv) < 12)
> > > data->fw_ddi = intel_get_mei_fw_ddi_index(port);
> > > @@ -2060,14 +2061,15 @@ void intel_hdcp_component_init(struct drm_i915_private *dev_priv)
> > > }
> > > }
> > >
> > > -static void intel_hdcp2_init(struct intel_connector *connector, enum port port,
> > > +static void intel_hdcp2_init(struct intel_connector *connector,
> > > + struct intel_digital_port *dig_port,
> > > const struct intel_hdcp_shim *shim)
> > > {
> > > struct drm_i915_private *i915 = to_i915(connector->base.dev);
> > > struct intel_hdcp *hdcp = &connector->hdcp;
> > > int ret;
> > >
> > > - ret = initialize_hdcp_port_data(connector, port, shim);
> > > + ret = initialize_hdcp_port_data(connector, dig_port, shim);
> > > if (ret) {
> > > drm_dbg_kms(&i915->drm, "Mei hdcp data init failed\n");
> > > return;
> > > @@ -2077,7 +2079,7 @@ static void intel_hdcp2_init(struct intel_connector *connector, enum port port,
> > > }
> > >
> > > int intel_hdcp_init(struct intel_connector *connector,
> > > - enum port port,
> > > + struct intel_digital_port *dig_port,
> > > const struct intel_hdcp_shim *shim)
> > > {
> > > struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > > @@ -2088,7 +2090,7 @@ int intel_hdcp_init(struct intel_connector *connector,
> > > return -EINVAL;
> > >
> > > if (is_hdcp2_supported(dev_priv) && !connector->mst_port)
> > > - intel_hdcp2_init(connector, port, shim);
> > > + intel_hdcp2_init(connector, dig_port, shim);
> > >
> > > ret =
> > > drm_connector_attach_content_protection_property(&connector->base,
> > > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h
> > > index b912a3a0f5b8..8f53b0c7fe5c 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_hdcp.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
> > > @@ -18,13 +18,15 @@ struct intel_connector;
> > > struct intel_crtc_state;
> > > struct intel_encoder;
> > > struct intel_hdcp_shim;
> > > +struct intel_digital_port;
> > > enum port;
> > > enum transcoder;
> > >
> > > void intel_hdcp_atomic_check(struct drm_connector *connector,
> > > struct drm_connector_state *old_state,
> > > struct drm_connector_state *new_state);
> > > -int intel_hdcp_init(struct intel_connector *connector, enum port port,
> > > +int intel_hdcp_init(struct intel_connector *connector,
> > > + struct intel_digital_port *dig_port,
> > > const struct intel_hdcp_shim *hdcp_shim);
> > > int intel_hdcp_enable(struct intel_connector *connector,
> > > const struct intel_crtc_state *pipe_config, u8 content_type);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > > index f58469226694..0788de04711b 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > > @@ -3302,7 +3302,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
> > > intel_hdmi->attached_connector = intel_connector;
> > >
> > > if (is_hdcp_supported(dev_priv, port)) {
> > > - int ret = intel_hdcp_init(intel_connector, port,
> > > + int ret = intel_hdcp_init(intel_connector, dig_port,
> > > &intel_hdmi_hdcp_shim);
> > > if (ret)
> > > drm_dbg_kms(&dev_priv->drm,
> > > --
> > > 2.26.2
> > >
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread
* [PATCH v4 09/16] drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
@ 2020-10-27 16:42 ` Anshuman Gupta
-1 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:42 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: jani.nikula, uma.shankar, seanpaul, Anshuman Gupta, juston.li
hdcp_port_data is specific to a port on which HDCP
encryption is getting enabled, so encapsulate it to
intel_digital_port.
This will be required to enable HDCP 2.2 stream encryption.
Cc: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +
.../drm/i915/display/intel_display_types.h | 5 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 56 +++++++++++--------
3 files changed, 39 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 779603a38cfc..1bc6cf0b83ec 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4746,6 +4746,8 @@ static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
intel_dp_encoder_flush_work(encoder);
drm_encoder_cleanup(encoder);
+ if (dig_port)
+ kfree(dig_port->port_data.streams);
kfree(dig_port);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 59b8fc21e3e8..749c3a7e0b45 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -402,7 +402,6 @@ struct intel_hdcp {
* content can flow only through a link protected by HDCP2.2.
*/
u8 content_type;
- struct hdcp_port_data port_data;
bool is_paired;
bool is_repeater;
@@ -1446,10 +1445,12 @@ struct intel_digital_port {
enum phy_fia tc_phy_fia;
u8 tc_phy_fia_idx;
- /* protects num_hdcp_streams reference count */
+ /* protects num_hdcp_streams reference count, port_data */
struct mutex hdcp_mutex;
/* the number of pipes using HDCP signalling out of this port */
unsigned int num_hdcp_streams;
+ /* HDCP port data need to pass to security f/w */
+ struct hdcp_port_data port_data;
void (*write_infoframe)(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index b0f47687bc59..a5ec4f72f50f 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -15,6 +15,7 @@
#include <drm/drm_hdcp.h>
#include <drm/i915_component.h>
+#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_display_power.h"
#include "intel_display_types.h"
@@ -1028,7 +1029,8 @@ static int
hdcp2_prepare_ake_init(struct intel_connector *connector,
struct hdcp2_ake_init *ake_data)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1057,7 +1059,8 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector,
struct hdcp2_ake_no_stored_km *ek_pub_km,
size_t *msg_sz)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1084,7 +1087,8 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector,
static int hdcp2_verify_hprime(struct intel_connector *connector,
struct hdcp2_ake_send_hprime *rx_hprime)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1109,7 +1113,8 @@ static int
hdcp2_store_pairing_info(struct intel_connector *connector,
struct hdcp2_ake_send_pairing_info *pairing_info)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1135,7 +1140,8 @@ static int
hdcp2_prepare_lc_init(struct intel_connector *connector,
struct hdcp2_lc_init *lc_init)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1161,7 +1167,8 @@ static int
hdcp2_verify_lprime(struct intel_connector *connector,
struct hdcp2_lc_send_lprime *rx_lprime)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1186,7 +1193,8 @@ hdcp2_verify_lprime(struct intel_connector *connector,
static int hdcp2_prepare_skey(struct intel_connector *connector,
struct hdcp2_ske_send_eks *ske_data)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1214,7 +1222,8 @@ hdcp2_verify_rep_topology_prepare_ack(struct intel_connector *connector,
*rep_topology,
struct hdcp2_rep_send_ack *rep_send_ack)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1242,7 +1251,8 @@ static int
hdcp2_verify_mprime(struct intel_connector *connector,
struct hdcp2_rep_stream_ready *stream_ready)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1265,7 +1275,8 @@ hdcp2_verify_mprime(struct intel_connector *connector,
static int hdcp2_authenticate_port(struct intel_connector *connector)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1289,6 +1300,7 @@ static int hdcp2_authenticate_port(struct intel_connector *connector)
static int hdcp2_close_mei_session(struct intel_connector *connector)
{
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1302,7 +1314,7 @@ static int hdcp2_close_mei_session(struct intel_connector *connector)
}
ret = comp->ops->close_hdcp_session(comp->mei_dev,
- &connector->hdcp.port_data);
+ &dig_port->port_data);
mutex_unlock(&dev_priv->hdcp_comp_mutex);
return ret;
@@ -1495,8 +1507,9 @@ int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
if (ret < 0)
goto out;
- hdcp->port_data.seq_num_m = hdcp->seq_num_m;
- hdcp->port_data.streams[0].stream_type = hdcp->content_type;
+ dig_port->port_data.seq_num_m = hdcp->seq_num_m;
+ dig_port->port_data.streams[0].stream_type = hdcp->content_type;
+
ret = hdcp2_verify_mprime(connector, &msgs.stream_ready);
out:
@@ -1728,7 +1741,9 @@ hdcp2_propagate_stream_management_info(struct intel_connector *connector)
static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
{
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct intel_hdcp *hdcp = &connector->hdcp;
int ret, i, tries = 3;
@@ -1742,8 +1757,7 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
ret);
break;
}
- hdcp->port_data.streams[0].stream_type =
- hdcp->content_type;
+ data->streams[0].stream_type = hdcp->content_type;
ret = hdcp2_authenticate_port(connector);
if (!ret)
break;
@@ -1986,8 +2000,8 @@ static int initialize_hdcp_port_data(struct intel_connector *connector,
const struct intel_hdcp_shim *shim)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct intel_hdcp *hdcp = &connector->hdcp;
- struct hdcp_port_data *data = &hdcp->port_data;
enum port port = dig_port->base.port;
if (INTEL_GEN(dev_priv) < 12)
@@ -2009,16 +2023,15 @@ static int initialize_hdcp_port_data(struct intel_connector *connector,
data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED;
data->protocol = (u8)shim->protocol;
- data->k = 1;
if (!data->streams)
- data->streams = kcalloc(data->k,
+ data->streams = kcalloc(INTEL_NUM_PIPES(dev_priv),
sizeof(struct hdcp2_streamid_type),
GFP_KERNEL);
if (!data->streams) {
drm_err(&dev_priv->drm, "Out of Memory\n");
return -ENOMEM;
}
-
+ /* For SST */
data->streams[0].stream_id = 0;
data->streams[0].stream_type = hdcp->content_type;
@@ -2097,7 +2110,7 @@ int intel_hdcp_init(struct intel_connector *connector,
hdcp->hdcp2_supported);
if (ret) {
hdcp->hdcp2_supported = false;
- kfree(hdcp->port_data.streams);
+ kfree(dig_port->port_data.streams);
return ret;
}
@@ -2137,7 +2150,7 @@ int intel_hdcp_enable(struct intel_connector *connector,
}
if (INTEL_GEN(dev_priv) >= 12)
- hdcp->port_data.fw_tc = intel_get_mei_fw_tc(hdcp->cpu_transcoder);
+ dig_port->port_data.fw_tc = intel_get_mei_fw_tc(hdcp->cpu_transcoder);
/*
* Considering that HDCP2.2 is more secure than HDCP1.4, If the setup
@@ -2307,7 +2320,6 @@ void intel_hdcp_cleanup(struct intel_connector *connector)
drm_WARN_ON(connector->base.dev, work_pending(&hdcp->prop_work));
mutex_lock(&hdcp->mutex);
- kfree(hdcp->port_data.streams);
hdcp->shim = NULL;
mutex_unlock(&hdcp->mutex);
}
--
2.26.2
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 111+ messages in thread* [Intel-gfx] [PATCH v4 09/16] drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port
@ 2020-10-27 16:42 ` Anshuman Gupta
0 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:42 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula, seanpaul
hdcp_port_data is specific to a port on which HDCP
encryption is getting enabled, so encapsulate it to
intel_digital_port.
This will be required to enable HDCP 2.2 stream encryption.
Cc: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +
.../drm/i915/display/intel_display_types.h | 5 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 56 +++++++++++--------
3 files changed, 39 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 779603a38cfc..1bc6cf0b83ec 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4746,6 +4746,8 @@ static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
intel_dp_encoder_flush_work(encoder);
drm_encoder_cleanup(encoder);
+ if (dig_port)
+ kfree(dig_port->port_data.streams);
kfree(dig_port);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 59b8fc21e3e8..749c3a7e0b45 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -402,7 +402,6 @@ struct intel_hdcp {
* content can flow only through a link protected by HDCP2.2.
*/
u8 content_type;
- struct hdcp_port_data port_data;
bool is_paired;
bool is_repeater;
@@ -1446,10 +1445,12 @@ struct intel_digital_port {
enum phy_fia tc_phy_fia;
u8 tc_phy_fia_idx;
- /* protects num_hdcp_streams reference count */
+ /* protects num_hdcp_streams reference count, port_data */
struct mutex hdcp_mutex;
/* the number of pipes using HDCP signalling out of this port */
unsigned int num_hdcp_streams;
+ /* HDCP port data need to pass to security f/w */
+ struct hdcp_port_data port_data;
void (*write_infoframe)(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index b0f47687bc59..a5ec4f72f50f 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -15,6 +15,7 @@
#include <drm/drm_hdcp.h>
#include <drm/i915_component.h>
+#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_display_power.h"
#include "intel_display_types.h"
@@ -1028,7 +1029,8 @@ static int
hdcp2_prepare_ake_init(struct intel_connector *connector,
struct hdcp2_ake_init *ake_data)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1057,7 +1059,8 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector,
struct hdcp2_ake_no_stored_km *ek_pub_km,
size_t *msg_sz)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1084,7 +1087,8 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector,
static int hdcp2_verify_hprime(struct intel_connector *connector,
struct hdcp2_ake_send_hprime *rx_hprime)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1109,7 +1113,8 @@ static int
hdcp2_store_pairing_info(struct intel_connector *connector,
struct hdcp2_ake_send_pairing_info *pairing_info)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1135,7 +1140,8 @@ static int
hdcp2_prepare_lc_init(struct intel_connector *connector,
struct hdcp2_lc_init *lc_init)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1161,7 +1167,8 @@ static int
hdcp2_verify_lprime(struct intel_connector *connector,
struct hdcp2_lc_send_lprime *rx_lprime)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1186,7 +1193,8 @@ hdcp2_verify_lprime(struct intel_connector *connector,
static int hdcp2_prepare_skey(struct intel_connector *connector,
struct hdcp2_ske_send_eks *ske_data)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1214,7 +1222,8 @@ hdcp2_verify_rep_topology_prepare_ack(struct intel_connector *connector,
*rep_topology,
struct hdcp2_rep_send_ack *rep_send_ack)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1242,7 +1251,8 @@ static int
hdcp2_verify_mprime(struct intel_connector *connector,
struct hdcp2_rep_stream_ready *stream_ready)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1265,7 +1275,8 @@ hdcp2_verify_mprime(struct intel_connector *connector,
static int hdcp2_authenticate_port(struct intel_connector *connector)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1289,6 +1300,7 @@ static int hdcp2_authenticate_port(struct intel_connector *connector)
static int hdcp2_close_mei_session(struct intel_connector *connector)
{
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1302,7 +1314,7 @@ static int hdcp2_close_mei_session(struct intel_connector *connector)
}
ret = comp->ops->close_hdcp_session(comp->mei_dev,
- &connector->hdcp.port_data);
+ &dig_port->port_data);
mutex_unlock(&dev_priv->hdcp_comp_mutex);
return ret;
@@ -1495,8 +1507,9 @@ int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
if (ret < 0)
goto out;
- hdcp->port_data.seq_num_m = hdcp->seq_num_m;
- hdcp->port_data.streams[0].stream_type = hdcp->content_type;
+ dig_port->port_data.seq_num_m = hdcp->seq_num_m;
+ dig_port->port_data.streams[0].stream_type = hdcp->content_type;
+
ret = hdcp2_verify_mprime(connector, &msgs.stream_ready);
out:
@@ -1728,7 +1741,9 @@ hdcp2_propagate_stream_management_info(struct intel_connector *connector)
static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
{
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct intel_hdcp *hdcp = &connector->hdcp;
int ret, i, tries = 3;
@@ -1742,8 +1757,7 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
ret);
break;
}
- hdcp->port_data.streams[0].stream_type =
- hdcp->content_type;
+ data->streams[0].stream_type = hdcp->content_type;
ret = hdcp2_authenticate_port(connector);
if (!ret)
break;
@@ -1986,8 +2000,8 @@ static int initialize_hdcp_port_data(struct intel_connector *connector,
const struct intel_hdcp_shim *shim)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct intel_hdcp *hdcp = &connector->hdcp;
- struct hdcp_port_data *data = &hdcp->port_data;
enum port port = dig_port->base.port;
if (INTEL_GEN(dev_priv) < 12)
@@ -2009,16 +2023,15 @@ static int initialize_hdcp_port_data(struct intel_connector *connector,
data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED;
data->protocol = (u8)shim->protocol;
- data->k = 1;
if (!data->streams)
- data->streams = kcalloc(data->k,
+ data->streams = kcalloc(INTEL_NUM_PIPES(dev_priv),
sizeof(struct hdcp2_streamid_type),
GFP_KERNEL);
if (!data->streams) {
drm_err(&dev_priv->drm, "Out of Memory\n");
return -ENOMEM;
}
-
+ /* For SST */
data->streams[0].stream_id = 0;
data->streams[0].stream_type = hdcp->content_type;
@@ -2097,7 +2110,7 @@ int intel_hdcp_init(struct intel_connector *connector,
hdcp->hdcp2_supported);
if (ret) {
hdcp->hdcp2_supported = false;
- kfree(hdcp->port_data.streams);
+ kfree(dig_port->port_data.streams);
return ret;
}
@@ -2137,7 +2150,7 @@ int intel_hdcp_enable(struct intel_connector *connector,
}
if (INTEL_GEN(dev_priv) >= 12)
- hdcp->port_data.fw_tc = intel_get_mei_fw_tc(hdcp->cpu_transcoder);
+ dig_port->port_data.fw_tc = intel_get_mei_fw_tc(hdcp->cpu_transcoder);
/*
* Considering that HDCP2.2 is more secure than HDCP1.4, If the setup
@@ -2307,7 +2320,6 @@ void intel_hdcp_cleanup(struct intel_connector *connector)
drm_WARN_ON(connector->base.dev, work_pending(&hdcp->prop_work));
mutex_lock(&hdcp->mutex);
- kfree(hdcp->port_data.streams);
hdcp->shim = NULL;
mutex_unlock(&hdcp->mutex);
}
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 111+ messages in thread* Re: [PATCH v4 09/16] drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port
2020-10-27 16:42 ` [Intel-gfx] " Anshuman Gupta
@ 2020-11-06 11:34 ` Ramalingam C
-1 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-06 11:34 UTC (permalink / raw)
To: Anshuman Gupta
Cc: jani.nikula, intel-gfx, dri-devel, uma.shankar, seanpaul, juston.li
On 2020-10-27 at 22:12:01 +0530, Anshuman Gupta wrote:
> hdcp_port_data is specific to a port on which HDCP
> encryption is getting enabled, so encapsulate it to
> intel_digital_port.
> This will be required to enable HDCP 2.2 stream encryption.
>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 2 +
> .../drm/i915/display/intel_display_types.h | 5 +-
> drivers/gpu/drm/i915/display/intel_hdcp.c | 56 +++++++++++--------
> 3 files changed, 39 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 779603a38cfc..1bc6cf0b83ec 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4746,6 +4746,8 @@ static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
> intel_dp_encoder_flush_work(encoder);
>
> drm_encoder_cleanup(encoder);
> + if (dig_port)
> + kfree(dig_port->port_data.streams);
> kfree(dig_port);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 59b8fc21e3e8..749c3a7e0b45 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -402,7 +402,6 @@ struct intel_hdcp {
> * content can flow only through a link protected by HDCP2.2.
> */
> u8 content_type;
> - struct hdcp_port_data port_data;
>
> bool is_paired;
> bool is_repeater;
> @@ -1446,10 +1445,12 @@ struct intel_digital_port {
> enum phy_fia tc_phy_fia;
> u8 tc_phy_fia_idx;
>
> - /* protects num_hdcp_streams reference count */
> + /* protects num_hdcp_streams reference count, port_data */
> struct mutex hdcp_mutex;
> /* the number of pipes using HDCP signalling out of this port */
> unsigned int num_hdcp_streams;
> + /* HDCP port data need to pass to security f/w */
> + struct hdcp_port_data port_data;
Since this is outside intel_hdcp, better ad prefix of hdcp_
With that addressed
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
>
> void (*write_infoframe)(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index b0f47687bc59..a5ec4f72f50f 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -15,6 +15,7 @@
> #include <drm/drm_hdcp.h>
> #include <drm/i915_component.h>
>
> +#include "i915_drv.h"
> #include "i915_reg.h"
> #include "intel_display_power.h"
> #include "intel_display_types.h"
> @@ -1028,7 +1029,8 @@ static int
> hdcp2_prepare_ake_init(struct intel_connector *connector,
> struct hdcp2_ake_init *ake_data)
> {
> - struct hdcp_port_data *data = &connector->hdcp.port_data;
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct i915_hdcp_comp_master *comp;
> int ret;
> @@ -1057,7 +1059,8 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector,
> struct hdcp2_ake_no_stored_km *ek_pub_km,
> size_t *msg_sz)
> {
> - struct hdcp_port_data *data = &connector->hdcp.port_data;
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct i915_hdcp_comp_master *comp;
> int ret;
> @@ -1084,7 +1087,8 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector,
> static int hdcp2_verify_hprime(struct intel_connector *connector,
> struct hdcp2_ake_send_hprime *rx_hprime)
> {
> - struct hdcp_port_data *data = &connector->hdcp.port_data;
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct i915_hdcp_comp_master *comp;
> int ret;
> @@ -1109,7 +1113,8 @@ static int
> hdcp2_store_pairing_info(struct intel_connector *connector,
> struct hdcp2_ake_send_pairing_info *pairing_info)
> {
> - struct hdcp_port_data *data = &connector->hdcp.port_data;
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct i915_hdcp_comp_master *comp;
> int ret;
> @@ -1135,7 +1140,8 @@ static int
> hdcp2_prepare_lc_init(struct intel_connector *connector,
> struct hdcp2_lc_init *lc_init)
> {
> - struct hdcp_port_data *data = &connector->hdcp.port_data;
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct i915_hdcp_comp_master *comp;
> int ret;
> @@ -1161,7 +1167,8 @@ static int
> hdcp2_verify_lprime(struct intel_connector *connector,
> struct hdcp2_lc_send_lprime *rx_lprime)
> {
> - struct hdcp_port_data *data = &connector->hdcp.port_data;
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct i915_hdcp_comp_master *comp;
> int ret;
> @@ -1186,7 +1193,8 @@ hdcp2_verify_lprime(struct intel_connector *connector,
> static int hdcp2_prepare_skey(struct intel_connector *connector,
> struct hdcp2_ske_send_eks *ske_data)
> {
> - struct hdcp_port_data *data = &connector->hdcp.port_data;
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct i915_hdcp_comp_master *comp;
> int ret;
> @@ -1214,7 +1222,8 @@ hdcp2_verify_rep_topology_prepare_ack(struct intel_connector *connector,
> *rep_topology,
> struct hdcp2_rep_send_ack *rep_send_ack)
> {
> - struct hdcp_port_data *data = &connector->hdcp.port_data;
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct i915_hdcp_comp_master *comp;
> int ret;
> @@ -1242,7 +1251,8 @@ static int
> hdcp2_verify_mprime(struct intel_connector *connector,
> struct hdcp2_rep_stream_ready *stream_ready)
> {
> - struct hdcp_port_data *data = &connector->hdcp.port_data;
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct i915_hdcp_comp_master *comp;
> int ret;
> @@ -1265,7 +1275,8 @@ hdcp2_verify_mprime(struct intel_connector *connector,
>
> static int hdcp2_authenticate_port(struct intel_connector *connector)
> {
> - struct hdcp_port_data *data = &connector->hdcp.port_data;
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct i915_hdcp_comp_master *comp;
> int ret;
> @@ -1289,6 +1300,7 @@ static int hdcp2_authenticate_port(struct intel_connector *connector)
>
> static int hdcp2_close_mei_session(struct intel_connector *connector)
> {
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct i915_hdcp_comp_master *comp;
> int ret;
> @@ -1302,7 +1314,7 @@ static int hdcp2_close_mei_session(struct intel_connector *connector)
> }
>
> ret = comp->ops->close_hdcp_session(comp->mei_dev,
> - &connector->hdcp.port_data);
> + &dig_port->port_data);
> mutex_unlock(&dev_priv->hdcp_comp_mutex);
>
> return ret;
> @@ -1495,8 +1507,9 @@ int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
> if (ret < 0)
> goto out;
>
> - hdcp->port_data.seq_num_m = hdcp->seq_num_m;
> - hdcp->port_data.streams[0].stream_type = hdcp->content_type;
> + dig_port->port_data.seq_num_m = hdcp->seq_num_m;
> + dig_port->port_data.streams[0].stream_type = hdcp->content_type;
> +
> ret = hdcp2_verify_mprime(connector, &msgs.stream_ready);
>
> out:
> @@ -1728,7 +1741,9 @@ hdcp2_propagate_stream_management_info(struct intel_connector *connector)
>
> static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
> {
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct intel_hdcp *hdcp = &connector->hdcp;
> int ret, i, tries = 3;
>
> @@ -1742,8 +1757,7 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
> ret);
> break;
> }
> - hdcp->port_data.streams[0].stream_type =
> - hdcp->content_type;
> + data->streams[0].stream_type = hdcp->content_type;
> ret = hdcp2_authenticate_port(connector);
> if (!ret)
> break;
> @@ -1986,8 +2000,8 @@ static int initialize_hdcp_port_data(struct intel_connector *connector,
> const struct intel_hdcp_shim *shim)
> {
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct intel_hdcp *hdcp = &connector->hdcp;
> - struct hdcp_port_data *data = &hdcp->port_data;
> enum port port = dig_port->base.port;
>
> if (INTEL_GEN(dev_priv) < 12)
> @@ -2009,16 +2023,15 @@ static int initialize_hdcp_port_data(struct intel_connector *connector,
> data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED;
> data->protocol = (u8)shim->protocol;
>
> - data->k = 1;
> if (!data->streams)
> - data->streams = kcalloc(data->k,
> + data->streams = kcalloc(INTEL_NUM_PIPES(dev_priv),
> sizeof(struct hdcp2_streamid_type),
> GFP_KERNEL);
> if (!data->streams) {
> drm_err(&dev_priv->drm, "Out of Memory\n");
> return -ENOMEM;
> }
> -
> + /* For SST */
> data->streams[0].stream_id = 0;
> data->streams[0].stream_type = hdcp->content_type;
>
> @@ -2097,7 +2110,7 @@ int intel_hdcp_init(struct intel_connector *connector,
> hdcp->hdcp2_supported);
> if (ret) {
> hdcp->hdcp2_supported = false;
> - kfree(hdcp->port_data.streams);
> + kfree(dig_port->port_data.streams);
> return ret;
> }
>
> @@ -2137,7 +2150,7 @@ int intel_hdcp_enable(struct intel_connector *connector,
> }
>
> if (INTEL_GEN(dev_priv) >= 12)
> - hdcp->port_data.fw_tc = intel_get_mei_fw_tc(hdcp->cpu_transcoder);
> + dig_port->port_data.fw_tc = intel_get_mei_fw_tc(hdcp->cpu_transcoder);
>
> /*
> * Considering that HDCP2.2 is more secure than HDCP1.4, If the setup
> @@ -2307,7 +2320,6 @@ void intel_hdcp_cleanup(struct intel_connector *connector)
> drm_WARN_ON(connector->base.dev, work_pending(&hdcp->prop_work));
>
> mutex_lock(&hdcp->mutex);
> - kfree(hdcp->port_data.streams);
> hdcp->shim = NULL;
> mutex_unlock(&hdcp->mutex);
> }
> --
> 2.26.2
>
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^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 09/16] drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port
@ 2020-11-06 11:34 ` Ramalingam C
0 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-06 11:34 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: jani.nikula, intel-gfx, dri-devel, seanpaul
On 2020-10-27 at 22:12:01 +0530, Anshuman Gupta wrote:
> hdcp_port_data is specific to a port on which HDCP
> encryption is getting enabled, so encapsulate it to
> intel_digital_port.
> This will be required to enable HDCP 2.2 stream encryption.
>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 2 +
> .../drm/i915/display/intel_display_types.h | 5 +-
> drivers/gpu/drm/i915/display/intel_hdcp.c | 56 +++++++++++--------
> 3 files changed, 39 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 779603a38cfc..1bc6cf0b83ec 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4746,6 +4746,8 @@ static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
> intel_dp_encoder_flush_work(encoder);
>
> drm_encoder_cleanup(encoder);
> + if (dig_port)
> + kfree(dig_port->port_data.streams);
> kfree(dig_port);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 59b8fc21e3e8..749c3a7e0b45 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -402,7 +402,6 @@ struct intel_hdcp {
> * content can flow only through a link protected by HDCP2.2.
> */
> u8 content_type;
> - struct hdcp_port_data port_data;
>
> bool is_paired;
> bool is_repeater;
> @@ -1446,10 +1445,12 @@ struct intel_digital_port {
> enum phy_fia tc_phy_fia;
> u8 tc_phy_fia_idx;
>
> - /* protects num_hdcp_streams reference count */
> + /* protects num_hdcp_streams reference count, port_data */
> struct mutex hdcp_mutex;
> /* the number of pipes using HDCP signalling out of this port */
> unsigned int num_hdcp_streams;
> + /* HDCP port data need to pass to security f/w */
> + struct hdcp_port_data port_data;
Since this is outside intel_hdcp, better ad prefix of hdcp_
With that addressed
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
>
> void (*write_infoframe)(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index b0f47687bc59..a5ec4f72f50f 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -15,6 +15,7 @@
> #include <drm/drm_hdcp.h>
> #include <drm/i915_component.h>
>
> +#include "i915_drv.h"
> #include "i915_reg.h"
> #include "intel_display_power.h"
> #include "intel_display_types.h"
> @@ -1028,7 +1029,8 @@ static int
> hdcp2_prepare_ake_init(struct intel_connector *connector,
> struct hdcp2_ake_init *ake_data)
> {
> - struct hdcp_port_data *data = &connector->hdcp.port_data;
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct i915_hdcp_comp_master *comp;
> int ret;
> @@ -1057,7 +1059,8 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector,
> struct hdcp2_ake_no_stored_km *ek_pub_km,
> size_t *msg_sz)
> {
> - struct hdcp_port_data *data = &connector->hdcp.port_data;
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct i915_hdcp_comp_master *comp;
> int ret;
> @@ -1084,7 +1087,8 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector,
> static int hdcp2_verify_hprime(struct intel_connector *connector,
> struct hdcp2_ake_send_hprime *rx_hprime)
> {
> - struct hdcp_port_data *data = &connector->hdcp.port_data;
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct i915_hdcp_comp_master *comp;
> int ret;
> @@ -1109,7 +1113,8 @@ static int
> hdcp2_store_pairing_info(struct intel_connector *connector,
> struct hdcp2_ake_send_pairing_info *pairing_info)
> {
> - struct hdcp_port_data *data = &connector->hdcp.port_data;
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct i915_hdcp_comp_master *comp;
> int ret;
> @@ -1135,7 +1140,8 @@ static int
> hdcp2_prepare_lc_init(struct intel_connector *connector,
> struct hdcp2_lc_init *lc_init)
> {
> - struct hdcp_port_data *data = &connector->hdcp.port_data;
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct i915_hdcp_comp_master *comp;
> int ret;
> @@ -1161,7 +1167,8 @@ static int
> hdcp2_verify_lprime(struct intel_connector *connector,
> struct hdcp2_lc_send_lprime *rx_lprime)
> {
> - struct hdcp_port_data *data = &connector->hdcp.port_data;
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct i915_hdcp_comp_master *comp;
> int ret;
> @@ -1186,7 +1193,8 @@ hdcp2_verify_lprime(struct intel_connector *connector,
> static int hdcp2_prepare_skey(struct intel_connector *connector,
> struct hdcp2_ske_send_eks *ske_data)
> {
> - struct hdcp_port_data *data = &connector->hdcp.port_data;
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct i915_hdcp_comp_master *comp;
> int ret;
> @@ -1214,7 +1222,8 @@ hdcp2_verify_rep_topology_prepare_ack(struct intel_connector *connector,
> *rep_topology,
> struct hdcp2_rep_send_ack *rep_send_ack)
> {
> - struct hdcp_port_data *data = &connector->hdcp.port_data;
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct i915_hdcp_comp_master *comp;
> int ret;
> @@ -1242,7 +1251,8 @@ static int
> hdcp2_verify_mprime(struct intel_connector *connector,
> struct hdcp2_rep_stream_ready *stream_ready)
> {
> - struct hdcp_port_data *data = &connector->hdcp.port_data;
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct i915_hdcp_comp_master *comp;
> int ret;
> @@ -1265,7 +1275,8 @@ hdcp2_verify_mprime(struct intel_connector *connector,
>
> static int hdcp2_authenticate_port(struct intel_connector *connector)
> {
> - struct hdcp_port_data *data = &connector->hdcp.port_data;
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct i915_hdcp_comp_master *comp;
> int ret;
> @@ -1289,6 +1300,7 @@ static int hdcp2_authenticate_port(struct intel_connector *connector)
>
> static int hdcp2_close_mei_session(struct intel_connector *connector)
> {
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct i915_hdcp_comp_master *comp;
> int ret;
> @@ -1302,7 +1314,7 @@ static int hdcp2_close_mei_session(struct intel_connector *connector)
> }
>
> ret = comp->ops->close_hdcp_session(comp->mei_dev,
> - &connector->hdcp.port_data);
> + &dig_port->port_data);
> mutex_unlock(&dev_priv->hdcp_comp_mutex);
>
> return ret;
> @@ -1495,8 +1507,9 @@ int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
> if (ret < 0)
> goto out;
>
> - hdcp->port_data.seq_num_m = hdcp->seq_num_m;
> - hdcp->port_data.streams[0].stream_type = hdcp->content_type;
> + dig_port->port_data.seq_num_m = hdcp->seq_num_m;
> + dig_port->port_data.streams[0].stream_type = hdcp->content_type;
> +
> ret = hdcp2_verify_mprime(connector, &msgs.stream_ready);
>
> out:
> @@ -1728,7 +1741,9 @@ hdcp2_propagate_stream_management_info(struct intel_connector *connector)
>
> static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
> {
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct intel_hdcp *hdcp = &connector->hdcp;
> int ret, i, tries = 3;
>
> @@ -1742,8 +1757,7 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
> ret);
> break;
> }
> - hdcp->port_data.streams[0].stream_type =
> - hdcp->content_type;
> + data->streams[0].stream_type = hdcp->content_type;
> ret = hdcp2_authenticate_port(connector);
> if (!ret)
> break;
> @@ -1986,8 +2000,8 @@ static int initialize_hdcp_port_data(struct intel_connector *connector,
> const struct intel_hdcp_shim *shim)
> {
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct intel_hdcp *hdcp = &connector->hdcp;
> - struct hdcp_port_data *data = &hdcp->port_data;
> enum port port = dig_port->base.port;
>
> if (INTEL_GEN(dev_priv) < 12)
> @@ -2009,16 +2023,15 @@ static int initialize_hdcp_port_data(struct intel_connector *connector,
> data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED;
> data->protocol = (u8)shim->protocol;
>
> - data->k = 1;
> if (!data->streams)
> - data->streams = kcalloc(data->k,
> + data->streams = kcalloc(INTEL_NUM_PIPES(dev_priv),
> sizeof(struct hdcp2_streamid_type),
> GFP_KERNEL);
> if (!data->streams) {
> drm_err(&dev_priv->drm, "Out of Memory\n");
> return -ENOMEM;
> }
> -
> + /* For SST */
> data->streams[0].stream_id = 0;
> data->streams[0].stream_type = hdcp->content_type;
>
> @@ -2097,7 +2110,7 @@ int intel_hdcp_init(struct intel_connector *connector,
> hdcp->hdcp2_supported);
> if (ret) {
> hdcp->hdcp2_supported = false;
> - kfree(hdcp->port_data.streams);
> + kfree(dig_port->port_data.streams);
> return ret;
> }
>
> @@ -2137,7 +2150,7 @@ int intel_hdcp_enable(struct intel_connector *connector,
> }
>
> if (INTEL_GEN(dev_priv) >= 12)
> - hdcp->port_data.fw_tc = intel_get_mei_fw_tc(hdcp->cpu_transcoder);
> + dig_port->port_data.fw_tc = intel_get_mei_fw_tc(hdcp->cpu_transcoder);
>
> /*
> * Considering that HDCP2.2 is more secure than HDCP1.4, If the setup
> @@ -2307,7 +2320,6 @@ void intel_hdcp_cleanup(struct intel_connector *connector)
> drm_WARN_ON(connector->base.dev, work_pending(&hdcp->prop_work));
>
> mutex_lock(&hdcp->mutex);
> - kfree(hdcp->port_data.streams);
> hdcp->shim = NULL;
> mutex_unlock(&hdcp->mutex);
> }
> --
> 2.26.2
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread
* [PATCH v4 10/16] misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
@ 2020-10-27 16:42 ` Anshuman Gupta
-1 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:42 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: jani.nikula, uma.shankar, seanpaul, Anshuman Gupta,
Tomas Winkler, juston.li
Fix the size of WIRED_REPEATER_AUTH_STREAM_REQ cmd buffer size.
It is based upon the actual number of MST streams and size
of wired_cmd_repeater_auth_stream_req_in.
Excluding the size of hdcp_cmd_header.
v2:
hdcp_cmd_header size annotation nitpick. [Tomas]
Cc: Tomas Winkler <tomas.winkler@intel.com>
Cc: Ramalingam C <ramalingam.c@intel.com>
Acked-by: Tomas Winkler <tomas.winkler@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/misc/mei/hdcp/mei_hdcp.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index 9ae9669e46ea..3506a3534294 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -569,8 +569,7 @@ static int mei_hdcp_verify_mprime(struct device *dev,
verify_mprime_in->header.api_version = HDCP_API_VERSION;
verify_mprime_in->header.command_id = WIRED_REPEATER_AUTH_STREAM_REQ;
verify_mprime_in->header.status = ME_HDCP_STATUS_SUCCESS;
- verify_mprime_in->header.buffer_len =
- WIRED_CMD_BUF_LEN_REPEATER_AUTH_STREAM_REQ_MIN_IN;
+ verify_mprime_in->header.buffer_len = cmd_size - sizeof(verify_mprime_in->header);
verify_mprime_in->port.integrated_port_type = data->port_type;
verify_mprime_in->port.physical_port = (u8)data->fw_ddi;
--
2.26.2
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^ permalink raw reply related [flat|nested] 111+ messages in thread
* [Intel-gfx] [PATCH v4 10/16] misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len
@ 2020-10-27 16:42 ` Anshuman Gupta
0 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:42 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula, seanpaul, Tomas Winkler
Fix the size of WIRED_REPEATER_AUTH_STREAM_REQ cmd buffer size.
It is based upon the actual number of MST streams and size
of wired_cmd_repeater_auth_stream_req_in.
Excluding the size of hdcp_cmd_header.
v2:
hdcp_cmd_header size annotation nitpick. [Tomas]
Cc: Tomas Winkler <tomas.winkler@intel.com>
Cc: Ramalingam C <ramalingam.c@intel.com>
Acked-by: Tomas Winkler <tomas.winkler@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/misc/mei/hdcp/mei_hdcp.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index 9ae9669e46ea..3506a3534294 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -569,8 +569,7 @@ static int mei_hdcp_verify_mprime(struct device *dev,
verify_mprime_in->header.api_version = HDCP_API_VERSION;
verify_mprime_in->header.command_id = WIRED_REPEATER_AUTH_STREAM_REQ;
verify_mprime_in->header.status = ME_HDCP_STATUS_SUCCESS;
- verify_mprime_in->header.buffer_len =
- WIRED_CMD_BUF_LEN_REPEATER_AUTH_STREAM_REQ_MIN_IN;
+ verify_mprime_in->header.buffer_len = cmd_size - sizeof(verify_mprime_in->header);
verify_mprime_in->port.integrated_port_type = data->port_type;
verify_mprime_in->port.physical_port = (u8)data->fw_ddi;
--
2.26.2
_______________________________________________
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^ permalink raw reply related [flat|nested] 111+ messages in thread
* Re: [PATCH v4 10/16] misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len
2020-10-27 16:42 ` [Intel-gfx] " Anshuman Gupta
@ 2020-11-05 16:07 ` Ramalingam C
-1 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-05 16:07 UTC (permalink / raw)
To: Anshuman Gupta
Cc: jani.nikula, intel-gfx, dri-devel, uma.shankar, seanpaul,
Tomas Winkler, juston.li
On 2020-10-27 at 22:12:02 +0530, Anshuman Gupta wrote:
> Fix the size of WIRED_REPEATER_AUTH_STREAM_REQ cmd buffer size.
> It is based upon the actual number of MST streams and size
> of wired_cmd_repeater_auth_stream_req_in.
> Excluding the size of hdcp_cmd_header.
>
> v2:
> hdcp_cmd_header size annotation nitpick. [Tomas]
>
> Cc: Tomas Winkler <tomas.winkler@intel.com>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Acked-by: Tomas Winkler <tomas.winkler@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/misc/mei/hdcp/mei_hdcp.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
> index 9ae9669e46ea..3506a3534294 100644
> --- a/drivers/misc/mei/hdcp/mei_hdcp.c
> +++ b/drivers/misc/mei/hdcp/mei_hdcp.c
> @@ -569,8 +569,7 @@ static int mei_hdcp_verify_mprime(struct device *dev,
> verify_mprime_in->header.api_version = HDCP_API_VERSION;
> verify_mprime_in->header.command_id = WIRED_REPEATER_AUTH_STREAM_REQ;
> verify_mprime_in->header.status = ME_HDCP_STATUS_SUCCESS;
> - verify_mprime_in->header.buffer_len =
> - WIRED_CMD_BUF_LEN_REPEATER_AUTH_STREAM_REQ_MIN_IN;
> + verify_mprime_in->header.buffer_len = cmd_size - sizeof(verify_mprime_in->header);
since only this packet is varying in size we need to calculate in
runtime.
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
>
> verify_mprime_in->port.integrated_port_type = data->port_type;
> verify_mprime_in->port.physical_port = (u8)data->fw_ddi;
> --
> 2.26.2
>
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^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [Intel-gfx] [PATCH v4 10/16] misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len
@ 2020-11-05 16:07 ` Ramalingam C
0 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-05 16:07 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: jani.nikula, intel-gfx, dri-devel, seanpaul, Tomas Winkler
On 2020-10-27 at 22:12:02 +0530, Anshuman Gupta wrote:
> Fix the size of WIRED_REPEATER_AUTH_STREAM_REQ cmd buffer size.
> It is based upon the actual number of MST streams and size
> of wired_cmd_repeater_auth_stream_req_in.
> Excluding the size of hdcp_cmd_header.
>
> v2:
> hdcp_cmd_header size annotation nitpick. [Tomas]
>
> Cc: Tomas Winkler <tomas.winkler@intel.com>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Acked-by: Tomas Winkler <tomas.winkler@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/misc/mei/hdcp/mei_hdcp.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
> index 9ae9669e46ea..3506a3534294 100644
> --- a/drivers/misc/mei/hdcp/mei_hdcp.c
> +++ b/drivers/misc/mei/hdcp/mei_hdcp.c
> @@ -569,8 +569,7 @@ static int mei_hdcp_verify_mprime(struct device *dev,
> verify_mprime_in->header.api_version = HDCP_API_VERSION;
> verify_mprime_in->header.command_id = WIRED_REPEATER_AUTH_STREAM_REQ;
> verify_mprime_in->header.status = ME_HDCP_STATUS_SUCCESS;
> - verify_mprime_in->header.buffer_len =
> - WIRED_CMD_BUF_LEN_REPEATER_AUTH_STREAM_REQ_MIN_IN;
> + verify_mprime_in->header.buffer_len = cmd_size - sizeof(verify_mprime_in->header);
since only this packet is varying in size we need to calculate in
runtime.
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
>
> verify_mprime_in->port.integrated_port_type = data->port_type;
> verify_mprime_in->port.physical_port = (u8)data->fw_ddi;
> --
> 2.26.2
>
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^ permalink raw reply [flat|nested] 111+ messages in thread
* [PATCH v4 11/16] drm/hdcp: Max MST content streams
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
@ 2020-10-27 16:42 ` Anshuman Gupta
-1 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:42 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: jani.nikula, uma.shankar, seanpaul, Anshuman Gupta, juston.li
Let's define Maximum MST content streams up to four
generically which can be supported by modern display
controllers.
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Ramalingam C <ramalingam.c@intel.com>
Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
include/drm/drm_hdcp.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
index fe58dbb46962..ac22c246542a 100644
--- a/include/drm/drm_hdcp.h
+++ b/include/drm/drm_hdcp.h
@@ -101,11 +101,11 @@
/* Following Macros take a byte at a time for bit(s) masking */
/*
- * TODO: This has to be changed for DP MST, as multiple stream on
- * same port is possible.
- * For HDCP2.2 on HDMI and DP SST this value is always 1.
+ * TODO: HDCP_2_2_MAX_CONTENT_STREAMS_CNT is based upon actual
+ * H/W MST streams capacity.
+ * This required to be moved out to platform specific header.
*/
-#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1
+#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 4
#define HDCP_2_2_TXCAP_MASK_LEN 2
#define HDCP_2_2_RXCAPS_LEN 3
#define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0))
--
2.26.2
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^ permalink raw reply related [flat|nested] 111+ messages in thread
* [Intel-gfx] [PATCH v4 11/16] drm/hdcp: Max MST content streams
@ 2020-10-27 16:42 ` Anshuman Gupta
0 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:42 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula, seanpaul
Let's define Maximum MST content streams up to four
generically which can be supported by modern display
controllers.
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Ramalingam C <ramalingam.c@intel.com>
Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
include/drm/drm_hdcp.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
index fe58dbb46962..ac22c246542a 100644
--- a/include/drm/drm_hdcp.h
+++ b/include/drm/drm_hdcp.h
@@ -101,11 +101,11 @@
/* Following Macros take a byte at a time for bit(s) masking */
/*
- * TODO: This has to be changed for DP MST, as multiple stream on
- * same port is possible.
- * For HDCP2.2 on HDMI and DP SST this value is always 1.
+ * TODO: HDCP_2_2_MAX_CONTENT_STREAMS_CNT is based upon actual
+ * H/W MST streams capacity.
+ * This required to be moved out to platform specific header.
*/
-#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1
+#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 4
#define HDCP_2_2_TXCAP_MASK_LEN 2
#define HDCP_2_2_RXCAPS_LEN 3
#define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0))
--
2.26.2
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 111+ messages in thread
* Re: [PATCH v4 11/16] drm/hdcp: Max MST content streams
2020-10-27 16:42 ` [Intel-gfx] " Anshuman Gupta
@ 2020-11-05 16:09 ` Ramalingam C
-1 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-05 16:09 UTC (permalink / raw)
To: Anshuman Gupta
Cc: jani.nikula, intel-gfx, dri-devel, uma.shankar, seanpaul, juston.li
On 2020-10-27 at 22:12:03 +0530, Anshuman Gupta wrote:
> Let's define Maximum MST content streams up to four
> generically which can be supported by modern display
> controllers.
>
> Cc: Sean Paul <seanpaul@chromium.org>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> include/drm/drm_hdcp.h | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
> index fe58dbb46962..ac22c246542a 100644
> --- a/include/drm/drm_hdcp.h
> +++ b/include/drm/drm_hdcp.h
> @@ -101,11 +101,11 @@
>
> /* Following Macros take a byte at a time for bit(s) masking */
> /*
> - * TODO: This has to be changed for DP MST, as multiple stream on
> - * same port is possible.
> - * For HDCP2.2 on HDMI and DP SST this value is always 1.
> + * TODO: HDCP_2_2_MAX_CONTENT_STREAMS_CNT is based upon actual
> + * H/W MST streams capacity.
> + * This required to be moved out to platform specific header.
> */
> -#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1
> +#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 4
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
> #define HDCP_2_2_TXCAP_MASK_LEN 2
> #define HDCP_2_2_RXCAPS_LEN 3
> #define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0))
> --
> 2.26.2
>
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [Intel-gfx] [PATCH v4 11/16] drm/hdcp: Max MST content streams
@ 2020-11-05 16:09 ` Ramalingam C
0 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-05 16:09 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: jani.nikula, intel-gfx, dri-devel, seanpaul
On 2020-10-27 at 22:12:03 +0530, Anshuman Gupta wrote:
> Let's define Maximum MST content streams up to four
> generically which can be supported by modern display
> controllers.
>
> Cc: Sean Paul <seanpaul@chromium.org>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> include/drm/drm_hdcp.h | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
> index fe58dbb46962..ac22c246542a 100644
> --- a/include/drm/drm_hdcp.h
> +++ b/include/drm/drm_hdcp.h
> @@ -101,11 +101,11 @@
>
> /* Following Macros take a byte at a time for bit(s) masking */
> /*
> - * TODO: This has to be changed for DP MST, as multiple stream on
> - * same port is possible.
> - * For HDCP2.2 on HDMI and DP SST this value is always 1.
> + * TODO: HDCP_2_2_MAX_CONTENT_STREAMS_CNT is based upon actual
> + * H/W MST streams capacity.
> + * This required to be moved out to platform specific header.
> */
> -#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1
> +#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 4
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
> #define HDCP_2_2_TXCAP_MASK_LEN 2
> #define HDCP_2_2_RXCAPS_LEN 3
> #define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0))
> --
> 2.26.2
>
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread
* [PATCH v4 12/16] drm/i915/hdcp: MST streams support in hdcp port_data
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
@ 2020-10-27 16:42 ` Anshuman Gupta
-1 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:42 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: jani.nikula, uma.shankar, seanpaul, Anshuman Gupta, juston.li
Add support for multiple mst stream in hdcp port data
which will be used by RepeaterAuthStreamManage msg and
HDCP 2.2 security f/w for m' validation.
v2:
Init the hdcp port data k for HDMI/DP SST strem.
v3:
Cosmetic changes. [Uma]
Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
.../drm/i915/display/intel_display_types.h | 4 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 103 +++++++++++++++---
2 files changed, 92 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 749c3a7e0b45..24e0067c2e7c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1445,10 +1445,12 @@ struct intel_digital_port {
enum phy_fia tc_phy_fia;
u8 tc_phy_fia_idx;
- /* protects num_hdcp_streams reference count, port_data */
+ /* protects num_hdcp_streams reference count, port_data and port_auth */
struct mutex hdcp_mutex;
/* the number of pipes using HDCP signalling out of this port */
unsigned int num_hdcp_streams;
+ /* port HDCP auth status */
+ bool port_auth;
/* HDCP port data need to pass to security f/w */
struct hdcp_port_data port_data;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index a5ec4f72f50f..1df6d4a23476 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -26,6 +26,64 @@
#define KEY_LOAD_TRIES 5
#define HDCP2_LC_RETRY_CNT 3
+static int intel_conn_to_vcpi(struct intel_connector *connector)
+{
+ /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
+ return connector->port ? connector->port->vcpi.vcpi : 0;
+}
+
+static int
+intel_hdcp_required_content_stream(struct intel_digital_port *dig_port)
+{
+ struct drm_connector_list_iter conn_iter;
+ struct intel_digital_port *conn_dig_port;
+ struct intel_connector *connector;
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct hdcp_port_data *data = &dig_port->port_data;
+ bool enforce_type0 = false;
+ int k;
+
+ if (dig_port->port_auth)
+ return 0;
+
+ drm_connector_list_iter_begin(&i915->drm, &conn_iter);
+ for_each_intel_connector_iter(connector, &conn_iter) {
+ if (!intel_encoder_is_mst(intel_attached_encoder(connector)))
+ continue;
+
+ conn_dig_port = intel_attached_dig_port(connector);
+ if (conn_dig_port != dig_port)
+ continue;
+
+ if (connector->base.status == connector_status_disconnected)
+ continue;
+
+ if (!enforce_type0 && !intel_hdcp2_capable(connector))
+ enforce_type0 = true;
+
+ data->streams[data->k].stream_id = intel_conn_to_vcpi(connector);
+ data->k++;
+
+ /* if there is only one active stream */
+ if (dig_port->dp.active_mst_links <= 1)
+ break;
+ }
+ drm_connector_list_iter_end(&conn_iter);
+
+ if (drm_WARN_ON(&i915->drm, data->k > INTEL_NUM_PIPES(i915) || data->k == 0))
+ return -EINVAL;
+
+ /*
+ * Apply common protection level across all streams in DP MST Topology.
+ * Use highest supported content type for all streams in DP MST Topology.
+ */
+ for (k = 0; k < data->k; k++)
+ data->streams[k].stream_type =
+ enforce_type0 ? DRM_MODE_HDCP_CONTENT_TYPE0 : DRM_MODE_HDCP_CONTENT_TYPE1;
+
+ return 0;
+}
+
static
bool intel_hdcp_is_ksv_valid(u8 *ksv)
{
@@ -1474,13 +1532,14 @@ static
int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
{
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct intel_hdcp *hdcp = &connector->hdcp;
union {
struct hdcp2_rep_stream_manage stream_manage;
struct hdcp2_rep_stream_ready stream_ready;
} msgs;
const struct intel_hdcp_shim *shim = hdcp->shim;
- int ret;
+ int ret, streams_size_delta, i;
if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX)
return -ERANGE;
@@ -1489,16 +1548,18 @@ int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
msgs.stream_manage.msg_id = HDCP_2_2_REP_STREAM_MANAGE;
drm_hdcp_cpu_to_be24(msgs.stream_manage.seq_num_m, hdcp->seq_num_m);
- /* K no of streams is fixed as 1. Stored as big-endian. */
- msgs.stream_manage.k = cpu_to_be16(1);
+ msgs.stream_manage.k = cpu_to_be16(data->k);
- /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
- msgs.stream_manage.streams[0].stream_id = 0;
- msgs.stream_manage.streams[0].stream_type = hdcp->content_type;
+ for (i = 0; i < data->k; i++) {
+ msgs.stream_manage.streams[i].stream_id = data->streams[i].stream_id;
+ msgs.stream_manage.streams[i].stream_type = data->streams[i].stream_type;
+ }
+ streams_size_delta = (HDCP_2_2_MAX_CONTENT_STREAMS_CNT - data->k) *
+ sizeof(struct hdcp2_streamid_type);
/* Send it to Repeater */
ret = shim->write_2_2_msg(dig_port, &msgs.stream_manage,
- sizeof(msgs.stream_manage));
+ sizeof(msgs.stream_manage) - streams_size_delta);
if (ret < 0)
goto out;
@@ -1507,8 +1568,7 @@ int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
if (ret < 0)
goto out;
- dig_port->port_data.seq_num_m = hdcp->seq_num_m;
- dig_port->port_data.streams[0].stream_type = hdcp->content_type;
+ data->seq_num_m = hdcp->seq_num_m;
ret = hdcp2_verify_mprime(connector, &msgs.stream_ready);
@@ -1669,6 +1729,7 @@ static int hdcp2_enable_encryption(struct intel_connector *connector)
port),
LINK_ENCRYPTION_STATUS,
HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
+ dig_port->port_auth = true;
return ret;
}
@@ -1743,11 +1804,9 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
{
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
- struct hdcp_port_data *data = &dig_port->port_data;
- struct intel_hdcp *hdcp = &connector->hdcp;
- int ret, i, tries = 3;
+ int ret = 0, i, tries = 3;
- for (i = 0; i < tries; i++) {
+ for (i = 0; i < tries && !dig_port->port_auth; i++) {
ret = hdcp2_authenticate_sink(connector);
if (!ret) {
ret = hdcp2_propagate_stream_management_info(connector);
@@ -1757,7 +1816,7 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
ret);
break;
}
- data->streams[0].stream_type = hdcp->content_type;
+
ret = hdcp2_authenticate_port(connector);
if (!ret)
break;
@@ -1792,7 +1851,9 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
static int _intel_hdcp2_enable(struct intel_connector *connector)
{
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct intel_hdcp *hdcp = &connector->hdcp;
int ret;
@@ -1800,6 +1861,16 @@ static int _intel_hdcp2_enable(struct intel_connector *connector)
connector->base.name, connector->base.base.id,
hdcp->content_type);
+ /* Stream which requires encryption */
+ if (!intel_encoder_is_mst(intel_attached_encoder(connector))) {
+ data->k = 1;
+ data->streams[0].stream_type = hdcp->content_type;
+ } else {
+ ret = intel_hdcp_required_content_stream(dig_port);
+ if (ret)
+ return ret;
+ }
+
ret = hdcp2_authenticate_and_encrypt(connector);
if (ret) {
drm_dbg_kms(&i915->drm, "HDCP2 Type%d Enabling Failed. (%d)\n",
@@ -1817,7 +1888,9 @@ static int _intel_hdcp2_enable(struct intel_connector *connector)
static int _intel_hdcp2_disable(struct intel_connector *connector)
{
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct hdcp_port_data *data = &dig_port->port_data;
int ret;
drm_dbg_kms(&i915->drm, "[%s:%d] HDCP2.2 is being Disabled\n",
@@ -1829,6 +1902,8 @@ static int _intel_hdcp2_disable(struct intel_connector *connector)
drm_dbg_kms(&i915->drm, "Port deauth failed.\n");
connector->hdcp.hdcp2_encrypted = false;
+ dig_port->port_auth = false;
+ data->k = 0;
return ret;
}
--
2.26.2
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^ permalink raw reply related [flat|nested] 111+ messages in thread* [Intel-gfx] [PATCH v4 12/16] drm/i915/hdcp: MST streams support in hdcp port_data
@ 2020-10-27 16:42 ` Anshuman Gupta
0 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:42 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula, seanpaul
Add support for multiple mst stream in hdcp port data
which will be used by RepeaterAuthStreamManage msg and
HDCP 2.2 security f/w for m' validation.
v2:
Init the hdcp port data k for HDMI/DP SST strem.
v3:
Cosmetic changes. [Uma]
Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
.../drm/i915/display/intel_display_types.h | 4 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 103 +++++++++++++++---
2 files changed, 92 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 749c3a7e0b45..24e0067c2e7c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1445,10 +1445,12 @@ struct intel_digital_port {
enum phy_fia tc_phy_fia;
u8 tc_phy_fia_idx;
- /* protects num_hdcp_streams reference count, port_data */
+ /* protects num_hdcp_streams reference count, port_data and port_auth */
struct mutex hdcp_mutex;
/* the number of pipes using HDCP signalling out of this port */
unsigned int num_hdcp_streams;
+ /* port HDCP auth status */
+ bool port_auth;
/* HDCP port data need to pass to security f/w */
struct hdcp_port_data port_data;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index a5ec4f72f50f..1df6d4a23476 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -26,6 +26,64 @@
#define KEY_LOAD_TRIES 5
#define HDCP2_LC_RETRY_CNT 3
+static int intel_conn_to_vcpi(struct intel_connector *connector)
+{
+ /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
+ return connector->port ? connector->port->vcpi.vcpi : 0;
+}
+
+static int
+intel_hdcp_required_content_stream(struct intel_digital_port *dig_port)
+{
+ struct drm_connector_list_iter conn_iter;
+ struct intel_digital_port *conn_dig_port;
+ struct intel_connector *connector;
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct hdcp_port_data *data = &dig_port->port_data;
+ bool enforce_type0 = false;
+ int k;
+
+ if (dig_port->port_auth)
+ return 0;
+
+ drm_connector_list_iter_begin(&i915->drm, &conn_iter);
+ for_each_intel_connector_iter(connector, &conn_iter) {
+ if (!intel_encoder_is_mst(intel_attached_encoder(connector)))
+ continue;
+
+ conn_dig_port = intel_attached_dig_port(connector);
+ if (conn_dig_port != dig_port)
+ continue;
+
+ if (connector->base.status == connector_status_disconnected)
+ continue;
+
+ if (!enforce_type0 && !intel_hdcp2_capable(connector))
+ enforce_type0 = true;
+
+ data->streams[data->k].stream_id = intel_conn_to_vcpi(connector);
+ data->k++;
+
+ /* if there is only one active stream */
+ if (dig_port->dp.active_mst_links <= 1)
+ break;
+ }
+ drm_connector_list_iter_end(&conn_iter);
+
+ if (drm_WARN_ON(&i915->drm, data->k > INTEL_NUM_PIPES(i915) || data->k == 0))
+ return -EINVAL;
+
+ /*
+ * Apply common protection level across all streams in DP MST Topology.
+ * Use highest supported content type for all streams in DP MST Topology.
+ */
+ for (k = 0; k < data->k; k++)
+ data->streams[k].stream_type =
+ enforce_type0 ? DRM_MODE_HDCP_CONTENT_TYPE0 : DRM_MODE_HDCP_CONTENT_TYPE1;
+
+ return 0;
+}
+
static
bool intel_hdcp_is_ksv_valid(u8 *ksv)
{
@@ -1474,13 +1532,14 @@ static
int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
{
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct intel_hdcp *hdcp = &connector->hdcp;
union {
struct hdcp2_rep_stream_manage stream_manage;
struct hdcp2_rep_stream_ready stream_ready;
} msgs;
const struct intel_hdcp_shim *shim = hdcp->shim;
- int ret;
+ int ret, streams_size_delta, i;
if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX)
return -ERANGE;
@@ -1489,16 +1548,18 @@ int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
msgs.stream_manage.msg_id = HDCP_2_2_REP_STREAM_MANAGE;
drm_hdcp_cpu_to_be24(msgs.stream_manage.seq_num_m, hdcp->seq_num_m);
- /* K no of streams is fixed as 1. Stored as big-endian. */
- msgs.stream_manage.k = cpu_to_be16(1);
+ msgs.stream_manage.k = cpu_to_be16(data->k);
- /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
- msgs.stream_manage.streams[0].stream_id = 0;
- msgs.stream_manage.streams[0].stream_type = hdcp->content_type;
+ for (i = 0; i < data->k; i++) {
+ msgs.stream_manage.streams[i].stream_id = data->streams[i].stream_id;
+ msgs.stream_manage.streams[i].stream_type = data->streams[i].stream_type;
+ }
+ streams_size_delta = (HDCP_2_2_MAX_CONTENT_STREAMS_CNT - data->k) *
+ sizeof(struct hdcp2_streamid_type);
/* Send it to Repeater */
ret = shim->write_2_2_msg(dig_port, &msgs.stream_manage,
- sizeof(msgs.stream_manage));
+ sizeof(msgs.stream_manage) - streams_size_delta);
if (ret < 0)
goto out;
@@ -1507,8 +1568,7 @@ int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
if (ret < 0)
goto out;
- dig_port->port_data.seq_num_m = hdcp->seq_num_m;
- dig_port->port_data.streams[0].stream_type = hdcp->content_type;
+ data->seq_num_m = hdcp->seq_num_m;
ret = hdcp2_verify_mprime(connector, &msgs.stream_ready);
@@ -1669,6 +1729,7 @@ static int hdcp2_enable_encryption(struct intel_connector *connector)
port),
LINK_ENCRYPTION_STATUS,
HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
+ dig_port->port_auth = true;
return ret;
}
@@ -1743,11 +1804,9 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
{
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
- struct hdcp_port_data *data = &dig_port->port_data;
- struct intel_hdcp *hdcp = &connector->hdcp;
- int ret, i, tries = 3;
+ int ret = 0, i, tries = 3;
- for (i = 0; i < tries; i++) {
+ for (i = 0; i < tries && !dig_port->port_auth; i++) {
ret = hdcp2_authenticate_sink(connector);
if (!ret) {
ret = hdcp2_propagate_stream_management_info(connector);
@@ -1757,7 +1816,7 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
ret);
break;
}
- data->streams[0].stream_type = hdcp->content_type;
+
ret = hdcp2_authenticate_port(connector);
if (!ret)
break;
@@ -1792,7 +1851,9 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
static int _intel_hdcp2_enable(struct intel_connector *connector)
{
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct intel_hdcp *hdcp = &connector->hdcp;
int ret;
@@ -1800,6 +1861,16 @@ static int _intel_hdcp2_enable(struct intel_connector *connector)
connector->base.name, connector->base.base.id,
hdcp->content_type);
+ /* Stream which requires encryption */
+ if (!intel_encoder_is_mst(intel_attached_encoder(connector))) {
+ data->k = 1;
+ data->streams[0].stream_type = hdcp->content_type;
+ } else {
+ ret = intel_hdcp_required_content_stream(dig_port);
+ if (ret)
+ return ret;
+ }
+
ret = hdcp2_authenticate_and_encrypt(connector);
if (ret) {
drm_dbg_kms(&i915->drm, "HDCP2 Type%d Enabling Failed. (%d)\n",
@@ -1817,7 +1888,9 @@ static int _intel_hdcp2_enable(struct intel_connector *connector)
static int _intel_hdcp2_disable(struct intel_connector *connector)
{
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct hdcp_port_data *data = &dig_port->port_data;
int ret;
drm_dbg_kms(&i915->drm, "[%s:%d] HDCP2.2 is being Disabled\n",
@@ -1829,6 +1902,8 @@ static int _intel_hdcp2_disable(struct intel_connector *connector)
drm_dbg_kms(&i915->drm, "Port deauth failed.\n");
connector->hdcp.hdcp2_encrypted = false;
+ dig_port->port_auth = false;
+ data->k = 0;
return ret;
}
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 111+ messages in thread* RE: [PATCH v4 12/16] drm/i915/hdcp: MST streams support in hdcp port_data
2020-10-27 16:42 ` [Intel-gfx] " Anshuman Gupta
@ 2020-11-02 7:49 ` Shankar, Uma
-1 siblings, 0 replies; 111+ messages in thread
From: Shankar, Uma @ 2020-11-02 7:49 UTC (permalink / raw)
To: Gupta, Anshuman, intel-gfx, dri-devel
Cc: Nikula, Jani, seanpaul, Li, Juston, Gupta, Anshuman
> -----Original Message-----
> From: Anshuman Gupta <anshuman.gupta@intel.com>
> Sent: Tuesday, October 27, 2020 10:12 PM
> To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: seanpaul@chromium.org; Nikula, Jani <jani.nikula@intel.com>; C,
> Ramalingam <ramalingam.c@intel.com>; Li, Juston <juston.li@intel.com>;
> Shankar, Uma <uma.shankar@intel.com>; Gupta, Anshuman
> <anshuman.gupta@intel.com>
> Subject: [PATCH v4 12/16] drm/i915/hdcp: MST streams support in hdcp
> port_data
>
> Add support for multiple mst stream in hdcp port data which will be used by
> RepeaterAuthStreamManage msg and HDCP 2.2 security f/w for m' validation.
>
> v2:
> Init the hdcp port data k for HDMI/DP SST strem.
>
> v3:
> Cosmetic changes. [Uma]
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 4 +-
> drivers/gpu/drm/i915/display/intel_hdcp.c | 103 +++++++++++++++---
> 2 files changed, 92 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 749c3a7e0b45..24e0067c2e7c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1445,10 +1445,12 @@ struct intel_digital_port {
> enum phy_fia tc_phy_fia;
> u8 tc_phy_fia_idx;
>
> - /* protects num_hdcp_streams reference count, port_data */
> + /* protects num_hdcp_streams reference count, port_data and
> port_auth
> +*/
> struct mutex hdcp_mutex;
> /* the number of pipes using HDCP signalling out of this port */
> unsigned int num_hdcp_streams;
> + /* port HDCP auth status */
> + bool port_auth;
> /* HDCP port data need to pass to security f/w */
> struct hdcp_port_data port_data;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index a5ec4f72f50f..1df6d4a23476 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -26,6 +26,64 @@
> #define KEY_LOAD_TRIES 5
> #define HDCP2_LC_RETRY_CNT 3
>
> +static int intel_conn_to_vcpi(struct intel_connector *connector) {
> + /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
> + return connector->port ? connector->port->vcpi.vcpi : 0;
> +}
> +
> +static int
> +intel_hdcp_required_content_stream(struct intel_digital_port *dig_port)
> +{
> + struct drm_connector_list_iter conn_iter;
> + struct intel_digital_port *conn_dig_port;
> + struct intel_connector *connector;
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + struct hdcp_port_data *data = &dig_port->port_data;
> + bool enforce_type0 = false;
> + int k;
> +
> + if (dig_port->port_auth)
> + return 0;
> +
> + drm_connector_list_iter_begin(&i915->drm, &conn_iter);
> + for_each_intel_connector_iter(connector, &conn_iter) {
> + if (!intel_encoder_is_mst(intel_attached_encoder(connector)))
> + continue;
> +
> + conn_dig_port = intel_attached_dig_port(connector);
> + if (conn_dig_port != dig_port)
> + continue;
> +
> + if (connector->base.status == connector_status_disconnected)
> + continue;
> +
> + if (!enforce_type0 && !intel_hdcp2_capable(connector))
> + enforce_type0 = true;
> +
> + data->streams[data->k].stream_id =
> intel_conn_to_vcpi(connector);
> + data->k++;
> +
> + /* if there is only one active stream */
> + if (dig_port->dp.active_mst_links <= 1)
> + break;
> + }
> + drm_connector_list_iter_end(&conn_iter);
> +
> + if (drm_WARN_ON(&i915->drm, data->k > INTEL_NUM_PIPES(i915) ||
> data->k == 0))
> + return -EINVAL;
> +
> + /*
> + * Apply common protection level across all streams in DP MST Topology.
> + * Use highest supported content type for all streams in DP MST
> Topology.
> + */
> + for (k = 0; k < data->k; k++)
> + data->streams[k].stream_type =
> + enforce_type0 ? DRM_MODE_HDCP_CONTENT_TYPE0 :
> +DRM_MODE_HDCP_CONTENT_TYPE1;
> +
> + return 0;
> +}
> +
> static
> bool intel_hdcp_is_ksv_valid(u8 *ksv)
> {
> @@ -1474,13 +1532,14 @@ static
> int _hdcp2_propagate_stream_management_info(struct intel_connector
> *connector) {
> struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct intel_hdcp *hdcp = &connector->hdcp;
> union {
> struct hdcp2_rep_stream_manage stream_manage;
> struct hdcp2_rep_stream_ready stream_ready;
> } msgs;
> const struct intel_hdcp_shim *shim = hdcp->shim;
> - int ret;
> + int ret, streams_size_delta, i;
>
> if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX)
> return -ERANGE;
> @@ -1489,16 +1548,18 @@ int
> _hdcp2_propagate_stream_management_info(struct intel_connector
> *connector)
> msgs.stream_manage.msg_id = HDCP_2_2_REP_STREAM_MANAGE;
> drm_hdcp_cpu_to_be24(msgs.stream_manage.seq_num_m, hdcp-
> >seq_num_m);
>
> - /* K no of streams is fixed as 1. Stored as big-endian. */
> - msgs.stream_manage.k = cpu_to_be16(1);
> + msgs.stream_manage.k = cpu_to_be16(data->k);
>
> - /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
> - msgs.stream_manage.streams[0].stream_id = 0;
> - msgs.stream_manage.streams[0].stream_type = hdcp->content_type;
> + for (i = 0; i < data->k; i++) {
> + msgs.stream_manage.streams[i].stream_id = data-
> >streams[i].stream_id;
> + msgs.stream_manage.streams[i].stream_type = data-
> >streams[i].stream_type;
> + }
>
> + streams_size_delta = (HDCP_2_2_MAX_CONTENT_STREAMS_CNT - data-
> >k) *
> + sizeof(struct hdcp2_streamid_type);
> /* Send it to Repeater */
> ret = shim->write_2_2_msg(dig_port, &msgs.stream_manage,
> - sizeof(msgs.stream_manage));
> + sizeof(msgs.stream_manage) -
> streams_size_delta);
> if (ret < 0)
> goto out;
>
> @@ -1507,8 +1568,7 @@ int
> _hdcp2_propagate_stream_management_info(struct intel_connector
> *connector)
> if (ret < 0)
> goto out;
>
> - dig_port->port_data.seq_num_m = hdcp->seq_num_m;
> - dig_port->port_data.streams[0].stream_type = hdcp->content_type;
> + data->seq_num_m = hdcp->seq_num_m;
>
> ret = hdcp2_verify_mprime(connector, &msgs.stream_ready);
>
> @@ -1669,6 +1729,7 @@ static int hdcp2_enable_encryption(struct
> intel_connector *connector)
> port),
> LINK_ENCRYPTION_STATUS,
>
> HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
> + dig_port->port_auth = true;
>
> return ret;
> }
> @@ -1743,11 +1804,9 @@ static int hdcp2_authenticate_and_encrypt(struct
> intel_connector *connector) {
> struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> - struct hdcp_port_data *data = &dig_port->port_data;
> - struct intel_hdcp *hdcp = &connector->hdcp;
> - int ret, i, tries = 3;
> + int ret = 0, i, tries = 3;
>
> - for (i = 0; i < tries; i++) {
> + for (i = 0; i < tries && !dig_port->port_auth; i++) {
> ret = hdcp2_authenticate_sink(connector);
> if (!ret) {
> ret =
> hdcp2_propagate_stream_management_info(connector);
> @@ -1757,7 +1816,7 @@ static int hdcp2_authenticate_and_encrypt(struct
> intel_connector *connector)
> ret);
> break;
> }
> - data->streams[0].stream_type = hdcp->content_type;
> +
> ret = hdcp2_authenticate_port(connector);
> if (!ret)
> break;
> @@ -1792,7 +1851,9 @@ static int hdcp2_authenticate_and_encrypt(struct
> intel_connector *connector)
>
> static int _intel_hdcp2_enable(struct intel_connector *connector) {
> + struct intel_digital_port *dig_port =
> +intel_attached_dig_port(connector);
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct intel_hdcp *hdcp = &connector->hdcp;
> int ret;
>
> @@ -1800,6 +1861,16 @@ static int _intel_hdcp2_enable(struct intel_connector
> *connector)
> connector->base.name, connector->base.base.id,
> hdcp->content_type);
>
> + /* Stream which requires encryption */
> + if (!intel_encoder_is_mst(intel_attached_encoder(connector))) {
> + data->k = 1;
> + data->streams[0].stream_type = hdcp->content_type;
> + } else {
> + ret = intel_hdcp_required_content_stream(dig_port);
> + if (ret)
> + return ret;
> + }
> +
> ret = hdcp2_authenticate_and_encrypt(connector);
> if (ret) {
> drm_dbg_kms(&i915->drm, "HDCP2 Type%d Enabling Failed.
> (%d)\n", @@ -1817,7 +1888,9 @@ static int _intel_hdcp2_enable(struct
> intel_connector *connector)
>
> static int _intel_hdcp2_disable(struct intel_connector *connector) {
> + struct intel_digital_port *dig_port =
> +intel_attached_dig_port(connector);
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct hdcp_port_data *data = &dig_port->port_data;
> int ret;
>
> drm_dbg_kms(&i915->drm, "[%s:%d] HDCP2.2 is being Disabled\n", @@ -
> 1829,6 +1902,8 @@ static int _intel_hdcp2_disable(struct intel_connector
> *connector)
> drm_dbg_kms(&i915->drm, "Port deauth failed.\n");
>
> connector->hdcp.hdcp2_encrypted = false;
> + dig_port->port_auth = false;
> + data->k = 0;
>
> return ret;
> }
> --
> 2.26.2
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 12/16] drm/i915/hdcp: MST streams support in hdcp port_data
@ 2020-11-02 7:49 ` Shankar, Uma
0 siblings, 0 replies; 111+ messages in thread
From: Shankar, Uma @ 2020-11-02 7:49 UTC (permalink / raw)
To: Gupta, Anshuman, intel-gfx, dri-devel; +Cc: Nikula, Jani, seanpaul
> -----Original Message-----
> From: Anshuman Gupta <anshuman.gupta@intel.com>
> Sent: Tuesday, October 27, 2020 10:12 PM
> To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: seanpaul@chromium.org; Nikula, Jani <jani.nikula@intel.com>; C,
> Ramalingam <ramalingam.c@intel.com>; Li, Juston <juston.li@intel.com>;
> Shankar, Uma <uma.shankar@intel.com>; Gupta, Anshuman
> <anshuman.gupta@intel.com>
> Subject: [PATCH v4 12/16] drm/i915/hdcp: MST streams support in hdcp
> port_data
>
> Add support for multiple mst stream in hdcp port data which will be used by
> RepeaterAuthStreamManage msg and HDCP 2.2 security f/w for m' validation.
>
> v2:
> Init the hdcp port data k for HDMI/DP SST strem.
>
> v3:
> Cosmetic changes. [Uma]
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 4 +-
> drivers/gpu/drm/i915/display/intel_hdcp.c | 103 +++++++++++++++---
> 2 files changed, 92 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 749c3a7e0b45..24e0067c2e7c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1445,10 +1445,12 @@ struct intel_digital_port {
> enum phy_fia tc_phy_fia;
> u8 tc_phy_fia_idx;
>
> - /* protects num_hdcp_streams reference count, port_data */
> + /* protects num_hdcp_streams reference count, port_data and
> port_auth
> +*/
> struct mutex hdcp_mutex;
> /* the number of pipes using HDCP signalling out of this port */
> unsigned int num_hdcp_streams;
> + /* port HDCP auth status */
> + bool port_auth;
> /* HDCP port data need to pass to security f/w */
> struct hdcp_port_data port_data;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index a5ec4f72f50f..1df6d4a23476 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -26,6 +26,64 @@
> #define KEY_LOAD_TRIES 5
> #define HDCP2_LC_RETRY_CNT 3
>
> +static int intel_conn_to_vcpi(struct intel_connector *connector) {
> + /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
> + return connector->port ? connector->port->vcpi.vcpi : 0;
> +}
> +
> +static int
> +intel_hdcp_required_content_stream(struct intel_digital_port *dig_port)
> +{
> + struct drm_connector_list_iter conn_iter;
> + struct intel_digital_port *conn_dig_port;
> + struct intel_connector *connector;
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + struct hdcp_port_data *data = &dig_port->port_data;
> + bool enforce_type0 = false;
> + int k;
> +
> + if (dig_port->port_auth)
> + return 0;
> +
> + drm_connector_list_iter_begin(&i915->drm, &conn_iter);
> + for_each_intel_connector_iter(connector, &conn_iter) {
> + if (!intel_encoder_is_mst(intel_attached_encoder(connector)))
> + continue;
> +
> + conn_dig_port = intel_attached_dig_port(connector);
> + if (conn_dig_port != dig_port)
> + continue;
> +
> + if (connector->base.status == connector_status_disconnected)
> + continue;
> +
> + if (!enforce_type0 && !intel_hdcp2_capable(connector))
> + enforce_type0 = true;
> +
> + data->streams[data->k].stream_id =
> intel_conn_to_vcpi(connector);
> + data->k++;
> +
> + /* if there is only one active stream */
> + if (dig_port->dp.active_mst_links <= 1)
> + break;
> + }
> + drm_connector_list_iter_end(&conn_iter);
> +
> + if (drm_WARN_ON(&i915->drm, data->k > INTEL_NUM_PIPES(i915) ||
> data->k == 0))
> + return -EINVAL;
> +
> + /*
> + * Apply common protection level across all streams in DP MST Topology.
> + * Use highest supported content type for all streams in DP MST
> Topology.
> + */
> + for (k = 0; k < data->k; k++)
> + data->streams[k].stream_type =
> + enforce_type0 ? DRM_MODE_HDCP_CONTENT_TYPE0 :
> +DRM_MODE_HDCP_CONTENT_TYPE1;
> +
> + return 0;
> +}
> +
> static
> bool intel_hdcp_is_ksv_valid(u8 *ksv)
> {
> @@ -1474,13 +1532,14 @@ static
> int _hdcp2_propagate_stream_management_info(struct intel_connector
> *connector) {
> struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct intel_hdcp *hdcp = &connector->hdcp;
> union {
> struct hdcp2_rep_stream_manage stream_manage;
> struct hdcp2_rep_stream_ready stream_ready;
> } msgs;
> const struct intel_hdcp_shim *shim = hdcp->shim;
> - int ret;
> + int ret, streams_size_delta, i;
>
> if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX)
> return -ERANGE;
> @@ -1489,16 +1548,18 @@ int
> _hdcp2_propagate_stream_management_info(struct intel_connector
> *connector)
> msgs.stream_manage.msg_id = HDCP_2_2_REP_STREAM_MANAGE;
> drm_hdcp_cpu_to_be24(msgs.stream_manage.seq_num_m, hdcp-
> >seq_num_m);
>
> - /* K no of streams is fixed as 1. Stored as big-endian. */
> - msgs.stream_manage.k = cpu_to_be16(1);
> + msgs.stream_manage.k = cpu_to_be16(data->k);
>
> - /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
> - msgs.stream_manage.streams[0].stream_id = 0;
> - msgs.stream_manage.streams[0].stream_type = hdcp->content_type;
> + for (i = 0; i < data->k; i++) {
> + msgs.stream_manage.streams[i].stream_id = data-
> >streams[i].stream_id;
> + msgs.stream_manage.streams[i].stream_type = data-
> >streams[i].stream_type;
> + }
>
> + streams_size_delta = (HDCP_2_2_MAX_CONTENT_STREAMS_CNT - data-
> >k) *
> + sizeof(struct hdcp2_streamid_type);
> /* Send it to Repeater */
> ret = shim->write_2_2_msg(dig_port, &msgs.stream_manage,
> - sizeof(msgs.stream_manage));
> + sizeof(msgs.stream_manage) -
> streams_size_delta);
> if (ret < 0)
> goto out;
>
> @@ -1507,8 +1568,7 @@ int
> _hdcp2_propagate_stream_management_info(struct intel_connector
> *connector)
> if (ret < 0)
> goto out;
>
> - dig_port->port_data.seq_num_m = hdcp->seq_num_m;
> - dig_port->port_data.streams[0].stream_type = hdcp->content_type;
> + data->seq_num_m = hdcp->seq_num_m;
>
> ret = hdcp2_verify_mprime(connector, &msgs.stream_ready);
>
> @@ -1669,6 +1729,7 @@ static int hdcp2_enable_encryption(struct
> intel_connector *connector)
> port),
> LINK_ENCRYPTION_STATUS,
>
> HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
> + dig_port->port_auth = true;
>
> return ret;
> }
> @@ -1743,11 +1804,9 @@ static int hdcp2_authenticate_and_encrypt(struct
> intel_connector *connector) {
> struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> - struct hdcp_port_data *data = &dig_port->port_data;
> - struct intel_hdcp *hdcp = &connector->hdcp;
> - int ret, i, tries = 3;
> + int ret = 0, i, tries = 3;
>
> - for (i = 0; i < tries; i++) {
> + for (i = 0; i < tries && !dig_port->port_auth; i++) {
> ret = hdcp2_authenticate_sink(connector);
> if (!ret) {
> ret =
> hdcp2_propagate_stream_management_info(connector);
> @@ -1757,7 +1816,7 @@ static int hdcp2_authenticate_and_encrypt(struct
> intel_connector *connector)
> ret);
> break;
> }
> - data->streams[0].stream_type = hdcp->content_type;
> +
> ret = hdcp2_authenticate_port(connector);
> if (!ret)
> break;
> @@ -1792,7 +1851,9 @@ static int hdcp2_authenticate_and_encrypt(struct
> intel_connector *connector)
>
> static int _intel_hdcp2_enable(struct intel_connector *connector) {
> + struct intel_digital_port *dig_port =
> +intel_attached_dig_port(connector);
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct intel_hdcp *hdcp = &connector->hdcp;
> int ret;
>
> @@ -1800,6 +1861,16 @@ static int _intel_hdcp2_enable(struct intel_connector
> *connector)
> connector->base.name, connector->base.base.id,
> hdcp->content_type);
>
> + /* Stream which requires encryption */
> + if (!intel_encoder_is_mst(intel_attached_encoder(connector))) {
> + data->k = 1;
> + data->streams[0].stream_type = hdcp->content_type;
> + } else {
> + ret = intel_hdcp_required_content_stream(dig_port);
> + if (ret)
> + return ret;
> + }
> +
> ret = hdcp2_authenticate_and_encrypt(connector);
> if (ret) {
> drm_dbg_kms(&i915->drm, "HDCP2 Type%d Enabling Failed.
> (%d)\n", @@ -1817,7 +1888,9 @@ static int _intel_hdcp2_enable(struct
> intel_connector *connector)
>
> static int _intel_hdcp2_disable(struct intel_connector *connector) {
> + struct intel_digital_port *dig_port =
> +intel_attached_dig_port(connector);
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct hdcp_port_data *data = &dig_port->port_data;
> int ret;
>
> drm_dbg_kms(&i915->drm, "[%s:%d] HDCP2.2 is being Disabled\n", @@ -
> 1829,6 +1902,8 @@ static int _intel_hdcp2_disable(struct intel_connector
> *connector)
> drm_dbg_kms(&i915->drm, "Port deauth failed.\n");
>
> connector->hdcp.hdcp2_encrypted = false;
> + dig_port->port_auth = false;
> + data->k = 0;
>
> return ret;
> }
> --
> 2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v4 12/16] drm/i915/hdcp: MST streams support in hdcp port_data
2020-10-27 16:42 ` [Intel-gfx] " Anshuman Gupta
@ 2020-11-05 16:34 ` Ramalingam C
-1 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-05 16:34 UTC (permalink / raw)
To: Anshuman Gupta
Cc: jani.nikula, intel-gfx, dri-devel, uma.shankar, seanpaul, juston.li
On 2020-10-27 at 22:12:04 +0530, Anshuman Gupta wrote:
> Add support for multiple mst stream in hdcp port data
> which will be used by RepeaterAuthStreamManage msg and
> HDCP 2.2 security f/w for m' validation.
>
> v2:
> Init the hdcp port data k for HDMI/DP SST strem.
>
> v3:
> Cosmetic changes. [Uma]
>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 4 +-
> drivers/gpu/drm/i915/display/intel_hdcp.c | 103 +++++++++++++++---
> 2 files changed, 92 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 749c3a7e0b45..24e0067c2e7c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1445,10 +1445,12 @@ struct intel_digital_port {
> enum phy_fia tc_phy_fia;
> u8 tc_phy_fia_idx;
>
> - /* protects num_hdcp_streams reference count, port_data */
> + /* protects num_hdcp_streams reference count, port_data and port_auth */
> struct mutex hdcp_mutex;
> /* the number of pipes using HDCP signalling out of this port */
> unsigned int num_hdcp_streams;
> + /* port HDCP auth status */
> + bool port_auth;
> /* HDCP port data need to pass to security f/w */
> struct hdcp_port_data port_data;
since this is no more in hdcp related struct, it will be better to be named as
hdcp_auth_status and hdcp_port_data !?
-Ram
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index a5ec4f72f50f..1df6d4a23476 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -26,6 +26,64 @@
> #define KEY_LOAD_TRIES 5
> #define HDCP2_LC_RETRY_CNT 3
>
> +static int intel_conn_to_vcpi(struct intel_connector *connector)
> +{
> + /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
> + return connector->port ? connector->port->vcpi.vcpi : 0;
> +}
> +
> +static int
> +intel_hdcp_required_content_stream(struct intel_digital_port *dig_port)
> +{
> + struct drm_connector_list_iter conn_iter;
> + struct intel_digital_port *conn_dig_port;
> + struct intel_connector *connector;
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + struct hdcp_port_data *data = &dig_port->port_data;
> + bool enforce_type0 = false;
> + int k;
> +
> + if (dig_port->port_auth)
> + return 0;
> +
> + drm_connector_list_iter_begin(&i915->drm, &conn_iter);
> + for_each_intel_connector_iter(connector, &conn_iter) {
> + if (!intel_encoder_is_mst(intel_attached_encoder(connector)))
> + continue;
> +
> + conn_dig_port = intel_attached_dig_port(connector);
> + if (conn_dig_port != dig_port)
> + continue;
> +
> + if (connector->base.status == connector_status_disconnected)
> + continue;
> +
> + if (!enforce_type0 && !intel_hdcp2_capable(connector))
> + enforce_type0 = true;
> +
> + data->streams[data->k].stream_id = intel_conn_to_vcpi(connector);
> + data->k++;
> +
> + /* if there is only one active stream */
> + if (dig_port->dp.active_mst_links <= 1)
> + break;
> + }
> + drm_connector_list_iter_end(&conn_iter);
> +
> + if (drm_WARN_ON(&i915->drm, data->k > INTEL_NUM_PIPES(i915) || data->k == 0))
> + return -EINVAL;
> +
> + /*
> + * Apply common protection level across all streams in DP MST Topology.
> + * Use highest supported content type for all streams in DP MST Topology.
> + */
> + for (k = 0; k < data->k; k++)
> + data->streams[k].stream_type =
> + enforce_type0 ? DRM_MODE_HDCP_CONTENT_TYPE0 : DRM_MODE_HDCP_CONTENT_TYPE1;
> +
> + return 0;
> +}
> +
> static
> bool intel_hdcp_is_ksv_valid(u8 *ksv)
> {
> @@ -1474,13 +1532,14 @@ static
> int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
> {
> struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct intel_hdcp *hdcp = &connector->hdcp;
> union {
> struct hdcp2_rep_stream_manage stream_manage;
> struct hdcp2_rep_stream_ready stream_ready;
> } msgs;
> const struct intel_hdcp_shim *shim = hdcp->shim;
> - int ret;
> + int ret, streams_size_delta, i;
>
> if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX)
> return -ERANGE;
> @@ -1489,16 +1548,18 @@ int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
> msgs.stream_manage.msg_id = HDCP_2_2_REP_STREAM_MANAGE;
> drm_hdcp_cpu_to_be24(msgs.stream_manage.seq_num_m, hdcp->seq_num_m);
>
> - /* K no of streams is fixed as 1. Stored as big-endian. */
> - msgs.stream_manage.k = cpu_to_be16(1);
> + msgs.stream_manage.k = cpu_to_be16(data->k);
>
> - /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
> - msgs.stream_manage.streams[0].stream_id = 0;
> - msgs.stream_manage.streams[0].stream_type = hdcp->content_type;
> + for (i = 0; i < data->k; i++) {
> + msgs.stream_manage.streams[i].stream_id = data->streams[i].stream_id;
> + msgs.stream_manage.streams[i].stream_type = data->streams[i].stream_type;
> + }
>
> + streams_size_delta = (HDCP_2_2_MAX_CONTENT_STREAMS_CNT - data->k) *
> + sizeof(struct hdcp2_streamid_type);
> /* Send it to Repeater */
> ret = shim->write_2_2_msg(dig_port, &msgs.stream_manage,
> - sizeof(msgs.stream_manage));
> + sizeof(msgs.stream_manage) - streams_size_delta);
> if (ret < 0)
> goto out;
>
> @@ -1507,8 +1568,7 @@ int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
> if (ret < 0)
> goto out;
>
> - dig_port->port_data.seq_num_m = hdcp->seq_num_m;
> - dig_port->port_data.streams[0].stream_type = hdcp->content_type;
> + data->seq_num_m = hdcp->seq_num_m;
>
> ret = hdcp2_verify_mprime(connector, &msgs.stream_ready);
>
> @@ -1669,6 +1729,7 @@ static int hdcp2_enable_encryption(struct intel_connector *connector)
> port),
> LINK_ENCRYPTION_STATUS,
> HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
> + dig_port->port_auth = true;
>
> return ret;
> }
> @@ -1743,11 +1804,9 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
> {
> struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> - struct hdcp_port_data *data = &dig_port->port_data;
> - struct intel_hdcp *hdcp = &connector->hdcp;
> - int ret, i, tries = 3;
> + int ret = 0, i, tries = 3;
>
> - for (i = 0; i < tries; i++) {
> + for (i = 0; i < tries && !dig_port->port_auth; i++) {
> ret = hdcp2_authenticate_sink(connector);
> if (!ret) {
> ret = hdcp2_propagate_stream_management_info(connector);
> @@ -1757,7 +1816,7 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
> ret);
> break;
> }
> - data->streams[0].stream_type = hdcp->content_type;
> +
> ret = hdcp2_authenticate_port(connector);
> if (!ret)
> break;
> @@ -1792,7 +1851,9 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
>
> static int _intel_hdcp2_enable(struct intel_connector *connector)
> {
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct intel_hdcp *hdcp = &connector->hdcp;
> int ret;
>
> @@ -1800,6 +1861,16 @@ static int _intel_hdcp2_enable(struct intel_connector *connector)
> connector->base.name, connector->base.base.id,
> hdcp->content_type);
>
> + /* Stream which requires encryption */
> + if (!intel_encoder_is_mst(intel_attached_encoder(connector))) {
> + data->k = 1;
> + data->streams[0].stream_type = hdcp->content_type;
> + } else {
> + ret = intel_hdcp_required_content_stream(dig_port);
> + if (ret)
> + return ret;
> + }
> +
> ret = hdcp2_authenticate_and_encrypt(connector);
> if (ret) {
> drm_dbg_kms(&i915->drm, "HDCP2 Type%d Enabling Failed. (%d)\n",
> @@ -1817,7 +1888,9 @@ static int _intel_hdcp2_enable(struct intel_connector *connector)
>
> static int _intel_hdcp2_disable(struct intel_connector *connector)
> {
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct hdcp_port_data *data = &dig_port->port_data;
> int ret;
>
> drm_dbg_kms(&i915->drm, "[%s:%d] HDCP2.2 is being Disabled\n",
> @@ -1829,6 +1902,8 @@ static int _intel_hdcp2_disable(struct intel_connector *connector)
> drm_dbg_kms(&i915->drm, "Port deauth failed.\n");
>
> connector->hdcp.hdcp2_encrypted = false;
> + dig_port->port_auth = false;
> + data->k = 0;
>
> return ret;
> }
> --
> 2.26.2
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 12/16] drm/i915/hdcp: MST streams support in hdcp port_data
@ 2020-11-05 16:34 ` Ramalingam C
0 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-05 16:34 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: jani.nikula, intel-gfx, dri-devel, seanpaul
On 2020-10-27 at 22:12:04 +0530, Anshuman Gupta wrote:
> Add support for multiple mst stream in hdcp port data
> which will be used by RepeaterAuthStreamManage msg and
> HDCP 2.2 security f/w for m' validation.
>
> v2:
> Init the hdcp port data k for HDMI/DP SST strem.
>
> v3:
> Cosmetic changes. [Uma]
>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 4 +-
> drivers/gpu/drm/i915/display/intel_hdcp.c | 103 +++++++++++++++---
> 2 files changed, 92 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 749c3a7e0b45..24e0067c2e7c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1445,10 +1445,12 @@ struct intel_digital_port {
> enum phy_fia tc_phy_fia;
> u8 tc_phy_fia_idx;
>
> - /* protects num_hdcp_streams reference count, port_data */
> + /* protects num_hdcp_streams reference count, port_data and port_auth */
> struct mutex hdcp_mutex;
> /* the number of pipes using HDCP signalling out of this port */
> unsigned int num_hdcp_streams;
> + /* port HDCP auth status */
> + bool port_auth;
> /* HDCP port data need to pass to security f/w */
> struct hdcp_port_data port_data;
since this is no more in hdcp related struct, it will be better to be named as
hdcp_auth_status and hdcp_port_data !?
-Ram
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index a5ec4f72f50f..1df6d4a23476 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -26,6 +26,64 @@
> #define KEY_LOAD_TRIES 5
> #define HDCP2_LC_RETRY_CNT 3
>
> +static int intel_conn_to_vcpi(struct intel_connector *connector)
> +{
> + /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
> + return connector->port ? connector->port->vcpi.vcpi : 0;
> +}
> +
> +static int
> +intel_hdcp_required_content_stream(struct intel_digital_port *dig_port)
> +{
> + struct drm_connector_list_iter conn_iter;
> + struct intel_digital_port *conn_dig_port;
> + struct intel_connector *connector;
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + struct hdcp_port_data *data = &dig_port->port_data;
> + bool enforce_type0 = false;
> + int k;
> +
> + if (dig_port->port_auth)
> + return 0;
> +
> + drm_connector_list_iter_begin(&i915->drm, &conn_iter);
> + for_each_intel_connector_iter(connector, &conn_iter) {
> + if (!intel_encoder_is_mst(intel_attached_encoder(connector)))
> + continue;
> +
> + conn_dig_port = intel_attached_dig_port(connector);
> + if (conn_dig_port != dig_port)
> + continue;
> +
> + if (connector->base.status == connector_status_disconnected)
> + continue;
> +
> + if (!enforce_type0 && !intel_hdcp2_capable(connector))
> + enforce_type0 = true;
> +
> + data->streams[data->k].stream_id = intel_conn_to_vcpi(connector);
> + data->k++;
> +
> + /* if there is only one active stream */
> + if (dig_port->dp.active_mst_links <= 1)
> + break;
> + }
> + drm_connector_list_iter_end(&conn_iter);
> +
> + if (drm_WARN_ON(&i915->drm, data->k > INTEL_NUM_PIPES(i915) || data->k == 0))
> + return -EINVAL;
> +
> + /*
> + * Apply common protection level across all streams in DP MST Topology.
> + * Use highest supported content type for all streams in DP MST Topology.
> + */
> + for (k = 0; k < data->k; k++)
> + data->streams[k].stream_type =
> + enforce_type0 ? DRM_MODE_HDCP_CONTENT_TYPE0 : DRM_MODE_HDCP_CONTENT_TYPE1;
> +
> + return 0;
> +}
> +
> static
> bool intel_hdcp_is_ksv_valid(u8 *ksv)
> {
> @@ -1474,13 +1532,14 @@ static
> int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
> {
> struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct intel_hdcp *hdcp = &connector->hdcp;
> union {
> struct hdcp2_rep_stream_manage stream_manage;
> struct hdcp2_rep_stream_ready stream_ready;
> } msgs;
> const struct intel_hdcp_shim *shim = hdcp->shim;
> - int ret;
> + int ret, streams_size_delta, i;
>
> if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX)
> return -ERANGE;
> @@ -1489,16 +1548,18 @@ int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
> msgs.stream_manage.msg_id = HDCP_2_2_REP_STREAM_MANAGE;
> drm_hdcp_cpu_to_be24(msgs.stream_manage.seq_num_m, hdcp->seq_num_m);
>
> - /* K no of streams is fixed as 1. Stored as big-endian. */
> - msgs.stream_manage.k = cpu_to_be16(1);
> + msgs.stream_manage.k = cpu_to_be16(data->k);
>
> - /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
> - msgs.stream_manage.streams[0].stream_id = 0;
> - msgs.stream_manage.streams[0].stream_type = hdcp->content_type;
> + for (i = 0; i < data->k; i++) {
> + msgs.stream_manage.streams[i].stream_id = data->streams[i].stream_id;
> + msgs.stream_manage.streams[i].stream_type = data->streams[i].stream_type;
> + }
>
> + streams_size_delta = (HDCP_2_2_MAX_CONTENT_STREAMS_CNT - data->k) *
> + sizeof(struct hdcp2_streamid_type);
> /* Send it to Repeater */
> ret = shim->write_2_2_msg(dig_port, &msgs.stream_manage,
> - sizeof(msgs.stream_manage));
> + sizeof(msgs.stream_manage) - streams_size_delta);
> if (ret < 0)
> goto out;
>
> @@ -1507,8 +1568,7 @@ int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
> if (ret < 0)
> goto out;
>
> - dig_port->port_data.seq_num_m = hdcp->seq_num_m;
> - dig_port->port_data.streams[0].stream_type = hdcp->content_type;
> + data->seq_num_m = hdcp->seq_num_m;
>
> ret = hdcp2_verify_mprime(connector, &msgs.stream_ready);
>
> @@ -1669,6 +1729,7 @@ static int hdcp2_enable_encryption(struct intel_connector *connector)
> port),
> LINK_ENCRYPTION_STATUS,
> HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
> + dig_port->port_auth = true;
>
> return ret;
> }
> @@ -1743,11 +1804,9 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
> {
> struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> - struct hdcp_port_data *data = &dig_port->port_data;
> - struct intel_hdcp *hdcp = &connector->hdcp;
> - int ret, i, tries = 3;
> + int ret = 0, i, tries = 3;
>
> - for (i = 0; i < tries; i++) {
> + for (i = 0; i < tries && !dig_port->port_auth; i++) {
> ret = hdcp2_authenticate_sink(connector);
> if (!ret) {
> ret = hdcp2_propagate_stream_management_info(connector);
> @@ -1757,7 +1816,7 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
> ret);
> break;
> }
> - data->streams[0].stream_type = hdcp->content_type;
> +
> ret = hdcp2_authenticate_port(connector);
> if (!ret)
> break;
> @@ -1792,7 +1851,9 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
>
> static int _intel_hdcp2_enable(struct intel_connector *connector)
> {
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct hdcp_port_data *data = &dig_port->port_data;
> struct intel_hdcp *hdcp = &connector->hdcp;
> int ret;
>
> @@ -1800,6 +1861,16 @@ static int _intel_hdcp2_enable(struct intel_connector *connector)
> connector->base.name, connector->base.base.id,
> hdcp->content_type);
>
> + /* Stream which requires encryption */
> + if (!intel_encoder_is_mst(intel_attached_encoder(connector))) {
> + data->k = 1;
> + data->streams[0].stream_type = hdcp->content_type;
> + } else {
> + ret = intel_hdcp_required_content_stream(dig_port);
> + if (ret)
> + return ret;
> + }
> +
> ret = hdcp2_authenticate_and_encrypt(connector);
> if (ret) {
> drm_dbg_kms(&i915->drm, "HDCP2 Type%d Enabling Failed. (%d)\n",
> @@ -1817,7 +1888,9 @@ static int _intel_hdcp2_enable(struct intel_connector *connector)
>
> static int _intel_hdcp2_disable(struct intel_connector *connector)
> {
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct hdcp_port_data *data = &dig_port->port_data;
> int ret;
>
> drm_dbg_kms(&i915->drm, "[%s:%d] HDCP2.2 is being Disabled\n",
> @@ -1829,6 +1902,8 @@ static int _intel_hdcp2_disable(struct intel_connector *connector)
> drm_dbg_kms(&i915->drm, "Port deauth failed.\n");
>
> connector->hdcp.hdcp2_encrypted = false;
> + dig_port->port_auth = false;
> + data->k = 0;
>
> return ret;
> }
> --
> 2.26.2
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [PATCH v4 12/16] drm/i915/hdcp: MST streams support in hdcp port_data
2020-11-05 16:34 ` [Intel-gfx] " Ramalingam C
@ 2020-11-06 6:35 ` Anshuman Gupta
-1 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-11-06 6:35 UTC (permalink / raw)
To: Ramalingam C
Cc: jani.nikula, intel-gfx, dri-devel, uma.shankar, seanpaul, juston.li
On 2020-11-05 at 22:04:15 +0530, Ramalingam C wrote:
> On 2020-10-27 at 22:12:04 +0530, Anshuman Gupta wrote:
> > Add support for multiple mst stream in hdcp port data
> > which will be used by RepeaterAuthStreamManage msg and
> > HDCP 2.2 security f/w for m' validation.
> >
> > v2:
> > Init the hdcp port data k for HDMI/DP SST strem.
> >
> > v3:
> > Cosmetic changes. [Uma]
> >
> > Cc: Ramalingam C <ramalingam.c@intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > ---
> > .../drm/i915/display/intel_display_types.h | 4 +-
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 103 +++++++++++++++---
> > 2 files changed, 92 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 749c3a7e0b45..24e0067c2e7c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1445,10 +1445,12 @@ struct intel_digital_port {
> > enum phy_fia tc_phy_fia;
> > u8 tc_phy_fia_idx;
> >
> > - /* protects num_hdcp_streams reference count, port_data */
> > + /* protects num_hdcp_streams reference count, port_data and port_auth */
> > struct mutex hdcp_mutex;
> > /* the number of pipes using HDCP signalling out of this port */
> > unsigned int num_hdcp_streams;
> > + /* port HDCP auth status */
> > + bool port_auth;
> > /* HDCP port data need to pass to security f/w */
> > struct hdcp_port_data port_data;
> since this is no more in hdcp related struct, it will be better to be named as
> hdcp_auth_status and hdcp_port_data !?
sure i will do this chnage.
Thanks,
Anshuman Gupta.
>
> -Ram
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index a5ec4f72f50f..1df6d4a23476 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -26,6 +26,64 @@
> > #define KEY_LOAD_TRIES 5
> > #define HDCP2_LC_RETRY_CNT 3
> >
> > +static int intel_conn_to_vcpi(struct intel_connector *connector)
> > +{
> > + /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
> > + return connector->port ? connector->port->vcpi.vcpi : 0;
> > +}
> > +
> > +static int
> > +intel_hdcp_required_content_stream(struct intel_digital_port *dig_port)
> > +{
> > + struct drm_connector_list_iter conn_iter;
> > + struct intel_digital_port *conn_dig_port;
> > + struct intel_connector *connector;
> > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > + struct hdcp_port_data *data = &dig_port->port_data;
> > + bool enforce_type0 = false;
> > + int k;
> > +
> > + if (dig_port->port_auth)
> > + return 0;
> > +
> > + drm_connector_list_iter_begin(&i915->drm, &conn_iter);
> > + for_each_intel_connector_iter(connector, &conn_iter) {
> > + if (!intel_encoder_is_mst(intel_attached_encoder(connector)))
> > + continue;
> > +
> > + conn_dig_port = intel_attached_dig_port(connector);
> > + if (conn_dig_port != dig_port)
> > + continue;
> > +
> > + if (connector->base.status == connector_status_disconnected)
> > + continue;
> > +
> > + if (!enforce_type0 && !intel_hdcp2_capable(connector))
> > + enforce_type0 = true;
> > +
> > + data->streams[data->k].stream_id = intel_conn_to_vcpi(connector);
> > + data->k++;
> > +
> > + /* if there is only one active stream */
> > + if (dig_port->dp.active_mst_links <= 1)
> > + break;
> > + }
> > + drm_connector_list_iter_end(&conn_iter);
> > +
> > + if (drm_WARN_ON(&i915->drm, data->k > INTEL_NUM_PIPES(i915) || data->k == 0))
> > + return -EINVAL;
> > +
> > + /*
> > + * Apply common protection level across all streams in DP MST Topology.
> > + * Use highest supported content type for all streams in DP MST Topology.
> > + */
> > + for (k = 0; k < data->k; k++)
> > + data->streams[k].stream_type =
> > + enforce_type0 ? DRM_MODE_HDCP_CONTENT_TYPE0 : DRM_MODE_HDCP_CONTENT_TYPE1;
> > +
> > + return 0;
> > +}
> > +
> > static
> > bool intel_hdcp_is_ksv_valid(u8 *ksv)
> > {
> > @@ -1474,13 +1532,14 @@ static
> > int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
> > {
> > struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> > + struct hdcp_port_data *data = &dig_port->port_data;
> > struct intel_hdcp *hdcp = &connector->hdcp;
> > union {
> > struct hdcp2_rep_stream_manage stream_manage;
> > struct hdcp2_rep_stream_ready stream_ready;
> > } msgs;
> > const struct intel_hdcp_shim *shim = hdcp->shim;
> > - int ret;
> > + int ret, streams_size_delta, i;
> >
> > if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX)
> > return -ERANGE;
> > @@ -1489,16 +1548,18 @@ int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
> > msgs.stream_manage.msg_id = HDCP_2_2_REP_STREAM_MANAGE;
> > drm_hdcp_cpu_to_be24(msgs.stream_manage.seq_num_m, hdcp->seq_num_m);
> >
> > - /* K no of streams is fixed as 1. Stored as big-endian. */
> > - msgs.stream_manage.k = cpu_to_be16(1);
> > + msgs.stream_manage.k = cpu_to_be16(data->k);
> >
> > - /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
> > - msgs.stream_manage.streams[0].stream_id = 0;
> > - msgs.stream_manage.streams[0].stream_type = hdcp->content_type;
> > + for (i = 0; i < data->k; i++) {
> > + msgs.stream_manage.streams[i].stream_id = data->streams[i].stream_id;
> > + msgs.stream_manage.streams[i].stream_type = data->streams[i].stream_type;
> > + }
> >
> > + streams_size_delta = (HDCP_2_2_MAX_CONTENT_STREAMS_CNT - data->k) *
> > + sizeof(struct hdcp2_streamid_type);
> > /* Send it to Repeater */
> > ret = shim->write_2_2_msg(dig_port, &msgs.stream_manage,
> > - sizeof(msgs.stream_manage));
> > + sizeof(msgs.stream_manage) - streams_size_delta);
> > if (ret < 0)
> > goto out;
> >
> > @@ -1507,8 +1568,7 @@ int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
> > if (ret < 0)
> > goto out;
> >
> > - dig_port->port_data.seq_num_m = hdcp->seq_num_m;
> > - dig_port->port_data.streams[0].stream_type = hdcp->content_type;
> > + data->seq_num_m = hdcp->seq_num_m;
> >
> > ret = hdcp2_verify_mprime(connector, &msgs.stream_ready);
> >
> > @@ -1669,6 +1729,7 @@ static int hdcp2_enable_encryption(struct intel_connector *connector)
> > port),
> > LINK_ENCRYPTION_STATUS,
> > HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
> > + dig_port->port_auth = true;
> >
> > return ret;
> > }
> > @@ -1743,11 +1804,9 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
> > {
> > struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> > struct drm_i915_private *i915 = to_i915(connector->base.dev);
> > - struct hdcp_port_data *data = &dig_port->port_data;
> > - struct intel_hdcp *hdcp = &connector->hdcp;
> > - int ret, i, tries = 3;
> > + int ret = 0, i, tries = 3;
> >
> > - for (i = 0; i < tries; i++) {
> > + for (i = 0; i < tries && !dig_port->port_auth; i++) {
> > ret = hdcp2_authenticate_sink(connector);
> > if (!ret) {
> > ret = hdcp2_propagate_stream_management_info(connector);
> > @@ -1757,7 +1816,7 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
> > ret);
> > break;
> > }
> > - data->streams[0].stream_type = hdcp->content_type;
> > +
> > ret = hdcp2_authenticate_port(connector);
> > if (!ret)
> > break;
> > @@ -1792,7 +1851,9 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
> >
> > static int _intel_hdcp2_enable(struct intel_connector *connector)
> > {
> > + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> > struct drm_i915_private *i915 = to_i915(connector->base.dev);
> > + struct hdcp_port_data *data = &dig_port->port_data;
> > struct intel_hdcp *hdcp = &connector->hdcp;
> > int ret;
> >
> > @@ -1800,6 +1861,16 @@ static int _intel_hdcp2_enable(struct intel_connector *connector)
> > connector->base.name, connector->base.base.id,
> > hdcp->content_type);
> >
> > + /* Stream which requires encryption */
> > + if (!intel_encoder_is_mst(intel_attached_encoder(connector))) {
> > + data->k = 1;
> > + data->streams[0].stream_type = hdcp->content_type;
> > + } else {
> > + ret = intel_hdcp_required_content_stream(dig_port);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > ret = hdcp2_authenticate_and_encrypt(connector);
> > if (ret) {
> > drm_dbg_kms(&i915->drm, "HDCP2 Type%d Enabling Failed. (%d)\n",
> > @@ -1817,7 +1888,9 @@ static int _intel_hdcp2_enable(struct intel_connector *connector)
> >
> > static int _intel_hdcp2_disable(struct intel_connector *connector)
> > {
> > + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> > struct drm_i915_private *i915 = to_i915(connector->base.dev);
> > + struct hdcp_port_data *data = &dig_port->port_data;
> > int ret;
> >
> > drm_dbg_kms(&i915->drm, "[%s:%d] HDCP2.2 is being Disabled\n",
> > @@ -1829,6 +1902,8 @@ static int _intel_hdcp2_disable(struct intel_connector *connector)
> > drm_dbg_kms(&i915->drm, "Port deauth failed.\n");
> >
> > connector->hdcp.hdcp2_encrypted = false;
> > + dig_port->port_auth = false;
> > + data->k = 0;
> >
> > return ret;
> > }
> > --
> > 2.26.2
> >
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 12/16] drm/i915/hdcp: MST streams support in hdcp port_data
@ 2020-11-06 6:35 ` Anshuman Gupta
0 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-11-06 6:35 UTC (permalink / raw)
To: Ramalingam C; +Cc: jani.nikula, intel-gfx, dri-devel, seanpaul
On 2020-11-05 at 22:04:15 +0530, Ramalingam C wrote:
> On 2020-10-27 at 22:12:04 +0530, Anshuman Gupta wrote:
> > Add support for multiple mst stream in hdcp port data
> > which will be used by RepeaterAuthStreamManage msg and
> > HDCP 2.2 security f/w for m' validation.
> >
> > v2:
> > Init the hdcp port data k for HDMI/DP SST strem.
> >
> > v3:
> > Cosmetic changes. [Uma]
> >
> > Cc: Ramalingam C <ramalingam.c@intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > ---
> > .../drm/i915/display/intel_display_types.h | 4 +-
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 103 +++++++++++++++---
> > 2 files changed, 92 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 749c3a7e0b45..24e0067c2e7c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1445,10 +1445,12 @@ struct intel_digital_port {
> > enum phy_fia tc_phy_fia;
> > u8 tc_phy_fia_idx;
> >
> > - /* protects num_hdcp_streams reference count, port_data */
> > + /* protects num_hdcp_streams reference count, port_data and port_auth */
> > struct mutex hdcp_mutex;
> > /* the number of pipes using HDCP signalling out of this port */
> > unsigned int num_hdcp_streams;
> > + /* port HDCP auth status */
> > + bool port_auth;
> > /* HDCP port data need to pass to security f/w */
> > struct hdcp_port_data port_data;
> since this is no more in hdcp related struct, it will be better to be named as
> hdcp_auth_status and hdcp_port_data !?
sure i will do this chnage.
Thanks,
Anshuman Gupta.
>
> -Ram
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index a5ec4f72f50f..1df6d4a23476 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -26,6 +26,64 @@
> > #define KEY_LOAD_TRIES 5
> > #define HDCP2_LC_RETRY_CNT 3
> >
> > +static int intel_conn_to_vcpi(struct intel_connector *connector)
> > +{
> > + /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
> > + return connector->port ? connector->port->vcpi.vcpi : 0;
> > +}
> > +
> > +static int
> > +intel_hdcp_required_content_stream(struct intel_digital_port *dig_port)
> > +{
> > + struct drm_connector_list_iter conn_iter;
> > + struct intel_digital_port *conn_dig_port;
> > + struct intel_connector *connector;
> > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > + struct hdcp_port_data *data = &dig_port->port_data;
> > + bool enforce_type0 = false;
> > + int k;
> > +
> > + if (dig_port->port_auth)
> > + return 0;
> > +
> > + drm_connector_list_iter_begin(&i915->drm, &conn_iter);
> > + for_each_intel_connector_iter(connector, &conn_iter) {
> > + if (!intel_encoder_is_mst(intel_attached_encoder(connector)))
> > + continue;
> > +
> > + conn_dig_port = intel_attached_dig_port(connector);
> > + if (conn_dig_port != dig_port)
> > + continue;
> > +
> > + if (connector->base.status == connector_status_disconnected)
> > + continue;
> > +
> > + if (!enforce_type0 && !intel_hdcp2_capable(connector))
> > + enforce_type0 = true;
> > +
> > + data->streams[data->k].stream_id = intel_conn_to_vcpi(connector);
> > + data->k++;
> > +
> > + /* if there is only one active stream */
> > + if (dig_port->dp.active_mst_links <= 1)
> > + break;
> > + }
> > + drm_connector_list_iter_end(&conn_iter);
> > +
> > + if (drm_WARN_ON(&i915->drm, data->k > INTEL_NUM_PIPES(i915) || data->k == 0))
> > + return -EINVAL;
> > +
> > + /*
> > + * Apply common protection level across all streams in DP MST Topology.
> > + * Use highest supported content type for all streams in DP MST Topology.
> > + */
> > + for (k = 0; k < data->k; k++)
> > + data->streams[k].stream_type =
> > + enforce_type0 ? DRM_MODE_HDCP_CONTENT_TYPE0 : DRM_MODE_HDCP_CONTENT_TYPE1;
> > +
> > + return 0;
> > +}
> > +
> > static
> > bool intel_hdcp_is_ksv_valid(u8 *ksv)
> > {
> > @@ -1474,13 +1532,14 @@ static
> > int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
> > {
> > struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> > + struct hdcp_port_data *data = &dig_port->port_data;
> > struct intel_hdcp *hdcp = &connector->hdcp;
> > union {
> > struct hdcp2_rep_stream_manage stream_manage;
> > struct hdcp2_rep_stream_ready stream_ready;
> > } msgs;
> > const struct intel_hdcp_shim *shim = hdcp->shim;
> > - int ret;
> > + int ret, streams_size_delta, i;
> >
> > if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX)
> > return -ERANGE;
> > @@ -1489,16 +1548,18 @@ int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
> > msgs.stream_manage.msg_id = HDCP_2_2_REP_STREAM_MANAGE;
> > drm_hdcp_cpu_to_be24(msgs.stream_manage.seq_num_m, hdcp->seq_num_m);
> >
> > - /* K no of streams is fixed as 1. Stored as big-endian. */
> > - msgs.stream_manage.k = cpu_to_be16(1);
> > + msgs.stream_manage.k = cpu_to_be16(data->k);
> >
> > - /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
> > - msgs.stream_manage.streams[0].stream_id = 0;
> > - msgs.stream_manage.streams[0].stream_type = hdcp->content_type;
> > + for (i = 0; i < data->k; i++) {
> > + msgs.stream_manage.streams[i].stream_id = data->streams[i].stream_id;
> > + msgs.stream_manage.streams[i].stream_type = data->streams[i].stream_type;
> > + }
> >
> > + streams_size_delta = (HDCP_2_2_MAX_CONTENT_STREAMS_CNT - data->k) *
> > + sizeof(struct hdcp2_streamid_type);
> > /* Send it to Repeater */
> > ret = shim->write_2_2_msg(dig_port, &msgs.stream_manage,
> > - sizeof(msgs.stream_manage));
> > + sizeof(msgs.stream_manage) - streams_size_delta);
> > if (ret < 0)
> > goto out;
> >
> > @@ -1507,8 +1568,7 @@ int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
> > if (ret < 0)
> > goto out;
> >
> > - dig_port->port_data.seq_num_m = hdcp->seq_num_m;
> > - dig_port->port_data.streams[0].stream_type = hdcp->content_type;
> > + data->seq_num_m = hdcp->seq_num_m;
> >
> > ret = hdcp2_verify_mprime(connector, &msgs.stream_ready);
> >
> > @@ -1669,6 +1729,7 @@ static int hdcp2_enable_encryption(struct intel_connector *connector)
> > port),
> > LINK_ENCRYPTION_STATUS,
> > HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
> > + dig_port->port_auth = true;
> >
> > return ret;
> > }
> > @@ -1743,11 +1804,9 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
> > {
> > struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> > struct drm_i915_private *i915 = to_i915(connector->base.dev);
> > - struct hdcp_port_data *data = &dig_port->port_data;
> > - struct intel_hdcp *hdcp = &connector->hdcp;
> > - int ret, i, tries = 3;
> > + int ret = 0, i, tries = 3;
> >
> > - for (i = 0; i < tries; i++) {
> > + for (i = 0; i < tries && !dig_port->port_auth; i++) {
> > ret = hdcp2_authenticate_sink(connector);
> > if (!ret) {
> > ret = hdcp2_propagate_stream_management_info(connector);
> > @@ -1757,7 +1816,7 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
> > ret);
> > break;
> > }
> > - data->streams[0].stream_type = hdcp->content_type;
> > +
> > ret = hdcp2_authenticate_port(connector);
> > if (!ret)
> > break;
> > @@ -1792,7 +1851,9 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
> >
> > static int _intel_hdcp2_enable(struct intel_connector *connector)
> > {
> > + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> > struct drm_i915_private *i915 = to_i915(connector->base.dev);
> > + struct hdcp_port_data *data = &dig_port->port_data;
> > struct intel_hdcp *hdcp = &connector->hdcp;
> > int ret;
> >
> > @@ -1800,6 +1861,16 @@ static int _intel_hdcp2_enable(struct intel_connector *connector)
> > connector->base.name, connector->base.base.id,
> > hdcp->content_type);
> >
> > + /* Stream which requires encryption */
> > + if (!intel_encoder_is_mst(intel_attached_encoder(connector))) {
> > + data->k = 1;
> > + data->streams[0].stream_type = hdcp->content_type;
> > + } else {
> > + ret = intel_hdcp_required_content_stream(dig_port);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > ret = hdcp2_authenticate_and_encrypt(connector);
> > if (ret) {
> > drm_dbg_kms(&i915->drm, "HDCP2 Type%d Enabling Failed. (%d)\n",
> > @@ -1817,7 +1888,9 @@ static int _intel_hdcp2_enable(struct intel_connector *connector)
> >
> > static int _intel_hdcp2_disable(struct intel_connector *connector)
> > {
> > + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> > struct drm_i915_private *i915 = to_i915(connector->base.dev);
> > + struct hdcp_port_data *data = &dig_port->port_data;
> > int ret;
> >
> > drm_dbg_kms(&i915->drm, "[%s:%d] HDCP2.2 is being Disabled\n",
> > @@ -1829,6 +1902,8 @@ static int _intel_hdcp2_disable(struct intel_connector *connector)
> > drm_dbg_kms(&i915->drm, "Port deauth failed.\n");
> >
> > connector->hdcp.hdcp2_encrypted = false;
> > + dig_port->port_auth = false;
> > + data->k = 0;
> >
> > return ret;
> > }
> > --
> > 2.26.2
> >
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [PATCH v4 12/16] drm/i915/hdcp: MST streams support in hdcp port_data
2020-11-06 6:35 ` [Intel-gfx] " Anshuman Gupta
@ 2020-11-06 11:28 ` Ramalingam C
-1 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-06 11:28 UTC (permalink / raw)
To: Anshuman Gupta
Cc: jani.nikula, intel-gfx, dri-devel, uma.shankar, seanpaul, juston.li
On 2020-11-06 at 12:05:14 +0530, Anshuman Gupta wrote:
> On 2020-11-05 at 22:04:15 +0530, Ramalingam C wrote:
> > On 2020-10-27 at 22:12:04 +0530, Anshuman Gupta wrote:
> > > Add support for multiple mst stream in hdcp port data
> > > which will be used by RepeaterAuthStreamManage msg and
> > > HDCP 2.2 security f/w for m' validation.
> > >
> > > v2:
> > > Init the hdcp port data k for HDMI/DP SST strem.
> > >
> > > v3:
> > > Cosmetic changes. [Uma]
> > >
> > > Cc: Ramalingam C <ramalingam.c@intel.com>
> > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > > ---
> > > .../drm/i915/display/intel_display_types.h | 4 +-
> > > drivers/gpu/drm/i915/display/intel_hdcp.c | 103 +++++++++++++++---
> > > 2 files changed, 92 insertions(+), 15 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 749c3a7e0b45..24e0067c2e7c 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -1445,10 +1445,12 @@ struct intel_digital_port {
> > > enum phy_fia tc_phy_fia;
> > > u8 tc_phy_fia_idx;
> > >
> > > - /* protects num_hdcp_streams reference count, port_data */
> > > + /* protects num_hdcp_streams reference count, port_data and port_auth */
> > > struct mutex hdcp_mutex;
> > > /* the number of pipes using HDCP signalling out of this port */
> > > unsigned int num_hdcp_streams;
> > > + /* port HDCP auth status */
> > > + bool port_auth;
> > > /* HDCP port data need to pass to security f/w */
> > > struct hdcp_port_data port_data;
> > since this is no more in hdcp related struct, it will be better to be named as
> > hdcp_auth_status and hdcp_port_data !?
> sure i will do this chnage.
> Thanks,
> Anshuman Gupta.
> >
> > -Ram
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > index a5ec4f72f50f..1df6d4a23476 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > @@ -26,6 +26,64 @@
> > > #define KEY_LOAD_TRIES 5
> > > #define HDCP2_LC_RETRY_CNT 3
> > >
> > > +static int intel_conn_to_vcpi(struct intel_connector *connector)
> > > +{
> > > + /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
> > > + return connector->port ? connector->port->vcpi.vcpi : 0;
> > > +}
> > > +
> > > +static int
> > > +intel_hdcp_required_content_stream(struct intel_digital_port *dig_port)
> > > +{
> > > + struct drm_connector_list_iter conn_iter;
> > > + struct intel_digital_port *conn_dig_port;
> > > + struct intel_connector *connector;
> > > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > > + struct hdcp_port_data *data = &dig_port->port_data;
> > > + bool enforce_type0 = false;
> > > + int k;
> > > +
> > > + if (dig_port->port_auth)
> > > + return 0;
> > > +
> > > + drm_connector_list_iter_begin(&i915->drm, &conn_iter);
> > > + for_each_intel_connector_iter(connector, &conn_iter) {
> > > + if (!intel_encoder_is_mst(intel_attached_encoder(connector)))
> > > + continue;
> > > +
> > > + conn_dig_port = intel_attached_dig_port(connector);
> > > + if (conn_dig_port != dig_port)
> > > + continue;
> > > +
> > > + if (connector->base.status == connector_status_disconnected)
> > > + continue;
> > > +
> > > + if (!enforce_type0 && !intel_hdcp2_capable(connector))
> > > + enforce_type0 = true;
> > > +
> > > + data->streams[data->k].stream_id = intel_conn_to_vcpi(connector);
> > > + data->k++;
> > > +
> > > + /* if there is only one active stream */
> > > + if (dig_port->dp.active_mst_links <= 1)
> > > + break;
> > > + }
> > > + drm_connector_list_iter_end(&conn_iter);
> > > +
> > > + if (drm_WARN_ON(&i915->drm, data->k > INTEL_NUM_PIPES(i915) || data->k == 0))
> > > + return -EINVAL;
> > > +
> > > + /*
> > > + * Apply common protection level across all streams in DP MST Topology.
> > > + * Use highest supported content type for all streams in DP MST Topology.
> > > + */
> > > + for (k = 0; k < data->k; k++)
> > > + data->streams[k].stream_type =
> > > + enforce_type0 ? DRM_MODE_HDCP_CONTENT_TYPE0 : DRM_MODE_HDCP_CONTENT_TYPE1;
> > > +
> > > + return 0;
> > > +}
This will force userspace to use most highest common possible HDCP type
on all streams. On MST if one sink is HDCP2.2 capable and where others
are not, this will prohibit the owner of the stream corresponding to the
HDCP2.2 capable sink from using the content type1, just bacuse other
sinks are not HDCP2.2 capable. ME FW should change its rules and allow
the different content type on different streams. And also dynamic update
of the stream type support will be ideal.
-Ram
> > > +
> > > static
> > > bool intel_hdcp_is_ksv_valid(u8 *ksv)
> > > {
> > > @@ -1474,13 +1532,14 @@ static
> > > int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
> > > {
> > > struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> > > + struct hdcp_port_data *data = &dig_port->port_data;
> > > struct intel_hdcp *hdcp = &connector->hdcp;
> > > union {
> > > struct hdcp2_rep_stream_manage stream_manage;
> > > struct hdcp2_rep_stream_ready stream_ready;
> > > } msgs;
> > > const struct intel_hdcp_shim *shim = hdcp->shim;
> > > - int ret;
> > > + int ret, streams_size_delta, i;
> > >
> > > if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX)
> > > return -ERANGE;
> > > @@ -1489,16 +1548,18 @@ int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
> > > msgs.stream_manage.msg_id = HDCP_2_2_REP_STREAM_MANAGE;
> > > drm_hdcp_cpu_to_be24(msgs.stream_manage.seq_num_m, hdcp->seq_num_m);
> > >
> > > - /* K no of streams is fixed as 1. Stored as big-endian. */
> > > - msgs.stream_manage.k = cpu_to_be16(1);
> > > + msgs.stream_manage.k = cpu_to_be16(data->k);
> > >
> > > - /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
> > > - msgs.stream_manage.streams[0].stream_id = 0;
> > > - msgs.stream_manage.streams[0].stream_type = hdcp->content_type;
> > > + for (i = 0; i < data->k; i++) {
> > > + msgs.stream_manage.streams[i].stream_id = data->streams[i].stream_id;
> > > + msgs.stream_manage.streams[i].stream_type = data->streams[i].stream_type;
> > > + }
> > >
> > > + streams_size_delta = (HDCP_2_2_MAX_CONTENT_STREAMS_CNT - data->k) *
> > > + sizeof(struct hdcp2_streamid_type);
> > > /* Send it to Repeater */
> > > ret = shim->write_2_2_msg(dig_port, &msgs.stream_manage,
> > > - sizeof(msgs.stream_manage));
> > > + sizeof(msgs.stream_manage) - streams_size_delta);
> > > if (ret < 0)
> > > goto out;
> > >
> > > @@ -1507,8 +1568,7 @@ int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
> > > if (ret < 0)
> > > goto out;
> > >
> > > - dig_port->port_data.seq_num_m = hdcp->seq_num_m;
> > > - dig_port->port_data.streams[0].stream_type = hdcp->content_type;
> > > + data->seq_num_m = hdcp->seq_num_m;
> > >
> > > ret = hdcp2_verify_mprime(connector, &msgs.stream_ready);
> > >
> > > @@ -1669,6 +1729,7 @@ static int hdcp2_enable_encryption(struct intel_connector *connector)
> > > port),
> > > LINK_ENCRYPTION_STATUS,
> > > HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
> > > + dig_port->port_auth = true;
> > >
> > > return ret;
> > > }
> > > @@ -1743,11 +1804,9 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
> > > {
> > > struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> > > struct drm_i915_private *i915 = to_i915(connector->base.dev);
> > > - struct hdcp_port_data *data = &dig_port->port_data;
> > > - struct intel_hdcp *hdcp = &connector->hdcp;
> > > - int ret, i, tries = 3;
> > > + int ret = 0, i, tries = 3;
> > >
> > > - for (i = 0; i < tries; i++) {
> > > + for (i = 0; i < tries && !dig_port->port_auth; i++) {
> > > ret = hdcp2_authenticate_sink(connector);
> > > if (!ret) {
> > > ret = hdcp2_propagate_stream_management_info(connector);
> > > @@ -1757,7 +1816,7 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
> > > ret);
> > > break;
> > > }
> > > - data->streams[0].stream_type = hdcp->content_type;
> > > +
> > > ret = hdcp2_authenticate_port(connector);
> > > if (!ret)
> > > break;
> > > @@ -1792,7 +1851,9 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
> > >
> > > static int _intel_hdcp2_enable(struct intel_connector *connector)
> > > {
> > > + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> > > struct drm_i915_private *i915 = to_i915(connector->base.dev);
> > > + struct hdcp_port_data *data = &dig_port->port_data;
> > > struct intel_hdcp *hdcp = &connector->hdcp;
> > > int ret;
> > >
> > > @@ -1800,6 +1861,16 @@ static int _intel_hdcp2_enable(struct intel_connector *connector)
> > > connector->base.name, connector->base.base.id,
> > > hdcp->content_type);
> > >
> > > + /* Stream which requires encryption */
> > > + if (!intel_encoder_is_mst(intel_attached_encoder(connector))) {
> > > + data->k = 1;
> > > + data->streams[0].stream_type = hdcp->content_type;
> > > + } else {
> > > + ret = intel_hdcp_required_content_stream(dig_port);
> > > + if (ret)
> > > + return ret;
> > > + }
> > > +
> > > ret = hdcp2_authenticate_and_encrypt(connector);
> > > if (ret) {
> > > drm_dbg_kms(&i915->drm, "HDCP2 Type%d Enabling Failed. (%d)\n",
> > > @@ -1817,7 +1888,9 @@ static int _intel_hdcp2_enable(struct intel_connector *connector)
> > >
> > > static int _intel_hdcp2_disable(struct intel_connector *connector)
> > > {
> > > + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> > > struct drm_i915_private *i915 = to_i915(connector->base.dev);
> > > + struct hdcp_port_data *data = &dig_port->port_data;
> > > int ret;
> > >
> > > drm_dbg_kms(&i915->drm, "[%s:%d] HDCP2.2 is being Disabled\n",
> > > @@ -1829,6 +1902,8 @@ static int _intel_hdcp2_disable(struct intel_connector *connector)
> > > drm_dbg_kms(&i915->drm, "Port deauth failed.\n");
> > >
> > > connector->hdcp.hdcp2_encrypted = false;
> > > + dig_port->port_auth = false;
> > > + data->k = 0;
> > >
> > > return ret;
> > > }
> > > --
> > > 2.26.2
> > >
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 12/16] drm/i915/hdcp: MST streams support in hdcp port_data
@ 2020-11-06 11:28 ` Ramalingam C
0 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-06 11:28 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: jani.nikula, intel-gfx, dri-devel, seanpaul
On 2020-11-06 at 12:05:14 +0530, Anshuman Gupta wrote:
> On 2020-11-05 at 22:04:15 +0530, Ramalingam C wrote:
> > On 2020-10-27 at 22:12:04 +0530, Anshuman Gupta wrote:
> > > Add support for multiple mst stream in hdcp port data
> > > which will be used by RepeaterAuthStreamManage msg and
> > > HDCP 2.2 security f/w for m' validation.
> > >
> > > v2:
> > > Init the hdcp port data k for HDMI/DP SST strem.
> > >
> > > v3:
> > > Cosmetic changes. [Uma]
> > >
> > > Cc: Ramalingam C <ramalingam.c@intel.com>
> > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > > ---
> > > .../drm/i915/display/intel_display_types.h | 4 +-
> > > drivers/gpu/drm/i915/display/intel_hdcp.c | 103 +++++++++++++++---
> > > 2 files changed, 92 insertions(+), 15 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 749c3a7e0b45..24e0067c2e7c 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -1445,10 +1445,12 @@ struct intel_digital_port {
> > > enum phy_fia tc_phy_fia;
> > > u8 tc_phy_fia_idx;
> > >
> > > - /* protects num_hdcp_streams reference count, port_data */
> > > + /* protects num_hdcp_streams reference count, port_data and port_auth */
> > > struct mutex hdcp_mutex;
> > > /* the number of pipes using HDCP signalling out of this port */
> > > unsigned int num_hdcp_streams;
> > > + /* port HDCP auth status */
> > > + bool port_auth;
> > > /* HDCP port data need to pass to security f/w */
> > > struct hdcp_port_data port_data;
> > since this is no more in hdcp related struct, it will be better to be named as
> > hdcp_auth_status and hdcp_port_data !?
> sure i will do this chnage.
> Thanks,
> Anshuman Gupta.
> >
> > -Ram
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > index a5ec4f72f50f..1df6d4a23476 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > @@ -26,6 +26,64 @@
> > > #define KEY_LOAD_TRIES 5
> > > #define HDCP2_LC_RETRY_CNT 3
> > >
> > > +static int intel_conn_to_vcpi(struct intel_connector *connector)
> > > +{
> > > + /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
> > > + return connector->port ? connector->port->vcpi.vcpi : 0;
> > > +}
> > > +
> > > +static int
> > > +intel_hdcp_required_content_stream(struct intel_digital_port *dig_port)
> > > +{
> > > + struct drm_connector_list_iter conn_iter;
> > > + struct intel_digital_port *conn_dig_port;
> > > + struct intel_connector *connector;
> > > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > > + struct hdcp_port_data *data = &dig_port->port_data;
> > > + bool enforce_type0 = false;
> > > + int k;
> > > +
> > > + if (dig_port->port_auth)
> > > + return 0;
> > > +
> > > + drm_connector_list_iter_begin(&i915->drm, &conn_iter);
> > > + for_each_intel_connector_iter(connector, &conn_iter) {
> > > + if (!intel_encoder_is_mst(intel_attached_encoder(connector)))
> > > + continue;
> > > +
> > > + conn_dig_port = intel_attached_dig_port(connector);
> > > + if (conn_dig_port != dig_port)
> > > + continue;
> > > +
> > > + if (connector->base.status == connector_status_disconnected)
> > > + continue;
> > > +
> > > + if (!enforce_type0 && !intel_hdcp2_capable(connector))
> > > + enforce_type0 = true;
> > > +
> > > + data->streams[data->k].stream_id = intel_conn_to_vcpi(connector);
> > > + data->k++;
> > > +
> > > + /* if there is only one active stream */
> > > + if (dig_port->dp.active_mst_links <= 1)
> > > + break;
> > > + }
> > > + drm_connector_list_iter_end(&conn_iter);
> > > +
> > > + if (drm_WARN_ON(&i915->drm, data->k > INTEL_NUM_PIPES(i915) || data->k == 0))
> > > + return -EINVAL;
> > > +
> > > + /*
> > > + * Apply common protection level across all streams in DP MST Topology.
> > > + * Use highest supported content type for all streams in DP MST Topology.
> > > + */
> > > + for (k = 0; k < data->k; k++)
> > > + data->streams[k].stream_type =
> > > + enforce_type0 ? DRM_MODE_HDCP_CONTENT_TYPE0 : DRM_MODE_HDCP_CONTENT_TYPE1;
> > > +
> > > + return 0;
> > > +}
This will force userspace to use most highest common possible HDCP type
on all streams. On MST if one sink is HDCP2.2 capable and where others
are not, this will prohibit the owner of the stream corresponding to the
HDCP2.2 capable sink from using the content type1, just bacuse other
sinks are not HDCP2.2 capable. ME FW should change its rules and allow
the different content type on different streams. And also dynamic update
of the stream type support will be ideal.
-Ram
> > > +
> > > static
> > > bool intel_hdcp_is_ksv_valid(u8 *ksv)
> > > {
> > > @@ -1474,13 +1532,14 @@ static
> > > int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
> > > {
> > > struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> > > + struct hdcp_port_data *data = &dig_port->port_data;
> > > struct intel_hdcp *hdcp = &connector->hdcp;
> > > union {
> > > struct hdcp2_rep_stream_manage stream_manage;
> > > struct hdcp2_rep_stream_ready stream_ready;
> > > } msgs;
> > > const struct intel_hdcp_shim *shim = hdcp->shim;
> > > - int ret;
> > > + int ret, streams_size_delta, i;
> > >
> > > if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX)
> > > return -ERANGE;
> > > @@ -1489,16 +1548,18 @@ int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
> > > msgs.stream_manage.msg_id = HDCP_2_2_REP_STREAM_MANAGE;
> > > drm_hdcp_cpu_to_be24(msgs.stream_manage.seq_num_m, hdcp->seq_num_m);
> > >
> > > - /* K no of streams is fixed as 1. Stored as big-endian. */
> > > - msgs.stream_manage.k = cpu_to_be16(1);
> > > + msgs.stream_manage.k = cpu_to_be16(data->k);
> > >
> > > - /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
> > > - msgs.stream_manage.streams[0].stream_id = 0;
> > > - msgs.stream_manage.streams[0].stream_type = hdcp->content_type;
> > > + for (i = 0; i < data->k; i++) {
> > > + msgs.stream_manage.streams[i].stream_id = data->streams[i].stream_id;
> > > + msgs.stream_manage.streams[i].stream_type = data->streams[i].stream_type;
> > > + }
> > >
> > > + streams_size_delta = (HDCP_2_2_MAX_CONTENT_STREAMS_CNT - data->k) *
> > > + sizeof(struct hdcp2_streamid_type);
> > > /* Send it to Repeater */
> > > ret = shim->write_2_2_msg(dig_port, &msgs.stream_manage,
> > > - sizeof(msgs.stream_manage));
> > > + sizeof(msgs.stream_manage) - streams_size_delta);
> > > if (ret < 0)
> > > goto out;
> > >
> > > @@ -1507,8 +1568,7 @@ int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
> > > if (ret < 0)
> > > goto out;
> > >
> > > - dig_port->port_data.seq_num_m = hdcp->seq_num_m;
> > > - dig_port->port_data.streams[0].stream_type = hdcp->content_type;
> > > + data->seq_num_m = hdcp->seq_num_m;
> > >
> > > ret = hdcp2_verify_mprime(connector, &msgs.stream_ready);
> > >
> > > @@ -1669,6 +1729,7 @@ static int hdcp2_enable_encryption(struct intel_connector *connector)
> > > port),
> > > LINK_ENCRYPTION_STATUS,
> > > HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
> > > + dig_port->port_auth = true;
> > >
> > > return ret;
> > > }
> > > @@ -1743,11 +1804,9 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
> > > {
> > > struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> > > struct drm_i915_private *i915 = to_i915(connector->base.dev);
> > > - struct hdcp_port_data *data = &dig_port->port_data;
> > > - struct intel_hdcp *hdcp = &connector->hdcp;
> > > - int ret, i, tries = 3;
> > > + int ret = 0, i, tries = 3;
> > >
> > > - for (i = 0; i < tries; i++) {
> > > + for (i = 0; i < tries && !dig_port->port_auth; i++) {
> > > ret = hdcp2_authenticate_sink(connector);
> > > if (!ret) {
> > > ret = hdcp2_propagate_stream_management_info(connector);
> > > @@ -1757,7 +1816,7 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
> > > ret);
> > > break;
> > > }
> > > - data->streams[0].stream_type = hdcp->content_type;
> > > +
> > > ret = hdcp2_authenticate_port(connector);
> > > if (!ret)
> > > break;
> > > @@ -1792,7 +1851,9 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
> > >
> > > static int _intel_hdcp2_enable(struct intel_connector *connector)
> > > {
> > > + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> > > struct drm_i915_private *i915 = to_i915(connector->base.dev);
> > > + struct hdcp_port_data *data = &dig_port->port_data;
> > > struct intel_hdcp *hdcp = &connector->hdcp;
> > > int ret;
> > >
> > > @@ -1800,6 +1861,16 @@ static int _intel_hdcp2_enable(struct intel_connector *connector)
> > > connector->base.name, connector->base.base.id,
> > > hdcp->content_type);
> > >
> > > + /* Stream which requires encryption */
> > > + if (!intel_encoder_is_mst(intel_attached_encoder(connector))) {
> > > + data->k = 1;
> > > + data->streams[0].stream_type = hdcp->content_type;
> > > + } else {
> > > + ret = intel_hdcp_required_content_stream(dig_port);
> > > + if (ret)
> > > + return ret;
> > > + }
> > > +
> > > ret = hdcp2_authenticate_and_encrypt(connector);
> > > if (ret) {
> > > drm_dbg_kms(&i915->drm, "HDCP2 Type%d Enabling Failed. (%d)\n",
> > > @@ -1817,7 +1888,9 @@ static int _intel_hdcp2_enable(struct intel_connector *connector)
> > >
> > > static int _intel_hdcp2_disable(struct intel_connector *connector)
> > > {
> > > + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> > > struct drm_i915_private *i915 = to_i915(connector->base.dev);
> > > + struct hdcp_port_data *data = &dig_port->port_data;
> > > int ret;
> > >
> > > drm_dbg_kms(&i915->drm, "[%s:%d] HDCP2.2 is being Disabled\n",
> > > @@ -1829,6 +1902,8 @@ static int _intel_hdcp2_disable(struct intel_connector *connector)
> > > drm_dbg_kms(&i915->drm, "Port deauth failed.\n");
> > >
> > > connector->hdcp.hdcp2_encrypted = false;
> > > + dig_port->port_auth = false;
> > > + data->k = 0;
> > >
> > > return ret;
> > > }
> > > --
> > > 2.26.2
> > >
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread
* [PATCH v4 13/16] drm/i915/hdcp: Pass connector to check_2_2_link
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
@ 2020-10-27 16:42 ` Anshuman Gupta
-1 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:42 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: jani.nikula, uma.shankar, seanpaul, Anshuman Gupta, juston.li
This requires for HDCP 2.2 MST check link.
Cc: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_types.h | 3 ++-
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 3 ++-
drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++-
4 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 24e0067c2e7c..dfb5be64e03a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -375,7 +375,8 @@ struct intel_hdcp_shim {
bool is_repeater, u8 type);
/* HDCP2.2 Link Integrity Check */
- int (*check_2_2_link)(struct intel_digital_port *dig_port);
+ int (*check_2_2_link)(struct intel_digital_port *dig_port,
+ struct intel_connector *connector);
};
struct intel_hdcp {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 591b68e5de48..4be61e7fde4e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -585,7 +585,8 @@ int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *dig_port,
}
static
-int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port)
+int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
{
u8 rx_status;
int ret;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 1df6d4a23476..87f7aaf3a319 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1940,7 +1940,7 @@ static int intel_hdcp2_check_link(struct intel_connector *connector)
goto out;
}
- ret = hdcp->shim->check_2_2_link(dig_port);
+ ret = hdcp->shim->check_2_2_link(dig_port, connector);
if (ret == HDCP_LINK_PROTECTED) {
if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
intel_hdcp_update_value(connector,
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 0788de04711b..bd0d91101464 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1734,7 +1734,8 @@ int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port,
}
static
-int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port)
+int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
{
u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
int ret;
--
2.26.2
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^ permalink raw reply related [flat|nested] 111+ messages in thread* [Intel-gfx] [PATCH v4 13/16] drm/i915/hdcp: Pass connector to check_2_2_link
@ 2020-10-27 16:42 ` Anshuman Gupta
0 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:42 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula, seanpaul
This requires for HDCP 2.2 MST check link.
Cc: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_types.h | 3 ++-
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 3 ++-
drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++-
4 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 24e0067c2e7c..dfb5be64e03a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -375,7 +375,8 @@ struct intel_hdcp_shim {
bool is_repeater, u8 type);
/* HDCP2.2 Link Integrity Check */
- int (*check_2_2_link)(struct intel_digital_port *dig_port);
+ int (*check_2_2_link)(struct intel_digital_port *dig_port,
+ struct intel_connector *connector);
};
struct intel_hdcp {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 591b68e5de48..4be61e7fde4e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -585,7 +585,8 @@ int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *dig_port,
}
static
-int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port)
+int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
{
u8 rx_status;
int ret;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 1df6d4a23476..87f7aaf3a319 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1940,7 +1940,7 @@ static int intel_hdcp2_check_link(struct intel_connector *connector)
goto out;
}
- ret = hdcp->shim->check_2_2_link(dig_port);
+ ret = hdcp->shim->check_2_2_link(dig_port, connector);
if (ret == HDCP_LINK_PROTECTED) {
if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
intel_hdcp_update_value(connector,
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 0788de04711b..bd0d91101464 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1734,7 +1734,8 @@ int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port,
}
static
-int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port)
+int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
{
u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
int ret;
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 111+ messages in thread* Re: [PATCH v4 13/16] drm/i915/hdcp: Pass connector to check_2_2_link
2020-10-27 16:42 ` [Intel-gfx] " Anshuman Gupta
@ 2020-11-05 16:45 ` Ramalingam C
-1 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-05 16:45 UTC (permalink / raw)
To: Anshuman Gupta
Cc: jani.nikula, intel-gfx, dri-devel, uma.shankar, seanpaul, juston.li
On 2020-10-27 at 22:12:05 +0530, Anshuman Gupta wrote:
> This requires for HDCP 2.2 MST check link.
>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_types.h | 3 ++-
> drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 3 ++-
> drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
> drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++-
> 4 files changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 24e0067c2e7c..dfb5be64e03a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -375,7 +375,8 @@ struct intel_hdcp_shim {
> bool is_repeater, u8 type);
>
> /* HDCP2.2 Link Integrity Check */
> - int (*check_2_2_link)(struct intel_digital_port *dig_port);
> + int (*check_2_2_link)(struct intel_digital_port *dig_port,
> + struct intel_connector *connector);
do we need both of them?
-Ram.
> };
>
> struct intel_hdcp {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> index 591b68e5de48..4be61e7fde4e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> @@ -585,7 +585,8 @@ int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *dig_port,
> }
>
> static
> -int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port)
> +int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port,
> + struct intel_connector *connector)
> {
> u8 rx_status;
> int ret;
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 1df6d4a23476..87f7aaf3a319 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -1940,7 +1940,7 @@ static int intel_hdcp2_check_link(struct intel_connector *connector)
> goto out;
> }
>
> - ret = hdcp->shim->check_2_2_link(dig_port);
> + ret = hdcp->shim->check_2_2_link(dig_port, connector);
> if (ret == HDCP_LINK_PROTECTED) {
> if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
> intel_hdcp_update_value(connector,
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 0788de04711b..bd0d91101464 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -1734,7 +1734,8 @@ int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port,
> }
>
> static
> -int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port)
> +int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
> + struct intel_connector *connector)
> {
> u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
> int ret;
> --
> 2.26.2
>
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^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 13/16] drm/i915/hdcp: Pass connector to check_2_2_link
@ 2020-11-05 16:45 ` Ramalingam C
0 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-05 16:45 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: jani.nikula, intel-gfx, dri-devel, seanpaul
On 2020-10-27 at 22:12:05 +0530, Anshuman Gupta wrote:
> This requires for HDCP 2.2 MST check link.
>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_types.h | 3 ++-
> drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 3 ++-
> drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
> drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++-
> 4 files changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 24e0067c2e7c..dfb5be64e03a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -375,7 +375,8 @@ struct intel_hdcp_shim {
> bool is_repeater, u8 type);
>
> /* HDCP2.2 Link Integrity Check */
> - int (*check_2_2_link)(struct intel_digital_port *dig_port);
> + int (*check_2_2_link)(struct intel_digital_port *dig_port,
> + struct intel_connector *connector);
do we need both of them?
-Ram.
> };
>
> struct intel_hdcp {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> index 591b68e5de48..4be61e7fde4e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> @@ -585,7 +585,8 @@ int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *dig_port,
> }
>
> static
> -int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port)
> +int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port,
> + struct intel_connector *connector)
> {
> u8 rx_status;
> int ret;
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 1df6d4a23476..87f7aaf3a319 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -1940,7 +1940,7 @@ static int intel_hdcp2_check_link(struct intel_connector *connector)
> goto out;
> }
>
> - ret = hdcp->shim->check_2_2_link(dig_port);
> + ret = hdcp->shim->check_2_2_link(dig_port, connector);
> if (ret == HDCP_LINK_PROTECTED) {
> if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
> intel_hdcp_update_value(connector,
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 0788de04711b..bd0d91101464 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -1734,7 +1734,8 @@ int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port,
> }
>
> static
> -int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port)
> +int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
> + struct intel_connector *connector)
> {
> u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
> int ret;
> --
> 2.26.2
>
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^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [PATCH v4 13/16] drm/i915/hdcp: Pass connector to check_2_2_link
2020-11-05 16:45 ` [Intel-gfx] " Ramalingam C
@ 2020-11-06 5:08 ` Anshuman Gupta
-1 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-11-06 5:08 UTC (permalink / raw)
To: Ramalingam C
Cc: jani.nikula, intel-gfx, dri-devel, uma.shankar, seanpaul, juston.li
On 2020-11-05 at 22:15:37 +0530, Ramalingam C wrote:
> On 2020-10-27 at 22:12:05 +0530, Anshuman Gupta wrote:
> > This requires for HDCP 2.2 MST check link.
> >
> > Cc: Ramalingam C <ramalingam.c@intel.com>
> > Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display_types.h | 3 ++-
> > drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 3 ++-
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++-
> > 4 files changed, 7 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 24e0067c2e7c..dfb5be64e03a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -375,7 +375,8 @@ struct intel_hdcp_shim {
> > bool is_repeater, u8 type);
> >
> > /* HDCP2.2 Link Integrity Check */
> > - int (*check_2_2_link)(struct intel_digital_port *dig_port);
> > + int (*check_2_2_link)(struct intel_digital_port *dig_port,
> > + struct intel_connector *connector);
> do we need both of them?
I have followed the HDCP 1.4 check_link signature.
https://patchwork.freedesktop.org/patch/386157/?series=78749&rev=3
We need connector for QSES check, we can't retrieve DP MST connector from
dig_port.
Thanks,
Anshuman
>
> -Ram.
> > };
> >
> > struct intel_hdcp {
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > index 591b68e5de48..4be61e7fde4e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > @@ -585,7 +585,8 @@ int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *dig_port,
> > }
> >
> > static
> > -int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port)
> > +int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port,
> > + struct intel_connector *connector)
> > {
> > u8 rx_status;
> > int ret;
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index 1df6d4a23476..87f7aaf3a319 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -1940,7 +1940,7 @@ static int intel_hdcp2_check_link(struct intel_connector *connector)
> > goto out;
> > }
> >
> > - ret = hdcp->shim->check_2_2_link(dig_port);
> > + ret = hdcp->shim->check_2_2_link(dig_port, connector);
> > if (ret == HDCP_LINK_PROTECTED) {
> > if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
> > intel_hdcp_update_value(connector,
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > index 0788de04711b..bd0d91101464 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > @@ -1734,7 +1734,8 @@ int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port,
> > }
> >
> > static
> > -int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port)
> > +int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
> > + struct intel_connector *connector)
> > {
> > u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
> > int ret;
> > --
> > 2.26.2
> >
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^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 13/16] drm/i915/hdcp: Pass connector to check_2_2_link
@ 2020-11-06 5:08 ` Anshuman Gupta
0 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-11-06 5:08 UTC (permalink / raw)
To: Ramalingam C; +Cc: jani.nikula, intel-gfx, dri-devel, seanpaul
On 2020-11-05 at 22:15:37 +0530, Ramalingam C wrote:
> On 2020-10-27 at 22:12:05 +0530, Anshuman Gupta wrote:
> > This requires for HDCP 2.2 MST check link.
> >
> > Cc: Ramalingam C <ramalingam.c@intel.com>
> > Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display_types.h | 3 ++-
> > drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 3 ++-
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++-
> > 4 files changed, 7 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 24e0067c2e7c..dfb5be64e03a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -375,7 +375,8 @@ struct intel_hdcp_shim {
> > bool is_repeater, u8 type);
> >
> > /* HDCP2.2 Link Integrity Check */
> > - int (*check_2_2_link)(struct intel_digital_port *dig_port);
> > + int (*check_2_2_link)(struct intel_digital_port *dig_port,
> > + struct intel_connector *connector);
> do we need both of them?
I have followed the HDCP 1.4 check_link signature.
https://patchwork.freedesktop.org/patch/386157/?series=78749&rev=3
We need connector for QSES check, we can't retrieve DP MST connector from
dig_port.
Thanks,
Anshuman
>
> -Ram.
> > };
> >
> > struct intel_hdcp {
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > index 591b68e5de48..4be61e7fde4e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > @@ -585,7 +585,8 @@ int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *dig_port,
> > }
> >
> > static
> > -int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port)
> > +int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port,
> > + struct intel_connector *connector)
> > {
> > u8 rx_status;
> > int ret;
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index 1df6d4a23476..87f7aaf3a319 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -1940,7 +1940,7 @@ static int intel_hdcp2_check_link(struct intel_connector *connector)
> > goto out;
> > }
> >
> > - ret = hdcp->shim->check_2_2_link(dig_port);
> > + ret = hdcp->shim->check_2_2_link(dig_port, connector);
> > if (ret == HDCP_LINK_PROTECTED) {
> > if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
> > intel_hdcp_update_value(connector,
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > index 0788de04711b..bd0d91101464 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > @@ -1734,7 +1734,8 @@ int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port,
> > }
> >
> > static
> > -int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port)
> > +int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
> > + struct intel_connector *connector)
> > {
> > u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
> > int ret;
> > --
> > 2.26.2
> >
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread
* [PATCH v4 14/16] drm/i915/hdcp: Add HDCP 2.2 stream register
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
@ 2020-10-27 16:42 ` Anshuman Gupta
-1 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:42 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: jani.nikula, uma.shankar, seanpaul, Anshuman Gupta, juston.li
Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS
and HDCP2_AUTH_STREAM register in i915_reg header.
Cc: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 77461cde6549..c9678c77883d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9894,6 +9894,7 @@ enum skl_power_gate {
_PORTD_HDCP2_BASE, \
_PORTE_HDCP2_BASE, \
_PORTF_HDCP2_BASE) + (x))
+
#define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98)
#define _TRANSA_HDCP2_AUTH 0x66498
#define _TRANSB_HDCP2_AUTH 0x66598
@@ -9933,6 +9934,35 @@ enum skl_power_gate {
TRANS_HDCP2_STATUS(trans) : \
PORT_HDCP2_STATUS(port))
+#define PORT_HDCP2_STREAM_STATUS(port) _PORT_HDCP2_BASE(port, 0xC0)
+#define _TRANSA_HDCP2_STREAM_STATUS 0x664C0
+#define _TRANSB_HDCP2_STREAM_STATUS 0x665C0
+#define TRANS_HDCP2_STREAM_STATUS(trans) _MMIO_TRANS(trans, \
+ _TRANSA_HDCP2_STREAM_STATUS, \
+ _TRANSB_HDCP2_STREAM_STATUS)
+#define STREAM_ENCRYPTION_STATUS BIT(31)
+#define STREAM_TYPE_STATUS BIT(30)
+#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+ TRANS_HDCP2_STREAM_STATUS(trans) : \
+ PORT_HDCP2_STREAM_STATUS(port))
+
+#define _PORTA_HDCP2_AUTH_STREAM 0x66F00
+#define _PORTB_HDCP2_AUTH_STREAM 0x66F04
+#define PORT_HDCP2_AUTH_STREAM(port) _MMIO_PORT(port, \
+ _PORTA_HDCP2_AUTH_STREAM, \
+ _PORTB_HDCP2_AUTH_STREAM)
+#define _TRANSA_HDCP2_AUTH_STREAM 0x66F00
+#define _TRANSB_HDCP2_AUTH_STREAM 0x66F04
+#define TRANS_HDCP2_AUTH_STREAM(trans) _MMIO_TRANS(trans, \
+ _TRANSA_HDCP2_AUTH_STREAM, \
+ _TRANSB_HDCP2_AUTH_STREAM)
+#define AUTH_STREAM_TYPE BIT(31)
+#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+ TRANS_HDCP2_AUTH_STREAM(trans) : \
+ PORT_HDCP2_AUTH_STREAM(port))
+
/* Per-pipe DDI Function Control */
#define _TRANS_DDI_FUNC_CTL_A 0x60400
#define _TRANS_DDI_FUNC_CTL_B 0x61400
--
2.26.2
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^ permalink raw reply related [flat|nested] 111+ messages in thread* [Intel-gfx] [PATCH v4 14/16] drm/i915/hdcp: Add HDCP 2.2 stream register
@ 2020-10-27 16:42 ` Anshuman Gupta
0 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:42 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula, seanpaul
Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS
and HDCP2_AUTH_STREAM register in i915_reg header.
Cc: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 77461cde6549..c9678c77883d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9894,6 +9894,7 @@ enum skl_power_gate {
_PORTD_HDCP2_BASE, \
_PORTE_HDCP2_BASE, \
_PORTF_HDCP2_BASE) + (x))
+
#define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98)
#define _TRANSA_HDCP2_AUTH 0x66498
#define _TRANSB_HDCP2_AUTH 0x66598
@@ -9933,6 +9934,35 @@ enum skl_power_gate {
TRANS_HDCP2_STATUS(trans) : \
PORT_HDCP2_STATUS(port))
+#define PORT_HDCP2_STREAM_STATUS(port) _PORT_HDCP2_BASE(port, 0xC0)
+#define _TRANSA_HDCP2_STREAM_STATUS 0x664C0
+#define _TRANSB_HDCP2_STREAM_STATUS 0x665C0
+#define TRANS_HDCP2_STREAM_STATUS(trans) _MMIO_TRANS(trans, \
+ _TRANSA_HDCP2_STREAM_STATUS, \
+ _TRANSB_HDCP2_STREAM_STATUS)
+#define STREAM_ENCRYPTION_STATUS BIT(31)
+#define STREAM_TYPE_STATUS BIT(30)
+#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+ TRANS_HDCP2_STREAM_STATUS(trans) : \
+ PORT_HDCP2_STREAM_STATUS(port))
+
+#define _PORTA_HDCP2_AUTH_STREAM 0x66F00
+#define _PORTB_HDCP2_AUTH_STREAM 0x66F04
+#define PORT_HDCP2_AUTH_STREAM(port) _MMIO_PORT(port, \
+ _PORTA_HDCP2_AUTH_STREAM, \
+ _PORTB_HDCP2_AUTH_STREAM)
+#define _TRANSA_HDCP2_AUTH_STREAM 0x66F00
+#define _TRANSB_HDCP2_AUTH_STREAM 0x66F04
+#define TRANS_HDCP2_AUTH_STREAM(trans) _MMIO_TRANS(trans, \
+ _TRANSA_HDCP2_AUTH_STREAM, \
+ _TRANSB_HDCP2_AUTH_STREAM)
+#define AUTH_STREAM_TYPE BIT(31)
+#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+ TRANS_HDCP2_AUTH_STREAM(trans) : \
+ PORT_HDCP2_AUTH_STREAM(port))
+
/* Per-pipe DDI Function Control */
#define _TRANS_DDI_FUNC_CTL_A 0x60400
#define _TRANS_DDI_FUNC_CTL_B 0x61400
--
2.26.2
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^ permalink raw reply related [flat|nested] 111+ messages in thread* Re: [PATCH v4 14/16] drm/i915/hdcp: Add HDCP 2.2 stream register
2020-10-27 16:42 ` [Intel-gfx] " Anshuman Gupta
@ 2020-11-05 16:47 ` Ramalingam C
-1 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-05 16:47 UTC (permalink / raw)
To: Anshuman Gupta
Cc: jani.nikula, intel-gfx, dri-devel, uma.shankar, seanpaul, juston.li
On 2020-10-27 at 22:12:06 +0530, Anshuman Gupta wrote:
> Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS
> and HDCP2_AUTH_STREAM register in i915_reg header.
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 30 ++++++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 77461cde6549..c9678c77883d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9894,6 +9894,7 @@ enum skl_power_gate {
> _PORTD_HDCP2_BASE, \
> _PORTE_HDCP2_BASE, \
> _PORTF_HDCP2_BASE) + (x))
> +
> #define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98)
> #define _TRANSA_HDCP2_AUTH 0x66498
> #define _TRANSB_HDCP2_AUTH 0x66598
> @@ -9933,6 +9934,35 @@ enum skl_power_gate {
> TRANS_HDCP2_STATUS(trans) : \
> PORT_HDCP2_STATUS(port))
>
> +#define PORT_HDCP2_STREAM_STATUS(port) _PORT_HDCP2_BASE(port, 0xC0)
> +#define _TRANSA_HDCP2_STREAM_STATUS 0x664C0
> +#define _TRANSB_HDCP2_STREAM_STATUS 0x665C0
> +#define TRANS_HDCP2_STREAM_STATUS(trans) _MMIO_TRANS(trans, \
> + _TRANSA_HDCP2_STREAM_STATUS, \
> + _TRANSB_HDCP2_STREAM_STATUS)
> +#define STREAM_ENCRYPTION_STATUS BIT(31)
> +#define STREAM_TYPE_STATUS BIT(30)
> +#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \
> + (INTEL_GEN(dev_priv) >= 12 ? \
> + TRANS_HDCP2_STREAM_STATUS(trans) : \
> + PORT_HDCP2_STREAM_STATUS(port))
> +
> +#define _PORTA_HDCP2_AUTH_STREAM 0x66F00
> +#define _PORTB_HDCP2_AUTH_STREAM 0x66F04
> +#define PORT_HDCP2_AUTH_STREAM(port) _MMIO_PORT(port, \
> + _PORTA_HDCP2_AUTH_STREAM, \
> + _PORTB_HDCP2_AUTH_STREAM)
> +#define _TRANSA_HDCP2_AUTH_STREAM 0x66F00
> +#define _TRANSB_HDCP2_AUTH_STREAM 0x66F04
> +#define TRANS_HDCP2_AUTH_STREAM(trans) _MMIO_TRANS(trans, \
> + _TRANSA_HDCP2_AUTH_STREAM, \
> + _TRANSB_HDCP2_AUTH_STREAM)
> +#define AUTH_STREAM_TYPE BIT(31)
> +#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \
> + (INTEL_GEN(dev_priv) >= 12 ? \
> + TRANS_HDCP2_AUTH_STREAM(trans) : \
> + PORT_HDCP2_AUTH_STREAM(port))
> +
> /* Per-pipe DDI Function Control */
> #define _TRANS_DDI_FUNC_CTL_A 0x60400
> #define _TRANS_DDI_FUNC_CTL_B 0x61400
> --
> 2.26.2
>
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^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 14/16] drm/i915/hdcp: Add HDCP 2.2 stream register
@ 2020-11-05 16:47 ` Ramalingam C
0 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-05 16:47 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: jani.nikula, intel-gfx, dri-devel, seanpaul
On 2020-10-27 at 22:12:06 +0530, Anshuman Gupta wrote:
> Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS
> and HDCP2_AUTH_STREAM register in i915_reg header.
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 30 ++++++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 77461cde6549..c9678c77883d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9894,6 +9894,7 @@ enum skl_power_gate {
> _PORTD_HDCP2_BASE, \
> _PORTE_HDCP2_BASE, \
> _PORTF_HDCP2_BASE) + (x))
> +
> #define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98)
> #define _TRANSA_HDCP2_AUTH 0x66498
> #define _TRANSB_HDCP2_AUTH 0x66598
> @@ -9933,6 +9934,35 @@ enum skl_power_gate {
> TRANS_HDCP2_STATUS(trans) : \
> PORT_HDCP2_STATUS(port))
>
> +#define PORT_HDCP2_STREAM_STATUS(port) _PORT_HDCP2_BASE(port, 0xC0)
> +#define _TRANSA_HDCP2_STREAM_STATUS 0x664C0
> +#define _TRANSB_HDCP2_STREAM_STATUS 0x665C0
> +#define TRANS_HDCP2_STREAM_STATUS(trans) _MMIO_TRANS(trans, \
> + _TRANSA_HDCP2_STREAM_STATUS, \
> + _TRANSB_HDCP2_STREAM_STATUS)
> +#define STREAM_ENCRYPTION_STATUS BIT(31)
> +#define STREAM_TYPE_STATUS BIT(30)
> +#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \
> + (INTEL_GEN(dev_priv) >= 12 ? \
> + TRANS_HDCP2_STREAM_STATUS(trans) : \
> + PORT_HDCP2_STREAM_STATUS(port))
> +
> +#define _PORTA_HDCP2_AUTH_STREAM 0x66F00
> +#define _PORTB_HDCP2_AUTH_STREAM 0x66F04
> +#define PORT_HDCP2_AUTH_STREAM(port) _MMIO_PORT(port, \
> + _PORTA_HDCP2_AUTH_STREAM, \
> + _PORTB_HDCP2_AUTH_STREAM)
> +#define _TRANSA_HDCP2_AUTH_STREAM 0x66F00
> +#define _TRANSB_HDCP2_AUTH_STREAM 0x66F04
> +#define TRANS_HDCP2_AUTH_STREAM(trans) _MMIO_TRANS(trans, \
> + _TRANSA_HDCP2_AUTH_STREAM, \
> + _TRANSB_HDCP2_AUTH_STREAM)
> +#define AUTH_STREAM_TYPE BIT(31)
> +#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \
> + (INTEL_GEN(dev_priv) >= 12 ? \
> + TRANS_HDCP2_AUTH_STREAM(trans) : \
> + PORT_HDCP2_AUTH_STREAM(port))
> +
> /* Per-pipe DDI Function Control */
> #define _TRANS_DDI_FUNC_CTL_A 0x60400
> #define _TRANS_DDI_FUNC_CTL_B 0x61400
> --
> 2.26.2
>
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^ permalink raw reply [flat|nested] 111+ messages in thread
* [PATCH v4 15/16] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
@ 2020-10-27 16:42 ` Anshuman Gupta
-1 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:42 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: jani.nikula, uma.shankar, seanpaul, Anshuman Gupta, juston.li
Add support for HDCP 2.2 DP MST shim callback.
This adds existing DP HDCP shim callback for Link Authentication
and Encryption and HDCP 2.2 stream encryption
callback.
v2:
Added a WARN_ON() instead of drm_err. [Uma]
Cosmetic chnages. [Uma]
Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
.../drm/i915/display/intel_display_types.h | 4 +
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 80 +++++++++++++++++--
2 files changed, 76 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index dfb5be64e03a..4cbb151ff3cf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -374,6 +374,10 @@ struct intel_hdcp_shim {
int (*config_stream_type)(struct intel_digital_port *dig_port,
bool is_repeater, u8 type);
+ /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */
+ int (*stream_2_2_encryption)(struct intel_digital_port *dig_port,
+ bool enable);
+
/* HDCP2.2 Link Integrity Check */
int (*check_2_2_link)(struct intel_digital_port *dig_port,
struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 4be61e7fde4e..35c1543fe0e2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -698,18 +698,14 @@ intel_dp_mst_hdcp_stream_encryption(struct intel_digital_port *dig_port,
return 0;
}
-static
-bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
- struct intel_connector *connector)
+static bool intel_dp_mst_get_qses_status(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
- struct intel_dp *intel_dp = &dig_port->dp;
struct drm_dp_query_stream_enc_status_ack_reply reply;
+ struct intel_dp *intel_dp = &dig_port->dp;
int ret;
- if (!intel_dp_hdcp_check_link(dig_port, connector))
- return false;
-
ret = drm_dp_send_query_stream_enc_status(&intel_dp->mst_mgr,
connector->port, &reply);
if (ret) {
@@ -722,6 +718,69 @@ bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
return reply.auth_completed && reply.encryption_enabled;
}
+static
+bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
+{
+ if (!intel_dp_hdcp_check_link(dig_port, connector))
+ return false;
+
+ return intel_dp_mst_get_qses_status(dig_port, connector);
+}
+
+static int
+intel_dp_mst_hdcp2_stream_encryption(struct intel_digital_port *dig_port,
+ bool enable)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct hdcp_port_data *data = &dig_port->port_data;
+ struct intel_dp *dp = &dig_port->dp;
+ struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
+ enum port port = dig_port->base.port;
+ /* HDCP2.x register uses stream transcoder */
+ enum transcoder cpu_transcoder = hdcp->stream_transcoder;
+ int ret;
+
+ drm_WARN_ON(&i915->drm, enable &&
+ !!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915, cpu_transcoder, port))
+ & AUTH_STREAM_TYPE) != data->streams[0].stream_type);
+
+ ret = intel_dp_mst_toggle_hdcp_stream_select(dig_port, enable);
+ if (ret)
+ return ret;
+
+ /* Wait for encryption confirmation */
+ if (intel_de_wait_for_register(i915,
+ HDCP2_STREAM_STATUS(i915, cpu_transcoder, port),
+ STREAM_ENCRYPTION_STATUS,
+ enable ? STREAM_ENCRYPTION_STATUS : 0,
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ drm_err(&i915->drm, "Timed out waiting for stream encryption %s\n",
+ enable ? "enabled" : "disabled");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+/*
+ * DP v2.0 I.3.3 ignore the stream signature L' in QSES reply msg reply.
+ * I.3.5 MST source device may use a QSES msg to query downstream status
+ * for a particular stream.
+ */
+static
+int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
+{
+ int ret;
+
+ ret = intel_dp_hdcp2_check_link(dig_port, connector);
+ if (ret)
+ return ret;
+
+ return intel_dp_mst_get_qses_status(dig_port, connector) ? 0 : -EINVAL;
+}
+
static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
.write_an_aksv = intel_dp_hdcp_write_an_aksv,
.read_bksv = intel_dp_hdcp_read_bksv,
@@ -735,7 +794,12 @@ static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
.stream_encryption = intel_dp_mst_hdcp_stream_encryption,
.check_link = intel_dp_mst_hdcp_check_link,
.hdcp_capable = intel_dp_hdcp_capable,
-
+ .write_2_2_msg = intel_dp_hdcp2_write_msg,
+ .read_2_2_msg = intel_dp_hdcp2_read_msg,
+ .config_stream_type = intel_dp_hdcp2_config_stream_type,
+ .stream_2_2_encryption = intel_dp_mst_hdcp2_stream_encryption,
+ .check_2_2_link = intel_dp_mst_hdcp2_check_link,
+ .hdcp_2_2_capable = intel_dp_hdcp2_capable,
.protocol = HDCP_PROTOCOL_DP,
};
--
2.26.2
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^ permalink raw reply related [flat|nested] 111+ messages in thread* [Intel-gfx] [PATCH v4 15/16] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks
@ 2020-10-27 16:42 ` Anshuman Gupta
0 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:42 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula, seanpaul
Add support for HDCP 2.2 DP MST shim callback.
This adds existing DP HDCP shim callback for Link Authentication
and Encryption and HDCP 2.2 stream encryption
callback.
v2:
Added a WARN_ON() instead of drm_err. [Uma]
Cosmetic chnages. [Uma]
Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
.../drm/i915/display/intel_display_types.h | 4 +
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 80 +++++++++++++++++--
2 files changed, 76 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index dfb5be64e03a..4cbb151ff3cf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -374,6 +374,10 @@ struct intel_hdcp_shim {
int (*config_stream_type)(struct intel_digital_port *dig_port,
bool is_repeater, u8 type);
+ /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */
+ int (*stream_2_2_encryption)(struct intel_digital_port *dig_port,
+ bool enable);
+
/* HDCP2.2 Link Integrity Check */
int (*check_2_2_link)(struct intel_digital_port *dig_port,
struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 4be61e7fde4e..35c1543fe0e2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -698,18 +698,14 @@ intel_dp_mst_hdcp_stream_encryption(struct intel_digital_port *dig_port,
return 0;
}
-static
-bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
- struct intel_connector *connector)
+static bool intel_dp_mst_get_qses_status(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
- struct intel_dp *intel_dp = &dig_port->dp;
struct drm_dp_query_stream_enc_status_ack_reply reply;
+ struct intel_dp *intel_dp = &dig_port->dp;
int ret;
- if (!intel_dp_hdcp_check_link(dig_port, connector))
- return false;
-
ret = drm_dp_send_query_stream_enc_status(&intel_dp->mst_mgr,
connector->port, &reply);
if (ret) {
@@ -722,6 +718,69 @@ bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
return reply.auth_completed && reply.encryption_enabled;
}
+static
+bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
+{
+ if (!intel_dp_hdcp_check_link(dig_port, connector))
+ return false;
+
+ return intel_dp_mst_get_qses_status(dig_port, connector);
+}
+
+static int
+intel_dp_mst_hdcp2_stream_encryption(struct intel_digital_port *dig_port,
+ bool enable)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct hdcp_port_data *data = &dig_port->port_data;
+ struct intel_dp *dp = &dig_port->dp;
+ struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
+ enum port port = dig_port->base.port;
+ /* HDCP2.x register uses stream transcoder */
+ enum transcoder cpu_transcoder = hdcp->stream_transcoder;
+ int ret;
+
+ drm_WARN_ON(&i915->drm, enable &&
+ !!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915, cpu_transcoder, port))
+ & AUTH_STREAM_TYPE) != data->streams[0].stream_type);
+
+ ret = intel_dp_mst_toggle_hdcp_stream_select(dig_port, enable);
+ if (ret)
+ return ret;
+
+ /* Wait for encryption confirmation */
+ if (intel_de_wait_for_register(i915,
+ HDCP2_STREAM_STATUS(i915, cpu_transcoder, port),
+ STREAM_ENCRYPTION_STATUS,
+ enable ? STREAM_ENCRYPTION_STATUS : 0,
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ drm_err(&i915->drm, "Timed out waiting for stream encryption %s\n",
+ enable ? "enabled" : "disabled");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+/*
+ * DP v2.0 I.3.3 ignore the stream signature L' in QSES reply msg reply.
+ * I.3.5 MST source device may use a QSES msg to query downstream status
+ * for a particular stream.
+ */
+static
+int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
+{
+ int ret;
+
+ ret = intel_dp_hdcp2_check_link(dig_port, connector);
+ if (ret)
+ return ret;
+
+ return intel_dp_mst_get_qses_status(dig_port, connector) ? 0 : -EINVAL;
+}
+
static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
.write_an_aksv = intel_dp_hdcp_write_an_aksv,
.read_bksv = intel_dp_hdcp_read_bksv,
@@ -735,7 +794,12 @@ static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
.stream_encryption = intel_dp_mst_hdcp_stream_encryption,
.check_link = intel_dp_mst_hdcp_check_link,
.hdcp_capable = intel_dp_hdcp_capable,
-
+ .write_2_2_msg = intel_dp_hdcp2_write_msg,
+ .read_2_2_msg = intel_dp_hdcp2_read_msg,
+ .config_stream_type = intel_dp_hdcp2_config_stream_type,
+ .stream_2_2_encryption = intel_dp_mst_hdcp2_stream_encryption,
+ .check_2_2_link = intel_dp_mst_hdcp2_check_link,
+ .hdcp_2_2_capable = intel_dp_hdcp2_capable,
.protocol = HDCP_PROTOCOL_DP,
};
--
2.26.2
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^ permalink raw reply related [flat|nested] 111+ messages in thread* RE: [PATCH v4 15/16] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks
2020-10-27 16:42 ` [Intel-gfx] " Anshuman Gupta
@ 2020-11-02 7:49 ` Shankar, Uma
-1 siblings, 0 replies; 111+ messages in thread
From: Shankar, Uma @ 2020-11-02 7:49 UTC (permalink / raw)
To: Gupta, Anshuman, intel-gfx, dri-devel
Cc: Nikula, Jani, seanpaul, Li, Juston, Gupta, Anshuman
> -----Original Message-----
> From: Anshuman Gupta <anshuman.gupta@intel.com>
> Sent: Tuesday, October 27, 2020 10:12 PM
> To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: seanpaul@chromium.org; Nikula, Jani <jani.nikula@intel.com>; C,
> Ramalingam <ramalingam.c@intel.com>; Li, Juston <juston.li@intel.com>;
> Shankar, Uma <uma.shankar@intel.com>; Gupta, Anshuman
> <anshuman.gupta@intel.com>
> Subject: [PATCH v4 15/16] drm/i915/hdcp: Support for HDCP 2.2 MST shim
> callbacks
>
> Add support for HDCP 2.2 DP MST shim callback.
> This adds existing DP HDCP shim callback for Link Authentication and Encryption
> and HDCP 2.2 stream encryption callback.
>
> v2:
> Added a WARN_ON() instead of drm_err. [Uma] Cosmetic chnages. [Uma]
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 4 +
> drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 80 +++++++++++++++++--
> 2 files changed, 76 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index dfb5be64e03a..4cbb151ff3cf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -374,6 +374,10 @@ struct intel_hdcp_shim {
> int (*config_stream_type)(struct intel_digital_port *dig_port,
> bool is_repeater, u8 type);
>
> + /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link
> */
> + int (*stream_2_2_encryption)(struct intel_digital_port *dig_port,
> + bool enable);
> +
> /* HDCP2.2 Link Integrity Check */
> int (*check_2_2_link)(struct intel_digital_port *dig_port,
> struct intel_connector *connector); diff --git
> a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> index 4be61e7fde4e..35c1543fe0e2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> @@ -698,18 +698,14 @@ intel_dp_mst_hdcp_stream_encryption(struct
> intel_digital_port *dig_port,
> return 0;
> }
>
> -static
> -bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
> - struct intel_connector *connector)
> +static bool intel_dp_mst_get_qses_status(struct intel_digital_port *dig_port,
> + struct intel_connector *connector)
> {
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> - struct intel_dp *intel_dp = &dig_port->dp;
> struct drm_dp_query_stream_enc_status_ack_reply reply;
> + struct intel_dp *intel_dp = &dig_port->dp;
> int ret;
>
> - if (!intel_dp_hdcp_check_link(dig_port, connector))
> - return false;
> -
> ret = drm_dp_send_query_stream_enc_status(&intel_dp->mst_mgr,
> connector->port, &reply);
> if (ret) {
> @@ -722,6 +718,69 @@ bool intel_dp_mst_hdcp_check_link(struct
> intel_digital_port *dig_port,
> return reply.auth_completed && reply.encryption_enabled; }
>
> +static
> +bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
> + struct intel_connector *connector) {
> + if (!intel_dp_hdcp_check_link(dig_port, connector))
> + return false;
> +
> + return intel_dp_mst_get_qses_status(dig_port, connector); }
> +
> +static int
> +intel_dp_mst_hdcp2_stream_encryption(struct intel_digital_port *dig_port,
> + bool enable)
> +{
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + struct hdcp_port_data *data = &dig_port->port_data;
> + struct intel_dp *dp = &dig_port->dp;
> + struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
> + enum port port = dig_port->base.port;
> + /* HDCP2.x register uses stream transcoder */
> + enum transcoder cpu_transcoder = hdcp->stream_transcoder;
> + int ret;
> +
> + drm_WARN_ON(&i915->drm, enable &&
> + !!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915,
> cpu_transcoder, port))
> + & AUTH_STREAM_TYPE) != data->streams[0].stream_type);
> +
> + ret = intel_dp_mst_toggle_hdcp_stream_select(dig_port, enable);
> + if (ret)
> + return ret;
> +
> + /* Wait for encryption confirmation */
> + if (intel_de_wait_for_register(i915,
> + HDCP2_STREAM_STATUS(i915,
> cpu_transcoder, port),
> + STREAM_ENCRYPTION_STATUS,
> + enable ? STREAM_ENCRYPTION_STATUS : 0,
> +
> HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> + drm_err(&i915->drm, "Timed out waiting for stream encryption
> %s\n",
> + enable ? "enabled" : "disabled");
> + return -ETIMEDOUT;
> + }
> +
> + return 0;
> +}
> +
> +/*
> + * DP v2.0 I.3.3 ignore the stream signature L' in QSES reply msg reply.
> + * I.3.5 MST source device may use a QSES msg to query downstream
> +status
> + * for a particular stream.
> + */
> +static
> +int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port,
> + struct intel_connector *connector) {
> + int ret;
> +
> + ret = intel_dp_hdcp2_check_link(dig_port, connector);
> + if (ret)
> + return ret;
> +
> + return intel_dp_mst_get_qses_status(dig_port, connector) ? 0 :
> +-EINVAL; }
> +
> static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
> .write_an_aksv = intel_dp_hdcp_write_an_aksv,
> .read_bksv = intel_dp_hdcp_read_bksv,
> @@ -735,7 +794,12 @@ static const struct intel_hdcp_shim
> intel_dp_mst_hdcp_shim = {
> .stream_encryption = intel_dp_mst_hdcp_stream_encryption,
> .check_link = intel_dp_mst_hdcp_check_link,
> .hdcp_capable = intel_dp_hdcp_capable,
> -
> + .write_2_2_msg = intel_dp_hdcp2_write_msg,
> + .read_2_2_msg = intel_dp_hdcp2_read_msg,
> + .config_stream_type = intel_dp_hdcp2_config_stream_type,
> + .stream_2_2_encryption = intel_dp_mst_hdcp2_stream_encryption,
> + .check_2_2_link = intel_dp_mst_hdcp2_check_link,
> + .hdcp_2_2_capable = intel_dp_hdcp2_capable,
> .protocol = HDCP_PROTOCOL_DP,
> };
>
> --
> 2.26.2
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 15/16] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks
@ 2020-11-02 7:49 ` Shankar, Uma
0 siblings, 0 replies; 111+ messages in thread
From: Shankar, Uma @ 2020-11-02 7:49 UTC (permalink / raw)
To: Gupta, Anshuman, intel-gfx, dri-devel; +Cc: Nikula, Jani, seanpaul
> -----Original Message-----
> From: Anshuman Gupta <anshuman.gupta@intel.com>
> Sent: Tuesday, October 27, 2020 10:12 PM
> To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: seanpaul@chromium.org; Nikula, Jani <jani.nikula@intel.com>; C,
> Ramalingam <ramalingam.c@intel.com>; Li, Juston <juston.li@intel.com>;
> Shankar, Uma <uma.shankar@intel.com>; Gupta, Anshuman
> <anshuman.gupta@intel.com>
> Subject: [PATCH v4 15/16] drm/i915/hdcp: Support for HDCP 2.2 MST shim
> callbacks
>
> Add support for HDCP 2.2 DP MST shim callback.
> This adds existing DP HDCP shim callback for Link Authentication and Encryption
> and HDCP 2.2 stream encryption callback.
>
> v2:
> Added a WARN_ON() instead of drm_err. [Uma] Cosmetic chnages. [Uma]
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 4 +
> drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 80 +++++++++++++++++--
> 2 files changed, 76 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index dfb5be64e03a..4cbb151ff3cf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -374,6 +374,10 @@ struct intel_hdcp_shim {
> int (*config_stream_type)(struct intel_digital_port *dig_port,
> bool is_repeater, u8 type);
>
> + /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link
> */
> + int (*stream_2_2_encryption)(struct intel_digital_port *dig_port,
> + bool enable);
> +
> /* HDCP2.2 Link Integrity Check */
> int (*check_2_2_link)(struct intel_digital_port *dig_port,
> struct intel_connector *connector); diff --git
> a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> index 4be61e7fde4e..35c1543fe0e2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> @@ -698,18 +698,14 @@ intel_dp_mst_hdcp_stream_encryption(struct
> intel_digital_port *dig_port,
> return 0;
> }
>
> -static
> -bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
> - struct intel_connector *connector)
> +static bool intel_dp_mst_get_qses_status(struct intel_digital_port *dig_port,
> + struct intel_connector *connector)
> {
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> - struct intel_dp *intel_dp = &dig_port->dp;
> struct drm_dp_query_stream_enc_status_ack_reply reply;
> + struct intel_dp *intel_dp = &dig_port->dp;
> int ret;
>
> - if (!intel_dp_hdcp_check_link(dig_port, connector))
> - return false;
> -
> ret = drm_dp_send_query_stream_enc_status(&intel_dp->mst_mgr,
> connector->port, &reply);
> if (ret) {
> @@ -722,6 +718,69 @@ bool intel_dp_mst_hdcp_check_link(struct
> intel_digital_port *dig_port,
> return reply.auth_completed && reply.encryption_enabled; }
>
> +static
> +bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
> + struct intel_connector *connector) {
> + if (!intel_dp_hdcp_check_link(dig_port, connector))
> + return false;
> +
> + return intel_dp_mst_get_qses_status(dig_port, connector); }
> +
> +static int
> +intel_dp_mst_hdcp2_stream_encryption(struct intel_digital_port *dig_port,
> + bool enable)
> +{
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + struct hdcp_port_data *data = &dig_port->port_data;
> + struct intel_dp *dp = &dig_port->dp;
> + struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
> + enum port port = dig_port->base.port;
> + /* HDCP2.x register uses stream transcoder */
> + enum transcoder cpu_transcoder = hdcp->stream_transcoder;
> + int ret;
> +
> + drm_WARN_ON(&i915->drm, enable &&
> + !!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915,
> cpu_transcoder, port))
> + & AUTH_STREAM_TYPE) != data->streams[0].stream_type);
> +
> + ret = intel_dp_mst_toggle_hdcp_stream_select(dig_port, enable);
> + if (ret)
> + return ret;
> +
> + /* Wait for encryption confirmation */
> + if (intel_de_wait_for_register(i915,
> + HDCP2_STREAM_STATUS(i915,
> cpu_transcoder, port),
> + STREAM_ENCRYPTION_STATUS,
> + enable ? STREAM_ENCRYPTION_STATUS : 0,
> +
> HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> + drm_err(&i915->drm, "Timed out waiting for stream encryption
> %s\n",
> + enable ? "enabled" : "disabled");
> + return -ETIMEDOUT;
> + }
> +
> + return 0;
> +}
> +
> +/*
> + * DP v2.0 I.3.3 ignore the stream signature L' in QSES reply msg reply.
> + * I.3.5 MST source device may use a QSES msg to query downstream
> +status
> + * for a particular stream.
> + */
> +static
> +int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port,
> + struct intel_connector *connector) {
> + int ret;
> +
> + ret = intel_dp_hdcp2_check_link(dig_port, connector);
> + if (ret)
> + return ret;
> +
> + return intel_dp_mst_get_qses_status(dig_port, connector) ? 0 :
> +-EINVAL; }
> +
> static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
> .write_an_aksv = intel_dp_hdcp_write_an_aksv,
> .read_bksv = intel_dp_hdcp_read_bksv,
> @@ -735,7 +794,12 @@ static const struct intel_hdcp_shim
> intel_dp_mst_hdcp_shim = {
> .stream_encryption = intel_dp_mst_hdcp_stream_encryption,
> .check_link = intel_dp_mst_hdcp_check_link,
> .hdcp_capable = intel_dp_hdcp_capable,
> -
> + .write_2_2_msg = intel_dp_hdcp2_write_msg,
> + .read_2_2_msg = intel_dp_hdcp2_read_msg,
> + .config_stream_type = intel_dp_hdcp2_config_stream_type,
> + .stream_2_2_encryption = intel_dp_mst_hdcp2_stream_encryption,
> + .check_2_2_link = intel_dp_mst_hdcp2_check_link,
> + .hdcp_2_2_capable = intel_dp_hdcp2_capable,
> .protocol = HDCP_PROTOCOL_DP,
> };
>
> --
> 2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread
* [Intel-gfx] [PATCH v4 15/16] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks
2020-10-27 16:42 ` [Intel-gfx] " Anshuman Gupta
(?)
(?)
@ 2020-11-03 6:27 ` Anshuman Gupta
2020-11-06 9:27 ` Ramalingam C
-1 siblings, 1 reply; 111+ messages in thread
From: Anshuman Gupta @ 2020-11-03 6:27 UTC (permalink / raw)
To: intel-gfx
Add support for HDCP 2.2 DP MST shim callback.
This adds existing DP HDCP shim callback for Link Authentication
and Encryption and HDCP 2.2 stream encryption
callback.
v2:
Added a WARN_ON() instead of drm_err. [Uma]
Cosmetic changes. [Uma]
Cc: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
.../drm/i915/display/intel_display_types.h | 4 +
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 80 +++++++++++++++++--
2 files changed, 76 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index dfb5be64e03a..4cbb151ff3cf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -374,6 +374,10 @@ struct intel_hdcp_shim {
int (*config_stream_type)(struct intel_digital_port *dig_port,
bool is_repeater, u8 type);
+ /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */
+ int (*stream_2_2_encryption)(struct intel_digital_port *dig_port,
+ bool enable);
+
/* HDCP2.2 Link Integrity Check */
int (*check_2_2_link)(struct intel_digital_port *dig_port,
struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 4be61e7fde4e..35c1543fe0e2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -698,18 +698,14 @@ intel_dp_mst_hdcp_stream_encryption(struct intel_digital_port *dig_port,
return 0;
}
-static
-bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
- struct intel_connector *connector)
+static bool intel_dp_mst_get_qses_status(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
- struct intel_dp *intel_dp = &dig_port->dp;
struct drm_dp_query_stream_enc_status_ack_reply reply;
+ struct intel_dp *intel_dp = &dig_port->dp;
int ret;
- if (!intel_dp_hdcp_check_link(dig_port, connector))
- return false;
-
ret = drm_dp_send_query_stream_enc_status(&intel_dp->mst_mgr,
connector->port, &reply);
if (ret) {
@@ -722,6 +718,69 @@ bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
return reply.auth_completed && reply.encryption_enabled;
}
+static
+bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
+{
+ if (!intel_dp_hdcp_check_link(dig_port, connector))
+ return false;
+
+ return intel_dp_mst_get_qses_status(dig_port, connector);
+}
+
+static int
+intel_dp_mst_hdcp2_stream_encryption(struct intel_digital_port *dig_port,
+ bool enable)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct hdcp_port_data *data = &dig_port->port_data;
+ struct intel_dp *dp = &dig_port->dp;
+ struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
+ enum port port = dig_port->base.port;
+ /* HDCP2.x register uses stream transcoder */
+ enum transcoder cpu_transcoder = hdcp->stream_transcoder;
+ int ret;
+
+ drm_WARN_ON(&i915->drm, enable &&
+ !!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915, cpu_transcoder, port))
+ & AUTH_STREAM_TYPE) != data->streams[0].stream_type);
+
+ ret = intel_dp_mst_toggle_hdcp_stream_select(dig_port, enable);
+ if (ret)
+ return ret;
+
+ /* Wait for encryption confirmation */
+ if (intel_de_wait_for_register(i915,
+ HDCP2_STREAM_STATUS(i915, cpu_transcoder, port),
+ STREAM_ENCRYPTION_STATUS,
+ enable ? STREAM_ENCRYPTION_STATUS : 0,
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ drm_err(&i915->drm, "Timed out waiting for stream encryption %s\n",
+ enable ? "enabled" : "disabled");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+/*
+ * DP v2.0 I.3.3 ignore the stream signature L' in QSES reply msg reply.
+ * I.3.5 MST source device may use a QSES msg to query downstream status
+ * for a particular stream.
+ */
+static
+int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
+{
+ int ret;
+
+ ret = intel_dp_hdcp2_check_link(dig_port, connector);
+ if (ret)
+ return ret;
+
+ return intel_dp_mst_get_qses_status(dig_port, connector) ? 0 : -EINVAL;
+}
+
static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
.write_an_aksv = intel_dp_hdcp_write_an_aksv,
.read_bksv = intel_dp_hdcp_read_bksv,
@@ -735,7 +794,12 @@ static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
.stream_encryption = intel_dp_mst_hdcp_stream_encryption,
.check_link = intel_dp_mst_hdcp_check_link,
.hdcp_capable = intel_dp_hdcp_capable,
-
+ .write_2_2_msg = intel_dp_hdcp2_write_msg,
+ .read_2_2_msg = intel_dp_hdcp2_read_msg,
+ .config_stream_type = intel_dp_hdcp2_config_stream_type,
+ .stream_2_2_encryption = intel_dp_mst_hdcp2_stream_encryption,
+ .check_2_2_link = intel_dp_mst_hdcp2_check_link,
+ .hdcp_2_2_capable = intel_dp_hdcp2_capable,
.protocol = HDCP_PROTOCOL_DP,
};
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 15/16] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks
2020-11-03 6:27 ` Anshuman Gupta
@ 2020-11-06 9:27 ` Ramalingam C
2020-11-06 11:12 ` Ramalingam C
0 siblings, 1 reply; 111+ messages in thread
From: Ramalingam C @ 2020-11-06 9:27 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
On 2020-11-03 at 11:57:00 +0530, Anshuman Gupta wrote:
> Add support for HDCP 2.2 DP MST shim callback.
> This adds existing DP HDCP shim callback for Link Authentication
> and Encryption and HDCP 2.2 stream encryption
> callback.
>
> v2:
> Added a WARN_ON() instead of drm_err. [Uma]
> Cosmetic changes. [Uma]
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 4 +
> drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 80 +++++++++++++++++--
> 2 files changed, 76 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index dfb5be64e03a..4cbb151ff3cf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -374,6 +374,10 @@ struct intel_hdcp_shim {
> int (*config_stream_type)(struct intel_digital_port *dig_port,
> bool is_repeater, u8 type);
>
> + /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */
> + int (*stream_2_2_encryption)(struct intel_digital_port *dig_port,
> + bool enable);
> +
> /* HDCP2.2 Link Integrity Check */
> int (*check_2_2_link)(struct intel_digital_port *dig_port,
> struct intel_connector *connector);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> index 4be61e7fde4e..35c1543fe0e2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> @@ -698,18 +698,14 @@ intel_dp_mst_hdcp_stream_encryption(struct intel_digital_port *dig_port,
> return 0;
> }
>
> -static
> -bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
> - struct intel_connector *connector)
> +static bool intel_dp_mst_get_qses_status(struct intel_digital_port *dig_port,
> + struct intel_connector *connector)
> {
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> - struct intel_dp *intel_dp = &dig_port->dp;
> struct drm_dp_query_stream_enc_status_ack_reply reply;
> + struct intel_dp *intel_dp = &dig_port->dp;
> int ret;
>
> - if (!intel_dp_hdcp_check_link(dig_port, connector))
> - return false;
> -
> ret = drm_dp_send_query_stream_enc_status(&intel_dp->mst_mgr,
> connector->port, &reply);
> if (ret) {
> @@ -722,6 +718,69 @@ bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
> return reply.auth_completed && reply.encryption_enabled;
> }
>
> +static
> +bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
> + struct intel_connector *connector)
> +{
> + if (!intel_dp_hdcp_check_link(dig_port, connector))
> + return false;
> +
> + return intel_dp_mst_get_qses_status(dig_port, connector);
> +}
> +
> +static int
> +intel_dp_mst_hdcp2_stream_encryption(struct intel_digital_port *dig_port,
> + bool enable)
> +{
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + struct hdcp_port_data *data = &dig_port->port_data;
> + struct intel_dp *dp = &dig_port->dp;
> + struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
> + enum port port = dig_port->base.port;
> + /* HDCP2.x register uses stream transcoder */
> + enum transcoder cpu_transcoder = hdcp->stream_transcoder;
> + int ret;
> +
> + drm_WARN_ON(&i915->drm, enable &&
> + !!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915, cpu_transcoder, port))
> + & AUTH_STREAM_TYPE) != data->streams[0].stream_type);
> +
> + ret = intel_dp_mst_toggle_hdcp_stream_select(dig_port, enable);
> + if (ret)
> + return ret;
> +
> + /* Wait for encryption confirmation */
> + if (intel_de_wait_for_register(i915,
> + HDCP2_STREAM_STATUS(i915, cpu_transcoder, port),
> + STREAM_ENCRYPTION_STATUS,
> + enable ? STREAM_ENCRYPTION_STATUS : 0,
> + HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> + drm_err(&i915->drm, "Timed out waiting for stream encryption %s\n",
> + enable ? "enabled" : "disabled");
> + return -ETIMEDOUT;
> + }
> +
> + return 0;
> +}
> +
> +/*
> + * DP v2.0 I.3.3 ignore the stream signature L' in QSES reply msg reply.
> + * I.3.5 MST source device may use a QSES msg to query downstream status
> + * for a particular stream.
> + */
> +static
> +int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port,
> + struct intel_connector *connector)
> +{
> + int ret;
> +
> + ret = intel_dp_hdcp2_check_link(dig_port, connector);
> + if (ret)
> + return ret;
> +
> + return intel_dp_mst_get_qses_status(dig_port, connector) ? 0 : -EINVAL;
> +}
> +
> static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
> .write_an_aksv = intel_dp_hdcp_write_an_aksv,
> .read_bksv = intel_dp_hdcp_read_bksv,
> @@ -735,7 +794,12 @@ static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
> .stream_encryption = intel_dp_mst_hdcp_stream_encryption,
> .check_link = intel_dp_mst_hdcp_check_link,
> .hdcp_capable = intel_dp_hdcp_capable,
> -
> + .write_2_2_msg = intel_dp_hdcp2_write_msg,
> + .read_2_2_msg = intel_dp_hdcp2_read_msg,
> + .config_stream_type = intel_dp_hdcp2_config_stream_type,
> + .stream_2_2_encryption = intel_dp_mst_hdcp2_stream_encryption,
> + .check_2_2_link = intel_dp_mst_hdcp2_check_link,
> + .hdcp_2_2_capable = intel_dp_hdcp2_capable,
> .protocol = HDCP_PROTOCOL_DP,
> };
>
> --
> 2.26.2
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 15/16] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks
2020-11-06 9:27 ` Ramalingam C
@ 2020-11-06 11:12 ` Ramalingam C
2020-11-09 5:36 ` Anshuman Gupta
0 siblings, 1 reply; 111+ messages in thread
From: Ramalingam C @ 2020-11-06 11:12 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
On 2020-11-06 at 14:57:25 +0530, Ramalingam C wrote:
> On 2020-11-03 at 11:57:00 +0530, Anshuman Gupta wrote:
> > Add support for HDCP 2.2 DP MST shim callback.
> > This adds existing DP HDCP shim callback for Link Authentication
> > and Encryption and HDCP 2.2 stream encryption
> > callback.
> >
> > v2:
> > Added a WARN_ON() instead of drm_err. [Uma]
> > Cosmetic changes. [Uma]
>
> Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
I think we can improvise further here.
> >
> > Cc: Ramalingam C <ramalingam.c@intel.com>
> > Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > ---
> > .../drm/i915/display/intel_display_types.h | 4 +
> > drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 80 +++++++++++++++++--
> > 2 files changed, 76 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index dfb5be64e03a..4cbb151ff3cf 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -374,6 +374,10 @@ struct intel_hdcp_shim {
> > int (*config_stream_type)(struct intel_digital_port *dig_port,
> > bool is_repeater, u8 type);
> >
> > + /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */
> > + int (*stream_2_2_encryption)(struct intel_digital_port *dig_port,
> > + bool enable);
> > +
> > /* HDCP2.2 Link Integrity Check */
> > int (*check_2_2_link)(struct intel_digital_port *dig_port,
> > struct intel_connector *connector);
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > index 4be61e7fde4e..35c1543fe0e2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > @@ -698,18 +698,14 @@ intel_dp_mst_hdcp_stream_encryption(struct intel_digital_port *dig_port,
> > return 0;
> > }
> >
> > -static
> > -bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
> > - struct intel_connector *connector)
> > +static bool intel_dp_mst_get_qses_status(struct intel_digital_port *dig_port,
> > + struct intel_connector *connector)
> > {
> > struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > - struct intel_dp *intel_dp = &dig_port->dp;
> > struct drm_dp_query_stream_enc_status_ack_reply reply;
> > + struct intel_dp *intel_dp = &dig_port->dp;
> > int ret;
> >
> > - if (!intel_dp_hdcp_check_link(dig_port, connector))
> > - return false;
> > -
> > ret = drm_dp_send_query_stream_enc_status(&intel_dp->mst_mgr,
> > connector->port, &reply);
> > if (ret) {
> > @@ -722,6 +718,69 @@ bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
> > return reply.auth_completed && reply.encryption_enabled;
> > }
> >
> > +static
> > +bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
> > + struct intel_connector *connector)
> > +{
> > + if (!intel_dp_hdcp_check_link(dig_port, connector))
> > + return false;
> > +
> > + return intel_dp_mst_get_qses_status(dig_port, connector);
> > +}
> > +
> > +static int
> > +intel_dp_mst_hdcp2_stream_encryption(struct intel_digital_port *dig_port,
> > + bool enable)
> > +{
> > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > + struct hdcp_port_data *data = &dig_port->port_data;
> > + struct intel_dp *dp = &dig_port->dp;
> > + struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
> > + enum port port = dig_port->base.port;
> > + /* HDCP2.x register uses stream transcoder */
> > + enum transcoder cpu_transcoder = hdcp->stream_transcoder;
> > + int ret;
> > +
> > + drm_WARN_ON(&i915->drm, enable &&
> > + !!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915, cpu_transcoder, port))
> > + & AUTH_STREAM_TYPE) != data->streams[0].stream_type);
> > +
> > + ret = intel_dp_mst_toggle_hdcp_stream_select(dig_port, enable);
> > + if (ret)
> > + return ret;
> > +
> > + /* Wait for encryption confirmation */
> > + if (intel_de_wait_for_register(i915,
> > + HDCP2_STREAM_STATUS(i915, cpu_transcoder, port),
> > + STREAM_ENCRYPTION_STATUS,
> > + enable ? STREAM_ENCRYPTION_STATUS : 0,
> > + HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> > + drm_err(&i915->drm, "Timed out waiting for stream encryption %s\n",
> > + enable ? "enabled" : "disabled");
> > + return -ETIMEDOUT;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +/*
> > + * DP v2.0 I.3.3 ignore the stream signature L' in QSES reply msg reply.
> > + * I.3.5 MST source device may use a QSES msg to query downstream status
> > + * for a particular stream.
> > + */
> > +static
> > +int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port,
> > + struct intel_connector *connector)
> > +{
Since on MST topology only for connector with mst transcoder hdcp
authentication will be done. all other connectors' hdcp enable are just
enabling the stream encryption.
So the check link is needed for the port which has done the real hdcp
authentication. other hdcp instances need the qses check for the stream
encryption status check.
this can be combined schedule the check_link{1.4, 2.2) work only for the
connector with mst transcoder. and in that check_link work, do the qses
check for all the connectors on that mst topology and then do the real
check_link for the mst port alone. This way we avoid the three to four
instance of check link delayed work with one.
-Ram
> > + int ret;
> > +
> > + ret = intel_dp_hdcp2_check_link(dig_port, connector);
> > + if (ret)
> > + return ret;
> > +
> > + return intel_dp_mst_get_qses_status(dig_port, connector) ? 0 : -EINVAL;
> > +}
> > +
> > static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
> > .write_an_aksv = intel_dp_hdcp_write_an_aksv,
> > .read_bksv = intel_dp_hdcp_read_bksv,
> > @@ -735,7 +794,12 @@ static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
> > .stream_encryption = intel_dp_mst_hdcp_stream_encryption,
> > .check_link = intel_dp_mst_hdcp_check_link,
> > .hdcp_capable = intel_dp_hdcp_capable,
> > -
> > + .write_2_2_msg = intel_dp_hdcp2_write_msg,
> > + .read_2_2_msg = intel_dp_hdcp2_read_msg,
> > + .config_stream_type = intel_dp_hdcp2_config_stream_type,
> > + .stream_2_2_encryption = intel_dp_mst_hdcp2_stream_encryption,
> > + .check_2_2_link = intel_dp_mst_hdcp2_check_link,
> > + .hdcp_2_2_capable = intel_dp_hdcp2_capable,
> > .protocol = HDCP_PROTOCOL_DP,
> > };
> >
> > --
> > 2.26.2
> >
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 15/16] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks
2020-11-06 11:12 ` Ramalingam C
@ 2020-11-09 5:36 ` Anshuman Gupta
2020-11-09 8:38 ` Ramalingam C
0 siblings, 1 reply; 111+ messages in thread
From: Anshuman Gupta @ 2020-11-09 5:36 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx
On 2020-11-06 at 16:42:21 +0530, Ramalingam C wrote:
> On 2020-11-06 at 14:57:25 +0530, Ramalingam C wrote:
> > On 2020-11-03 at 11:57:00 +0530, Anshuman Gupta wrote:
> > > Add support for HDCP 2.2 DP MST shim callback.
> > > This adds existing DP HDCP shim callback for Link Authentication
> > > and Encryption and HDCP 2.2 stream encryption
> > > callback.
> > >
> > > v2:
> > > Added a WARN_ON() instead of drm_err. [Uma]
> > > Cosmetic changes. [Uma]
> >
> > Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
> I think we can improvise further here.
>
> > >
> > > Cc: Ramalingam C <ramalingam.c@intel.com>
> > > Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > > ---
> > > .../drm/i915/display/intel_display_types.h | 4 +
> > > drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 80 +++++++++++++++++--
> > > 2 files changed, 76 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index dfb5be64e03a..4cbb151ff3cf 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -374,6 +374,10 @@ struct intel_hdcp_shim {
> > > int (*config_stream_type)(struct intel_digital_port *dig_port,
> > > bool is_repeater, u8 type);
> > >
> > > + /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */
> > > + int (*stream_2_2_encryption)(struct intel_digital_port *dig_port,
> > > + bool enable);
> > > +
> > > /* HDCP2.2 Link Integrity Check */
> > > int (*check_2_2_link)(struct intel_digital_port *dig_port,
> > > struct intel_connector *connector);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > > index 4be61e7fde4e..35c1543fe0e2 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > > @@ -698,18 +698,14 @@ intel_dp_mst_hdcp_stream_encryption(struct intel_digital_port *dig_port,
> > > return 0;
> > > }
> > >
> > > -static
> > > -bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
> > > - struct intel_connector *connector)
> > > +static bool intel_dp_mst_get_qses_status(struct intel_digital_port *dig_port,
> > > + struct intel_connector *connector)
> > > {
> > > struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > > - struct intel_dp *intel_dp = &dig_port->dp;
> > > struct drm_dp_query_stream_enc_status_ack_reply reply;
> > > + struct intel_dp *intel_dp = &dig_port->dp;
> > > int ret;
> > >
> > > - if (!intel_dp_hdcp_check_link(dig_port, connector))
> > > - return false;
> > > -
> > > ret = drm_dp_send_query_stream_enc_status(&intel_dp->mst_mgr,
> > > connector->port, &reply);
> > > if (ret) {
> > > @@ -722,6 +718,69 @@ bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
> > > return reply.auth_completed && reply.encryption_enabled;
> > > }
> > >
> > > +static
> > > +bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
> > > + struct intel_connector *connector)
> > > +{
> > > + if (!intel_dp_hdcp_check_link(dig_port, connector))
> > > + return false;
> > > +
> > > + return intel_dp_mst_get_qses_status(dig_port, connector);
> > > +}
> > > +
> > > +static int
> > > +intel_dp_mst_hdcp2_stream_encryption(struct intel_digital_port *dig_port,
> > > + bool enable)
> > > +{
> > > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > > + struct hdcp_port_data *data = &dig_port->port_data;
> > > + struct intel_dp *dp = &dig_port->dp;
> > > + struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
> > > + enum port port = dig_port->base.port;
> > > + /* HDCP2.x register uses stream transcoder */
> > > + enum transcoder cpu_transcoder = hdcp->stream_transcoder;
> > > + int ret;
> > > +
> > > + drm_WARN_ON(&i915->drm, enable &&
> > > + !!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915, cpu_transcoder, port))
> > > + & AUTH_STREAM_TYPE) != data->streams[0].stream_type);
> > > +
> > > + ret = intel_dp_mst_toggle_hdcp_stream_select(dig_port, enable);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + /* Wait for encryption confirmation */
> > > + if (intel_de_wait_for_register(i915,
> > > + HDCP2_STREAM_STATUS(i915, cpu_transcoder, port),
> > > + STREAM_ENCRYPTION_STATUS,
> > > + enable ? STREAM_ENCRYPTION_STATUS : 0,
> > > + HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> > > + drm_err(&i915->drm, "Timed out waiting for stream encryption %s\n",
> > > + enable ? "enabled" : "disabled");
> > > + return -ETIMEDOUT;
> > > + }
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +/*
> > > + * DP v2.0 I.3.3 ignore the stream signature L' in QSES reply msg reply.
> > > + * I.3.5 MST source device may use a QSES msg to query downstream status
> > > + * for a particular stream.
> > > + */
> > > +static
> > > +int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port,
> > > + struct intel_connector *connector)
> > > +{
>
> Since on MST topology only for connector with mst transcoder hdcp
> authentication will be done. all other connectors' hdcp enable are just
> enabling the stream encryption.
One correction here, driver will authenticate the link and enable the encryption
on the link for the first HDCP request form user space(user space can ask to enable
HDCP on any stream first as it is not aware of master/slave), so driver doesn't
need to distinguish between master trascoder and slave transcoder.
When link is encrypted driver will enable the stream encryption for the stream
which has asked for it.
>
> So the check link is needed for the port which has done the real hdcp
> authentication. other hdcp instances need the qses check for the stream
> encryption status check.
Yes this can be optimized, check link required for the connector
which has involved with link authentication and encryption,
i would prefer to use hdcp->is_repeater for that becuase this will be true
only for the connector which has involved with link authentication and encryption.
>
> this can be combined schedule the check_link{1.4, 2.2) work only for the
> connector with mst transcoder. and in that check_link work, do the qses
> check for all the connectors on that mst topology and then do the real
> check_link for the mst port alone. This way we avoid the three to four
> instance of check link delayed work with one.
I think it would be the better way to skip the link check for the connector
which has hdcp->is_repeater false and limit those only with QSES check
in check_2_2_link shim callback. This will abstract this from intel_hdcp.c
by just keeping in shim callbacks. Please provide your opinion ?
HDCP 1.4 will go through link authentication and encryption for each connector
in DP MST topology, so i belive let it call the check_link for each connector
along with QSES check.
Thanks,
Anshuman Gupta.
>
>
> -Ram
> > > + int ret;
> > > +
> > > + ret = intel_dp_hdcp2_check_link(dig_port, connector);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + return intel_dp_mst_get_qses_status(dig_port, connector) ? 0 : -EINVAL;
> > > +}
> > > +
> > > static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
> > > .write_an_aksv = intel_dp_hdcp_write_an_aksv,
> > > .read_bksv = intel_dp_hdcp_read_bksv,
> > > @@ -735,7 +794,12 @@ static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
> > > .stream_encryption = intel_dp_mst_hdcp_stream_encryption,
> > > .check_link = intel_dp_mst_hdcp_check_link,
> > > .hdcp_capable = intel_dp_hdcp_capable,
> > > -
> > > + .write_2_2_msg = intel_dp_hdcp2_write_msg,
> > > + .read_2_2_msg = intel_dp_hdcp2_read_msg,
> > > + .config_stream_type = intel_dp_hdcp2_config_stream_type,
> > > + .stream_2_2_encryption = intel_dp_mst_hdcp2_stream_encryption,
> > > + .check_2_2_link = intel_dp_mst_hdcp2_check_link,
> > > + .hdcp_2_2_capable = intel_dp_hdcp2_capable,
> > > .protocol = HDCP_PROTOCOL_DP,
> > > };
> > >
> > > --
> > > 2.26.2
> > >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 15/16] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks
2020-11-09 5:36 ` Anshuman Gupta
@ 2020-11-09 8:38 ` Ramalingam C
0 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-09 8:38 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
On 2020-11-09 at 11:06:24 +0530, Anshuman Gupta wrote:
> On 2020-11-06 at 16:42:21 +0530, Ramalingam C wrote:
> > On 2020-11-06 at 14:57:25 +0530, Ramalingam C wrote:
> > > On 2020-11-03 at 11:57:00 +0530, Anshuman Gupta wrote:
> > > > Add support for HDCP 2.2 DP MST shim callback.
> > > > This adds existing DP HDCP shim callback for Link Authentication
> > > > and Encryption and HDCP 2.2 stream encryption
> > > > callback.
> > > >
> > > > v2:
> > > > Added a WARN_ON() instead of drm_err. [Uma]
> > > > Cosmetic changes. [Uma]
> > >
> > > Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
> > I think we can improvise further here.
> >
> > > >
> > > > Cc: Ramalingam C <ramalingam.c@intel.com>
> > > > Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> > > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > > > ---
> > > > .../drm/i915/display/intel_display_types.h | 4 +
> > > > drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 80 +++++++++++++++++--
> > > > 2 files changed, 76 insertions(+), 8 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > index dfb5be64e03a..4cbb151ff3cf 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > @@ -374,6 +374,10 @@ struct intel_hdcp_shim {
> > > > int (*config_stream_type)(struct intel_digital_port *dig_port,
> > > > bool is_repeater, u8 type);
> > > >
> > > > + /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */
> > > > + int (*stream_2_2_encryption)(struct intel_digital_port *dig_port,
> > > > + bool enable);
> > > > +
> > > > /* HDCP2.2 Link Integrity Check */
> > > > int (*check_2_2_link)(struct intel_digital_port *dig_port,
> > > > struct intel_connector *connector);
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > > > index 4be61e7fde4e..35c1543fe0e2 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > > > @@ -698,18 +698,14 @@ intel_dp_mst_hdcp_stream_encryption(struct intel_digital_port *dig_port,
> > > > return 0;
> > > > }
> > > >
> > > > -static
> > > > -bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
> > > > - struct intel_connector *connector)
> > > > +static bool intel_dp_mst_get_qses_status(struct intel_digital_port *dig_port,
> > > > + struct intel_connector *connector)
> > > > {
> > > > struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > > > - struct intel_dp *intel_dp = &dig_port->dp;
> > > > struct drm_dp_query_stream_enc_status_ack_reply reply;
> > > > + struct intel_dp *intel_dp = &dig_port->dp;
> > > > int ret;
> > > >
> > > > - if (!intel_dp_hdcp_check_link(dig_port, connector))
> > > > - return false;
> > > > -
> > > > ret = drm_dp_send_query_stream_enc_status(&intel_dp->mst_mgr,
> > > > connector->port, &reply);
> > > > if (ret) {
> > > > @@ -722,6 +718,69 @@ bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
> > > > return reply.auth_completed && reply.encryption_enabled;
> > > > }
> > > >
> > > > +static
> > > > +bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
> > > > + struct intel_connector *connector)
> > > > +{
> > > > + if (!intel_dp_hdcp_check_link(dig_port, connector))
> > > > + return false;
> > > > +
> > > > + return intel_dp_mst_get_qses_status(dig_port, connector);
> > > > +}
> > > > +
> > > > +static int
> > > > +intel_dp_mst_hdcp2_stream_encryption(struct intel_digital_port *dig_port,
> > > > + bool enable)
> > > > +{
> > > > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > > > + struct hdcp_port_data *data = &dig_port->port_data;
> > > > + struct intel_dp *dp = &dig_port->dp;
> > > > + struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
> > > > + enum port port = dig_port->base.port;
> > > > + /* HDCP2.x register uses stream transcoder */
> > > > + enum transcoder cpu_transcoder = hdcp->stream_transcoder;
> > > > + int ret;
> > > > +
> > > > + drm_WARN_ON(&i915->drm, enable &&
> > > > + !!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915, cpu_transcoder, port))
> > > > + & AUTH_STREAM_TYPE) != data->streams[0].stream_type);
> > > > +
> > > > + ret = intel_dp_mst_toggle_hdcp_stream_select(dig_port, enable);
> > > > + if (ret)
> > > > + return ret;
> > > > +
> > > > + /* Wait for encryption confirmation */
> > > > + if (intel_de_wait_for_register(i915,
> > > > + HDCP2_STREAM_STATUS(i915, cpu_transcoder, port),
> > > > + STREAM_ENCRYPTION_STATUS,
> > > > + enable ? STREAM_ENCRYPTION_STATUS : 0,
> > > > + HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> > > > + drm_err(&i915->drm, "Timed out waiting for stream encryption %s\n",
> > > > + enable ? "enabled" : "disabled");
> > > > + return -ETIMEDOUT;
> > > > + }
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +/*
> > > > + * DP v2.0 I.3.3 ignore the stream signature L' in QSES reply msg reply.
> > > > + * I.3.5 MST source device may use a QSES msg to query downstream status
> > > > + * for a particular stream.
> > > > + */
> > > > +static
> > > > +int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port,
> > > > + struct intel_connector *connector)
> > > > +{
> >
> > Since on MST topology only for connector with mst transcoder hdcp
> > authentication will be done. all other connectors' hdcp enable are just
> > enabling the stream encryption.
> One correction here, driver will authenticate the link and enable the encryption
> on the link for the first HDCP request form user space(user space can ask to enable
> HDCP on any stream first as it is not aware of master/slave), so driver doesn't
> need to distinguish between master trascoder and slave transcoder.
> When link is encrypted driver will enable the stream encryption for the stream
> which has asked for it.
> >
> > So the check link is needed for the port which has done the real hdcp
> > authentication. other hdcp instances need the qses check for the stream
> > encryption status check.
> Yes this can be optimized, check link required for the connector
> which has involved with link authentication and encryption,
> i would prefer to use hdcp->is_repeater for that becuase this will be true
> only for the connector which has involved with link authentication and encryption.
May be we need to comment on why this is_reepeater is checked at this
point..
> >
> > this can be combined schedule the check_link{1.4, 2.2) work only for the
> > connector with mst transcoder. and in that check_link work, do the qses
> > check for all the connectors on that mst topology and then do the real
> > check_link for the mst port alone. This way we avoid the three to four
> > instance of check link delayed work with one.
> I think it would be the better way to skip the link check for the connector
> which has hdcp->is_repeater false and limit those only with QSES check
> in check_2_2_link shim callback. This will abstract this from intel_hdcp.c
> by just keeping in shim callbacks. Please provide your opinion ?
>
> HDCP 1.4 will go through link authentication and encryption for each connector
> in DP MST topology, so i belive let it call the check_link for each connector
> along with QSES check.
With this delayed work count is not going down. If there is any concern
in future, we could revisit this decision. Otherwise this looks fine
now.
-Ram
>
> Thanks,
> Anshuman Gupta.
> >
> >
> > -Ram
> > > > + int ret;
> > > > +
> > > > + ret = intel_dp_hdcp2_check_link(dig_port, connector);
> > > > + if (ret)
> > > > + return ret;
> > > > +
> > > > + return intel_dp_mst_get_qses_status(dig_port, connector) ? 0 : -EINVAL;
> > > > +}
> > > > +
> > > > static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
> > > > .write_an_aksv = intel_dp_hdcp_write_an_aksv,
> > > > .read_bksv = intel_dp_hdcp_read_bksv,
> > > > @@ -735,7 +794,12 @@ static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
> > > > .stream_encryption = intel_dp_mst_hdcp_stream_encryption,
> > > > .check_link = intel_dp_mst_hdcp_check_link,
> > > > .hdcp_capable = intel_dp_hdcp_capable,
> > > > -
> > > > + .write_2_2_msg = intel_dp_hdcp2_write_msg,
> > > > + .read_2_2_msg = intel_dp_hdcp2_read_msg,
> > > > + .config_stream_type = intel_dp_hdcp2_config_stream_type,
> > > > + .stream_2_2_encryption = intel_dp_mst_hdcp2_stream_encryption,
> > > > + .check_2_2_link = intel_dp_mst_hdcp2_check_link,
> > > > + .hdcp_2_2_capable = intel_dp_hdcp2_capable,
> > > > .protocol = HDCP_PROTOCOL_DP,
> > > > };
> > > >
> > > > --
> > > > 2.26.2
> > > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread
* [PATCH v4 16/16] drm/i915/hdcp: Enable HDCP 2.2 MST support
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
@ 2020-10-27 16:42 ` Anshuman Gupta
-1 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:42 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: jani.nikula, uma.shankar, seanpaul, Anshuman Gupta, juston.li
Enable HDCP 2.2 over DP MST.
Authenticate and enable port encryption only once for
an active HDCP 2.2 session, once port is authenticated
and encrypted enable encryption for each stream that
requires encryption on this port.
Similarly disable the stream encryption for each encrypted
stream, once all encrypted stream encryption is disabled,
disable the port HDCP encryption and deauthenticate the port.
Cc: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 46 ++++++++++++++++++++++-
1 file changed, 44 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 87f7aaf3a319..71fd01bf63a6 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1693,6 +1693,32 @@ static int hdcp2_authenticate_sink(struct intel_connector *connector)
return ret;
}
+static int hdcp2_enable_stream_encryption(struct intel_connector *connector)
+{
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct intel_hdcp *hdcp = &connector->hdcp;
+ enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
+ enum port port = dig_port->base.port;
+ int ret = 0;
+
+ if (!(intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder, port)) &
+ LINK_ENCRYPTION_STATUS)) {
+ drm_err(&dev_priv->drm, "HDCP 2.2 Link is not encrypted\n");
+ return -EPERM;
+ }
+
+ if (hdcp->shim->stream_2_2_encryption) {
+ ret = hdcp->shim->stream_2_2_encryption(dig_port, true);
+ if (ret) {
+ drm_err(&dev_priv->drm, "Failed to enable HDCP 2.2 stream enc\n");
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
static int hdcp2_enable_encryption(struct intel_connector *connector)
{
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
@@ -1831,7 +1857,7 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
drm_dbg_kms(&i915->drm, "Port deauth failed.\n");
}
- if (!ret) {
+ if (!ret && !dig_port->port_auth) {
/*
* Ensuring the required 200mSec min time interval between
* Session Key Exchange and encryption.
@@ -1846,6 +1872,8 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
}
}
+ ret = hdcp2_enable_stream_encryption(connector);
+
return ret;
}
@@ -1891,11 +1919,23 @@ static int _intel_hdcp2_disable(struct intel_connector *connector)
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct hdcp_port_data *data = &dig_port->port_data;
+ struct intel_hdcp *hdcp = &connector->hdcp;
int ret;
drm_dbg_kms(&i915->drm, "[%s:%d] HDCP2.2 is being Disabled\n",
connector->base.name, connector->base.base.id);
+ if (hdcp->shim->stream_2_2_encryption) {
+ ret = hdcp->shim->stream_2_2_encryption(dig_port, false);
+ if (ret) {
+ drm_err(&i915->drm, "Failed to disable HDCP 2.2 stream enc\n");
+ return ret;
+ }
+ }
+
+ if (dig_port->num_hdcp_streams > 0)
+ return ret;
+
ret = hdcp2_disable_encryption(connector);
if (hdcp2_deauthenticate_port(connector) < 0)
@@ -1919,6 +1959,7 @@ static int intel_hdcp2_check_link(struct intel_connector *connector)
int ret = 0;
mutex_lock(&hdcp->mutex);
+ mutex_lock(&dig_port->hdcp_mutex);
cpu_transcoder = hdcp->cpu_transcoder;
/* hdcp2_check_link is expected only when HDCP2.2 is Enabled */
@@ -1996,6 +2037,7 @@ static int intel_hdcp2_check_link(struct intel_connector *connector)
}
out:
+ mutex_unlock(&dig_port->hdcp_mutex);
mutex_unlock(&hdcp->mutex);
return ret;
}
@@ -2177,7 +2219,7 @@ int intel_hdcp_init(struct intel_connector *connector,
if (!shim)
return -EINVAL;
- if (is_hdcp2_supported(dev_priv) && !connector->mst_port)
+ if (is_hdcp2_supported(dev_priv))
intel_hdcp2_init(connector, dig_port, shim);
ret =
--
2.26.2
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 111+ messages in thread* [Intel-gfx] [PATCH v4 16/16] drm/i915/hdcp: Enable HDCP 2.2 MST support
@ 2020-10-27 16:42 ` Anshuman Gupta
0 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-27 16:42 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula, seanpaul
Enable HDCP 2.2 over DP MST.
Authenticate and enable port encryption only once for
an active HDCP 2.2 session, once port is authenticated
and encrypted enable encryption for each stream that
requires encryption on this port.
Similarly disable the stream encryption for each encrypted
stream, once all encrypted stream encryption is disabled,
disable the port HDCP encryption and deauthenticate the port.
Cc: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 46 ++++++++++++++++++++++-
1 file changed, 44 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 87f7aaf3a319..71fd01bf63a6 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1693,6 +1693,32 @@ static int hdcp2_authenticate_sink(struct intel_connector *connector)
return ret;
}
+static int hdcp2_enable_stream_encryption(struct intel_connector *connector)
+{
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct intel_hdcp *hdcp = &connector->hdcp;
+ enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
+ enum port port = dig_port->base.port;
+ int ret = 0;
+
+ if (!(intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder, port)) &
+ LINK_ENCRYPTION_STATUS)) {
+ drm_err(&dev_priv->drm, "HDCP 2.2 Link is not encrypted\n");
+ return -EPERM;
+ }
+
+ if (hdcp->shim->stream_2_2_encryption) {
+ ret = hdcp->shim->stream_2_2_encryption(dig_port, true);
+ if (ret) {
+ drm_err(&dev_priv->drm, "Failed to enable HDCP 2.2 stream enc\n");
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
static int hdcp2_enable_encryption(struct intel_connector *connector)
{
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
@@ -1831,7 +1857,7 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
drm_dbg_kms(&i915->drm, "Port deauth failed.\n");
}
- if (!ret) {
+ if (!ret && !dig_port->port_auth) {
/*
* Ensuring the required 200mSec min time interval between
* Session Key Exchange and encryption.
@@ -1846,6 +1872,8 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
}
}
+ ret = hdcp2_enable_stream_encryption(connector);
+
return ret;
}
@@ -1891,11 +1919,23 @@ static int _intel_hdcp2_disable(struct intel_connector *connector)
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct hdcp_port_data *data = &dig_port->port_data;
+ struct intel_hdcp *hdcp = &connector->hdcp;
int ret;
drm_dbg_kms(&i915->drm, "[%s:%d] HDCP2.2 is being Disabled\n",
connector->base.name, connector->base.base.id);
+ if (hdcp->shim->stream_2_2_encryption) {
+ ret = hdcp->shim->stream_2_2_encryption(dig_port, false);
+ if (ret) {
+ drm_err(&i915->drm, "Failed to disable HDCP 2.2 stream enc\n");
+ return ret;
+ }
+ }
+
+ if (dig_port->num_hdcp_streams > 0)
+ return ret;
+
ret = hdcp2_disable_encryption(connector);
if (hdcp2_deauthenticate_port(connector) < 0)
@@ -1919,6 +1959,7 @@ static int intel_hdcp2_check_link(struct intel_connector *connector)
int ret = 0;
mutex_lock(&hdcp->mutex);
+ mutex_lock(&dig_port->hdcp_mutex);
cpu_transcoder = hdcp->cpu_transcoder;
/* hdcp2_check_link is expected only when HDCP2.2 is Enabled */
@@ -1996,6 +2037,7 @@ static int intel_hdcp2_check_link(struct intel_connector *connector)
}
out:
+ mutex_unlock(&dig_port->hdcp_mutex);
mutex_unlock(&hdcp->mutex);
return ret;
}
@@ -2177,7 +2219,7 @@ int intel_hdcp_init(struct intel_connector *connector,
if (!shim)
return -EINVAL;
- if (is_hdcp2_supported(dev_priv) && !connector->mst_port)
+ if (is_hdcp2_supported(dev_priv))
intel_hdcp2_init(connector, dig_port, shim);
ret =
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 111+ messages in thread* Re: [PATCH v4 16/16] drm/i915/hdcp: Enable HDCP 2.2 MST support
2020-10-27 16:42 ` [Intel-gfx] " Anshuman Gupta
@ 2020-11-06 11:58 ` Ramalingam C
-1 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-06 11:58 UTC (permalink / raw)
To: Anshuman Gupta
Cc: jani.nikula, intel-gfx, dri-devel, uma.shankar, seanpaul, juston.li
On 2020-10-27 at 22:12:08 +0530, Anshuman Gupta wrote:
> Enable HDCP 2.2 over DP MST.
> Authenticate and enable port encryption only once for
> an active HDCP 2.2 session, once port is authenticated
> and encrypted enable encryption for each stream that
> requires encryption on this port.
>
> Similarly disable the stream encryption for each encrypted
> stream, once all encrypted stream encryption is disabled,
> disable the port HDCP encryption and deauthenticate the port.
>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 46 ++++++++++++++++++++++-
> 1 file changed, 44 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 87f7aaf3a319..71fd01bf63a6 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -1693,6 +1693,32 @@ static int hdcp2_authenticate_sink(struct intel_connector *connector)
> return ret;
> }
>
> +static int hdcp2_enable_stream_encryption(struct intel_connector *connector)
> +{
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> + struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> + struct intel_hdcp *hdcp = &connector->hdcp;
> + enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
> + enum port port = dig_port->base.port;
> + int ret = 0;
> +
> + if (!(intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder, port)) &
> + LINK_ENCRYPTION_STATUS)) {
> + drm_err(&dev_priv->drm, "HDCP 2.2 Link is not encrypted\n");
Provide the connector details in err.
> + return -EPERM;
> + }
> +
> + if (hdcp->shim->stream_2_2_encryption) {
> + ret = hdcp->shim->stream_2_2_encryption(dig_port, true);
> + if (ret) {
> + drm_err(&dev_priv->drm, "Failed to enable HDCP 2.2 stream enc\n");
connector details.
> + return ret;
> + }
> + }
> +
> + return ret;
> +}
> +
> static int hdcp2_enable_encryption(struct intel_connector *connector)
> {
> struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> @@ -1831,7 +1857,7 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
> drm_dbg_kms(&i915->drm, "Port deauth failed.\n");
> }
>
> - if (!ret) {
> + if (!ret && !dig_port->port_auth) {
> /*
> * Ensuring the required 200mSec min time interval between
> * Session Key Exchange and encryption.
> @@ -1846,6 +1872,8 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
> }
> }
>
> + ret = hdcp2_enable_stream_encryption(connector);
> +
> return ret;
> }
>
> @@ -1891,11 +1919,23 @@ static int _intel_hdcp2_disable(struct intel_connector *connector)
> struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> struct hdcp_port_data *data = &dig_port->port_data;
> + struct intel_hdcp *hdcp = &connector->hdcp;
> int ret;
>
> drm_dbg_kms(&i915->drm, "[%s:%d] HDCP2.2 is being Disabled\n",
> connector->base.name, connector->base.base.id);
>
> + if (hdcp->shim->stream_2_2_encryption) {
> + ret = hdcp->shim->stream_2_2_encryption(dig_port, false);
> + if (ret) {
> + drm_err(&i915->drm, "Failed to disable HDCP 2.2 stream enc\n");
connector details in err.
-Ram
> + return ret;
> + }
> + }
> +
> + if (dig_port->num_hdcp_streams > 0)
> + return ret;
> +
> ret = hdcp2_disable_encryption(connector);
>
> if (hdcp2_deauthenticate_port(connector) < 0)
> @@ -1919,6 +1959,7 @@ static int intel_hdcp2_check_link(struct intel_connector *connector)
> int ret = 0;
>
> mutex_lock(&hdcp->mutex);
> + mutex_lock(&dig_port->hdcp_mutex);
> cpu_transcoder = hdcp->cpu_transcoder;
>
> /* hdcp2_check_link is expected only when HDCP2.2 is Enabled */
> @@ -1996,6 +2037,7 @@ static int intel_hdcp2_check_link(struct intel_connector *connector)
> }
>
> out:
> + mutex_unlock(&dig_port->hdcp_mutex);
> mutex_unlock(&hdcp->mutex);
> return ret;
> }
> @@ -2177,7 +2219,7 @@ int intel_hdcp_init(struct intel_connector *connector,
> if (!shim)
> return -EINVAL;
>
> - if (is_hdcp2_supported(dev_priv) && !connector->mst_port)
> + if (is_hdcp2_supported(dev_priv))
> intel_hdcp2_init(connector, dig_port, shim);
>
> ret =
> --
> 2.26.2
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] [PATCH v4 16/16] drm/i915/hdcp: Enable HDCP 2.2 MST support
@ 2020-11-06 11:58 ` Ramalingam C
0 siblings, 0 replies; 111+ messages in thread
From: Ramalingam C @ 2020-11-06 11:58 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: jani.nikula, intel-gfx, dri-devel, seanpaul
On 2020-10-27 at 22:12:08 +0530, Anshuman Gupta wrote:
> Enable HDCP 2.2 over DP MST.
> Authenticate and enable port encryption only once for
> an active HDCP 2.2 session, once port is authenticated
> and encrypted enable encryption for each stream that
> requires encryption on this port.
>
> Similarly disable the stream encryption for each encrypted
> stream, once all encrypted stream encryption is disabled,
> disable the port HDCP encryption and deauthenticate the port.
>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 46 ++++++++++++++++++++++-
> 1 file changed, 44 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 87f7aaf3a319..71fd01bf63a6 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -1693,6 +1693,32 @@ static int hdcp2_authenticate_sink(struct intel_connector *connector)
> return ret;
> }
>
> +static int hdcp2_enable_stream_encryption(struct intel_connector *connector)
> +{
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> + struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> + struct intel_hdcp *hdcp = &connector->hdcp;
> + enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
> + enum port port = dig_port->base.port;
> + int ret = 0;
> +
> + if (!(intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder, port)) &
> + LINK_ENCRYPTION_STATUS)) {
> + drm_err(&dev_priv->drm, "HDCP 2.2 Link is not encrypted\n");
Provide the connector details in err.
> + return -EPERM;
> + }
> +
> + if (hdcp->shim->stream_2_2_encryption) {
> + ret = hdcp->shim->stream_2_2_encryption(dig_port, true);
> + if (ret) {
> + drm_err(&dev_priv->drm, "Failed to enable HDCP 2.2 stream enc\n");
connector details.
> + return ret;
> + }
> + }
> +
> + return ret;
> +}
> +
> static int hdcp2_enable_encryption(struct intel_connector *connector)
> {
> struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> @@ -1831,7 +1857,7 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
> drm_dbg_kms(&i915->drm, "Port deauth failed.\n");
> }
>
> - if (!ret) {
> + if (!ret && !dig_port->port_auth) {
> /*
> * Ensuring the required 200mSec min time interval between
> * Session Key Exchange and encryption.
> @@ -1846,6 +1872,8 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
> }
> }
>
> + ret = hdcp2_enable_stream_encryption(connector);
> +
> return ret;
> }
>
> @@ -1891,11 +1919,23 @@ static int _intel_hdcp2_disable(struct intel_connector *connector)
> struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> struct hdcp_port_data *data = &dig_port->port_data;
> + struct intel_hdcp *hdcp = &connector->hdcp;
> int ret;
>
> drm_dbg_kms(&i915->drm, "[%s:%d] HDCP2.2 is being Disabled\n",
> connector->base.name, connector->base.base.id);
>
> + if (hdcp->shim->stream_2_2_encryption) {
> + ret = hdcp->shim->stream_2_2_encryption(dig_port, false);
> + if (ret) {
> + drm_err(&i915->drm, "Failed to disable HDCP 2.2 stream enc\n");
connector details in err.
-Ram
> + return ret;
> + }
> + }
> +
> + if (dig_port->num_hdcp_streams > 0)
> + return ret;
> +
> ret = hdcp2_disable_encryption(connector);
>
> if (hdcp2_deauthenticate_port(connector) < 0)
> @@ -1919,6 +1959,7 @@ static int intel_hdcp2_check_link(struct intel_connector *connector)
> int ret = 0;
>
> mutex_lock(&hdcp->mutex);
> + mutex_lock(&dig_port->hdcp_mutex);
> cpu_transcoder = hdcp->cpu_transcoder;
>
> /* hdcp2_check_link is expected only when HDCP2.2 is Enabled */
> @@ -1996,6 +2037,7 @@ static int intel_hdcp2_check_link(struct intel_connector *connector)
> }
>
> out:
> + mutex_unlock(&dig_port->hdcp_mutex);
> mutex_unlock(&hdcp->mutex);
> return ret;
> }
> @@ -2177,7 +2219,7 @@ int intel_hdcp_init(struct intel_connector *connector,
> if (!shim)
> return -EINVAL;
>
> - if (is_hdcp2_supported(dev_priv) && !connector->mst_port)
> + if (is_hdcp2_supported(dev_priv))
> intel_hdcp2_init(connector, dig_port, shim);
>
> ret =
> --
> 2.26.2
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev2)
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
` (16 preceding siblings ...)
(?)
@ 2020-10-28 2:47 ` Patchwork
-1 siblings, 0 replies; 111+ messages in thread
From: Patchwork @ 2020-10-28 2:47 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
== Series Details ==
Series: HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev2)
URL : https://patchwork.freedesktop.org/series/82998/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
bb73b788c82a drm/i915/hdcp: Update CP property in update_pipe
1b2040195053 drm/i915/hdcp: Get conn while content_type changed
734531fa0d46 drm/i915/hotplug: Handle CP_IRQ for DP-MST
1c9e7f470f41 drm/i915/hdcp: DP MST transcoder for link and stream
1b51c22e0608 drm/i915/hdcp: Move HDCP enc status timeout to header
ba5452d71c60 drm/i915/hdcp: HDCP stream encryption support
d7f3f52ee6f6 drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support
364b23b18975 drm/i915/hdcp: Pass dig_port to intel_hdcp_init
9b2956b02d6e drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port
d38e764365d0 misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len
7dcbaf56e27e drm/hdcp: Max MST content streams
9ecb513d0858 drm/i915/hdcp: MST streams support in hdcp port_data
9a53600027fd drm/i915/hdcp: Pass connector to check_2_2_link
3e86f0424b87 drm/i915/hdcp: Add HDCP 2.2 stream register
514afd1e53e6 drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks
-:13: WARNING:TYPO_SPELLING: 'chnages' may be misspelled - perhaps 'changes'?
#13:
Cosmetic chnages. [Uma]
total: 0 errors, 1 warnings, 0 checks, 113 lines checked
d046e7f1a967 drm/i915/hdcp: Enable HDCP 2.2 MST support
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev2)
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
` (17 preceding siblings ...)
(?)
@ 2020-10-28 2:49 ` Patchwork
-1 siblings, 0 replies; 111+ messages in thread
From: Patchwork @ 2020-10-28 2:49 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
== Series Details ==
Series: HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev2)
URL : https://patchwork.freedesktop.org/series/82998/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: expected unsigned int [usertype] *s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216
+./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:864:16: warning: trying to copy expression type 31
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev2)
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
` (18 preceding siblings ...)
(?)
@ 2020-10-28 3:17 ` Patchwork
-1 siblings, 0 replies; 111+ messages in thread
From: Patchwork @ 2020-10-28 3:17 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 11127 bytes --]
== Series Details ==
Series: HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev2)
URL : https://patchwork.freedesktop.org/series/82998/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9206 -> Patchwork_18788
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18788:
### IGT changes ###
#### Possible regressions ####
* {igt@kms_content_protectoin@dp-mst-lic-type-0} (NEW):
- fi-tgl-u2: NOTRUN -> [SKIP][1] +3 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/fi-tgl-u2/igt@kms_content_protectoin@dp-mst-lic-type-0.html
- {fi-tgl-dsi}: NOTRUN -> [SKIP][2] +3 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/fi-tgl-dsi/igt@kms_content_protectoin@dp-mst-lic-type-0.html
- fi-cml-u2: NOTRUN -> [SKIP][3] +3 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/fi-cml-u2/igt@kms_content_protectoin@dp-mst-lic-type-0.html
* {igt@kms_content_protectoin@dp-mst-lic-type-1} (NEW):
- fi-icl-u2: NOTRUN -> [SKIP][4] +3 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/fi-icl-u2/igt@kms_content_protectoin@dp-mst-lic-type-1.html
- fi-icl-y: NOTRUN -> [SKIP][5] +3 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/fi-icl-y/igt@kms_content_protectoin@dp-mst-lic-type-1.html
* {igt@kms_content_protectoin@dp-mst-type-0} (NEW):
- {fi-ehl-1}: NOTRUN -> [SKIP][6] +3 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/fi-ehl-1/igt@kms_content_protectoin@dp-mst-type-0.html
- fi-tgl-y: NOTRUN -> [SKIP][7] +3 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/fi-tgl-y/igt@kms_content_protectoin@dp-mst-type-0.html
New tests
---------
New tests have been introduced between CI_DRM_9206 and Patchwork_18788:
### New CI tests (1) ###
* boot:
- Statuses : 41 pass(s)
- Exec time: [0.0] s
### New IGT tests (4) ###
* igt@kms_content_protectoin@dp-mst-lic-type-0:
- Statuses : 31 skip(s)
- Exec time: [0.0] s
* igt@kms_content_protectoin@dp-mst-lic-type-1:
- Statuses : 31 skip(s)
- Exec time: [0.0] s
* igt@kms_content_protectoin@dp-mst-type-0:
- Statuses : 31 skip(s)
- Exec time: [0.0] s
* igt@kms_content_protectoin@dp-mst-type-1:
- Statuses : 31 skip(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_18788 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2: [PASS][8] -> [DMESG-WARN][9] ([i915#1982])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html
* igt@fbdev@mmap:
- fi-tgl-y: [PASS][10] -> [DMESG-WARN][11] ([i915#1982]) +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-y/igt@fbdev@mmap.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/fi-tgl-y/igt@fbdev@mmap.html
* igt@gem_ctx_create@basic-files:
- fi-apl-guc: [PASS][12] -> [INCOMPLETE][13] ([i915#1635])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-apl-guc/igt@gem_ctx_create@basic-files.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/fi-apl-guc/igt@gem_ctx_create@basic-files.html
* igt@i915_pm_rpm@module-reload:
- fi-byt-j1900: [PASS][14] -> [DMESG-WARN][15] ([i915#1982])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [PASS][16] -> [INCOMPLETE][17] ([i915#2606])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_psr@cursor_plane_move:
- fi-kbl-soraka: [PASS][18] -> [INCOMPLETE][19] ([i915#2606])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-kbl-soraka/igt@kms_psr@cursor_plane_move.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/fi-kbl-soraka/igt@kms_psr@cursor_plane_move.html
* igt@kms_psr@primary_mmap_gtt:
- fi-cml-s: [PASS][20] -> [INCOMPLETE][21] ([i915#2606])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-cml-s/igt@kms_psr@primary_mmap_gtt.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/fi-cml-s/igt@kms_psr@primary_mmap_gtt.html
* igt@prime_self_import@basic-with_two_bos:
- fi-tgl-y: [PASS][22] -> [DMESG-WARN][23] ([i915#402]) +2 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
#### Possible fixes ####
* igt@debugfs_test@read_all_entries:
- {fi-kbl-7560u}: [INCOMPLETE][24] ([i915#2417]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-kbl-7560u/igt@debugfs_test@read_all_entries.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/fi-kbl-7560u/igt@debugfs_test@read_all_entries.html
* igt@i915_module_load@reload:
- {fi-ehl-1}: [DMESG-WARN][26] ([i915#1982]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-ehl-1/igt@i915_module_load@reload.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/fi-ehl-1/igt@i915_module_load@reload.html
- fi-skl-lmem: [DMESG-WARN][28] ([i915#2605]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-skl-lmem/igt@i915_module_load@reload.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/fi-skl-lmem/igt@i915_module_load@reload.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [DMESG-WARN][30] ([i915#1982]) -> [PASS][31]
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@kms_busy@basic@flip:
- {fi-tgl-dsi}: [DMESG-WARN][32] ([i915#1982]) -> [PASS][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-dsi/igt@kms_busy@basic@flip.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/fi-tgl-dsi/igt@kms_busy@basic@flip.html
* igt@kms_chamelium@dp-crc-fast:
- fi-icl-u2: [INCOMPLETE][34] ([i915#2606]) -> [PASS][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-byt-j1900: [DMESG-WARN][36] ([i915#1982]) -> [PASS][37] +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_psr@sprite_plane_onoff:
- fi-tgl-y: [DMESG-WARN][38] ([i915#1982]) -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-y/igt@kms_psr@sprite_plane_onoff.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/fi-tgl-y/igt@kms_psr@sprite_plane_onoff.html
* igt@prime_vgem@basic-read:
- fi-tgl-y: [DMESG-WARN][40] ([i915#402]) -> [PASS][41] +1 similar issue
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-y/igt@prime_vgem@basic-read.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/fi-tgl-y/igt@prime_vgem@basic-read.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1784]: https://gitlab.freedesktop.org/drm/intel/issues/1784
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2417]: https://gitlab.freedesktop.org/drm/intel/issues/2417
[i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605
[i915#2606]: https://gitlab.freedesktop.org/drm/intel/issues/2606
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (43 -> 41)
------------------------------
Missing (2): fi-bsw-cyan fi-bdw-samus
Build changes
-------------
* IGT: IGT_5827 -> IGTPW_5090
* Linux: CI_DRM_9206 -> Patchwork_18788
CI-20190529: 20190529
CI_DRM_9206: 85ce674ff932ed7ca41aef52d8bb42c04fbe2171 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_5090: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5090/index.html
IGT_5827: 7fd7e3fb8b42eb4e62a4575f6edc5a048e5bec3d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18788: d046e7f1a967ed742d1fdecb23c6eb56cddcc95f @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d046e7f1a967 drm/i915/hdcp: Enable HDCP 2.2 MST support
514afd1e53e6 drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks
3e86f0424b87 drm/i915/hdcp: Add HDCP 2.2 stream register
9a53600027fd drm/i915/hdcp: Pass connector to check_2_2_link
9ecb513d0858 drm/i915/hdcp: MST streams support in hdcp port_data
7dcbaf56e27e drm/hdcp: Max MST content streams
d38e764365d0 misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len
9b2956b02d6e drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port
364b23b18975 drm/i915/hdcp: Pass dig_port to intel_hdcp_init
d7f3f52ee6f6 drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support
ba5452d71c60 drm/i915/hdcp: HDCP stream encryption support
1b51c22e0608 drm/i915/hdcp: Move HDCP enc status timeout to header
1c9e7f470f41 drm/i915/hdcp: DP MST transcoder for link and stream
734531fa0d46 drm/i915/hotplug: Handle CP_IRQ for DP-MST
1b2040195053 drm/i915/hdcp: Get conn while content_type changed
bb73b788c82a drm/i915/hdcp: Update CP property in update_pipe
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/index.html
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev2)
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
` (19 preceding siblings ...)
(?)
@ 2020-10-28 6:40 ` Patchwork
2020-10-29 8:37 ` Anshuman Gupta
-1 siblings, 1 reply; 111+ messages in thread
From: Patchwork @ 2020-10-28 6:40 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 27875 bytes --]
== Series Details ==
Series: HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev2)
URL : https://patchwork.freedesktop.org/series/82998/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9206_full -> Patchwork_18788_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18788_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18788_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18788_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@evict:
- shard-skl: [PASS][1] -> [INCOMPLETE][2] +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl9/igt@i915_selftest@live@evict.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl3/igt@i915_selftest@live@evict.html
* igt@kms_big_fb@linear-32bpp-rotate-180:
- shard-glk: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk8/igt@kms_big_fb@linear-32bpp-rotate-180.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-glk2/igt@kms_big_fb@linear-32bpp-rotate-180.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
- shard-iclb: NOTRUN -> [INCOMPLETE][5] +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt:
- shard-tglb: NOTRUN -> [DMESG-WARN][6]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
- shard-iclb: NOTRUN -> [DMESG-WARN][7] +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary:
- shard-tglb: NOTRUN -> [INCOMPLETE][8] +11 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html
* igt@perf_pmu@busy-idle-no-semaphores@rcs0:
- shard-hsw: [PASS][9] -> [FAIL][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw4/igt@perf_pmu@busy-idle-no-semaphores@rcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw4/igt@perf_pmu@busy-idle-no-semaphores@rcs0.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_exec_parallel@engines@userptr}:
- shard-hsw: [PASS][11] -> [FAIL][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw6/igt@gem_exec_parallel@engines@userptr.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw4/igt@gem_exec_parallel@engines@userptr.html
### Piglit changes ###
#### Possible regressions ####
* spec@glsl-4.00@execution@built-in-functions@gs-op-mult-dmat3-dmat3 (NEW):
- {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][13] +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/pig-icl-1065g7/spec@glsl-4.00@execution@built-in-functions@gs-op-mult-dmat3-dmat3.html
New tests
---------
New tests have been introduced between CI_DRM_9206_full and Patchwork_18788_full:
### New CI tests (1) ###
* boot:
- Statuses : 200 pass(s)
- Exec time: [0.0] s
### New IGT tests (4) ###
* igt@kms_content_protection@dp-mst-lic-type-0:
- Statuses : 5 skip(s)
- Exec time: [0.0] s
* igt@kms_content_protection@dp-mst-lic-type-1:
- Statuses : 5 skip(s)
- Exec time: [0.0] s
* igt@kms_content_protection@dp-mst-type-0:
- Statuses : 6 skip(s)
- Exec time: [0.0, 0.00] s
* igt@kms_content_protection@dp-mst-type-1:
- Statuses : 5 skip(s)
- Exec time: [0.0] s
### New Piglit tests (3) ###
* spec@glsl-4.00@execution@built-in-functions@fs-op-mult-dmat4-dmat2x4:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@glsl-4.00@execution@built-in-functions@gs-op-mult-dmat3-dmat3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@glsl-4.00@execution@built-in-functions@gs-op-mult-dmat4x3-double:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_18788_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@drm_read@empty-nonblock:
- shard-glk: [PASS][14] -> [DMESG-WARN][15] ([i915#1982]) +2 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk7/igt@drm_read@empty-nonblock.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-glk5/igt@drm_read@empty-nonblock.html
* igt@gem_exec_parallel@engines@contexts:
- shard-snb: [PASS][16] -> [INCOMPLETE][17] ([i915#82])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-snb5/igt@gem_exec_parallel@engines@contexts.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-snb4/igt@gem_exec_parallel@engines@contexts.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-hsw: [PASS][18] -> [FAIL][19] ([i915#1888])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw1/igt@gem_userptr_blits@unsync-unmap-cycles.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw4/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- shard-skl: [PASS][20] -> [DMESG-WARN][21] ([i915#1982]) +6 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-hsw: [PASS][22] -> [FAIL][23] ([i915#2370])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw1/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
* igt@kms_draw_crc@draw-method-rgb565-blt-xtiled:
- shard-snb: [PASS][24] -> [SKIP][25] ([fdo#109271]) +2 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-snb2/igt@kms_draw_crc@draw-method-rgb565-blt-xtiled.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-snb4/igt@kms_draw_crc@draw-method-rgb565-blt-xtiled.html
* igt@kms_draw_crc@draw-method-rgb565-render-ytiled:
- shard-apl: [PASS][26] -> [DMESG-WARN][27] ([i915#1635] / [i915#1982]) +2 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl8/igt@kms_draw_crc@draw-method-rgb565-render-ytiled.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl6/igt@kms_draw_crc@draw-method-rgb565-render-ytiled.html
* igt@kms_flip@2x-plain-flip-ts-check@ab-vga1-hdmi-a1:
- shard-hsw: [PASS][28] -> [DMESG-WARN][29] ([i915#1982]) +3 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw2/igt@kms_flip@2x-plain-flip-ts-check@ab-vga1-hdmi-a1.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw6/igt@kms_flip@2x-plain-flip-ts-check@ab-vga1-hdmi-a1.html
* igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc:
- shard-snb: [PASS][30] -> [FAIL][31] ([i915#2546])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-snb6/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-snb7/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [PASS][32] -> [INCOMPLETE][33] ([i915#1635] / [i915#2606])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-skl: [PASS][34] -> [DMESG-WARN][35] ([i915#2606])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-skl: [PASS][36] -> [INCOMPLETE][37] ([i915#123]) +3 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff:
- shard-skl: [PASS][38] -> [INCOMPLETE][39] ([i915#123] / [i915#2606])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][40] -> [FAIL][41] ([i915#1635] / [i915#31])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl3/igt@kms_setmode@basic.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl3/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-b-wait-forked-busy:
- shard-kbl: [PASS][42] -> [DMESG-WARN][43] ([i915#1982]) +2 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl1/igt@kms_vblank@pipe-b-wait-forked-busy.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-kbl1/igt@kms_vblank@pipe-b-wait-forked-busy.html
* igt@perf@oa-exponents:
- shard-apl: [PASS][44] -> [SKIP][45] ([fdo#109271] / [i915#1354] / [i915#1635]) +1 similar issue
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl7/igt@perf@oa-exponents.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl3/igt@perf@oa-exponents.html
* igt@perf@rc6-disable:
- shard-hsw: [PASS][46] -> [SKIP][47] ([fdo#109271]) +1 similar issue
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw2/igt@perf@rc6-disable.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw4/igt@perf@rc6-disable.html
- shard-kbl: [PASS][48] -> [SKIP][49] ([fdo#109271] / [i915#1354]) +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl7/igt@perf@rc6-disable.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-kbl4/igt@perf@rc6-disable.html
#### Possible fixes ####
* igt@gem_exec_create@basic:
- shard-snb: [INCOMPLETE][50] ([i915#82]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-snb2/igt@gem_exec_create@basic.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-snb4/igt@gem_exec_create@basic.html
* igt@gem_exec_gttfill@all:
- shard-glk: [DMESG-WARN][52] ([i915#118] / [i915#95]) -> [PASS][53]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk5/igt@gem_exec_gttfill@all.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-glk7/igt@gem_exec_gttfill@all.html
* {igt@kms_async_flips@async-flip-with-page-flip-events}:
- shard-kbl: [FAIL][54] ([i915#2521]) -> [PASS][55]
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl1/igt@kms_async_flips@async-flip-with-page-flip-events.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-kbl1/igt@kms_async_flips@async-flip-with-page-flip-events.html
* igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@edp-1-pipe-a:
- shard-skl: [DMESG-WARN][56] ([i915#1982]) -> [PASS][57] +5 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl7/igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@edp-1-pipe-a.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl2/igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@edp-1-pipe-a.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-0:
- shard-kbl: [DMESG-WARN][58] ([i915#1982]) -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl1/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-kbl1/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
* igt@kms_cursor_crc@pipe-c-cursor-alpha-transparent:
- shard-skl: [FAIL][60] ([i915#54]) -> [PASS][61]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl2/igt@kms_cursor_crc@pipe-c-cursor-alpha-transparent.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl2/igt@kms_cursor_crc@pipe-c-cursor-alpha-transparent.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: [INCOMPLETE][62] ([i915#1635]) -> [PASS][63] +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_edge_walk@pipe-c-256x256-left-edge:
- shard-glk: [DMESG-WARN][64] ([i915#1982]) -> [PASS][65] +4 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk4/igt@kms_cursor_edge_walk@pipe-c-256x256-left-edge.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-glk7/igt@kms_cursor_edge_walk@pipe-c-256x256-left-edge.html
* igt@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled:
- shard-hsw: [DMESG-WARN][66] ([i915#1982]) -> [PASS][67]
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw6/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw2/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt:
- shard-skl: [INCOMPLETE][68] ([i915#123]) -> [PASS][69] +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt:
- shard-skl: [INCOMPLETE][70] ([i915#123] / [i915#2606]) -> [PASS][71]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- shard-skl: [SKIP][72] ([fdo#109271]) -> [PASS][73] +7 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl1/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl6/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-kbl: [DMESG-WARN][74] ([i915#165] / [i915#78]) -> [PASS][75]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl2/igt@kms_plane_lowres@pipe-a-tiling-x.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-kbl2/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_vblank@pipe-c-wait-forked-busy:
- shard-apl: [DMESG-WARN][76] ([i915#1635] / [i915#1982]) -> [PASS][77] +3 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl1/igt@kms_vblank@pipe-c-wait-forked-busy.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl8/igt@kms_vblank@pipe-c-wait-forked-busy.html
#### Warnings ####
* igt@core_hotunplug@hotrebind-lateclose:
- shard-hsw: [FAIL][78] -> [WARN][79] ([i915#2283])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw4/igt@core_hotunplug@hotrebind-lateclose.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw1/igt@core_hotunplug@hotrebind-lateclose.html
* igt@kms_flip_tiling@flip-y-tiled:
- shard-skl: [DMESG-WARN][80] ([i915#1982]) -> [FAIL][81] ([i915#699])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl8/igt@kms_flip_tiling@flip-y-tiled.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl1/igt@kms_flip_tiling@flip-y-tiled.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc:
- shard-skl: [INCOMPLETE][82] ([i915#123] / [i915#2606]) -> [DMESG-WARN][83] ([i915#1982])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-modesetfrombusy:
- shard-skl: [SKIP][84] ([fdo#109271]) -> [INCOMPLETE][85] ([i915#123] / [i915#2606])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl1/igt@kms_frontbuffer_tracking@psr-modesetfrombusy.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl10/igt@kms_frontbuffer_tracking@psr-modesetfrombusy.html
* igt@runner@aborted:
- shard-apl: ([FAIL][86], [FAIL][87]) ([i915#1611] / [i915#1635] / [i915#1814]) -> [FAIL][88] ([fdo#109271] / [i915#1635] / [i915#1814])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl7/igt@runner@aborted.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl1/igt@runner@aborted.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl4/igt@runner@aborted.html
- shard-tglb: ([FAIL][89], [FAIL][90], [FAIL][91], [FAIL][92], [FAIL][93], [FAIL][94], [FAIL][95], [FAIL][96], [FAIL][97], [FAIL][98], [FAIL][99], [FAIL][100], [FAIL][101], [FAIL][102], [FAIL][103], [FAIL][104], [FAIL][105], [FAIL][106], [FAIL][107], [FAIL][108], [FAIL][109], [FAIL][110], [FAIL][111], [FAIL][112], [FAIL][113]) ([i915#1764] / [i915#1814] / [i915#456] / [k.org#205379]) -> ([FAIL][114], [FAIL][115], [FAIL][116], [FAIL][117], [FAIL][118], [FAIL][119], [FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124], [FAIL][125], [FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138]) ([i915#1602] / [i915#1764] / [i915#1814] / [i915#456] / [k.org#205379])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@runner@aborted.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@runner@aborted.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb8/igt@runner@aborted.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb8/igt@runner@aborted.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@runner@aborted.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb7/igt@runner@aborted.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb8/igt@runner@aborted.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb7/igt@runner@aborted.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb7/igt@runner@aborted.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb1/igt@runner@aborted.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb7/igt@runner@aborted.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb8/igt@runner@aborted.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb8/igt@runner@aborted.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb2/igt@runner@aborted.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb2/igt@runner@aborted.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb8/igt@runner@aborted.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb8/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb5/igt@runner@aborted.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb1/igt@runner@aborted.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb3/igt@runner@aborted.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb6/igt@runner@aborted.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb2/igt@runner@aborted.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb7/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb5/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb7/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb1/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb6/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb2/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb3/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb5/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb6/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb1/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb5/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb6/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123
[i915#1354]: https://gitlab.freedesktop.org/drm/intel/issues/1354
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#1611]: https://gitlab.freedesktop.org/drm/intel/issues/1611
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#1764]: https://gitlab.freedesktop.org/drm/intel/issues/1764
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283
[i915#2370]: https://gitlab.freedesktop.org/drm/intel/issues/2370
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
[i915#2606]: https://gitlab.freedesktop.org/drm/intel/issues/2606
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#699]: https://gitlab.freedesktop.org/drm/intel/issues/699
[i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* IGT: IGT_5827 -> IGTPW_5090
* Linux: CI_DRM_9206 -> Patchwork_18788
CI-20190529: 20190529
CI_DRM_9206: 85ce674ff932ed7ca41aef52d8bb42c04fbe2171 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_5090: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5090/index.html
IGT_5827: 7fd7e3fb8b42eb4e62a4575f6edc5a048e5bec3d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18788: d046e7f1a967ed742d1fdecb23c6eb56cddcc95f @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/index.html
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_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev2)
2020-10-28 6:40 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-10-29 8:37 ` Anshuman Gupta
2020-10-29 22:11 ` Vudum, Lakshminarayana
0 siblings, 1 reply; 111+ messages in thread
From: Anshuman Gupta @ 2020-10-29 8:37 UTC (permalink / raw)
To: lakshminarayana.vudum; +Cc: intel-gfx
Hi Lakshmi,
Below HDCP over DP-MST patchwork series has unrelated failures from GEM and display side as well.
Similar series i had sent earlier on tryboat it was passing
https://patchwork.freedesktop.org/series/82919/
Could you please let us know if below INCOMPLETE and DMESG-WARN are already known issue
in case these are not known issue could we create bug and rerport the results.
All of the below igt@kms_frontbuffer_tracking are failing due to similar dmesg warning.
igt@kms_big_fb is odd one out a kernel panic.
Rest of all are gem failures.
Thanks,
Anshuman Gupta.
On 2020-10-28 at 06:40:42 +0000, Patchwork wrote:
> == Series Details ==
>
> Series: HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev2)
> URL : https://patchwork.freedesktop.org/series/82998/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_9206_full -> Patchwork_18788_full
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_18788_full absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_18788_full, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_18788_full:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@i915_selftest@live@evict:
> - shard-skl: [PASS][1] -> [INCOMPLETE][2] +1 similar issue
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl9/igt@i915_selftest@live@evict.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl3/igt@i915_selftest@live@evict.html
>
> * igt@kms_big_fb@linear-32bpp-rotate-180:
> - shard-glk: [PASS][3] -> [INCOMPLETE][4]
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk8/igt@kms_big_fb@linear-32bpp-rotate-180.html
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-glk2/igt@kms_big_fb@linear-32bpp-rotate-180.html
>
> * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
> - shard-iclb: NOTRUN -> [INCOMPLETE][5] +2 similar issues
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt:
> - shard-tglb: NOTRUN -> [DMESG-WARN][6]
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html
>
> * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
> - shard-iclb: NOTRUN -> [DMESG-WARN][7] +1 similar issue
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
>
> * igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary:
> - shard-tglb: NOTRUN -> [INCOMPLETE][8] +11 similar issues
> [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html
>
> * igt@perf_pmu@busy-idle-no-semaphores@rcs0:
> - shard-hsw: [PASS][9] -> [FAIL][10]
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw4/igt@perf_pmu@busy-idle-no-semaphores@rcs0.html
> [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw4/igt@perf_pmu@busy-idle-no-semaphores@rcs0.html
>
>
> #### Suppressed ####
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * {igt@gem_exec_parallel@engines@userptr}:
> - shard-hsw: [PASS][11] -> [FAIL][12]
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw6/igt@gem_exec_parallel@engines@userptr.html
> [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw4/igt@gem_exec_parallel@engines@userptr.html
>
>
>
> ### Piglit changes ###
>
> #### Possible regressions ####
>
> * spec@glsl-4.00@execution@built-in-functions@gs-op-mult-dmat3-dmat3 (NEW):
> - {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][13] +2 similar issues
> [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/pig-icl-1065g7/spec@glsl-4.00@execution@built-in-functions@gs-op-mult-dmat3-dmat3.html
>
>
> New tests
> ---------
>
> New tests have been introduced between CI_DRM_9206_full and Patchwork_18788_full:
>
> ### New CI tests (1) ###
>
> * boot:
> - Statuses : 200 pass(s)
> - Exec time: [0.0] s
>
>
>
>
> ### New IGT tests (4) ###
>
> * igt@kms_content_protection@dp-mst-lic-type-0:
> - Statuses : 5 skip(s)
> - Exec time: [0.0] s
>
> * igt@kms_content_protection@dp-mst-lic-type-1:
> - Statuses : 5 skip(s)
> - Exec time: [0.0] s
>
> * igt@kms_content_protection@dp-mst-type-0:
> - Statuses : 6 skip(s)
> - Exec time: [0.0, 0.00] s
>
> * igt@kms_content_protection@dp-mst-type-1:
> - Statuses : 5 skip(s)
> - Exec time: [0.0] s
>
>
>
>
> ### New Piglit tests (3) ###
>
> * spec@glsl-4.00@execution@built-in-functions@fs-op-mult-dmat4-dmat2x4:
> - Statuses : 1 incomplete(s)
> - Exec time: [0.0] s
>
> * spec@glsl-4.00@execution@built-in-functions@gs-op-mult-dmat3-dmat3:
> - Statuses : 1 incomplete(s)
> - Exec time: [0.0] s
>
> * spec@glsl-4.00@execution@built-in-functions@gs-op-mult-dmat4x3-double:
> - Statuses : 1 incomplete(s)
> - Exec time: [0.0] s
>
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_18788_full that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@drm_read@empty-nonblock:
> - shard-glk: [PASS][14] -> [DMESG-WARN][15] ([i915#1982]) +2 similar issues
> [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk7/igt@drm_read@empty-nonblock.html
> [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-glk5/igt@drm_read@empty-nonblock.html
>
> * igt@gem_exec_parallel@engines@contexts:
> - shard-snb: [PASS][16] -> [INCOMPLETE][17] ([i915#82])
> [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-snb5/igt@gem_exec_parallel@engines@contexts.html
> [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-snb4/igt@gem_exec_parallel@engines@contexts.html
>
> * igt@gem_userptr_blits@unsync-unmap-cycles:
> - shard-hsw: [PASS][18] -> [FAIL][19] ([i915#1888])
> [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw1/igt@gem_userptr_blits@unsync-unmap-cycles.html
> [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw4/igt@gem_userptr_blits@unsync-unmap-cycles.html
>
> * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
> - shard-skl: [PASS][20] -> [DMESG-WARN][21] ([i915#1982]) +6 similar issues
> [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
> [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
>
> * igt@kms_cursor_legacy@cursor-vs-flip-toggle:
> - shard-hsw: [PASS][22] -> [FAIL][23] ([i915#2370])
> [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw1/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
> [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
>
> * igt@kms_draw_crc@draw-method-rgb565-blt-xtiled:
> - shard-snb: [PASS][24] -> [SKIP][25] ([fdo#109271]) +2 similar issues
> [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-snb2/igt@kms_draw_crc@draw-method-rgb565-blt-xtiled.html
> [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-snb4/igt@kms_draw_crc@draw-method-rgb565-blt-xtiled.html
>
> * igt@kms_draw_crc@draw-method-rgb565-render-ytiled:
> - shard-apl: [PASS][26] -> [DMESG-WARN][27] ([i915#1635] / [i915#1982]) +2 similar issues
> [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl8/igt@kms_draw_crc@draw-method-rgb565-render-ytiled.html
> [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl6/igt@kms_draw_crc@draw-method-rgb565-render-ytiled.html
>
> * igt@kms_flip@2x-plain-flip-ts-check@ab-vga1-hdmi-a1:
> - shard-hsw: [PASS][28] -> [DMESG-WARN][29] ([i915#1982]) +3 similar issues
> [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw2/igt@kms_flip@2x-plain-flip-ts-check@ab-vga1-hdmi-a1.html
> [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw6/igt@kms_flip@2x-plain-flip-ts-check@ab-vga1-hdmi-a1.html
>
> * igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc:
> - shard-snb: [PASS][30] -> [FAIL][31] ([i915#2546])
> [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-snb6/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc.html
> [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-snb7/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc.html
>
> * igt@kms_frontbuffer_tracking@fbc-suspend:
> - shard-apl: [PASS][32] -> [INCOMPLETE][33] ([i915#1635] / [i915#2606])
> [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
> [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
>
> * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-gtt:
> - shard-skl: [PASS][34] -> [DMESG-WARN][35] ([i915#2606])
> [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
> [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
>
> * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite:
> - shard-skl: [PASS][36] -> [INCOMPLETE][37] ([i915#123]) +3 similar issues
> [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
> [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
>
> * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff:
> - shard-skl: [PASS][38] -> [INCOMPLETE][39] ([i915#123] / [i915#2606])
> [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff.html
> [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff.html
>
> * igt@kms_setmode@basic:
> - shard-apl: [PASS][40] -> [FAIL][41] ([i915#1635] / [i915#31])
> [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl3/igt@kms_setmode@basic.html
> [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl3/igt@kms_setmode@basic.html
>
> * igt@kms_vblank@pipe-b-wait-forked-busy:
> - shard-kbl: [PASS][42] -> [DMESG-WARN][43] ([i915#1982]) +2 similar issues
> [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl1/igt@kms_vblank@pipe-b-wait-forked-busy.html
> [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-kbl1/igt@kms_vblank@pipe-b-wait-forked-busy.html
>
> * igt@perf@oa-exponents:
> - shard-apl: [PASS][44] -> [SKIP][45] ([fdo#109271] / [i915#1354] / [i915#1635]) +1 similar issue
> [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl7/igt@perf@oa-exponents.html
> [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl3/igt@perf@oa-exponents.html
>
> * igt@perf@rc6-disable:
> - shard-hsw: [PASS][46] -> [SKIP][47] ([fdo#109271]) +1 similar issue
> [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw2/igt@perf@rc6-disable.html
> [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw4/igt@perf@rc6-disable.html
> - shard-kbl: [PASS][48] -> [SKIP][49] ([fdo#109271] / [i915#1354]) +1 similar issue
> [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl7/igt@perf@rc6-disable.html
> [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-kbl4/igt@perf@rc6-disable.html
>
>
> #### Possible fixes ####
>
> * igt@gem_exec_create@basic:
> - shard-snb: [INCOMPLETE][50] ([i915#82]) -> [PASS][51]
> [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-snb2/igt@gem_exec_create@basic.html
> [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-snb4/igt@gem_exec_create@basic.html
>
> * igt@gem_exec_gttfill@all:
> - shard-glk: [DMESG-WARN][52] ([i915#118] / [i915#95]) -> [PASS][53]
> [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk5/igt@gem_exec_gttfill@all.html
> [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-glk7/igt@gem_exec_gttfill@all.html
>
> * {igt@kms_async_flips@async-flip-with-page-flip-events}:
> - shard-kbl: [FAIL][54] ([i915#2521]) -> [PASS][55]
> [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl1/igt@kms_async_flips@async-flip-with-page-flip-events.html
> [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-kbl1/igt@kms_async_flips@async-flip-with-page-flip-events.html
>
> * igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@edp-1-pipe-a:
> - shard-skl: [DMESG-WARN][56] ([i915#1982]) -> [PASS][57] +5 similar issues
> [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl7/igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@edp-1-pipe-a.html
> [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl2/igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@edp-1-pipe-a.html
>
> * igt@kms_big_fb@x-tiled-8bpp-rotate-0:
> - shard-kbl: [DMESG-WARN][58] ([i915#1982]) -> [PASS][59]
> [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl1/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
> [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-kbl1/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
>
> * igt@kms_cursor_crc@pipe-c-cursor-alpha-transparent:
> - shard-skl: [FAIL][60] ([i915#54]) -> [PASS][61]
> [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl2/igt@kms_cursor_crc@pipe-c-cursor-alpha-transparent.html
> [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl2/igt@kms_cursor_crc@pipe-c-cursor-alpha-transparent.html
>
> * igt@kms_cursor_crc@pipe-c-cursor-suspend:
> - shard-apl: [INCOMPLETE][62] ([i915#1635]) -> [PASS][63] +1 similar issue
> [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
> [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
>
> * igt@kms_cursor_edge_walk@pipe-c-256x256-left-edge:
> - shard-glk: [DMESG-WARN][64] ([i915#1982]) -> [PASS][65] +4 similar issues
> [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk4/igt@kms_cursor_edge_walk@pipe-c-256x256-left-edge.html
> [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-glk7/igt@kms_cursor_edge_walk@pipe-c-256x256-left-edge.html
>
> * igt@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled:
> - shard-hsw: [DMESG-WARN][66] ([i915#1982]) -> [PASS][67]
> [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw6/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled.html
> [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw2/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled.html
>
> * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt:
> - shard-skl: [INCOMPLETE][68] ([i915#123]) -> [PASS][69] +1 similar issue
> [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
> [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
>
> * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt:
> - shard-skl: [INCOMPLETE][70] ([i915#123] / [i915#2606]) -> [PASS][71]
> [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
> [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
>
> * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
> - shard-skl: [SKIP][72] ([fdo#109271]) -> [PASS][73] +7 similar issues
> [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl1/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
> [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl6/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
>
> * igt@kms_plane_lowres@pipe-a-tiling-x:
> - shard-kbl: [DMESG-WARN][74] ([i915#165] / [i915#78]) -> [PASS][75]
> [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl2/igt@kms_plane_lowres@pipe-a-tiling-x.html
> [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-kbl2/igt@kms_plane_lowres@pipe-a-tiling-x.html
>
> * igt@kms_vblank@pipe-c-wait-forked-busy:
> - shard-apl: [DMESG-WARN][76] ([i915#1635] / [i915#1982]) -> [PASS][77] +3 similar issues
> [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl1/igt@kms_vblank@pipe-c-wait-forked-busy.html
> [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl8/igt@kms_vblank@pipe-c-wait-forked-busy.html
>
>
> #### Warnings ####
>
> * igt@core_hotunplug@hotrebind-lateclose:
> - shard-hsw: [FAIL][78] -> [WARN][79] ([i915#2283])
> [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw4/igt@core_hotunplug@hotrebind-lateclose.html
> [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw1/igt@core_hotunplug@hotrebind-lateclose.html
>
> * igt@kms_flip_tiling@flip-y-tiled:
> - shard-skl: [DMESG-WARN][80] ([i915#1982]) -> [FAIL][81] ([i915#699])
> [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl8/igt@kms_flip_tiling@flip-y-tiled.html
> [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl1/igt@kms_flip_tiling@flip-y-tiled.html
>
> * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc:
> - shard-skl: [INCOMPLETE][82] ([i915#123] / [i915#2606]) -> [DMESG-WARN][83] ([i915#1982])
> [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc.html
> [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc.html
>
> * igt@kms_frontbuffer_tracking@psr-modesetfrombusy:
> - shard-skl: [SKIP][84] ([fdo#109271]) -> [INCOMPLETE][85] ([i915#123] / [i915#2606])
> [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl1/igt@kms_frontbuffer_tracking@psr-modesetfrombusy.html
> [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl10/igt@kms_frontbuffer_tracking@psr-modesetfrombusy.html
>
> * igt@runner@aborted:
> - shard-apl: ([FAIL][86], [FAIL][87]) ([i915#1611] / [i915#1635] / [i915#1814]) -> [FAIL][88] ([fdo#109271] / [i915#1635] / [i915#1814])
> [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl7/igt@runner@aborted.html
> [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl1/igt@runner@aborted.html
> [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl4/igt@runner@aborted.html
> - shard-tglb: ([FAIL][89], [FAIL][90], [FAIL][91], [FAIL][92], [FAIL][93], [FAIL][94], [FAIL][95], [FAIL][96], [FAIL][97], [FAIL][98], [FAIL][99], [FAIL][100], [FAIL][101], [FAIL][102], [FAIL][103], [FAIL][104], [FAIL][105], [FAIL][106], [FAIL][107], [FAIL][108], [FAIL][109], [FAIL][110], [FAIL][111], [FAIL][112], [FAIL][113]) ([i915#1764] / [i915#1814] / [i915#456] / [k.org#205379]) -> ([FAIL][114], [FAIL][115], [FAIL][116], [FAIL][117], [FAIL][118], [FAIL][119], [FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124], [FAIL][125], [FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138]) ([i915#1602] / [i915#1764] / [i915#1814] / [i915#456] / [k.org#205379])
> [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
> [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
> [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
> [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@runner@aborted.html
> [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
> [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@runner@aborted.html
> [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
> [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
> [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb8/igt@runner@aborted.html
> [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb8/igt@runner@aborted.html
> [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
> [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
> [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
> [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@runner@aborted.html
> [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb7/igt@runner@aborted.html
> [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
> [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
> [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
> [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb8/igt@runner@aborted.html
> [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
> [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
> [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb7/igt@runner@aborted.html
> [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb7/igt@runner@aborted.html
> [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
> [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
> [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb1/igt@runner@aborted.html
> [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb7/igt@runner@aborted.html
> [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb8/igt@runner@aborted.html
> [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb8/igt@runner@aborted.html
> [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb2/igt@runner@aborted.html
> [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb2/igt@runner@aborted.html
> [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb8/igt@runner@aborted.html
> [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb8/igt@runner@aborted.html
> [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb5/igt@runner@aborted.html
> [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb1/igt@runner@aborted.html
> [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb3/igt@runner@aborted.html
> [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb6/igt@runner@aborted.html
> [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb2/igt@runner@aborted.html
> [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb7/igt@runner@aborted.html
> [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb5/igt@runner@aborted.html
> [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb7/igt@runner@aborted.html
> [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb1/igt@runner@aborted.html
> [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb6/igt@runner@aborted.html
> [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb2/igt@runner@aborted.html
> [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb3/igt@runner@aborted.html
> [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb5/igt@runner@aborted.html
> [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb6/igt@runner@aborted.html
> [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb1/igt@runner@aborted.html
> [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb5/igt@runner@aborted.html
> [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb6/igt@runner@aborted.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
> [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
> [i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123
> [i915#1354]: https://gitlab.freedesktop.org/drm/intel/issues/1354
> [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
> [i915#1611]: https://gitlab.freedesktop.org/drm/intel/issues/1611
> [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
> [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
> [i915#1764]: https://gitlab.freedesktop.org/drm/intel/issues/1764
> [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
> [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
> [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
> [i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283
> [i915#2370]: https://gitlab.freedesktop.org/drm/intel/issues/2370
> [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
> [i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
> [i915#2606]: https://gitlab.freedesktop.org/drm/intel/issues/2606
> [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
> [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
> [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
> [i915#699]: https://gitlab.freedesktop.org/drm/intel/issues/699
> [i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78
> [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
> [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
> [k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
>
>
> Participating hosts (11 -> 11)
> ------------------------------
>
> No changes in participating hosts
>
>
> Build changes
> -------------
>
> * IGT: IGT_5827 -> IGTPW_5090
> * Linux: CI_DRM_9206 -> Patchwork_18788
>
> CI-20190529: 20190529
> CI_DRM_9206: 85ce674ff932ed7ca41aef52d8bb42c04fbe2171 @ git://anongit.freedesktop.org/gfx-ci/linux
> IGTPW_5090: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5090/index.html
> IGT_5827: 7fd7e3fb8b42eb4e62a4575f6edc5a048e5bec3d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_18788: d046e7f1a967ed742d1fdecb23c6eb56cddcc95f @ git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev2)
2020-10-29 8:37 ` Anshuman Gupta
@ 2020-10-29 22:11 ` Vudum, Lakshminarayana
0 siblings, 0 replies; 111+ messages in thread
From: Vudum, Lakshminarayana @ 2020-10-29 22:11 UTC (permalink / raw)
To: Gupta, Anshuman; +Cc: intel-gfx
@Anshuman Gupta All the failures are addressed and re-reported.
Lakshmi.
-----Original Message-----
From: Anshuman Gupta <anshuman.gupta@intel.com>
Sent: Thursday, October 29, 2020 1:38 AM
To: Vudum, Lakshminarayana <lakshminarayana.vudum@intel.com>
Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>
Subject: Re: ✗ Fi.CI.IGT: failure for HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev2)
Hi Lakshmi,
Below HDCP over DP-MST patchwork series has unrelated failures from GEM and display side as well.
Similar series i had sent earlier on tryboat it was passing https://patchwork.freedesktop.org/series/82919/
Could you please let us know if below INCOMPLETE and DMESG-WARN are already known issue in case these are not known issue could we create bug and rerport the results.
All of the below igt@kms_frontbuffer_tracking are failing due to similar dmesg warning.
igt@kms_big_fb is odd one out a kernel panic.
Rest of all are gem failures.
Thanks,
Anshuman Gupta.
On 2020-10-28 at 06:40:42 +0000, Patchwork wrote:
> == Series Details ==
>
> Series: HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev2)
> URL : https://patchwork.freedesktop.org/series/82998/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_9206_full -> Patchwork_18788_full
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_18788_full absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_18788_full, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_18788_full:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@i915_selftest@live@evict:
> - shard-skl: [PASS][1] -> [INCOMPLETE][2] +1 similar issue
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl9/igt@i915_selftest@live@evict.html
> [2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl3/ig
> t@i915_selftest@live@evict.html
>
> * igt@kms_big_fb@linear-32bpp-rotate-180:
> - shard-glk: [PASS][3] -> [INCOMPLETE][4]
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk8/igt@kms_big_fb@linear-32bpp-rotate-180.html
> [4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-glk2/ig
> t@kms_big_fb@linear-32bpp-rotate-180.html
>
> * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
> - shard-iclb: NOTRUN -> [INCOMPLETE][5] +2 similar issues
> [5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-iclb2/i
> gt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt:
> - shard-tglb: NOTRUN -> [DMESG-WARN][6]
> [6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb7/i
> gt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html
>
> * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
> - shard-iclb: NOTRUN -> [DMESG-WARN][7] +1 similar issue
> [7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-iclb8/i
> gt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
>
> * igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary:
> - shard-tglb: NOTRUN -> [INCOMPLETE][8] +11 similar issues
> [8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb8/i
> gt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html
>
> * igt@perf_pmu@busy-idle-no-semaphores@rcs0:
> - shard-hsw: [PASS][9] -> [FAIL][10]
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw4/igt@perf_pmu@busy-idle-no-semaphores@rcs0.html
> [10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw4/ig
> t@perf_pmu@busy-idle-no-semaphores@rcs0.html
>
>
> #### Suppressed ####
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * {igt@gem_exec_parallel@engines@userptr}:
> - shard-hsw: [PASS][11] -> [FAIL][12]
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw6/igt@gem_exec_parallel@engines@userptr.html
> [12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw4/ig
> t@gem_exec_parallel@engines@userptr.html
>
>
>
> ### Piglit changes ###
>
> #### Possible regressions ####
>
> * spec@glsl-4.00@execution@built-in-functions@gs-op-mult-dmat3-dmat3 (NEW):
> - {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][13] +2 similar issues
> [13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/pig-icl-1065g
> 7/spec@glsl-4.00@execution@built-in-functions@gs-op-mult-dmat3-dmat3.h
> tml
>
>
> New tests
> ---------
>
> New tests have been introduced between CI_DRM_9206_full and Patchwork_18788_full:
>
> ### New CI tests (1) ###
>
> * boot:
> - Statuses : 200 pass(s)
> - Exec time: [0.0] s
>
>
>
>
> ### New IGT tests (4) ###
>
> * igt@kms_content_protection@dp-mst-lic-type-0:
> - Statuses : 5 skip(s)
> - Exec time: [0.0] s
>
> * igt@kms_content_protection@dp-mst-lic-type-1:
> - Statuses : 5 skip(s)
> - Exec time: [0.0] s
>
> * igt@kms_content_protection@dp-mst-type-0:
> - Statuses : 6 skip(s)
> - Exec time: [0.0, 0.00] s
>
> * igt@kms_content_protection@dp-mst-type-1:
> - Statuses : 5 skip(s)
> - Exec time: [0.0] s
>
>
>
>
> ### New Piglit tests (3) ###
>
> * spec@glsl-4.00@execution@built-in-functions@fs-op-mult-dmat4-dmat2x4:
> - Statuses : 1 incomplete(s)
> - Exec time: [0.0] s
>
> * spec@glsl-4.00@execution@built-in-functions@gs-op-mult-dmat3-dmat3:
> - Statuses : 1 incomplete(s)
> - Exec time: [0.0] s
>
> * spec@glsl-4.00@execution@built-in-functions@gs-op-mult-dmat4x3-double:
> - Statuses : 1 incomplete(s)
> - Exec time: [0.0] s
>
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_18788_full that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@drm_read@empty-nonblock:
> - shard-glk: [PASS][14] -> [DMESG-WARN][15] ([i915#1982]) +2 similar issues
> [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk7/igt@drm_read@empty-nonblock.html
> [15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-glk5/ig
> t@drm_read@empty-nonblock.html
>
> * igt@gem_exec_parallel@engines@contexts:
> - shard-snb: [PASS][16] -> [INCOMPLETE][17] ([i915#82])
> [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-snb5/igt@gem_exec_parallel@engines@contexts.html
> [17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-snb4/ig
> t@gem_exec_parallel@engines@contexts.html
>
> * igt@gem_userptr_blits@unsync-unmap-cycles:
> - shard-hsw: [PASS][18] -> [FAIL][19] ([i915#1888])
> [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw1/igt@gem_userptr_blits@unsync-unmap-cycles.html
> [19]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw4/ig
> t@gem_userptr_blits@unsync-unmap-cycles.html
>
> * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
> - shard-skl: [PASS][20] -> [DMESG-WARN][21] ([i915#1982]) +6 similar issues
> [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
> [21]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl8/ig
> t@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
>
> * igt@kms_cursor_legacy@cursor-vs-flip-toggle:
> - shard-hsw: [PASS][22] -> [FAIL][23] ([i915#2370])
> [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw1/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
> [23]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw6/ig
> t@kms_cursor_legacy@cursor-vs-flip-toggle.html
>
> * igt@kms_draw_crc@draw-method-rgb565-blt-xtiled:
> - shard-snb: [PASS][24] -> [SKIP][25] ([fdo#109271]) +2 similar issues
> [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-snb2/igt@kms_draw_crc@draw-method-rgb565-blt-xtiled.html
> [25]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-snb4/ig
> t@kms_draw_crc@draw-method-rgb565-blt-xtiled.html
>
> * igt@kms_draw_crc@draw-method-rgb565-render-ytiled:
> - shard-apl: [PASS][26] -> [DMESG-WARN][27] ([i915#1635] / [i915#1982]) +2 similar issues
> [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl8/igt@kms_draw_crc@draw-method-rgb565-render-ytiled.html
> [27]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl6/ig
> t@kms_draw_crc@draw-method-rgb565-render-ytiled.html
>
> * igt@kms_flip@2x-plain-flip-ts-check@ab-vga1-hdmi-a1:
> - shard-hsw: [PASS][28] -> [DMESG-WARN][29] ([i915#1982]) +3 similar issues
> [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw2/igt@kms_flip@2x-plain-flip-ts-check@ab-vga1-hdmi-a1.html
> [29]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw6/ig
> t@kms_flip@2x-plain-flip-ts-check@ab-vga1-hdmi-a1.html
>
> * igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc:
> - shard-snb: [PASS][30] -> [FAIL][31] ([i915#2546])
> [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-snb6/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc.html
> [31]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-snb7/ig
> t@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc.html
>
> * igt@kms_frontbuffer_tracking@fbc-suspend:
> - shard-apl: [PASS][32] -> [INCOMPLETE][33] ([i915#1635] / [i915#2606])
> [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
> [33]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl4/ig
> t@kms_frontbuffer_tracking@fbc-suspend.html
>
> * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-gtt:
> - shard-skl: [PASS][34] -> [DMESG-WARN][35] ([i915#2606])
> [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
> [35]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl10/i
> gt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-gtt.ht
> ml
>
> * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite:
> - shard-skl: [PASS][36] -> [INCOMPLETE][37] ([i915#123]) +3 similar issues
> [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
> [37]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl2/ig
> t@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
>
> * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff:
> - shard-skl: [PASS][38] -> [INCOMPLETE][39] ([i915#123] / [i915#2606])
> [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff.html
> [39]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl1/ig
> t@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff.html
>
> * igt@kms_setmode@basic:
> - shard-apl: [PASS][40] -> [FAIL][41] ([i915#1635] / [i915#31])
> [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl3/igt@kms_setmode@basic.html
> [41]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl3/ig
> t@kms_setmode@basic.html
>
> * igt@kms_vblank@pipe-b-wait-forked-busy:
> - shard-kbl: [PASS][42] -> [DMESG-WARN][43] ([i915#1982]) +2 similar issues
> [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl1/igt@kms_vblank@pipe-b-wait-forked-busy.html
> [43]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-kbl1/ig
> t@kms_vblank@pipe-b-wait-forked-busy.html
>
> * igt@perf@oa-exponents:
> - shard-apl: [PASS][44] -> [SKIP][45] ([fdo#109271] / [i915#1354] / [i915#1635]) +1 similar issue
> [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl7/igt@perf@oa-exponents.html
> [45]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl3/ig
> t@perf@oa-exponents.html
>
> * igt@perf@rc6-disable:
> - shard-hsw: [PASS][46] -> [SKIP][47] ([fdo#109271]) +1 similar issue
> [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw2/igt@perf@rc6-disable.html
> [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw4/igt@perf@rc6-disable.html
> - shard-kbl: [PASS][48] -> [SKIP][49] ([fdo#109271] / [i915#1354]) +1 similar issue
> [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl7/igt@perf@rc6-disable.html
> [49]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-kbl4/ig
> t@perf@rc6-disable.html
>
>
> #### Possible fixes ####
>
> * igt@gem_exec_create@basic:
> - shard-snb: [INCOMPLETE][50] ([i915#82]) -> [PASS][51]
> [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-snb2/igt@gem_exec_create@basic.html
> [51]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-snb4/ig
> t@gem_exec_create@basic.html
>
> * igt@gem_exec_gttfill@all:
> - shard-glk: [DMESG-WARN][52] ([i915#118] / [i915#95]) -> [PASS][53]
> [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk5/igt@gem_exec_gttfill@all.html
> [53]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-glk7/ig
> t@gem_exec_gttfill@all.html
>
> * {igt@kms_async_flips@async-flip-with-page-flip-events}:
> - shard-kbl: [FAIL][54] ([i915#2521]) -> [PASS][55]
> [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl1/igt@kms_async_flips@async-flip-with-page-flip-events.html
> [55]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-kbl1/ig
> t@kms_async_flips@async-flip-with-page-flip-events.html
>
> * igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@edp-1-pipe-a:
> - shard-skl: [DMESG-WARN][56] ([i915#1982]) -> [PASS][57] +5 similar issues
> [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl7/igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@edp-1-pipe-a.html
> [57]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl2/ig
> t@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@edp
> -1-pipe-a.html
>
> * igt@kms_big_fb@x-tiled-8bpp-rotate-0:
> - shard-kbl: [DMESG-WARN][58] ([i915#1982]) -> [PASS][59]
> [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl1/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
> [59]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-kbl1/ig
> t@kms_big_fb@x-tiled-8bpp-rotate-0.html
>
> * igt@kms_cursor_crc@pipe-c-cursor-alpha-transparent:
> - shard-skl: [FAIL][60] ([i915#54]) -> [PASS][61]
> [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl2/igt@kms_cursor_crc@pipe-c-cursor-alpha-transparent.html
> [61]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl2/ig
> t@kms_cursor_crc@pipe-c-cursor-alpha-transparent.html
>
> * igt@kms_cursor_crc@pipe-c-cursor-suspend:
> - shard-apl: [INCOMPLETE][62] ([i915#1635]) -> [PASS][63] +1 similar issue
> [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
> [63]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl7/ig
> t@kms_cursor_crc@pipe-c-cursor-suspend.html
>
> * igt@kms_cursor_edge_walk@pipe-c-256x256-left-edge:
> - shard-glk: [DMESG-WARN][64] ([i915#1982]) -> [PASS][65] +4 similar issues
> [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk4/igt@kms_cursor_edge_walk@pipe-c-256x256-left-edge.html
> [65]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-glk7/ig
> t@kms_cursor_edge_walk@pipe-c-256x256-left-edge.html
>
> * igt@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled:
> - shard-hsw: [DMESG-WARN][66] ([i915#1982]) -> [PASS][67]
> [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw6/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled.html
> [67]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw2/ig
> t@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled.html
>
> * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt:
> - shard-skl: [INCOMPLETE][68] ([i915#123]) -> [PASS][69] +1 similar issue
> [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
> [69]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl4/ig
> t@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
>
> * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt:
> - shard-skl: [INCOMPLETE][70] ([i915#123] / [i915#2606]) -> [PASS][71]
> [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
> [71]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl7/ig
> t@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
>
> * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
> - shard-skl: [SKIP][72] ([fdo#109271]) -> [PASS][73] +7 similar issues
> [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl1/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
> [73]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl6/ig
> t@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
>
> * igt@kms_plane_lowres@pipe-a-tiling-x:
> - shard-kbl: [DMESG-WARN][74] ([i915#165] / [i915#78]) -> [PASS][75]
> [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl2/igt@kms_plane_lowres@pipe-a-tiling-x.html
> [75]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-kbl2/ig
> t@kms_plane_lowres@pipe-a-tiling-x.html
>
> * igt@kms_vblank@pipe-c-wait-forked-busy:
> - shard-apl: [DMESG-WARN][76] ([i915#1635] / [i915#1982]) -> [PASS][77] +3 similar issues
> [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl1/igt@kms_vblank@pipe-c-wait-forked-busy.html
> [77]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl8/ig
> t@kms_vblank@pipe-c-wait-forked-busy.html
>
>
> #### Warnings ####
>
> * igt@core_hotunplug@hotrebind-lateclose:
> - shard-hsw: [FAIL][78] -> [WARN][79] ([i915#2283])
> [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw4/igt@core_hotunplug@hotrebind-lateclose.html
> [79]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw1/ig
> t@core_hotunplug@hotrebind-lateclose.html
>
> * igt@kms_flip_tiling@flip-y-tiled:
> - shard-skl: [DMESG-WARN][80] ([i915#1982]) -> [FAIL][81] ([i915#699])
> [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl8/igt@kms_flip_tiling@flip-y-tiled.html
> [81]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl1/ig
> t@kms_flip_tiling@flip-y-tiled.html
>
> * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc:
> - shard-skl: [INCOMPLETE][82] ([i915#123] / [i915#2606]) -> [DMESG-WARN][83] ([i915#1982])
> [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc.html
> [83]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl10/i
> gt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc.htm
> l
>
> * igt@kms_frontbuffer_tracking@psr-modesetfrombusy:
> - shard-skl: [SKIP][84] ([fdo#109271]) -> [INCOMPLETE][85] ([i915#123] / [i915#2606])
> [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl1/igt@kms_frontbuffer_tracking@psr-modesetfrombusy.html
> [85]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl10/i
> gt@kms_frontbuffer_tracking@psr-modesetfrombusy.html
>
> * igt@runner@aborted:
> - shard-apl: ([FAIL][86], [FAIL][87]) ([i915#1611] / [i915#1635] / [i915#1814]) -> [FAIL][88] ([fdo#109271] / [i915#1635] / [i915#1814])
> [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl7/igt@runner@aborted.html
> [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl1/igt@runner@aborted.html
> [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl4/igt@runner@aborted.html
> - shard-tglb: ([FAIL][89], [FAIL][90], [FAIL][91], [FAIL][92], [FAIL][93], [FAIL][94], [FAIL][95], [FAIL][96], [FAIL][97], [FAIL][98], [FAIL][99], [FAIL][100], [FAIL][101], [FAIL][102], [FAIL][103], [FAIL][104], [FAIL][105], [FAIL][106], [FAIL][107], [FAIL][108], [FAIL][109], [FAIL][110], [FAIL][111], [FAIL][112], [FAIL][113]) ([i915#1764] / [i915#1814] / [i915#456] / [k.org#205379]) -> ([FAIL][114], [FAIL][115], [FAIL][116], [FAIL][117], [FAIL][118], [FAIL][119], [FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124], [FAIL][125], [FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138]) ([i915#1602] / [i915#1764] / [i915#1814] / [i915#456] / [k.org#205379])
> [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
> [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
> [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
> [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@runner@aborted.html
> [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
> [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@runner@aborted.html
> [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
> [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
> [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb8/igt@runner@aborted.html
> [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb8/igt@runner@aborted.html
> [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
> [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
> [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
> [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@runner@aborted.html
> [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb7/igt@runner@aborted.html
> [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
> [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
> [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
> [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb8/igt@runner@aborted.html
> [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
> [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
> [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb7/igt@runner@aborted.html
> [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb7/igt@runner@aborted.html
> [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
> [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
> [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb1/igt@runner@aborted.html
> [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb7/igt@runner@aborted.html
> [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb8/igt@runner@aborted.html
> [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb8/igt@runner@aborted.html
> [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb2/igt@runner@aborted.html
> [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb2/igt@runner@aborted.html
> [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb8/igt@runner@aborted.html
> [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb8/igt@runner@aborted.html
> [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb5/igt@runner@aborted.html
> [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb1/igt@runner@aborted.html
> [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb3/igt@runner@aborted.html
> [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb6/igt@runner@aborted.html
> [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb2/igt@runner@aborted.html
> [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb7/igt@runner@aborted.html
> [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb5/igt@runner@aborted.html
> [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb7/igt@runner@aborted.html
> [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb1/igt@runner@aborted.html
> [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb6/igt@runner@aborted.html
> [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb2/igt@runner@aborted.html
> [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb3/igt@runner@aborted.html
> [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb5/igt@runner@aborted.html
> [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb6/igt@runner@aborted.html
> [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb1/igt@runner@aborted.html
> [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb5/igt@runner@aborted.html
> [138]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb6/i
> gt@runner@aborted.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
> [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
> [i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123
> [i915#1354]: https://gitlab.freedesktop.org/drm/intel/issues/1354
> [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
> [i915#1611]: https://gitlab.freedesktop.org/drm/intel/issues/1611
> [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
> [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
> [i915#1764]: https://gitlab.freedesktop.org/drm/intel/issues/1764
> [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
> [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
> [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
> [i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283
> [i915#2370]: https://gitlab.freedesktop.org/drm/intel/issues/2370
> [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
> [i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
> [i915#2606]: https://gitlab.freedesktop.org/drm/intel/issues/2606
> [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
> [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
> [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
> [i915#699]: https://gitlab.freedesktop.org/drm/intel/issues/699
> [i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78
> [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
> [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
> [k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
>
>
> Participating hosts (11 -> 11)
> ------------------------------
>
> No changes in participating hosts
>
>
> Build changes
> -------------
>
> * IGT: IGT_5827 -> IGTPW_5090
> * Linux: CI_DRM_9206 -> Patchwork_18788
>
> CI-20190529: 20190529
> CI_DRM_9206: 85ce674ff932ed7ca41aef52d8bb42c04fbe2171 @ git://anongit.freedesktop.org/gfx-ci/linux
> IGTPW_5090: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5090/index.html
> IGT_5827: 7fd7e3fb8b42eb4e62a4575f6edc5a048e5bec3d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_18788: d046e7f1a967ed742d1fdecb23c6eb56cddcc95f @ git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev2)
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
` (20 preceding siblings ...)
(?)
@ 2020-10-29 17:40 ` Patchwork
-1 siblings, 0 replies; 111+ messages in thread
From: Patchwork @ 2020-10-29 17:40 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 27236 bytes --]
== Series Details ==
Series: HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev2)
URL : https://patchwork.freedesktop.org/series/82998/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9206_full -> Patchwork_18788_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18788_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18788_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18788_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_big_fb@linear-32bpp-rotate-180:
- shard-glk: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk8/igt@kms_big_fb@linear-32bpp-rotate-180.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-glk2/igt@kms_big_fb@linear-32bpp-rotate-180.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_exec_parallel@engines@userptr}:
- shard-hsw: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw6/igt@gem_exec_parallel@engines@userptr.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw4/igt@gem_exec_parallel@engines@userptr.html
### Piglit changes ###
#### Possible regressions ####
* spec@glsl-4.00@execution@built-in-functions@gs-op-mult-dmat3-dmat3 (NEW):
- {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][5] +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/pig-icl-1065g7/spec@glsl-4.00@execution@built-in-functions@gs-op-mult-dmat3-dmat3.html
New tests
---------
New tests have been introduced between CI_DRM_9206_full and Patchwork_18788_full:
### New CI tests (1) ###
* boot:
- Statuses : 200 pass(s)
- Exec time: [0.0] s
### New IGT tests (4) ###
* igt@kms_content_protection@dp-mst-lic-type-0:
- Statuses : 5 skip(s)
- Exec time: [0.0] s
* igt@kms_content_protection@dp-mst-lic-type-1:
- Statuses : 5 skip(s)
- Exec time: [0.0] s
* igt@kms_content_protection@dp-mst-type-0:
- Statuses : 6 skip(s)
- Exec time: [0.0, 0.00] s
* igt@kms_content_protection@dp-mst-type-1:
- Statuses : 5 skip(s)
- Exec time: [0.0] s
### New Piglit tests (3) ###
* spec@glsl-4.00@execution@built-in-functions@fs-op-mult-dmat4-dmat2x4:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@glsl-4.00@execution@built-in-functions@gs-op-mult-dmat3-dmat3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@glsl-4.00@execution@built-in-functions@gs-op-mult-dmat4x3-double:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_18788_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@drm_read@empty-nonblock:
- shard-glk: [PASS][6] -> [DMESG-WARN][7] ([i915#1982]) +2 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk7/igt@drm_read@empty-nonblock.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-glk5/igt@drm_read@empty-nonblock.html
* igt@gem_exec_parallel@engines@contexts:
- shard-snb: [PASS][8] -> [INCOMPLETE][9] ([i915#82])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-snb5/igt@gem_exec_parallel@engines@contexts.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-snb4/igt@gem_exec_parallel@engines@contexts.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-hsw: [PASS][10] -> [FAIL][11] ([i915#1888])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw1/igt@gem_userptr_blits@unsync-unmap-cycles.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw4/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@i915_selftest@live@evict:
- shard-skl: [PASS][12] -> [INCOMPLETE][13] ([i915#198])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl9/igt@i915_selftest@live@evict.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl3/igt@i915_selftest@live@evict.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- shard-skl: [PASS][14] -> [DMESG-WARN][15] ([i915#1982]) +6 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-hsw: [PASS][16] -> [FAIL][17] ([i915#2370])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw1/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
* igt@kms_draw_crc@draw-method-rgb565-blt-xtiled:
- shard-snb: [PASS][18] -> [SKIP][19] ([fdo#109271]) +2 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-snb2/igt@kms_draw_crc@draw-method-rgb565-blt-xtiled.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-snb4/igt@kms_draw_crc@draw-method-rgb565-blt-xtiled.html
* igt@kms_draw_crc@draw-method-rgb565-render-ytiled:
- shard-apl: [PASS][20] -> [DMESG-WARN][21] ([i915#1635] / [i915#1982]) +2 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl8/igt@kms_draw_crc@draw-method-rgb565-render-ytiled.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl6/igt@kms_draw_crc@draw-method-rgb565-render-ytiled.html
* igt@kms_flip@2x-plain-flip-ts-check@ab-vga1-hdmi-a1:
- shard-hsw: [PASS][22] -> [DMESG-WARN][23] ([i915#1982]) +3 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw2/igt@kms_flip@2x-plain-flip-ts-check@ab-vga1-hdmi-a1.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw6/igt@kms_flip@2x-plain-flip-ts-check@ab-vga1-hdmi-a1.html
* igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc:
- shard-snb: [PASS][24] -> [FAIL][25] ([i915#2546])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-snb6/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-snb7/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [PASS][26] -> [INCOMPLETE][27] ([i915#1635] / [i915#2606])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-skl: [PASS][28] -> [DMESG-WARN][29] ([i915#2606])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-skl: [PASS][30] -> [INCOMPLETE][31] ([i915#123]) +3 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff:
- shard-skl: [PASS][32] -> [INCOMPLETE][33] ([i915#123] / [i915#2606])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff.html
* igt@kms_psr@cursor_mmap_gtt:
- shard-skl: [PASS][34] -> [INCOMPLETE][35] ([i915#2606])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl4/igt@kms_psr@cursor_mmap_gtt.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl7/igt@kms_psr@cursor_mmap_gtt.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][36] -> [FAIL][37] ([i915#1635] / [i915#31])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl3/igt@kms_setmode@basic.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl3/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-b-wait-forked-busy:
- shard-kbl: [PASS][38] -> [DMESG-WARN][39] ([i915#1982]) +2 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl1/igt@kms_vblank@pipe-b-wait-forked-busy.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-kbl1/igt@kms_vblank@pipe-b-wait-forked-busy.html
* igt@perf@oa-exponents:
- shard-apl: [PASS][40] -> [SKIP][41] ([fdo#109271] / [i915#1354] / [i915#1635]) +1 similar issue
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl7/igt@perf@oa-exponents.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl3/igt@perf@oa-exponents.html
* igt@perf@rc6-disable:
- shard-hsw: [PASS][42] -> [SKIP][43] ([fdo#109271]) +1 similar issue
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw2/igt@perf@rc6-disable.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw4/igt@perf@rc6-disable.html
- shard-kbl: [PASS][44] -> [SKIP][45] ([fdo#109271] / [i915#1354]) +1 similar issue
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl7/igt@perf@rc6-disable.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-kbl4/igt@perf@rc6-disable.html
* igt@perf_pmu@busy-idle-no-semaphores@rcs0:
- shard-hsw: [PASS][46] -> [FAIL][47] ([i915#2614])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw4/igt@perf_pmu@busy-idle-no-semaphores@rcs0.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw4/igt@perf_pmu@busy-idle-no-semaphores@rcs0.html
#### Possible fixes ####
* igt@gem_exec_create@basic:
- shard-snb: [INCOMPLETE][48] ([i915#82]) -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-snb2/igt@gem_exec_create@basic.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-snb4/igt@gem_exec_create@basic.html
* igt@gem_exec_gttfill@all:
- shard-glk: [DMESG-WARN][50] ([i915#118] / [i915#95]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk5/igt@gem_exec_gttfill@all.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-glk7/igt@gem_exec_gttfill@all.html
* {igt@kms_async_flips@async-flip-with-page-flip-events}:
- shard-kbl: [FAIL][52] ([i915#2521]) -> [PASS][53]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl1/igt@kms_async_flips@async-flip-with-page-flip-events.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-kbl1/igt@kms_async_flips@async-flip-with-page-flip-events.html
* igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@edp-1-pipe-a:
- shard-skl: [DMESG-WARN][54] ([i915#1982]) -> [PASS][55] +5 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl7/igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@edp-1-pipe-a.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl2/igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@edp-1-pipe-a.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-0:
- shard-kbl: [DMESG-WARN][56] ([i915#1982]) -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl1/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-kbl1/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
* igt@kms_cursor_crc@pipe-c-cursor-alpha-transparent:
- shard-skl: [FAIL][58] ([i915#54]) -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl2/igt@kms_cursor_crc@pipe-c-cursor-alpha-transparent.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl2/igt@kms_cursor_crc@pipe-c-cursor-alpha-transparent.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: [INCOMPLETE][60] ([i915#1635]) -> [PASS][61] +1 similar issue
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_edge_walk@pipe-c-256x256-left-edge:
- shard-glk: [DMESG-WARN][62] ([i915#1982]) -> [PASS][63] +4 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk4/igt@kms_cursor_edge_walk@pipe-c-256x256-left-edge.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-glk7/igt@kms_cursor_edge_walk@pipe-c-256x256-left-edge.html
* igt@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled:
- shard-hsw: [DMESG-WARN][64] ([i915#1982]) -> [PASS][65]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw6/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw2/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt:
- shard-skl: [INCOMPLETE][66] ([i915#123]) -> [PASS][67] +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt:
- shard-skl: [INCOMPLETE][68] ([i915#123] / [i915#2606]) -> [PASS][69]
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- shard-skl: [SKIP][70] ([fdo#109271]) -> [PASS][71] +7 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl1/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl6/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-kbl: [DMESG-WARN][72] ([i915#165] / [i915#78]) -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl2/igt@kms_plane_lowres@pipe-a-tiling-x.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-kbl2/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_vblank@pipe-c-wait-forked-busy:
- shard-apl: [DMESG-WARN][74] ([i915#1635] / [i915#1982]) -> [PASS][75] +3 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl1/igt@kms_vblank@pipe-c-wait-forked-busy.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl8/igt@kms_vblank@pipe-c-wait-forked-busy.html
#### Warnings ####
* igt@core_hotunplug@hotrebind-lateclose:
- shard-hsw: [FAIL][76] -> [WARN][77] ([i915#2283])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw4/igt@core_hotunplug@hotrebind-lateclose.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw1/igt@core_hotunplug@hotrebind-lateclose.html
* igt@kms_flip_tiling@flip-y-tiled:
- shard-skl: [DMESG-WARN][78] ([i915#1982]) -> [FAIL][79] ([i915#699])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl8/igt@kms_flip_tiling@flip-y-tiled.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl1/igt@kms_flip_tiling@flip-y-tiled.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc:
- shard-skl: [INCOMPLETE][80] ([i915#123] / [i915#2606]) -> [DMESG-WARN][81] ([i915#1982])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-modesetfrombusy:
- shard-skl: [SKIP][82] ([fdo#109271]) -> [INCOMPLETE][83] ([i915#123] / [i915#2606])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl1/igt@kms_frontbuffer_tracking@psr-modesetfrombusy.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl10/igt@kms_frontbuffer_tracking@psr-modesetfrombusy.html
* igt@runner@aborted:
- shard-apl: ([FAIL][84], [FAIL][85]) ([i915#1611] / [i915#1635] / [i915#1814]) -> [FAIL][86] ([fdo#109271] / [i915#1635] / [i915#1814])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl7/igt@runner@aborted.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl1/igt@runner@aborted.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl4/igt@runner@aborted.html
- shard-tglb: ([FAIL][87], [FAIL][88], [FAIL][89], [FAIL][90], [FAIL][91], [FAIL][92], [FAIL][93], [FAIL][94], [FAIL][95], [FAIL][96], [FAIL][97], [FAIL][98], [FAIL][99], [FAIL][100], [FAIL][101], [FAIL][102], [FAIL][103], [FAIL][104], [FAIL][105], [FAIL][106], [FAIL][107], [FAIL][108], [FAIL][109], [FAIL][110], [FAIL][111]) ([i915#1764] / [i915#1814] / [i915#456] / [k.org#205379]) -> ([FAIL][112], [FAIL][113], [FAIL][114], [FAIL][115], [FAIL][116], [FAIL][117], [FAIL][118], [FAIL][119], [FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124], [FAIL][125], [FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136]) ([i915#1602] / [i915#1764] / [i915#1814] / [i915#456] / [k.org#205379])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@runner@aborted.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@runner@aborted.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb8/igt@runner@aborted.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb8/igt@runner@aborted.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@runner@aborted.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb7/igt@runner@aborted.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb8/igt@runner@aborted.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb7/igt@runner@aborted.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb7/igt@runner@aborted.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb1/igt@runner@aborted.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb7/igt@runner@aborted.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb8/igt@runner@aborted.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb8/igt@runner@aborted.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb2/igt@runner@aborted.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb2/igt@runner@aborted.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb8/igt@runner@aborted.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb8/igt@runner@aborted.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb5/igt@runner@aborted.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb1/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb3/igt@runner@aborted.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb6/igt@runner@aborted.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb2/igt@runner@aborted.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb7/igt@runner@aborted.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb5/igt@runner@aborted.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb7/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb1/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb6/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb2/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb3/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb5/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb6/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb1/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb5/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb6/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123
[i915#1354]: https://gitlab.freedesktop.org/drm/intel/issues/1354
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#1611]: https://gitlab.freedesktop.org/drm/intel/issues/1611
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#1764]: https://gitlab.freedesktop.org/drm/intel/issues/1764
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283
[i915#2370]: https://gitlab.freedesktop.org/drm/intel/issues/2370
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
[i915#2606]: https://gitlab.freedesktop.org/drm/intel/issues/2606
[i915#2614]: https://gitlab.freedesktop.org/drm/intel/issues/2614
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#699]: https://gitlab.freedesktop.org/drm/intel/issues/699
[i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* IGT: IGT_5827 -> IGTPW_5090
* Linux: CI_DRM_9206 -> Patchwork_18788
CI-20190529: 20190529
CI_DRM_9206: 85ce674ff932ed7ca41aef52d8bb42c04fbe2171 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_5090: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5090/index.html
IGT_5827: 7fd7e3fb8b42eb4e62a4575f6edc5a048e5bec3d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18788: d046e7f1a967ed742d1fdecb23c6eb56cddcc95f @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/index.html
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev2)
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
` (21 preceding siblings ...)
(?)
@ 2020-10-29 17:54 ` Patchwork
2020-11-02 9:02 ` Anshuman Gupta
-1 siblings, 1 reply; 111+ messages in thread
From: Patchwork @ 2020-10-29 17:54 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 26904 bytes --]
== Series Details ==
Series: HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev2)
URL : https://patchwork.freedesktop.org/series/82998/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9206_full -> Patchwork_18788_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18788_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_exec_parallel@engines@userptr}:
- shard-hsw: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw6/igt@gem_exec_parallel@engines@userptr.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw4/igt@gem_exec_parallel@engines@userptr.html
### Piglit changes ###
#### Possible regressions ####
* spec@glsl-4.00@execution@built-in-functions@gs-op-mult-dmat3-dmat3 (NEW):
- {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][3] +2 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/pig-icl-1065g7/spec@glsl-4.00@execution@built-in-functions@gs-op-mult-dmat3-dmat3.html
New tests
---------
New tests have been introduced between CI_DRM_9206_full and Patchwork_18788_full:
### New CI tests (1) ###
* boot:
- Statuses : 200 pass(s)
- Exec time: [0.0] s
### New IGT tests (4) ###
* igt@kms_content_protection@dp-mst-lic-type-0:
- Statuses : 5 skip(s)
- Exec time: [0.0] s
* igt@kms_content_protection@dp-mst-lic-type-1:
- Statuses : 5 skip(s)
- Exec time: [0.0] s
* igt@kms_content_protection@dp-mst-type-0:
- Statuses : 6 skip(s)
- Exec time: [0.0, 0.00] s
* igt@kms_content_protection@dp-mst-type-1:
- Statuses : 5 skip(s)
- Exec time: [0.0] s
### New Piglit tests (3) ###
* spec@glsl-4.00@execution@built-in-functions@fs-op-mult-dmat4-dmat2x4:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@glsl-4.00@execution@built-in-functions@gs-op-mult-dmat3-dmat3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@glsl-4.00@execution@built-in-functions@gs-op-mult-dmat4x3-double:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_18788_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@drm_read@empty-nonblock:
- shard-glk: [PASS][4] -> [DMESG-WARN][5] ([i915#1982]) +2 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk7/igt@drm_read@empty-nonblock.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-glk5/igt@drm_read@empty-nonblock.html
* igt@gem_exec_parallel@engines@contexts:
- shard-snb: [PASS][6] -> [INCOMPLETE][7] ([i915#82])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-snb5/igt@gem_exec_parallel@engines@contexts.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-snb4/igt@gem_exec_parallel@engines@contexts.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-hsw: [PASS][8] -> [FAIL][9] ([i915#1888])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw1/igt@gem_userptr_blits@unsync-unmap-cycles.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw4/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@i915_selftest@live@evict:
- shard-skl: [PASS][10] -> [INCOMPLETE][11] ([i915#198])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl9/igt@i915_selftest@live@evict.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl3/igt@i915_selftest@live@evict.html
* igt@kms_big_fb@linear-32bpp-rotate-180:
- shard-glk: [PASS][12] -> [INCOMPLETE][13] ([i915#1888])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk8/igt@kms_big_fb@linear-32bpp-rotate-180.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-glk2/igt@kms_big_fb@linear-32bpp-rotate-180.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- shard-skl: [PASS][14] -> [DMESG-WARN][15] ([i915#1982]) +6 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-hsw: [PASS][16] -> [FAIL][17] ([i915#2370])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw1/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
* igt@kms_draw_crc@draw-method-rgb565-blt-xtiled:
- shard-snb: [PASS][18] -> [SKIP][19] ([fdo#109271]) +2 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-snb2/igt@kms_draw_crc@draw-method-rgb565-blt-xtiled.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-snb4/igt@kms_draw_crc@draw-method-rgb565-blt-xtiled.html
* igt@kms_draw_crc@draw-method-rgb565-render-ytiled:
- shard-apl: [PASS][20] -> [DMESG-WARN][21] ([i915#1635] / [i915#1982]) +2 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl8/igt@kms_draw_crc@draw-method-rgb565-render-ytiled.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl6/igt@kms_draw_crc@draw-method-rgb565-render-ytiled.html
* igt@kms_flip@2x-plain-flip-ts-check@ab-vga1-hdmi-a1:
- shard-hsw: [PASS][22] -> [DMESG-WARN][23] ([i915#1982]) +3 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw2/igt@kms_flip@2x-plain-flip-ts-check@ab-vga1-hdmi-a1.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw6/igt@kms_flip@2x-plain-flip-ts-check@ab-vga1-hdmi-a1.html
* igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc:
- shard-snb: [PASS][24] -> [FAIL][25] ([i915#2546])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-snb6/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-snb7/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [PASS][26] -> [INCOMPLETE][27] ([i915#1635] / [i915#2606])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-skl: [PASS][28] -> [DMESG-WARN][29] ([i915#2606])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-skl: [PASS][30] -> [INCOMPLETE][31] ([i915#123]) +3 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff:
- shard-skl: [PASS][32] -> [INCOMPLETE][33] ([i915#123] / [i915#2606])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff.html
* igt@kms_psr@cursor_mmap_gtt:
- shard-skl: [PASS][34] -> [INCOMPLETE][35] ([i915#2606])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl4/igt@kms_psr@cursor_mmap_gtt.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl7/igt@kms_psr@cursor_mmap_gtt.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][36] -> [FAIL][37] ([i915#1635] / [i915#31])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl3/igt@kms_setmode@basic.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl3/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-b-wait-forked-busy:
- shard-kbl: [PASS][38] -> [DMESG-WARN][39] ([i915#1982]) +2 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl1/igt@kms_vblank@pipe-b-wait-forked-busy.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-kbl1/igt@kms_vblank@pipe-b-wait-forked-busy.html
* igt@perf@oa-exponents:
- shard-apl: [PASS][40] -> [SKIP][41] ([fdo#109271] / [i915#1354] / [i915#1635]) +1 similar issue
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl7/igt@perf@oa-exponents.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl3/igt@perf@oa-exponents.html
* igt@perf@rc6-disable:
- shard-hsw: [PASS][42] -> [SKIP][43] ([fdo#109271]) +1 similar issue
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw2/igt@perf@rc6-disable.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw4/igt@perf@rc6-disable.html
- shard-kbl: [PASS][44] -> [SKIP][45] ([fdo#109271] / [i915#1354]) +1 similar issue
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl7/igt@perf@rc6-disable.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-kbl4/igt@perf@rc6-disable.html
* igt@perf_pmu@busy-idle-no-semaphores@rcs0:
- shard-hsw: [PASS][46] -> [FAIL][47] ([i915#2614])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw4/igt@perf_pmu@busy-idle-no-semaphores@rcs0.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw4/igt@perf_pmu@busy-idle-no-semaphores@rcs0.html
#### Possible fixes ####
* igt@gem_exec_create@basic:
- shard-snb: [INCOMPLETE][48] ([i915#82]) -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-snb2/igt@gem_exec_create@basic.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-snb4/igt@gem_exec_create@basic.html
* igt@gem_exec_gttfill@all:
- shard-glk: [DMESG-WARN][50] ([i915#118] / [i915#95]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk5/igt@gem_exec_gttfill@all.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-glk7/igt@gem_exec_gttfill@all.html
* {igt@kms_async_flips@async-flip-with-page-flip-events}:
- shard-kbl: [FAIL][52] ([i915#2521]) -> [PASS][53]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl1/igt@kms_async_flips@async-flip-with-page-flip-events.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-kbl1/igt@kms_async_flips@async-flip-with-page-flip-events.html
* igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@edp-1-pipe-a:
- shard-skl: [DMESG-WARN][54] ([i915#1982]) -> [PASS][55] +5 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl7/igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@edp-1-pipe-a.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl2/igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@edp-1-pipe-a.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-0:
- shard-kbl: [DMESG-WARN][56] ([i915#1982]) -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl1/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-kbl1/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
* igt@kms_cursor_crc@pipe-c-cursor-alpha-transparent:
- shard-skl: [FAIL][58] ([i915#54]) -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl2/igt@kms_cursor_crc@pipe-c-cursor-alpha-transparent.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl2/igt@kms_cursor_crc@pipe-c-cursor-alpha-transparent.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: [INCOMPLETE][60] ([i915#1635]) -> [PASS][61] +1 similar issue
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_edge_walk@pipe-c-256x256-left-edge:
- shard-glk: [DMESG-WARN][62] ([i915#1982]) -> [PASS][63] +4 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk4/igt@kms_cursor_edge_walk@pipe-c-256x256-left-edge.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-glk7/igt@kms_cursor_edge_walk@pipe-c-256x256-left-edge.html
* igt@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled:
- shard-hsw: [DMESG-WARN][64] ([i915#1982]) -> [PASS][65]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw6/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw2/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt:
- shard-skl: [INCOMPLETE][66] ([i915#123]) -> [PASS][67] +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt:
- shard-skl: [INCOMPLETE][68] ([i915#123] / [i915#2606]) -> [PASS][69]
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- shard-skl: [SKIP][70] ([fdo#109271]) -> [PASS][71] +7 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl1/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl6/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-kbl: [DMESG-WARN][72] ([i915#165] / [i915#78]) -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl2/igt@kms_plane_lowres@pipe-a-tiling-x.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-kbl2/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_vblank@pipe-c-wait-forked-busy:
- shard-apl: [DMESG-WARN][74] ([i915#1635] / [i915#1982]) -> [PASS][75] +3 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl1/igt@kms_vblank@pipe-c-wait-forked-busy.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl8/igt@kms_vblank@pipe-c-wait-forked-busy.html
#### Warnings ####
* igt@core_hotunplug@hotrebind-lateclose:
- shard-hsw: [FAIL][76] -> [WARN][77] ([i915#2283])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw4/igt@core_hotunplug@hotrebind-lateclose.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw1/igt@core_hotunplug@hotrebind-lateclose.html
* igt@kms_flip_tiling@flip-y-tiled:
- shard-skl: [DMESG-WARN][78] ([i915#1982]) -> [FAIL][79] ([i915#699])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl8/igt@kms_flip_tiling@flip-y-tiled.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl1/igt@kms_flip_tiling@flip-y-tiled.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc:
- shard-skl: [INCOMPLETE][80] ([i915#123] / [i915#2606]) -> [DMESG-WARN][81] ([i915#1982])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-modesetfrombusy:
- shard-skl: [SKIP][82] ([fdo#109271]) -> [INCOMPLETE][83] ([i915#123] / [i915#2606])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl1/igt@kms_frontbuffer_tracking@psr-modesetfrombusy.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl10/igt@kms_frontbuffer_tracking@psr-modesetfrombusy.html
* igt@runner@aborted:
- shard-apl: ([FAIL][84], [FAIL][85]) ([i915#1611] / [i915#1635] / [i915#1814]) -> [FAIL][86] ([fdo#109271] / [i915#1635] / [i915#1814])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl7/igt@runner@aborted.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl1/igt@runner@aborted.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl4/igt@runner@aborted.html
- shard-tglb: ([FAIL][87], [FAIL][88], [FAIL][89], [FAIL][90], [FAIL][91], [FAIL][92], [FAIL][93], [FAIL][94], [FAIL][95], [FAIL][96], [FAIL][97], [FAIL][98], [FAIL][99], [FAIL][100], [FAIL][101], [FAIL][102], [FAIL][103], [FAIL][104], [FAIL][105], [FAIL][106], [FAIL][107], [FAIL][108], [FAIL][109], [FAIL][110], [FAIL][111]) ([i915#1764] / [i915#1814] / [i915#456] / [k.org#205379]) -> ([FAIL][112], [FAIL][113], [FAIL][114], [FAIL][115], [FAIL][116], [FAIL][117], [FAIL][118], [FAIL][119], [FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124], [FAIL][125], [FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136]) ([i915#1602] / [i915#1764] / [i915#1814] / [i915#456] / [k.org#205379])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@runner@aborted.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@runner@aborted.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb8/igt@runner@aborted.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb8/igt@runner@aborted.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@runner@aborted.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb7/igt@runner@aborted.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb8/igt@runner@aborted.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb7/igt@runner@aborted.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb7/igt@runner@aborted.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb1/igt@runner@aborted.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb7/igt@runner@aborted.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb8/igt@runner@aborted.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb8/igt@runner@aborted.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb2/igt@runner@aborted.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb2/igt@runner@aborted.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb8/igt@runner@aborted.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb8/igt@runner@aborted.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb5/igt@runner@aborted.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb1/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb3/igt@runner@aborted.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb6/igt@runner@aborted.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb2/igt@runner@aborted.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb7/igt@runner@aborted.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb5/igt@runner@aborted.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb7/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb1/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb6/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb2/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb3/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb5/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb6/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb1/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb5/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb6/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123
[i915#1354]: https://gitlab.freedesktop.org/drm/intel/issues/1354
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#1611]: https://gitlab.freedesktop.org/drm/intel/issues/1611
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#1764]: https://gitlab.freedesktop.org/drm/intel/issues/1764
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283
[i915#2370]: https://gitlab.freedesktop.org/drm/intel/issues/2370
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
[i915#2606]: https://gitlab.freedesktop.org/drm/intel/issues/2606
[i915#2614]: https://gitlab.freedesktop.org/drm/intel/issues/2614
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#699]: https://gitlab.freedesktop.org/drm/intel/issues/699
[i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* IGT: IGT_5827 -> IGTPW_5090
* Linux: CI_DRM_9206 -> Patchwork_18788
CI-20190529: 20190529
CI_DRM_9206: 85ce674ff932ed7ca41aef52d8bb42c04fbe2171 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_5090: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5090/index.html
IGT_5827: 7fd7e3fb8b42eb4e62a4575f6edc5a048e5bec3d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18788: d046e7f1a967ed742d1fdecb23c6eb56cddcc95f @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/index.html
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread* Re: [Intel-gfx] ✓ Fi.CI.IGT: success for HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev2)
2020-10-29 17:54 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
@ 2020-11-02 9:02 ` Anshuman Gupta
0 siblings, 0 replies; 111+ messages in thread
From: Anshuman Gupta @ 2020-11-02 9:02 UTC (permalink / raw)
To: intel-gfx
Hi Ram ,
Below series is reviewed by Uma and CI results are green.
New HDCP MST test are skipping since there is no HDCP and DP-MST coverage in CI.
But it have tested the new IGT test locally.
Could you please take a look at this in order to merge the series.
There is a typo require to fix in patch [v4,15/16] commit log, i will send
a patch for this.
"drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks
-:13: WARNING:TYPO_SPELLING: 'chnages' may be misspelled - perhaps 'changes'?"
Thanks,
Anshuman Gupta.
On 2020-10-29 at 17:54:44 +0000, Patchwork wrote:
> == Series Details ==
>
> Series: HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev2)
> URL : https://patchwork.freedesktop.org/series/82998/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_9206_full -> Patchwork_18788_full
> ====================================================
>
> Summary
> -------
>
> **SUCCESS**
>
> No regressions found.
>
>
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_18788_full:
>
> ### IGT changes ###
>
> #### Suppressed ####
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * {igt@gem_exec_parallel@engines@userptr}:
> - shard-hsw: [PASS][1] -> [FAIL][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw6/igt@gem_exec_parallel@engines@userptr.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw4/igt@gem_exec_parallel@engines@userptr.html
>
>
>
> ### Piglit changes ###
>
> #### Possible regressions ####
>
> * spec@glsl-4.00@execution@built-in-functions@gs-op-mult-dmat3-dmat3 (NEW):
> - {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][3] +2 similar issues
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/pig-icl-1065g7/spec@glsl-4.00@execution@built-in-functions@gs-op-mult-dmat3-dmat3.html
>
>
> New tests
> ---------
>
> New tests have been introduced between CI_DRM_9206_full and Patchwork_18788_full:
>
> ### New CI tests (1) ###
>
> * boot:
> - Statuses : 200 pass(s)
> - Exec time: [0.0] s
>
>
>
>
> ### New IGT tests (4) ###
>
> * igt@kms_content_protection@dp-mst-lic-type-0:
> - Statuses : 5 skip(s)
> - Exec time: [0.0] s
>
> * igt@kms_content_protection@dp-mst-lic-type-1:
> - Statuses : 5 skip(s)
> - Exec time: [0.0] s
>
> * igt@kms_content_protection@dp-mst-type-0:
> - Statuses : 6 skip(s)
> - Exec time: [0.0, 0.00] s
>
> * igt@kms_content_protection@dp-mst-type-1:
> - Statuses : 5 skip(s)
> - Exec time: [0.0] s
>
>
>
>
> ### New Piglit tests (3) ###
>
> * spec@glsl-4.00@execution@built-in-functions@fs-op-mult-dmat4-dmat2x4:
> - Statuses : 1 incomplete(s)
> - Exec time: [0.0] s
>
> * spec@glsl-4.00@execution@built-in-functions@gs-op-mult-dmat3-dmat3:
> - Statuses : 1 incomplete(s)
> - Exec time: [0.0] s
>
> * spec@glsl-4.00@execution@built-in-functions@gs-op-mult-dmat4x3-double:
> - Statuses : 1 incomplete(s)
> - Exec time: [0.0] s
>
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_18788_full that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@drm_read@empty-nonblock:
> - shard-glk: [PASS][4] -> [DMESG-WARN][5] ([i915#1982]) +2 similar issues
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk7/igt@drm_read@empty-nonblock.html
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-glk5/igt@drm_read@empty-nonblock.html
>
> * igt@gem_exec_parallel@engines@contexts:
> - shard-snb: [PASS][6] -> [INCOMPLETE][7] ([i915#82])
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-snb5/igt@gem_exec_parallel@engines@contexts.html
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-snb4/igt@gem_exec_parallel@engines@contexts.html
>
> * igt@gem_userptr_blits@unsync-unmap-cycles:
> - shard-hsw: [PASS][8] -> [FAIL][9] ([i915#1888])
> [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw1/igt@gem_userptr_blits@unsync-unmap-cycles.html
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw4/igt@gem_userptr_blits@unsync-unmap-cycles.html
>
> * igt@i915_selftest@live@evict:
> - shard-skl: [PASS][10] -> [INCOMPLETE][11] ([i915#198])
> [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl9/igt@i915_selftest@live@evict.html
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl3/igt@i915_selftest@live@evict.html
>
> * igt@kms_big_fb@linear-32bpp-rotate-180:
> - shard-glk: [PASS][12] -> [INCOMPLETE][13] ([i915#1888])
> [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk8/igt@kms_big_fb@linear-32bpp-rotate-180.html
> [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-glk2/igt@kms_big_fb@linear-32bpp-rotate-180.html
>
> * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
> - shard-skl: [PASS][14] -> [DMESG-WARN][15] ([i915#1982]) +6 similar issues
> [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
> [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
>
> * igt@kms_cursor_legacy@cursor-vs-flip-toggle:
> - shard-hsw: [PASS][16] -> [FAIL][17] ([i915#2370])
> [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw1/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
> [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
>
> * igt@kms_draw_crc@draw-method-rgb565-blt-xtiled:
> - shard-snb: [PASS][18] -> [SKIP][19] ([fdo#109271]) +2 similar issues
> [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-snb2/igt@kms_draw_crc@draw-method-rgb565-blt-xtiled.html
> [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-snb4/igt@kms_draw_crc@draw-method-rgb565-blt-xtiled.html
>
> * igt@kms_draw_crc@draw-method-rgb565-render-ytiled:
> - shard-apl: [PASS][20] -> [DMESG-WARN][21] ([i915#1635] / [i915#1982]) +2 similar issues
> [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl8/igt@kms_draw_crc@draw-method-rgb565-render-ytiled.html
> [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl6/igt@kms_draw_crc@draw-method-rgb565-render-ytiled.html
>
> * igt@kms_flip@2x-plain-flip-ts-check@ab-vga1-hdmi-a1:
> - shard-hsw: [PASS][22] -> [DMESG-WARN][23] ([i915#1982]) +3 similar issues
> [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw2/igt@kms_flip@2x-plain-flip-ts-check@ab-vga1-hdmi-a1.html
> [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw6/igt@kms_flip@2x-plain-flip-ts-check@ab-vga1-hdmi-a1.html
>
> * igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc:
> - shard-snb: [PASS][24] -> [FAIL][25] ([i915#2546])
> [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-snb6/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc.html
> [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-snb7/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc.html
>
> * igt@kms_frontbuffer_tracking@fbc-suspend:
> - shard-apl: [PASS][26] -> [INCOMPLETE][27] ([i915#1635] / [i915#2606])
> [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
> [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
>
> * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-gtt:
> - shard-skl: [PASS][28] -> [DMESG-WARN][29] ([i915#2606])
> [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
> [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
>
> * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite:
> - shard-skl: [PASS][30] -> [INCOMPLETE][31] ([i915#123]) +3 similar issues
> [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
> [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
>
> * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff:
> - shard-skl: [PASS][32] -> [INCOMPLETE][33] ([i915#123] / [i915#2606])
> [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff.html
> [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff.html
>
> * igt@kms_psr@cursor_mmap_gtt:
> - shard-skl: [PASS][34] -> [INCOMPLETE][35] ([i915#2606])
> [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl4/igt@kms_psr@cursor_mmap_gtt.html
> [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl7/igt@kms_psr@cursor_mmap_gtt.html
>
> * igt@kms_setmode@basic:
> - shard-apl: [PASS][36] -> [FAIL][37] ([i915#1635] / [i915#31])
> [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl3/igt@kms_setmode@basic.html
> [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl3/igt@kms_setmode@basic.html
>
> * igt@kms_vblank@pipe-b-wait-forked-busy:
> - shard-kbl: [PASS][38] -> [DMESG-WARN][39] ([i915#1982]) +2 similar issues
> [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl1/igt@kms_vblank@pipe-b-wait-forked-busy.html
> [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-kbl1/igt@kms_vblank@pipe-b-wait-forked-busy.html
>
> * igt@perf@oa-exponents:
> - shard-apl: [PASS][40] -> [SKIP][41] ([fdo#109271] / [i915#1354] / [i915#1635]) +1 similar issue
> [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl7/igt@perf@oa-exponents.html
> [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl3/igt@perf@oa-exponents.html
>
> * igt@perf@rc6-disable:
> - shard-hsw: [PASS][42] -> [SKIP][43] ([fdo#109271]) +1 similar issue
> [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw2/igt@perf@rc6-disable.html
> [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw4/igt@perf@rc6-disable.html
> - shard-kbl: [PASS][44] -> [SKIP][45] ([fdo#109271] / [i915#1354]) +1 similar issue
> [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl7/igt@perf@rc6-disable.html
> [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-kbl4/igt@perf@rc6-disable.html
>
> * igt@perf_pmu@busy-idle-no-semaphores@rcs0:
> - shard-hsw: [PASS][46] -> [FAIL][47] ([i915#2614])
> [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw4/igt@perf_pmu@busy-idle-no-semaphores@rcs0.html
> [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw4/igt@perf_pmu@busy-idle-no-semaphores@rcs0.html
>
>
> #### Possible fixes ####
>
> * igt@gem_exec_create@basic:
> - shard-snb: [INCOMPLETE][48] ([i915#82]) -> [PASS][49]
> [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-snb2/igt@gem_exec_create@basic.html
> [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-snb4/igt@gem_exec_create@basic.html
>
> * igt@gem_exec_gttfill@all:
> - shard-glk: [DMESG-WARN][50] ([i915#118] / [i915#95]) -> [PASS][51]
> [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk5/igt@gem_exec_gttfill@all.html
> [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-glk7/igt@gem_exec_gttfill@all.html
>
> * {igt@kms_async_flips@async-flip-with-page-flip-events}:
> - shard-kbl: [FAIL][52] ([i915#2521]) -> [PASS][53]
> [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl1/igt@kms_async_flips@async-flip-with-page-flip-events.html
> [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-kbl1/igt@kms_async_flips@async-flip-with-page-flip-events.html
>
> * igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@edp-1-pipe-a:
> - shard-skl: [DMESG-WARN][54] ([i915#1982]) -> [PASS][55] +5 similar issues
> [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl7/igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@edp-1-pipe-a.html
> [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl2/igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@edp-1-pipe-a.html
>
> * igt@kms_big_fb@x-tiled-8bpp-rotate-0:
> - shard-kbl: [DMESG-WARN][56] ([i915#1982]) -> [PASS][57]
> [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl1/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
> [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-kbl1/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
>
> * igt@kms_cursor_crc@pipe-c-cursor-alpha-transparent:
> - shard-skl: [FAIL][58] ([i915#54]) -> [PASS][59]
> [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl2/igt@kms_cursor_crc@pipe-c-cursor-alpha-transparent.html
> [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl2/igt@kms_cursor_crc@pipe-c-cursor-alpha-transparent.html
>
> * igt@kms_cursor_crc@pipe-c-cursor-suspend:
> - shard-apl: [INCOMPLETE][60] ([i915#1635]) -> [PASS][61] +1 similar issue
> [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
> [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
>
> * igt@kms_cursor_edge_walk@pipe-c-256x256-left-edge:
> - shard-glk: [DMESG-WARN][62] ([i915#1982]) -> [PASS][63] +4 similar issues
> [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk4/igt@kms_cursor_edge_walk@pipe-c-256x256-left-edge.html
> [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-glk7/igt@kms_cursor_edge_walk@pipe-c-256x256-left-edge.html
>
> * igt@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled:
> - shard-hsw: [DMESG-WARN][64] ([i915#1982]) -> [PASS][65]
> [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw6/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled.html
> [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw2/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled.html
>
> * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt:
> - shard-skl: [INCOMPLETE][66] ([i915#123]) -> [PASS][67] +1 similar issue
> [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
> [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
>
> * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt:
> - shard-skl: [INCOMPLETE][68] ([i915#123] / [i915#2606]) -> [PASS][69]
> [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
> [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
>
> * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
> - shard-skl: [SKIP][70] ([fdo#109271]) -> [PASS][71] +7 similar issues
> [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl1/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
> [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl6/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
>
> * igt@kms_plane_lowres@pipe-a-tiling-x:
> - shard-kbl: [DMESG-WARN][72] ([i915#165] / [i915#78]) -> [PASS][73]
> [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl2/igt@kms_plane_lowres@pipe-a-tiling-x.html
> [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-kbl2/igt@kms_plane_lowres@pipe-a-tiling-x.html
>
> * igt@kms_vblank@pipe-c-wait-forked-busy:
> - shard-apl: [DMESG-WARN][74] ([i915#1635] / [i915#1982]) -> [PASS][75] +3 similar issues
> [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl1/igt@kms_vblank@pipe-c-wait-forked-busy.html
> [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl8/igt@kms_vblank@pipe-c-wait-forked-busy.html
>
>
> #### Warnings ####
>
> * igt@core_hotunplug@hotrebind-lateclose:
> - shard-hsw: [FAIL][76] -> [WARN][77] ([i915#2283])
> [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw4/igt@core_hotunplug@hotrebind-lateclose.html
> [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw1/igt@core_hotunplug@hotrebind-lateclose.html
>
> * igt@kms_flip_tiling@flip-y-tiled:
> - shard-skl: [DMESG-WARN][78] ([i915#1982]) -> [FAIL][79] ([i915#699])
> [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl8/igt@kms_flip_tiling@flip-y-tiled.html
> [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl1/igt@kms_flip_tiling@flip-y-tiled.html
>
> * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc:
> - shard-skl: [INCOMPLETE][80] ([i915#123] / [i915#2606]) -> [DMESG-WARN][81] ([i915#1982])
> [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc.html
> [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc.html
>
> * igt@kms_frontbuffer_tracking@psr-modesetfrombusy:
> - shard-skl: [SKIP][82] ([fdo#109271]) -> [INCOMPLETE][83] ([i915#123] / [i915#2606])
> [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl1/igt@kms_frontbuffer_tracking@psr-modesetfrombusy.html
> [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl10/igt@kms_frontbuffer_tracking@psr-modesetfrombusy.html
>
> * igt@runner@aborted:
> - shard-apl: ([FAIL][84], [FAIL][85]) ([i915#1611] / [i915#1635] / [i915#1814]) -> [FAIL][86] ([fdo#109271] / [i915#1635] / [i915#1814])
> [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl7/igt@runner@aborted.html
> [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl1/igt@runner@aborted.html
> [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-apl4/igt@runner@aborted.html
> - shard-tglb: ([FAIL][87], [FAIL][88], [FAIL][89], [FAIL][90], [FAIL][91], [FAIL][92], [FAIL][93], [FAIL][94], [FAIL][95], [FAIL][96], [FAIL][97], [FAIL][98], [FAIL][99], [FAIL][100], [FAIL][101], [FAIL][102], [FAIL][103], [FAIL][104], [FAIL][105], [FAIL][106], [FAIL][107], [FAIL][108], [FAIL][109], [FAIL][110], [FAIL][111]) ([i915#1764] / [i915#1814] / [i915#456] / [k.org#205379]) -> ([FAIL][112], [FAIL][113], [FAIL][114], [FAIL][115], [FAIL][116], [FAIL][117], [FAIL][118], [FAIL][119], [FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124], [FAIL][125], [FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136]) ([i915#1602] / [i915#1764] / [i915#1814] / [i915#456] / [k.org#205379])
> [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
> [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
> [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
> [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@runner@aborted.html
> [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
> [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@runner@aborted.html
> [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
> [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
> [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb8/igt@runner@aborted.html
> [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb8/igt@runner@aborted.html
> [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
> [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
> [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
> [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@runner@aborted.html
> [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb7/igt@runner@aborted.html
> [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
> [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
> [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
> [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb8/igt@runner@aborted.html
> [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
> [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
> [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb7/igt@runner@aborted.html
> [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb7/igt@runner@aborted.html
> [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
> [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
> [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb1/igt@runner@aborted.html
> [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb7/igt@runner@aborted.html
> [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb8/igt@runner@aborted.html
> [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb8/igt@runner@aborted.html
> [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb2/igt@runner@aborted.html
> [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb2/igt@runner@aborted.html
> [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb8/igt@runner@aborted.html
> [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb8/igt@runner@aborted.html
> [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb5/igt@runner@aborted.html
> [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb1/igt@runner@aborted.html
> [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb3/igt@runner@aborted.html
> [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb6/igt@runner@aborted.html
> [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb2/igt@runner@aborted.html
> [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb7/igt@runner@aborted.html
> [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb5/igt@runner@aborted.html
> [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb7/igt@runner@aborted.html
> [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb1/igt@runner@aborted.html
> [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb6/igt@runner@aborted.html
> [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb2/igt@runner@aborted.html
> [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb3/igt@runner@aborted.html
> [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb5/igt@runner@aborted.html
> [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb6/igt@runner@aborted.html
> [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb1/igt@runner@aborted.html
> [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb5/igt@runner@aborted.html
> [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb6/igt@runner@aborted.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
> [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
> [i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123
> [i915#1354]: https://gitlab.freedesktop.org/drm/intel/issues/1354
> [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
> [i915#1611]: https://gitlab.freedesktop.org/drm/intel/issues/1611
> [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
> [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
> [i915#1764]: https://gitlab.freedesktop.org/drm/intel/issues/1764
> [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
> [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
> [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
> [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
> [i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283
> [i915#2370]: https://gitlab.freedesktop.org/drm/intel/issues/2370
> [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
> [i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
> [i915#2606]: https://gitlab.freedesktop.org/drm/intel/issues/2606
> [i915#2614]: https://gitlab.freedesktop.org/drm/intel/issues/2614
> [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
> [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
> [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
> [i915#699]: https://gitlab.freedesktop.org/drm/intel/issues/699
> [i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78
> [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
> [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
> [k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
>
>
> Participating hosts (11 -> 11)
> ------------------------------
>
> No changes in participating hosts
>
>
> Build changes
> -------------
>
> * IGT: IGT_5827 -> IGTPW_5090
> * Linux: CI_DRM_9206 -> Patchwork_18788
>
> CI-20190529: 20190529
> CI_DRM_9206: 85ce674ff932ed7ca41aef52d8bb42c04fbe2171 @ git://anongit.freedesktop.org/gfx-ci/linux
> IGTPW_5090: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5090/index.html
> IGT_5827: 7fd7e3fb8b42eb4e62a4575f6edc5a048e5bec3d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_18788: d046e7f1a967ed742d1fdecb23c6eb56cddcc95f @ git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 111+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev3)
2020-10-27 16:41 ` [Intel-gfx] " Anshuman Gupta
` (22 preceding siblings ...)
(?)
@ 2020-11-03 7:05 ` Patchwork
-1 siblings, 0 replies; 111+ messages in thread
From: Patchwork @ 2020-11-03 7:05 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
== Series Details ==
Series: HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev3)
URL : https://patchwork.freedesktop.org/series/82998/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: expected unsigned int [usertype] *s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216
+./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:864:16: warning: trying to copy expression type 31
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
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