* [Intel-gfx] [PATCH 01/21] drm/i915/dg1: Enable ports
2020-11-17 18:50 [Intel-gfx] [PATCH 00/21] Introduce Alderlake-S Aditya Swarup
@ 2020-11-17 18:50 ` Aditya Swarup
2020-11-17 18:50 ` [Intel-gfx] [PATCH 02/21] drm/i915/tgl: Fix macros for TGL SOC based WA Aditya Swarup
` (24 subsequent siblings)
25 siblings, 0 replies; 56+ messages in thread
From: Aditya Swarup @ 2020-11-17 18:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
For DG1 we have a little of mix up wrt to DDI/port names and indexes.
Bspec refers to the ports as DDIA, DDIB, DDI USBC1 and DDI USBC2
(besides the DDIA, DDIB, DDIC, DDID), but the previous naming is the
most unambiguous one. This means that for any register on Display Engine
we should use the index of A, B, D and E. However in some places this is
not true:
- VBT: uses C and D and have to be mapped to D/E
- IO/Combo: uses C and D, but we already differentiate those when
we created the phy vs port distinction.
This additional mapping for VBT and phy are already covered in previous
patches, so now we can initialize all the DDIs as A, B, D and E.
v2: Squash previous patch enabling just ports A and B since most of the
pumbling code is already merged now
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index bc532711470b..e8874cd22abf 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7343,7 +7343,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
{
if (phy == PHY_NONE)
return false;
- else if (IS_ROCKETLAKE(dev_priv))
+ else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
return phy <= PHY_D;
else if (IS_JSL_EHL(dev_priv))
return phy <= PHY_C;
@@ -7355,7 +7355,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
{
- if (IS_ROCKETLAKE(dev_priv))
+ if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
return false;
else if (INTEL_GEN(dev_priv) >= 12)
return phy >= PHY_D && phy <= PHY_I;
@@ -7367,7 +7367,7 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
{
- if (IS_ROCKETLAKE(i915) && port >= PORT_TC1)
+ if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
return PHY_C + port - PORT_TC1;
else if (IS_JSL_EHL(i915) && port == PORT_D)
return PHY_A;
@@ -17240,7 +17240,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- if (IS_ROCKETLAKE(dev_priv)) {
+ if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_TC1);
--
2.27.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* [Intel-gfx] [PATCH 02/21] drm/i915/tgl: Fix macros for TGL SOC based WA
2020-11-17 18:50 [Intel-gfx] [PATCH 00/21] Introduce Alderlake-S Aditya Swarup
2020-11-17 18:50 ` [Intel-gfx] [PATCH 01/21] drm/i915/dg1: Enable ports Aditya Swarup
@ 2020-11-17 18:50 ` Aditya Swarup
2020-11-17 19:03 ` Souza, Jose
2020-11-17 19:31 ` Lucas De Marchi
2020-11-17 18:50 ` [Intel-gfx] [PATCH 03/21] drm/i915/adl_s: Add ADL-S platform info and PCI ids Aditya Swarup
` (23 subsequent siblings)
25 siblings, 2 replies; 56+ messages in thread
From: Aditya Swarup @ 2020-11-17 18:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi
Fix macros for applying TGL SOC WAs by using INTEL_REVID()
as index to fetch correct revision offset in TGL GT/DISP stepping
table.
Also, remove redundant macros and simplify it to use GT and DISP
macros for getting applicable stepping for TGL.
Fixes: ("drm/i915/tgl: Fix stepping WA matching")
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
.../drm/i915/display/intel_display_power.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
drivers/gpu/drm/i915/display/intel_sprite.c | 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 ++++++++--------
drivers/gpu/drm/i915/i915_drv.h | 24 +++++++------------
drivers/gpu/drm/i915/intel_pm.c | 2 +-
6 files changed, 24 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index fe2d90bba536..06c036e2092c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5283,7 +5283,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
int config, i;
if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
- IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
+ IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_B0))
/* Wa_1409767108:tgl,dg1 */
table = wa_1409767108_buddy_page_masks;
else
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index b3631b722de3..c057a03b2ed4 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -550,7 +550,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
if (dev_priv->psr.psr2_sel_fetch_enabled) {
/* WA 1408330847 */
- if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
+ if (IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_A0) ||
IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
DIS_RAM_BYPASS_PSR2_MAN_TRACK,
@@ -1102,7 +1102,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
/* WA 1408330847 */
if (dev_priv->psr.psr2_sel_fetch_enabled &&
- (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
+ (IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_A0) ||
IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index a3ab44694118..f7da4a56054e 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -3022,7 +3022,7 @@ static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
{
/* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
- IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
+ IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_C0))
return false;
return plane_id < PLANE_SPRITE4;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index a82554baa6ac..d756155d82ea 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -71,16 +71,16 @@ const struct i915_rev_steppings kbl_revids[] = {
};
const struct i915_rev_steppings tgl_uy_revids[] = {
- [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_A0 },
- [1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_C0 },
- [2] = { .gt_stepping = TGL_REVID_B1, .disp_stepping = TGL_REVID_C0 },
- [3] = { .gt_stepping = TGL_REVID_C0, .disp_stepping = TGL_REVID_D0 },
+ [0] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_A0 },
+ [1] = { .gt_stepping = REVID_B0, .disp_stepping = REVID_C0 },
+ [2] = { .gt_stepping = REVID_B1, .disp_stepping = REVID_C0 },
+ [3] = { .gt_stepping = REVID_C0, .disp_stepping = REVID_D0 },
};
/* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */
const struct i915_rev_steppings tgl_revids[] = {
- [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_B0 },
- [1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_D0 },
+ [0] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_B0 },
+ [1] = { .gt_stepping = REVID_B0, .disp_stepping = REVID_D0 },
};
static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
@@ -1250,13 +1250,13 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
gen12_gt_workarounds_init(i915, wal);
/* Wa_1409420604:tgl */
- if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
+ if (IS_TGL_GT_REVID(i915, REVID_A0, REVID_A0))
wa_write_or(wal,
SUBSLICE_UNIT_LEVEL_CLKGATE2,
CPSSUNIT_CLKGATE_DIS);
/* Wa_1607087056:tgl also know as BUG:1409180338 */
- if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
+ if (IS_TGL_GT_REVID(i915, REVID_A0, REVID_A0))
wa_write_or(wal,
SLICE_UNIT_LEVEL_CLKGATE,
L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
@@ -1734,7 +1734,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
struct drm_i915_private *i915 = engine->i915;
if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
- IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
+ IS_TGL_GT_REVID(i915, REVID_A0, REVID_A0)) {
/*
* Wa_1607138336:tgl[a0],dg1[a0]
* Wa_1607063988:tgl[a0],dg1[a0]
@@ -1744,7 +1744,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
}
- if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
+ if (IS_TGL_GT_REVID(i915, REVID_A0, REVID_A0)) {
/*
* Wa_1606679103:tgl
* (see also Wa_1606682166:icl)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 15be8debae54..437916aacaa6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1565,11 +1565,11 @@ extern const struct i915_rev_steppings kbl_revids[];
(IS_JSL_EHL(p) && IS_REVID(p, since, until))
enum {
- TGL_REVID_A0,
- TGL_REVID_B0,
- TGL_REVID_B1,
- TGL_REVID_C0,
- TGL_REVID_D0,
+ REVID_A0,
+ REVID_B0,
+ REVID_B1,
+ REVID_C0,
+ REVID_D0,
};
extern const struct i915_rev_steppings tgl_uy_revids[];
@@ -1579,9 +1579,9 @@ static inline const struct i915_rev_steppings *
tgl_revids_get(struct drm_i915_private *dev_priv)
{
if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv))
- return tgl_uy_revids;
+ return tgl_uy_revids + INTEL_REVID(dev_priv);
else
- return tgl_revids;
+ return tgl_revids + INTEL_REVID(dev_priv);
}
#define IS_TGL_DISP_REVID(p, since, until) \
@@ -1589,16 +1589,10 @@ tgl_revids_get(struct drm_i915_private *dev_priv)
tgl_revids_get(p)->disp_stepping >= (since) && \
tgl_revids_get(p)->disp_stepping <= (until))
-#define IS_TGL_UY_GT_REVID(p, since, until) \
- ((IS_TGL_U(p) || IS_TGL_Y(p)) && \
- tgl_uy_revids->gt_stepping >= (since) && \
- tgl_uy_revids->gt_stepping <= (until))
-
#define IS_TGL_GT_REVID(p, since, until) \
(IS_TIGERLAKE(p) && \
- !(IS_TGL_U(p) || IS_TGL_Y(p)) && \
- tgl_revids->gt_stepping >= (since) && \
- tgl_revids->gt_stepping <= (until))
+ tgl_revids_get(p)->gt_stepping >= (since) && \
+ tgl_revids_get(p)->gt_stepping <= (until))
#define RKL_REVID_A0 0x0
#define RKL_REVID_B0 0x1
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a20b5051f18c..69840aa0d4db 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7110,7 +7110,7 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
/* Wa_1409825376:tgl (pre-prod)*/
- if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1))
+ if (IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_B1))
I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
TGL_VRH_GATING_DIS);
--
2.27.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH 02/21] drm/i915/tgl: Fix macros for TGL SOC based WA
2020-11-17 18:50 ` [Intel-gfx] [PATCH 02/21] drm/i915/tgl: Fix macros for TGL SOC based WA Aditya Swarup
@ 2020-11-17 19:03 ` Souza, Jose
2020-11-17 19:28 ` Lucas De Marchi
2020-11-17 19:31 ` Lucas De Marchi
1 sibling, 1 reply; 56+ messages in thread
From: Souza, Jose @ 2020-11-17 19:03 UTC (permalink / raw)
To: Swarup, Aditya, intel-gfx; +Cc: Nikula, Jani, De Marchi, Lucas
On Tue, 2020-11-17 at 10:50 -0800, Aditya Swarup wrote:
> Fix macros for applying TGL SOC WAs by using INTEL_REVID()
> as index to fetch correct revision offset in TGL GT/DISP stepping
> table.
Please explain what exactly is the issue you are fixing, the change you did in tgl_revids_get() + IS_TGL_GT_REVID looks a improvement but not a fix.
>
> Also, remove redundant macros and simplify it to use GT and DISP
> macros for getting applicable stepping for TGL.
>
> Fixes: ("drm/i915/tgl: Fix stepping WA matching")
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> ---
> .../drm/i915/display/intel_display_power.c | 2 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
> drivers/gpu/drm/i915/display/intel_sprite.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 ++++++++--------
> drivers/gpu/drm/i915/i915_drv.h | 24 +++++++------------
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> 6 files changed, 24 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index fe2d90bba536..06c036e2092c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5283,7 +5283,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
> int config, i;
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
> if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
> - IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
> + IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_B0))
> /* Wa_1409767108:tgl,dg1 */
> table = wa_1409767108_buddy_page_masks;
> else
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index b3631b722de3..c057a03b2ed4 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -550,7 +550,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
> if (dev_priv->psr.psr2_sel_fetch_enabled) {
> /* WA 1408330847 */
> - if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
> + if (IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_A0) ||
> IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
> intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> DIS_RAM_BYPASS_PSR2_MAN_TRACK,
> @@ -1102,7 +1102,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
> /* WA 1408330847 */
> if (dev_priv->psr.psr2_sel_fetch_enabled &&
> - (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
> + (IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_A0) ||
> IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
> intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index a3ab44694118..f7da4a56054e 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -3022,7 +3022,7 @@ static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
> {
> /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
> if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
> - IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
> + IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_C0))
> return false;
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
> return plane_id < PLANE_SPRITE4;
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index a82554baa6ac..d756155d82ea 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -71,16 +71,16 @@ const struct i915_rev_steppings kbl_revids[] = {
> };
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
> const struct i915_rev_steppings tgl_uy_revids[] = {
> - [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_A0 },
> - [1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_C0 },
> - [2] = { .gt_stepping = TGL_REVID_B1, .disp_stepping = TGL_REVID_C0 },
> - [3] = { .gt_stepping = TGL_REVID_C0, .disp_stepping = TGL_REVID_D0 },
> + [0] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_A0 },
> + [1] = { .gt_stepping = REVID_B0, .disp_stepping = REVID_C0 },
> + [2] = { .gt_stepping = REVID_B1, .disp_stepping = REVID_C0 },
> + [3] = { .gt_stepping = REVID_C0, .disp_stepping = REVID_D0 },
> };
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
> /* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */
> const struct i915_rev_steppings tgl_revids[] = {
> - [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_B0 },
> - [1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_D0 },
> + [0] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_B0 },
> + [1] = { .gt_stepping = REVID_B0, .disp_stepping = REVID_D0 },
> };
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
> static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
> @@ -1250,13 +1250,13 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> gen12_gt_workarounds_init(i915, wal);
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
> /* Wa_1409420604:tgl */
> - if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
> + if (IS_TGL_GT_REVID(i915, REVID_A0, REVID_A0))
> wa_write_or(wal,
> SUBSLICE_UNIT_LEVEL_CLKGATE2,
> CPSSUNIT_CLKGATE_DIS);
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
> /* Wa_1607087056:tgl also know as BUG:1409180338 */
> - if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
> + if (IS_TGL_GT_REVID(i915, REVID_A0, REVID_A0))
> wa_write_or(wal,
> SLICE_UNIT_LEVEL_CLKGATE,
> L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
> @@ -1734,7 +1734,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> struct drm_i915_private *i915 = engine->i915;
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
> if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
> - IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
> + IS_TGL_GT_REVID(i915, REVID_A0, REVID_A0)) {
> /*
> * Wa_1607138336:tgl[a0],dg1[a0]
> * Wa_1607063988:tgl[a0],dg1[a0]
> @@ -1744,7 +1744,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
> }
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
> - if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
> + if (IS_TGL_GT_REVID(i915, REVID_A0, REVID_A0)) {
> /*
> * Wa_1606679103:tgl
> * (see also Wa_1606682166:icl)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 15be8debae54..437916aacaa6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1565,11 +1565,11 @@ extern const struct i915_rev_steppings kbl_revids[];
> (IS_JSL_EHL(p) && IS_REVID(p, since, until))
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
> enum {
> - TGL_REVID_A0,
> - TGL_REVID_B0,
> - TGL_REVID_B1,
> - TGL_REVID_C0,
> - TGL_REVID_D0,
> + REVID_A0,
> + REVID_B0,
> + REVID_B1,
> + REVID_C0,
> + REVID_D0,
Better keep "TGL_" otherwise this could be used in other platforms that have different values for each revision.
> };
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
> extern const struct i915_rev_steppings tgl_uy_revids[];
> @@ -1579,9 +1579,9 @@ static inline const struct i915_rev_steppings *
> tgl_revids_get(struct drm_i915_private *dev_priv)
> {
> if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv))
> - return tgl_uy_revids;
> + return tgl_uy_revids + INTEL_REVID(dev_priv);
> else
> - return tgl_revids;
> + return tgl_revids + INTEL_REVID(dev_priv);
better do tgl_revids[INTEL_REVID(dev_priv)] with a array size check first.
> }
>
>
>
>
>
>
>
>
> #define IS_TGL_DISP_REVID(p, since, until) \
> @@ -1589,16 +1589,10 @@ tgl_revids_get(struct drm_i915_private *dev_priv)
> tgl_revids_get(p)->disp_stepping >= (since) && \
> tgl_revids_get(p)->disp_stepping <= (until))
>
>
>
>
>
>
>
>
> -#define IS_TGL_UY_GT_REVID(p, since, until) \
> - ((IS_TGL_U(p) || IS_TGL_Y(p)) && \
> - tgl_uy_revids->gt_stepping >= (since) && \
> - tgl_uy_revids->gt_stepping <= (until))
> -
> #define IS_TGL_GT_REVID(p, since, until) \
> (IS_TIGERLAKE(p) && \
> - !(IS_TGL_U(p) || IS_TGL_Y(p)) && \
> - tgl_revids->gt_stepping >= (since) && \
> - tgl_revids->gt_stepping <= (until))
> + tgl_revids_get(p)->gt_stepping >= (since) && \
> + tgl_revids_get(p)->gt_stepping <= (until))
>
>
>
>
>
>
>
>
> #define RKL_REVID_A0 0x0
> #define RKL_REVID_B0 0x1
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a20b5051f18c..69840aa0d4db 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7110,7 +7110,7 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
> ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
>
>
>
>
>
>
>
>
> /* Wa_1409825376:tgl (pre-prod)*/
> - if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1))
> + if (IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_B1))
> I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
> TGL_VRH_GATING_DIS);
>
>
>
>
>
>
>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH 02/21] drm/i915/tgl: Fix macros for TGL SOC based WA
2020-11-17 19:03 ` Souza, Jose
@ 2020-11-17 19:28 ` Lucas De Marchi
2020-11-17 19:33 ` Souza, Jose
0 siblings, 1 reply; 56+ messages in thread
From: Lucas De Marchi @ 2020-11-17 19:28 UTC (permalink / raw)
To: Souza, Jose; +Cc: Nikula, Jani, intel-gfx
On Tue, Nov 17, 2020 at 07:03:05PM +0000, Jose Souza wrote:
>On Tue, 2020-11-17 at 10:50 -0800, Aditya Swarup wrote:
>> Fix macros for applying TGL SOC WAs by using INTEL_REVID()
>> as index to fetch correct revision offset in TGL GT/DISP stepping
>> table.
>
>Please explain what exactly is the issue you are fixing, the change you did in tgl_revids_get() + IS_TGL_GT_REVID looks a improvement but not a fix.
otherwise it always gets the first entry from the table, regardless
what' s the revid we are running on... so it does look like a very
important fix.
>
>>
>> Also, remove redundant macros and simplify it to use GT and DISP
>> macros for getting applicable stepping for TGL.
As a fix, this should not be mixed with the noisy s/TGL_REVID/REVID/, as
it makes it much more difficult for backports and to review. Please
split it in another patch (I actually don' t see a reason to do it
actually... I'd rather try to move away from these tables if possible).
Lucas De Marchi
>>
>> Fixes: ("drm/i915/tgl: Fix stepping WA matching")
>> Cc: José Roberto de Souza <jose.souza@intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>> ---
>> .../drm/i915/display/intel_display_power.c | 2 +-
>> drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
>> drivers/gpu/drm/i915/display/intel_sprite.c | 2 +-
>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 ++++++++--------
>> drivers/gpu/drm/i915/i915_drv.h | 24 +++++++------------
>> drivers/gpu/drm/i915/intel_pm.c | 2 +-
>> 6 files changed, 24 insertions(+), 30 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index fe2d90bba536..06c036e2092c 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -5283,7 +5283,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
>> int config, i;
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>> if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
>> - IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
>> + IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_B0))
>> /* Wa_1409767108:tgl,dg1 */
>> table = wa_1409767108_buddy_page_masks;
>> else
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>> index b3631b722de3..c057a03b2ed4 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -550,7 +550,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>> if (dev_priv->psr.psr2_sel_fetch_enabled) {
>> /* WA 1408330847 */
>> - if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
>> + if (IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_A0) ||
>> IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
>> intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>> DIS_RAM_BYPASS_PSR2_MAN_TRACK,
>> @@ -1102,7 +1102,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>> /* WA 1408330847 */
>> if (dev_priv->psr.psr2_sel_fetch_enabled &&
>> - (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
>> + (IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_A0) ||
>> IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
>> intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>> DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
>> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
>> index a3ab44694118..f7da4a56054e 100644
>> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>> @@ -3022,7 +3022,7 @@ static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
>> {
>> /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
>> if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
>> - IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
>> + IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_C0))
>> return false;
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>> return plane_id < PLANE_SPRITE4;
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index a82554baa6ac..d756155d82ea 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -71,16 +71,16 @@ const struct i915_rev_steppings kbl_revids[] = {
>> };
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>> const struct i915_rev_steppings tgl_uy_revids[] = {
>> - [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_A0 },
>> - [1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_C0 },
>> - [2] = { .gt_stepping = TGL_REVID_B1, .disp_stepping = TGL_REVID_C0 },
>> - [3] = { .gt_stepping = TGL_REVID_C0, .disp_stepping = TGL_REVID_D0 },
>> + [0] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_A0 },
>> + [1] = { .gt_stepping = REVID_B0, .disp_stepping = REVID_C0 },
>> + [2] = { .gt_stepping = REVID_B1, .disp_stepping = REVID_C0 },
>> + [3] = { .gt_stepping = REVID_C0, .disp_stepping = REVID_D0 },
>> };
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>> /* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */
>> const struct i915_rev_steppings tgl_revids[] = {
>> - [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_B0 },
>> - [1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_D0 },
>> + [0] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_B0 },
>> + [1] = { .gt_stepping = REVID_B0, .disp_stepping = REVID_D0 },
>> };
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>> static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
>> @@ -1250,13 +1250,13 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>> gen12_gt_workarounds_init(i915, wal);
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>> /* Wa_1409420604:tgl */
>> - if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
>> + if (IS_TGL_GT_REVID(i915, REVID_A0, REVID_A0))
>> wa_write_or(wal,
>> SUBSLICE_UNIT_LEVEL_CLKGATE2,
>> CPSSUNIT_CLKGATE_DIS);
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>> /* Wa_1607087056:tgl also know as BUG:1409180338 */
>> - if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
>> + if (IS_TGL_GT_REVID(i915, REVID_A0, REVID_A0))
>> wa_write_or(wal,
>> SLICE_UNIT_LEVEL_CLKGATE,
>> L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
>> @@ -1734,7 +1734,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> struct drm_i915_private *i915 = engine->i915;
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>> if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
>> - IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
>> + IS_TGL_GT_REVID(i915, REVID_A0, REVID_A0)) {
>> /*
>> * Wa_1607138336:tgl[a0],dg1[a0]
>> * Wa_1607063988:tgl[a0],dg1[a0]
>> @@ -1744,7 +1744,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
>> }
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>> - if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
>> + if (IS_TGL_GT_REVID(i915, REVID_A0, REVID_A0)) {
>> /*
>> * Wa_1606679103:tgl
>> * (see also Wa_1606682166:icl)
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 15be8debae54..437916aacaa6 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1565,11 +1565,11 @@ extern const struct i915_rev_steppings kbl_revids[];
>> (IS_JSL_EHL(p) && IS_REVID(p, since, until))
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>> enum {
>> - TGL_REVID_A0,
>> - TGL_REVID_B0,
>> - TGL_REVID_B1,
>> - TGL_REVID_C0,
>> - TGL_REVID_D0,
>> + REVID_A0,
>> + REVID_B0,
>> + REVID_B1,
>> + REVID_C0,
>> + REVID_D0,
>
>Better keep "TGL_" otherwise this could be used in other platforms that have different values for each revision.
>
>> };
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>> extern const struct i915_rev_steppings tgl_uy_revids[];
>> @@ -1579,9 +1579,9 @@ static inline const struct i915_rev_steppings *
>> tgl_revids_get(struct drm_i915_private *dev_priv)
>> {
>> if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv))
>> - return tgl_uy_revids;
>> + return tgl_uy_revids + INTEL_REVID(dev_priv);
>> else
>> - return tgl_revids;
>> + return tgl_revids + INTEL_REVID(dev_priv);
>
>better do tgl_revids[INTEL_REVID(dev_priv)] with a array size check first.
>
>> }
>>
>>
>>
>>
>>
>>
>>
>>
>> #define IS_TGL_DISP_REVID(p, since, until) \
>> @@ -1589,16 +1589,10 @@ tgl_revids_get(struct drm_i915_private *dev_priv)
>> tgl_revids_get(p)->disp_stepping >= (since) && \
>> tgl_revids_get(p)->disp_stepping <= (until))
>>
>>
>>
>>
>>
>>
>>
>>
>> -#define IS_TGL_UY_GT_REVID(p, since, until) \
>> - ((IS_TGL_U(p) || IS_TGL_Y(p)) && \
>> - tgl_uy_revids->gt_stepping >= (since) && \
>> - tgl_uy_revids->gt_stepping <= (until))
>> -
>> #define IS_TGL_GT_REVID(p, since, until) \
>> (IS_TIGERLAKE(p) && \
>> - !(IS_TGL_U(p) || IS_TGL_Y(p)) && \
>> - tgl_revids->gt_stepping >= (since) && \
>> - tgl_revids->gt_stepping <= (until))
>> + tgl_revids_get(p)->gt_stepping >= (since) && \
>> + tgl_revids_get(p)->gt_stepping <= (until))
>>
>>
>>
>>
>>
>>
>>
>>
>> #define RKL_REVID_A0 0x0
>> #define RKL_REVID_B0 0x1
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index a20b5051f18c..69840aa0d4db 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -7110,7 +7110,7 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
>> ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
>>
>>
>>
>>
>>
>>
>>
>>
>> /* Wa_1409825376:tgl (pre-prod)*/
>> - if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1))
>> + if (IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_B1))
>> I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
>> TGL_VRH_GATING_DIS);
>>
>>
>>
>>
>>
>>
>>
>>
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH 02/21] drm/i915/tgl: Fix macros for TGL SOC based WA
2020-11-17 19:28 ` Lucas De Marchi
@ 2020-11-17 19:33 ` Souza, Jose
2020-11-18 7:56 ` Lucas De Marchi
0 siblings, 1 reply; 56+ messages in thread
From: Souza, Jose @ 2020-11-17 19:33 UTC (permalink / raw)
To: De Marchi, Lucas; +Cc: Nikula, Jani, intel-gfx
On Tue, 2020-11-17 at 11:28 -0800, Lucas De Marchi wrote:
> On Tue, Nov 17, 2020 at 07:03:05PM +0000, Jose Souza wrote:
> > On Tue, 2020-11-17 at 10:50 -0800, Aditya Swarup wrote:
> > > Fix macros for applying TGL SOC WAs by using INTEL_REVID()
> > > as index to fetch correct revision offset in TGL GT/DISP stepping
> > > table.
> >
> > Please explain what exactly is the issue you are fixing, the change you did in tgl_revids_get() + IS_TGL_GT_REVID looks a improvement but not a fix.
>
> otherwise it always gets the first entry from the table, regardless
> what' s the revid we are running on... so it does look like a very
> important fix.
Ooh okay, so the fix should only be
tgl_uy_revids/tgl_revids->gt_stepping[INTEL_REVID(dev_priv)]
Then the improvements in other patches.
>
> >
> > >
> > > Also, remove redundant macros and simplify it to use GT and DISP
> > > macros for getting applicable stepping for TGL.
>
> As a fix, this should not be mixed with the noisy s/TGL_REVID/REVID/, as
> it makes it much more difficult for backports and to review. Please
> split it in another patch (I actually don' t see a reason to do it
> actually... I'd rather try to move away from these tables if possible).
>
> Lucas De Marchi
>
> > >
> > > Fixes: ("drm/i915/tgl: Fix stepping WA matching")
> > > Cc: José Roberto de Souza <jose.souza@intel.com>
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > > Cc: Jani Nikula <jani.nikula@intel.com>
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> > > ---
> > > .../drm/i915/display/intel_display_power.c | 2 +-
> > > drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
> > > drivers/gpu/drm/i915/display/intel_sprite.c | 2 +-
> > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 ++++++++--------
> > > drivers/gpu/drm/i915/i915_drv.h | 24 +++++++------------
> > > drivers/gpu/drm/i915/intel_pm.c | 2 +-
> > > 6 files changed, 24 insertions(+), 30 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > index fe2d90bba536..06c036e2092c 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > @@ -5283,7 +5283,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
> > > int config, i;
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
> > > - IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
> > > + IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_B0))
> > > /* Wa_1409767108:tgl,dg1 */
> > > table = wa_1409767108_buddy_page_masks;
> > > else
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index b3631b722de3..c057a03b2ed4 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -550,7 +550,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > if (dev_priv->psr.psr2_sel_fetch_enabled) {
> > > /* WA 1408330847 */
> > > - if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
> > > + if (IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_A0) ||
> > > IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
> > > intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> > > DIS_RAM_BYPASS_PSR2_MAN_TRACK,
> > > @@ -1102,7 +1102,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > /* WA 1408330847 */
> > > if (dev_priv->psr.psr2_sel_fetch_enabled &&
> > > - (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
> > > + (IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_A0) ||
> > > IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
> > > intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> > > DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> > > index a3ab44694118..f7da4a56054e 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > > @@ -3022,7 +3022,7 @@ static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
> > > {
> > > /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
> > > if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
> > > - IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
> > > + IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_C0))
> > > return false;
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > return plane_id < PLANE_SPRITE4;
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > index a82554baa6ac..d756155d82ea 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > @@ -71,16 +71,16 @@ const struct i915_rev_steppings kbl_revids[] = {
> > > };
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > const struct i915_rev_steppings tgl_uy_revids[] = {
> > > - [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_A0 },
> > > - [1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_C0 },
> > > - [2] = { .gt_stepping = TGL_REVID_B1, .disp_stepping = TGL_REVID_C0 },
> > > - [3] = { .gt_stepping = TGL_REVID_C0, .disp_stepping = TGL_REVID_D0 },
> > > + [0] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_A0 },
> > > + [1] = { .gt_stepping = REVID_B0, .disp_stepping = REVID_C0 },
> > > + [2] = { .gt_stepping = REVID_B1, .disp_stepping = REVID_C0 },
> > > + [3] = { .gt_stepping = REVID_C0, .disp_stepping = REVID_D0 },
> > > };
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > /* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */
> > > const struct i915_rev_steppings tgl_revids[] = {
> > > - [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_B0 },
> > > - [1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_D0 },
> > > + [0] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_B0 },
> > > + [1] = { .gt_stepping = REVID_B0, .disp_stepping = REVID_D0 },
> > > };
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
> > > @@ -1250,13 +1250,13 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> > > gen12_gt_workarounds_init(i915, wal);
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > /* Wa_1409420604:tgl */
> > > - if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
> > > + if (IS_TGL_GT_REVID(i915, REVID_A0, REVID_A0))
> > > wa_write_or(wal,
> > > SUBSLICE_UNIT_LEVEL_CLKGATE2,
> > > CPSSUNIT_CLKGATE_DIS);
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > /* Wa_1607087056:tgl also know as BUG:1409180338 */
> > > - if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
> > > + if (IS_TGL_GT_REVID(i915, REVID_A0, REVID_A0))
> > > wa_write_or(wal,
> > > SLICE_UNIT_LEVEL_CLKGATE,
> > > L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
> > > @@ -1734,7 +1734,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > > struct drm_i915_private *i915 = engine->i915;
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
> > > - IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
> > > + IS_TGL_GT_REVID(i915, REVID_A0, REVID_A0)) {
> > > /*
> > > * Wa_1607138336:tgl[a0],dg1[a0]
> > > * Wa_1607063988:tgl[a0],dg1[a0]
> > > @@ -1744,7 +1744,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > > GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
> > > }
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > - if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
> > > + if (IS_TGL_GT_REVID(i915, REVID_A0, REVID_A0)) {
> > > /*
> > > * Wa_1606679103:tgl
> > > * (see also Wa_1606682166:icl)
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > index 15be8debae54..437916aacaa6 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -1565,11 +1565,11 @@ extern const struct i915_rev_steppings kbl_revids[];
> > > (IS_JSL_EHL(p) && IS_REVID(p, since, until))
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > enum {
> > > - TGL_REVID_A0,
> > > - TGL_REVID_B0,
> > > - TGL_REVID_B1,
> > > - TGL_REVID_C0,
> > > - TGL_REVID_D0,
> > > + REVID_A0,
> > > + REVID_B0,
> > > + REVID_B1,
> > > + REVID_C0,
> > > + REVID_D0,
> >
> > Better keep "TGL_" otherwise this could be used in other platforms that have different values for each revision.
> >
> > > };
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > extern const struct i915_rev_steppings tgl_uy_revids[];
> > > @@ -1579,9 +1579,9 @@ static inline const struct i915_rev_steppings *
> > > tgl_revids_get(struct drm_i915_private *dev_priv)
> > > {
> > > if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv))
> > > - return tgl_uy_revids;
> > > + return tgl_uy_revids + INTEL_REVID(dev_priv);
> > > else
> > > - return tgl_revids;
> > > + return tgl_revids + INTEL_REVID(dev_priv);
> >
> > better do tgl_revids[INTEL_REVID(dev_priv)] with a array size check first.
> >
> > > }
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > #define IS_TGL_DISP_REVID(p, since, until) \
> > > @@ -1589,16 +1589,10 @@ tgl_revids_get(struct drm_i915_private *dev_priv)
> > > tgl_revids_get(p)->disp_stepping >= (since) && \
> > > tgl_revids_get(p)->disp_stepping <= (until))
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > -#define IS_TGL_UY_GT_REVID(p, since, until) \
> > > - ((IS_TGL_U(p) || IS_TGL_Y(p)) && \
> > > - tgl_uy_revids->gt_stepping >= (since) && \
> > > - tgl_uy_revids->gt_stepping <= (until))
> > > -
> > > #define IS_TGL_GT_REVID(p, since, until) \
> > > (IS_TIGERLAKE(p) && \
> > > - !(IS_TGL_U(p) || IS_TGL_Y(p)) && \
> > > - tgl_revids->gt_stepping >= (since) && \
> > > - tgl_revids->gt_stepping <= (until))
> > > + tgl_revids_get(p)->gt_stepping >= (since) && \
> > > + tgl_revids_get(p)->gt_stepping <= (until))
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > #define RKL_REVID_A0 0x0
> > > #define RKL_REVID_B0 0x1
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index a20b5051f18c..69840aa0d4db 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -7110,7 +7110,7 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
> > > ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > /* Wa_1409825376:tgl (pre-prod)*/
> > > - if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1))
> > > + if (IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_B1))
> > > I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
> > > TGL_VRH_GATING_DIS);
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH 02/21] drm/i915/tgl: Fix macros for TGL SOC based WA
2020-11-17 19:33 ` Souza, Jose
@ 2020-11-18 7:56 ` Lucas De Marchi
0 siblings, 0 replies; 56+ messages in thread
From: Lucas De Marchi @ 2020-11-18 7:56 UTC (permalink / raw)
To: Souza, Jose; +Cc: Nikula, Jani, intel-gfx
On Tue, Nov 17, 2020 at 07:33:11PM +0000, Jose Souza wrote:
>On Tue, 2020-11-17 at 11:28 -0800, Lucas De Marchi wrote:
>> On Tue, Nov 17, 2020 at 07:03:05PM +0000, Jose Souza wrote:
>> > On Tue, 2020-11-17 at 10:50 -0800, Aditya Swarup wrote:
>> > > Fix macros for applying TGL SOC WAs by using INTEL_REVID()
>> > > as index to fetch correct revision offset in TGL GT/DISP stepping
>> > > table.
>> >
>> > Please explain what exactly is the issue you are fixing, the change you did in tgl_revids_get() + IS_TGL_GT_REVID looks a improvement but not a fix.
>>
>> otherwise it always gets the first entry from the table, regardless
>> what' s the revid we are running on... so it does look like a very
>> important fix.
>
>Ooh okay, so the fix should only be
>tgl_uy_revids/tgl_revids->gt_stepping[INTEL_REVID(dev_priv)]
as noted in my review to the patch, after checking the array bounds
Lucas De marchi
>
>Then the improvements in other patches.
>
>>
>> >
>> > >
>> > > Also, remove redundant macros and simplify it to use GT and DISP
>> > > macros for getting applicable stepping for TGL.
>>
>> As a fix, this should not be mixed with the noisy s/TGL_REVID/REVID/, as
>> it makes it much more difficult for backports and to review. Please
>> split it in another patch (I actually don' t see a reason to do it
>> actually... I'd rather try to move away from these tables if possible).
>>
>> Lucas De Marchi
>>
>> > >
>> > > Fixes: ("drm/i915/tgl: Fix stepping WA matching")
>> > > Cc: José Roberto de Souza <jose.souza@intel.com>
>> > > Cc: Matt Roper <matthew.d.roper@intel.com>
>> > > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>> > > Cc: Jani Nikula <jani.nikula@intel.com>
>> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > > Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>> > > ---
>> > > .../drm/i915/display/intel_display_power.c | 2 +-
>> > > drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
>> > > drivers/gpu/drm/i915/display/intel_sprite.c | 2 +-
>> > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 ++++++++--------
>> > > drivers/gpu/drm/i915/i915_drv.h | 24 +++++++------------
>> > > drivers/gpu/drm/i915/intel_pm.c | 2 +-
>> > > 6 files changed, 24 insertions(+), 30 deletions(-)
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>> > > index fe2d90bba536..06c036e2092c 100644
>> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> > > @@ -5283,7 +5283,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
>> > > int config, i;
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > > if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
>> > > - IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
>> > > + IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_B0))
>> > > /* Wa_1409767108:tgl,dg1 */
>> > > table = wa_1409767108_buddy_page_masks;
>> > > else
>> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>> > > index b3631b722de3..c057a03b2ed4 100644
>> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> > > @@ -550,7 +550,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > > if (dev_priv->psr.psr2_sel_fetch_enabled) {
>> > > /* WA 1408330847 */
>> > > - if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
>> > > + if (IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_A0) ||
>> > > IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
>> > > intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>> > > DIS_RAM_BYPASS_PSR2_MAN_TRACK,
>> > > @@ -1102,7 +1102,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > > /* WA 1408330847 */
>> > > if (dev_priv->psr.psr2_sel_fetch_enabled &&
>> > > - (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
>> > > + (IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_A0) ||
>> > > IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
>> > > intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>> > > DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
>> > > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
>> > > index a3ab44694118..f7da4a56054e 100644
>> > > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
>> > > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>> > > @@ -3022,7 +3022,7 @@ static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
>> > > {
>> > > /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
>> > > if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
>> > > - IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
>> > > + IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_C0))
>> > > return false;
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > > return plane_id < PLANE_SPRITE4;
>> > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> > > index a82554baa6ac..d756155d82ea 100644
>> > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> > > @@ -71,16 +71,16 @@ const struct i915_rev_steppings kbl_revids[] = {
>> > > };
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > > const struct i915_rev_steppings tgl_uy_revids[] = {
>> > > - [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_A0 },
>> > > - [1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_C0 },
>> > > - [2] = { .gt_stepping = TGL_REVID_B1, .disp_stepping = TGL_REVID_C0 },
>> > > - [3] = { .gt_stepping = TGL_REVID_C0, .disp_stepping = TGL_REVID_D0 },
>> > > + [0] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_A0 },
>> > > + [1] = { .gt_stepping = REVID_B0, .disp_stepping = REVID_C0 },
>> > > + [2] = { .gt_stepping = REVID_B1, .disp_stepping = REVID_C0 },
>> > > + [3] = { .gt_stepping = REVID_C0, .disp_stepping = REVID_D0 },
>> > > };
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > > /* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */
>> > > const struct i915_rev_steppings tgl_revids[] = {
>> > > - [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_B0 },
>> > > - [1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_D0 },
>> > > + [0] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_B0 },
>> > > + [1] = { .gt_stepping = REVID_B0, .disp_stepping = REVID_D0 },
>> > > };
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > > static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
>> > > @@ -1250,13 +1250,13 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>> > > gen12_gt_workarounds_init(i915, wal);
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > > /* Wa_1409420604:tgl */
>> > > - if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
>> > > + if (IS_TGL_GT_REVID(i915, REVID_A0, REVID_A0))
>> > > wa_write_or(wal,
>> > > SUBSLICE_UNIT_LEVEL_CLKGATE2,
>> > > CPSSUNIT_CLKGATE_DIS);
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > > /* Wa_1607087056:tgl also know as BUG:1409180338 */
>> > > - if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
>> > > + if (IS_TGL_GT_REVID(i915, REVID_A0, REVID_A0))
>> > > wa_write_or(wal,
>> > > SLICE_UNIT_LEVEL_CLKGATE,
>> > > L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
>> > > @@ -1734,7 +1734,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> > > struct drm_i915_private *i915 = engine->i915;
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > > if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
>> > > - IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
>> > > + IS_TGL_GT_REVID(i915, REVID_A0, REVID_A0)) {
>> > > /*
>> > > * Wa_1607138336:tgl[a0],dg1[a0]
>> > > * Wa_1607063988:tgl[a0],dg1[a0]
>> > > @@ -1744,7 +1744,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> > > GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
>> > > }
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > > - if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
>> > > + if (IS_TGL_GT_REVID(i915, REVID_A0, REVID_A0)) {
>> > > /*
>> > > * Wa_1606679103:tgl
>> > > * (see also Wa_1606682166:icl)
>> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> > > index 15be8debae54..437916aacaa6 100644
>> > > --- a/drivers/gpu/drm/i915/i915_drv.h
>> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
>> > > @@ -1565,11 +1565,11 @@ extern const struct i915_rev_steppings kbl_revids[];
>> > > (IS_JSL_EHL(p) && IS_REVID(p, since, until))
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > > enum {
>> > > - TGL_REVID_A0,
>> > > - TGL_REVID_B0,
>> > > - TGL_REVID_B1,
>> > > - TGL_REVID_C0,
>> > > - TGL_REVID_D0,
>> > > + REVID_A0,
>> > > + REVID_B0,
>> > > + REVID_B1,
>> > > + REVID_C0,
>> > > + REVID_D0,
>> >
>> > Better keep "TGL_" otherwise this could be used in other platforms that have different values for each revision.
>> >
>> > > };
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > > extern const struct i915_rev_steppings tgl_uy_revids[];
>> > > @@ -1579,9 +1579,9 @@ static inline const struct i915_rev_steppings *
>> > > tgl_revids_get(struct drm_i915_private *dev_priv)
>> > > {
>> > > if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv))
>> > > - return tgl_uy_revids;
>> > > + return tgl_uy_revids + INTEL_REVID(dev_priv);
>> > > else
>> > > - return tgl_revids;
>> > > + return tgl_revids + INTEL_REVID(dev_priv);
>> >
>> > better do tgl_revids[INTEL_REVID(dev_priv)] with a array size check first.
>> >
>> > > }
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > > #define IS_TGL_DISP_REVID(p, since, until) \
>> > > @@ -1589,16 +1589,10 @@ tgl_revids_get(struct drm_i915_private *dev_priv)
>> > > tgl_revids_get(p)->disp_stepping >= (since) && \
>> > > tgl_revids_get(p)->disp_stepping <= (until))
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > > -#define IS_TGL_UY_GT_REVID(p, since, until) \
>> > > - ((IS_TGL_U(p) || IS_TGL_Y(p)) && \
>> > > - tgl_uy_revids->gt_stepping >= (since) && \
>> > > - tgl_uy_revids->gt_stepping <= (until))
>> > > -
>> > > #define IS_TGL_GT_REVID(p, since, until) \
>> > > (IS_TIGERLAKE(p) && \
>> > > - !(IS_TGL_U(p) || IS_TGL_Y(p)) && \
>> > > - tgl_revids->gt_stepping >= (since) && \
>> > > - tgl_revids->gt_stepping <= (until))
>> > > + tgl_revids_get(p)->gt_stepping >= (since) && \
>> > > + tgl_revids_get(p)->gt_stepping <= (until))
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > > #define RKL_REVID_A0 0x0
>> > > #define RKL_REVID_B0 0x1
>> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> > > index a20b5051f18c..69840aa0d4db 100644
>> > > --- a/drivers/gpu/drm/i915/intel_pm.c
>> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
>> > > @@ -7110,7 +7110,7 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
>> > > ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > > /* Wa_1409825376:tgl (pre-prod)*/
>> > > - if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1))
>> > > + if (IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_B1))
>> > > I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
>> > > TGL_VRH_GATING_DIS);
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> >
>> > _______________________________________________
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Intel-gfx] [PATCH 02/21] drm/i915/tgl: Fix macros for TGL SOC based WA
2020-11-17 18:50 ` [Intel-gfx] [PATCH 02/21] drm/i915/tgl: Fix macros for TGL SOC based WA Aditya Swarup
2020-11-17 19:03 ` Souza, Jose
@ 2020-11-17 19:31 ` Lucas De Marchi
2020-11-18 9:18 ` Jani Nikula
1 sibling, 1 reply; 56+ messages in thread
From: Lucas De Marchi @ 2020-11-17 19:31 UTC (permalink / raw)
To: Aditya Swarup; +Cc: Jani Nikula, intel-gfx
On Tue, Nov 17, 2020 at 10:50:10AM -0800, Aditya Swarup wrote:
>@@ -1579,9 +1579,9 @@ static inline const struct i915_rev_steppings *
> tgl_revids_get(struct drm_i915_private *dev_priv)
> {
> if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv))
>- return tgl_uy_revids;
>+ return tgl_uy_revids + INTEL_REVID(dev_priv);
oohh, no. You have to at least check you are not accessing out of
bounds. New HW running on old kernel should not access create invalid
accesses like this.
Lucas De Marchi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH 02/21] drm/i915/tgl: Fix macros for TGL SOC based WA
2020-11-17 19:31 ` Lucas De Marchi
@ 2020-11-18 9:18 ` Jani Nikula
2020-11-24 1:32 ` Aditya Swarup
0 siblings, 1 reply; 56+ messages in thread
From: Jani Nikula @ 2020-11-18 9:18 UTC (permalink / raw)
To: Lucas De Marchi, Aditya Swarup; +Cc: intel-gfx
On Tue, 17 Nov 2020, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> On Tue, Nov 17, 2020 at 10:50:10AM -0800, Aditya Swarup wrote:
>>@@ -1579,9 +1579,9 @@ static inline const struct i915_rev_steppings *
>> tgl_revids_get(struct drm_i915_private *dev_priv)
>> {
>> if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv))
>>- return tgl_uy_revids;
>>+ return tgl_uy_revids + INTEL_REVID(dev_priv);
>
> oohh, no. You have to at least check you are not accessing out of
> bounds. New HW running on old kernel should not access create invalid
> accesses like this.
And this is just one reason why exposing arrays directly as an interface
to the rest of the driver is a bad idea. Basically I look at *all*
externs in the driver with suspicion, and they're all exceptions that
should not be repeated. The revid arrays are a direct invitation to keep
adding more and more extern arrays. And more ways to go out of bounds.
I'd rather we seek for ways to either nuke the revid arrays altogether,
or encapsulate them within a .c file with static scope.
And for that .c file... the arrays are now in gt/intel_workarounds.c
which is a really weird place for stuff that's used for generic stepping
info, and particularly for *display* stepping info.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH 02/21] drm/i915/tgl: Fix macros for TGL SOC based WA
2020-11-18 9:18 ` Jani Nikula
@ 2020-11-24 1:32 ` Aditya Swarup
2020-11-24 13:14 ` Lucas De Marchi
0 siblings, 1 reply; 56+ messages in thread
From: Aditya Swarup @ 2020-11-24 1:32 UTC (permalink / raw)
To: Jani Nikula, Lucas De Marchi; +Cc: intel-gfx
On 11/18/20 1:18 AM, Jani Nikula wrote:
> On Tue, 17 Nov 2020, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>> On Tue, Nov 17, 2020 at 10:50:10AM -0800, Aditya Swarup wrote:
>>> @@ -1579,9 +1579,9 @@ static inline const struct i915_rev_steppings *
>>> tgl_revids_get(struct drm_i915_private *dev_priv)
>>> {
>>> if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv))
>>> - return tgl_uy_revids;
>>> + return tgl_uy_revids + INTEL_REVID(dev_priv);
>>
>> oohh, no. You have to at least check you are not accessing out of
>> bounds. New HW running on old kernel should not access create invalid
>> accesses like this.
>
> And this is just one reason why exposing arrays directly as an interface
> to the rest of the driver is a bad idea. Basically I look at *all*
> externs in the driver with suspicion, and they're all exceptions that
> should not be repeated. The revid arrays are a direct invitation to keep
> adding more and more extern arrays. And more ways to go out of bounds.
We definitely need an array table for the SOC -> Display, GT stepping mapping.
SOC steppings were usually the same as display steppings/GT steppings until TGL and therefore
didn't require special mapping cases. But from TGL onwards, we have different combinations of
Disp and GT steppings per SOC stepping. Alderlake-S makes this direct mapping even more difficult
without the array requiring more macros to deal with SOC -> DISP/GT stepping differences.
Will fix the array bound checks but the possibility of SOC revision id from drm struct going
out of bounds is minimal. Can only happen if we don't have support for latest SOC -> Disp/GT table
for TGL from Bspec and if we are picking up wrong revision id from drm struct that means the platform
information obtained itself is wrong which will be a general platform problem unrelated to Gfx driver.
>
> I'd rather we seek for ways to either nuke the revid arrays altogether,
> or encapsulate them within a .c file with static scope.
I don't think we should nuke the revid arrays but I agree with finding a more appropriate place to
parse the gt/display stepping info. This should be an exercise for a later patch that takes
care of kbl,tgl and adl-s mappings.
>
> And for that .c file... the arrays are now in gt/intel_workarounds.c
> which is a really weird place for stuff that's used for generic stepping
> info, and particularly for *display* stepping info.
I agree and we can change the approach with a different patch later.
>
> BR,
> Jani.
>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH 02/21] drm/i915/tgl: Fix macros for TGL SOC based WA
2020-11-24 1:32 ` Aditya Swarup
@ 2020-11-24 13:14 ` Lucas De Marchi
2020-11-24 14:20 ` Jani Nikula
0 siblings, 1 reply; 56+ messages in thread
From: Lucas De Marchi @ 2020-11-24 13:14 UTC (permalink / raw)
To: Aditya Swarup; +Cc: Jani Nikula, intel-gfx
On Mon, Nov 23, 2020 at 05:32:22PM -0800, Aditya Swarup wrote:
>On 11/18/20 1:18 AM, Jani Nikula wrote:
>> On Tue, 17 Nov 2020, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>>> On Tue, Nov 17, 2020 at 10:50:10AM -0800, Aditya Swarup wrote:
>>>> @@ -1579,9 +1579,9 @@ static inline const struct i915_rev_steppings *
>>>> tgl_revids_get(struct drm_i915_private *dev_priv)
>>>> {
>>>> if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv))
>>>> - return tgl_uy_revids;
>>>> + return tgl_uy_revids + INTEL_REVID(dev_priv);
>>>
>>> oohh, no. You have to at least check you are not accessing out of
>>> bounds. New HW running on old kernel should not access create invalid
>>> accesses like this.
>>
>> And this is just one reason why exposing arrays directly as an interface
>> to the rest of the driver is a bad idea. Basically I look at *all*
>> externs in the driver with suspicion, and they're all exceptions that
>> should not be repeated. The revid arrays are a direct invitation to keep
>> adding more and more extern arrays. And more ways to go out of bounds.
>
>We definitely need an array table for the SOC -> Display, GT stepping mapping.
the mapping could be very well in the define iff you don't have
different mappings per sku as is the case with TGL. Example:
#define ADLS_REVID_A0 0
#define ADLS_REVID_A1 5
#define ADLS_DISP_REVID_A0 0
#define ADLS_DISP_REVID_B0 5
The actual value is actually the *SoC* revid, regardless the name of the
macro. Since we already have to use a different macro -
IS_DISP_REVID() - I don't think this is much worse and would allow us to
get rid of the table *for ADL-S*, at the expense of having to pass as
argument the ADLS_DISP_REVID_*. However this doesn't apply to TGL as TGL
has a different mapping per sku.
>SOC steppings were usually the same as display steppings/GT steppings until TGL and therefore
>didn't require special mapping cases. But from TGL onwards, we have different combinations of
>Disp and GT steppings per SOC stepping. Alderlake-S makes this direct mapping even more difficult
>without the array requiring more macros to deal with SOC -> DISP/GT stepping differences.
>
>Will fix the array bound checks but the possibility of SOC revision id from drm struct going
>out of bounds is minimal. Can only happen if we don't have support for latest SOC -> Disp/GT table
this is very common. It's just a matter of trying to run a slightly old
kernel in a slightly newer rev of the hardware.
>for TGL from Bspec and if we are picking up wrong revision id from drm struct that means the platform
>information obtained itself is wrong which will be a general platform problem unrelated to Gfx driver.
Nothing else should really be a problem. We don't really use the revid
much, mostly for WAs. And if other parts of the kernel are trying to use
the SoC revid, then they are reading that info themselves, not using
something we read.
We are simply reading the revid from hardware and using that value
without checking and that needs to change.
>
>>
>> I'd rather we seek for ways to either nuke the revid arrays altogether,
>> or encapsulate them within a .c file with static scope.
>
>I don't think we should nuke the revid arrays but I agree with finding a more appropriate place to
>parse the gt/display stepping info. This should be an exercise for a later patch that takes
>care of kbl,tgl and adl-s mappings.
>
>>
>> And for that .c file... the arrays are now in gt/intel_workarounds.c
>> which is a really weird place for stuff that's used for generic stepping
>> info, and particularly for *display* stepping info.
>
>I agree and we can change the approach with a different patch later.
>
>>
>> BR,
>> Jani.
>>
>>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH 02/21] drm/i915/tgl: Fix macros for TGL SOC based WA
2020-11-24 13:14 ` Lucas De Marchi
@ 2020-11-24 14:20 ` Jani Nikula
2020-11-24 20:11 ` Lucas De Marchi
0 siblings, 1 reply; 56+ messages in thread
From: Jani Nikula @ 2020-11-24 14:20 UTC (permalink / raw)
To: Lucas De Marchi, Aditya Swarup; +Cc: intel-gfx
On Tue, 24 Nov 2020, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> On Mon, Nov 23, 2020 at 05:32:22PM -0800, Aditya Swarup wrote:
>>On 11/18/20 1:18 AM, Jani Nikula wrote:
>>> On Tue, 17 Nov 2020, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>>>> On Tue, Nov 17, 2020 at 10:50:10AM -0800, Aditya Swarup wrote:
>>>>> @@ -1579,9 +1579,9 @@ static inline const struct i915_rev_steppings *
>>>>> tgl_revids_get(struct drm_i915_private *dev_priv)
>>>>> {
>>>>> if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv))
>>>>> - return tgl_uy_revids;
>>>>> + return tgl_uy_revids + INTEL_REVID(dev_priv);
>>>>
>>>> oohh, no. You have to at least check you are not accessing out of
>>>> bounds. New HW running on old kernel should not access create invalid
>>>> accesses like this.
>>>
>>> And this is just one reason why exposing arrays directly as an interface
>>> to the rest of the driver is a bad idea. Basically I look at *all*
>>> externs in the driver with suspicion, and they're all exceptions that
>>> should not be repeated. The revid arrays are a direct invitation to keep
>>> adding more and more extern arrays. And more ways to go out of bounds.
>>
>>We definitely need an array table for the SOC -> Display, GT stepping mapping.
>
> the mapping could be very well in the define iff you don't have
> different mappings per sku as is the case with TGL. Example:
>
> #define ADLS_REVID_A0 0
> #define ADLS_REVID_A1 5
>
> #define ADLS_DISP_REVID_A0 0
> #define ADLS_DISP_REVID_B0 5
>
> The actual value is actually the *SoC* revid, regardless the name of the
> macro. Since we already have to use a different macro -
> IS_DISP_REVID() - I don't think this is much worse and would allow us to
> get rid of the table *for ADL-S*, at the expense of having to pass as
> argument the ADLS_DISP_REVID_*. However this doesn't apply to TGL as TGL
> has a different mapping per sku.
>
>
>>SOC steppings were usually the same as display steppings/GT steppings until TGL and therefore
>>didn't require special mapping cases. But from TGL onwards, we have different combinations of
>>Disp and GT steppings per SOC stepping. Alderlake-S makes this direct mapping even more difficult
>>without the array requiring more macros to deal with SOC -> DISP/GT stepping differences.
>>
>>Will fix the array bound checks but the possibility of SOC revision id from drm struct going
>>out of bounds is minimal. Can only happen if we don't have support for latest SOC -> Disp/GT table
>
> this is very common. It's just a matter of trying to run a slightly old
> kernel in a slightly newer rev of the hardware.
Indeed. All kernels released with the arrays are simply bust for any new
hardware revisions. They'll need a minimal Cc: stable fix.
Here's something I drafted [1] to fix the situation more
generally. There are still some issues to overcome, though they exist
already in the current code.
This could be followed up with converting *all* platforms to the scheme,
making it universal, regardless of whether the revids in the hardware
are consecutive or not.
BR,
Jani.
[1] https://cgit.freedesktop.org/~jani/drm/log/?h=revid-stepping-scheme
>
>>for TGL from Bspec and if we are picking up wrong revision id from drm struct that means the platform
>>information obtained itself is wrong which will be a general platform problem unrelated to Gfx driver.
>
> Nothing else should really be a problem. We don't really use the revid
> much, mostly for WAs. And if other parts of the kernel are trying to use
> the SoC revid, then they are reading that info themselves, not using
> something we read.
>
> We are simply reading the revid from hardware and using that value
> without checking and that needs to change.
>
>
>>
>>>
>>> I'd rather we seek for ways to either nuke the revid arrays altogether,
>>> or encapsulate them within a .c file with static scope.
>>
>>I don't think we should nuke the revid arrays but I agree with finding a more appropriate place to
>>parse the gt/display stepping info. This should be an exercise for a later patch that takes
>>care of kbl,tgl and adl-s mappings.
>>
>>>
>>> And for that .c file... the arrays are now in gt/intel_workarounds.c
>>> which is a really weird place for stuff that's used for generic stepping
>>> info, and particularly for *display* stepping info.
>>
>>I agree and we can change the approach with a different patch later.
>>
>>>
>>> BR,
>>> Jani.
>>>
>>>
>>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH 02/21] drm/i915/tgl: Fix macros for TGL SOC based WA
2020-11-24 14:20 ` Jani Nikula
@ 2020-11-24 20:11 ` Lucas De Marchi
2020-11-25 0:48 ` Aditya Swarup
0 siblings, 1 reply; 56+ messages in thread
From: Lucas De Marchi @ 2020-11-24 20:11 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
+Matt Roper, see question in item (3) below
On Tue, Nov 24, 2020 at 04:20:40PM +0200, Jani Nikula wrote:
>On Tue, 24 Nov 2020, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>> On Mon, Nov 23, 2020 at 05:32:22PM -0800, Aditya Swarup wrote:
>>>On 11/18/20 1:18 AM, Jani Nikula wrote:
>>>> On Tue, 17 Nov 2020, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>>>>> On Tue, Nov 17, 2020 at 10:50:10AM -0800, Aditya Swarup wrote:
>>>>>> @@ -1579,9 +1579,9 @@ static inline const struct i915_rev_steppings *
>>>>>> tgl_revids_get(struct drm_i915_private *dev_priv)
>>>>>> {
>>>>>> if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv))
>>>>>> - return tgl_uy_revids;
>>>>>> + return tgl_uy_revids + INTEL_REVID(dev_priv);
>>>>>
>>>>> oohh, no. You have to at least check you are not accessing out of
>>>>> bounds. New HW running on old kernel should not access create invalid
>>>>> accesses like this.
>>>>
>>>> And this is just one reason why exposing arrays directly as an interface
>>>> to the rest of the driver is a bad idea. Basically I look at *all*
>>>> externs in the driver with suspicion, and they're all exceptions that
>>>> should not be repeated. The revid arrays are a direct invitation to keep
>>>> adding more and more extern arrays. And more ways to go out of bounds.
>>>
>>>We definitely need an array table for the SOC -> Display, GT stepping mapping.
>>
>> the mapping could be very well in the define iff you don't have
>> different mappings per sku as is the case with TGL. Example:
>>
>> #define ADLS_REVID_A0 0
>> #define ADLS_REVID_A1 5
>>
>> #define ADLS_DISP_REVID_A0 0
>> #define ADLS_DISP_REVID_B0 5
>>
>> The actual value is actually the *SoC* revid, regardless the name of the
>> macro. Since we already have to use a different macro -
>> IS_DISP_REVID() - I don't think this is much worse and would allow us to
>> get rid of the table *for ADL-S*, at the expense of having to pass as
>> argument the ADLS_DISP_REVID_*. However this doesn't apply to TGL as TGL
>> has a different mapping per sku.
>>
>>
>>>SOC steppings were usually the same as display steppings/GT steppings until TGL and therefore
>>>didn't require special mapping cases. But from TGL onwards, we have different combinations of
>>>Disp and GT steppings per SOC stepping. Alderlake-S makes this direct mapping even more difficult
>>>without the array requiring more macros to deal with SOC -> DISP/GT stepping differences.
>>>
>>>Will fix the array bound checks but the possibility of SOC revision id from drm struct going
>>>out of bounds is minimal. Can only happen if we don't have support for latest SOC -> Disp/GT table
>>
>> this is very common. It's just a matter of trying to run a slightly old
>> kernel in a slightly newer rev of the hardware.
>
>Indeed. All kernels released with the arrays are simply bust for any new
>hardware revisions. They'll need a minimal Cc: stable fix.
>
>Here's something I drafted [1] to fix the situation more
>generally. There are still some issues to overcome, though they exist
>already in the current code.
>
>This could be followed up with converting *all* platforms to the scheme,
>making it universal, regardless of whether the revids in the hardware
>are consecutive or not.
>
>BR,
>Jani.
>
>
>[1] https://cgit.freedesktop.org/~jani/drm/log/?h=revid-stepping-scheme
That is looking good. Some feedback I can give before this series being
sent for review:
1) You need to call the init function from somewhere
2) For the FIXMEs:
+ /*
+ * FIXME: We should be able to take into account new revids not
+ * recognized by this kernel version.
+ */
+ /*
+ * FIXME: We should be able to handle gaps in revid arrays gracefully,
+ * and in a way that works sensibly for the range checks. This is true
+ * for the existing revid range checks; it's fine if a new id pops up in
+ * the middle.
+ *
+ * It's okay for the display stepping to be zero, though in an array all
+ * or none should be set to non-zero, not a mix.
+ */
Maybe consider that gt_stepping will never be 0 and in the case it is (or
size > ARRAY_SIZE), just backtrack to use the first one we find with
gt_stepping != 0? then we probably should add a warning that we are not
actually using the correct one, but it's the best we can do.
3) REVID_BXT_B_LAST
what is that? The only thing that comes to mind is for "matching all B
steps". Matt Roper had a patch to change the way we interpret the WA
ranges so the bounds are [lower, upper) rather than [lower, upper].
Matt, any problem you faced with that patch? It makes more sense
because we know the stepping in which it's fixed, but we may have
additional revids before that
But I don't see any trace of REVID_BXT_B_LAST in the tree, so not sure
what's this about.
4)
Lastly, I'd still like the simple fix for TGL without all the noise and
without the refactor. It's the simplest fix we can do for the 5.10
timeframe.
Lucas De Marchi
>
>
>
>
>>
>>>for TGL from Bspec and if we are picking up wrong revision id from drm struct that means the platform
>>>information obtained itself is wrong which will be a general platform problem unrelated to Gfx driver.
>>
>> Nothing else should really be a problem. We don't really use the revid
>> much, mostly for WAs. And if other parts of the kernel are trying to use
>> the SoC revid, then they are reading that info themselves, not using
>> something we read.
>>
>> We are simply reading the revid from hardware and using that value
>> without checking and that needs to change.
>>
>>
>>>
>>>>
>>>> I'd rather we seek for ways to either nuke the revid arrays altogether,
>>>> or encapsulate them within a .c file with static scope.
>>>
>>>I don't think we should nuke the revid arrays but I agree with finding a more appropriate place to
>>>parse the gt/display stepping info. This should be an exercise for a later patch that takes
>>>care of kbl,tgl and adl-s mappings.
>>>
>>>>
>>>> And for that .c file... the arrays are now in gt/intel_workarounds.c
>>>> which is a really weird place for stuff that's used for generic stepping
>>>> info, and particularly for *display* stepping info.
>>>
>>>I agree and we can change the approach with a different patch later.
>>>
>>>>
>>>> BR,
>>>> Jani.
>>>>
>>>>
>>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>--
>Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH 02/21] drm/i915/tgl: Fix macros for TGL SOC based WA
2020-11-24 20:11 ` Lucas De Marchi
@ 2020-11-25 0:48 ` Aditya Swarup
2020-11-25 8:36 ` Jani Nikula
0 siblings, 1 reply; 56+ messages in thread
From: Aditya Swarup @ 2020-11-25 0:48 UTC (permalink / raw)
To: Lucas De Marchi, Jani Nikula; +Cc: intel-gfx
On 11/24/20 12:11 PM, Lucas De Marchi wrote:
> +Matt Roper, see question in item (3) below
>
> On Tue, Nov 24, 2020 at 04:20:40PM +0200, Jani Nikula wrote:
>> On Tue, 24 Nov 2020, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>>> On Mon, Nov 23, 2020 at 05:32:22PM -0800, Aditya Swarup wrote:
>>>> On 11/18/20 1:18 AM, Jani Nikula wrote:
>>>>> On Tue, 17 Nov 2020, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>>>>>> On Tue, Nov 17, 2020 at 10:50:10AM -0800, Aditya Swarup wrote:
>>>>>>> @@ -1579,9 +1579,9 @@ static inline const struct i915_rev_steppings *
>>>>>>> tgl_revids_get(struct drm_i915_private *dev_priv)
>>>>>>> {
>>>>>>> if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv))
>>>>>>> - return tgl_uy_revids;
>>>>>>> + return tgl_uy_revids + INTEL_REVID(dev_priv);
>>>>>>
>>>>>> oohh, no. You have to at least check you are not accessing out of
>>>>>> bounds. New HW running on old kernel should not access create invalid
>>>>>> accesses like this.
>>>>>
>>>>> And this is just one reason why exposing arrays directly as an interface
>>>>> to the rest of the driver is a bad idea. Basically I look at *all*
>>>>> externs in the driver with suspicion, and they're all exceptions that
>>>>> should not be repeated. The revid arrays are a direct invitation to keep
>>>>> adding more and more extern arrays. And more ways to go out of bounds.
>>>>
>>>> We definitely need an array table for the SOC -> Display, GT stepping mapping.
>>>
>>> the mapping could be very well in the define iff you don't have
>>> different mappings per sku as is the case with TGL. Example:
>>>
>>> #define ADLS_REVID_A0 0
>>> #define ADLS_REVID_A1 5
>>>
>>> #define ADLS_DISP_REVID_A0 0
>>> #define ADLS_DISP_REVID_B0 5
>>>
>>> The actual value is actually the *SoC* revid, regardless the name of the
>>> macro. Since we already have to use a different macro -
>>> IS_DISP_REVID() - I don't think this is much worse and would allow us to
>>> get rid of the table *for ADL-S*, at the expense of having to pass as
>>> argument the ADLS_DISP_REVID_*. However this doesn't apply to TGL as TGL
>>> has a different mapping per sku.
>>>
>>>
>>>> SOC steppings were usually the same as display steppings/GT steppings until TGL and therefore
>>>> didn't require special mapping cases. But from TGL onwards, we have different combinations of
>>>> Disp and GT steppings per SOC stepping. Alderlake-S makes this direct mapping even more difficult
>>>> without the array requiring more macros to deal with SOC -> DISP/GT stepping differences.
>>>>
>>>> Will fix the array bound checks but the possibility of SOC revision id from drm struct going
>>>> out of bounds is minimal. Can only happen if we don't have support for latest SOC -> Disp/GT table
>>>
>>> this is very common. It's just a matter of trying to run a slightly old
>>> kernel in a slightly newer rev of the hardware.
>>
>> Indeed. All kernels released with the arrays are simply bust for any new
>> hardware revisions. They'll need a minimal Cc: stable fix.
>>
>> Here's something I drafted [1] to fix the situation more
>> generally. There are still some issues to overcome, though they exist
>> already in the current code.
>>
>> This could be followed up with converting *all* platforms to the scheme,
>> making it universal, regardless of whether the revids in the hardware
>> are consecutive or not.
>>
>> BR,
>> Jani.
>>
>>
>> [1] https://cgit.freedesktop.org/~jani/drm/log/?h=revid-stepping-scheme
>
> That is looking good. Some feedback I can give before this series being
> sent for review:
I like this approach as well and we were discussing this in the ADLS rev ID thread. With the tables it
makes it simpler to manage rather than worrying about individual macros. Jani do you want me to rebase ADLS
changes on top of your patches and resubmit your patches for review or you will be submitting this series yourself?
>
> 1) You need to call the init function from somewhere
> 2) For the FIXMEs:
>
> + /*
> + * FIXME: We should be able to take into account new revids not
> + * recognized by this kernel version.
> + */
>
> + /*
> + * FIXME: We should be able to handle gaps in revid arrays gracefully,
> + * and in a way that works sensibly for the range checks. This is true
> + * for the existing revid range checks; it's fine if a new id pops up in
> + * the middle.
> + *
> + * It's okay for the display stepping to be zero, though in an array all
> + * or none should be set to non-zero, not a mix.
> + */
>
> Maybe consider that gt_stepping will never be 0 and in the case it is (or
> size > ARRAY_SIZE), just backtrack to use the first one we find with
> gt_stepping != 0? then we probably should add a warning that we are not
> actually using the correct one, but it's the best we can do.
>
> 3) REVID_BXT_B_LAST
I couldn't spot REVID_NONE as well in the patches.
>
> what is that? The only thing that comes to mind is for "matching all B
> steps". Matt Roper had a patch to change the way we interpret the WA
> ranges so the bounds are [lower, upper) rather than [lower, upper].
> Matt, any problem you faced with that patch? It makes more sense
> because we know the stepping in which it's fixed, but we may have
> additional revids before that
>
> But I don't see any trace of REVID_BXT_B_LAST in the tree, so not sure
> what's this about.
>
> 4)
>
> Lastly, I'd still like the simple fix for TGL without all the noise and
> without the refactor. It's the simplest fix we can do for the 5.10
> timeframe.
I just submitted the fix.
Aditya
>
>
> Lucas De Marchi
>
>>
>>
>>
>>
>>>
>>>> for TGL from Bspec and if we are picking up wrong revision id from drm struct that means the platform
>>>> information obtained itself is wrong which will be a general platform problem unrelated to Gfx driver.
>>>
>>> Nothing else should really be a problem. We don't really use the revid
>>> much, mostly for WAs. And if other parts of the kernel are trying to use
>>> the SoC revid, then they are reading that info themselves, not using
>>> something we read.
>>>
>>> We are simply reading the revid from hardware and using that value
>>> without checking and that needs to change.
>>>
>>>
>>>>
>>>>>
>>>>> I'd rather we seek for ways to either nuke the revid arrays altogether,
>>>>> or encapsulate them within a .c file with static scope.
>>>>
>>>> I don't think we should nuke the revid arrays but I agree with finding a more appropriate place to
>>>> parse the gt/display stepping info. This should be an exercise for a later patch that takes
>>>> care of kbl,tgl and adl-s mappings.
>>>>
>>>>>
>>>>> And for that .c file... the arrays are now in gt/intel_workarounds.c
>>>>> which is a really weird place for stuff that's used for generic stepping
>>>>> info, and particularly for *display* stepping info.
>>>>
>>>> I agree and we can change the approach with a different patch later.
>>>>
>>>>>
>>>>> BR,
>>>>> Jani.
>>>>>
>>>>>
>>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH 02/21] drm/i915/tgl: Fix macros for TGL SOC based WA
2020-11-25 0:48 ` Aditya Swarup
@ 2020-11-25 8:36 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2020-11-25 8:36 UTC (permalink / raw)
To: Aditya Swarup, Lucas De Marchi; +Cc: intel-gfx
On Tue, 24 Nov 2020, Aditya Swarup <aditya.swarup@intel.com> wrote:
> On 11/24/20 12:11 PM, Lucas De Marchi wrote:
>> +Matt Roper, see question in item (3) below
>>
>> On Tue, Nov 24, 2020 at 04:20:40PM +0200, Jani Nikula wrote:
>>> On Tue, 24 Nov 2020, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>>>> On Mon, Nov 23, 2020 at 05:32:22PM -0800, Aditya Swarup wrote:
>>>>> On 11/18/20 1:18 AM, Jani Nikula wrote:
>>>>>> On Tue, 17 Nov 2020, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>>>>>>> On Tue, Nov 17, 2020 at 10:50:10AM -0800, Aditya Swarup wrote:
>>>>>>>> @@ -1579,9 +1579,9 @@ static inline const struct i915_rev_steppings *
>>>>>>>> tgl_revids_get(struct drm_i915_private *dev_priv)
>>>>>>>> {
>>>>>>>> if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv))
>>>>>>>> - return tgl_uy_revids;
>>>>>>>> + return tgl_uy_revids + INTEL_REVID(dev_priv);
>>>>>>>
>>>>>>> oohh, no. You have to at least check you are not accessing out of
>>>>>>> bounds. New HW running on old kernel should not access create invalid
>>>>>>> accesses like this.
>>>>>>
>>>>>> And this is just one reason why exposing arrays directly as an interface
>>>>>> to the rest of the driver is a bad idea. Basically I look at *all*
>>>>>> externs in the driver with suspicion, and they're all exceptions that
>>>>>> should not be repeated. The revid arrays are a direct invitation to keep
>>>>>> adding more and more extern arrays. And more ways to go out of bounds.
>>>>>
>>>>> We definitely need an array table for the SOC -> Display, GT stepping mapping.
>>>>
>>>> the mapping could be very well in the define iff you don't have
>>>> different mappings per sku as is the case with TGL. Example:
>>>>
>>>> #define ADLS_REVID_A0 0
>>>> #define ADLS_REVID_A1 5
>>>>
>>>> #define ADLS_DISP_REVID_A0 0
>>>> #define ADLS_DISP_REVID_B0 5
>>>>
>>>> The actual value is actually the *SoC* revid, regardless the name of the
>>>> macro. Since we already have to use a different macro -
>>>> IS_DISP_REVID() - I don't think this is much worse and would allow us to
>>>> get rid of the table *for ADL-S*, at the expense of having to pass as
>>>> argument the ADLS_DISP_REVID_*. However this doesn't apply to TGL as TGL
>>>> has a different mapping per sku.
>>>>
>>>>
>>>>> SOC steppings were usually the same as display steppings/GT steppings until TGL and therefore
>>>>> didn't require special mapping cases. But from TGL onwards, we have different combinations of
>>>>> Disp and GT steppings per SOC stepping. Alderlake-S makes this direct mapping even more difficult
>>>>> without the array requiring more macros to deal with SOC -> DISP/GT stepping differences.
>>>>>
>>>>> Will fix the array bound checks but the possibility of SOC revision id from drm struct going
>>>>> out of bounds is minimal. Can only happen if we don't have support for latest SOC -> Disp/GT table
>>>>
>>>> this is very common. It's just a matter of trying to run a slightly old
>>>> kernel in a slightly newer rev of the hardware.
>>>
>>> Indeed. All kernels released with the arrays are simply bust for any new
>>> hardware revisions. They'll need a minimal Cc: stable fix.
>>>
>>> Here's something I drafted [1] to fix the situation more
>>> generally. There are still some issues to overcome, though they exist
>>> already in the current code.
>>>
>>> This could be followed up with converting *all* platforms to the scheme,
>>> making it universal, regardless of whether the revids in the hardware
>>> are consecutive or not.
>>>
>>> BR,
>>> Jani.
>>>
>>>
>>> [1] https://cgit.freedesktop.org/~jani/drm/log/?h=revid-stepping-scheme
>>
>> That is looking good. Some feedback I can give before this series being
>> sent for review:
>
> I like this approach as well and we were discussing this in the ADLS
> rev ID thread. With the tables it makes it simpler to manage rather
> than worrying about individual macros. Jani do you want me to rebase
> ADLS changes on top of your patches and resubmit your patches for
> review or you will be submitting this series yourself?
Please proceed with ADL as you were, I'll do the refactoring afterwards
on top. It'll take a while anyway, we don't want to delay ADL with
this. Just add the required bounds checks to the ADL patches.
>>
>> 1) You need to call the init function from somewhere
Yeah, that's a FIXME in a commit message. Draft patches and all that. ;)
I'll need to figure out where and how early we need to set this up, as
it needs to be set up before any users, obviously.
>> 2) For the FIXMEs:
>>
>> + /*
>> + * FIXME: We should be able to take into account new revids not
>> + * recognized by this kernel version.
>> + */
>>
>> + /*
>> + * FIXME: We should be able to handle gaps in revid arrays gracefully,
>> + * and in a way that works sensibly for the range checks. This is true
>> + * for the existing revid range checks; it's fine if a new id pops up in
>> + * the middle.
>> + *
>> + * It's okay for the display stepping to be zero, though in an array all
>> + * or none should be set to non-zero, not a mix.
>> + */
>>
>> Maybe consider that gt_stepping will never be 0 and in the case it is (or
>> size > ARRAY_SIZE), just backtrack to use the first one we find with
>> gt_stepping != 0? then we probably should add a warning that we are not
>> actually using the correct one, but it's the best we can do.
Yeah, it'll probably need to be something like that. I'll figure
something out.
>>
>> 3) REVID_BXT_B_LAST
>
> I couldn't spot REVID_NONE as well in the patches.
For now REVID_NONE was intended as a placeholder to ensure all valid
symbolic revids are non-zero, for array initialization purposes.
>>
>> what is that? The only thing that comes to mind is for "matching all B
>> steps". Matt Roper had a patch to change the way we interpret the WA
>> ranges so the bounds are [lower, upper) rather than [lower, upper].
>> Matt, any problem you faced with that patch? It makes more sense
>> because we know the stepping in which it's fixed, but we may have
>> additional revids before that
>>
>> But I don't see any trace of REVID_BXT_B_LAST in the tree, so not sure
>> what's this about.
I just indiscriminately scooped up all revid macros from i915_drv.h for
starters. We have BXT_REVID_B_LAST to identify the last pre-pro bxt
before C0. Needs cleanup, agreed.
>>
>> 4)
>>
>> Lastly, I'd still like the simple fix for TGL without all the noise and
>> without the refactor. It's the simplest fix we can do for the 5.10
>> timeframe.
Agreed.
> I just submitted the fix.
Thanks. Let's get that done first, then the ADL enabling, then I'll do
the refactoring afterwards.
BR,
Jani.
>
> Aditya
>
>>
>>
>> Lucas De Marchi
>>
>>>
>>>
>>>
>>>
>>>>
>>>>> for TGL from Bspec and if we are picking up wrong revision id from drm struct that means the platform
>>>>> information obtained itself is wrong which will be a general platform problem unrelated to Gfx driver.
>>>>
>>>> Nothing else should really be a problem. We don't really use the revid
>>>> much, mostly for WAs. And if other parts of the kernel are trying to use
>>>> the SoC revid, then they are reading that info themselves, not using
>>>> something we read.
>>>>
>>>> We are simply reading the revid from hardware and using that value
>>>> without checking and that needs to change.
>>>>
>>>>
>>>>>
>>>>>>
>>>>>> I'd rather we seek for ways to either nuke the revid arrays altogether,
>>>>>> or encapsulate them within a .c file with static scope.
>>>>>
>>>>> I don't think we should nuke the revid arrays but I agree with finding a more appropriate place to
>>>>> parse the gt/display stepping info. This should be an exercise for a later patch that takes
>>>>> care of kbl,tgl and adl-s mappings.
>>>>>
>>>>>>
>>>>>> And for that .c file... the arrays are now in gt/intel_workarounds.c
>>>>>> which is a really weird place for stuff that's used for generic stepping
>>>>>> info, and particularly for *display* stepping info.
>>>>>
>>>>> I agree and we can change the approach with a different patch later.
>>>>>
>>>>>>
>>>>>> BR,
>>>>>> Jani.
>>>>>>
>>>>>>
>>>>>
>>>> _______________________________________________
>>>> Intel-gfx mailing list
>>>> Intel-gfx@lists.freedesktop.org
>>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>>
>>> --
>>> Jani Nikula, Intel Open Source Graphics Center
>
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread
* [Intel-gfx] [PATCH 03/21] drm/i915/adl_s: Add ADL-S platform info and PCI ids
2020-11-17 18:50 [Intel-gfx] [PATCH 00/21] Introduce Alderlake-S Aditya Swarup
2020-11-17 18:50 ` [Intel-gfx] [PATCH 01/21] drm/i915/dg1: Enable ports Aditya Swarup
2020-11-17 18:50 ` [Intel-gfx] [PATCH 02/21] drm/i915/tgl: Fix macros for TGL SOC based WA Aditya Swarup
@ 2020-11-17 18:50 ` Aditya Swarup
2020-11-17 19:17 ` Jani Nikula
2020-11-17 18:50 ` [Intel-gfx] [PATCH 04/21] x86/gpu: add ADL_S stolen memory support Aditya Swarup
` (22 subsequent siblings)
25 siblings, 1 reply; 56+ messages in thread
From: Aditya Swarup @ 2020-11-17 18:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi
From: Caz Yokoyama <caz.yokoyama@intel.com>
- Add the initial platform information for Alderlake-S.
- Specify ppgtt_size value
- Add dma_mask_size
- Add ADLS REVIDs
- HW tracking(Selective Update Tracking Enable) has been
removed from ADLS. Disable PSR2 till we enable software/
manual tracking.
v2:
- Add support for different ADLS SOC steppings to select
correct GT/DISP stepping based on Bspec 53655 based on
feedback from Matt Roper.(aswarup)
Bspec: 53597
Bspec: 53648
Bspec: 53655
Bspec: 48028
Bspec: 53650
BSpec: 50422
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++++++
drivers/gpu/drm/i915/i915_drv.h | 20 ++++++++++++++++++++
drivers/gpu/drm/i915/i915_pci.c | 12 ++++++++++++
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
include/drm/i915_pciids.h | 13 +++++++++++++
6 files changed, 55 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index d756155d82ea..d88d3d60fb1c 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -83,6 +83,14 @@ const struct i915_rev_steppings tgl_revids[] = {
[1] = { .gt_stepping = REVID_B0, .disp_stepping = REVID_D0 },
};
+const struct i915_rev_steppings adls_revids[] = {
+ [ADLS_REVID_A0] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_A0 },
+ [ADLS_REVID_A2] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_A2 },
+ [ADLS_REVID_B0] = { .gt_stepping = REVID_B0, .disp_stepping = REVID_B0 },
+ [ADLS_REVID_G0] = { .gt_stepping = REVID_C0, .disp_stepping = REVID_B0 },
+ [ADLS_REVID_C0] = { .gt_stepping = REVID_D0, .disp_stepping = REVID_C0 },
+};
+
static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
{
wal->name = name;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 437916aacaa6..817a5102b94f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1423,6 +1423,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
#define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
#define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
+#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv) \
@@ -1566,6 +1567,7 @@ extern const struct i915_rev_steppings kbl_revids[];
enum {
REVID_A0,
+ REVID_A2,
REVID_B0,
REVID_B1,
REVID_C0,
@@ -1607,6 +1609,24 @@ tgl_revids_get(struct drm_i915_private *dev_priv)
#define IS_DG1_REVID(p, since, until) \
(IS_DG1(p) && IS_REVID(p, since, until))
+#define ADLS_REVID_A0 0x0
+#define ADLS_REVID_A2 0x1
+#define ADLS_REVID_B0 0x4
+#define ADLS_REVID_G0 0x8
+#define ADLS_REVID_C0 0xC /*Same as H0 ADLS SOC stepping*/
+
+extern const struct i915_rev_steppings adls_revids[];
+
+#define IS_ADLS_DISP_REVID(p, since, until) \
+ (IS_ALDERLAKE_S(p) && \
+ adls_revids[INTEL_REVID(p)].disp_stepping >= (since) && \
+ adls_revids[INTEL_REVID(p)].disp_stepping <= (until))
+
+#define IS_ADLS_GT_REVID(p, since, until) \
+ (IS_ALDERLAKE_S(p) && \
+ adls_revids[INTEL_REVID(p)].gt_stepping >= (since) && \
+ adls_revids[INTEL_REVID(p)].gt_stepping <= (until))
+
#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
#define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
#define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 11fe790b1969..069ac0c28bb3 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -925,6 +925,17 @@ static const struct intel_device_info dg1_info __maybe_unused = {
.ppgtt_size = 47,
};
+static const struct intel_device_info adl_s_info = {
+ GEN12_FEATURES,
+ PLATFORM(INTEL_ALDERLAKE_S),
+ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
+ .require_force_probe = 1,
+ .display.has_psr_hw_tracking = 0,
+ .platform_engine_mask =
+ BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
+ .dma_mask_size = 46,
+};
+
#undef GEN
#undef PLATFORM
@@ -1001,6 +1012,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_JSL_IDS(&jsl_info),
INTEL_TGL_12_IDS(&tgl_info),
INTEL_RKL_IDS(&rkl_info),
+ INTEL_ADLS_IDS(&adl_s_info),
{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index e67cec8fa2aa..7310e019c611 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -66,6 +66,7 @@ static const char * const platform_names[] = {
PLATFORM_NAME(TIGERLAKE),
PLATFORM_NAME(ROCKETLAKE),
PLATFORM_NAME(DG1),
+ PLATFORM_NAME(ALDERLAKE_S),
};
#undef PLATFORM_NAME
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index d92fa041c700..360f3f1835f5 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -84,6 +84,7 @@ enum intel_platform {
INTEL_TIGERLAKE,
INTEL_ROCKETLAKE,
INTEL_DG1,
+ INTEL_ALDERLAKE_S,
INTEL_MAX_PLATFORMS
};
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 931e46191047..ae53ff8462ae 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -634,4 +634,17 @@
INTEL_VGA_DEVICE(0x4907, info), \
INTEL_VGA_DEVICE(0x4908, info)
+/* ADL-S */
+#define INTEL_ADLS_IDS(info) \
+ INTEL_VGA_DEVICE(0x4680, info), \
+ INTEL_VGA_DEVICE(0x4681, info), \
+ INTEL_VGA_DEVICE(0x4682, info), \
+ INTEL_VGA_DEVICE(0x4683, info), \
+ INTEL_VGA_DEVICE(0x4690, info), \
+ INTEL_VGA_DEVICE(0x4691, info), \
+ INTEL_VGA_DEVICE(0x4692, info), \
+ INTEL_VGA_DEVICE(0x4693, info), \
+ INTEL_VGA_DEVICE(0x4698, info), \
+ INTEL_VGA_DEVICE(0x4699, info)
+
#endif /* _I915_PCIIDS_H */
--
2.27.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH 03/21] drm/i915/adl_s: Add ADL-S platform info and PCI ids
2020-11-17 18:50 ` [Intel-gfx] [PATCH 03/21] drm/i915/adl_s: Add ADL-S platform info and PCI ids Aditya Swarup
@ 2020-11-17 19:17 ` Jani Nikula
2020-11-24 1:50 ` Aditya Swarup
0 siblings, 1 reply; 56+ messages in thread
From: Jani Nikula @ 2020-11-17 19:17 UTC (permalink / raw)
To: Aditya Swarup, intel-gfx; +Cc: Lucas De Marchi
On Tue, 17 Nov 2020, Aditya Swarup <aditya.swarup@intel.com> wrote:
> From: Caz Yokoyama <caz.yokoyama@intel.com>
>
> - Add the initial platform information for Alderlake-S.
> - Specify ppgtt_size value
> - Add dma_mask_size
> - Add ADLS REVIDs
> - HW tracking(Selective Update Tracking Enable) has been
> removed from ADLS. Disable PSR2 till we enable software/
> manual tracking.
>
> v2:
> - Add support for different ADLS SOC steppings to select
> correct GT/DISP stepping based on Bspec 53655 based on
> feedback from Matt Roper.(aswarup)
>
> Bspec: 53597
> Bspec: 53648
> Bspec: 53655
> Bspec: 48028
> Bspec: 53650
> BSpec: 50422
>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++++++
> drivers/gpu/drm/i915/i915_drv.h | 20 ++++++++++++++++++++
> drivers/gpu/drm/i915/i915_pci.c | 12 ++++++++++++
> drivers/gpu/drm/i915/intel_device_info.c | 1 +
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> include/drm/i915_pciids.h | 13 +++++++++++++
> 6 files changed, 55 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index d756155d82ea..d88d3d60fb1c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -83,6 +83,14 @@ const struct i915_rev_steppings tgl_revids[] = {
> [1] = { .gt_stepping = REVID_B0, .disp_stepping = REVID_D0 },
> };
>
> +const struct i915_rev_steppings adls_revids[] = {
> + [ADLS_REVID_A0] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_A0 },
> + [ADLS_REVID_A2] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_A2 },
> + [ADLS_REVID_B0] = { .gt_stepping = REVID_B0, .disp_stepping = REVID_B0 },
> + [ADLS_REVID_G0] = { .gt_stepping = REVID_C0, .disp_stepping = REVID_B0 },
> + [ADLS_REVID_C0] = { .gt_stepping = REVID_D0, .disp_stepping = REVID_C0 },
> +};
> +
> static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
> {
> wal->name = name;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 437916aacaa6..817a5102b94f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1423,6 +1423,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
> #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
> #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
> +#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
> #define IS_BDW_ULT(dev_priv) \
> @@ -1566,6 +1567,7 @@ extern const struct i915_rev_steppings kbl_revids[];
>
> enum {
> REVID_A0,
> + REVID_A2,
Don't the numerical values matter?
> REVID_B0,
> REVID_B1,
> REVID_C0,
> @@ -1607,6 +1609,24 @@ tgl_revids_get(struct drm_i915_private *dev_priv)
> #define IS_DG1_REVID(p, since, until) \
> (IS_DG1(p) && IS_REVID(p, since, until))
>
> +#define ADLS_REVID_A0 0x0
> +#define ADLS_REVID_A2 0x1
> +#define ADLS_REVID_B0 0x4
> +#define ADLS_REVID_G0 0x8
> +#define ADLS_REVID_C0 0xC /*Same as H0 ADLS SOC stepping*/
Why do we now have both macros and enums for this stuff?
> +
> +extern const struct i915_rev_steppings adls_revids[];
Yuck. Oh man, we really really should not have embarked on this path of
adding array externs to begin with. It should have been better
abstracted.
BR,
Jani.
> +
> +#define IS_ADLS_DISP_REVID(p, since, until) \
> + (IS_ALDERLAKE_S(p) && \
> + adls_revids[INTEL_REVID(p)].disp_stepping >= (since) && \
> + adls_revids[INTEL_REVID(p)].disp_stepping <= (until))
> +
> +#define IS_ADLS_GT_REVID(p, since, until) \
> + (IS_ALDERLAKE_S(p) && \
> + adls_revids[INTEL_REVID(p)].gt_stepping >= (since) && \
> + adls_revids[INTEL_REVID(p)].gt_stepping <= (until))
> +
> #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
> #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
> #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 11fe790b1969..069ac0c28bb3 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -925,6 +925,17 @@ static const struct intel_device_info dg1_info __maybe_unused = {
> .ppgtt_size = 47,
> };
>
> +static const struct intel_device_info adl_s_info = {
> + GEN12_FEATURES,
> + PLATFORM(INTEL_ALDERLAKE_S),
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> + .require_force_probe = 1,
> + .display.has_psr_hw_tracking = 0,
> + .platform_engine_mask =
> + BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> + .dma_mask_size = 46,
> +};
> +
> #undef GEN
> #undef PLATFORM
>
> @@ -1001,6 +1012,7 @@ static const struct pci_device_id pciidlist[] = {
> INTEL_JSL_IDS(&jsl_info),
> INTEL_TGL_12_IDS(&tgl_info),
> INTEL_RKL_IDS(&rkl_info),
> + INTEL_ADLS_IDS(&adl_s_info),
> {0, 0, 0}
> };
> MODULE_DEVICE_TABLE(pci, pciidlist);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index e67cec8fa2aa..7310e019c611 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -66,6 +66,7 @@ static const char * const platform_names[] = {
> PLATFORM_NAME(TIGERLAKE),
> PLATFORM_NAME(ROCKETLAKE),
> PLATFORM_NAME(DG1),
> + PLATFORM_NAME(ALDERLAKE_S),
> };
> #undef PLATFORM_NAME
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index d92fa041c700..360f3f1835f5 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -84,6 +84,7 @@ enum intel_platform {
> INTEL_TIGERLAKE,
> INTEL_ROCKETLAKE,
> INTEL_DG1,
> + INTEL_ALDERLAKE_S,
> INTEL_MAX_PLATFORMS
> };
>
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 931e46191047..ae53ff8462ae 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -634,4 +634,17 @@
> INTEL_VGA_DEVICE(0x4907, info), \
> INTEL_VGA_DEVICE(0x4908, info)
>
> +/* ADL-S */
> +#define INTEL_ADLS_IDS(info) \
> + INTEL_VGA_DEVICE(0x4680, info), \
> + INTEL_VGA_DEVICE(0x4681, info), \
> + INTEL_VGA_DEVICE(0x4682, info), \
> + INTEL_VGA_DEVICE(0x4683, info), \
> + INTEL_VGA_DEVICE(0x4690, info), \
> + INTEL_VGA_DEVICE(0x4691, info), \
> + INTEL_VGA_DEVICE(0x4692, info), \
> + INTEL_VGA_DEVICE(0x4693, info), \
> + INTEL_VGA_DEVICE(0x4698, info), \
> + INTEL_VGA_DEVICE(0x4699, info)
> +
> #endif /* _I915_PCIIDS_H */
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH 03/21] drm/i915/adl_s: Add ADL-S platform info and PCI ids
2020-11-17 19:17 ` Jani Nikula
@ 2020-11-24 1:50 ` Aditya Swarup
2020-11-24 9:28 ` Jani Nikula
0 siblings, 1 reply; 56+ messages in thread
From: Aditya Swarup @ 2020-11-24 1:50 UTC (permalink / raw)
To: Jani Nikula, intel-gfx; +Cc: Lucas De Marchi
On 11/17/20 11:17 AM, Jani Nikula wrote:
> On Tue, 17 Nov 2020, Aditya Swarup <aditya.swarup@intel.com> wrote:
>> From: Caz Yokoyama <caz.yokoyama@intel.com>
>>
>> - Add the initial platform information for Alderlake-S.
>> - Specify ppgtt_size value
>> - Add dma_mask_size
>> - Add ADLS REVIDs
>> - HW tracking(Selective Update Tracking Enable) has been
>> removed from ADLS. Disable PSR2 till we enable software/
>> manual tracking.
>>
>> v2:
>> - Add support for different ADLS SOC steppings to select
>> correct GT/DISP stepping based on Bspec 53655 based on
>> feedback from Matt Roper.(aswarup)
>>
>> Bspec: 53597
>> Bspec: 53648
>> Bspec: 53655
>> Bspec: 48028
>> Bspec: 53650
>> BSpec: 50422
>>
>> Cc: José Roberto de Souza <jose.souza@intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Cc: Imre Deak <imre.deak@intel.com>
>> Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
>> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++++++
>> drivers/gpu/drm/i915/i915_drv.h | 20 ++++++++++++++++++++
>> drivers/gpu/drm/i915/i915_pci.c | 12 ++++++++++++
>> drivers/gpu/drm/i915/intel_device_info.c | 1 +
>> drivers/gpu/drm/i915/intel_device_info.h | 1 +
>> include/drm/i915_pciids.h | 13 +++++++++++++
>> 6 files changed, 55 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index d756155d82ea..d88d3d60fb1c 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -83,6 +83,14 @@ const struct i915_rev_steppings tgl_revids[] = {
>> [1] = { .gt_stepping = REVID_B0, .disp_stepping = REVID_D0 },
>> };
>>
>> +const struct i915_rev_steppings adls_revids[] = {
>> + [ADLS_REVID_A0] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_A0 },
>> + [ADLS_REVID_A2] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_A2 },
>> + [ADLS_REVID_B0] = { .gt_stepping = REVID_B0, .disp_stepping = REVID_B0 },
>> + [ADLS_REVID_G0] = { .gt_stepping = REVID_C0, .disp_stepping = REVID_B0 },
>> + [ADLS_REVID_C0] = { .gt_stepping = REVID_D0, .disp_stepping = REVID_C0 },
>> +};
>> +
>> static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
>> {
>> wal->name = name;
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 437916aacaa6..817a5102b94f 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1423,6 +1423,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>> #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
>> #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
>> #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
>> +#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
>> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
>> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
>> #define IS_BDW_ULT(dev_priv) \
>> @@ -1566,6 +1567,7 @@ extern const struct i915_rev_steppings kbl_revids[];
>>
>> enum {
>> REVID_A0,
>> + REVID_A2,
>
> Don't the numerical values matter?
This is an internal mapping for Display/GT steppings and hence the values don't
matter as long as they are distinct. Value of SOC stepping matters which is declared
as a separate macro and used as an index to obtain the correct Display/GT stepping info,
to be used in conjunction
>
>> REVID_B0,
>> REVID_B1,
>> REVID_C0,
>> @@ -1607,6 +1609,24 @@ tgl_revids_get(struct drm_i915_private *dev_priv)
>> #define IS_DG1_REVID(p, since, until) \
>> (IS_DG1(p) && IS_REVID(p, since, until))
>>
>> +#define ADLS_REVID_A0 0x0
>> +#define ADLS_REVID_A2 0x1
>> +#define ADLS_REVID_B0 0x4
>> +#define ADLS_REVID_G0 0x8
>> +#define ADLS_REVID_C0 0xC /*Same as H0 ADLS SOC stepping*/
>
> Why do we now have both macros and enums for this stuff?
Because SOC steppings and disp/GT steppings are not the same anymore for ADL-S from
Bspec: 53655. What we get from drm revision id is the SOC stepping and then we need
to map it internally for display/GT steppins(hence separate enums to deal with this
as it is an internal mapping for i915 driver to be used with application of WAs based
on display stepping info)
>
>> +
>> +extern const struct i915_rev_steppings adls_revids[];
>
> Yuck. Oh man, we really really should not have embarked on this path of
> adding array externs to begin with. It should have been better
> abstracted.
I agree but can you please accept this approach for ADLS as it is following similar
convention from KBL and TGL. I can address this approach in a later patch to not use externs
for all the platforms in question.
Aditya
>
> BR,
> Jani.
>
>> +
>> +#define IS_ADLS_DISP_REVID(p, since, until) \
>> + (IS_ALDERLAKE_S(p) && \
>> + adls_revids[INTEL_REVID(p)].disp_stepping >= (since) && \
>> + adls_revids[INTEL_REVID(p)].disp_stepping <= (until))
>> +
>> +#define IS_ADLS_GT_REVID(p, since, until) \
>> + (IS_ALDERLAKE_S(p) && \
>> + adls_revids[INTEL_REVID(p)].gt_stepping >= (since) && \
>> + adls_revids[INTEL_REVID(p)].gt_stepping <= (until))
>> +
>> #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
>> #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
>> #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
>> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>> index 11fe790b1969..069ac0c28bb3 100644
>> --- a/drivers/gpu/drm/i915/i915_pci.c
>> +++ b/drivers/gpu/drm/i915/i915_pci.c
>> @@ -925,6 +925,17 @@ static const struct intel_device_info dg1_info __maybe_unused = {
>> .ppgtt_size = 47,
>> };
>>
>> +static const struct intel_device_info adl_s_info = {
>> + GEN12_FEATURES,
>> + PLATFORM(INTEL_ALDERLAKE_S),
>> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
>> + .require_force_probe = 1,
>> + .display.has_psr_hw_tracking = 0,
>> + .platform_engine_mask =
>> + BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
>> + .dma_mask_size = 46,
>> +};
>> +
>> #undef GEN
>> #undef PLATFORM
>>
>> @@ -1001,6 +1012,7 @@ static const struct pci_device_id pciidlist[] = {
>> INTEL_JSL_IDS(&jsl_info),
>> INTEL_TGL_12_IDS(&tgl_info),
>> INTEL_RKL_IDS(&rkl_info),
>> + INTEL_ADLS_IDS(&adl_s_info),
>> {0, 0, 0}
>> };
>> MODULE_DEVICE_TABLE(pci, pciidlist);
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>> index e67cec8fa2aa..7310e019c611 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -66,6 +66,7 @@ static const char * const platform_names[] = {
>> PLATFORM_NAME(TIGERLAKE),
>> PLATFORM_NAME(ROCKETLAKE),
>> PLATFORM_NAME(DG1),
>> + PLATFORM_NAME(ALDERLAKE_S),
>> };
>> #undef PLATFORM_NAME
>>
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>> index d92fa041c700..360f3f1835f5 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.h
>> +++ b/drivers/gpu/drm/i915/intel_device_info.h
>> @@ -84,6 +84,7 @@ enum intel_platform {
>> INTEL_TIGERLAKE,
>> INTEL_ROCKETLAKE,
>> INTEL_DG1,
>> + INTEL_ALDERLAKE_S,
>> INTEL_MAX_PLATFORMS
>> };
>>
>> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
>> index 931e46191047..ae53ff8462ae 100644
>> --- a/include/drm/i915_pciids.h
>> +++ b/include/drm/i915_pciids.h
>> @@ -634,4 +634,17 @@
>> INTEL_VGA_DEVICE(0x4907, info), \
>> INTEL_VGA_DEVICE(0x4908, info)
>>
>> +/* ADL-S */
>> +#define INTEL_ADLS_IDS(info) \
>> + INTEL_VGA_DEVICE(0x4680, info), \
>> + INTEL_VGA_DEVICE(0x4681, info), \
>> + INTEL_VGA_DEVICE(0x4682, info), \
>> + INTEL_VGA_DEVICE(0x4683, info), \
>> + INTEL_VGA_DEVICE(0x4690, info), \
>> + INTEL_VGA_DEVICE(0x4691, info), \
>> + INTEL_VGA_DEVICE(0x4692, info), \
>> + INTEL_VGA_DEVICE(0x4693, info), \
>> + INTEL_VGA_DEVICE(0x4698, info), \
>> + INTEL_VGA_DEVICE(0x4699, info)
>> +
>> #endif /* _I915_PCIIDS_H */
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH 03/21] drm/i915/adl_s: Add ADL-S platform info and PCI ids
2020-11-24 1:50 ` Aditya Swarup
@ 2020-11-24 9:28 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2020-11-24 9:28 UTC (permalink / raw)
To: Aditya Swarup, intel-gfx; +Cc: Lucas De Marchi
On Mon, 23 Nov 2020, Aditya Swarup <aditya.swarup@intel.com> wrote:
> On 11/17/20 11:17 AM, Jani Nikula wrote:
>> On Tue, 17 Nov 2020, Aditya Swarup <aditya.swarup@intel.com> wrote:
>>> From: Caz Yokoyama <caz.yokoyama@intel.com>
>>>
>>> - Add the initial platform information for Alderlake-S.
>>> - Specify ppgtt_size value
>>> - Add dma_mask_size
>>> - Add ADLS REVIDs
>>> - HW tracking(Selective Update Tracking Enable) has been
>>> removed from ADLS. Disable PSR2 till we enable software/
>>> manual tracking.
>>>
>>> v2:
>>> - Add support for different ADLS SOC steppings to select
>>> correct GT/DISP stepping based on Bspec 53655 based on
>>> feedback from Matt Roper.(aswarup)
>>>
>>> Bspec: 53597
>>> Bspec: 53648
>>> Bspec: 53655
>>> Bspec: 48028
>>> Bspec: 53650
>>> BSpec: 50422
>>>
>>> Cc: José Roberto de Souza <jose.souza@intel.com>
>>> Cc: Matt Roper <matthew.d.roper@intel.com>
>>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>>> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>>> Cc: Jani Nikula <jani.nikula@intel.com>
>>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>> Cc: Imre Deak <imre.deak@intel.com>
>>> Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
>>> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++++++
>>> drivers/gpu/drm/i915/i915_drv.h | 20 ++++++++++++++++++++
>>> drivers/gpu/drm/i915/i915_pci.c | 12 ++++++++++++
>>> drivers/gpu/drm/i915/intel_device_info.c | 1 +
>>> drivers/gpu/drm/i915/intel_device_info.h | 1 +
>>> include/drm/i915_pciids.h | 13 +++++++++++++
>>> 6 files changed, 55 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> index d756155d82ea..d88d3d60fb1c 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> @@ -83,6 +83,14 @@ const struct i915_rev_steppings tgl_revids[] = {
>>> [1] = { .gt_stepping = REVID_B0, .disp_stepping = REVID_D0 },
>>> };
>>>
>>> +const struct i915_rev_steppings adls_revids[] = {
>>> + [ADLS_REVID_A0] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_A0 },
>>> + [ADLS_REVID_A2] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_A2 },
>>> + [ADLS_REVID_B0] = { .gt_stepping = REVID_B0, .disp_stepping = REVID_B0 },
>>> + [ADLS_REVID_G0] = { .gt_stepping = REVID_C0, .disp_stepping = REVID_B0 },
>>> + [ADLS_REVID_C0] = { .gt_stepping = REVID_D0, .disp_stepping = REVID_C0 },
>>> +};
>>> +
>>> static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
>>> {
>>> wal->name = name;
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>> index 437916aacaa6..817a5102b94f 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -1423,6 +1423,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>>> #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
>>> #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
>>> #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
>>> +#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
>>> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
>>> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
>>> #define IS_BDW_ULT(dev_priv) \
>>> @@ -1566,6 +1567,7 @@ extern const struct i915_rev_steppings kbl_revids[];
>>>
>>> enum {
>>> REVID_A0,
>>> + REVID_A2,
>>
>> Don't the numerical values matter?
>
> This is an internal mapping for Display/GT steppings and hence the values don't
> matter as long as they are distinct. Value of SOC stepping matters which is declared
> as a separate macro and used as an index to obtain the correct Display/GT stepping info,
> to be used in conjunction
>
>>
>>> REVID_B0,
>>> REVID_B1,
>>> REVID_C0,
>>> @@ -1607,6 +1609,24 @@ tgl_revids_get(struct drm_i915_private *dev_priv)
>>> #define IS_DG1_REVID(p, since, until) \
>>> (IS_DG1(p) && IS_REVID(p, since, until))
>>>
>>> +#define ADLS_REVID_A0 0x0
>>> +#define ADLS_REVID_A2 0x1
>>> +#define ADLS_REVID_B0 0x4
>>> +#define ADLS_REVID_G0 0x8
>>> +#define ADLS_REVID_C0 0xC /*Same as H0 ADLS SOC stepping*/
>>
>> Why do we now have both macros and enums for this stuff?
>
> Because SOC steppings and disp/GT steppings are not the same anymore for ADL-S from
> Bspec: 53655. What we get from drm revision id is the SOC stepping and then we need
> to map it internally for display/GT steppins(hence separate enums to deal with this
> as it is an internal mapping for i915 driver to be used with application of WAs based
> on display stepping info)
Right. We need to hide away the platform specific "physical" steppings
in a .c file, and only have the "logical" driver steppings exposed in
the .h file.
I think the right approach for this might be to convert the physical
stepping to a logical stepping in device info init stage, and add the
logical steppings to e.g. struct intel_runtime_info. Then we can use the
*same* revid check macros everywhere.
BR,
Jani.
>
>>
>>> +
>>> +extern const struct i915_rev_steppings adls_revids[];
>>
>> Yuck. Oh man, we really really should not have embarked on this path of
>> adding array externs to begin with. It should have been better
>> abstracted.
>
> I agree but can you please accept this approach for ADLS as it is following similar
> convention from KBL and TGL. I can address this approach in a later patch to not use externs
> for all the platforms in question.
>
> Aditya
>
>>
>> BR,
>> Jani.
>>
>>> +
>>> +#define IS_ADLS_DISP_REVID(p, since, until) \
>>> + (IS_ALDERLAKE_S(p) && \
>>> + adls_revids[INTEL_REVID(p)].disp_stepping >= (since) && \
>>> + adls_revids[INTEL_REVID(p)].disp_stepping <= (until))
>>> +
>>> +#define IS_ADLS_GT_REVID(p, since, until) \
>>> + (IS_ALDERLAKE_S(p) && \
>>> + adls_revids[INTEL_REVID(p)].gt_stepping >= (since) && \
>>> + adls_revids[INTEL_REVID(p)].gt_stepping <= (until))
>>> +
>>> #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
>>> #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
>>> #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
>>> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>>> index 11fe790b1969..069ac0c28bb3 100644
>>> --- a/drivers/gpu/drm/i915/i915_pci.c
>>> +++ b/drivers/gpu/drm/i915/i915_pci.c
>>> @@ -925,6 +925,17 @@ static const struct intel_device_info dg1_info __maybe_unused = {
>>> .ppgtt_size = 47,
>>> };
>>>
>>> +static const struct intel_device_info adl_s_info = {
>>> + GEN12_FEATURES,
>>> + PLATFORM(INTEL_ALDERLAKE_S),
>>> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
>>> + .require_force_probe = 1,
>>> + .display.has_psr_hw_tracking = 0,
>>> + .platform_engine_mask =
>>> + BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
>>> + .dma_mask_size = 46,
>>> +};
>>> +
>>> #undef GEN
>>> #undef PLATFORM
>>>
>>> @@ -1001,6 +1012,7 @@ static const struct pci_device_id pciidlist[] = {
>>> INTEL_JSL_IDS(&jsl_info),
>>> INTEL_TGL_12_IDS(&tgl_info),
>>> INTEL_RKL_IDS(&rkl_info),
>>> + INTEL_ADLS_IDS(&adl_s_info),
>>> {0, 0, 0}
>>> };
>>> MODULE_DEVICE_TABLE(pci, pciidlist);
>>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>>> index e67cec8fa2aa..7310e019c611 100644
>>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>>> @@ -66,6 +66,7 @@ static const char * const platform_names[] = {
>>> PLATFORM_NAME(TIGERLAKE),
>>> PLATFORM_NAME(ROCKETLAKE),
>>> PLATFORM_NAME(DG1),
>>> + PLATFORM_NAME(ALDERLAKE_S),
>>> };
>>> #undef PLATFORM_NAME
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>>> index d92fa041c700..360f3f1835f5 100644
>>> --- a/drivers/gpu/drm/i915/intel_device_info.h
>>> +++ b/drivers/gpu/drm/i915/intel_device_info.h
>>> @@ -84,6 +84,7 @@ enum intel_platform {
>>> INTEL_TIGERLAKE,
>>> INTEL_ROCKETLAKE,
>>> INTEL_DG1,
>>> + INTEL_ALDERLAKE_S,
>>> INTEL_MAX_PLATFORMS
>>> };
>>>
>>> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
>>> index 931e46191047..ae53ff8462ae 100644
>>> --- a/include/drm/i915_pciids.h
>>> +++ b/include/drm/i915_pciids.h
>>> @@ -634,4 +634,17 @@
>>> INTEL_VGA_DEVICE(0x4907, info), \
>>> INTEL_VGA_DEVICE(0x4908, info)
>>>
>>> +/* ADL-S */
>>> +#define INTEL_ADLS_IDS(info) \
>>> + INTEL_VGA_DEVICE(0x4680, info), \
>>> + INTEL_VGA_DEVICE(0x4681, info), \
>>> + INTEL_VGA_DEVICE(0x4682, info), \
>>> + INTEL_VGA_DEVICE(0x4683, info), \
>>> + INTEL_VGA_DEVICE(0x4690, info), \
>>> + INTEL_VGA_DEVICE(0x4691, info), \
>>> + INTEL_VGA_DEVICE(0x4692, info), \
>>> + INTEL_VGA_DEVICE(0x4693, info), \
>>> + INTEL_VGA_DEVICE(0x4698, info), \
>>> + INTEL_VGA_DEVICE(0x4699, info)
>>> +
>>> #endif /* _I915_PCIIDS_H */
>>
>
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread
* [Intel-gfx] [PATCH 04/21] x86/gpu: add ADL_S stolen memory support
2020-11-17 18:50 [Intel-gfx] [PATCH 00/21] Introduce Alderlake-S Aditya Swarup
` (2 preceding siblings ...)
2020-11-17 18:50 ` [Intel-gfx] [PATCH 03/21] drm/i915/adl_s: Add ADL-S platform info and PCI ids Aditya Swarup
@ 2020-11-17 18:50 ` Aditya Swarup
2020-11-17 18:50 ` [Intel-gfx] [PATCH 05/21] drm/i915/adl_s: Add PCH support Aditya Swarup
` (21 subsequent siblings)
25 siblings, 0 replies; 56+ messages in thread
From: Aditya Swarup @ 2020-11-17 18:50 UTC (permalink / raw)
To: intel-gfx
Cc: Jani Nikula, x86, Lucas De Marchi, Ingo Molnar, Thomas Gleixner,
Borislav Petkov
From: Caz Yokoyama <caz.yokoyama@intel.com>
ADL_S re-uses the same stolen memory registers as TGL and ICL.
This patch has a dependency on:
("drm/i915/adl_s: Add ADL-S platform info and PCI ids")
Bspec: 52055
Bspec: 49589
Bspec: 49636
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: x86@kernel.org
Cc: Ingo Molnar <mingo@redhat.com>,
Cc: Thomas Gleixner <tglx@linutronix.de>,
Cc: Borislav Petkov <bp@suse.de>
Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
arch/x86/kernel/early-quirks.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index a4b5af03dcc1..6edd1e2ee8af 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -551,6 +551,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = {
INTEL_EHL_IDS(&gen11_early_ops),
INTEL_TGL_12_IDS(&gen11_early_ops),
INTEL_RKL_IDS(&gen11_early_ops),
+ INTEL_ADLS_IDS(&gen11_early_ops),
};
struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
--
2.27.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* [Intel-gfx] [PATCH 05/21] drm/i915/adl_s: Add PCH support
2020-11-17 18:50 [Intel-gfx] [PATCH 00/21] Introduce Alderlake-S Aditya Swarup
` (3 preceding siblings ...)
2020-11-17 18:50 ` [Intel-gfx] [PATCH 04/21] x86/gpu: add ADL_S stolen memory support Aditya Swarup
@ 2020-11-17 18:50 ` Aditya Swarup
2020-11-20 0:09 ` Matt Roper
2020-11-17 18:50 ` [Intel-gfx] [PATCH 06/21] drm/i915/adl_s: Add Interrupt Support Aditya Swarup
` (20 subsequent siblings)
25 siblings, 1 reply; 56+ messages in thread
From: Aditya Swarup @ 2020-11-17 18:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
Add support for Alderpoint(ADP) PCH used with Alderlake-S.
v2:
- Use drm_dbg_kms and drm_WARN_ON based on Jani's feedback.(aswarup)
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Caz Yokoyama <caz.yokoyama@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
drivers/gpu/drm/i915/intel_pch.c | 8 +++++++-
drivers/gpu/drm/i915/intel_pch.h | 3 +++
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index f31c0dabd0cc..2a6d70f247e8 100644
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@ -128,6 +128,10 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
drm_dbg_kms(&dev_priv->drm, "Found Jasper Lake PCH\n");
drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
return PCH_JSP;
+ case INTEL_PCH_ADP_DEVICE_ID_TYPE:
+ drm_dbg_kms(&dev_priv->drm, "Found Alder Lake PCH\n");
+ drm_WARN_ON(&dev_priv->drm, !IS_ALDERLAKE_S(dev_priv));
+ return PCH_ADP;
default:
return PCH_NONE;
}
@@ -155,7 +159,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
* make an educated guess as to which PCH is really there.
*/
- if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
+ if (IS_ALDERLAKE_S(dev_priv))
+ id = INTEL_PCH_ADP_DEVICE_ID_TYPE;
+ else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
else if (IS_JSL_EHL(dev_priv))
id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h
index 06d2cd50af0b..7318377503b0 100644
--- a/drivers/gpu/drm/i915/intel_pch.h
+++ b/drivers/gpu/drm/i915/intel_pch.h
@@ -26,6 +26,7 @@ enum intel_pch {
PCH_JSP, /* Jasper Lake PCH */
PCH_MCC, /* Mule Creek Canyon PCH */
PCH_TGP, /* Tiger Lake PCH */
+ PCH_ADP, /* Alder Lake PCH */
/* Fake PCHs, functionality handled on the same PCI dev */
PCH_DG1 = 1024,
@@ -53,12 +54,14 @@ enum intel_pch {
#define INTEL_PCH_TGP2_DEVICE_ID_TYPE 0x4380
#define INTEL_PCH_JSP_DEVICE_ID_TYPE 0x4D80
#define INTEL_PCH_JSP2_DEVICE_ID_TYPE 0x3880
+#define INTEL_PCH_ADP_DEVICE_ID_TYPE 0x7A80
#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
+#define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
#define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1)
#define HAS_PCH_JSP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_JSP)
#define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
--
2.27.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH 05/21] drm/i915/adl_s: Add PCH support
2020-11-17 18:50 ` [Intel-gfx] [PATCH 05/21] drm/i915/adl_s: Add PCH support Aditya Swarup
@ 2020-11-20 0:09 ` Matt Roper
0 siblings, 0 replies; 56+ messages in thread
From: Matt Roper @ 2020-11-20 0:09 UTC (permalink / raw)
To: Aditya Swarup; +Cc: Jani Nikula, intel-gfx, Lucas De Marchi
On Tue, Nov 17, 2020 at 10:50:13AM -0800, Aditya Swarup wrote:
> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
> Add support for Alderpoint(ADP) PCH used with Alderlake-S.
>
> v2:
> - Use drm_dbg_kms and drm_WARN_ON based on Jani's feedback.(aswarup)
>
This patch looks okay, so
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
but I'll have some comments on later patches which are basing south
display conditions on a check for ADL-S rather than a check for ADP.
Even if we anticipate future platforms re-using ADP and needing
different logic in those areas (like we do with TGP when paired with
RKL), I think we might want to handle that differently if/when the time
comes.
Matt
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Caz Yokoyama <caz.yokoyama@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pch.c | 8 +++++++-
> drivers/gpu/drm/i915/intel_pch.h | 3 +++
> 2 files changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
> index f31c0dabd0cc..2a6d70f247e8 100644
> --- a/drivers/gpu/drm/i915/intel_pch.c
> +++ b/drivers/gpu/drm/i915/intel_pch.c
> @@ -128,6 +128,10 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
> drm_dbg_kms(&dev_priv->drm, "Found Jasper Lake PCH\n");
> drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
> return PCH_JSP;
> + case INTEL_PCH_ADP_DEVICE_ID_TYPE:
> + drm_dbg_kms(&dev_priv->drm, "Found Alder Lake PCH\n");
> + drm_WARN_ON(&dev_priv->drm, !IS_ALDERLAKE_S(dev_priv));
> + return PCH_ADP;
> default:
> return PCH_NONE;
> }
> @@ -155,7 +159,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
> * make an educated guess as to which PCH is really there.
> */
>
> - if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
> + if (IS_ALDERLAKE_S(dev_priv))
> + id = INTEL_PCH_ADP_DEVICE_ID_TYPE;
> + else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
> id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
> else if (IS_JSL_EHL(dev_priv))
> id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
> diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h
> index 06d2cd50af0b..7318377503b0 100644
> --- a/drivers/gpu/drm/i915/intel_pch.h
> +++ b/drivers/gpu/drm/i915/intel_pch.h
> @@ -26,6 +26,7 @@ enum intel_pch {
> PCH_JSP, /* Jasper Lake PCH */
> PCH_MCC, /* Mule Creek Canyon PCH */
> PCH_TGP, /* Tiger Lake PCH */
> + PCH_ADP, /* Alder Lake PCH */
>
> /* Fake PCHs, functionality handled on the same PCI dev */
> PCH_DG1 = 1024,
> @@ -53,12 +54,14 @@ enum intel_pch {
> #define INTEL_PCH_TGP2_DEVICE_ID_TYPE 0x4380
> #define INTEL_PCH_JSP_DEVICE_ID_TYPE 0x4D80
> #define INTEL_PCH_JSP2_DEVICE_ID_TYPE 0x3880
> +#define INTEL_PCH_ADP_DEVICE_ID_TYPE 0x7A80
> #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
> #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
> #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
>
> #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
> #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
> +#define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
> #define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1)
> #define HAS_PCH_JSP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_JSP)
> #define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
> --
> 2.27.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread
* [Intel-gfx] [PATCH 06/21] drm/i915/adl_s: Add Interrupt Support
2020-11-17 18:50 [Intel-gfx] [PATCH 00/21] Introduce Alderlake-S Aditya Swarup
` (4 preceding siblings ...)
2020-11-17 18:50 ` [Intel-gfx] [PATCH 05/21] drm/i915/adl_s: Add PCH support Aditya Swarup
@ 2020-11-17 18:50 ` Aditya Swarup
2020-11-20 0:12 ` Matt Roper
2020-11-17 18:50 ` [Intel-gfx] [PATCH 07/21] drm/i915/adl_s: Add PHYs for Alderlake S Aditya Swarup
` (19 subsequent siblings)
25 siblings, 1 reply; 56+ messages in thread
From: Aditya Swarup @ 2020-11-17 18:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
ADLS follows ICP/TGP like interrupts.
v2: Use "INTEL_PCH_TYPE(dev_priv) >= PCH_ICP" of hpd_icp (Lucas)
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index dc6febc63f1c..758ed4f6c9f3 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -191,8 +191,7 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
if (HAS_PCH_DG1(dev_priv))
hpd->pch_hpd = hpd_sde_dg1;
- else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) ||
- HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
hpd->pch_hpd = hpd_icp;
else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
hpd->pch_hpd = hpd_spt;
--
2.27.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH 06/21] drm/i915/adl_s: Add Interrupt Support
2020-11-17 18:50 ` [Intel-gfx] [PATCH 06/21] drm/i915/adl_s: Add Interrupt Support Aditya Swarup
@ 2020-11-20 0:12 ` Matt Roper
0 siblings, 0 replies; 56+ messages in thread
From: Matt Roper @ 2020-11-20 0:12 UTC (permalink / raw)
To: Aditya Swarup; +Cc: Jani Nikula, intel-gfx, Lucas De Marchi
On Tue, Nov 17, 2020 at 10:50:14AM -0800, Aditya Swarup wrote:
> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
> ADLS follows ICP/TGP like interrupts.
>
> v2: Use "INTEL_PCH_TYPE(dev_priv) >= PCH_ICP" of hpd_icp (Lucas)
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index dc6febc63f1c..758ed4f6c9f3 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -191,8 +191,7 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
>
> if (HAS_PCH_DG1(dev_priv))
> hpd->pch_hpd = hpd_sde_dg1;
> - else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) ||
> - HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
> + else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> hpd->pch_hpd = hpd_icp;
> else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
> hpd->pch_hpd = hpd_spt;
> --
> 2.27.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread
* [Intel-gfx] [PATCH 07/21] drm/i915/adl_s: Add PHYs for Alderlake S
2020-11-17 18:50 [Intel-gfx] [PATCH 00/21] Introduce Alderlake-S Aditya Swarup
` (5 preceding siblings ...)
2020-11-17 18:50 ` [Intel-gfx] [PATCH 06/21] drm/i915/adl_s: Add Interrupt Support Aditya Swarup
@ 2020-11-17 18:50 ` Aditya Swarup
2020-11-20 0:20 ` Matt Roper
2020-11-17 18:50 ` [Intel-gfx] [PATCH 08/21] drm/i915/adl_s: Configure DPLL for ADL-S Aditya Swarup
` (18 subsequent siblings)
25 siblings, 1 reply; 56+ messages in thread
From: Aditya Swarup @ 2020-11-17 18:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
Alderlake-S has 5 combo phys, add reg definitions for
combo phys and update the port to phy helper for ADL-S.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++--
drivers/gpu/drm/i915/i915_reg.h | 5 ++++-
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e8874cd22abf..848bcd83b15f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7343,6 +7343,8 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
{
if (phy == PHY_NONE)
return false;
+ else if (IS_ALDERLAKE_S(dev_priv))
+ return phy <= PHY_E;
else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
return phy <= PHY_D;
else if (IS_JSL_EHL(dev_priv))
@@ -7355,7 +7357,8 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
{
- if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
+ if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv) ||
+ IS_ROCKETLAKE(dev_priv))
return false;
else if (INTEL_GEN(dev_priv) >= 12)
return phy >= PHY_D && phy <= PHY_I;
@@ -7367,7 +7370,9 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
{
- if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
+ if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
+ return PHY_B + port - PORT_TC1;
+ else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
return PHY_C + port - PORT_TC1;
else if (IS_JSL_EHL(i915) && port == PORT_D)
return PHY_A;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7ea70b7ffcc6..402ea8cd602b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1872,10 +1872,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define _ICL_COMBOPHY_B 0x6C000
#define _EHL_COMBOPHY_C 0x160000
#define _RKL_COMBOPHY_D 0x161000
+#define _ADL_COMBOPHY_E 0x16B000
+
#define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \
_ICL_COMBOPHY_B, \
_EHL_COMBOPHY_C, \
- _RKL_COMBOPHY_D)
+ _RKL_COMBOPHY_D, \
+ _ADL_COMBOPHY_E)
/* CNL/ICL Port CL_DW registers */
#define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
--
2.27.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH 07/21] drm/i915/adl_s: Add PHYs for Alderlake S
2020-11-17 18:50 ` [Intel-gfx] [PATCH 07/21] drm/i915/adl_s: Add PHYs for Alderlake S Aditya Swarup
@ 2020-11-20 0:20 ` Matt Roper
0 siblings, 0 replies; 56+ messages in thread
From: Matt Roper @ 2020-11-20 0:20 UTC (permalink / raw)
To: Aditya Swarup; +Cc: Jani Nikula, intel-gfx, Lucas De Marchi
On Tue, Nov 17, 2020 at 10:50:15AM -0800, Aditya Swarup wrote:
> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
> Alderlake-S has 5 combo phys, add reg definitions for
> combo phys and update the port to phy helper for ADL-S.
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++--
> drivers/gpu/drm/i915/i915_reg.h | 5 ++++-
> 2 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index e8874cd22abf..848bcd83b15f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7343,6 +7343,8 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
> {
> if (phy == PHY_NONE)
> return false;
> + else if (IS_ALDERLAKE_S(dev_priv))
> + return phy <= PHY_E;
> else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
> return phy <= PHY_D;
> else if (IS_JSL_EHL(dev_priv))
> @@ -7355,7 +7357,8 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
>
> bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
> {
> - if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
> + if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv) ||
> + IS_ROCKETLAKE(dev_priv))
> return false;
> else if (INTEL_GEN(dev_priv) >= 12)
> return phy >= PHY_D && phy <= PHY_I;
Since ICL/TGL are the exception rather than the rule for actually having
Type-C ports, it might make more sense to just flip this around and have
if (TGL)
...
else if (ICL)
...
else
return false;
Matt
> @@ -7367,7 +7370,9 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
>
> enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
> {
> - if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
> + if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
> + return PHY_B + port - PORT_TC1;
> + else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
> return PHY_C + port - PORT_TC1;
> else if (IS_JSL_EHL(i915) && port == PORT_D)
> return PHY_A;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7ea70b7ffcc6..402ea8cd602b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1872,10 +1872,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define _ICL_COMBOPHY_B 0x6C000
> #define _EHL_COMBOPHY_C 0x160000
> #define _RKL_COMBOPHY_D 0x161000
> +#define _ADL_COMBOPHY_E 0x16B000
> +
> #define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \
> _ICL_COMBOPHY_B, \
> _EHL_COMBOPHY_C, \
> - _RKL_COMBOPHY_D)
> + _RKL_COMBOPHY_D, \
> + _ADL_COMBOPHY_E)
>
> /* CNL/ICL Port CL_DW registers */
> #define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
> --
> 2.27.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread
* [Intel-gfx] [PATCH 08/21] drm/i915/adl_s: Configure DPLL for ADL-S
2020-11-17 18:50 [Intel-gfx] [PATCH 00/21] Introduce Alderlake-S Aditya Swarup
` (6 preceding siblings ...)
2020-11-17 18:50 ` [Intel-gfx] [PATCH 07/21] drm/i915/adl_s: Add PHYs for Alderlake S Aditya Swarup
@ 2020-11-17 18:50 ` Aditya Swarup
2020-11-17 18:50 ` [Intel-gfx] [PATCH 09/21] drm/i915/adl_s: Configure Port clock registers " Aditya Swarup
` (17 subsequent siblings)
25 siblings, 0 replies; 56+ messages in thread
From: Aditya Swarup @ 2020-11-17 18:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi
Add changes for configuring DPLL for ADL-S
- Reusing DG1 DPLL 2 & DPLL 3 for ADL-S
- Extend CNL macro to choose DPLL_ENABLE
for ADL-S.
- Select CFGCR0 and CFGCR1 for ADL-S plls.
On BSpec: 53720 PLL arrangement dig for adls:
DPLL2 cfgcr is programmed using _ADLS_DPLL3_CFGCR(0/1)
DPLL3 cfgcr is programmed using _ADLS_DPLL4_CFGCR(0/1)
v2 (Lucas): add missing update_ref_clks
Bspec: 50288
Bspec: 50289
Bspec: 49443
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 38 +++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 19 +++++++++-
2 files changed, 52 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index f6ad257a260e..529b1d569af2 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3559,7 +3559,13 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
- if (IS_DG1(dev_priv)) {
+ if (IS_ALDERLAKE_S(dev_priv)) {
+ dpll_mask =
+ BIT(DPLL_ID_DG1_DPLL3) |
+ BIT(DPLL_ID_DG1_DPLL2) |
+ BIT(DPLL_ID_ICL_DPLL1) |
+ BIT(DPLL_ID_ICL_DPLL0);
+ } else if (IS_DG1(dev_priv)) {
if (port == PORT_D || port == PORT_E) {
dpll_mask =
BIT(DPLL_ID_DG1_DPLL2) |
@@ -3865,7 +3871,10 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
if (!(val & PLL_ENABLE))
goto out;
- if (IS_DG1(dev_priv)) {
+ if (IS_ALDERLAKE_S(dev_priv)) {
+ hw_state->cfgcr0 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR0(id));
+ hw_state->cfgcr1 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR1(id));
+ } else if (IS_DG1(dev_priv)) {
hw_state->cfgcr0 = intel_de_read(dev_priv, DG1_DPLL_CFGCR0(id));
hw_state->cfgcr1 = intel_de_read(dev_priv, DG1_DPLL_CFGCR1(id));
} else if (IS_ROCKETLAKE(dev_priv)) {
@@ -3921,7 +3930,10 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
const enum intel_dpll_id id = pll->info->id;
i915_reg_t cfgcr0_reg, cfgcr1_reg;
- if (IS_DG1(dev_priv)) {
+ if (IS_ALDERLAKE_S(dev_priv)) {
+ cfgcr0_reg = ADLS_DPLL_CFGCR0(id);
+ cfgcr1_reg = ADLS_DPLL_CFGCR1(id);
+ } else if (IS_DG1(dev_priv)) {
cfgcr0_reg = DG1_DPLL_CFGCR0(id);
cfgcr1_reg = DG1_DPLL_CFGCR1(id);
} else if (IS_ROCKETLAKE(dev_priv)) {
@@ -4384,6 +4396,22 @@ static const struct intel_dpll_mgr dg1_pll_mgr = {
.dump_hw_state = icl_dump_hw_state,
};
+static const struct dpll_info adls_plls[] = {
+ { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
+ { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
+ { "DPLL 2", &combo_pll_funcs, DPLL_ID_DG1_DPLL2, 0 },
+ { "DPLL 3", &combo_pll_funcs, DPLL_ID_DG1_DPLL3, 0 },
+ { },
+};
+
+static const struct intel_dpll_mgr adls_pll_mgr = {
+ .dpll_info = adls_plls,
+ .get_dplls = icl_get_dplls,
+ .put_dplls = icl_put_dplls,
+ .update_ref_clks = icl_update_dpll_ref_clks,
+ .dump_hw_state = icl_dump_hw_state,
+};
+
/**
* intel_shared_dpll_init - Initialize shared DPLLs
* @dev: drm device
@@ -4397,7 +4425,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
const struct dpll_info *dpll_info;
int i;
- if (IS_DG1(dev_priv))
+ if (IS_ALDERLAKE_S(dev_priv))
+ dpll_mgr = &adls_pll_mgr;
+ else if (IS_DG1(dev_priv))
dpll_mgr = &dg1_pll_mgr;
else if (IS_ROCKETLAKE(dev_priv))
dpll_mgr = &rkl_pll_mgr;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 402ea8cd602b..98eefcccff95 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10343,11 +10343,14 @@ enum skl_power_gate {
/* CNL PLL */
#define DPLL0_ENABLE 0x46010
#define DPLL1_ENABLE 0x46014
+#define _ADLS_DPLL2_ENABLE 0x46018
+#define _ADLS_DPLL3_ENABLE 0x46030
#define PLL_ENABLE (1 << 31)
#define PLL_LOCK (1 << 30)
#define PLL_POWER_ENABLE (1 << 27)
#define PLL_POWER_STATE (1 << 26)
-#define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE)
+#define CNL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
+ _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE)
#define TBT_PLL_ENABLE _MMIO(0x46020)
@@ -10593,6 +10596,20 @@ enum skl_power_gate {
_DG1_DPLL2_CFGCR1, \
_DG1_DPLL3_CFGCR1)
+#define _ADLS_DPLL3_CFGCR0 0x1642C0
+#define _ADLS_DPLL4_CFGCR0 0x164294
+#define ADLS_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
+ _TGL_DPLL1_CFGCR0, \
+ _ADLS_DPLL3_CFGCR0, \
+ _ADLS_DPLL4_CFGCR0)
+
+#define _ADLS_DPLL3_CFGCR1 0x1642C4
+#define _ADLS_DPLL4_CFGCR1 0x164298
+#define ADLS_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
+ _TGL_DPLL1_CFGCR1, \
+ _ADLS_DPLL3_CFGCR1, \
+ _ADLS_DPLL4_CFGCR1)
+
#define _DKL_PHY1_BASE 0x168000
#define _DKL_PHY2_BASE 0x169000
#define _DKL_PHY3_BASE 0x16A000
--
2.27.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* [Intel-gfx] [PATCH 09/21] drm/i915/adl_s: Configure Port clock registers for ADL-S
2020-11-17 18:50 [Intel-gfx] [PATCH 00/21] Introduce Alderlake-S Aditya Swarup
` (7 preceding siblings ...)
2020-11-17 18:50 ` [Intel-gfx] [PATCH 08/21] drm/i915/adl_s: Configure DPLL for ADL-S Aditya Swarup
@ 2020-11-17 18:50 ` Aditya Swarup
2020-11-17 18:50 ` [Intel-gfx] [PATCH 10/21] drm/i915/adl_s: Add HTI support and initialize display " Aditya Swarup
` (16 subsequent siblings)
25 siblings, 0 replies; 56+ messages in thread
From: Aditya Swarup @ 2020-11-17 18:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi
Add changes to configure port clock registers for ADL-S. Combo phy port
clocks are configured by DPCLKA_CFGCR0 and DPCLKA_CFGCR1 registers.
The DDI to internal clock mappings in DPCLKA_CFGCR0 register for ADL-S
translates to
DDI A -> DDIA
DDI B -> USBC1
DDI I -> USBC2
For DPCLKA_CFGCR1
DDI J -> USBC3
DDI K -> USBC4
Bspec: 50287
Bspec: 53812
Bspec: 53723
v2: Replace I915_READ() with intel_de_read().(Jani)
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 64 +++++++++++++-------
drivers/gpu/drm/i915/display/intel_display.c | 18 +++++-
drivers/gpu/drm/i915/i915_reg.h | 23 ++++++-
3 files changed, 82 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 9d80e47e9558..6ad5ae911e94 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3094,25 +3094,30 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
- u32 val;
+ u32 val, mask, sel;
+ i915_reg_t reg;
+
+ if (IS_ALDERLAKE_S(dev_priv)) {
+ reg = ADLS_DPCLKA_CFGCR(phy);
+ mask = ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy);
+ sel = ((pll->info->id) << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
+ } else if (IS_ROCKETLAKE(dev_priv)) {
+ reg = ICL_DPCLKA_CFGCR0;
+ mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+ } else {
+ reg = ICL_DPCLKA_CFGCR0;
+ mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+ }
mutex_lock(&dev_priv->dpll.lock);
- val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
+ val = intel_de_read(dev_priv, reg);
drm_WARN_ON(&dev_priv->drm,
(val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
if (intel_phy_is_combo(dev_priv, phy)) {
- u32 mask, sel;
-
- if (IS_ROCKETLAKE(dev_priv)) {
- mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
- sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
- } else {
- mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
- sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
- }
-
/*
* Even though this register references DDIs, note that we
* want to pass the PHY rather than the port (DDI). For
@@ -3125,12 +3130,12 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
*/
val &= ~mask;
val |= sel;
- intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
- intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
+ intel_de_write(dev_priv, reg, val);
+ intel_de_posting_read(dev_priv, reg);
}
val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
- intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
+ intel_de_write(dev_priv, reg, val);
mutex_unlock(&dev_priv->dpll.lock);
}
@@ -3156,9 +3161,17 @@ static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
mutex_lock(&dev_priv->dpll.lock);
- val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
+ if (IS_ALDERLAKE_S(dev_priv))
+ val = intel_de_read(dev_priv, ADLS_DPCLKA_CFGCR(phy));
+ else
+ val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
+
val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
- intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
+
+ if (IS_ALDERLAKE_S(dev_priv))
+ intel_de_write(dev_priv, ADLS_DPCLKA_CFGCR(phy), val);
+ else
+ intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
mutex_unlock(&dev_priv->dpll.lock);
}
@@ -3198,13 +3211,19 @@ static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
u32 port_mask, bool ddi_clk_needed)
{
enum port port;
+ bool ddi_clk_off;
u32 val;
- val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
for_each_port_masked(port, port_mask) {
enum phy phy = intel_port_to_phy(dev_priv, port);
- bool ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv,
- phy);
+
+ if (IS_ALDERLAKE_S(dev_priv))
+ val = intel_de_read(dev_priv, ADLS_DPCLKA_CFGCR(phy));
+ else
+ val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
+
+ ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv,
+ phy);
if (ddi_clk_needed == !ddi_clk_off)
continue;
@@ -3220,7 +3239,10 @@ static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
"PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
phy_name(phy));
val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
- intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
+ if (IS_ALDERLAKE_S(dev_priv))
+ intel_de_write(dev_priv, ADLS_DPCLKA_CFGCR(phy), val);
+ else
+ intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 848bcd83b15f..dcb70efbfa3b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10940,6 +10940,20 @@ static int hsw_crtc_compute_clock(struct intel_crtc *crtc,
return 0;
}
+static void adls_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
+ struct intel_crtc_state *pipe_config)
+{
+ enum phy phy = intel_port_to_phy(dev_priv, port);
+ enum intel_dpll_id id;
+ u32 val;
+
+ val = intel_de_read(dev_priv, ADLS_DPCLKA_CFGCR(phy));
+ val &= ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy);
+ id = val >> ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy);
+
+ pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
+}
+
static void dg1_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
struct intel_crtc_state *pipe_config)
{
@@ -11311,7 +11325,9 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
}
- if (IS_DG1(dev_priv))
+ if (IS_ALDERLAKE_S(dev_priv))
+ adls_get_ddi_pll(dev_priv, port, pipe_config);
+ else if (IS_DG1(dev_priv))
dg1_get_ddi_pll(dev_priv, port, pipe_config);
else if (INTEL_GEN(dev_priv) >= 11)
icl_get_ddi_pll(dev_priv, port, pipe_config);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 98eefcccff95..5416d04373ae 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10305,7 +10305,7 @@ enum skl_power_gate {
/* ICL Clocks */
#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
-#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24))
+#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5))
#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \
(tc_port) + 12 : \
@@ -10340,6 +10340,27 @@ enum skl_power_gate {
#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_DPLL_MAP(clk_sel, phy) \
(((clk_sel) >> DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) + _DG1_PHY_DPLL_MAP(phy))
+/* ADLS Clocks */
+#define _ADLS_DPCLKA_CFGCR0 0x164280
+#define _ADLS_DPCLKA_CFGCR1 0x1642BC
+#define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3, \
+ _ADLS_DPCLKA_CFGCR0, \
+ _ADLS_DPCLKA_CFGCR1)
+#define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) * 2)
+/* ADLS DPCLKA_CFGCR0 DDI mask */
+#define ADLS_DPCLKA_DDII_SEL_MASK REG_GENMASK(5, 4)
+#define ADLS_DPCLKA_DDIB_SEL_MASK REG_GENMASK(3, 2)
+#define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0)
+/* ADLS DPCLKA_CFGCR1 DDI mask */
+#define ADLS_DPCLKA_DDIK_SEL_MASK REG_GENMASK(3, 2)
+#define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0)
+#define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \
+ ADLS_DPCLKA_DDIA_SEL_MASK, \
+ ADLS_DPCLKA_DDIB_SEL_MASK, \
+ ADLS_DPCLKA_DDII_SEL_MASK, \
+ ADLS_DPCLKA_DDIJ_SEL_MASK, \
+ ADLS_DPCLKA_DDIK_SEL_MASK)
+
/* CNL PLL */
#define DPLL0_ENABLE 0x46010
#define DPLL1_ENABLE 0x46014
--
2.27.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* [Intel-gfx] [PATCH 10/21] drm/i915/adl_s: Add HTI support and initialize display for ADL-S
2020-11-17 18:50 [Intel-gfx] [PATCH 00/21] Introduce Alderlake-S Aditya Swarup
` (8 preceding siblings ...)
2020-11-17 18:50 ` [Intel-gfx] [PATCH 09/21] drm/i915/adl_s: Configure Port clock registers " Aditya Swarup
@ 2020-11-17 18:50 ` Aditya Swarup
2020-11-20 0:27 ` Matt Roper
2020-11-17 18:50 ` [Intel-gfx] [PATCH 11/21] drm/i915/adl_s: Add adl-s ddc pin mapping Aditya Swarup
` (15 subsequent siblings)
25 siblings, 1 reply; 56+ messages in thread
From: Aditya Swarup @ 2020-11-17 18:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi
Initialize display outputs and add HTI support for ADL-S. ADL-S has 5
display outputs -> 1 eDP, 2 HDMI and 2 DP++ outputs.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 8 +++++++-
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 2 +-
3 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index dcb70efbfa3b..db8ba5e297ff 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17261,7 +17261,13 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
+ if (IS_ALDERLAKE_S(dev_priv)) {
+ intel_ddi_init(dev_priv, PORT_A);
+ intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */
+ intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */
+ intel_ddi_init(dev_priv, PORT_F); /* DDI TC3 */
+ intel_ddi_init(dev_priv, PORT_G); /* DDI TC4 */
+ } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_TC1);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 069ac0c28bb3..26e4bf8bb4ef 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -930,6 +930,7 @@ static const struct intel_device_info adl_s_info = {
PLATFORM(INTEL_ALDERLAKE_S),
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
.require_force_probe = 1,
+ .display.has_hti = 1,
.display.has_psr_hw_tracking = 0,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5416d04373ae..4c8d0d84af6a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2928,7 +2928,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
#define HDPORT_STATE _MMIO(0x45050)
-#define HDPORT_DPLL_USED_MASK REG_GENMASK(14, 12)
+#define HDPORT_DPLL_USED_MASK REG_GENMASK(15, 12)
#define HDPORT_PHY_USED_DP(phy) REG_BIT(2 * (phy) + 2)
#define HDPORT_PHY_USED_HDMI(phy) REG_BIT(2 * (phy) + 1)
#define HDPORT_ENABLED REG_BIT(0)
--
2.27.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH 10/21] drm/i915/adl_s: Add HTI support and initialize display for ADL-S
2020-11-17 18:50 ` [Intel-gfx] [PATCH 10/21] drm/i915/adl_s: Add HTI support and initialize display " Aditya Swarup
@ 2020-11-20 0:27 ` Matt Roper
0 siblings, 0 replies; 56+ messages in thread
From: Matt Roper @ 2020-11-20 0:27 UTC (permalink / raw)
To: Aditya Swarup; +Cc: Jani Nikula, intel-gfx, Lucas De Marchi
On Tue, Nov 17, 2020 at 10:50:18AM -0800, Aditya Swarup wrote:
> Initialize display outputs and add HTI support for ADL-S. ADL-S has 5
> display outputs -> 1 eDP, 2 HDMI and 2 DP++ outputs.
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 8 +++++++-
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 3 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index dcb70efbfa3b..db8ba5e297ff 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -17261,7 +17261,13 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
> if (!HAS_DISPLAY(dev_priv))
> return;
>
> - if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
> + if (IS_ALDERLAKE_S(dev_priv)) {
> + intel_ddi_init(dev_priv, PORT_A);
> + intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */
> + intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */
> + intel_ddi_init(dev_priv, PORT_F); /* DDI TC3 */
> + intel_ddi_init(dev_priv, PORT_G); /* DDI TC4 */
> + } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
> intel_ddi_init(dev_priv, PORT_A);
> intel_ddi_init(dev_priv, PORT_B);
> intel_ddi_init(dev_priv, PORT_TC1);
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 069ac0c28bb3..26e4bf8bb4ef 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -930,6 +930,7 @@ static const struct intel_device_info adl_s_info = {
> PLATFORM(INTEL_ALDERLAKE_S),
> .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> .require_force_probe = 1,
> + .display.has_hti = 1,
> .display.has_psr_hw_tracking = 0,
> .platform_engine_mask =
> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
This part should probably just go in the patch that added the initial
platform definition.
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5416d04373ae..4c8d0d84af6a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2928,7 +2928,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
>
> #define HDPORT_STATE _MMIO(0x45050)
> -#define HDPORT_DPLL_USED_MASK REG_GENMASK(14, 12)
> +#define HDPORT_DPLL_USED_MASK REG_GENMASK(15, 12)
This doesn't seem like it belongs in this patch. The DPLL patch might
be a better match for it?
Matt
> #define HDPORT_PHY_USED_DP(phy) REG_BIT(2 * (phy) + 2)
> #define HDPORT_PHY_USED_HDMI(phy) REG_BIT(2 * (phy) + 1)
> #define HDPORT_ENABLED REG_BIT(0)
> --
> 2.27.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread
* [Intel-gfx] [PATCH 11/21] drm/i915/adl_s: Add adl-s ddc pin mapping
2020-11-17 18:50 [Intel-gfx] [PATCH 00/21] Introduce Alderlake-S Aditya Swarup
` (9 preceding siblings ...)
2020-11-17 18:50 ` [Intel-gfx] [PATCH 10/21] drm/i915/adl_s: Add HTI support and initialize display " Aditya Swarup
@ 2020-11-17 18:50 ` Aditya Swarup
2020-11-20 0:33 ` Matt Roper
2020-11-17 18:50 ` [Intel-gfx] [PATCH 12/21] drm/i915/adl_s: Add vbt port and aux channel settings for adls Aditya Swarup
` (14 subsequent siblings)
25 siblings, 1 reply; 56+ messages in thread
From: Aditya Swarup @ 2020-11-17 18:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi
ADL-S requires TC pins to set up ddc for Combo PHY B, C, D and E.
Combo PHY A still uses the old ddc pin mapping.
From VBT, ddc pin info suggests the following mapping:
VBT DRIVER
DDI B->ddc_pin=2 should translate to PORT_D->0x9
DDI C->ddc_pin=3 should translate to PORT_E->0xa
DDI D->ddc_pin=4 should translate to PORT_F->0xb
DDI E->ddc_pin=5 should translate to PORT_G->0xc
Adding pin map to facilitate this translation as we cannot use existing
icl ddc pin map due to conflict with DDI B and DDI C info.
Bspec:20124
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 13 +++++++++++-
drivers/gpu/drm/i915/display/intel_hdmi.c | 20 ++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 4 ++++
3 files changed, 35 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 4cc949b228f2..716a15f87632 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1623,12 +1623,23 @@ static const u8 icp_ddc_pin_map[] = {
[TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP,
};
+static const u8 adls_ddc_pin_map[] = {
+ [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
+ [ADLS_DDC_BUS_PORT_TC1] = GMBUS_PIN_9_TC1_ICP,
+ [ADLS_DDC_BUS_PORT_TC2] = GMBUS_PIN_10_TC2_ICP,
+ [ADLS_DDC_BUS_PORT_TC3] = GMBUS_PIN_11_TC3_ICP,
+ [ADLS_DDC_BUS_PORT_TC4] = GMBUS_PIN_12_TC4_ICP,
+};
+
static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
{
const u8 *ddc_pin_map;
int n_entries;
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
+ if (IS_ALDERLAKE_S(dev_priv)) {
+ ddc_pin_map = adls_ddc_pin_map;
+ n_entries = ARRAY_SIZE(adls_ddc_pin_map);
+ } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
return vbt_pin;
} else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
ddc_pin_map = icp_ddc_pin_map;
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index f90838bc74fb..8fdf0623d663 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3145,6 +3145,22 @@ static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
return intel_port_to_phy(dev_priv, port) + 1;
}
+static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
+{
+ enum phy phy = intel_port_to_phy(dev_priv, port);
+
+ WARN_ON(port == PORT_B || port == PORT_C);
+
+ /*
+ * Pin mapping for ADL-S requires TC pins for all combo phy outputs
+ * except first combo output.
+ */
+ if (IS_ALDERLAKE_S(dev_priv) && phy >= PHY_B)
+ return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
+
+ return GMBUS_PIN_1_BXT + phy;
+}
+
static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
enum port port)
{
@@ -3182,7 +3198,9 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
return ddc_pin;
}
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ if (IS_ALDERLAKE_S(dev_priv))
+ ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
else if (IS_ROCKETLAKE(dev_priv))
ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 49b4b5fca941..32d1b4f05760 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -325,6 +325,10 @@ enum vbt_gmbus_ddi {
ICL_DDC_BUS_PORT_4,
TGL_DDC_BUS_PORT_5,
TGL_DDC_BUS_PORT_6,
+ ADLS_DDC_BUS_PORT_TC1 = 0x2,
+ ADLS_DDC_BUS_PORT_TC2,
+ ADLS_DDC_BUS_PORT_TC3,
+ ADLS_DDC_BUS_PORT_TC4
};
#define DP_AUX_A 0x40
--
2.27.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH 11/21] drm/i915/adl_s: Add adl-s ddc pin mapping
2020-11-17 18:50 ` [Intel-gfx] [PATCH 11/21] drm/i915/adl_s: Add adl-s ddc pin mapping Aditya Swarup
@ 2020-11-20 0:33 ` Matt Roper
0 siblings, 0 replies; 56+ messages in thread
From: Matt Roper @ 2020-11-20 0:33 UTC (permalink / raw)
To: Aditya Swarup; +Cc: Jani Nikula, intel-gfx, Lucas De Marchi
On Tue, Nov 17, 2020 at 10:50:19AM -0800, Aditya Swarup wrote:
> ADL-S requires TC pins to set up ddc for Combo PHY B, C, D and E.
> Combo PHY A still uses the old ddc pin mapping.
>
> From VBT, ddc pin info suggests the following mapping:
> VBT DRIVER
> DDI B->ddc_pin=2 should translate to PORT_D->0x9
> DDI C->ddc_pin=3 should translate to PORT_E->0xa
> DDI D->ddc_pin=4 should translate to PORT_F->0xb
> DDI E->ddc_pin=5 should translate to PORT_G->0xc
>
> Adding pin map to facilitate this translation as we cannot use existing
> icl ddc pin map due to conflict with DDI B and DDI C info.
>
> Bspec:20124
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 13 +++++++++++-
> drivers/gpu/drm/i915/display/intel_hdmi.c | 20 ++++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_vbt_defs.h | 4 ++++
> 3 files changed, 35 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index 4cc949b228f2..716a15f87632 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -1623,12 +1623,23 @@ static const u8 icp_ddc_pin_map[] = {
> [TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP,
> };
>
> +static const u8 adls_ddc_pin_map[] = {
> + [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
> + [ADLS_DDC_BUS_PORT_TC1] = GMBUS_PIN_9_TC1_ICP,
> + [ADLS_DDC_BUS_PORT_TC2] = GMBUS_PIN_10_TC2_ICP,
> + [ADLS_DDC_BUS_PORT_TC3] = GMBUS_PIN_11_TC3_ICP,
> + [ADLS_DDC_BUS_PORT_TC4] = GMBUS_PIN_12_TC4_ICP,
> +};
> +
> static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
> {
> const u8 *ddc_pin_map;
> int n_entries;
>
> - if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
> + if (IS_ALDERLAKE_S(dev_priv)) {
As I mentioned on an earlier patch, these kind of conditions should
probably just be HAS_PCH_ADP().
It's possible that in the future we'll run into a pairing of ADP with a
different GPU that should be handled in a special manner (like we have
with RKL+TGP differing from TGL+TGP), but the first platform should
still stay the "default" for conditions if that happens.
Alternatively if we wind up with another variant of ADP in the future
that behaves differently in general, then presumably it would also have
a different device ID and we could just treat them separately as
HAS_PCH_ADP_S() vs HAS_PCH_ADP_X() or whatever.
But we can cross that bridge if/when we get to it. For now it's
probably cleanest to just make this condition (and others like it later)
be HAS_PCH_ADP().
Matt
> + ddc_pin_map = adls_ddc_pin_map;
> + n_entries = ARRAY_SIZE(adls_ddc_pin_map);
> + } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
> return vbt_pin;
> } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
> ddc_pin_map = icp_ddc_pin_map;
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index f90838bc74fb..8fdf0623d663 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -3145,6 +3145,22 @@ static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
> return intel_port_to_phy(dev_priv, port) + 1;
> }
>
> +static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
> +{
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> +
> + WARN_ON(port == PORT_B || port == PORT_C);
> +
> + /*
> + * Pin mapping for ADL-S requires TC pins for all combo phy outputs
> + * except first combo output.
> + */
> + if (IS_ALDERLAKE_S(dev_priv) && phy >= PHY_B)
> + return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
> +
> + return GMBUS_PIN_1_BXT + phy;
> +}
> +
> static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
> enum port port)
> {
> @@ -3182,7 +3198,9 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
> return ddc_pin;
> }
>
> - if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> + if (IS_ALDERLAKE_S(dev_priv))
> + ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
> + else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
> else if (IS_ROCKETLAKE(dev_priv))
> ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index 49b4b5fca941..32d1b4f05760 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -325,6 +325,10 @@ enum vbt_gmbus_ddi {
> ICL_DDC_BUS_PORT_4,
> TGL_DDC_BUS_PORT_5,
> TGL_DDC_BUS_PORT_6,
> + ADLS_DDC_BUS_PORT_TC1 = 0x2,
> + ADLS_DDC_BUS_PORT_TC2,
> + ADLS_DDC_BUS_PORT_TC3,
> + ADLS_DDC_BUS_PORT_TC4
> };
>
> #define DP_AUX_A 0x40
> --
> 2.27.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread
* [Intel-gfx] [PATCH 12/21] drm/i915/adl_s: Add vbt port and aux channel settings for adls
2020-11-17 18:50 [Intel-gfx] [PATCH 00/21] Introduce Alderlake-S Aditya Swarup
` (10 preceding siblings ...)
2020-11-17 18:50 ` [Intel-gfx] [PATCH 11/21] drm/i915/adl_s: Add adl-s ddc pin mapping Aditya Swarup
@ 2020-11-17 18:50 ` Aditya Swarup
2020-11-17 18:50 ` [Intel-gfx] [PATCH 13/21] drm/i915/adl_s: Update combo PHY master/slave relationships Aditya Swarup
` (13 subsequent siblings)
25 siblings, 0 replies; 56+ messages in thread
From: Aditya Swarup @ 2020-11-17 18:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi
- ADL-S driver internal mapping uses PORT D, E, F, G for Combo phy B, C, D and E.
- Add ADLS specific port mappings for vbt port dvo settings.
- Select appropriate AUX CH specific to ADLS based on port mapping.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 57 ++++++++++++++++++-----
1 file changed, 46 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 716a15f87632..9cc69fdd33ea 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1709,8 +1709,26 @@ static enum port dvo_port_to_port(struct drm_i915_private *dev_priv,
[PORT_TC1] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
[PORT_TC2] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
};
+ /*
+ * Alderlake S ports used in the driver are PORT_A, PORT_D, PORT_E,
+ * PORT_F and PORT_G, we need to map that to correct VBT sections.
+ */
+ static const int adls_port_mapping[][3] = {
+ [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
+ [PORT_B] = { -1 },
+ [PORT_C] = { -1 },
+ [PORT_TC1] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
+ [PORT_TC2] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
+ [PORT_TC3] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
+ [PORT_TC4] = { DVO_PORT_HDMIE, DVO_PORT_DPE, -1 },
+ };
- if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
+ if (IS_ALDERLAKE_S(dev_priv))
+ return __dvo_port_to_port(ARRAY_SIZE(adls_port_mapping),
+ ARRAY_SIZE(adls_port_mapping[0]),
+ adls_port_mapping,
+ dvo_port);
+ else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping),
ARRAY_SIZE(rkl_port_mapping[0]),
rkl_port_mapping,
@@ -2667,27 +2685,44 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
return aux_ch;
}
+ /*
+ * RKL/DG1 VBT uses PHY based mapping. Combo PHYs A,B,C,D
+ * map to DDI A,B,TC1,TC2 respectively.
+ *
+ * ADL-S VBT uses PHY based mapping. Combo PHYs A,B,C,D,E
+ * map to DDI A,TC1,TC2,TC3,TC4 respectively.
+ */
switch (info->alternate_aux_channel) {
case DP_AUX_A:
aux_ch = AUX_CH_A;
break;
case DP_AUX_B:
- aux_ch = AUX_CH_B;
+ if (IS_ALDERLAKE_S(dev_priv))
+ aux_ch = AUX_CH_USBC1;
+ else
+ aux_ch = AUX_CH_B;
break;
case DP_AUX_C:
- /*
- * RKL/DG1 VBT uses PHY based mapping. Combo PHYs A,B,C,D
- * map to DDI A,B,TC1,TC2 respectively.
- */
- aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
- AUX_CH_USBC1 : AUX_CH_C;
+ if (IS_ALDERLAKE_S(dev_priv))
+ aux_ch = AUX_CH_USBC2;
+ else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
+ aux_ch = AUX_CH_USBC1;
+ else
+ aux_ch = AUX_CH_C;
break;
case DP_AUX_D:
- aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
- AUX_CH_USBC2 : AUX_CH_D;
+ if (IS_ALDERLAKE_S(dev_priv))
+ aux_ch = AUX_CH_USBC3;
+ else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
+ aux_ch = AUX_CH_USBC2;
+ else
+ aux_ch = AUX_CH_D;
break;
case DP_AUX_E:
- aux_ch = AUX_CH_E;
+ if (IS_ALDERLAKE_S(dev_priv))
+ aux_ch = AUX_CH_USBC4;
+ else
+ aux_ch = AUX_CH_E;
break;
case DP_AUX_F:
aux_ch = AUX_CH_F;
--
2.27.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* [Intel-gfx] [PATCH 13/21] drm/i915/adl_s: Update combo PHY master/slave relationships
2020-11-17 18:50 [Intel-gfx] [PATCH 00/21] Introduce Alderlake-S Aditya Swarup
` (11 preceding siblings ...)
2020-11-17 18:50 ` [Intel-gfx] [PATCH 12/21] drm/i915/adl_s: Add vbt port and aux channel settings for adls Aditya Swarup
@ 2020-11-17 18:50 ` Aditya Swarup
2020-11-25 23:38 ` Srivatsa, Anusha
2020-11-17 18:50 ` [Intel-gfx] [PATCH 14/21] drm/i915/adl_s: Update PHY_MISC programming Aditya Swarup
` (12 subsequent siblings)
25 siblings, 1 reply; 56+ messages in thread
From: Aditya Swarup @ 2020-11-17 18:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi
From: Matt Roper <matthew.d.roper@intel.com>
ADL-S switches up which PHYs are considered a master to other PHYs;
PHY-C is no longer a master, but PHY-D is now.
Bspec: 49291
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
drivers/gpu/drm/i915/display/intel_combo_phy.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index d5ad61e4083e..55d2d2d9efbb 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -246,14 +246,21 @@ static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy)
* RKL,DG1:
* A(master) -> B(slave)
* C(master) -> D(slave)
+ * ADL-S:
+ * A(master) -> B(slave), C(slave)
+ * D(master) -> E(slave)
*
* We must set the IREFGEN bit for any PHY acting as a master
* to another PHY.
*/
- if ((IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) && phy == PHY_C)
+ if (phy == PHY_A)
return true;
+ else if (IS_ALDERLAKE_S(dev_priv))
+ return phy == PHY_D;
+ else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
+ return phy == PHY_C;
- return phy == PHY_A;
+ return false;
}
static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
--
2.27.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH 13/21] drm/i915/adl_s: Update combo PHY master/slave relationships
2020-11-17 18:50 ` [Intel-gfx] [PATCH 13/21] drm/i915/adl_s: Update combo PHY master/slave relationships Aditya Swarup
@ 2020-11-25 23:38 ` Srivatsa, Anusha
0 siblings, 0 replies; 56+ messages in thread
From: Srivatsa, Anusha @ 2020-11-25 23:38 UTC (permalink / raw)
To: Swarup, Aditya, intel-gfx; +Cc: Nikula, Jani, De Marchi, Lucas
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Aditya Swarup
> Sent: Tuesday, November 17, 2020 10:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>
> Subject: [Intel-gfx] [PATCH 13/21] drm/i915/adl_s: Update combo PHY
> master/slave relationships
>
> From: Matt Roper <matthew.d.roper@intel.com>
>
> ADL-S switches up which PHYs are considered a master to other PHYs; PHY-C
> is no longer a master, but PHY-D is now.
>
> Bspec: 49291
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_combo_phy.c | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> index d5ad61e4083e..55d2d2d9efbb 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> @@ -246,14 +246,21 @@ static bool phy_is_master(struct
> drm_i915_private *dev_priv, enum phy phy)
> * RKL,DG1:
> * A(master) -> B(slave)
> * C(master) -> D(slave)
> + * ADL-S:
> + * A(master) -> B(slave), C(slave)
> + * D(master) -> E(slave)
> *
> * We must set the IREFGEN bit for any PHY acting as a master
> * to another PHY.
> */
> - if ((IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) && phy ==
> PHY_C)
> + if (phy == PHY_A)
> return true;
> + else if (IS_ALDERLAKE_S(dev_priv))
> + return phy == PHY_D;
> + else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
> + return phy == PHY_C;
>
> - return phy == PHY_A;
> + return false;
> }
>
> static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
> --
> 2.27.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread
* [Intel-gfx] [PATCH 14/21] drm/i915/adl_s: Update PHY_MISC programming
2020-11-17 18:50 [Intel-gfx] [PATCH 00/21] Introduce Alderlake-S Aditya Swarup
` (12 preceding siblings ...)
2020-11-17 18:50 ` [Intel-gfx] [PATCH 13/21] drm/i915/adl_s: Update combo PHY master/slave relationships Aditya Swarup
@ 2020-11-17 18:50 ` Aditya Swarup
2020-11-17 18:50 ` [Intel-gfx] [PATCH 15/21] drm/i915/adl_s: Add display, gt, ctx and ADL-S Aditya Swarup
` (11 subsequent siblings)
25 siblings, 0 replies; 56+ messages in thread
From: Aditya Swarup @ 2020-11-17 18:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi
From: Matt Roper <matthew.d.roper@intel.com>
ADL-S switches up which PHYs are considered a master to other PHYs;
PHY-C is no longer a master, but PHY-D is now.
Bspec: 49291
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
drivers/gpu/drm/i915/display/intel_combo_phy.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 55d2d2d9efbb..5a71adbd7a4d 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -187,10 +187,16 @@ static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)
* Some platforms only expect PHY_MISC to be programmed for PHY-A and
* PHY-B and may not even have instances of the register for the
* other combo PHY's.
+ *
+ * ADL-S technically has three instances of PHY_MISC, but only requires
+ * that we program it for PHY A.
*/
- if (IS_JSL_EHL(i915) ||
- IS_ROCKETLAKE(i915) ||
- IS_DG1(i915))
+
+ if (IS_ALDERLAKE_S(i915))
+ return phy == PHY_A;
+ else if (IS_JSL_EHL(i915) ||
+ IS_ROCKETLAKE(i915) ||
+ IS_DG1(i915))
return phy < PHY_C;
return true;
--
2.27.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* [Intel-gfx] [PATCH 15/21] drm/i915/adl_s: Add display, gt, ctx and ADL-S
2020-11-17 18:50 [Intel-gfx] [PATCH 00/21] Introduce Alderlake-S Aditya Swarup
` (13 preceding siblings ...)
2020-11-17 18:50 ` [Intel-gfx] [PATCH 14/21] drm/i915/adl_s: Update PHY_MISC programming Aditya Swarup
@ 2020-11-17 18:50 ` Aditya Swarup
2020-12-01 18:46 ` Srivatsa, Anusha
2020-11-17 18:50 ` [Intel-gfx] [PATCH 16/21] drm/i915/adl_s: MCHBAR memory info registers are moved Aditya Swarup
` (10 subsequent siblings)
25 siblings, 1 reply; 56+ messages in thread
From: Aditya Swarup @ 2020-11-17 18:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi
- Inherit the gen12 workarounds.
- Add placeholders to setup GT WA.
- Extend permanent driver WA Wa_1409767108 to adl-s and
Wa_14010685332 to adl-s.
- Extend permanent driver WA Wa_1606054188 to adl-s
- Add Wa_14011765242 for adl-s A0 stepping.
v2:
- Extend Wa_14010919138 and Wa_14010229206 to ADL-S (Madhumitha)
- Extend Wa_22010271021 to ADLS (cyokoyam)
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
.../drm/i915/display/intel_display_power.c | 7 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 4 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 91 +++++++++++++------
drivers/gpu/drm/i915/intel_device_info.c | 6 +-
4 files changed, 72 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 06c036e2092c..8b163d804a41 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5282,9 +5282,10 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask;
int config, i;
- if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
+ if (IS_ALDERLAKE_S(dev_priv) ||
+ IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_B0))
- /* Wa_1409767108:tgl,dg1 */
+ /* Wa_1409767108:tgl,dg1,adl-s */
table = wa_1409767108_buddy_page_masks;
else
table = tgl_buddy_page_masks;
@@ -5322,7 +5323,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
- /* Wa_14011294188:ehl,jsl,tgl,rkl */
+ /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */
if (INTEL_PCH_TYPE(dev_priv) >= PCH_JSP &&
INTEL_PCH_TYPE(dev_priv) < PCH_DG1)
intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0,
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index f7da4a56054e..1e954e2928fe 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2359,8 +2359,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
return -EINVAL;
}
- /* Wa_1606054188:tgl */
- if (IS_TIGERLAKE(dev_priv) &&
+ /* Wa_1606054188:tgl,adl-s */
+ if ((IS_ALDERLAKE_S(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE &&
intel_format_is_p01x(fb->format->format)) {
drm_dbg_kms(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index d88d3d60fb1c..e6f149bd537f 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -664,22 +664,6 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
gen12_ctx_workarounds_init(engine, wal);
-
- /*
- * Wa_1604555607:tgl,rkl
- *
- * Note that the implementation of this workaround is further modified
- * according to the FF_MODE2 guidance given by Wa_1608008084:gen12.
- * FF_MODE2 register will return the wrong value when read. The default
- * value for this register is zero for all fields and there are no bit
- * masks. So instead of doing a RMW we should just write the GS Timer
- * and TDS timer values for Wa_1604555607 and Wa_16011163337.
- */
- wa_add(wal,
- FF_MODE2,
- FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK,
- FF_MODE2_GS_TIMER_224 | FF_MODE2_TDS_TIMER_128,
- 0);
}
static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
@@ -696,6 +680,12 @@ static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE);
}
+static void adls_ctx_workarounds_init(struct intel_engine_cs *engine,
+ struct i915_wa_list *wal)
+{
+ gen12_ctx_workarounds_init(engine, wal);
+}
+
static void
__intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
struct i915_wa_list *wal,
@@ -708,7 +698,31 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
wa_init_start(wal, name, engine->name);
- if (IS_DG1(i915))
+ if (INTEL_GEN(i915) >= 12) {
+ /*
+ * This setting isn't actually a workaround, but is a general
+ * tuning setting that needs to be programmed on all platforms
+ * gen12+. Although some platforms also refer to this setting
+ * as Wa_1604555607, we need to program it even on platforms that
+ * don't explicitly list that workaround.
+ *
+ * Note that the implementation is further modified according
+ * to the FF_MODE2 guidance given by Wa_1608008084:gen12.
+ * FF_MODE2 register will return the wrong value when read.
+ * The default value for this register is zero for all fields
+ * and there are no bit masks. So instead of doing a RMW, we
+ * should just write the value directly.
+ */
+ wa_add(wal,
+ FF_MODE2,
+ FF_MODE2_TDS_TIMER_MASK,
+ FF_MODE2_TDS_TIMER_128,
+ 0);
+ }
+
+ if (IS_ALDERLAKE_S(i915))
+ adls_ctx_workarounds_init(engine, wal);
+ else if (IS_DG1(i915))
dg1_ctx_workarounds_init(engine, wal);
else if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915))
tgl_ctx_workarounds_init(engine, wal);
@@ -1294,10 +1308,18 @@ dg1_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
VSUNIT_CLKGATE_DIS_TGL);
}
+static void
+adls_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+{
+ gen12_gt_workarounds_init(i915, wal);
+}
+
static void
gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
- if (IS_DG1(i915))
+ if (IS_ALDERLAKE_S(i915))
+ adls_gt_workarounds_init(i915, wal);
+ else if (IS_DG1(i915))
dg1_gt_workarounds_init(i915, wal);
else if (IS_TIGERLAKE(i915))
tgl_gt_workarounds_init(i915, wal);
@@ -1678,6 +1700,11 @@ static void dg1_whitelist_build(struct intel_engine_cs *engine)
RING_FORCE_TO_NONPRIV_ACCESS_RD);
}
+static void adls_whitelist_build(struct intel_engine_cs *engine)
+{
+ tgl_whitelist_build(engine);
+}
+
void intel_engine_init_whitelist(struct intel_engine_cs *engine)
{
struct drm_i915_private *i915 = engine->i915;
@@ -1685,7 +1712,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
wa_init_start(w, "whitelist", engine->name);
- if (IS_DG1(i915))
+ if (IS_ALDERLAKE_S(i915))
+ adls_whitelist_build(engine);
+ else if (IS_DG1(i915))
dg1_whitelist_build(engine);
else if (IS_GEN(i915, 12))
tgl_whitelist_build(engine);
@@ -1766,37 +1795,38 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
VSUNIT_CLKGATE_DIS_TGL);
}
- if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
- /* Wa_1606931601:tgl,rkl,dg1 */
+ if (IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
+ IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
+ /* Wa_1606931601:tgl,rkl,dg1,adl-s */
wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
/*
* Wa_1407928979:tgl A*
* Wa_18011464164:tgl[B0+],dg1[B0+]
* Wa_22010931296:tgl[B0+],dg1[B0+]
- * Wa_14010919138:rkl, dg1
+ * Wa_14010919138:rkl,dg1,adl-s
*/
wa_write_or(wal, GEN7_FF_THREAD_MODE,
GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
/*
* Wa_1606700617:tgl,dg1
- * Wa_22010271021:tgl,rkl,dg1
+ * Wa_22010271021:tgl,rkl,dg1, adl-s
*/
wa_masked_en(wal,
GEN9_CS_DEBUG_MODE1,
FF_DOP_CLOCK_GATE_DISABLE);
}
- if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+ if (IS_ALDERLAKE_S(i915) || IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
- /* Wa_1409804808:tgl,rkl,dg1[a0] */
+ /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s */
wa_masked_en(wal, GEN7_ROW_CHICKEN2,
GEN12_PUSH_CONST_DEREF_HOLD_DIS);
/*
* Wa_1409085225:tgl
- * Wa_14010229206:tgl,rkl,dg1[a0]
+ * Wa_14010229206:tgl,rkl,dg1[a0],adl-s
*/
wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
@@ -1810,10 +1840,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
* it applies to all steppings so we trust the "all steppings."
* For DG1 this only applies to A0.
*/
- wa_masked_en(wal,
- GEN6_RC_SLEEP_PSMI_CONTROL,
- GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
- GEN8_RC_SEMA_IDLE_MSG_DISABLE);
+ if (!IS_ALDERLAKE_S(i915))
+ wa_masked_en(wal,
+ GEN6_RC_SLEEP_PSMI_CONTROL,
+ GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
+ GEN8_RC_SEMA_IDLE_MSG_DISABLE);
}
if (IS_GEN(i915, 12)) {
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 7310e019c611..64a09954fd54 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -394,7 +394,11 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
enum pipe pipe;
- if (INTEL_GEN(dev_priv) >= 10) {
+ /* Wa_14011765242: adl-s A0 */
+ if (IS_ADLS_DISP_REVID(dev_priv, REVID_A0, REVID_A0))
+ for_each_pipe(dev_priv, pipe)
+ runtime->num_scalers[pipe] = 0;
+ else if (INTEL_GEN(dev_priv) >= 10) {
for_each_pipe(dev_priv, pipe)
runtime->num_scalers[pipe] = 2;
} else if (IS_GEN(dev_priv, 9)) {
--
2.27.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH 15/21] drm/i915/adl_s: Add display, gt, ctx and ADL-S
2020-11-17 18:50 ` [Intel-gfx] [PATCH 15/21] drm/i915/adl_s: Add display, gt, ctx and ADL-S Aditya Swarup
@ 2020-12-01 18:46 ` Srivatsa, Anusha
2020-12-01 20:51 ` Lucas De Marchi
0 siblings, 1 reply; 56+ messages in thread
From: Srivatsa, Anusha @ 2020-12-01 18:46 UTC (permalink / raw)
To: Swarup, Aditya, intel-gfx; +Cc: Nikula, Jani, De Marchi, Lucas
s/Add display, gt, ctx and ADL-S/ Add display, gt, ctx WA for ADL-S
Anusha
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Aditya Swarup
> Sent: Tuesday, November 17, 2020 10:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>
> Subject: [Intel-gfx] [PATCH 15/21] drm/i915/adl_s: Add display, gt, ctx and
> ADL-S
>
> - Inherit the gen12 workarounds.
> - Add placeholders to setup GT WA.
> - Extend permanent driver WA Wa_1409767108 to adl-s and
> Wa_14010685332 to adl-s.
> - Extend permanent driver WA Wa_1606054188 to adl-s
> - Add Wa_14011765242 for adl-s A0 stepping.
>
> v2:
> - Extend Wa_14010919138 and Wa_14010229206 to ADL-S (Madhumitha)
> - Extend Wa_22010271021 to ADLS (cyokoyam)
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Madhumitha Tolakanahalli Pradeep
> <madhumitha.tolakanahalli.pradeep@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> ---
> .../drm/i915/display/intel_display_power.c | 7 +-
> drivers/gpu/drm/i915/display/intel_sprite.c | 4 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 91 +++++++++++++------
> drivers/gpu/drm/i915/intel_device_info.c | 6 +-
> 4 files changed, 72 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 06c036e2092c..8b163d804a41 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5282,9 +5282,10 @@ static void tgl_bw_buddy_init(struct
> drm_i915_private *dev_priv)
> unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask;
> int config, i;
>
> - if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
> + if (IS_ALDERLAKE_S(dev_priv) ||
> + IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
> IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_B0))
> - /* Wa_1409767108:tgl,dg1 */
> + /* Wa_1409767108:tgl,dg1,adl-s */
> table = wa_1409767108_buddy_page_masks;
> else
> table = tgl_buddy_page_masks;
> @@ -5322,7 +5323,7 @@ static void icl_display_core_init(struct
> drm_i915_private *dev_priv,
>
> gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>
> - /* Wa_14011294188:ehl,jsl,tgl,rkl */
> + /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */
> if (INTEL_PCH_TYPE(dev_priv) >= PCH_JSP &&
> INTEL_PCH_TYPE(dev_priv) < PCH_DG1)
> intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0, diff --git
> a/drivers/gpu/drm/i915/display/intel_sprite.c
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index f7da4a56054e..1e954e2928fe 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -2359,8 +2359,8 @@ static int skl_plane_check_fb(const struct
> intel_crtc_state *crtc_state,
> return -EINVAL;
> }
>
> - /* Wa_1606054188:tgl */
> - if (IS_TIGERLAKE(dev_priv) &&
> + /* Wa_1606054188:tgl,adl-s */
> + if ((IS_ALDERLAKE_S(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
> plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE &&
> intel_format_is_p01x(fb->format->format)) {
> drm_dbg_kms(&dev_priv->drm,
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index d88d3d60fb1c..e6f149bd537f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -664,22 +664,6 @@ static void tgl_ctx_workarounds_init(struct
> intel_engine_cs *engine,
> struct i915_wa_list *wal)
> {
> gen12_ctx_workarounds_init(engine, wal);
> -
> - /*
> - * Wa_1604555607:tgl,rkl
> - *
> - * Note that the implementation of this workaround is further
> modified
> - * according to the FF_MODE2 guidance given by
> Wa_1608008084:gen12.
> - * FF_MODE2 register will return the wrong value when read. The
> default
> - * value for this register is zero for all fields and there are no bit
> - * masks. So instead of doing a RMW we should just write the GS
> Timer
> - * and TDS timer values for Wa_1604555607 and Wa_16011163337.
> - */
> - wa_add(wal,
> - FF_MODE2,
> - FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK,
> - FF_MODE2_GS_TIMER_224 | FF_MODE2_TDS_TIMER_128,
> - 0);
> }
>
> static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, @@ -
> 696,6 +680,12 @@ static void dg1_ctx_workarounds_init(struct
> intel_engine_cs *engine,
>
> DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE);
> }
>
> +static void adls_ctx_workarounds_init(struct intel_engine_cs *engine,
> + struct i915_wa_list *wal)
> +{
> + gen12_ctx_workarounds_init(engine, wal); }
> +
> static void
> __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
> struct i915_wa_list *wal,
> @@ -708,7 +698,31 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs
> *engine,
>
> wa_init_start(wal, name, engine->name);
>
> - if (IS_DG1(i915))
> + if (INTEL_GEN(i915) >= 12) {
> + /*
> + * This setting isn't actually a workaround, but is a general
> + * tuning setting that needs to be programmed on all
> platforms
> + * gen12+. Although some platforms also refer to this
> setting
> + * as Wa_1604555607, we need to program it even on
> platforms that
> + * don't explicitly list that workaround.
> + *
> + * Note that the implementation is further modified
> according
> + * to the FF_MODE2 guidance given by
> Wa_1608008084:gen12.
> + * FF_MODE2 register will return the wrong value when
> read.
> + * The default value for this register is zero for all fields
> + * and there are no bit masks. So instead of doing a RMW,
> we
> + * should just write the value directly.
> + */
> + wa_add(wal,
> + FF_MODE2,
> + FF_MODE2_TDS_TIMER_MASK,
> + FF_MODE2_TDS_TIMER_128,
> + 0);
> + }
> +
> + if (IS_ALDERLAKE_S(i915))
> + adls_ctx_workarounds_init(engine, wal);
> + else if (IS_DG1(i915))
> dg1_ctx_workarounds_init(engine, wal);
> else if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915))
> tgl_ctx_workarounds_init(engine, wal); @@ -1294,10
> +1308,18 @@ dg1_gt_workarounds_init(struct drm_i915_private *i915,
> struct i915_wa_list *wal)
> VSUNIT_CLKGATE_DIS_TGL);
> }
>
> +static void
> +adls_gt_workarounds_init(struct drm_i915_private *i915, struct
> +i915_wa_list *wal) {
> + gen12_gt_workarounds_init(i915, wal);
> +}
> +
> static void
> gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list
> *wal) {
> - if (IS_DG1(i915))
> + if (IS_ALDERLAKE_S(i915))
> + adls_gt_workarounds_init(i915, wal);
> + else if (IS_DG1(i915))
> dg1_gt_workarounds_init(i915, wal);
> else if (IS_TIGERLAKE(i915))
> tgl_gt_workarounds_init(i915, wal);
> @@ -1678,6 +1700,11 @@ static void dg1_whitelist_build(struct
> intel_engine_cs *engine)
> RING_FORCE_TO_NONPRIV_ACCESS_RD); }
>
> +static void adls_whitelist_build(struct intel_engine_cs *engine) {
> + tgl_whitelist_build(engine);
> +}
> +
> void intel_engine_init_whitelist(struct intel_engine_cs *engine) {
> struct drm_i915_private *i915 = engine->i915; @@ -1685,7 +1712,9
> @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>
> wa_init_start(w, "whitelist", engine->name);
>
> - if (IS_DG1(i915))
> + if (IS_ALDERLAKE_S(i915))
> + adls_whitelist_build(engine);
> + else if (IS_DG1(i915))
> dg1_whitelist_build(engine);
> else if (IS_GEN(i915, 12))
> tgl_whitelist_build(engine);
> @@ -1766,37 +1795,38 @@ rcs_engine_wa_init(struct intel_engine_cs
> *engine, struct i915_wa_list *wal)
> VSUNIT_CLKGATE_DIS_TGL);
> }
>
> - if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> - /* Wa_1606931601:tgl,rkl,dg1 */
> + if (IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
> + IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> + /* Wa_1606931601:tgl,rkl,dg1,adl-s */
> wa_masked_en(wal, GEN7_ROW_CHICKEN2,
> GEN12_DISABLE_EARLY_READ);
>
> /*
> * Wa_1407928979:tgl A*
> * Wa_18011464164:tgl[B0+],dg1[B0+]
> * Wa_22010931296:tgl[B0+],dg1[B0+]
> - * Wa_14010919138:rkl, dg1
> + * Wa_14010919138:rkl,dg1,adl-s
> */
> wa_write_or(wal, GEN7_FF_THREAD_MODE,
> GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
>
> /*
> * Wa_1606700617:tgl,dg1
> - * Wa_22010271021:tgl,rkl,dg1
> + * Wa_22010271021:tgl,rkl,dg1, adl-s
> */
> wa_masked_en(wal,
> GEN9_CS_DEBUG_MODE1,
> FF_DOP_CLOCK_GATE_DISABLE);
> }
>
> - if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
> + if (IS_ALDERLAKE_S(i915) || IS_DG1_REVID(i915, DG1_REVID_A0,
> +DG1_REVID_A0) ||
> IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> - /* Wa_1409804808:tgl,rkl,dg1[a0] */
> + /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s */
> wa_masked_en(wal, GEN7_ROW_CHICKEN2,
> GEN12_PUSH_CONST_DEREF_HOLD_DIS);
>
> /*
> * Wa_1409085225:tgl
> - * Wa_14010229206:tgl,rkl,dg1[a0]
> + * Wa_14010229206:tgl,rkl,dg1[a0],adl-s
> */
> wa_masked_en(wal, GEN9_ROW_CHICKEN4,
> GEN12_DISABLE_TDL_PUSH);
>
> @@ -1810,10 +1840,11 @@ rcs_engine_wa_init(struct intel_engine_cs
> *engine, struct i915_wa_list *wal)
> * it applies to all steppings so we trust the "all steppings."
> * For DG1 this only applies to A0.
> */
> - wa_masked_en(wal,
> - GEN6_RC_SLEEP_PSMI_CONTROL,
> -
> GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
> - GEN8_RC_SEMA_IDLE_MSG_DISABLE);
> + if (!IS_ALDERLAKE_S(i915))
> + wa_masked_en(wal,
> + GEN6_RC_SLEEP_PSMI_CONTROL,
> +
> GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
> + GEN8_RC_SEMA_IDLE_MSG_DISABLE);
> }
>
> if (IS_GEN(i915, 12)) {
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index 7310e019c611..64a09954fd54 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -394,7 +394,11 @@ void intel_device_info_runtime_init(struct
> drm_i915_private *dev_priv)
> struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
> enum pipe pipe;
>
> - if (INTEL_GEN(dev_priv) >= 10) {
> + /* Wa_14011765242: adl-s A0 */
> + if (IS_ADLS_DISP_REVID(dev_priv, REVID_A0, REVID_A0))
> + for_each_pipe(dev_priv, pipe)
> + runtime->num_scalers[pipe] = 0;
> + else if (INTEL_GEN(dev_priv) >= 10) {
> for_each_pipe(dev_priv, pipe)
> runtime->num_scalers[pipe] = 2;
> } else if (IS_GEN(dev_priv, 9)) {
> --
> 2.27.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH 15/21] drm/i915/adl_s: Add display, gt, ctx and ADL-S
2020-12-01 18:46 ` Srivatsa, Anusha
@ 2020-12-01 20:51 ` Lucas De Marchi
0 siblings, 0 replies; 56+ messages in thread
From: Lucas De Marchi @ 2020-12-01 20:51 UTC (permalink / raw)
To: Srivatsa, Anusha; +Cc: Nikula, Jani, intel-gfx
On Tue, Dec 01, 2020 at 10:46:58AM -0800, Anusha Srivatsa wrote:
>s/Add display, gt, ctx and ADL-S/ Add display, gt, ctx WA for ADL-S
>
>Anusha
>
>
>> -----Original Message-----
>> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
>> Aditya Swarup
>> Sent: Tuesday, November 17, 2020 10:50 AM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
>> <lucas.demarchi@intel.com>
>> Subject: [Intel-gfx] [PATCH 15/21] drm/i915/adl_s: Add display, gt, ctx and
>> ADL-S
>>
>> - Inherit the gen12 workarounds.
>> - Add placeholders to setup GT WA.
>> - Extend permanent driver WA Wa_1409767108 to adl-s and
>> Wa_14010685332 to adl-s.
>> - Extend permanent driver WA Wa_1606054188 to adl-s
>> - Add Wa_14011765242 for adl-s A0 stepping.
>>
>> v2:
>> - Extend Wa_14010919138 and Wa_14010229206 to ADL-S (Madhumitha)
>> - Extend Wa_22010271021 to ADLS (cyokoyam)
>>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Cc: Imre Deak <imre.deak@intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>> Signed-off-by: Madhumitha Tolakanahalli Pradeep
>> <madhumitha.tolakanahalli.pradeep@intel.com>
>> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>> ---
>> .../drm/i915/display/intel_display_power.c | 7 +-
>> drivers/gpu/drm/i915/display/intel_sprite.c | 4 +-
>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 91 +++++++++++++------
this needs to be split out from the rest, since now the gt part is
applied to a different branch.
Lucas De Marchi
>> drivers/gpu/drm/i915/intel_device_info.c | 6 +-
>> 4 files changed, 72 insertions(+), 36 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
>> b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index 06c036e2092c..8b163d804a41 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -5282,9 +5282,10 @@ static void tgl_bw_buddy_init(struct
>> drm_i915_private *dev_priv)
>> unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask;
>> int config, i;
>>
>> - if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
>> + if (IS_ALDERLAKE_S(dev_priv) ||
>> + IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
>> IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_B0))
>> - /* Wa_1409767108:tgl,dg1 */
>> + /* Wa_1409767108:tgl,dg1,adl-s */
>> table = wa_1409767108_buddy_page_masks;
>> else
>> table = tgl_buddy_page_masks;
>> @@ -5322,7 +5323,7 @@ static void icl_display_core_init(struct
>> drm_i915_private *dev_priv,
>>
>> gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>>
>> - /* Wa_14011294188:ehl,jsl,tgl,rkl */
>> + /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */
>> if (INTEL_PCH_TYPE(dev_priv) >= PCH_JSP &&
>> INTEL_PCH_TYPE(dev_priv) < PCH_DG1)
>> intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0, diff --git
>> a/drivers/gpu/drm/i915/display/intel_sprite.c
>> b/drivers/gpu/drm/i915/display/intel_sprite.c
>> index f7da4a56054e..1e954e2928fe 100644
>> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>> @@ -2359,8 +2359,8 @@ static int skl_plane_check_fb(const struct
>> intel_crtc_state *crtc_state,
>> return -EINVAL;
>> }
>>
>> - /* Wa_1606054188:tgl */
>> - if (IS_TIGERLAKE(dev_priv) &&
>> + /* Wa_1606054188:tgl,adl-s */
>> + if ((IS_ALDERLAKE_S(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
>> plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE &&
>> intel_format_is_p01x(fb->format->format)) {
>> drm_dbg_kms(&dev_priv->drm,
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index d88d3d60fb1c..e6f149bd537f 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -664,22 +664,6 @@ static void tgl_ctx_workarounds_init(struct
>> intel_engine_cs *engine,
>> struct i915_wa_list *wal)
>> {
>> gen12_ctx_workarounds_init(engine, wal);
>> -
>> - /*
>> - * Wa_1604555607:tgl,rkl
>> - *
>> - * Note that the implementation of this workaround is further
>> modified
>> - * according to the FF_MODE2 guidance given by
>> Wa_1608008084:gen12.
>> - * FF_MODE2 register will return the wrong value when read. The
>> default
>> - * value for this register is zero for all fields and there are no bit
>> - * masks. So instead of doing a RMW we should just write the GS
>> Timer
>> - * and TDS timer values for Wa_1604555607 and Wa_16011163337.
>> - */
>> - wa_add(wal,
>> - FF_MODE2,
>> - FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK,
>> - FF_MODE2_GS_TIMER_224 | FF_MODE2_TDS_TIMER_128,
>> - 0);
>> }
>>
>> static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, @@ -
>> 696,6 +680,12 @@ static void dg1_ctx_workarounds_init(struct
>> intel_engine_cs *engine,
>>
>> DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE);
>> }
>>
>> +static void adls_ctx_workarounds_init(struct intel_engine_cs *engine,
>> + struct i915_wa_list *wal)
>> +{
>> + gen12_ctx_workarounds_init(engine, wal); }
>> +
>> static void
>> __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
>> struct i915_wa_list *wal,
>> @@ -708,7 +698,31 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs
>> *engine,
>>
>> wa_init_start(wal, name, engine->name);
>>
>> - if (IS_DG1(i915))
>> + if (INTEL_GEN(i915) >= 12) {
>> + /*
>> + * This setting isn't actually a workaround, but is a general
>> + * tuning setting that needs to be programmed on all
>> platforms
>> + * gen12+. Although some platforms also refer to this
>> setting
>> + * as Wa_1604555607, we need to program it even on
>> platforms that
>> + * don't explicitly list that workaround.
>> + *
>> + * Note that the implementation is further modified
>> according
>> + * to the FF_MODE2 guidance given by
>> Wa_1608008084:gen12.
>> + * FF_MODE2 register will return the wrong value when
>> read.
>> + * The default value for this register is zero for all fields
>> + * and there are no bit masks. So instead of doing a RMW,
>> we
>> + * should just write the value directly.
>> + */
>> + wa_add(wal,
>> + FF_MODE2,
>> + FF_MODE2_TDS_TIMER_MASK,
>> + FF_MODE2_TDS_TIMER_128,
>> + 0);
>> + }
>> +
>> + if (IS_ALDERLAKE_S(i915))
>> + adls_ctx_workarounds_init(engine, wal);
>> + else if (IS_DG1(i915))
>> dg1_ctx_workarounds_init(engine, wal);
>> else if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915))
>> tgl_ctx_workarounds_init(engine, wal); @@ -1294,10
>> +1308,18 @@ dg1_gt_workarounds_init(struct drm_i915_private *i915,
>> struct i915_wa_list *wal)
>> VSUNIT_CLKGATE_DIS_TGL);
>> }
>>
>> +static void
>> +adls_gt_workarounds_init(struct drm_i915_private *i915, struct
>> +i915_wa_list *wal) {
>> + gen12_gt_workarounds_init(i915, wal);
>> +}
>> +
>> static void
>> gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list
>> *wal) {
>> - if (IS_DG1(i915))
>> + if (IS_ALDERLAKE_S(i915))
>> + adls_gt_workarounds_init(i915, wal);
>> + else if (IS_DG1(i915))
>> dg1_gt_workarounds_init(i915, wal);
>> else if (IS_TIGERLAKE(i915))
>> tgl_gt_workarounds_init(i915, wal);
>> @@ -1678,6 +1700,11 @@ static void dg1_whitelist_build(struct
>> intel_engine_cs *engine)
>> RING_FORCE_TO_NONPRIV_ACCESS_RD); }
>>
>> +static void adls_whitelist_build(struct intel_engine_cs *engine) {
>> + tgl_whitelist_build(engine);
>> +}
>> +
>> void intel_engine_init_whitelist(struct intel_engine_cs *engine) {
>> struct drm_i915_private *i915 = engine->i915; @@ -1685,7 +1712,9
>> @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>>
>> wa_init_start(w, "whitelist", engine->name);
>>
>> - if (IS_DG1(i915))
>> + if (IS_ALDERLAKE_S(i915))
>> + adls_whitelist_build(engine);
>> + else if (IS_DG1(i915))
>> dg1_whitelist_build(engine);
>> else if (IS_GEN(i915, 12))
>> tgl_whitelist_build(engine);
>> @@ -1766,37 +1795,38 @@ rcs_engine_wa_init(struct intel_engine_cs
>> *engine, struct i915_wa_list *wal)
>> VSUNIT_CLKGATE_DIS_TGL);
>> }
>>
>> - if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
>> - /* Wa_1606931601:tgl,rkl,dg1 */
>> + if (IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
>> + IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
>> + /* Wa_1606931601:tgl,rkl,dg1,adl-s */
>> wa_masked_en(wal, GEN7_ROW_CHICKEN2,
>> GEN12_DISABLE_EARLY_READ);
>>
>> /*
>> * Wa_1407928979:tgl A*
>> * Wa_18011464164:tgl[B0+],dg1[B0+]
>> * Wa_22010931296:tgl[B0+],dg1[B0+]
>> - * Wa_14010919138:rkl, dg1
>> + * Wa_14010919138:rkl,dg1,adl-s
>> */
>> wa_write_or(wal, GEN7_FF_THREAD_MODE,
>> GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
>>
>> /*
>> * Wa_1606700617:tgl,dg1
>> - * Wa_22010271021:tgl,rkl,dg1
>> + * Wa_22010271021:tgl,rkl,dg1, adl-s
>> */
>> wa_masked_en(wal,
>> GEN9_CS_DEBUG_MODE1,
>> FF_DOP_CLOCK_GATE_DISABLE);
>> }
>>
>> - if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
>> + if (IS_ALDERLAKE_S(i915) || IS_DG1_REVID(i915, DG1_REVID_A0,
>> +DG1_REVID_A0) ||
>> IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
>> - /* Wa_1409804808:tgl,rkl,dg1[a0] */
>> + /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s */
>> wa_masked_en(wal, GEN7_ROW_CHICKEN2,
>> GEN12_PUSH_CONST_DEREF_HOLD_DIS);
>>
>> /*
>> * Wa_1409085225:tgl
>> - * Wa_14010229206:tgl,rkl,dg1[a0]
>> + * Wa_14010229206:tgl,rkl,dg1[a0],adl-s
>> */
>> wa_masked_en(wal, GEN9_ROW_CHICKEN4,
>> GEN12_DISABLE_TDL_PUSH);
>>
>> @@ -1810,10 +1840,11 @@ rcs_engine_wa_init(struct intel_engine_cs
>> *engine, struct i915_wa_list *wal)
>> * it applies to all steppings so we trust the "all steppings."
>> * For DG1 this only applies to A0.
>> */
>> - wa_masked_en(wal,
>> - GEN6_RC_SLEEP_PSMI_CONTROL,
>> -
>> GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
>> - GEN8_RC_SEMA_IDLE_MSG_DISABLE);
>> + if (!IS_ALDERLAKE_S(i915))
>> + wa_masked_en(wal,
>> + GEN6_RC_SLEEP_PSMI_CONTROL,
>> +
>> GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
>> + GEN8_RC_SEMA_IDLE_MSG_DISABLE);
>> }
>>
>> if (IS_GEN(i915, 12)) {
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
>> b/drivers/gpu/drm/i915/intel_device_info.c
>> index 7310e019c611..64a09954fd54 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -394,7 +394,11 @@ void intel_device_info_runtime_init(struct
>> drm_i915_private *dev_priv)
>> struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
>> enum pipe pipe;
>>
>> - if (INTEL_GEN(dev_priv) >= 10) {
>> + /* Wa_14011765242: adl-s A0 */
>> + if (IS_ADLS_DISP_REVID(dev_priv, REVID_A0, REVID_A0))
>> + for_each_pipe(dev_priv, pipe)
>> + runtime->num_scalers[pipe] = 0;
>> + else if (INTEL_GEN(dev_priv) >= 10) {
>> for_each_pipe(dev_priv, pipe)
>> runtime->num_scalers[pipe] = 2;
>> } else if (IS_GEN(dev_priv, 9)) {
>> --
>> 2.27.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread
* [Intel-gfx] [PATCH 16/21] drm/i915/adl_s: MCHBAR memory info registers are moved
2020-11-17 18:50 [Intel-gfx] [PATCH 00/21] Introduce Alderlake-S Aditya Swarup
` (14 preceding siblings ...)
2020-11-17 18:50 ` [Intel-gfx] [PATCH 15/21] drm/i915/adl_s: Add display, gt, ctx and ADL-S Aditya Swarup
@ 2020-11-17 18:50 ` Aditya Swarup
2020-11-20 20:18 ` Lucas De Marchi
2020-11-25 0:11 ` Lucas De Marchi
2020-11-17 18:50 ` [Intel-gfx] [PATCH 17/21] drm/i915/adl_s: Add power wells Aditya Swarup
` (9 subsequent siblings)
25 siblings, 2 replies; 56+ messages in thread
From: Aditya Swarup @ 2020-11-17 18:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi, Yokoyama
From: Caz Yokoyama <caz.yokoyama@intel.com>
The crwebview indicates on ADL-S that some of our MCHBAR
registers have moved from their traditional 0x50XX offsets to
new locations. The meaning and bit layout of the registers
remain same.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Yokoyama, Caz <caz.yokoyama@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++++
drivers/gpu/drm/i915/intel_dram.c | 18 +++++++++++++++---
2 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4c8d0d84af6a..6abba59592f7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10863,6 +10863,8 @@ enum skl_power_gate {
#define SKL_DRAM_DDR_TYPE_LPDDR3 (2 << 0)
#define SKL_DRAM_DDR_TYPE_LPDDR4 (3 << 0)
+#define ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6048)
+
#define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
#define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
#define SKL_DRAM_S_SHIFT 16
@@ -10890,6 +10892,9 @@ enum skl_power_gate {
#define CNL_DRAM_RANK_3 (0x2 << 9)
#define CNL_DRAM_RANK_4 (0x3 << 9)
+#define ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6054)
+#define ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6058)
+
/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
* since on HSW we can't write to it using I915_WRITE. */
#define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c
index 4754296a250e..e7427e5f4130 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -184,13 +184,21 @@ skl_dram_get_channels_info(struct drm_i915_private *i915)
u32 val;
int ret;
- val = intel_uncore_read(&i915->uncore,
+ if (IS_ALDERLAKE_S(i915))
+ val = intel_uncore_read(&i915->uncore,
+ ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR);
+ else
+ val = intel_uncore_read(&i915->uncore,
SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
ret = skl_dram_get_channel_info(i915, &ch0, 0, val);
if (ret == 0)
dram_info->num_channels++;
- val = intel_uncore_read(&i915->uncore,
+ if (IS_ALDERLAKE_S(i915))
+ val = intel_uncore_read(&i915->uncore,
+ ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR);
+ else
+ val = intel_uncore_read(&i915->uncore,
SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
ret = skl_dram_get_channel_info(i915, &ch1, 1, val);
if (ret == 0)
@@ -231,7 +239,11 @@ skl_get_dram_type(struct drm_i915_private *i915)
{
u32 val;
- val = intel_uncore_read(&i915->uncore,
+ if (IS_ALDERLAKE_S(i915))
+ val = intel_uncore_read(&i915->uncore,
+ ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR);
+ else
+ val = intel_uncore_read(&i915->uncore,
SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
switch (val & SKL_DRAM_DDR_TYPE_MASK) {
--
2.27.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH 16/21] drm/i915/adl_s: MCHBAR memory info registers are moved
2020-11-17 18:50 ` [Intel-gfx] [PATCH 16/21] drm/i915/adl_s: MCHBAR memory info registers are moved Aditya Swarup
@ 2020-11-20 20:18 ` Lucas De Marchi
2020-11-20 20:39 ` Caz Yokoyama
2020-11-25 0:11 ` Lucas De Marchi
1 sibling, 1 reply; 56+ messages in thread
From: Lucas De Marchi @ 2020-11-20 20:18 UTC (permalink / raw)
To: Aditya Swarup; +Cc: Jani Nikula, Yokoyama, intel-gfx
On Tue, Nov 17, 2020 at 10:50:24AM -0800, Aditya Swarup wrote:
>From: Caz Yokoyama <caz.yokoyama@intel.com>
>
>The crwebview indicates on ADL-S that some of our MCHBAR
>registers have moved from their traditional 0x50XX offsets to
>new locations. The meaning and bit layout of the registers
>remain same.
>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Cc: Jani Nikula <jani.nikula@intel.com>
>Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>Cc: Imre Deak <imre.deak@intel.com>
>Cc: Matt Roper <matthew.d.roper@intel.com>
>Signed-off-by: Yokoyama, Caz <caz.yokoyama@intel.com>
>Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>---
> drivers/gpu/drm/i915/i915_reg.h | 5 +++++
> drivers/gpu/drm/i915/intel_dram.c | 18 +++++++++++++++---
> 2 files changed, 20 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 4c8d0d84af6a..6abba59592f7 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -10863,6 +10863,8 @@ enum skl_power_gate {
> #define SKL_DRAM_DDR_TYPE_LPDDR3 (2 << 0)
> #define SKL_DRAM_DDR_TYPE_LPDDR4 (3 << 0)
>
>+#define ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6048)
>+
> #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
> #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
> #define SKL_DRAM_S_SHIFT 16
>@@ -10890,6 +10892,9 @@ enum skl_power_gate {
> #define CNL_DRAM_RANK_3 (0x2 << 9)
> #define CNL_DRAM_RANK_4 (0x3 << 9)
>
>+#define ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6054)
>+#define ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6058)
>+
> /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
> * since on HSW we can't write to it using I915_WRITE. */
> #define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
>diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c
>index 4754296a250e..e7427e5f4130 100644
>--- a/drivers/gpu/drm/i915/intel_dram.c
>+++ b/drivers/gpu/drm/i915/intel_dram.c
>@@ -184,13 +184,21 @@ skl_dram_get_channels_info(struct drm_i915_private *i915)
> u32 val;
> int ret;
>
>- val = intel_uncore_read(&i915->uncore,
>+ if (IS_ALDERLAKE_S(i915))
>+ val = intel_uncore_read(&i915->uncore,
>+ ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR);
>+ else
>+ val = intel_uncore_read(&i915->uncore,
> SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
> ret = skl_dram_get_channel_info(i915, &ch0, 0, val);
> if (ret == 0)
> dram_info->num_channels++;
>
>- val = intel_uncore_read(&i915->uncore,
>+ if (IS_ALDERLAKE_S(i915))
>+ val = intel_uncore_read(&i915->uncore,
>+ ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR);
>+ else
>+ val = intel_uncore_read(&i915->uncore,
> SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
probably better to:
u32 ch0, ch1;
and then keep the reads together in a single if/else chain.
Or use i915_reg_t ch0_reg, ch1_reg
Lucas De Marchi
> ret = skl_dram_get_channel_info(i915, &ch1, 1, val);
> if (ret == 0)
>@@ -231,7 +239,11 @@ skl_get_dram_type(struct drm_i915_private *i915)
> {
> u32 val;
>
>- val = intel_uncore_read(&i915->uncore,
>+ if (IS_ALDERLAKE_S(i915))
>+ val = intel_uncore_read(&i915->uncore,
>+ ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR);
>+ else
>+ val = intel_uncore_read(&i915->uncore,
> SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
>
> switch (val & SKL_DRAM_DDR_TYPE_MASK) {
>--
>2.27.0
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH 16/21] drm/i915/adl_s: MCHBAR memory info registers are moved
2020-11-20 20:18 ` Lucas De Marchi
@ 2020-11-20 20:39 ` Caz Yokoyama
0 siblings, 0 replies; 56+ messages in thread
From: Caz Yokoyama @ 2020-11-20 20:39 UTC (permalink / raw)
To: Lucas De Marchi, Aditya Swarup; +Cc: Jani Nikula, intel-gfx, Yokoyama
On Fri, 2020-11-20 at 12:18 -0800, Lucas De Marchi wrote:
> On Tue, Nov 17, 2020 at 10:50:24AM -0800, Aditya Swarup wrote:
> > From: Caz Yokoyama <caz.yokoyama@intel.com>
> >
> > The crwebview indicates on ADL-S that some of our MCHBAR
> > registers have moved from their traditional 0x50XX offsets to
> > new locations. The meaning and bit layout of the registers
> > remain same.
> >
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Imre Deak <imre.deak@intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Yokoyama, Caz <caz.yokoyama@intel.com>
> > Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 5 +++++
> > drivers/gpu/drm/i915/intel_dram.c | 18 +++++++++++++++---
> > 2 files changed, 20 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 4c8d0d84af6a..6abba59592f7 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -10863,6 +10863,8 @@ enum skl_power_gate {
> > #define SKL_DRAM_DDR_TYPE_LPDDR3 (2 << 0)
> > #define SKL_DRAM_DDR_TYPE_LPDDR4 (3 << 0)
> >
> > +#define ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR
> > _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6048)
> > +
> > #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MI
> > RROR_BASE_SNB + 0x500C)
> > #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MI
> > RROR_BASE_SNB + 0x5010)
> > #define SKL_DRAM_S_SHIFT 16
> > @@ -10890,6 +10892,9 @@ enum skl_power_gate {
> > #define CNL_DRAM_RANK_3 (0x2 << 9)
> > #define CNL_DRAM_RANK_4 (0x3 << 9)
> >
> > +#define ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR _MMIO(MCHBAR_MI
> > RROR_BASE_SNB + 0x6054)
> > +#define ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR _MMIO(MCHBAR_MI
> > RROR_BASE_SNB + 0x6058)
> > +
> > /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using
> > this register,
> > * since on HSW we can't write to it using I915_WRITE. */
> > #define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB +
> > 0x5F0C)
> > diff --git a/drivers/gpu/drm/i915/intel_dram.c
> > b/drivers/gpu/drm/i915/intel_dram.c
> > index 4754296a250e..e7427e5f4130 100644
> > --- a/drivers/gpu/drm/i915/intel_dram.c
> > +++ b/drivers/gpu/drm/i915/intel_dram.c
> > @@ -184,13 +184,21 @@ skl_dram_get_channels_info(struct
> > drm_i915_private *i915)
> > u32 val;
> > int ret;
> >
> > - val = intel_uncore_read(&i915->uncore,
> > + if (IS_ALDERLAKE_S(i915))
> > + val = intel_uncore_read(&i915->uncore,
> > + ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR);
> > + else
> > + val = intel_uncore_read(&i915->uncore,
> > SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
> > ret = skl_dram_get_channel_info(i915, &ch0, 0, val);
> > if (ret == 0)
> > dram_info->num_channels++;
> >
> > - val = intel_uncore_read(&i915->uncore,
> > + if (IS_ALDERLAKE_S(i915))
> > + val = intel_uncore_read(&i915->uncore,
> > + ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR);
> > + else
> > + val = intel_uncore_read(&i915->uncore,
> > SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
>
> probably better to:
>
> u32 ch0, ch1;
>
> and then keep the reads together in a single if/else chain.
> Or use i915_reg_t ch0_reg, ch1_reg
Agree/Better idea. When I worked for, I only concerned how to minimize
my patch and not think about whether the code is simple and readable.
-caz
>
> Lucas De Marchi
>
> > ret = skl_dram_get_channel_info(i915, &ch1, 1, val);
> > if (ret == 0)
> > @@ -231,7 +239,11 @@ skl_get_dram_type(struct drm_i915_private
> > *i915)
> > {
> > u32 val;
> >
> > - val = intel_uncore_read(&i915->uncore,
> > + if (IS_ALDERLAKE_S(i915))
> > + val = intel_uncore_read(&i915->uncore,
> > + ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR);
> > + else
> > + val = intel_uncore_read(&i915->uncore,
> > SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMA
> > IN);
> >
> > switch (val & SKL_DRAM_DDR_TYPE_MASK) {
> > --
> > 2.27.0
> >
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Intel-gfx] [PATCH 16/21] drm/i915/adl_s: MCHBAR memory info registers are moved
2020-11-17 18:50 ` [Intel-gfx] [PATCH 16/21] drm/i915/adl_s: MCHBAR memory info registers are moved Aditya Swarup
2020-11-20 20:18 ` Lucas De Marchi
@ 2020-11-25 0:11 ` Lucas De Marchi
1 sibling, 0 replies; 56+ messages in thread
From: Lucas De Marchi @ 2020-11-25 0:11 UTC (permalink / raw)
To: Aditya Swarup; +Cc: Jani Nikula, Yokoyama, intel-gfx
On Tue, Nov 17, 2020 at 10:50:24AM -0800, Aditya Swarup wrote:
>From: Caz Yokoyama <caz.yokoyama@intel.com>
>
>The crwebview indicates on ADL-S that some of our MCHBAR
>registers have moved from their traditional 0x50XX offsets to
>new locations. The meaning and bit layout of the registers
>remain same.
>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Cc: Jani Nikula <jani.nikula@intel.com>
>Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>Cc: Imre Deak <imre.deak@intel.com>
>Cc: Matt Roper <matthew.d.roper@intel.com>
>Signed-off-by: Yokoyama, Caz <caz.yokoyama@intel.com>
>Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>---
> drivers/gpu/drm/i915/i915_reg.h | 5 +++++
> drivers/gpu/drm/i915/intel_dram.c | 18 +++++++++++++++---
> 2 files changed, 20 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 4c8d0d84af6a..6abba59592f7 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -10863,6 +10863,8 @@ enum skl_power_gate {
> #define SKL_DRAM_DDR_TYPE_LPDDR3 (2 << 0)
> #define SKL_DRAM_DDR_TYPE_LPDDR4 (3 << 0)
>
>+#define ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6048)
should be single space after define
Lucas De Marchi
>+
> #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
> #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
> #define SKL_DRAM_S_SHIFT 16
>@@ -10890,6 +10892,9 @@ enum skl_power_gate {
> #define CNL_DRAM_RANK_3 (0x2 << 9)
> #define CNL_DRAM_RANK_4 (0x3 << 9)
>
>+#define ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6054)
>+#define ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6058)
>+
> /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
> * since on HSW we can't write to it using I915_WRITE. */
> #define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
>diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c
>index 4754296a250e..e7427e5f4130 100644
>--- a/drivers/gpu/drm/i915/intel_dram.c
>+++ b/drivers/gpu/drm/i915/intel_dram.c
>@@ -184,13 +184,21 @@ skl_dram_get_channels_info(struct drm_i915_private *i915)
> u32 val;
> int ret;
>
>- val = intel_uncore_read(&i915->uncore,
>+ if (IS_ALDERLAKE_S(i915))
>+ val = intel_uncore_read(&i915->uncore,
>+ ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR);
>+ else
>+ val = intel_uncore_read(&i915->uncore,
> SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
> ret = skl_dram_get_channel_info(i915, &ch0, 0, val);
> if (ret == 0)
> dram_info->num_channels++;
>
>- val = intel_uncore_read(&i915->uncore,
>+ if (IS_ALDERLAKE_S(i915))
>+ val = intel_uncore_read(&i915->uncore,
>+ ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR);
>+ else
>+ val = intel_uncore_read(&i915->uncore,
> SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
> ret = skl_dram_get_channel_info(i915, &ch1, 1, val);
> if (ret == 0)
>@@ -231,7 +239,11 @@ skl_get_dram_type(struct drm_i915_private *i915)
> {
> u32 val;
>
>- val = intel_uncore_read(&i915->uncore,
>+ if (IS_ALDERLAKE_S(i915))
>+ val = intel_uncore_read(&i915->uncore,
>+ ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR);
>+ else
>+ val = intel_uncore_read(&i915->uncore,
> SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
>
> switch (val & SKL_DRAM_DDR_TYPE_MASK) {
>--
>2.27.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread
* [Intel-gfx] [PATCH 17/21] drm/i915/adl_s: Add power wells
2020-11-17 18:50 [Intel-gfx] [PATCH 00/21] Introduce Alderlake-S Aditya Swarup
` (15 preceding siblings ...)
2020-11-17 18:50 ` [Intel-gfx] [PATCH 16/21] drm/i915/adl_s: MCHBAR memory info registers are moved Aditya Swarup
@ 2020-11-17 18:50 ` Aditya Swarup
2020-11-17 18:50 ` [Intel-gfx] [PATCH 18/21] drm/i915/adl_s: Re-use TGL GuC/HuC firmware Aditya Swarup
` (8 subsequent siblings)
25 siblings, 0 replies; 56+ messages in thread
From: Aditya Swarup @ 2020-11-17 18:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Lucas De Marchi <lucas.demarchi@intel.com>
TGL power wells can be re-used for ADL-S with the exception of the fake
power well for TC_COLD, just like DG-1.
Bspec: 53597
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 8b163d804a41..152cf4a6826d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4632,7 +4632,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
* The enabling order will be from lower to higher indexed wells,
* the disabling order is reversed.
*/
- if (IS_DG1(dev_priv)) {
+ if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) {
err = set_power_wells_mask(power_domains, tgl_power_wells,
BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));
} else if (IS_ROCKETLAKE(dev_priv)) {
--
2.27.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* [Intel-gfx] [PATCH 18/21] drm/i915/adl_s: Re-use TGL GuC/HuC firmware
2020-11-17 18:50 [Intel-gfx] [PATCH 00/21] Introduce Alderlake-S Aditya Swarup
` (16 preceding siblings ...)
2020-11-17 18:50 ` [Intel-gfx] [PATCH 17/21] drm/i915/adl_s: Add power wells Aditya Swarup
@ 2020-11-17 18:50 ` Aditya Swarup
2020-11-25 22:52 ` Srivatsa, Anusha
2020-11-17 18:50 ` [Intel-gfx] [PATCH 19/21] drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION Aditya Swarup
` (7 subsequent siblings)
25 siblings, 1 reply; 56+ messages in thread
From: Aditya Swarup @ 2020-11-17 18:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Matt Roper <matthew.d.roper@intel.com>
ADL-S, like RKL, uses the same internal device ID for the GuC and HuC as
TGL did, making them all firmware-compatible. Let's re-use TGL's
firmware for ADL-S.
Bspec: 50668
Cc: John Harrison <John.C.Harrison@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 180c23e2e25e..2d123158df0d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -44,9 +44,11 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
* List of required GuC and HuC binaries per-platform.
* Must be ordered based on platform + revid, from newer to older.
*
- * Note that RKL uses the same firmware as TGL.
+ * Note that RKL and ADL-S have the same GuC/HuC device ID's and use the same
+ * firmware as TGL.
*/
#define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
+ fw_def(ALDERLAKE_S, 0, guc_def(tgl, 49, 0, 1), huc_def(tgl, 7, 5, 0)) \
fw_def(ROCKETLAKE, 0, guc_def(tgl, 49, 0, 1), huc_def(tgl, 7, 5, 0)) \
fw_def(TIGERLAKE, 0, guc_def(tgl, 49, 0, 1), huc_def(tgl, 7, 5, 0)) \
fw_def(JASPERLAKE, 0, guc_def(ehl, 49, 0, 1), huc_def(ehl, 9, 0, 0)) \
--
2.27.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH 18/21] drm/i915/adl_s: Re-use TGL GuC/HuC firmware
2020-11-17 18:50 ` [Intel-gfx] [PATCH 18/21] drm/i915/adl_s: Re-use TGL GuC/HuC firmware Aditya Swarup
@ 2020-11-25 22:52 ` Srivatsa, Anusha
0 siblings, 0 replies; 56+ messages in thread
From: Srivatsa, Anusha @ 2020-11-25 22:52 UTC (permalink / raw)
To: Swarup, Aditya, intel-gfx; +Cc: De Marchi, Lucas
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Aditya Swarup
> Sent: Tuesday, November 17, 2020 10:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
> Subject: [Intel-gfx] [PATCH 18/21] drm/i915/adl_s: Re-use TGL GuC/HuC
> firmware
>
> From: Matt Roper <matthew.d.roper@intel.com>
>
> ADL-S, like RKL, uses the same internal device ID for the GuC and HuC as
> TGL did, making them all firmware-compatible. Let's re-use TGL's firmware
> for ADL-S.
>
> Bspec: 50668
> Cc: John Harrison <John.C.Harrison@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> index 180c23e2e25e..2d123158df0d 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> @@ -44,9 +44,11 @@ void intel_uc_fw_change_status(struct intel_uc_fw
> *uc_fw,
> * List of required GuC and HuC binaries per-platform.
> * Must be ordered based on platform + revid, from newer to older.
> *
> - * Note that RKL uses the same firmware as TGL.
> + * Note that RKL and ADL-S have the same GuC/HuC device ID's and use
> + the same
> + * firmware as TGL.
> */
> #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
> + fw_def(ALDERLAKE_S, 0, guc_def(tgl, 49, 0, 1), huc_def(tgl, 7, 5, 0))
> +\
> fw_def(ROCKETLAKE, 0, guc_def(tgl, 49, 0, 1), huc_def(tgl, 7, 5, 0)) \
> fw_def(TIGERLAKE, 0, guc_def(tgl, 49, 0, 1), huc_def(tgl, 7, 5, 0)) \
> fw_def(JASPERLAKE, 0, guc_def(ehl, 49, 0, 1), huc_def(ehl, 9, 0, 0)) \
> --
> 2.27.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread
* [Intel-gfx] [PATCH 19/21] drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION
2020-11-17 18:50 [Intel-gfx] [PATCH 00/21] Introduce Alderlake-S Aditya Swarup
` (17 preceding siblings ...)
2020-11-17 18:50 ` [Intel-gfx] [PATCH 18/21] drm/i915/adl_s: Re-use TGL GuC/HuC firmware Aditya Swarup
@ 2020-11-17 18:50 ` Aditya Swarup
2020-12-01 18:35 ` Srivatsa, Anusha
2020-11-17 18:50 ` [Intel-gfx] [PATCH 20/21] drm/i915/adl_s: Load DMC Aditya Swarup
` (6 subsequent siblings)
25 siblings, 1 reply; 56+ messages in thread
From: Aditya Swarup @ 2020-11-17 18:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi
From: José Roberto de Souza <jose.souza@intel.com>
- As RKL and ADL-S only have 5 planes, primary and 4 sprites and
the cursor plane, let's group the handling together under
HAS_D12_PLANE_MINIMIZATION.
- Also use macro to select pipe irq fault error mask.
BSpec: 49251
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
drivers/gpu/drm/i915/display/intel_sprite.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
4 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 1e954e2928fe..f65fd937bc55 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -351,7 +351,7 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915)
{
- if (IS_ROCKETLAKE(i915))
+ if (HAS_D12_PLANE_MINIMIZATION(i915))
return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3);
else
return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 817a5102b94f..f8d61785600d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1770,6 +1770,9 @@ extern const struct i915_rev_steppings adls_revids[];
#define INTEL_DISPLAY_ENABLED(dev_priv) \
(drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display)
+#define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
+ IS_ALDERLAKE_S(dev_priv))
+
static inline bool intel_vtd_active(void)
{
#ifdef CONFIG_INTEL_IOMMU
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 758ed4f6c9f3..e39db39cd796 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2246,7 +2246,7 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
{
- if (IS_ROCKETLAKE(dev_priv))
+ if (HAS_D12_PLANE_MINIMIZATION(dev_priv))
return RKL_DE_PIPE_IRQ_FAULT_ERRORS;
else if (INTEL_GEN(dev_priv) >= 11)
return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 64a09954fd54..49d5dac34d51 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -409,7 +409,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
- if (IS_ROCKETLAKE(dev_priv))
+ if (HAS_D12_PLANE_MINIMIZATION(dev_priv))
for_each_pipe(dev_priv, pipe)
runtime->num_sprites[pipe] = 4;
else if (INTEL_GEN(dev_priv) >= 11)
--
2.27.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH 19/21] drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION
2020-11-17 18:50 ` [Intel-gfx] [PATCH 19/21] drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION Aditya Swarup
@ 2020-12-01 18:35 ` Srivatsa, Anusha
0 siblings, 0 replies; 56+ messages in thread
From: Srivatsa, Anusha @ 2020-12-01 18:35 UTC (permalink / raw)
To: Swarup, Aditya, intel-gfx; +Cc: Nikula, Jani, De Marchi, Lucas
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Aditya Swarup
> Sent: Tuesday, November 17, 2020 10:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>
> Subject: [Intel-gfx] [PATCH 19/21] drm/i915/display: Add
> HAS_D12_PLANE_MINIMIZATION
>
> From: José Roberto de Souza <jose.souza@intel.com>
>
> - As RKL and ADL-S only have 5 planes, primary and 4 sprites and
> the cursor plane, let's group the handling together under
> HAS_D12_PLANE_MINIMIZATION.
> - Also use macro to select pipe irq fault error mask.
>
> BSpec: 49251
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_sprite.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 3 +++
> drivers/gpu/drm/i915/i915_irq.c | 2 +-
> drivers/gpu/drm/i915/intel_device_info.c | 2 +-
> 4 files changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 1e954e2928fe..f65fd937bc55 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -351,7 +351,7 @@ int intel_plane_check_src_coordinates(struct
> intel_plane_state *plane_state)
>
> static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915) {
> - if (IS_ROCKETLAKE(i915))
> + if (HAS_D12_PLANE_MINIMIZATION(i915))
> return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3);
> else
> return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5); diff --git
> a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 817a5102b94f..f8d61785600d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1770,6 +1770,9 @@ extern const struct i915_rev_steppings
> adls_revids[]; #define INTEL_DISPLAY_ENABLED(dev_priv) \
> (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)),
> !(dev_priv)->params.disable_display)
>
> +#define HAS_D12_PLANE_MINIMIZATION(dev_priv)
> (IS_ROCKETLAKE(dev_priv) || \
> + IS_ALDERLAKE_S(dev_priv))
> +
> static inline bool intel_vtd_active(void) { #ifdef CONFIG_INTEL_IOMMU
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c index 758ed4f6c9f3..e39db39cd796
> 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2246,7 +2246,7 @@ static u32 gen8_de_port_aux_mask(struct
> drm_i915_private *dev_priv)
>
> static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv) {
> - if (IS_ROCKETLAKE(dev_priv))
> + if (HAS_D12_PLANE_MINIMIZATION(dev_priv))
> return RKL_DE_PIPE_IRQ_FAULT_ERRORS;
> else if (INTEL_GEN(dev_priv) >= 11)
> return GEN11_DE_PIPE_IRQ_FAULT_ERRORS; diff --git
> a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index 64a09954fd54..49d5dac34d51 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -409,7 +409,7 @@ void intel_device_info_runtime_init(struct
> drm_i915_private *dev_priv)
>
> BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) <
> I915_NUM_ENGINES);
>
> - if (IS_ROCKETLAKE(dev_priv))
> + if (HAS_D12_PLANE_MINIMIZATION(dev_priv))
> for_each_pipe(dev_priv, pipe)
> runtime->num_sprites[pipe] = 4;
> else if (INTEL_GEN(dev_priv) >= 11)
> --
> 2.27.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread
* [Intel-gfx] [PATCH 20/21] drm/i915/adl_s: Load DMC
2020-11-17 18:50 [Intel-gfx] [PATCH 00/21] Introduce Alderlake-S Aditya Swarup
` (18 preceding siblings ...)
2020-11-17 18:50 ` [Intel-gfx] [PATCH 19/21] drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION Aditya Swarup
@ 2020-11-17 18:50 ` Aditya Swarup
2020-11-17 18:50 ` [Intel-gfx] [PATCH 21/21] drm/i915/adl_s: Update memory bandwidth parameters Aditya Swarup
` (5 subsequent siblings)
25 siblings, 0 replies; 56+ messages in thread
From: Aditya Swarup @ 2020-11-17 18:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
Load DMC on ADL_S v2.01. This is the first offcial
release of DMC for ADL_S.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
drivers/gpu/drm/i915/display/intel_csr.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
index 67dc64df78a5..db9f219c4b5a 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -40,6 +40,10 @@
#define GEN12_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE
+#define ADLS_CSR_PATH "i915/adls_dmc_ver2_01.bin"
+#define ADLS_CSR_VERSION_REQUIRED CSR_VERSION(2, 1)
+MODULE_FIRMWARE(ADLS_CSR_PATH);
+
#define DG1_CSR_PATH "i915/dg1_dmc_ver2_02.bin"
#define DG1_CSR_VERSION_REQUIRED CSR_VERSION(2, 2)
MODULE_FIRMWARE(DG1_CSR_PATH);
@@ -689,7 +693,11 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
*/
intel_csr_runtime_pm_get(dev_priv);
- if (IS_DG1(dev_priv)) {
+ if (IS_ALDERLAKE_S(dev_priv)) {
+ csr->fw_path = ADLS_CSR_PATH;
+ csr->required_version = ADLS_CSR_VERSION_REQUIRED;
+ csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+ } else if (IS_DG1(dev_priv)) {
csr->fw_path = DG1_CSR_PATH;
csr->required_version = DG1_CSR_VERSION_REQUIRED;
csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
--
2.27.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* [Intel-gfx] [PATCH 21/21] drm/i915/adl_s: Update memory bandwidth parameters
2020-11-17 18:50 [Intel-gfx] [PATCH 00/21] Introduce Alderlake-S Aditya Swarup
` (19 preceding siblings ...)
2020-11-17 18:50 ` [Intel-gfx] [PATCH 20/21] drm/i915/adl_s: Load DMC Aditya Swarup
@ 2020-11-17 18:50 ` Aditya Swarup
2020-11-25 22:46 ` Srivatsa, Anusha
2020-11-18 1:28 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Alderlake-S (rev2) Patchwork
` (4 subsequent siblings)
25 siblings, 1 reply; 56+ messages in thread
From: Aditya Swarup @ 2020-11-17 18:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi
From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Just like RKL, the ADL_S platform also has different memory
characteristics from past platforms. Update the values used
by our memory bandwidth calculations accordingly.
Bspec: 64631
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index bd060404d249..32522ec1ffb9 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -205,6 +205,12 @@ static const struct intel_sa_info rkl_sa_info = {
.displayrtids = 128,
};
+static const struct intel_sa_info adls_sa_info = {
+ .deburst = 16,
+ .deprogbwlimit = 38, /* GB/s */
+ .displayrtids = 256,
+};
+
static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
{
struct intel_qgv_info qi = {};
@@ -317,6 +323,8 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
if (IS_ROCKETLAKE(dev_priv))
icl_get_bw_info(dev_priv, &rkl_sa_info);
+ else if (IS_ALDERLAKE_S(dev_priv))
+ icl_get_bw_info(dev_priv, &adls_sa_info);
else if (IS_GEN(dev_priv, 12))
icl_get_bw_info(dev_priv, &tgl_sa_info);
else if (IS_GEN(dev_priv, 11))
--
2.27.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH 21/21] drm/i915/adl_s: Update memory bandwidth parameters
2020-11-17 18:50 ` [Intel-gfx] [PATCH 21/21] drm/i915/adl_s: Update memory bandwidth parameters Aditya Swarup
@ 2020-11-25 22:46 ` Srivatsa, Anusha
0 siblings, 0 replies; 56+ messages in thread
From: Srivatsa, Anusha @ 2020-11-25 22:46 UTC (permalink / raw)
To: Swarup, Aditya, intel-gfx; +Cc: Nikula, Jani, De Marchi, Lucas
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Aditya Swarup
> Sent: Tuesday, November 17, 2020 10:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>
> Subject: [Intel-gfx] [PATCH 21/21] drm/i915/adl_s: Update memory
> bandwidth parameters
>
> From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
>
> Just like RKL, the ADL_S platform also has different memory characteristics
> from past platforms. Update the values used by our memory bandwidth
> calculations accordingly.
>
> Bspec: 64631
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Tejas Upadhyay
> <tejaskumarx.surendrakumar.upadhyay@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index bd060404d249..32522ec1ffb9 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -205,6 +205,12 @@ static const struct intel_sa_info rkl_sa_info = {
> .displayrtids = 128,
> };
>
> +static const struct intel_sa_info adls_sa_info = {
> + .deburst = 16,
> + .deprogbwlimit = 38, /* GB/s */
> + .displayrtids = 256,
> +};
> +
> static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct
> intel_sa_info *sa) {
> struct intel_qgv_info qi = {};
> @@ -317,6 +323,8 @@ void intel_bw_init_hw(struct drm_i915_private
> *dev_priv)
>
> if (IS_ROCKETLAKE(dev_priv))
> icl_get_bw_info(dev_priv, &rkl_sa_info);
> + else if (IS_ALDERLAKE_S(dev_priv))
> + icl_get_bw_info(dev_priv, &adls_sa_info);
> else if (IS_GEN(dev_priv, 12))
> icl_get_bw_info(dev_priv, &tgl_sa_info);
> else if (IS_GEN(dev_priv, 11))
> --
> 2.27.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Alderlake-S (rev2)
2020-11-17 18:50 [Intel-gfx] [PATCH 00/21] Introduce Alderlake-S Aditya Swarup
` (20 preceding siblings ...)
2020-11-17 18:50 ` [Intel-gfx] [PATCH 21/21] drm/i915/adl_s: Update memory bandwidth parameters Aditya Swarup
@ 2020-11-18 1:28 ` Patchwork
2020-11-18 1:29 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
25 siblings, 0 replies; 56+ messages in thread
From: Patchwork @ 2020-11-18 1:28 UTC (permalink / raw)
To: Aditya Swarup; +Cc: intel-gfx
== Series Details ==
Series: Introduce Alderlake-S (rev2)
URL : https://patchwork.freedesktop.org/series/82917/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b9c32f37d365 drm/i915/dg1: Enable ports
022d6eeef421 drm/i915/tgl: Fix macros for TGL SOC based WA
d26e247df015 drm/i915/adl_s: Add ADL-S platform info and PCI ids
-:90: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#90: FILE: drivers/gpu/drm/i915/i915_drv.h:1620:
+#define IS_ADLS_DISP_REVID(p, since, until) \
+ (IS_ALDERLAKE_S(p) && \
+ adls_revids[INTEL_REVID(p)].disp_stepping >= (since) && \
+ adls_revids[INTEL_REVID(p)].disp_stepping <= (until))
-:95: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#95: FILE: drivers/gpu/drm/i915/i915_drv.h:1625:
+#define IS_ADLS_GT_REVID(p, since, until) \
+ (IS_ALDERLAKE_S(p) && \
+ adls_revids[INTEL_REVID(p)].gt_stepping >= (since) && \
+ adls_revids[INTEL_REVID(p)].gt_stepping <= (until))
-:166: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#166: FILE: include/drm/i915_pciids.h:638:
+#define INTEL_ADLS_IDS(info) \
+ INTEL_VGA_DEVICE(0x4680, info), \
+ INTEL_VGA_DEVICE(0x4681, info), \
+ INTEL_VGA_DEVICE(0x4682, info), \
+ INTEL_VGA_DEVICE(0x4683, info), \
+ INTEL_VGA_DEVICE(0x4690, info), \
+ INTEL_VGA_DEVICE(0x4691, info), \
+ INTEL_VGA_DEVICE(0x4692, info), \
+ INTEL_VGA_DEVICE(0x4693, info), \
+ INTEL_VGA_DEVICE(0x4698, info), \
+ INTEL_VGA_DEVICE(0x4699, info)
-:166: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#166: FILE: include/drm/i915_pciids.h:638:
+#define INTEL_ADLS_IDS(info) \
+ INTEL_VGA_DEVICE(0x4680, info), \
+ INTEL_VGA_DEVICE(0x4681, info), \
+ INTEL_VGA_DEVICE(0x4682, info), \
+ INTEL_VGA_DEVICE(0x4683, info), \
+ INTEL_VGA_DEVICE(0x4690, info), \
+ INTEL_VGA_DEVICE(0x4691, info), \
+ INTEL_VGA_DEVICE(0x4692, info), \
+ INTEL_VGA_DEVICE(0x4693, info), \
+ INTEL_VGA_DEVICE(0x4698, info), \
+ INTEL_VGA_DEVICE(0x4699, info)
total: 1 errors, 0 warnings, 3 checks, 107 lines checked
3db2935953f0 x86/gpu: add ADL_S stolen memory support
59b86438365e drm/i915/adl_s: Add PCH support
51af91e98816 drm/i915/adl_s: Add Interrupt Support
2248efb63de6 drm/i915/adl_s: Add PHYs for Alderlake S
4e420980faab drm/i915/adl_s: Configure DPLL for ADL-S
8ae3c608c0d5 drm/i915/adl_s: Configure Port clock registers for ADL-S
d7994db4541b drm/i915/adl_s: Add HTI support and initialize display for ADL-S
ad1a87bbd43c drm/i915/adl_s: Add adl-s ddc pin mapping
17a523c28460 drm/i915/adl_s: Add vbt port and aux channel settings for adls
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#10:
- ADL-S driver internal mapping uses PORT D, E, F, G for Combo phy B, C, D and E.
total: 0 errors, 1 warnings, 0 checks, 81 lines checked
aa5734095dbb drm/i915/adl_s: Update combo PHY master/slave relationships
3927a843ff1e drm/i915/adl_s: Update PHY_MISC programming
707aff1b0892 drm/i915/adl_s: Add display, gt, ctx and ADL-S
-:130: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#130: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:717:
+ wa_add(wal,
+ FF_MODE2,
total: 0 errors, 0 warnings, 1 checks, 208 lines checked
0074777509e7 drm/i915/adl_s: MCHBAR memory info registers are moved
-:56: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#56: FILE: drivers/gpu/drm/i915/intel_dram.c:189:
+ val = intel_uncore_read(&i915->uncore,
+ ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR);
-:59: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#59: FILE: drivers/gpu/drm/i915/intel_dram.c:192:
+ val = intel_uncore_read(&i915->uncore,
SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
-:67: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#67: FILE: drivers/gpu/drm/i915/intel_dram.c:199:
+ val = intel_uncore_read(&i915->uncore,
+ ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR);
-:70: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#70: FILE: drivers/gpu/drm/i915/intel_dram.c:202:
+ val = intel_uncore_read(&i915->uncore,
SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
-:80: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#80: FILE: drivers/gpu/drm/i915/intel_dram.c:244:
+ val = intel_uncore_read(&i915->uncore,
+ ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR);
-:83: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#83: FILE: drivers/gpu/drm/i915/intel_dram.c:247:
+ val = intel_uncore_read(&i915->uncore,
SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
-:85: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email name mismatch: 'From: Caz Yokoyama <caz.yokoyama@intel.com>' != 'Signed-off-by: Yokoyama, Caz <caz.yokoyama@intel.com>'
total: 0 errors, 1 warnings, 6 checks, 52 lines checked
6f031f0b15b7 drm/i915/adl_s: Add power wells
95ce70b633b1 drm/i915/adl_s: Re-use TGL GuC/HuC firmware
0078b410bdcf drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION
-:44: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#44: FILE: drivers/gpu/drm/i915/i915_drv.h:1773:
+#define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
+ IS_ALDERLAKE_S(dev_priv))
total: 0 errors, 0 warnings, 1 checks, 33 lines checked
0ac2f51c26c7 drm/i915/adl_s: Load DMC
8a6db152da02 drm/i915/adl_s: Update memory bandwidth parameters
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Introduce Alderlake-S (rev2)
2020-11-17 18:50 [Intel-gfx] [PATCH 00/21] Introduce Alderlake-S Aditya Swarup
` (21 preceding siblings ...)
2020-11-18 1:28 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Alderlake-S (rev2) Patchwork
@ 2020-11-18 1:29 ` Patchwork
2020-11-18 1:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
25 siblings, 0 replies; 56+ messages in thread
From: Patchwork @ 2020-11-18 1:29 UTC (permalink / raw)
To: Aditya Swarup; +Cc: intel-gfx
== Series Details ==
Series: Introduce Alderlake-S (rev2)
URL : https://patchwork.freedesktop.org/series/82917/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: expected unsigned int [usertype] *s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216
+./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:864:16: warning: trying to copy expression type 31
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for Introduce Alderlake-S (rev2)
2020-11-17 18:50 [Intel-gfx] [PATCH 00/21] Introduce Alderlake-S Aditya Swarup
` (22 preceding siblings ...)
2020-11-18 1:29 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2020-11-18 1:57 ` Patchwork
2020-11-18 7:53 ` [Intel-gfx] [PATCH 00/21] Introduce Alderlake-S Lucas De Marchi
2020-11-18 15:14 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for Introduce Alderlake-S (rev2) Patchwork
25 siblings, 0 replies; 56+ messages in thread
From: Patchwork @ 2020-11-18 1:57 UTC (permalink / raw)
To: Aditya Swarup; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 6094 bytes --]
== Series Details ==
Series: Introduce Alderlake-S (rev2)
URL : https://patchwork.freedesktop.org/series/82917/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9350 -> Patchwork_18927
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/index.html
New tests
---------
New tests have been introduced between CI_DRM_9350 and Patchwork_18927:
### New CI tests (1) ###
* boot:
- Statuses : 40 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_18927 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@reload:
- fi-byt-j1900: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/fi-byt-j1900/igt@i915_module_load@reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/fi-byt-j1900/igt@i915_module_load@reload.html
- fi-tgl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982] / [k.org#205379])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/fi-tgl-u2/igt@i915_module_load@reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/fi-tgl-u2/igt@i915_module_load@reload.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
- fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
* igt@kms_psr@primary_mmap_gtt:
- fi-tgl-y: [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/fi-tgl-y/igt@kms_psr@primary_mmap_gtt.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/fi-tgl-y/igt@kms_psr@primary_mmap_gtt.html
* igt@prime_vgem@basic-write:
- fi-tgl-y: [PASS][9] -> [DMESG-WARN][10] ([i915#402]) +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/fi-tgl-y/igt@prime_vgem@basic-write.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/fi-tgl-y/igt@prime_vgem@basic-write.html
#### Possible fixes ####
* igt@kms_busy@basic@flip:
- {fi-kbl-7560u}: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/fi-kbl-7560u/igt@kms_busy@basic@flip.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/fi-kbl-7560u/igt@kms_busy@basic@flip.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-icl-u2: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
* igt@kms_pipe_crc_basic@read-crc-pipe-c:
- fi-tgl-y: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/fi-tgl-y/igt@kms_pipe_crc_basic@read-crc-pipe-c.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/fi-tgl-y/igt@kms_pipe_crc_basic@read-crc-pipe-c.html
* igt@vgem_basic@setversion:
- fi-tgl-y: [DMESG-WARN][17] ([i915#402]) -> [PASS][18] +2 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/fi-tgl-y/igt@vgem_basic@setversion.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/fi-tgl-y/igt@vgem_basic@setversion.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
Participating hosts (45 -> 40)
------------------------------
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-blb-e6850 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9350 -> Patchwork_18927
CI-20190529: 20190529
CI_DRM_9350: 3161d1b26b7e1a7cb9146e3f8bd613f901ff5b38 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5855: d9b3c7058efe41e5224dd1e43fac05dc6d049380 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18927: 8a6db152da0270d8f3cb14f6aef8e1bd2c62fd50 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8a6db152da02 drm/i915/adl_s: Update memory bandwidth parameters
0ac2f51c26c7 drm/i915/adl_s: Load DMC
0078b410bdcf drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION
95ce70b633b1 drm/i915/adl_s: Re-use TGL GuC/HuC firmware
6f031f0b15b7 drm/i915/adl_s: Add power wells
0074777509e7 drm/i915/adl_s: MCHBAR memory info registers are moved
707aff1b0892 drm/i915/adl_s: Add display, gt, ctx and ADL-S
3927a843ff1e drm/i915/adl_s: Update PHY_MISC programming
aa5734095dbb drm/i915/adl_s: Update combo PHY master/slave relationships
17a523c28460 drm/i915/adl_s: Add vbt port and aux channel settings for adls
ad1a87bbd43c drm/i915/adl_s: Add adl-s ddc pin mapping
d7994db4541b drm/i915/adl_s: Add HTI support and initialize display for ADL-S
8ae3c608c0d5 drm/i915/adl_s: Configure Port clock registers for ADL-S
4e420980faab drm/i915/adl_s: Configure DPLL for ADL-S
2248efb63de6 drm/i915/adl_s: Add PHYs for Alderlake S
51af91e98816 drm/i915/adl_s: Add Interrupt Support
59b86438365e drm/i915/adl_s: Add PCH support
3db2935953f0 x86/gpu: add ADL_S stolen memory support
d26e247df015 drm/i915/adl_s: Add ADL-S platform info and PCI ids
022d6eeef421 drm/i915/tgl: Fix macros for TGL SOC based WA
b9c32f37d365 drm/i915/dg1: Enable ports
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/index.html
[-- Attachment #1.2: Type: text/html, Size: 7539 bytes --]
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_______________________________________________
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^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH 00/21] Introduce Alderlake-S
2020-11-17 18:50 [Intel-gfx] [PATCH 00/21] Introduce Alderlake-S Aditya Swarup
` (23 preceding siblings ...)
2020-11-18 1:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-11-18 7:53 ` Lucas De Marchi
2020-11-18 15:14 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for Introduce Alderlake-S (rev2) Patchwork
25 siblings, 0 replies; 56+ messages in thread
From: Lucas De Marchi @ 2020-11-18 7:53 UTC (permalink / raw)
To: Aditya Swarup; +Cc: intel-gfx
+Rodrigo, +Joonas
On Tue, Nov 17, 2020 at 10:50:08AM -0800, Aditya Swarup wrote:
>v2 of the patch series to introduce ADL-S.
>
>v1 for the series is posted at:
>https://patchwork.freedesktop.org/series/82917/
>
>This series is rebased after hotplug refactors and review
>comments addressed from v1.
>
>Please ignore the DG1 patch as it is cherry-picked to fix
>conflicts.
>
>Aditya Swarup (8):
> drm/i915/dg1: Enable ports
> drm/i915/tgl: Fix macros for TGL SOC based WA
> drm/i915/adl_s: Configure DPLL for ADL-S
> drm/i915/adl_s: Configure Port clock registers for ADL-S
> drm/i915/adl_s: Add HTI support and initialize display for ADL-S
> drm/i915/adl_s: Add adl-s ddc pin mapping
> drm/i915/adl_s: Add vbt port and aux channel settings for adls
> drm/i915/adl_s: Add display, gt, ctx and ADL-S
>
>Anusha Srivatsa (4):
> drm/i915/adl_s: Add PCH support
> drm/i915/adl_s: Add Interrupt Support
> drm/i915/adl_s: Add PHYs for Alderlake S
> drm/i915/adl_s: Load DMC
>
>Caz Yokoyama (3):
> drm/i915/adl_s: Add ADL-S platform info and PCI ids
> x86/gpu: add ADL_S stolen memory support
> drm/i915/adl_s: MCHBAR memory info registers are moved
>
>José Roberto de Souza (1):
> drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION
>
>Lucas De Marchi (1):
> drm/i915/adl_s: Add power wells
>
>Matt Roper (3):
> drm/i915/adl_s: Update combo PHY master/slave relationships
> drm/i915/adl_s: Update PHY_MISC programming
> drm/i915/adl_s: Re-use TGL GuC/HuC firmware
>
>Tejas Upadhyay (1):
> drm/i915/adl_s: Update memory bandwidth parameters
>
> arch/x86/kernel/early-quirks.c | 1 +
> drivers/gpu/drm/i915/display/intel_bios.c | 70 +++++++++--
> drivers/gpu/drm/i915/display/intel_bw.c | 8 ++
> .../gpu/drm/i915/display/intel_combo_phy.c | 23 +++-
> drivers/gpu/drm/i915/display/intel_csr.c | 10 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 64 ++++++----
> drivers/gpu/drm/i915/display/intel_display.c | 37 +++++-
> .../drm/i915/display/intel_display_power.c | 11 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 38 +++++-
> drivers/gpu/drm/i915/display/intel_hdmi.c | 20 ++-
> drivers/gpu/drm/i915/display/intel_psr.c | 4 +-
> drivers/gpu/drm/i915/display/intel_sprite.c | 8 +-
> drivers/gpu/drm/i915/display/intel_vbt_defs.h | 4 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 119 ++++++++++++------
> drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 4 +-
> drivers/gpu/drm/i915/i915_drv.h | 47 ++++---
> drivers/gpu/drm/i915/i915_irq.c | 5 +-
> drivers/gpu/drm/i915/i915_pci.c | 13 ++
> drivers/gpu/drm/i915/i915_reg.h | 54 +++++++-
> drivers/gpu/drm/i915/intel_device_info.c | 9 +-
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> drivers/gpu/drm/i915/intel_dram.c | 18 ++-
> drivers/gpu/drm/i915/intel_pch.c | 8 +-
> drivers/gpu/drm/i915/intel_pch.h | 3 +
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> include/drm/i915_pciids.h | 13 ++
besides the changes to uC and workarounds, all the rest would go
through dinq. Should we bother creating a topic branch for adl-s?
Lucas De Marchi
> 26 files changed, 464 insertions(+), 130 deletions(-)
>
>--
>2.27.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for Introduce Alderlake-S (rev2)
2020-11-17 18:50 [Intel-gfx] [PATCH 00/21] Introduce Alderlake-S Aditya Swarup
` (24 preceding siblings ...)
2020-11-18 7:53 ` [Intel-gfx] [PATCH 00/21] Introduce Alderlake-S Lucas De Marchi
@ 2020-11-18 15:14 ` Patchwork
25 siblings, 0 replies; 56+ messages in thread
From: Patchwork @ 2020-11-18 15:14 UTC (permalink / raw)
To: Aditya Swarup; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 21632 bytes --]
== Series Details ==
Series: Introduce Alderlake-S (rev2)
URL : https://patchwork.freedesktop.org/series/82917/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9350_full -> Patchwork_18927_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18927_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18927_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18927_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_caching@read-writes:
- shard-hsw: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-hsw2/igt@gem_caching@read-writes.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-hsw4/igt@gem_caching@read-writes.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_userptr_blits@huge-split}:
- shard-hsw: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-hsw2/igt@gem_userptr_blits@huge-split.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-hsw4/igt@gem_userptr_blits@huge-split.html
New tests
---------
New tests have been introduced between CI_DRM_9350_full and Patchwork_18927_full:
### New CI tests (1) ###
* boot:
- Statuses : 199 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_18927_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_reloc@basic-many-active@rcs0:
- shard-hsw: [PASS][5] -> [FAIL][6] ([i915#2389])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-hsw8/igt@gem_exec_reloc@basic-many-active@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-hsw4/igt@gem_exec_reloc@basic-many-active@rcs0.html
* igt@gem_exec_suspend@basic-s3:
- shard-hsw: [PASS][7] -> [FAIL][8] ([i915#1888])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-hsw2/igt@gem_exec_suspend@basic-s3.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-hsw4/igt@gem_exec_suspend@basic-s3.html
* igt@gem_exec_whisper@basic-contexts-forked:
- shard-hsw: [PASS][9] -> [TIMEOUT][10] ([i915#2502])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-hsw2/igt@gem_exec_whisper@basic-contexts-forked.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-hsw4/igt@gem_exec_whisper@basic-contexts-forked.html
* igt@gem_workarounds@suspend-resume:
- shard-apl: [PASS][11] -> [INCOMPLETE][12] ([i915#1635])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-apl3/igt@gem_workarounds@suspend-resume.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-apl1/igt@gem_workarounds@suspend-resume.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen:
- shard-glk: [PASS][13] -> [FAIL][14] ([i915#54])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-glk3/igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-glk6/igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-256x256-offscreen:
- shard-skl: [PASS][15] -> [FAIL][16] ([i915#54])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-skl4/igt@kms_cursor_crc@pipe-b-cursor-256x256-offscreen.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-skl7/igt@kms_cursor_crc@pipe-b-cursor-256x256-offscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#180])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-kbl3/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-kbl7/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
- shard-skl: [PASS][19] -> [DMESG-WARN][20] ([i915#1982] / [i915#2295])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-skl7/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-skl8/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-tglb: [PASS][21] -> [FAIL][22] ([i915#2346])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-tglb5/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-tglb5/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1:
- shard-apl: [PASS][23] -> [FAIL][24] ([i915#1635] / [i915#79])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-apl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-apl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-apl: [PASS][25] -> [DMESG-WARN][26] ([i915#1635] / [i915#1982]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-apl8/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-apl8/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
- shard-glk: [PASS][27] -> [DMESG-WARN][28] ([i915#1982])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-glk5/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-glk5/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary:
- shard-kbl: [PASS][29] -> [DMESG-WARN][30] ([i915#1982]) +2 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite:
- shard-skl: [PASS][31] -> [DMESG-WARN][32] ([i915#1982]) +6 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-skl2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite:
- shard-skl: [PASS][33] -> [FAIL][34] ([i915#49])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [PASS][35] -> [FAIL][36] ([i915#1188])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-skl1/igt@kms_hdr@bpc-switch.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-skl2/igt@kms_hdr@bpc-switch.html
* igt@kms_plane@plane-position-covered-pipe-b-planes:
- shard-skl: [PASS][37] -> [FAIL][38] ([i915#247])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-skl9/igt@kms_plane@plane-position-covered-pipe-b-planes.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-skl4/igt@kms_plane@plane-position-covered-pipe-b-planes.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][39] -> [SKIP][40] ([fdo#109642] / [fdo#111068])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-iclb4/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][41] -> [SKIP][42] ([fdo#109441])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-iclb4/igt@kms_psr@psr2_cursor_render.html
* igt@kms_psr@suspend:
- shard-skl: [PASS][43] -> [INCOMPLETE][44] ([i915#198]) +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-skl4/igt@kms_psr@suspend.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-skl2/igt@kms_psr@suspend.html
* igt@kms_sequence@queue-busy:
- shard-tglb: [PASS][45] -> [DMESG-WARN][46] ([i915#1982]) +3 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-tglb2/igt@kms_sequence@queue-busy.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-tglb6/igt@kms_sequence@queue-busy.html
* igt@perf@polling-parameterized:
- shard-skl: [PASS][47] -> [FAIL][48] ([i915#1542])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-skl6/igt@perf@polling-parameterized.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-skl7/igt@perf@polling-parameterized.html
* igt@prime_vgem@basic-fence-flip:
- shard-hsw: [PASS][49] -> [DMESG-WARN][50] ([i915#1982])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-hsw2/igt@prime_vgem@basic-fence-flip.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-hsw6/igt@prime_vgem@basic-fence-flip.html
#### Possible fixes ####
* igt@gem_eio@in-flight-internal-10ms:
- shard-skl: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-skl4/igt@gem_eio@in-flight-internal-10ms.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-skl2/igt@gem_eio@in-flight-internal-10ms.html
* igt@gem_eio@kms:
- shard-hsw: [INCOMPLETE][53] ([i915#1888] / [i915#2244]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-hsw2/igt@gem_eio@kms.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-hsw4/igt@gem_eio@kms.html
* igt@gem_exec_reloc@basic-many-active@rcs0:
- shard-glk: [FAIL][55] ([i915#2389]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-glk3/igt@gem_exec_reloc@basic-many-active@rcs0.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-glk6/igt@gem_exec_reloc@basic-many-active@rcs0.html
* igt@gem_exec_suspend@basic-s3:
- shard-glk: [FAIL][57] -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-glk6/igt@gem_exec_suspend@basic-s3.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-glk3/igt@gem_exec_suspend@basic-s3.html
- shard-kbl: [DMESG-WARN][59] ([i915#180]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-kbl2/igt@gem_exec_suspend@basic-s3.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-kbl2/igt@gem_exec_suspend@basic-s3.html
* igt@i915_module_load@reload:
- shard-iclb: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-iclb2/igt@i915_module_load@reload.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-iclb4/igt@i915_module_load@reload.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-glk: [DMESG-WARN][63] ([i915#1982]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-glk1/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-glk4/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* {igt@kms_async_flips@test-time-stamp}:
- shard-tglb: [FAIL][65] ([i915#2597]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-tglb1/igt@kms_async_flips@test-time-stamp.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-tglb6/igt@kms_async_flips@test-time-stamp.html
* igt@kms_cursor_crc@pipe-b-cursor-256x85-random:
- shard-skl: [FAIL][67] ([i915#54]) -> [PASS][68] +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-skl4/igt@kms_cursor_crc@pipe-b-cursor-256x85-random.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-skl8/igt@kms_cursor_crc@pipe-b-cursor-256x85-random.html
* igt@kms_cursor_edge_walk@pipe-a-128x128-left-edge:
- shard-hsw: [DMESG-WARN][69] ([i915#1982]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-hsw8/igt@kms_cursor_edge_walk@pipe-a-128x128-left-edge.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-hsw4/igt@kms_cursor_edge_walk@pipe-a-128x128-left-edge.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [FAIL][71] ([i915#2346]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions:
- shard-snb: [FAIL][73] -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-snb6/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-snb5/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions.html
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-ytiled:
- shard-apl: [DMESG-WARN][75] ([i915#1635] / [i915#1982]) -> [PASS][76] +3 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-apl6/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-ytiled.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-apl3/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-ytiled.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt:
- shard-tglb: [DMESG-WARN][77] ([i915#1982]) -> [PASS][78] +2 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][79] ([i915#1188]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-skl9/igt@kms_hdr@bpc-switch-dpms.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-skl4/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [SKIP][81] ([fdo#109441]) -> [PASS][82] +3 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-iclb6/igt@kms_psr@psr2_cursor_mmap_cpu.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@perf_pmu@module-unload:
- shard-skl: [DMESG-WARN][83] ([i915#1982] / [i915#262]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-skl10/igt@perf_pmu@module-unload.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-skl6/igt@perf_pmu@module-unload.html
#### Warnings ####
* igt@gem_softpin@noreloc-s3:
- shard-tglb: [DMESG-WARN][85] ([i915#1436]) -> [INCOMPLETE][86] ([i915#1373] / [i915#1436] / [i915#456])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-tglb7/igt@gem_softpin@noreloc-s3.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-tglb5/igt@gem_softpin@noreloc-s3.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [DMESG-WARN][87] ([i915#1226]) -> [SKIP][88] ([fdo#109349])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-iclb4/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@runner@aborted:
- shard-hsw: [FAIL][89] ([i915#2295] / [i915#2439] / [i915#483]) -> [FAIL][90] ([i915#2295] / [i915#2439])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-hsw1/igt@runner@aborted.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-hsw7/igt@runner@aborted.html
- shard-glk: ([FAIL][91], [FAIL][92]) ([i915#1611] / [i915#2295] / [i915#2439] / [i915#86] / [k.org#202321]) -> ([FAIL][93], [FAIL][94]) ([i915#1611] / [i915#2295] / [i915#2439] / [i915#483] / [i915#86] / [k.org#202321])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-glk2/igt@runner@aborted.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-glk6/igt@runner@aborted.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-glk7/igt@runner@aborted.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-glk3/igt@runner@aborted.html
- shard-skl: [FAIL][95] ([i915#1611] / [i915#2295] / [i915#2439]) -> [FAIL][96] ([i915#1611] / [i915#2295] / [i915#2439] / [i915#483])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-skl6/igt@runner@aborted.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/shard-skl9/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226
[i915#1373]: https://gitlab.freedesktop.org/drm/intel/issues/1373
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1611]: https://gitlab.freedesktop.org/drm/intel/issues/1611
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2244]: https://gitlab.freedesktop.org/drm/intel/issues/2244
[i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
[i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439
[i915#247]: https://gitlab.freedesktop.org/drm/intel/issues/247
[i915#2502]: https://gitlab.freedesktop.org/drm/intel/issues/2502
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2597]: https://gitlab.freedesktop.org/drm/intel/issues/2597
[i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
[i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
[i915#483]: https://gitlab.freedesktop.org/drm/intel/issues/483
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#86]: https://gitlab.freedesktop.org/drm/intel/issues/86
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_9350 -> Patchwork_18927
CI-20190529: 20190529
CI_DRM_9350: 3161d1b26b7e1a7cb9146e3f8bd613f901ff5b38 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5855: d9b3c7058efe41e5224dd1e43fac05dc6d049380 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18927: 8a6db152da0270d8f3cb14f6aef8e1bd2c62fd50 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18927/index.html
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