All of lore.kernel.org
 help / color / mirror / Atom feed
From: Ulrich Hecht <uli+renesas@fpond.eu>
To: linux-renesas-soc@vger.kernel.org
Cc: wsa@the-dreams.de, geert@linux-m68k.org, hoai.luu.ub@renesas.com,
	Ulrich Hecht <uli+renesas@fpond.eu>
Subject: [PATCH 10/11] pinctrl: renesas: r8a779a0: Add TMU pins, groups and functions
Date: Thu, 26 Nov 2020 18:21:53 +0100	[thread overview]
Message-ID: <20201126172154.25625-11-uli+renesas@fpond.eu> (raw)
In-Reply-To: <20201126172154.25625-1-uli+renesas@fpond.eu>

This patch adds TMU TCLK1-4 pins, groups and functions to the R8A779A0
(V3U) SoC.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
---
 drivers/pinctrl/renesas/pfc-r8a779a0.c | 47 ++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c
index a83b6fa9ab9e..4aa725b3fbca 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779a0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c
@@ -2502,6 +2502,39 @@ static const unsigned int scif_clk_mux[] = {
 	SCIF_CLK_MARK,
 };
 
+/* - TMU -------------------------------------------------------------------- */
+static const unsigned int tmu_tclk1_pins[] = {
+	/* TCLK1 */
+	RCAR_GP_PIN(2, 23),
+};
+static const unsigned int tmu_tclk1_mux[] = {
+	TCLK1_MARK,
+};
+
+static const unsigned int tmu_tclk2_pins[] = {
+	/* TCLK2 */
+	RCAR_GP_PIN(2, 24),
+};
+static const unsigned int tmu_tclk2_mux[] = {
+	TCLK2_MARK,
+};
+
+static const unsigned int tmu_tclk3_pins[] = {
+	/* TCLK3 */
+	RCAR_GP_PIN(2, 11),
+};
+static const unsigned int tmu_tclk3_mux[] = {
+	TCLK3_MARK,
+};
+
+static const unsigned int tmu_tclk4_pins[] = {
+	/* TCLK4 */
+	RCAR_GP_PIN(2, 12),
+};
+static const unsigned int tmu_tclk4_mux[] = {
+	TCLK4_MARK,
+};
+
 static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(avb0_link),
 	SH_PFC_PIN_GROUP(avb0_magic),
@@ -2666,6 +2699,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(scif4_clk),
 	SH_PFC_PIN_GROUP(scif4_ctrl),
 	SH_PFC_PIN_GROUP(scif_clk),
+
+	SH_PFC_PIN_GROUP(tmu_tclk1),
+	SH_PFC_PIN_GROUP(tmu_tclk2),
+	SH_PFC_PIN_GROUP(tmu_tclk3),
+	SH_PFC_PIN_GROUP(tmu_tclk4),
 };
 
 static const char * const avb0_groups[] = {
@@ -2952,6 +2990,13 @@ static const char * const scif_clk_groups[] = {
 	"scif_clk",
 };
 
+static const char * const tmu_groups[] = {
+	"tmu_tclk1",
+	"tmu_tclk2",
+	"tmu_tclk3",
+	"tmu_tclk4",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(avb0),
 	SH_PFC_FUNCTION(avb1),
@@ -3008,6 +3053,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(scif3),
 	SH_PFC_FUNCTION(scif4),
 	SH_PFC_FUNCTION(scif_clk),
+
+	SH_PFC_FUNCTION(tmu),
 };
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-- 
2.20.1


  parent reply	other threads:[~2020-11-26 17:28 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-26 17:21 [PATCH 00/11] pinctrl: renesas: R8A779A0 (V3U) device support Ulrich Hecht
2020-11-26 17:21 ` [PATCH 01/11] pinctrl: renesas: r8a779a0: Add EtherAVB pins, groups and functions Ulrich Hecht
2020-11-27 14:44   ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 02/11] pinctrl: renesas: r8a779a0: Add CANFD " Ulrich Hecht
2020-11-27 15:35   ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 03/11] pinctrl: renesas: r8a779a0: Add DU pins, groups and function Ulrich Hecht
2020-11-27 15:50   ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 04/11] pinctrl: renesas: r8a779a0: Add HSCIF pins, groups and functions Ulrich Hecht
2020-11-30 13:31   ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 05/11] pinctrl: renesas: r8a779a0: Add INTC-EX pins, groups and function Ulrich Hecht
2020-11-30 13:33   ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 06/11] pinctrl: renesas: r8a779a0: Add MMC pins, groups and functions Ulrich Hecht
2020-11-30 13:37   ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 07/11] pinctrl: renesas: r8a779a0: Add MSIOF " Ulrich Hecht
2020-11-30 13:43   ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 08/11] pinctrl: renesas: r8a779a0: Add PWM " Ulrich Hecht
2020-11-30 13:45   ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 09/11] pinctrl: renesas: r8a779a0: Add QSPI pins, groups, " Ulrich Hecht
2020-11-30 13:49   ` Geert Uytterhoeven
2020-11-26 17:21 ` Ulrich Hecht [this message]
2020-11-30 13:57   ` [PATCH 10/11] pinctrl: renesas: r8a779a0: Add TMU pins, groups " Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 11/11] pinctrl: renesas: r8a779a0: Add TPU " Ulrich Hecht
2020-11-30 13:59   ` Geert Uytterhoeven
2020-11-27 10:33 ` [PATCH 00/11] pinctrl: renesas: R8A779A0 (V3U) device support Geert Uytterhoeven
2020-11-30  8:24   ` Ulrich Hecht
2020-11-30  9:01     ` Geert Uytterhoeven

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20201126172154.25625-11-uli+renesas@fpond.eu \
    --to=uli+renesas@fpond.eu \
    --cc=geert@linux-m68k.org \
    --cc=hoai.luu.ub@renesas.com \
    --cc=linux-renesas-soc@vger.kernel.org \
    --cc=wsa@the-dreams.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.