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From: Ulrich Hecht <uli+renesas@fpond.eu>
To: linux-renesas-soc@vger.kernel.org
Cc: wsa@the-dreams.de, geert@linux-m68k.org, hoai.luu.ub@renesas.com,
	Ulrich Hecht <uli+renesas@fpond.eu>
Subject: [PATCH 05/11] pinctrl: renesas: r8a779a0: Add INTC-EX pins, groups and function
Date: Thu, 26 Nov 2020 18:21:48 +0100	[thread overview]
Message-ID: <20201126172154.25625-6-uli+renesas@fpond.eu> (raw)
In-Reply-To: <20201126172154.25625-1-uli+renesas@fpond.eu>

Add pins, groups, and function for the Interrupt Controller for External
Devices (INTC-EX) on the R-Car R8A779A0 (V3U) SoC.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
---
 drivers/pinctrl/renesas/pfc-r8a779a0.c | 62 ++++++++++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c
index 7b1fccf14956..8b5313a7917a 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779a0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c
@@ -1939,6 +1939,50 @@ static const unsigned int i2c6_mux[] = {
 	GP2_15_MARK, GP2_14_MARK,
 };
 
+/* - INTC-EX ---------------------------------------------------------------- */
+static const unsigned int intc_ex_irq0_pins[] = {
+	/* IRQ0 */
+	RCAR_GP_PIN(1, 24),
+};
+static const unsigned int intc_ex_irq0_mux[] = {
+	IRQ0_MARK,
+};
+static const unsigned int intc_ex_irq1_pins[] = {
+	/* IRQ1 */
+	RCAR_GP_PIN(1, 25),
+};
+static const unsigned int intc_ex_irq1_mux[] = {
+	IRQ1_MARK,
+};
+static const unsigned int intc_ex_irq2_pins[] = {
+	/* IRQ2 */
+	RCAR_GP_PIN(1, 26),
+};
+static const unsigned int intc_ex_irq2_mux[] = {
+	IRQ2_MARK,
+};
+static const unsigned int intc_ex_irq3_pins[] = {
+	/* IRQ3 */
+	RCAR_GP_PIN(1, 27),
+};
+static const unsigned int intc_ex_irq3_mux[] = {
+	IRQ3_MARK,
+};
+static const unsigned int intc_ex_irq4_pins[] = {
+	/* IRQ4 */
+	RCAR_GP_PIN(2, 14),
+};
+static const unsigned int intc_ex_irq4_mux[] = {
+	IRQ4_MARK,
+};
+static const unsigned int intc_ex_irq5_pins[] = {
+	/* IRQ5 */
+	RCAR_GP_PIN(2, 15),
+};
+static const unsigned int intc_ex_irq5_mux[] = {
+	IRQ5_MARK,
+};
+
 /* - SCIF0 ------------------------------------------------------------------ */
 static const unsigned int scif0_data_pins[] = {
 	/* RX0, TX0 */
@@ -2138,6 +2182,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(i2c5),
 	SH_PFC_PIN_GROUP(i2c6),
 
+	SH_PFC_PIN_GROUP(intc_ex_irq0),
+	SH_PFC_PIN_GROUP(intc_ex_irq1),
+	SH_PFC_PIN_GROUP(intc_ex_irq2),
+	SH_PFC_PIN_GROUP(intc_ex_irq3),
+	SH_PFC_PIN_GROUP(intc_ex_irq4),
+	SH_PFC_PIN_GROUP(intc_ex_irq5),
+
 	SH_PFC_PIN_GROUP(scif0_data),
 	SH_PFC_PIN_GROUP(scif0_clk),
 	SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -2322,6 +2373,15 @@ static const char * const i2c6_groups[] = {
 	"i2c6",
 };
 
+static const char * const intc_ex_groups[] = {
+	"intc_ex_irq0",
+	"intc_ex_irq1",
+	"intc_ex_irq2",
+	"intc_ex_irq3",
+	"intc_ex_irq4",
+	"intc_ex_irq5",
+};
+
 static const char * const scif0_groups[] = {
 	"scif0_data",
 	"scif0_clk",
@@ -2383,6 +2443,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(i2c5),
 	SH_PFC_FUNCTION(i2c6),
 
+	SH_PFC_FUNCTION(intc_ex),
+
 	SH_PFC_FUNCTION(scif0),
 	SH_PFC_FUNCTION(scif1),
 	SH_PFC_FUNCTION(scif3),
-- 
2.20.1


  parent reply	other threads:[~2020-11-26 17:28 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-26 17:21 [PATCH 00/11] pinctrl: renesas: R8A779A0 (V3U) device support Ulrich Hecht
2020-11-26 17:21 ` [PATCH 01/11] pinctrl: renesas: r8a779a0: Add EtherAVB pins, groups and functions Ulrich Hecht
2020-11-27 14:44   ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 02/11] pinctrl: renesas: r8a779a0: Add CANFD " Ulrich Hecht
2020-11-27 15:35   ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 03/11] pinctrl: renesas: r8a779a0: Add DU pins, groups and function Ulrich Hecht
2020-11-27 15:50   ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 04/11] pinctrl: renesas: r8a779a0: Add HSCIF pins, groups and functions Ulrich Hecht
2020-11-30 13:31   ` Geert Uytterhoeven
2020-11-26 17:21 ` Ulrich Hecht [this message]
2020-11-30 13:33   ` [PATCH 05/11] pinctrl: renesas: r8a779a0: Add INTC-EX pins, groups and function Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 06/11] pinctrl: renesas: r8a779a0: Add MMC pins, groups and functions Ulrich Hecht
2020-11-30 13:37   ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 07/11] pinctrl: renesas: r8a779a0: Add MSIOF " Ulrich Hecht
2020-11-30 13:43   ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 08/11] pinctrl: renesas: r8a779a0: Add PWM " Ulrich Hecht
2020-11-30 13:45   ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 09/11] pinctrl: renesas: r8a779a0: Add QSPI pins, groups, " Ulrich Hecht
2020-11-30 13:49   ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 10/11] pinctrl: renesas: r8a779a0: Add TMU pins, groups " Ulrich Hecht
2020-11-30 13:57   ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 11/11] pinctrl: renesas: r8a779a0: Add TPU " Ulrich Hecht
2020-11-30 13:59   ` Geert Uytterhoeven
2020-11-27 10:33 ` [PATCH 00/11] pinctrl: renesas: R8A779A0 (V3U) device support Geert Uytterhoeven
2020-11-30  8:24   ` Ulrich Hecht
2020-11-30  9:01     ` Geert Uytterhoeven

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