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From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Ulrich Hecht <uli+renesas@fpond.eu>
Cc: Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
	Wolfram Sang <wsa@the-dreams.de>,
	hoai.luu.ub@renesas.com
Subject: Re: [PATCH 03/11] pinctrl: renesas: r8a779a0: Add DU pins, groups and function
Date: Fri, 27 Nov 2020 16:50:28 +0100	[thread overview]
Message-ID: <CAMuHMdXQc2fHMV4Lb+1cGKyCN=NUTE+Eze4ad9mTmbmXoG+K6A@mail.gmail.com> (raw)
In-Reply-To: <20201126172154.25625-4-uli+renesas@fpond.eu>

Hi Uli,

On Thu, Nov 26, 2020 at 6:22 PM Ulrich Hecht <uli+renesas@fpond.eu> wrote:
> This patch adds DU pins, groups and function for the R8A779A0 (V3U) SoC.
> Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>

Thanks for your patch!

> --- a/drivers/pinctrl/renesas/pfc-r8a779a0.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c
> @@ -1736,6 +1736,53 @@ static const unsigned int canfd_clk_mux[] = {
>         CAN_CLK_MARK,
>  };
>
> +/* - DU --------------------------------------------------------------------- */
> +static const unsigned int du_rgb888_pins[] = {
> +       /* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */
> +       RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
> +       RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
> +       RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
> +       RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
> +       RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
> +       RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
> +};
> +static const unsigned int du_rgb888_mux[] = {
> +       DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
> +       DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
> +       DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
> +       DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
> +       DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
> +       DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
> +};
> +static const unsigned int du_clk_out_pins[] = {
> +       /* DU_DOTCLKOUT */
> +       RCAR_GP_PIN(1, 24),
> +};
> +static const unsigned int du_clk_out_mux[] = {
> +       DU_DOTCLKOUT_MARK,
> +};
> +static const unsigned int du_oddf_pins[] = {
> +       /* DU_EXODDF/DU_ODDF/DISP/CDE */
> +       RCAR_GP_PIN(1, 27),
> +};
> +static const unsigned int du_oddf_mux[] = {
> +       DU_ODDF_DISP_CDE_MARK,
> +};
> +static const unsigned int du_cde_pins[] = {
> +       /* DU_CDE */
> +       RCAR_GP_PIN(1, 27),
> +};
> +static const unsigned int du_cde_mux[] = {
> +       DU_ODDF_DISP_CDE_MARK,
> +};
> +static const unsigned int du_disp_pins[] = {
> +       /* DU_DISP */
> +       RCAR_GP_PIN(1, 27),
> +};
> +static const unsigned int du_disp_mux[] = {
> +       DU_ODDF_DISP_CDE_MARK,
> +};

With not-yet-submitted debug checks:

    r8a779a0_pfc: groups du_cde can be an alias for du_oddf
    r8a779a0_pfc: groups du_disp can be an alias for du_oddf
    r8a779a0_pfc: groups du_disp can be an alias for du_cde

Do we need all three?

> @@ -2103,6 +2156,15 @@ static const char * const canfd_clk_groups[] = {
>         "canfd_clk",
>  };
>
> +static const char * const du_groups[] = {
> +       "du_rgb888",
> +       "du_clk_out",
> +       "du_sync",

With CONFIG_DEBUG_PINCTRL=y:

    r8a779a0_pfc: function du: group du_sync not found

And indeed, the sync group with the HSYNC (GP1_25) and VSYNC (GP1_26)
pins is missing.

With the above fixed:

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

  reply	other threads:[~2020-11-27 15:50 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-26 17:21 [PATCH 00/11] pinctrl: renesas: R8A779A0 (V3U) device support Ulrich Hecht
2020-11-26 17:21 ` [PATCH 01/11] pinctrl: renesas: r8a779a0: Add EtherAVB pins, groups and functions Ulrich Hecht
2020-11-27 14:44   ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 02/11] pinctrl: renesas: r8a779a0: Add CANFD " Ulrich Hecht
2020-11-27 15:35   ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 03/11] pinctrl: renesas: r8a779a0: Add DU pins, groups and function Ulrich Hecht
2020-11-27 15:50   ` Geert Uytterhoeven [this message]
2020-11-26 17:21 ` [PATCH 04/11] pinctrl: renesas: r8a779a0: Add HSCIF pins, groups and functions Ulrich Hecht
2020-11-30 13:31   ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 05/11] pinctrl: renesas: r8a779a0: Add INTC-EX pins, groups and function Ulrich Hecht
2020-11-30 13:33   ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 06/11] pinctrl: renesas: r8a779a0: Add MMC pins, groups and functions Ulrich Hecht
2020-11-30 13:37   ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 07/11] pinctrl: renesas: r8a779a0: Add MSIOF " Ulrich Hecht
2020-11-30 13:43   ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 08/11] pinctrl: renesas: r8a779a0: Add PWM " Ulrich Hecht
2020-11-30 13:45   ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 09/11] pinctrl: renesas: r8a779a0: Add QSPI pins, groups, " Ulrich Hecht
2020-11-30 13:49   ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 10/11] pinctrl: renesas: r8a779a0: Add TMU pins, groups " Ulrich Hecht
2020-11-30 13:57   ` Geert Uytterhoeven
2020-11-26 17:21 ` [PATCH 11/11] pinctrl: renesas: r8a779a0: Add TPU " Ulrich Hecht
2020-11-30 13:59   ` Geert Uytterhoeven
2020-11-27 10:33 ` [PATCH 00/11] pinctrl: renesas: R8A779A0 (V3U) device support Geert Uytterhoeven
2020-11-30  8:24   ` Ulrich Hecht
2020-11-30  9:01     ` Geert Uytterhoeven

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