From: Anshuman Gupta <anshuman.gupta@intel.com> To: intel-gfx@lists.freedesktop.org Cc: imre.deak@intel.com, ville.syrjala@linux.intel.com, Anshuman Gupta <anshuman.gupta@intel.com>, stable@vger.kernel.org Subject: [RFC 2/2] drm/i915/display: Protect pipe_update against dc3co exit Date: Mon, 30 Nov 2020 14:46:46 +0530 [thread overview] Message-ID: <20201130091646.25576-3-anshuman.gupta@intel.com> (raw) In-Reply-To: <20201130091646.25576-1-anshuman.gupta@intel.com> At usual case DC3CO exit happen automatically by DMC f/w whenever PSR2 clears idle. This happens smoothly by DMC f/w to work with flips. But there are certain scenario where DC3CO Disallowed by driver asynchronous with flips. In such scenario display engine could be already in DC3CO state and driver has disallowed it, It initiates DC3CO exit sequence in DMC f/w which requires a dc3co exit delay of 200us in driver. It requires to protect intel_pipe_update_{update_end} with dc3co exit delay. Cc: Imre Deak <imre.deak@intel.com> Cc: <stable@vger.kernel.org> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ba26545392bc..3b81b98c0daf 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -15924,6 +15924,8 @@ static void intel_update_crtc(struct intel_atomic_state *state, else intel_fbc_enable(state, crtc); + /* Protect intel_pipe_update_{start,end} with power_domians lock */ + mutex_lock(&dev_priv->power_domains.lock); /* Perform vblank evasion around commit operation */ intel_pipe_update_start(new_crtc_state); @@ -15935,6 +15937,7 @@ static void intel_update_crtc(struct intel_atomic_state *state, i9xx_update_planes_on_crtc(state, crtc); intel_pipe_update_end(new_crtc_state); + mutex_unlock(&dev_prive->power_domains.lock); /* * We usually enable FIFO underrun interrupts as part of the -- 2.26.2
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From: Anshuman Gupta <anshuman.gupta@intel.com> To: intel-gfx@lists.freedesktop.org Cc: stable@vger.kernel.org Subject: [Intel-gfx] [RFC 2/2] drm/i915/display: Protect pipe_update against dc3co exit Date: Mon, 30 Nov 2020 14:46:46 +0530 [thread overview] Message-ID: <20201130091646.25576-3-anshuman.gupta@intel.com> (raw) In-Reply-To: <20201130091646.25576-1-anshuman.gupta@intel.com> At usual case DC3CO exit happen automatically by DMC f/w whenever PSR2 clears idle. This happens smoothly by DMC f/w to work with flips. But there are certain scenario where DC3CO Disallowed by driver asynchronous with flips. In such scenario display engine could be already in DC3CO state and driver has disallowed it, It initiates DC3CO exit sequence in DMC f/w which requires a dc3co exit delay of 200us in driver. It requires to protect intel_pipe_update_{update_end} with dc3co exit delay. Cc: Imre Deak <imre.deak@intel.com> Cc: <stable@vger.kernel.org> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ba26545392bc..3b81b98c0daf 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -15924,6 +15924,8 @@ static void intel_update_crtc(struct intel_atomic_state *state, else intel_fbc_enable(state, crtc); + /* Protect intel_pipe_update_{start,end} with power_domians lock */ + mutex_lock(&dev_priv->power_domains.lock); /* Perform vblank evasion around commit operation */ intel_pipe_update_start(new_crtc_state); @@ -15935,6 +15937,7 @@ static void intel_update_crtc(struct intel_atomic_state *state, i9xx_update_planes_on_crtc(state, crtc); intel_pipe_update_end(new_crtc_state); + mutex_unlock(&dev_prive->power_domains.lock); /* * We usually enable FIFO underrun interrupts as part of the -- 2.26.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-11-30 9:31 UTC|newest] Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-11-30 9:16 [Intel-gfx] [RFC 0/2] Display glitches fixes Anshuman Gupta 2020-11-30 9:16 ` [Intel-gfx] [RFC 1/2] drm/i915/dp: optimize pps_lock wherever required Anshuman Gupta 2020-11-30 9:16 ` Anshuman Gupta [this message] 2020-11-30 9:16 ` [Intel-gfx] [RFC 2/2] drm/i915/display: Protect pipe_update against dc3co exit Anshuman Gupta 2020-11-30 15:28 ` Imre Deak 2020-11-30 15:28 ` [Intel-gfx] " Imre Deak 2020-11-30 16:16 ` Anshuman Gupta 2020-11-30 16:16 ` [Intel-gfx] " Anshuman Gupta 2020-12-04 8:10 ` Anshuman Gupta 2020-12-04 8:10 ` [Intel-gfx] " Anshuman Gupta 2020-12-04 15:51 ` Ville Syrjälä 2020-12-04 15:51 ` [Intel-gfx] " Ville Syrjälä 2020-12-07 7:57 ` Anshuman Gupta 2020-12-07 7:57 ` [Intel-gfx] " Anshuman Gupta 2020-12-08 9:11 ` Anshuman Gupta 2020-12-08 9:11 ` [Intel-gfx] " Anshuman Gupta 2020-11-30 15:50 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Display glitches fixes Patchwork
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