From: Anshuman Gupta <anshuman.gupta@intel.com> To: Imre Deak <imre.deak@intel.com> Cc: intel-gfx@lists.freedesktop.org, ville.syrjala@linux.intel.com, stable@vger.kernel.org Subject: Re: [RFC 2/2] drm/i915/display: Protect pipe_update against dc3co exit Date: Mon, 30 Nov 2020 21:46:59 +0530 [thread overview] Message-ID: <20201130161658.GA30377@intel.com> (raw) In-Reply-To: <20201130152832.GB2348711@ideak-desk.fi.intel.com> On 2020-11-30 at 17:28:32 +0200, Imre Deak wrote: > On Mon, Nov 30, 2020 at 02:46:46PM +0530, Anshuman Gupta wrote: > > At usual case DC3CO exit happen automatically by DMC f/w whenever > > PSR2 clears idle. This happens smoothly by DMC f/w to work with flips. > > But there are certain scenario where DC3CO Disallowed by driver > > asynchronous with flips. In such scenario display engine could > > be already in DC3CO state and driver has disallowed it, > > It initiates DC3CO exit sequence in DMC f/w which requires a > > dc3co exit delay of 200us in driver. > > It requires to protect intel_pipe_update_{update_end} with > > dc3co exit delay. > > > > Cc: Imre Deak <imre.deak@intel.com> > > Cc: <stable@vger.kernel.org> > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> > > To make sure that it doesn't hide the root cause (or affects unrelated > platforms), I'd only add locking around DC3co changes with a new lock, > using lock/unlock helpers in intel_display_power.c called from > intel_pipe_update_start/end. > > Also please submit this patch separately, w/o the optimization in patch > 1/2, so we know that this change fixes the problem. Thanks imre for review comments, i will send a new patch with review comments fixed. Anshuman Gupta. > > --Imre > > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > index ba26545392bc..3b81b98c0daf 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -15924,6 +15924,8 @@ static void intel_update_crtc(struct intel_atomic_state *state, > > else > > intel_fbc_enable(state, crtc); > > > > + /* Protect intel_pipe_update_{start,end} with power_domians lock */ > > + mutex_lock(&dev_priv->power_domains.lock); > > /* Perform vblank evasion around commit operation */ > > intel_pipe_update_start(new_crtc_state); > > > > @@ -15935,6 +15937,7 @@ static void intel_update_crtc(struct intel_atomic_state *state, > > i9xx_update_planes_on_crtc(state, crtc); > > > > intel_pipe_update_end(new_crtc_state); > > + mutex_unlock(&dev_prive->power_domains.lock); > > > > /* > > * We usually enable FIFO underrun interrupts as part of the > > -- > > 2.26.2 > >
WARNING: multiple messages have this Message-ID (diff)
From: Anshuman Gupta <anshuman.gupta@intel.com> To: Imre Deak <imre.deak@intel.com> Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org Subject: Re: [Intel-gfx] [RFC 2/2] drm/i915/display: Protect pipe_update against dc3co exit Date: Mon, 30 Nov 2020 21:46:59 +0530 [thread overview] Message-ID: <20201130161658.GA30377@intel.com> (raw) In-Reply-To: <20201130152832.GB2348711@ideak-desk.fi.intel.com> On 2020-11-30 at 17:28:32 +0200, Imre Deak wrote: > On Mon, Nov 30, 2020 at 02:46:46PM +0530, Anshuman Gupta wrote: > > At usual case DC3CO exit happen automatically by DMC f/w whenever > > PSR2 clears idle. This happens smoothly by DMC f/w to work with flips. > > But there are certain scenario where DC3CO Disallowed by driver > > asynchronous with flips. In such scenario display engine could > > be already in DC3CO state and driver has disallowed it, > > It initiates DC3CO exit sequence in DMC f/w which requires a > > dc3co exit delay of 200us in driver. > > It requires to protect intel_pipe_update_{update_end} with > > dc3co exit delay. > > > > Cc: Imre Deak <imre.deak@intel.com> > > Cc: <stable@vger.kernel.org> > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> > > To make sure that it doesn't hide the root cause (or affects unrelated > platforms), I'd only add locking around DC3co changes with a new lock, > using lock/unlock helpers in intel_display_power.c called from > intel_pipe_update_start/end. > > Also please submit this patch separately, w/o the optimization in patch > 1/2, so we know that this change fixes the problem. Thanks imre for review comments, i will send a new patch with review comments fixed. Anshuman Gupta. > > --Imre > > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > index ba26545392bc..3b81b98c0daf 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -15924,6 +15924,8 @@ static void intel_update_crtc(struct intel_atomic_state *state, > > else > > intel_fbc_enable(state, crtc); > > > > + /* Protect intel_pipe_update_{start,end} with power_domians lock */ > > + mutex_lock(&dev_priv->power_domains.lock); > > /* Perform vblank evasion around commit operation */ > > intel_pipe_update_start(new_crtc_state); > > > > @@ -15935,6 +15937,7 @@ static void intel_update_crtc(struct intel_atomic_state *state, > > i9xx_update_planes_on_crtc(state, crtc); > > > > intel_pipe_update_end(new_crtc_state); > > + mutex_unlock(&dev_prive->power_domains.lock); > > > > /* > > * We usually enable FIFO underrun interrupts as part of the > > -- > > 2.26.2 > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-11-30 16:31 UTC|newest] Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-11-30 9:16 [Intel-gfx] [RFC 0/2] Display glitches fixes Anshuman Gupta 2020-11-30 9:16 ` [Intel-gfx] [RFC 1/2] drm/i915/dp: optimize pps_lock wherever required Anshuman Gupta 2020-11-30 9:16 ` [RFC 2/2] drm/i915/display: Protect pipe_update against dc3co exit Anshuman Gupta 2020-11-30 9:16 ` [Intel-gfx] " Anshuman Gupta 2020-11-30 15:28 ` Imre Deak 2020-11-30 15:28 ` [Intel-gfx] " Imre Deak 2020-11-30 16:16 ` Anshuman Gupta [this message] 2020-11-30 16:16 ` Anshuman Gupta 2020-12-04 8:10 ` Anshuman Gupta 2020-12-04 8:10 ` [Intel-gfx] " Anshuman Gupta 2020-12-04 15:51 ` Ville Syrjälä 2020-12-04 15:51 ` [Intel-gfx] " Ville Syrjälä 2020-12-07 7:57 ` Anshuman Gupta 2020-12-07 7:57 ` [Intel-gfx] " Anshuman Gupta 2020-12-08 9:11 ` Anshuman Gupta 2020-12-08 9:11 ` [Intel-gfx] " Anshuman Gupta 2020-11-30 15:50 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Display glitches fixes Patchwork
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