From: Andrew Lunn <andrew@lunn.ch> To: Steen Hegelund <steen.hegelund@microchip.com> Cc: Kishon Vijay Abraham I <kishon@ti.com>, Vinod Koul <vkoul@kernel.org>, linux-arm-kernel@lists.infradead.org, Alexandre Belloni <alexandre.belloni@bootlin.com>, Lars Povlsen <lars.povlsen@microchip.com>, Bjarni Jonasson <bjarni.jonasson@microchip.com>, Microchip UNG Driver List <UNGLinuxDriver@microchip.com>, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Russell King <rmk+kernel@armlinux.org.uk> Subject: Re: [PATCH v8 3/4] phy: Add Sparx5 ethernet serdes PHY driver Date: Thu, 3 Dec 2020 22:52:53 +0100 [thread overview] Message-ID: <20201203215253.GL2333853@lunn.ch> (raw) In-Reply-To: <20201203103015.3735373-4-steen.hegelund@microchip.com> > +/* map from SD25G28 interface width to configuration value */ > +static u8 sd25g28_get_iw_setting(const u8 interface_width) > +{ > + switch (interface_width) { > + case 10: return 0; > + case 16: return 1; > + case 32: return 3; > + case 40: return 4; > + case 64: return 5; > + default: > + pr_err("%s: Illegal value %d for interface width\n", > + __func__, interface_width); Please make use of dev_err(phy->dev, so we know which PHY has configuration problems. > +static int sparx5_serdes_validate(struct phy *phy, enum phy_mode mode, > + int submode, > + union phy_configure_opts *opts) > +{ > + struct sparx5_serdes_macro *macro = phy_get_drvdata(phy); > + struct sparx5_serdes_private *priv = macro->priv; > + u32 value, analog_sd; > + > + if (mode != PHY_MODE_ETHERNET) > + return -EINVAL; > + > + switch (submode) { > + case PHY_INTERFACE_MODE_1000BASEX: > + case PHY_INTERFACE_MODE_SGMII: > + case PHY_INTERFACE_MODE_QSGMII: > + case PHY_INTERFACE_MODE_10GBASER: > + break; > + default: > + return -EINVAL; > + } > + if (macro->serdestype == SPX5_SDT_6G) { > + value = sdx5_rd(priv, SD6G_LANE_LANE_DF(macro->stpidx)); > + analog_sd = SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(value); > + } else if (macro->serdestype == SPX5_SDT_10G) { > + value = sdx5_rd(priv, SD10G_LANE_LANE_DF(macro->stpidx)); > + analog_sd = SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(value); > + } else { > + value = sdx5_rd(priv, SD25G_LANE_LANE_DE(macro->stpidx)); > + analog_sd = SD25G_LANE_LANE_DE_LN_PMA_RXEI_GET(value); > + } > + /* Link up is when analog_sd == 0 */ > + return analog_sd; > +} What i have not yet seen is how this code plugs together with phylink_pcs_ops? Can this hardware also be used for SATA, USB? As far as i understand, the Marvell Comphy is multi-purpose, it is used for networking, USB, and SATA, etc. Making it a generic PHY then makes sense, because different subsystems need to use it. But it looks like this is for networking only? So i'm wondering if it belongs in driver/net/pcs and it should be accessed using phylink_pcs_ops? Andrew
WARNING: multiple messages have this Message-ID (diff)
From: Andrew Lunn <andrew@lunn.ch> To: Steen Hegelund <steen.hegelund@microchip.com> Cc: Bjarni Jonasson <bjarni.jonasson@microchip.com>, Alexandre Belloni <alexandre.belloni@bootlin.com>, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Kishon Vijay Abraham I <kishon@ti.com>, Vinod Koul <vkoul@kernel.org>, linux-arm-kernel@lists.infradead.org, Microchip UNG Driver List <UNGLinuxDriver@microchip.com>, Russell King <rmk+kernel@armlinux.org.uk>, Lars Povlsen <lars.povlsen@microchip.com> Subject: Re: [PATCH v8 3/4] phy: Add Sparx5 ethernet serdes PHY driver Date: Thu, 3 Dec 2020 22:52:53 +0100 [thread overview] Message-ID: <20201203215253.GL2333853@lunn.ch> (raw) In-Reply-To: <20201203103015.3735373-4-steen.hegelund@microchip.com> > +/* map from SD25G28 interface width to configuration value */ > +static u8 sd25g28_get_iw_setting(const u8 interface_width) > +{ > + switch (interface_width) { > + case 10: return 0; > + case 16: return 1; > + case 32: return 3; > + case 40: return 4; > + case 64: return 5; > + default: > + pr_err("%s: Illegal value %d for interface width\n", > + __func__, interface_width); Please make use of dev_err(phy->dev, so we know which PHY has configuration problems. > +static int sparx5_serdes_validate(struct phy *phy, enum phy_mode mode, > + int submode, > + union phy_configure_opts *opts) > +{ > + struct sparx5_serdes_macro *macro = phy_get_drvdata(phy); > + struct sparx5_serdes_private *priv = macro->priv; > + u32 value, analog_sd; > + > + if (mode != PHY_MODE_ETHERNET) > + return -EINVAL; > + > + switch (submode) { > + case PHY_INTERFACE_MODE_1000BASEX: > + case PHY_INTERFACE_MODE_SGMII: > + case PHY_INTERFACE_MODE_QSGMII: > + case PHY_INTERFACE_MODE_10GBASER: > + break; > + default: > + return -EINVAL; > + } > + if (macro->serdestype == SPX5_SDT_6G) { > + value = sdx5_rd(priv, SD6G_LANE_LANE_DF(macro->stpidx)); > + analog_sd = SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(value); > + } else if (macro->serdestype == SPX5_SDT_10G) { > + value = sdx5_rd(priv, SD10G_LANE_LANE_DF(macro->stpidx)); > + analog_sd = SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(value); > + } else { > + value = sdx5_rd(priv, SD25G_LANE_LANE_DE(macro->stpidx)); > + analog_sd = SD25G_LANE_LANE_DE_LN_PMA_RXEI_GET(value); > + } > + /* Link up is when analog_sd == 0 */ > + return analog_sd; > +} What i have not yet seen is how this code plugs together with phylink_pcs_ops? Can this hardware also be used for SATA, USB? As far as i understand, the Marvell Comphy is multi-purpose, it is used for networking, USB, and SATA, etc. Making it a generic PHY then makes sense, because different subsystems need to use it. But it looks like this is for networking only? So i'm wondering if it belongs in driver/net/pcs and it should be accessed using phylink_pcs_ops? Andrew _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-12-03 21:54 UTC|newest] Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-12-03 10:30 [PATCH v8 0/4] Adding the Sparx5 Serdes driver Steen Hegelund 2020-12-03 10:30 ` [PATCH v8 1/4] dt-bindings: phy: Add sparx5-serdes bindings Steen Hegelund 2020-12-03 10:30 ` [PATCH v8 2/4] phy: Add ethernet serdes configuration option Steen Hegelund 2020-12-03 10:30 ` [PATCH v8 3/4] phy: Add Sparx5 ethernet serdes PHY driver Steen Hegelund 2020-12-03 21:52 ` Andrew Lunn [this message] 2020-12-03 21:52 ` Andrew Lunn 2020-12-03 22:52 ` Russell King - ARM Linux admin 2020-12-03 22:52 ` Russell King - ARM Linux admin 2020-12-04 7:56 ` Alexandre Belloni 2020-12-04 7:56 ` Alexandre Belloni 2020-12-04 10:20 ` Russell King - ARM Linux admin 2020-12-04 10:20 ` Russell King - ARM Linux admin 2020-12-04 13:51 ` Steen Hegelund 2020-12-04 13:51 ` Steen Hegelund 2020-12-04 13:48 ` Steen Hegelund 2020-12-04 13:48 ` Steen Hegelund 2020-12-04 13:55 ` Russell King - ARM Linux admin 2020-12-04 13:55 ` Russell King - ARM Linux admin 2020-12-04 14:16 ` Alexandre Belloni 2020-12-04 14:16 ` Alexandre Belloni 2020-12-07 8:13 ` Steen Hegelund 2020-12-07 8:13 ` Steen Hegelund 2020-12-03 10:30 ` [PATCH v8 4/4] arm64: dts: sparx5: Add Sparx5 serdes driver node Steen Hegelund
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20201203215253.GL2333853@lunn.ch \ --to=andrew@lunn.ch \ --cc=UNGLinuxDriver@microchip.com \ --cc=alexandre.belloni@bootlin.com \ --cc=bjarni.jonasson@microchip.com \ --cc=kishon@ti.com \ --cc=lars.povlsen@microchip.com \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=netdev@vger.kernel.org \ --cc=rmk+kernel@armlinux.org.uk \ --cc=steen.hegelund@microchip.com \ --cc=vkoul@kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.