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* [PATCH v2 00/16] target/mips: Boring code reordering + add "translate.h"
@ 2020-12-14 18:37 ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: kvm, Aurelien Jarno, Huacai Chen, Aleksandar Rikalo, Jiaxun Yang,
	Laurent Vivier, Paolo Bonzini, Philippe Mathieu-Daudé

Hi,\r
\r
This series contains the patches previously sent in "Boring code\r
reordering" [1] and "Add translate.h and fpu_translate.h headers"\r
[2]. I removed the patches merged and addressed Richard review\r
comments.\r
\r
Missing review: 1 3-5 9-11 14 15\r
\r
Available as:\r
  https://gitlab.com/philmd/qemu/-/commits/refactor_translate_h\r
\r
Regards,\r
\r
Phil.\r
\r
Based-on: https://gitlab.com/philmd/qemu.git tags/mips-next\r
Supersedes: <20201206233949.3783184-1-f4bug@amsat.org>\r
Supersedes: <20201207235539.4070364-1-f4bug@amsat.org>\r
\r
[1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg764551.html\r
[2] https://www.mail-archive.com/qemu-devel@nongnu.org/msg764828.html\r
\r
Philippe Mathieu-Daudé (16):\r
  target/mips: Inline cpu_state_reset() in mips_cpu_reset()\r
  target/mips: Extract FPU helpers to 'fpu_helper.h'\r
  target/mips: Add !CONFIG_USER_ONLY comment after #endif\r
  target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs\r
  target/mips: Extract common helpers from helper.c to common_helper.c\r
  target/mips: Rename helper.c as tlb_helper.c\r
  target/mips: Fix code style for checkpatch.pl\r
  target/mips: Move mmu_init() functions to tlb_helper.c\r
  target/mips: Rename translate_init.c as cpu-defs.c\r
  target/mips: Replace gen_exception_err(err=0) by gen_exception_end()\r
  target/mips: Replace gen_exception_end(EXCP_RI) by\r
    gen_rsvd_instruction\r
  target/mips/translate: Extract DisasContext structure\r
  target/mips/translate: Add declarations for generic code\r
  target/mips: Declare generic FPU functions in 'translate.h'\r
  target/mips: Extract FPU specific definitions to translate.h\r
  target/mips: Only build TCG code when CONFIG_TCG is set\r
\r
 target/mips/fpu_helper.h                      |  59 ++\r
 target/mips/internal.h                        |  52 +-\r
 target/mips/translate.h                       | 166 ++++\r
 linux-user/mips/cpu_loop.c                    |   1 +\r
 target/mips/cpu.c                             | 243 ++++-\r
 target/mips/fpu_helper.c                      |   1 +\r
 target/mips/gdbstub.c                         |   1 +\r
 target/mips/kvm.c                             |   1 +\r
 target/mips/machine.c                         |   1 +\r
 target/mips/msa_helper.c                      |   1 +\r
 target/mips/op_helper.c                       |   2 +-\r
 target/mips/{helper.c => tlb_helper.c}        | 260 ++---\r
 target/mips/translate.c                       | 897 ++++++++----------\r
 .../{translate_init.c.inc => cpu-defs.c.inc}  |  50 +-\r
 target/mips/meson.build                       |  10 +-\r
 15 files changed, 903 insertions(+), 842 deletions(-)\r
 create mode 100644 target/mips/fpu_helper.h\r
 create mode 100644 target/mips/translate.h\r
 rename target/mips/{helper.c => tlb_helper.c} (87%)\r
 rename target/mips/{translate_init.c.inc => cpu-defs.c.inc} (96%)\r
\r
-- \r
2.26.2\r
\r

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 00/16] target/mips: Boring code reordering + add "translate.h"
@ 2020-12-14 18:37 ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, kvm, Huacai Chen, Laurent Vivier, Jiaxun Yang,
	Philippe Mathieu-Daudé,
	Paolo Bonzini, Aurelien Jarno

Hi,\r
\r
This series contains the patches previously sent in "Boring code\r
reordering" [1] and "Add translate.h and fpu_translate.h headers"\r
[2]. I removed the patches merged and addressed Richard review\r
comments.\r
\r
Missing review: 1 3-5 9-11 14 15\r
\r
Available as:\r
  https://gitlab.com/philmd/qemu/-/commits/refactor_translate_h\r
\r
Regards,\r
\r
Phil.\r
\r
Based-on: https://gitlab.com/philmd/qemu.git tags/mips-next\r
Supersedes: <20201206233949.3783184-1-f4bug@amsat.org>\r
Supersedes: <20201207235539.4070364-1-f4bug@amsat.org>\r
\r
[1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg764551.html\r
[2] https://www.mail-archive.com/qemu-devel@nongnu.org/msg764828.html\r
\r
Philippe Mathieu-Daudé (16):\r
  target/mips: Inline cpu_state_reset() in mips_cpu_reset()\r
  target/mips: Extract FPU helpers to 'fpu_helper.h'\r
  target/mips: Add !CONFIG_USER_ONLY comment after #endif\r
  target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs\r
  target/mips: Extract common helpers from helper.c to common_helper.c\r
  target/mips: Rename helper.c as tlb_helper.c\r
  target/mips: Fix code style for checkpatch.pl\r
  target/mips: Move mmu_init() functions to tlb_helper.c\r
  target/mips: Rename translate_init.c as cpu-defs.c\r
  target/mips: Replace gen_exception_err(err=0) by gen_exception_end()\r
  target/mips: Replace gen_exception_end(EXCP_RI) by\r
    gen_rsvd_instruction\r
  target/mips/translate: Extract DisasContext structure\r
  target/mips/translate: Add declarations for generic code\r
  target/mips: Declare generic FPU functions in 'translate.h'\r
  target/mips: Extract FPU specific definitions to translate.h\r
  target/mips: Only build TCG code when CONFIG_TCG is set\r
\r
 target/mips/fpu_helper.h                      |  59 ++\r
 target/mips/internal.h                        |  52 +-\r
 target/mips/translate.h                       | 166 ++++\r
 linux-user/mips/cpu_loop.c                    |   1 +\r
 target/mips/cpu.c                             | 243 ++++-\r
 target/mips/fpu_helper.c                      |   1 +\r
 target/mips/gdbstub.c                         |   1 +\r
 target/mips/kvm.c                             |   1 +\r
 target/mips/machine.c                         |   1 +\r
 target/mips/msa_helper.c                      |   1 +\r
 target/mips/op_helper.c                       |   2 +-\r
 target/mips/{helper.c => tlb_helper.c}        | 260 ++---\r
 target/mips/translate.c                       | 897 ++++++++----------\r
 .../{translate_init.c.inc => cpu-defs.c.inc}  |  50 +-\r
 target/mips/meson.build                       |  10 +-\r
 15 files changed, 903 insertions(+), 842 deletions(-)\r
 create mode 100644 target/mips/fpu_helper.h\r
 create mode 100644 target/mips/translate.h\r
 rename target/mips/{helper.c => tlb_helper.c} (87%)\r
 rename target/mips/{translate_init.c.inc => cpu-defs.c.inc} (96%)\r
\r
-- \r
2.26.2\r
\r


^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 01/16] target/mips: Inline cpu_state_reset() in mips_cpu_reset()
  2020-12-14 18:37 ` Philippe Mathieu-Daudé
@ 2020-12-14 18:37   ` Philippe Mathieu-Daudé
  -1 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: kvm, Aurelien Jarno, Huacai Chen, Aleksandar Rikalo, Jiaxun Yang,
	Laurent Vivier, Paolo Bonzini, Philippe Mathieu-Daudé

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/cpu.c | 26 +++++++++-----------------
 1 file changed, 9 insertions(+), 17 deletions(-)

diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index aadc6f8e74d..7a0dcb11ecd 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -104,10 +104,16 @@ static bool mips_cpu_has_work(CPUState *cs)
 
 #include "translate_init.c.inc"
 
-/* TODO QOM'ify CPU reset and remove */
-static void cpu_state_reset(CPUMIPSState *env)
+static void mips_cpu_reset(DeviceState *dev)
 {
-    CPUState *cs = env_cpu(env);
+    CPUState *cs = CPU(dev);
+    MIPSCPU *cpu = MIPS_CPU(cs);
+    MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
+    CPUMIPSState *env = &cpu->env;
+
+    mcc->parent_reset(dev);
+
+    memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));
 
     /* Reset registers to their default values */
     env->CP0_PRid = env->cpu_model->CP0_PRid;
@@ -330,20 +336,6 @@ static void cpu_state_reset(CPUMIPSState *env)
         /* UHI interface can be used to obtain argc and argv */
         env->active_tc.gpr[4] = -1;
     }
-}
-
-static void mips_cpu_reset(DeviceState *dev)
-{
-    CPUState *s = CPU(dev);
-    MIPSCPU *cpu = MIPS_CPU(s);
-    MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
-    CPUMIPSState *env = &cpu->env;
-
-    mcc->parent_reset(dev);
-
-    memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));
-
-    cpu_state_reset(env);
 
 #ifndef CONFIG_USER_ONLY
     if (kvm_enabled()) {
-- 
2.26.2


^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 01/16] target/mips: Inline cpu_state_reset() in mips_cpu_reset()
@ 2020-12-14 18:37   ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, kvm, Huacai Chen, Laurent Vivier, Jiaxun Yang,
	Philippe Mathieu-Daudé,
	Paolo Bonzini, Aurelien Jarno

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/cpu.c | 26 +++++++++-----------------
 1 file changed, 9 insertions(+), 17 deletions(-)

diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index aadc6f8e74d..7a0dcb11ecd 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -104,10 +104,16 @@ static bool mips_cpu_has_work(CPUState *cs)
 
 #include "translate_init.c.inc"
 
-/* TODO QOM'ify CPU reset and remove */
-static void cpu_state_reset(CPUMIPSState *env)
+static void mips_cpu_reset(DeviceState *dev)
 {
-    CPUState *cs = env_cpu(env);
+    CPUState *cs = CPU(dev);
+    MIPSCPU *cpu = MIPS_CPU(cs);
+    MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
+    CPUMIPSState *env = &cpu->env;
+
+    mcc->parent_reset(dev);
+
+    memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));
 
     /* Reset registers to their default values */
     env->CP0_PRid = env->cpu_model->CP0_PRid;
@@ -330,20 +336,6 @@ static void cpu_state_reset(CPUMIPSState *env)
         /* UHI interface can be used to obtain argc and argv */
         env->active_tc.gpr[4] = -1;
     }
-}
-
-static void mips_cpu_reset(DeviceState *dev)
-{
-    CPUState *s = CPU(dev);
-    MIPSCPU *cpu = MIPS_CPU(s);
-    MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
-    CPUMIPSState *env = &cpu->env;
-
-    mcc->parent_reset(dev);
-
-    memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));
-
-    cpu_state_reset(env);
 
 #ifndef CONFIG_USER_ONLY
     if (kvm_enabled()) {
-- 
2.26.2



^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 02/16] target/mips: Extract FPU helpers to 'fpu_helper.h'
  2020-12-14 18:37 ` Philippe Mathieu-Daudé
@ 2020-12-14 18:37   ` Philippe Mathieu-Daudé
  -1 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: kvm, Aurelien Jarno, Huacai Chen, Aleksandar Rikalo, Jiaxun Yang,
	Laurent Vivier, Paolo Bonzini, Philippe Mathieu-Daudé,
	Richard Henderson

Extract FPU specific helpers from "internal.h" to "fpu_helper.h".

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201120210844.2625602-2-f4bug@amsat.org>
---
 target/mips/fpu_helper.h         | 59 ++++++++++++++++++++++++++++++++
 target/mips/internal.h           | 49 --------------------------
 linux-user/mips/cpu_loop.c       |  1 +
 target/mips/fpu_helper.c         |  1 +
 target/mips/gdbstub.c            |  1 +
 target/mips/kvm.c                |  1 +
 target/mips/machine.c            |  1 +
 target/mips/msa_helper.c         |  1 +
 target/mips/op_helper.c          |  2 +-
 target/mips/translate.c          |  1 +
 target/mips/translate_init.c.inc |  2 ++
 11 files changed, 69 insertions(+), 50 deletions(-)
 create mode 100644 target/mips/fpu_helper.h

diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
new file mode 100644
index 00000000000..1c2d6d35a71
--- /dev/null
+++ b/target/mips/fpu_helper.h
@@ -0,0 +1,59 @@
+/*
+ * Helpers for emulation of FPU-related MIPS instructions.
+ *
+ *  Copyright (C) 2004-2005  Jocelyn Mayer
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+#include "fpu/softfloat-helpers.h"
+#include "cpu.h"
+
+extern const FloatRoundMode ieee_rm[4];
+
+uint32_t float_class_s(uint32_t arg, float_status *fst);
+uint64_t float_class_d(uint64_t arg, float_status *fst);
+
+static inline void restore_rounding_mode(CPUMIPSState *env)
+{
+    set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
+                            &env->active_fpu.fp_status);
+}
+
+static inline void restore_flush_mode(CPUMIPSState *env)
+{
+    set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0,
+                      &env->active_fpu.fp_status);
+}
+
+static inline void restore_snan_bit_mode(CPUMIPSState *env)
+{
+    set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0,
+                        &env->active_fpu.fp_status);
+}
+
+static inline void restore_fp_status(CPUMIPSState *env)
+{
+    restore_rounding_mode(env);
+    restore_flush_mode(env);
+    restore_snan_bit_mode(env);
+}
+
+/* MSA */
+
+enum CPUMIPSMSADataFormat {
+    DF_BYTE = 0,
+    DF_HALF,
+    DF_WORD,
+    DF_DOUBLE
+};
+
+static inline void restore_msa_fp_status(CPUMIPSState *env)
+{
+    float_status *status = &env->active_tc.msa_fp_status;
+    int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM;
+    bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0;
+
+    set_float_rounding_mode(ieee_rm[rounding_mode], status);
+    set_flush_to_zero(flush_to_zero, status);
+    set_flush_inputs_to_zero(flush_to_zero, status);
+}
diff --git a/target/mips/internal.h b/target/mips/internal.h
index e4d2d9f44f9..24d9f0d6a5c 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -9,7 +9,6 @@
 #define MIPS_INTERNAL_H
 
 #include "exec/memattrs.h"
-#include "fpu/softfloat-helpers.h"
 
 /*
  * MMU types, the first four entries have the same layout as the
@@ -75,13 +74,6 @@ struct mips_def_t {
 extern const struct mips_def_t mips_defs[];
 extern const int mips_defs_number;
 
-enum CPUMIPSMSADataFormat {
-    DF_BYTE = 0,
-    DF_HALF,
-    DF_WORD,
-    DF_DOUBLE
-};
-
 void mips_cpu_do_interrupt(CPUState *cpu);
 bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
 void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
@@ -220,49 +212,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                        bool probe, uintptr_t retaddr);
 
 /* op_helper.c */
-uint32_t float_class_s(uint32_t arg, float_status *fst);
-uint64_t float_class_d(uint64_t arg, float_status *fst);
-
-extern const FloatRoundMode ieee_rm[4];
-
 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
 
-static inline void restore_rounding_mode(CPUMIPSState *env)
-{
-    set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
-                            &env->active_fpu.fp_status);
-}
-
-static inline void restore_flush_mode(CPUMIPSState *env)
-{
-    set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0,
-                      &env->active_fpu.fp_status);
-}
-
-static inline void restore_snan_bit_mode(CPUMIPSState *env)
-{
-    set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0,
-                        &env->active_fpu.fp_status);
-}
-
-static inline void restore_fp_status(CPUMIPSState *env)
-{
-    restore_rounding_mode(env);
-    restore_flush_mode(env);
-    restore_snan_bit_mode(env);
-}
-
-static inline void restore_msa_fp_status(CPUMIPSState *env)
-{
-    float_status *status = &env->active_tc.msa_fp_status;
-    int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM;
-    bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0;
-
-    set_float_rounding_mode(ieee_rm[rounding_mode], status);
-    set_flush_to_zero(flush_to_zero, status);
-    set_flush_inputs_to_zero(flush_to_zero, status);
-}
-
 static inline void restore_pamask(CPUMIPSState *env)
 {
     if (env->hflags & MIPS_HFLAG_ELPA) {
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
index cfe7ba5c47d..b58dbeb83d1 100644
--- a/linux-user/mips/cpu_loop.c
+++ b/linux-user/mips/cpu_loop.c
@@ -23,6 +23,7 @@
 #include "cpu_loop-common.h"
 #include "elf.h"
 #include "internal.h"
+#include "fpu_helper.h"
 
 # ifdef TARGET_ABI_MIPSO32
 #  define MIPS_SYSCALL_NUMBER_UNUSED -1
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index bdb65065ee7..a3c05160b35 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -27,6 +27,7 @@
 #include "exec/exec-all.h"
 #include "exec/cpu_ldst.h"
 #include "fpu/softfloat.h"
+#include "fpu_helper.h"
 
 
 /* Complex FPU operations which may need stack space. */
diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c
index e39f8d75cf0..f1c2a2cf6d6 100644
--- a/target/mips/gdbstub.c
+++ b/target/mips/gdbstub.c
@@ -21,6 +21,7 @@
 #include "cpu.h"
 #include "internal.h"
 #include "exec/gdbstub.h"
+#include "fpu_helper.h"
 
 int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
 {
diff --git a/target/mips/kvm.c b/target/mips/kvm.c
index 477692566a4..a5b6fe35dbc 100644
--- a/target/mips/kvm.c
+++ b/target/mips/kvm.c
@@ -24,6 +24,7 @@
 #include "sysemu/runstate.h"
 #include "kvm_mips.h"
 #include "hw/boards.h"
+#include "fpu_helper.h"
 
 #define DEBUG_KVM 0
 
diff --git a/target/mips/machine.c b/target/mips/machine.c
index 5b23e3e912a..a4ea67c2980 100644
--- a/target/mips/machine.c
+++ b/target/mips/machine.c
@@ -2,6 +2,7 @@
 #include "cpu.h"
 #include "internal.h"
 #include "migration/cpu.h"
+#include "fpu_helper.h"
 
 static int cpu_post_load(void *opaque, int version_id)
 {
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 249f0fdad80..b89b4c44902 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -23,6 +23,7 @@
 #include "exec/exec-all.h"
 #include "exec/helper-proto.h"
 #include "fpu/softfloat.h"
+#include "fpu_helper.h"
 
 /* Data format min and max values */
 #define DF_BITS(df) (1 << ((df) + 3))
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 5aa97902e98..3386b8228e9 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -24,7 +24,7 @@
 #include "exec/helper-proto.h"
 #include "exec/exec-all.h"
 #include "exec/memop.h"
-
+#include "fpu_helper.h"
 
 /*****************************************************************************/
 /* Exceptions processing helpers */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 19933b7868c..d2614796214 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -35,6 +35,7 @@
 #include "exec/translator.h"
 #include "exec/log.h"
 #include "qemu/qemu-print.h"
+#include "fpu_helper.h"
 
 #define MIPS_DEBUG_DISAS 0
 
diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index f72fee3b40a..915277dd1f6 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -18,6 +18,8 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 
+#include "fpu_helper.h"
+
 /* CPU / CPU family specific config register values. */
 
 /* Have config1, uncached coherency */
-- 
2.26.2


^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 02/16] target/mips: Extract FPU helpers to 'fpu_helper.h'
@ 2020-12-14 18:37   ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, kvm, Huacai Chen, Richard Henderson,
	Laurent Vivier, Jiaxun Yang, Philippe Mathieu-Daudé,
	Paolo Bonzini, Aurelien Jarno

Extract FPU specific helpers from "internal.h" to "fpu_helper.h".

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201120210844.2625602-2-f4bug@amsat.org>
---
 target/mips/fpu_helper.h         | 59 ++++++++++++++++++++++++++++++++
 target/mips/internal.h           | 49 --------------------------
 linux-user/mips/cpu_loop.c       |  1 +
 target/mips/fpu_helper.c         |  1 +
 target/mips/gdbstub.c            |  1 +
 target/mips/kvm.c                |  1 +
 target/mips/machine.c            |  1 +
 target/mips/msa_helper.c         |  1 +
 target/mips/op_helper.c          |  2 +-
 target/mips/translate.c          |  1 +
 target/mips/translate_init.c.inc |  2 ++
 11 files changed, 69 insertions(+), 50 deletions(-)
 create mode 100644 target/mips/fpu_helper.h

diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
new file mode 100644
index 00000000000..1c2d6d35a71
--- /dev/null
+++ b/target/mips/fpu_helper.h
@@ -0,0 +1,59 @@
+/*
+ * Helpers for emulation of FPU-related MIPS instructions.
+ *
+ *  Copyright (C) 2004-2005  Jocelyn Mayer
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+#include "fpu/softfloat-helpers.h"
+#include "cpu.h"
+
+extern const FloatRoundMode ieee_rm[4];
+
+uint32_t float_class_s(uint32_t arg, float_status *fst);
+uint64_t float_class_d(uint64_t arg, float_status *fst);
+
+static inline void restore_rounding_mode(CPUMIPSState *env)
+{
+    set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
+                            &env->active_fpu.fp_status);
+}
+
+static inline void restore_flush_mode(CPUMIPSState *env)
+{
+    set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0,
+                      &env->active_fpu.fp_status);
+}
+
+static inline void restore_snan_bit_mode(CPUMIPSState *env)
+{
+    set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0,
+                        &env->active_fpu.fp_status);
+}
+
+static inline void restore_fp_status(CPUMIPSState *env)
+{
+    restore_rounding_mode(env);
+    restore_flush_mode(env);
+    restore_snan_bit_mode(env);
+}
+
+/* MSA */
+
+enum CPUMIPSMSADataFormat {
+    DF_BYTE = 0,
+    DF_HALF,
+    DF_WORD,
+    DF_DOUBLE
+};
+
+static inline void restore_msa_fp_status(CPUMIPSState *env)
+{
+    float_status *status = &env->active_tc.msa_fp_status;
+    int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM;
+    bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0;
+
+    set_float_rounding_mode(ieee_rm[rounding_mode], status);
+    set_flush_to_zero(flush_to_zero, status);
+    set_flush_inputs_to_zero(flush_to_zero, status);
+}
diff --git a/target/mips/internal.h b/target/mips/internal.h
index e4d2d9f44f9..24d9f0d6a5c 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -9,7 +9,6 @@
 #define MIPS_INTERNAL_H
 
 #include "exec/memattrs.h"
-#include "fpu/softfloat-helpers.h"
 
 /*
  * MMU types, the first four entries have the same layout as the
@@ -75,13 +74,6 @@ struct mips_def_t {
 extern const struct mips_def_t mips_defs[];
 extern const int mips_defs_number;
 
-enum CPUMIPSMSADataFormat {
-    DF_BYTE = 0,
-    DF_HALF,
-    DF_WORD,
-    DF_DOUBLE
-};
-
 void mips_cpu_do_interrupt(CPUState *cpu);
 bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
 void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
@@ -220,49 +212,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                        bool probe, uintptr_t retaddr);
 
 /* op_helper.c */
-uint32_t float_class_s(uint32_t arg, float_status *fst);
-uint64_t float_class_d(uint64_t arg, float_status *fst);
-
-extern const FloatRoundMode ieee_rm[4];
-
 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
 
-static inline void restore_rounding_mode(CPUMIPSState *env)
-{
-    set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
-                            &env->active_fpu.fp_status);
-}
-
-static inline void restore_flush_mode(CPUMIPSState *env)
-{
-    set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0,
-                      &env->active_fpu.fp_status);
-}
-
-static inline void restore_snan_bit_mode(CPUMIPSState *env)
-{
-    set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0,
-                        &env->active_fpu.fp_status);
-}
-
-static inline void restore_fp_status(CPUMIPSState *env)
-{
-    restore_rounding_mode(env);
-    restore_flush_mode(env);
-    restore_snan_bit_mode(env);
-}
-
-static inline void restore_msa_fp_status(CPUMIPSState *env)
-{
-    float_status *status = &env->active_tc.msa_fp_status;
-    int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM;
-    bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0;
-
-    set_float_rounding_mode(ieee_rm[rounding_mode], status);
-    set_flush_to_zero(flush_to_zero, status);
-    set_flush_inputs_to_zero(flush_to_zero, status);
-}
-
 static inline void restore_pamask(CPUMIPSState *env)
 {
     if (env->hflags & MIPS_HFLAG_ELPA) {
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
index cfe7ba5c47d..b58dbeb83d1 100644
--- a/linux-user/mips/cpu_loop.c
+++ b/linux-user/mips/cpu_loop.c
@@ -23,6 +23,7 @@
 #include "cpu_loop-common.h"
 #include "elf.h"
 #include "internal.h"
+#include "fpu_helper.h"
 
 # ifdef TARGET_ABI_MIPSO32
 #  define MIPS_SYSCALL_NUMBER_UNUSED -1
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index bdb65065ee7..a3c05160b35 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -27,6 +27,7 @@
 #include "exec/exec-all.h"
 #include "exec/cpu_ldst.h"
 #include "fpu/softfloat.h"
+#include "fpu_helper.h"
 
 
 /* Complex FPU operations which may need stack space. */
diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c
index e39f8d75cf0..f1c2a2cf6d6 100644
--- a/target/mips/gdbstub.c
+++ b/target/mips/gdbstub.c
@@ -21,6 +21,7 @@
 #include "cpu.h"
 #include "internal.h"
 #include "exec/gdbstub.h"
+#include "fpu_helper.h"
 
 int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
 {
diff --git a/target/mips/kvm.c b/target/mips/kvm.c
index 477692566a4..a5b6fe35dbc 100644
--- a/target/mips/kvm.c
+++ b/target/mips/kvm.c
@@ -24,6 +24,7 @@
 #include "sysemu/runstate.h"
 #include "kvm_mips.h"
 #include "hw/boards.h"
+#include "fpu_helper.h"
 
 #define DEBUG_KVM 0
 
diff --git a/target/mips/machine.c b/target/mips/machine.c
index 5b23e3e912a..a4ea67c2980 100644
--- a/target/mips/machine.c
+++ b/target/mips/machine.c
@@ -2,6 +2,7 @@
 #include "cpu.h"
 #include "internal.h"
 #include "migration/cpu.h"
+#include "fpu_helper.h"
 
 static int cpu_post_load(void *opaque, int version_id)
 {
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 249f0fdad80..b89b4c44902 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -23,6 +23,7 @@
 #include "exec/exec-all.h"
 #include "exec/helper-proto.h"
 #include "fpu/softfloat.h"
+#include "fpu_helper.h"
 
 /* Data format min and max values */
 #define DF_BITS(df) (1 << ((df) + 3))
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 5aa97902e98..3386b8228e9 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -24,7 +24,7 @@
 #include "exec/helper-proto.h"
 #include "exec/exec-all.h"
 #include "exec/memop.h"
-
+#include "fpu_helper.h"
 
 /*****************************************************************************/
 /* Exceptions processing helpers */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 19933b7868c..d2614796214 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -35,6 +35,7 @@
 #include "exec/translator.h"
 #include "exec/log.h"
 #include "qemu/qemu-print.h"
+#include "fpu_helper.h"
 
 #define MIPS_DEBUG_DISAS 0
 
diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index f72fee3b40a..915277dd1f6 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -18,6 +18,8 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 
+#include "fpu_helper.h"
+
 /* CPU / CPU family specific config register values. */
 
 /* Have config1, uncached coherency */
-- 
2.26.2



^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 03/16] target/mips: Add !CONFIG_USER_ONLY comment after #endif
  2020-12-14 18:37 ` Philippe Mathieu-Daudé
@ 2020-12-14 18:37   ` Philippe Mathieu-Daudé
  -1 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: kvm, Aurelien Jarno, Huacai Chen, Aleksandar Rikalo, Jiaxun Yang,
	Laurent Vivier, Paolo Bonzini, Philippe Mathieu-Daudé

To help understand ifdef'ry, add comment after #endif.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/helper.c | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/target/mips/helper.c b/target/mips/helper.c
index 87296fbad69..cdd7704789d 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -455,7 +455,8 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
         }
     }
 }
-#endif
+
+#endif /* !CONFIG_USER_ONLY */
 
 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
                                 int rw, int tlb_error)
@@ -537,6 +538,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
 }
 
 #if !defined(CONFIG_USER_ONLY)
+
 hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 {
     MIPSCPU *cpu = MIPS_CPU(cs);
@@ -550,7 +552,7 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
     }
     return phys_addr;
 }
-#endif
+#endif /* !CONFIG_USER_ONLY */
 
 #if !defined(CONFIG_USER_ONLY)
 #if !defined(TARGET_MIPS64)
@@ -886,7 +888,7 @@ refill:
     return true;
 }
 #endif
-#endif
+#endif /* !CONFIG_USER_ONLY */
 
 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                        MMUAccessType access_type, int mmu_idx,
@@ -1088,7 +1090,8 @@ static inline void set_badinstr_registers(CPUMIPSState *env)
         env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4);
     }
 }
-#endif
+
+#endif /* !CONFIG_USER_ONLY */
 
 void mips_cpu_do_interrupt(CPUState *cs)
 {
@@ -1482,7 +1485,7 @@ void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
         }
     }
 }
-#endif
+#endif /* !CONFIG_USER_ONLY */
 
 void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
                                           uint32_t exception,
-- 
2.26.2


^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 03/16] target/mips: Add !CONFIG_USER_ONLY comment after #endif
@ 2020-12-14 18:37   ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, kvm, Huacai Chen, Laurent Vivier, Jiaxun Yang,
	Philippe Mathieu-Daudé,
	Paolo Bonzini, Aurelien Jarno

To help understand ifdef'ry, add comment after #endif.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/helper.c | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/target/mips/helper.c b/target/mips/helper.c
index 87296fbad69..cdd7704789d 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -455,7 +455,8 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
         }
     }
 }
-#endif
+
+#endif /* !CONFIG_USER_ONLY */
 
 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
                                 int rw, int tlb_error)
@@ -537,6 +538,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
 }
 
 #if !defined(CONFIG_USER_ONLY)
+
 hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 {
     MIPSCPU *cpu = MIPS_CPU(cs);
@@ -550,7 +552,7 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
     }
     return phys_addr;
 }
-#endif
+#endif /* !CONFIG_USER_ONLY */
 
 #if !defined(CONFIG_USER_ONLY)
 #if !defined(TARGET_MIPS64)
@@ -886,7 +888,7 @@ refill:
     return true;
 }
 #endif
-#endif
+#endif /* !CONFIG_USER_ONLY */
 
 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                        MMUAccessType access_type, int mmu_idx,
@@ -1088,7 +1090,8 @@ static inline void set_badinstr_registers(CPUMIPSState *env)
         env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4);
     }
 }
-#endif
+
+#endif /* !CONFIG_USER_ONLY */
 
 void mips_cpu_do_interrupt(CPUState *cs)
 {
@@ -1482,7 +1485,7 @@ void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
         }
     }
 }
-#endif
+#endif /* !CONFIG_USER_ONLY */
 
 void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
                                           uint32_t exception,
-- 
2.26.2



^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 04/16] target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs
  2020-12-14 18:37 ` Philippe Mathieu-Daudé
@ 2020-12-14 18:37   ` Philippe Mathieu-Daudé
  -1 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: kvm, Aurelien Jarno, Huacai Chen, Aleksandar Rikalo, Jiaxun Yang,
	Laurent Vivier, Paolo Bonzini, Philippe Mathieu-Daudé

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/helper.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/target/mips/helper.c b/target/mips/helper.c
index cdd7704789d..0692e232f0a 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -552,9 +552,7 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
     }
     return phys_addr;
 }
-#endif /* !CONFIG_USER_ONLY */
 
-#if !defined(CONFIG_USER_ONLY)
 #if !defined(TARGET_MIPS64)
 
 /*
-- 
2.26.2


^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 04/16] target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs
@ 2020-12-14 18:37   ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, kvm, Huacai Chen, Laurent Vivier, Jiaxun Yang,
	Philippe Mathieu-Daudé,
	Paolo Bonzini, Aurelien Jarno

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/helper.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/target/mips/helper.c b/target/mips/helper.c
index cdd7704789d..0692e232f0a 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -552,9 +552,7 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
     }
     return phys_addr;
 }
-#endif /* !CONFIG_USER_ONLY */
 
-#if !defined(CONFIG_USER_ONLY)
 #if !defined(TARGET_MIPS64)
 
 /*
-- 
2.26.2



^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 05/16] target/mips: Extract common helpers from helper.c to common_helper.c
  2020-12-14 18:37 ` Philippe Mathieu-Daudé
@ 2020-12-14 18:37   ` Philippe Mathieu-Daudé
  -1 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: kvm, Aurelien Jarno, Huacai Chen, Aleksandar Rikalo, Jiaxun Yang,
	Laurent Vivier, Paolo Bonzini, Philippe Mathieu-Daudé

The rest of helper.c is TLB related. Extract the non TLB
specific functions to a new file, so we can rename helper.c
as tlb_helper.c in the next commit.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/internal.h |   2 +
 target/mips/cpu.c      | 215 +++++++++++++++++++++++++++++++++++++++--
 target/mips/helper.c   | 201 --------------------------------------
 3 files changed, 211 insertions(+), 207 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 24d9f0d6a5c..c1401492c46 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -399,6 +399,8 @@ void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
 
+const char *mips_exception_name(int32_t exception);
+
 void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
                                           int error_code, uintptr_t pc);
 
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 7a0dcb11ecd..a54be034a2b 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -34,6 +34,215 @@
 #include "hw/semihosting/semihost.h"
 #include "qapi/qapi-commands-machine-target.h"
 
+#if !defined(CONFIG_USER_ONLY)
+
+/* Called for updates to CP0_Status.  */
+void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
+{
+    int32_t tcstatus, *tcst;
+    uint32_t v = cpu->CP0_Status;
+    uint32_t cu, mx, asid, ksu;
+    uint32_t mask = ((1 << CP0TCSt_TCU3)
+                       | (1 << CP0TCSt_TCU2)
+                       | (1 << CP0TCSt_TCU1)
+                       | (1 << CP0TCSt_TCU0)
+                       | (1 << CP0TCSt_TMX)
+                       | (3 << CP0TCSt_TKSU)
+                       | (0xff << CP0TCSt_TASID));
+
+    cu = (v >> CP0St_CU0) & 0xf;
+    mx = (v >> CP0St_MX) & 0x1;
+    ksu = (v >> CP0St_KSU) & 0x3;
+    asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
+
+    tcstatus = cu << CP0TCSt_TCU0;
+    tcstatus |= mx << CP0TCSt_TMX;
+    tcstatus |= ksu << CP0TCSt_TKSU;
+    tcstatus |= asid;
+
+    if (tc == cpu->current_tc) {
+        tcst = &cpu->active_tc.CP0_TCStatus;
+    } else {
+        tcst = &cpu->tcs[tc].CP0_TCStatus;
+    }
+
+    *tcst &= ~mask;
+    *tcst |= tcstatus;
+    compute_hflags(cpu);
+}
+
+void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
+{
+    uint32_t mask = env->CP0_Status_rw_bitmask;
+    target_ulong old = env->CP0_Status;
+
+    if (env->insn_flags & ISA_MIPS32R6) {
+        bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
+#if defined(TARGET_MIPS64)
+        uint32_t ksux = (1 << CP0St_KX) & val;
+        ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
+        ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
+        val = (val & ~(7 << CP0St_UX)) | ksux;
+#endif
+        if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
+            mask &= ~(3 << CP0St_KSU);
+        }
+        mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
+    }
+
+    env->CP0_Status = (old & ~mask) | (val & mask);
+#if defined(TARGET_MIPS64)
+    if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
+        /* Access to at least one of the 64-bit segments has been disabled */
+        tlb_flush(env_cpu(env));
+    }
+#endif
+    if (ase_mt_available(env)) {
+        sync_c0_status(env, env, env->current_tc);
+    } else {
+        compute_hflags(env);
+    }
+}
+
+void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
+{
+    uint32_t mask = 0x00C00300;
+    uint32_t old = env->CP0_Cause;
+    int i;
+
+    if (env->insn_flags & ISA_MIPS32R2) {
+        mask |= 1 << CP0Ca_DC;
+    }
+    if (env->insn_flags & ISA_MIPS32R6) {
+        mask &= ~((1 << CP0Ca_WP) & val);
+    }
+
+    env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
+
+    if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
+        if (env->CP0_Cause & (1 << CP0Ca_DC)) {
+            cpu_mips_stop_count(env);
+        } else {
+            cpu_mips_start_count(env);
+        }
+    }
+
+    /* Set/reset software interrupts */
+    for (i = 0 ; i < 2 ; i++) {
+        if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
+            cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
+        }
+    }
+}
+
+#endif /* !CONFIG_USER_ONLY */
+
+static const char * const excp_names[EXCP_LAST + 1] = {
+    [EXCP_RESET] = "reset",
+    [EXCP_SRESET] = "soft reset",
+    [EXCP_DSS] = "debug single step",
+    [EXCP_DINT] = "debug interrupt",
+    [EXCP_NMI] = "non-maskable interrupt",
+    [EXCP_MCHECK] = "machine check",
+    [EXCP_EXT_INTERRUPT] = "interrupt",
+    [EXCP_DFWATCH] = "deferred watchpoint",
+    [EXCP_DIB] = "debug instruction breakpoint",
+    [EXCP_IWATCH] = "instruction fetch watchpoint",
+    [EXCP_AdEL] = "address error load",
+    [EXCP_AdES] = "address error store",
+    [EXCP_TLBF] = "TLB refill",
+    [EXCP_IBE] = "instruction bus error",
+    [EXCP_DBp] = "debug breakpoint",
+    [EXCP_SYSCALL] = "syscall",
+    [EXCP_BREAK] = "break",
+    [EXCP_CpU] = "coprocessor unusable",
+    [EXCP_RI] = "reserved instruction",
+    [EXCP_OVERFLOW] = "arithmetic overflow",
+    [EXCP_TRAP] = "trap",
+    [EXCP_FPE] = "floating point",
+    [EXCP_DDBS] = "debug data break store",
+    [EXCP_DWATCH] = "data watchpoint",
+    [EXCP_LTLBL] = "TLB modify",
+    [EXCP_TLBL] = "TLB load",
+    [EXCP_TLBS] = "TLB store",
+    [EXCP_DBE] = "data bus error",
+    [EXCP_DDBL] = "debug data break load",
+    [EXCP_THREAD] = "thread",
+    [EXCP_MDMX] = "MDMX",
+    [EXCP_C2E] = "precise coprocessor 2",
+    [EXCP_CACHE] = "cache error",
+    [EXCP_TLBXI] = "TLB execute-inhibit",
+    [EXCP_TLBRI] = "TLB read-inhibit",
+    [EXCP_MSADIS] = "MSA disabled",
+    [EXCP_MSAFPE] = "MSA floating point",
+};
+
+const char *mips_exception_name(int32_t exception)
+{
+    if (exception < 0 || exception > EXCP_LAST) {
+        return "unknown";
+    }
+    return excp_names[exception];
+}
+
+void cpu_set_exception_base(int vp_index, target_ulong address)
+{
+    MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));
+    vp->env.exception_base = address;
+}
+
+target_ulong exception_resume_pc(CPUMIPSState *env)
+{
+    target_ulong bad_pc;
+    target_ulong isa_mode;
+
+    isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
+    bad_pc = env->active_tc.PC | isa_mode;
+    if (env->hflags & MIPS_HFLAG_BMASK) {
+        /*
+         * If the exception was raised from a delay slot, come back to
+         * the jump.
+         */
+        bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
+    }
+
+    return bad_pc;
+}
+
+bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+{
+    if (interrupt_request & CPU_INTERRUPT_HARD) {
+        MIPSCPU *cpu = MIPS_CPU(cs);
+        CPUMIPSState *env = &cpu->env;
+
+        if (cpu_mips_hw_interrupts_enabled(env) &&
+            cpu_mips_hw_interrupts_pending(env)) {
+            /* Raise it */
+            cs->exception_index = EXCP_EXT_INTERRUPT;
+            env->error_code = 0;
+            mips_cpu_do_interrupt(cs);
+            return true;
+        }
+    }
+    return false;
+}
+
+void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
+                                          uint32_t exception,
+                                          int error_code,
+                                          uintptr_t pc)
+{
+    CPUState *cs = env_cpu(env);
+
+    qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n",
+                  __func__, exception, mips_exception_name(exception),
+                  error_code);
+    cs->exception_index = exception;
+    env->error_code = error_code;
+
+    cpu_loop_exit_restore(cs, pc);
+}
+
 static void mips_cpu_set_pc(CPUState *cs, vaddr value)
 {
     MIPSCPU *cpu = MIPS_CPU(cs);
@@ -591,9 +800,3 @@ bool cpu_type_supports_cps_smp(const char *cpu_type)
     const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
     return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
 }
-
-void cpu_set_exception_base(int vp_index, target_ulong address)
-{
-    MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));
-    vp->env.exception_base = address;
-}
diff --git a/target/mips/helper.c b/target/mips/helper.c
index 0692e232f0a..59787b870b8 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -357,105 +357,6 @@ void cpu_mips_tlb_flush(CPUMIPSState *env)
     env->tlb->tlb_in_use = env->tlb->nb_tlb;
 }
 
-/* Called for updates to CP0_Status.  */
-void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
-{
-    int32_t tcstatus, *tcst;
-    uint32_t v = cpu->CP0_Status;
-    uint32_t cu, mx, asid, ksu;
-    uint32_t mask = ((1 << CP0TCSt_TCU3)
-                       | (1 << CP0TCSt_TCU2)
-                       | (1 << CP0TCSt_TCU1)
-                       | (1 << CP0TCSt_TCU0)
-                       | (1 << CP0TCSt_TMX)
-                       | (3 << CP0TCSt_TKSU)
-                       | (0xff << CP0TCSt_TASID));
-
-    cu = (v >> CP0St_CU0) & 0xf;
-    mx = (v >> CP0St_MX) & 0x1;
-    ksu = (v >> CP0St_KSU) & 0x3;
-    asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
-
-    tcstatus = cu << CP0TCSt_TCU0;
-    tcstatus |= mx << CP0TCSt_TMX;
-    tcstatus |= ksu << CP0TCSt_TKSU;
-    tcstatus |= asid;
-
-    if (tc == cpu->current_tc) {
-        tcst = &cpu->active_tc.CP0_TCStatus;
-    } else {
-        tcst = &cpu->tcs[tc].CP0_TCStatus;
-    }
-
-    *tcst &= ~mask;
-    *tcst |= tcstatus;
-    compute_hflags(cpu);
-}
-
-void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
-{
-    uint32_t mask = env->CP0_Status_rw_bitmask;
-    target_ulong old = env->CP0_Status;
-
-    if (env->insn_flags & ISA_MIPS32R6) {
-        bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
-#if defined(TARGET_MIPS64)
-        uint32_t ksux = (1 << CP0St_KX) & val;
-        ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
-        ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
-        val = (val & ~(7 << CP0St_UX)) | ksux;
-#endif
-        if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
-            mask &= ~(3 << CP0St_KSU);
-        }
-        mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
-    }
-
-    env->CP0_Status = (old & ~mask) | (val & mask);
-#if defined(TARGET_MIPS64)
-    if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
-        /* Access to at least one of the 64-bit segments has been disabled */
-        tlb_flush(env_cpu(env));
-    }
-#endif
-    if (ase_mt_available(env)) {
-        sync_c0_status(env, env, env->current_tc);
-    } else {
-        compute_hflags(env);
-    }
-}
-
-void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
-{
-    uint32_t mask = 0x00C00300;
-    uint32_t old = env->CP0_Cause;
-    int i;
-
-    if (env->insn_flags & ISA_MIPS32R2) {
-        mask |= 1 << CP0Ca_DC;
-    }
-    if (env->insn_flags & ISA_MIPS32R6) {
-        mask &= ~((1 << CP0Ca_WP) & val);
-    }
-
-    env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
-
-    if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
-        if (env->CP0_Cause & (1 << CP0Ca_DC)) {
-            cpu_mips_stop_count(env);
-        } else {
-            cpu_mips_start_count(env);
-        }
-    }
-
-    /* Set/reset software interrupts */
-    for (i = 0 ; i < 2 ; i++) {
-        if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
-            cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
-        }
-    }
-}
-
 #endif /* !CONFIG_USER_ONLY */
 
 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
@@ -977,75 +878,7 @@ hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
         return physical;
     }
 }
-#endif /* !CONFIG_USER_ONLY */
 
-static const char * const excp_names[EXCP_LAST + 1] = {
-    [EXCP_RESET] = "reset",
-    [EXCP_SRESET] = "soft reset",
-    [EXCP_DSS] = "debug single step",
-    [EXCP_DINT] = "debug interrupt",
-    [EXCP_NMI] = "non-maskable interrupt",
-    [EXCP_MCHECK] = "machine check",
-    [EXCP_EXT_INTERRUPT] = "interrupt",
-    [EXCP_DFWATCH] = "deferred watchpoint",
-    [EXCP_DIB] = "debug instruction breakpoint",
-    [EXCP_IWATCH] = "instruction fetch watchpoint",
-    [EXCP_AdEL] = "address error load",
-    [EXCP_AdES] = "address error store",
-    [EXCP_TLBF] = "TLB refill",
-    [EXCP_IBE] = "instruction bus error",
-    [EXCP_DBp] = "debug breakpoint",
-    [EXCP_SYSCALL] = "syscall",
-    [EXCP_BREAK] = "break",
-    [EXCP_CpU] = "coprocessor unusable",
-    [EXCP_RI] = "reserved instruction",
-    [EXCP_OVERFLOW] = "arithmetic overflow",
-    [EXCP_TRAP] = "trap",
-    [EXCP_FPE] = "floating point",
-    [EXCP_DDBS] = "debug data break store",
-    [EXCP_DWATCH] = "data watchpoint",
-    [EXCP_LTLBL] = "TLB modify",
-    [EXCP_TLBL] = "TLB load",
-    [EXCP_TLBS] = "TLB store",
-    [EXCP_DBE] = "data bus error",
-    [EXCP_DDBL] = "debug data break load",
-    [EXCP_THREAD] = "thread",
-    [EXCP_MDMX] = "MDMX",
-    [EXCP_C2E] = "precise coprocessor 2",
-    [EXCP_CACHE] = "cache error",
-    [EXCP_TLBXI] = "TLB execute-inhibit",
-    [EXCP_TLBRI] = "TLB read-inhibit",
-    [EXCP_MSADIS] = "MSA disabled",
-    [EXCP_MSAFPE] = "MSA floating point",
-};
-
-static const char *mips_exception_name(int32_t exception)
-{
-    if (exception < 0 || exception > EXCP_LAST) {
-        return "unknown";
-    }
-    return excp_names[exception];
-}
-
-target_ulong exception_resume_pc(CPUMIPSState *env)
-{
-    target_ulong bad_pc;
-    target_ulong isa_mode;
-
-    isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
-    bad_pc = env->active_tc.PC | isa_mode;
-    if (env->hflags & MIPS_HFLAG_BMASK) {
-        /*
-         * If the exception was raised from a delay slot, come back to
-         * the jump.
-         */
-        bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
-    }
-
-    return bad_pc;
-}
-
-#if !defined(CONFIG_USER_ONLY)
 static void set_hflags_for_handler(CPUMIPSState *env)
 {
     /* Exception handlers are entered in 32-bit mode.  */
@@ -1400,24 +1233,6 @@ void mips_cpu_do_interrupt(CPUState *cs)
     cs->exception_index = EXCP_NONE;
 }
 
-bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
-{
-    if (interrupt_request & CPU_INTERRUPT_HARD) {
-        MIPSCPU *cpu = MIPS_CPU(cs);
-        CPUMIPSState *env = &cpu->env;
-
-        if (cpu_mips_hw_interrupts_enabled(env) &&
-            cpu_mips_hw_interrupts_pending(env)) {
-            /* Raise it */
-            cs->exception_index = EXCP_EXT_INTERRUPT;
-            env->error_code = 0;
-            mips_cpu_do_interrupt(cs);
-            return true;
-        }
-    }
-    return false;
-}
-
 #if !defined(CONFIG_USER_ONLY)
 void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
 {
@@ -1484,19 +1299,3 @@ void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
     }
 }
 #endif /* !CONFIG_USER_ONLY */
-
-void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
-                                          uint32_t exception,
-                                          int error_code,
-                                          uintptr_t pc)
-{
-    CPUState *cs = env_cpu(env);
-
-    qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n",
-                  __func__, exception, mips_exception_name(exception),
-                  error_code);
-    cs->exception_index = exception;
-    env->error_code = error_code;
-
-    cpu_loop_exit_restore(cs, pc);
-}
-- 
2.26.2


^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 05/16] target/mips: Extract common helpers from helper.c to common_helper.c
@ 2020-12-14 18:37   ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, kvm, Huacai Chen, Laurent Vivier, Jiaxun Yang,
	Philippe Mathieu-Daudé,
	Paolo Bonzini, Aurelien Jarno

The rest of helper.c is TLB related. Extract the non TLB
specific functions to a new file, so we can rename helper.c
as tlb_helper.c in the next commit.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/internal.h |   2 +
 target/mips/cpu.c      | 215 +++++++++++++++++++++++++++++++++++++++--
 target/mips/helper.c   | 201 --------------------------------------
 3 files changed, 211 insertions(+), 207 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 24d9f0d6a5c..c1401492c46 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -399,6 +399,8 @@ void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
 
+const char *mips_exception_name(int32_t exception);
+
 void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
                                           int error_code, uintptr_t pc);
 
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 7a0dcb11ecd..a54be034a2b 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -34,6 +34,215 @@
 #include "hw/semihosting/semihost.h"
 #include "qapi/qapi-commands-machine-target.h"
 
+#if !defined(CONFIG_USER_ONLY)
+
+/* Called for updates to CP0_Status.  */
+void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
+{
+    int32_t tcstatus, *tcst;
+    uint32_t v = cpu->CP0_Status;
+    uint32_t cu, mx, asid, ksu;
+    uint32_t mask = ((1 << CP0TCSt_TCU3)
+                       | (1 << CP0TCSt_TCU2)
+                       | (1 << CP0TCSt_TCU1)
+                       | (1 << CP0TCSt_TCU0)
+                       | (1 << CP0TCSt_TMX)
+                       | (3 << CP0TCSt_TKSU)
+                       | (0xff << CP0TCSt_TASID));
+
+    cu = (v >> CP0St_CU0) & 0xf;
+    mx = (v >> CP0St_MX) & 0x1;
+    ksu = (v >> CP0St_KSU) & 0x3;
+    asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
+
+    tcstatus = cu << CP0TCSt_TCU0;
+    tcstatus |= mx << CP0TCSt_TMX;
+    tcstatus |= ksu << CP0TCSt_TKSU;
+    tcstatus |= asid;
+
+    if (tc == cpu->current_tc) {
+        tcst = &cpu->active_tc.CP0_TCStatus;
+    } else {
+        tcst = &cpu->tcs[tc].CP0_TCStatus;
+    }
+
+    *tcst &= ~mask;
+    *tcst |= tcstatus;
+    compute_hflags(cpu);
+}
+
+void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
+{
+    uint32_t mask = env->CP0_Status_rw_bitmask;
+    target_ulong old = env->CP0_Status;
+
+    if (env->insn_flags & ISA_MIPS32R6) {
+        bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
+#if defined(TARGET_MIPS64)
+        uint32_t ksux = (1 << CP0St_KX) & val;
+        ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
+        ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
+        val = (val & ~(7 << CP0St_UX)) | ksux;
+#endif
+        if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
+            mask &= ~(3 << CP0St_KSU);
+        }
+        mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
+    }
+
+    env->CP0_Status = (old & ~mask) | (val & mask);
+#if defined(TARGET_MIPS64)
+    if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
+        /* Access to at least one of the 64-bit segments has been disabled */
+        tlb_flush(env_cpu(env));
+    }
+#endif
+    if (ase_mt_available(env)) {
+        sync_c0_status(env, env, env->current_tc);
+    } else {
+        compute_hflags(env);
+    }
+}
+
+void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
+{
+    uint32_t mask = 0x00C00300;
+    uint32_t old = env->CP0_Cause;
+    int i;
+
+    if (env->insn_flags & ISA_MIPS32R2) {
+        mask |= 1 << CP0Ca_DC;
+    }
+    if (env->insn_flags & ISA_MIPS32R6) {
+        mask &= ~((1 << CP0Ca_WP) & val);
+    }
+
+    env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
+
+    if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
+        if (env->CP0_Cause & (1 << CP0Ca_DC)) {
+            cpu_mips_stop_count(env);
+        } else {
+            cpu_mips_start_count(env);
+        }
+    }
+
+    /* Set/reset software interrupts */
+    for (i = 0 ; i < 2 ; i++) {
+        if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
+            cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
+        }
+    }
+}
+
+#endif /* !CONFIG_USER_ONLY */
+
+static const char * const excp_names[EXCP_LAST + 1] = {
+    [EXCP_RESET] = "reset",
+    [EXCP_SRESET] = "soft reset",
+    [EXCP_DSS] = "debug single step",
+    [EXCP_DINT] = "debug interrupt",
+    [EXCP_NMI] = "non-maskable interrupt",
+    [EXCP_MCHECK] = "machine check",
+    [EXCP_EXT_INTERRUPT] = "interrupt",
+    [EXCP_DFWATCH] = "deferred watchpoint",
+    [EXCP_DIB] = "debug instruction breakpoint",
+    [EXCP_IWATCH] = "instruction fetch watchpoint",
+    [EXCP_AdEL] = "address error load",
+    [EXCP_AdES] = "address error store",
+    [EXCP_TLBF] = "TLB refill",
+    [EXCP_IBE] = "instruction bus error",
+    [EXCP_DBp] = "debug breakpoint",
+    [EXCP_SYSCALL] = "syscall",
+    [EXCP_BREAK] = "break",
+    [EXCP_CpU] = "coprocessor unusable",
+    [EXCP_RI] = "reserved instruction",
+    [EXCP_OVERFLOW] = "arithmetic overflow",
+    [EXCP_TRAP] = "trap",
+    [EXCP_FPE] = "floating point",
+    [EXCP_DDBS] = "debug data break store",
+    [EXCP_DWATCH] = "data watchpoint",
+    [EXCP_LTLBL] = "TLB modify",
+    [EXCP_TLBL] = "TLB load",
+    [EXCP_TLBS] = "TLB store",
+    [EXCP_DBE] = "data bus error",
+    [EXCP_DDBL] = "debug data break load",
+    [EXCP_THREAD] = "thread",
+    [EXCP_MDMX] = "MDMX",
+    [EXCP_C2E] = "precise coprocessor 2",
+    [EXCP_CACHE] = "cache error",
+    [EXCP_TLBXI] = "TLB execute-inhibit",
+    [EXCP_TLBRI] = "TLB read-inhibit",
+    [EXCP_MSADIS] = "MSA disabled",
+    [EXCP_MSAFPE] = "MSA floating point",
+};
+
+const char *mips_exception_name(int32_t exception)
+{
+    if (exception < 0 || exception > EXCP_LAST) {
+        return "unknown";
+    }
+    return excp_names[exception];
+}
+
+void cpu_set_exception_base(int vp_index, target_ulong address)
+{
+    MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));
+    vp->env.exception_base = address;
+}
+
+target_ulong exception_resume_pc(CPUMIPSState *env)
+{
+    target_ulong bad_pc;
+    target_ulong isa_mode;
+
+    isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
+    bad_pc = env->active_tc.PC | isa_mode;
+    if (env->hflags & MIPS_HFLAG_BMASK) {
+        /*
+         * If the exception was raised from a delay slot, come back to
+         * the jump.
+         */
+        bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
+    }
+
+    return bad_pc;
+}
+
+bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+{
+    if (interrupt_request & CPU_INTERRUPT_HARD) {
+        MIPSCPU *cpu = MIPS_CPU(cs);
+        CPUMIPSState *env = &cpu->env;
+
+        if (cpu_mips_hw_interrupts_enabled(env) &&
+            cpu_mips_hw_interrupts_pending(env)) {
+            /* Raise it */
+            cs->exception_index = EXCP_EXT_INTERRUPT;
+            env->error_code = 0;
+            mips_cpu_do_interrupt(cs);
+            return true;
+        }
+    }
+    return false;
+}
+
+void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
+                                          uint32_t exception,
+                                          int error_code,
+                                          uintptr_t pc)
+{
+    CPUState *cs = env_cpu(env);
+
+    qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n",
+                  __func__, exception, mips_exception_name(exception),
+                  error_code);
+    cs->exception_index = exception;
+    env->error_code = error_code;
+
+    cpu_loop_exit_restore(cs, pc);
+}
+
 static void mips_cpu_set_pc(CPUState *cs, vaddr value)
 {
     MIPSCPU *cpu = MIPS_CPU(cs);
@@ -591,9 +800,3 @@ bool cpu_type_supports_cps_smp(const char *cpu_type)
     const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
     return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
 }
-
-void cpu_set_exception_base(int vp_index, target_ulong address)
-{
-    MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));
-    vp->env.exception_base = address;
-}
diff --git a/target/mips/helper.c b/target/mips/helper.c
index 0692e232f0a..59787b870b8 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -357,105 +357,6 @@ void cpu_mips_tlb_flush(CPUMIPSState *env)
     env->tlb->tlb_in_use = env->tlb->nb_tlb;
 }
 
-/* Called for updates to CP0_Status.  */
-void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
-{
-    int32_t tcstatus, *tcst;
-    uint32_t v = cpu->CP0_Status;
-    uint32_t cu, mx, asid, ksu;
-    uint32_t mask = ((1 << CP0TCSt_TCU3)
-                       | (1 << CP0TCSt_TCU2)
-                       | (1 << CP0TCSt_TCU1)
-                       | (1 << CP0TCSt_TCU0)
-                       | (1 << CP0TCSt_TMX)
-                       | (3 << CP0TCSt_TKSU)
-                       | (0xff << CP0TCSt_TASID));
-
-    cu = (v >> CP0St_CU0) & 0xf;
-    mx = (v >> CP0St_MX) & 0x1;
-    ksu = (v >> CP0St_KSU) & 0x3;
-    asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
-
-    tcstatus = cu << CP0TCSt_TCU0;
-    tcstatus |= mx << CP0TCSt_TMX;
-    tcstatus |= ksu << CP0TCSt_TKSU;
-    tcstatus |= asid;
-
-    if (tc == cpu->current_tc) {
-        tcst = &cpu->active_tc.CP0_TCStatus;
-    } else {
-        tcst = &cpu->tcs[tc].CP0_TCStatus;
-    }
-
-    *tcst &= ~mask;
-    *tcst |= tcstatus;
-    compute_hflags(cpu);
-}
-
-void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
-{
-    uint32_t mask = env->CP0_Status_rw_bitmask;
-    target_ulong old = env->CP0_Status;
-
-    if (env->insn_flags & ISA_MIPS32R6) {
-        bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
-#if defined(TARGET_MIPS64)
-        uint32_t ksux = (1 << CP0St_KX) & val;
-        ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
-        ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
-        val = (val & ~(7 << CP0St_UX)) | ksux;
-#endif
-        if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
-            mask &= ~(3 << CP0St_KSU);
-        }
-        mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
-    }
-
-    env->CP0_Status = (old & ~mask) | (val & mask);
-#if defined(TARGET_MIPS64)
-    if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
-        /* Access to at least one of the 64-bit segments has been disabled */
-        tlb_flush(env_cpu(env));
-    }
-#endif
-    if (ase_mt_available(env)) {
-        sync_c0_status(env, env, env->current_tc);
-    } else {
-        compute_hflags(env);
-    }
-}
-
-void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
-{
-    uint32_t mask = 0x00C00300;
-    uint32_t old = env->CP0_Cause;
-    int i;
-
-    if (env->insn_flags & ISA_MIPS32R2) {
-        mask |= 1 << CP0Ca_DC;
-    }
-    if (env->insn_flags & ISA_MIPS32R6) {
-        mask &= ~((1 << CP0Ca_WP) & val);
-    }
-
-    env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
-
-    if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
-        if (env->CP0_Cause & (1 << CP0Ca_DC)) {
-            cpu_mips_stop_count(env);
-        } else {
-            cpu_mips_start_count(env);
-        }
-    }
-
-    /* Set/reset software interrupts */
-    for (i = 0 ; i < 2 ; i++) {
-        if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
-            cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
-        }
-    }
-}
-
 #endif /* !CONFIG_USER_ONLY */
 
 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
@@ -977,75 +878,7 @@ hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
         return physical;
     }
 }
-#endif /* !CONFIG_USER_ONLY */
 
-static const char * const excp_names[EXCP_LAST + 1] = {
-    [EXCP_RESET] = "reset",
-    [EXCP_SRESET] = "soft reset",
-    [EXCP_DSS] = "debug single step",
-    [EXCP_DINT] = "debug interrupt",
-    [EXCP_NMI] = "non-maskable interrupt",
-    [EXCP_MCHECK] = "machine check",
-    [EXCP_EXT_INTERRUPT] = "interrupt",
-    [EXCP_DFWATCH] = "deferred watchpoint",
-    [EXCP_DIB] = "debug instruction breakpoint",
-    [EXCP_IWATCH] = "instruction fetch watchpoint",
-    [EXCP_AdEL] = "address error load",
-    [EXCP_AdES] = "address error store",
-    [EXCP_TLBF] = "TLB refill",
-    [EXCP_IBE] = "instruction bus error",
-    [EXCP_DBp] = "debug breakpoint",
-    [EXCP_SYSCALL] = "syscall",
-    [EXCP_BREAK] = "break",
-    [EXCP_CpU] = "coprocessor unusable",
-    [EXCP_RI] = "reserved instruction",
-    [EXCP_OVERFLOW] = "arithmetic overflow",
-    [EXCP_TRAP] = "trap",
-    [EXCP_FPE] = "floating point",
-    [EXCP_DDBS] = "debug data break store",
-    [EXCP_DWATCH] = "data watchpoint",
-    [EXCP_LTLBL] = "TLB modify",
-    [EXCP_TLBL] = "TLB load",
-    [EXCP_TLBS] = "TLB store",
-    [EXCP_DBE] = "data bus error",
-    [EXCP_DDBL] = "debug data break load",
-    [EXCP_THREAD] = "thread",
-    [EXCP_MDMX] = "MDMX",
-    [EXCP_C2E] = "precise coprocessor 2",
-    [EXCP_CACHE] = "cache error",
-    [EXCP_TLBXI] = "TLB execute-inhibit",
-    [EXCP_TLBRI] = "TLB read-inhibit",
-    [EXCP_MSADIS] = "MSA disabled",
-    [EXCP_MSAFPE] = "MSA floating point",
-};
-
-static const char *mips_exception_name(int32_t exception)
-{
-    if (exception < 0 || exception > EXCP_LAST) {
-        return "unknown";
-    }
-    return excp_names[exception];
-}
-
-target_ulong exception_resume_pc(CPUMIPSState *env)
-{
-    target_ulong bad_pc;
-    target_ulong isa_mode;
-
-    isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
-    bad_pc = env->active_tc.PC | isa_mode;
-    if (env->hflags & MIPS_HFLAG_BMASK) {
-        /*
-         * If the exception was raised from a delay slot, come back to
-         * the jump.
-         */
-        bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
-    }
-
-    return bad_pc;
-}
-
-#if !defined(CONFIG_USER_ONLY)
 static void set_hflags_for_handler(CPUMIPSState *env)
 {
     /* Exception handlers are entered in 32-bit mode.  */
@@ -1400,24 +1233,6 @@ void mips_cpu_do_interrupt(CPUState *cs)
     cs->exception_index = EXCP_NONE;
 }
 
-bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
-{
-    if (interrupt_request & CPU_INTERRUPT_HARD) {
-        MIPSCPU *cpu = MIPS_CPU(cs);
-        CPUMIPSState *env = &cpu->env;
-
-        if (cpu_mips_hw_interrupts_enabled(env) &&
-            cpu_mips_hw_interrupts_pending(env)) {
-            /* Raise it */
-            cs->exception_index = EXCP_EXT_INTERRUPT;
-            env->error_code = 0;
-            mips_cpu_do_interrupt(cs);
-            return true;
-        }
-    }
-    return false;
-}
-
 #if !defined(CONFIG_USER_ONLY)
 void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
 {
@@ -1484,19 +1299,3 @@ void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
     }
 }
 #endif /* !CONFIG_USER_ONLY */
-
-void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
-                                          uint32_t exception,
-                                          int error_code,
-                                          uintptr_t pc)
-{
-    CPUState *cs = env_cpu(env);
-
-    qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n",
-                  __func__, exception, mips_exception_name(exception),
-                  error_code);
-    cs->exception_index = exception;
-    env->error_code = error_code;
-
-    cpu_loop_exit_restore(cs, pc);
-}
-- 
2.26.2



^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 06/16] target/mips: Rename helper.c as tlb_helper.c
  2020-12-14 18:37 ` Philippe Mathieu-Daudé
@ 2020-12-14 18:37   ` Philippe Mathieu-Daudé
  -1 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: kvm, Aurelien Jarno, Huacai Chen, Aleksandar Rikalo, Jiaxun Yang,
	Laurent Vivier, Paolo Bonzini, Philippe Mathieu-Daudé,
	Richard Henderson

This file contains functions related to TLB management,
rename it as 'tlb_helper.c'.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201206233949.3783184-13-f4bug@amsat.org>
---
 target/mips/{helper.c => tlb_helper.c} | 2 +-
 target/mips/meson.build                | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)
 rename target/mips/{helper.c => tlb_helper.c} (99%)

diff --git a/target/mips/helper.c b/target/mips/tlb_helper.c
similarity index 99%
rename from target/mips/helper.c
rename to target/mips/tlb_helper.c
index 59787b870b8..2e52539a511 100644
--- a/target/mips/helper.c
+++ b/target/mips/tlb_helper.c
@@ -1,5 +1,5 @@
 /*
- *  MIPS emulation helpers for qemu.
+ * MIPS TLB (Translation lookaside buffer) helpers.
  *
  *  Copyright (c) 2004-2005 Jocelyn Mayer
  *
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 4179395a8ea..5a49951c6d7 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -4,10 +4,10 @@
   'dsp_helper.c',
   'fpu_helper.c',
   'gdbstub.c',
-  'helper.c',
   'lmmi_helper.c',
   'msa_helper.c',
   'op_helper.c',
+  'tlb_helper.c',
   'translate.c',
 ))
 mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
-- 
2.26.2


^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 06/16] target/mips: Rename helper.c as tlb_helper.c
@ 2020-12-14 18:37   ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, kvm, Huacai Chen, Richard Henderson,
	Laurent Vivier, Jiaxun Yang, Philippe Mathieu-Daudé,
	Paolo Bonzini, Aurelien Jarno

This file contains functions related to TLB management,
rename it as 'tlb_helper.c'.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201206233949.3783184-13-f4bug@amsat.org>
---
 target/mips/{helper.c => tlb_helper.c} | 2 +-
 target/mips/meson.build                | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)
 rename target/mips/{helper.c => tlb_helper.c} (99%)

diff --git a/target/mips/helper.c b/target/mips/tlb_helper.c
similarity index 99%
rename from target/mips/helper.c
rename to target/mips/tlb_helper.c
index 59787b870b8..2e52539a511 100644
--- a/target/mips/helper.c
+++ b/target/mips/tlb_helper.c
@@ -1,5 +1,5 @@
 /*
- *  MIPS emulation helpers for qemu.
+ * MIPS TLB (Translation lookaside buffer) helpers.
  *
  *  Copyright (c) 2004-2005 Jocelyn Mayer
  *
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 4179395a8ea..5a49951c6d7 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -4,10 +4,10 @@
   'dsp_helper.c',
   'fpu_helper.c',
   'gdbstub.c',
-  'helper.c',
   'lmmi_helper.c',
   'msa_helper.c',
   'op_helper.c',
+  'tlb_helper.c',
   'translate.c',
 ))
 mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
-- 
2.26.2



^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 07/16] target/mips: Fix code style for checkpatch.pl
  2020-12-14 18:37 ` Philippe Mathieu-Daudé
@ 2020-12-14 18:37   ` Philippe Mathieu-Daudé
  -1 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: kvm, Aurelien Jarno, Huacai Chen, Aleksandar Rikalo, Jiaxun Yang,
	Laurent Vivier, Paolo Bonzini, Philippe Mathieu-Daudé,
	Richard Henderson

We are going to move this code, fix its style first.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201206233949.3783184-14-f4bug@amsat.org>
---
 target/mips/translate_init.c.inc | 36 ++++++++++++++++----------------
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index 915277dd1f6..ff14502529b 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -934,19 +934,19 @@ void mips_cpu_list(void)
 }
 
 #ifndef CONFIG_USER_ONLY
-static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
+static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def)
 {
     env->tlb->nb_tlb = 1;
     env->tlb->map_address = &no_mmu_map_address;
 }
 
-static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
+static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def)
 {
     env->tlb->nb_tlb = 1;
     env->tlb->map_address = &fixed_mmu_map_address;
 }
 
-static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
+static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def)
 {
     env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
     env->tlb->map_address = &r4k_map_address;
@@ -958,25 +958,25 @@ static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
     env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
 }
 
-static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
+static void mmu_init(CPUMIPSState *env, const mips_def_t *def)
 {
     env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
 
     switch (def->mmu_type) {
-        case MMU_TYPE_NONE:
-            no_mmu_init(env, def);
-            break;
-        case MMU_TYPE_R4000:
-            r4k_mmu_init(env, def);
-            break;
-        case MMU_TYPE_FMT:
-            fixed_mmu_init(env, def);
-            break;
-        case MMU_TYPE_R3000:
-        case MMU_TYPE_R6000:
-        case MMU_TYPE_R8000:
-        default:
-            cpu_abort(env_cpu(env), "MMU type not supported\n");
+    case MMU_TYPE_NONE:
+        no_mmu_init(env, def);
+        break;
+    case MMU_TYPE_R4000:
+        r4k_mmu_init(env, def);
+        break;
+    case MMU_TYPE_FMT:
+        fixed_mmu_init(env, def);
+        break;
+    case MMU_TYPE_R3000:
+    case MMU_TYPE_R6000:
+    case MMU_TYPE_R8000:
+    default:
+        cpu_abort(env_cpu(env), "MMU type not supported\n");
     }
 }
 #endif /* CONFIG_USER_ONLY */
-- 
2.26.2


^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 07/16] target/mips: Fix code style for checkpatch.pl
@ 2020-12-14 18:37   ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, kvm, Huacai Chen, Richard Henderson,
	Laurent Vivier, Jiaxun Yang, Philippe Mathieu-Daudé,
	Paolo Bonzini, Aurelien Jarno

We are going to move this code, fix its style first.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201206233949.3783184-14-f4bug@amsat.org>
---
 target/mips/translate_init.c.inc | 36 ++++++++++++++++----------------
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index 915277dd1f6..ff14502529b 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -934,19 +934,19 @@ void mips_cpu_list(void)
 }
 
 #ifndef CONFIG_USER_ONLY
-static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
+static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def)
 {
     env->tlb->nb_tlb = 1;
     env->tlb->map_address = &no_mmu_map_address;
 }
 
-static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
+static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def)
 {
     env->tlb->nb_tlb = 1;
     env->tlb->map_address = &fixed_mmu_map_address;
 }
 
-static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
+static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def)
 {
     env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
     env->tlb->map_address = &r4k_map_address;
@@ -958,25 +958,25 @@ static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
     env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
 }
 
-static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
+static void mmu_init(CPUMIPSState *env, const mips_def_t *def)
 {
     env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
 
     switch (def->mmu_type) {
-        case MMU_TYPE_NONE:
-            no_mmu_init(env, def);
-            break;
-        case MMU_TYPE_R4000:
-            r4k_mmu_init(env, def);
-            break;
-        case MMU_TYPE_FMT:
-            fixed_mmu_init(env, def);
-            break;
-        case MMU_TYPE_R3000:
-        case MMU_TYPE_R6000:
-        case MMU_TYPE_R8000:
-        default:
-            cpu_abort(env_cpu(env), "MMU type not supported\n");
+    case MMU_TYPE_NONE:
+        no_mmu_init(env, def);
+        break;
+    case MMU_TYPE_R4000:
+        r4k_mmu_init(env, def);
+        break;
+    case MMU_TYPE_FMT:
+        fixed_mmu_init(env, def);
+        break;
+    case MMU_TYPE_R3000:
+    case MMU_TYPE_R6000:
+    case MMU_TYPE_R8000:
+    default:
+        cpu_abort(env_cpu(env), "MMU type not supported\n");
     }
 }
 #endif /* CONFIG_USER_ONLY */
-- 
2.26.2



^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 08/16] target/mips: Move mmu_init() functions to tlb_helper.c
  2020-12-14 18:37 ` Philippe Mathieu-Daudé
@ 2020-12-14 18:37   ` Philippe Mathieu-Daudé
  -1 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: kvm, Aurelien Jarno, Huacai Chen, Aleksandar Rikalo, Jiaxun Yang,
	Laurent Vivier, Paolo Bonzini, Philippe Mathieu-Daudé,
	Richard Henderson

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201206233949.3783184-15-f4bug@amsat.org>
---
 target/mips/internal.h           |  1 +
 target/mips/tlb_helper.c         | 46 ++++++++++++++++++++++++++++++
 target/mips/translate_init.c.inc | 48 --------------------------------
 3 files changed, 47 insertions(+), 48 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index c1401492c46..968a3a8db8f 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -207,6 +207,7 @@ void cpu_mips_start_count(CPUMIPSState *env);
 void cpu_mips_stop_count(CPUMIPSState *env);
 
 /* helper.c */
+void mmu_init(CPUMIPSState *env, const mips_def_t *def);
 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                        MMUAccessType access_type, int mmu_idx,
                        bool probe, uintptr_t retaddr);
diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c
index 2e52539a511..94a482e3dbe 100644
--- a/target/mips/tlb_helper.c
+++ b/target/mips/tlb_helper.c
@@ -120,6 +120,52 @@ int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
     return TLBRET_NOMATCH;
 }
 
+static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def)
+{
+    env->tlb->nb_tlb = 1;
+    env->tlb->map_address = &no_mmu_map_address;
+}
+
+static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def)
+{
+    env->tlb->nb_tlb = 1;
+    env->tlb->map_address = &fixed_mmu_map_address;
+}
+
+static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def)
+{
+    env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
+    env->tlb->map_address = &r4k_map_address;
+    env->tlb->helper_tlbwi = r4k_helper_tlbwi;
+    env->tlb->helper_tlbwr = r4k_helper_tlbwr;
+    env->tlb->helper_tlbp = r4k_helper_tlbp;
+    env->tlb->helper_tlbr = r4k_helper_tlbr;
+    env->tlb->helper_tlbinv = r4k_helper_tlbinv;
+    env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
+}
+
+void mmu_init(CPUMIPSState *env, const mips_def_t *def)
+{
+    env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
+
+    switch (def->mmu_type) {
+    case MMU_TYPE_NONE:
+        no_mmu_init(env, def);
+        break;
+    case MMU_TYPE_R4000:
+        r4k_mmu_init(env, def);
+        break;
+    case MMU_TYPE_FMT:
+        fixed_mmu_init(env, def);
+        break;
+    case MMU_TYPE_R3000:
+    case MMU_TYPE_R6000:
+    case MMU_TYPE_R8000:
+    default:
+        cpu_abort(env_cpu(env), "MMU type not supported\n");
+    }
+}
+
 static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx)
 {
     /*
diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index ff14502529b..a788f5a6b6d 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -933,54 +933,6 @@ void mips_cpu_list(void)
     }
 }
 
-#ifndef CONFIG_USER_ONLY
-static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def)
-{
-    env->tlb->nb_tlb = 1;
-    env->tlb->map_address = &no_mmu_map_address;
-}
-
-static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def)
-{
-    env->tlb->nb_tlb = 1;
-    env->tlb->map_address = &fixed_mmu_map_address;
-}
-
-static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def)
-{
-    env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
-    env->tlb->map_address = &r4k_map_address;
-    env->tlb->helper_tlbwi = r4k_helper_tlbwi;
-    env->tlb->helper_tlbwr = r4k_helper_tlbwr;
-    env->tlb->helper_tlbp = r4k_helper_tlbp;
-    env->tlb->helper_tlbr = r4k_helper_tlbr;
-    env->tlb->helper_tlbinv = r4k_helper_tlbinv;
-    env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
-}
-
-static void mmu_init(CPUMIPSState *env, const mips_def_t *def)
-{
-    env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
-
-    switch (def->mmu_type) {
-    case MMU_TYPE_NONE:
-        no_mmu_init(env, def);
-        break;
-    case MMU_TYPE_R4000:
-        r4k_mmu_init(env, def);
-        break;
-    case MMU_TYPE_FMT:
-        fixed_mmu_init(env, def);
-        break;
-    case MMU_TYPE_R3000:
-    case MMU_TYPE_R6000:
-    case MMU_TYPE_R8000:
-    default:
-        cpu_abort(env_cpu(env), "MMU type not supported\n");
-    }
-}
-#endif /* CONFIG_USER_ONLY */
-
 static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
 {
     int i;
-- 
2.26.2


^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 08/16] target/mips: Move mmu_init() functions to tlb_helper.c
@ 2020-12-14 18:37   ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, kvm, Huacai Chen, Richard Henderson,
	Laurent Vivier, Jiaxun Yang, Philippe Mathieu-Daudé,
	Paolo Bonzini, Aurelien Jarno

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201206233949.3783184-15-f4bug@amsat.org>
---
 target/mips/internal.h           |  1 +
 target/mips/tlb_helper.c         | 46 ++++++++++++++++++++++++++++++
 target/mips/translate_init.c.inc | 48 --------------------------------
 3 files changed, 47 insertions(+), 48 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index c1401492c46..968a3a8db8f 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -207,6 +207,7 @@ void cpu_mips_start_count(CPUMIPSState *env);
 void cpu_mips_stop_count(CPUMIPSState *env);
 
 /* helper.c */
+void mmu_init(CPUMIPSState *env, const mips_def_t *def);
 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                        MMUAccessType access_type, int mmu_idx,
                        bool probe, uintptr_t retaddr);
diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c
index 2e52539a511..94a482e3dbe 100644
--- a/target/mips/tlb_helper.c
+++ b/target/mips/tlb_helper.c
@@ -120,6 +120,52 @@ int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
     return TLBRET_NOMATCH;
 }
 
+static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def)
+{
+    env->tlb->nb_tlb = 1;
+    env->tlb->map_address = &no_mmu_map_address;
+}
+
+static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def)
+{
+    env->tlb->nb_tlb = 1;
+    env->tlb->map_address = &fixed_mmu_map_address;
+}
+
+static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def)
+{
+    env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
+    env->tlb->map_address = &r4k_map_address;
+    env->tlb->helper_tlbwi = r4k_helper_tlbwi;
+    env->tlb->helper_tlbwr = r4k_helper_tlbwr;
+    env->tlb->helper_tlbp = r4k_helper_tlbp;
+    env->tlb->helper_tlbr = r4k_helper_tlbr;
+    env->tlb->helper_tlbinv = r4k_helper_tlbinv;
+    env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
+}
+
+void mmu_init(CPUMIPSState *env, const mips_def_t *def)
+{
+    env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
+
+    switch (def->mmu_type) {
+    case MMU_TYPE_NONE:
+        no_mmu_init(env, def);
+        break;
+    case MMU_TYPE_R4000:
+        r4k_mmu_init(env, def);
+        break;
+    case MMU_TYPE_FMT:
+        fixed_mmu_init(env, def);
+        break;
+    case MMU_TYPE_R3000:
+    case MMU_TYPE_R6000:
+    case MMU_TYPE_R8000:
+    default:
+        cpu_abort(env_cpu(env), "MMU type not supported\n");
+    }
+}
+
 static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx)
 {
     /*
diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index ff14502529b..a788f5a6b6d 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -933,54 +933,6 @@ void mips_cpu_list(void)
     }
 }
 
-#ifndef CONFIG_USER_ONLY
-static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def)
-{
-    env->tlb->nb_tlb = 1;
-    env->tlb->map_address = &no_mmu_map_address;
-}
-
-static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def)
-{
-    env->tlb->nb_tlb = 1;
-    env->tlb->map_address = &fixed_mmu_map_address;
-}
-
-static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def)
-{
-    env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
-    env->tlb->map_address = &r4k_map_address;
-    env->tlb->helper_tlbwi = r4k_helper_tlbwi;
-    env->tlb->helper_tlbwr = r4k_helper_tlbwr;
-    env->tlb->helper_tlbp = r4k_helper_tlbp;
-    env->tlb->helper_tlbr = r4k_helper_tlbr;
-    env->tlb->helper_tlbinv = r4k_helper_tlbinv;
-    env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
-}
-
-static void mmu_init(CPUMIPSState *env, const mips_def_t *def)
-{
-    env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
-
-    switch (def->mmu_type) {
-    case MMU_TYPE_NONE:
-        no_mmu_init(env, def);
-        break;
-    case MMU_TYPE_R4000:
-        r4k_mmu_init(env, def);
-        break;
-    case MMU_TYPE_FMT:
-        fixed_mmu_init(env, def);
-        break;
-    case MMU_TYPE_R3000:
-    case MMU_TYPE_R6000:
-    case MMU_TYPE_R8000:
-    default:
-        cpu_abort(env_cpu(env), "MMU type not supported\n");
-    }
-}
-#endif /* CONFIG_USER_ONLY */
-
 static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
 {
     int i;
-- 
2.26.2



^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 09/16] target/mips: Rename translate_init.c as cpu-defs.c
  2020-12-14 18:37 ` Philippe Mathieu-Daudé
@ 2020-12-14 18:37   ` Philippe Mathieu-Daudé
  -1 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: kvm, Aurelien Jarno, Huacai Chen, Aleksandar Rikalo, Jiaxun Yang,
	Laurent Vivier, Paolo Bonzini, Philippe Mathieu-Daudé

This file is not TCG specific, contains CPU definitions
and is consumed by cpu.c. Rename it as such.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/cpu.c                                    | 2 +-
 target/mips/{translate_init.c.inc => cpu-defs.c.inc} | 0
 2 files changed, 1 insertion(+), 1 deletion(-)
 rename target/mips/{translate_init.c.inc => cpu-defs.c.inc} (100%)

diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index a54be034a2b..4191c0741f4 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -311,7 +311,7 @@ static bool mips_cpu_has_work(CPUState *cs)
     return has_work;
 }
 
-#include "translate_init.c.inc"
+#include "cpu-defs.c.inc"
 
 static void mips_cpu_reset(DeviceState *dev)
 {
diff --git a/target/mips/translate_init.c.inc b/target/mips/cpu-defs.c.inc
similarity index 100%
rename from target/mips/translate_init.c.inc
rename to target/mips/cpu-defs.c.inc
-- 
2.26.2


^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 09/16] target/mips: Rename translate_init.c as cpu-defs.c
@ 2020-12-14 18:37   ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, kvm, Huacai Chen, Laurent Vivier, Jiaxun Yang,
	Philippe Mathieu-Daudé,
	Paolo Bonzini, Aurelien Jarno

This file is not TCG specific, contains CPU definitions
and is consumed by cpu.c. Rename it as such.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/cpu.c                                    | 2 +-
 target/mips/{translate_init.c.inc => cpu-defs.c.inc} | 0
 2 files changed, 1 insertion(+), 1 deletion(-)
 rename target/mips/{translate_init.c.inc => cpu-defs.c.inc} (100%)

diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index a54be034a2b..4191c0741f4 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -311,7 +311,7 @@ static bool mips_cpu_has_work(CPUState *cs)
     return has_work;
 }
 
-#include "translate_init.c.inc"
+#include "cpu-defs.c.inc"
 
 static void mips_cpu_reset(DeviceState *dev)
 {
diff --git a/target/mips/translate_init.c.inc b/target/mips/cpu-defs.c.inc
similarity index 100%
rename from target/mips/translate_init.c.inc
rename to target/mips/cpu-defs.c.inc
-- 
2.26.2



^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 10/16] target/mips: Replace gen_exception_err(err=0) by gen_exception_end()
  2020-12-14 18:37 ` Philippe Mathieu-Daudé
@ 2020-12-14 18:37   ` Philippe Mathieu-Daudé
  -1 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: kvm, Aurelien Jarno, Huacai Chen, Aleksandar Rikalo, Jiaxun Yang,
	Laurent Vivier, Paolo Bonzini, Philippe Mathieu-Daudé

generate_exception_err(err=0) is simply generate_exception_end().

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/translate.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index d2614796214..2662cf26fe7 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2956,7 +2956,7 @@ static inline void gen_move_high32(TCGv ret, TCGv_i64 arg)
 static inline void check_cp0_enabled(DisasContext *ctx)
 {
     if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) {
-        generate_exception_err(ctx, EXCP_CpU, 0);
+        generate_exception_end(ctx, EXCP_CpU);
     }
 }
 
@@ -3162,10 +3162,10 @@ static inline void check_mt(DisasContext *ctx)
 static inline void check_cp0_mt(DisasContext *ctx)
 {
     if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) {
-        generate_exception_err(ctx, EXCP_CpU, 0);
+        generate_exception_end(ctx, EXCP_CpU);
     } else {
         if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) {
-            generate_exception_err(ctx, EXCP_RI, 0);
+            generate_exception_end(ctx, EXCP_RI);
         }
     }
 }
-- 
2.26.2


^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 10/16] target/mips: Replace gen_exception_err(err=0) by gen_exception_end()
@ 2020-12-14 18:37   ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, kvm, Huacai Chen, Laurent Vivier, Jiaxun Yang,
	Philippe Mathieu-Daudé,
	Paolo Bonzini, Aurelien Jarno

generate_exception_err(err=0) is simply generate_exception_end().

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/translate.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index d2614796214..2662cf26fe7 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2956,7 +2956,7 @@ static inline void gen_move_high32(TCGv ret, TCGv_i64 arg)
 static inline void check_cp0_enabled(DisasContext *ctx)
 {
     if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) {
-        generate_exception_err(ctx, EXCP_CpU, 0);
+        generate_exception_end(ctx, EXCP_CpU);
     }
 }
 
@@ -3162,10 +3162,10 @@ static inline void check_mt(DisasContext *ctx)
 static inline void check_cp0_mt(DisasContext *ctx)
 {
     if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) {
-        generate_exception_err(ctx, EXCP_CpU, 0);
+        generate_exception_end(ctx, EXCP_CpU);
     } else {
         if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) {
-            generate_exception_err(ctx, EXCP_RI, 0);
+            generate_exception_end(ctx, EXCP_RI);
         }
     }
 }
-- 
2.26.2



^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 11/16] target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction
  2020-12-14 18:37 ` Philippe Mathieu-Daudé
                   ` (10 preceding siblings ...)
  (?)
@ 2020-12-14 18:37 ` Philippe Mathieu-Daudé
  2020-12-15 14:09   ` Richard Henderson
  -1 siblings, 1 reply; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, kvm, Huacai Chen, Laurent Vivier, Jiaxun Yang,
	Philippe Mathieu-Daudé,
	Paolo Bonzini, Aurelien Jarno

gen_reserved_instruction() is easier to read than
generate_exception_end(ctx, EXCP_RI), replace it.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/translate.c | 724 ++++++++++++++++++++--------------------
 1 file changed, 362 insertions(+), 362 deletions(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 2662cf26fe7..49570a95615 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2975,7 +2975,7 @@ static inline void check_cp1_enabled(DisasContext *ctx)
 static inline void check_cop1x(DisasContext *ctx)
 {
     if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) {
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
     }
 }
 
@@ -2986,7 +2986,7 @@ static inline void check_cop1x(DisasContext *ctx)
 static inline void check_cp1_64bitmode(DisasContext *ctx)
 {
     if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) {
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
     }
 }
 
@@ -3004,7 +3004,7 @@ static inline void check_cp1_64bitmode(DisasContext *ctx)
 static inline void check_cp1_registers(DisasContext *ctx, int regs)
 {
     if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) {
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
     }
 }
 
@@ -3018,7 +3018,7 @@ static inline void check_dsp(DisasContext *ctx)
         if (ctx->insn_flags & ASE_DSP) {
             generate_exception_end(ctx, EXCP_DSPDIS);
         } else {
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
         }
     }
 }
@@ -3029,7 +3029,7 @@ static inline void check_dsp_r2(DisasContext *ctx)
         if (ctx->insn_flags & ASE_DSP) {
             generate_exception_end(ctx, EXCP_DSPDIS);
         } else {
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
         }
     }
 }
@@ -3040,7 +3040,7 @@ static inline void check_dsp_r3(DisasContext *ctx)
         if (ctx->insn_flags & ASE_DSP) {
             generate_exception_end(ctx, EXCP_DSPDIS);
         } else {
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
         }
     }
 }
@@ -3052,7 +3052,7 @@ static inline void check_dsp_r3(DisasContext *ctx)
 static inline void check_insn(DisasContext *ctx, uint64_t flags)
 {
     if (unlikely(!(ctx->insn_flags & flags))) {
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
     }
 }
 
@@ -3064,7 +3064,7 @@ static inline void check_insn(DisasContext *ctx, uint64_t flags)
 static inline void check_insn_opc_removed(DisasContext *ctx, uint64_t flags)
 {
     if (unlikely(ctx->insn_flags & flags)) {
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
     }
 }
 
@@ -3103,7 +3103,7 @@ static inline void check_ps(DisasContext *ctx)
 static inline void check_mips_64(DisasContext *ctx)
 {
     if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) {
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
     }
 }
 #endif
@@ -3124,7 +3124,7 @@ static inline void check_mvh(DisasContext *ctx)
 static inline void check_xnp(DisasContext *ctx)
 {
     if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_XNP))) {
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
     }
 }
 
@@ -3136,7 +3136,7 @@ static inline void check_xnp(DisasContext *ctx)
 static inline void check_pw(DisasContext *ctx)
 {
     if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_PW)))) {
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
     }
 }
 #endif
@@ -3148,7 +3148,7 @@ static inline void check_pw(DisasContext *ctx)
 static inline void check_mt(DisasContext *ctx)
 {
     if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) {
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
     }
 }
 
@@ -3165,7 +3165,7 @@ static inline void check_cp0_mt(DisasContext *ctx)
         generate_exception_end(ctx, EXCP_CpU);
     } else {
         if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) {
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
         }
     }
 }
@@ -3178,7 +3178,7 @@ static inline void check_cp0_mt(DisasContext *ctx)
 static inline void check_nms(DisasContext *ctx)
 {
     if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_NMS))) {
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
     }
 }
 
@@ -3195,7 +3195,7 @@ static inline void check_nms_dl_il_sl_tl_l2c(DisasContext *ctx)
                  !(ctx->CP0_Config2 & (1 << CP0C2_SL)) &&
                  !(ctx->CP0_Config2 & (1 << CP0C2_TL)) &&
                  !(ctx->CP0_Config5 & (1 << CP0C5_L2C)))) {
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
     }
 }
 
@@ -3206,7 +3206,7 @@ static inline void check_nms_dl_il_sl_tl_l2c(DisasContext *ctx)
 static inline void check_eva(DisasContext *ctx)
 {
     if (unlikely(!(ctx->CP0_Config5 & (1 << CP0C5_EVA)))) {
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
     }
 }
 
@@ -3872,7 +3872,7 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft,
         break;
     default:
         MIPS_INVAL("flt_ldst");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -4521,7 +4521,7 @@ static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg)
         break;
     default:
         MIPS_INVAL("mfthilo1 TX79");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -4656,7 +4656,7 @@ static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc,
 #endif
         default:
             MIPS_INVAL("OPC_PCREL");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -4867,7 +4867,7 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
 #endif
     default:
         MIPS_INVAL("r6 mul/div");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         goto out;
     }
  out:
@@ -4925,7 +4925,7 @@ static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt)
         break;
     default:
         MIPS_INVAL("div1 TX79");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         goto out;
     }
  out:
@@ -5118,7 +5118,7 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
         break;
     default:
         MIPS_INVAL("mul/div");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         goto out;
     }
  out:
@@ -5249,7 +5249,7 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
         break;
     default:
         MIPS_INVAL("mul/madd TXx9");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         goto out;
     }
 
@@ -5312,7 +5312,7 @@ static void gen_mul_vr54xx(DisasContext *ctx, uint32_t opc,
         break;
     default:
         MIPS_INVAL("mul vr54xx");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         goto out;
     }
     gen_store_gpr(t0, rd);
@@ -5938,7 +5938,7 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)
         break;
     default:
         MIPS_INVAL("loongson_cp2");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         return;
     }
 
@@ -6127,7 +6127,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
 #endif
         default:
             MIPS_INVAL("loongson_gsshfl");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -6175,13 +6175,13 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
 #endif
         default:
             MIPS_INVAL("loongson_gsshfs");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
     default:
         MIPS_INVAL("loongson_gslsq");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
     tcg_temp_free(t0);
@@ -6230,7 +6230,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
         break;
     default:
         MIPS_INVAL("loongson_lsdc2");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         return;
         break;
     }
@@ -6486,7 +6486,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc,
         LOG_DISAS("Branch in delay / forbidden slot at PC 0x"
                   TARGET_FMT_lx "\n", ctx->base.pc_next);
 #endif
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         goto out;
     }
 
@@ -6549,14 +6549,14 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc,
              * others are reserved.
              */
             MIPS_INVAL("jump hint");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             goto out;
         }
         gen_load_gpr(btarget, rs);
         break;
     default:
         MIPS_INVAL("branch/jump");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         goto out;
     }
     if (bcond_compute == 0) {
@@ -6621,7 +6621,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc,
             break;
         default:
             MIPS_INVAL("branch/jump");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             goto out;
         }
     } else {
@@ -6692,7 +6692,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc,
             break;
         default:
             MIPS_INVAL("conditional branch/jump");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             goto out;
         }
     }
@@ -6769,14 +6769,14 @@ static void gen_compute_branch_nm(DisasContext *ctx, uint32_t opc,
              * others are reserved.
              */
             MIPS_INVAL("jump hint");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             goto out;
         }
         gen_load_gpr(btarget, rs);
         break;
     default:
         MIPS_INVAL("branch/jump");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         goto out;
     }
     if (bcond_compute == 0) {
@@ -6809,7 +6809,7 @@ static void gen_compute_branch_nm(DisasContext *ctx, uint32_t opc,
             break;
         default:
             MIPS_INVAL("branch/jump");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             goto out;
         }
     } else {
@@ -6832,7 +6832,7 @@ static void gen_compute_branch_nm(DisasContext *ctx, uint32_t opc,
             break;
         default:
             MIPS_INVAL("conditional branch/jump");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             goto out;
         }
     }
@@ -6912,7 +6912,7 @@ static void gen_bitops(DisasContext *ctx, uint32_t opc, int rt,
     default:
 fail:
         MIPS_INVAL("bitops");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         tcg_temp_free(t0);
         tcg_temp_free(t1);
         return;
@@ -6990,7 +6990,7 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd)
 #endif
     default:
         MIPS_INVAL("bsfhl");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         tcg_temp_free(t0);
         return;
     }
@@ -10644,7 +10644,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
 die:
     tcg_temp_free(t0);
     LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h);
-    generate_exception_end(ctx, EXCP_RI);
+    gen_reserved_instruction(ctx);
 }
 
 static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
@@ -10854,7 +10854,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
 die:
     tcg_temp_free(t0);
     LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h);
-    generate_exception_end(ctx, EXCP_RI);
+    gen_reserved_instruction(ctx);
 }
 
 static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
@@ -11014,7 +11014,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
         }
         if (!(ctx->hflags & MIPS_HFLAG_DM)) {
             MIPS_INVAL(opn);
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
         } else {
             gen_helper_deret(cpu_env);
             ctx->base.is_jmp = DISAS_EXIT;
@@ -11037,7 +11037,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
     default:
  die:
         MIPS_INVAL(opn);
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         return;
     }
     (void)opn; /* avoid a compiler warning */
@@ -11052,7 +11052,7 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
     TCGv_i32 t0 = tcg_temp_new_i32();
 
     if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) {
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         goto out;
     }
 
@@ -11143,7 +11143,7 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
         break;
     default:
         MIPS_INVAL("cp1 cond branch");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         goto out;
     }
     ctx->btarget = btarget;
@@ -11165,7 +11165,7 @@ static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op,
         LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
                   "\n", ctx->base.pc_next);
 #endif
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         goto out;
     }
 
@@ -11185,7 +11185,7 @@ static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op,
         break;
     default:
         MIPS_INVAL("cp1 cond branch");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         goto out;
     }
 
@@ -11493,7 +11493,7 @@ static void gen_cp1(DisasContext *ctx, uint32_t opc, int rt, int fs)
         break;
     default:
         MIPS_INVAL("cp1 move");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         goto out;
     }
 
@@ -11630,7 +11630,7 @@ static void gen_sel_s(DisasContext *ctx, enum fopcode op1, int fd, int ft,
         break;
     default:
         MIPS_INVAL("gen_sel_s");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 
@@ -11667,7 +11667,7 @@ static void gen_sel_d(DisasContext *ctx, enum fopcode op1, int fd, int ft,
         break;
     default:
         MIPS_INVAL("gen_sel_d");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 
@@ -13101,7 +13101,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
         break;
     default:
         MIPS_INVAL("farith");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         return;
     }
 }
@@ -13440,7 +13440,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
         break;
     default:
         MIPS_INVAL("flt3_arith");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         return;
     }
 }
@@ -13515,13 +13515,13 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
                           offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
             gen_store_gpr(t0, rt);
         } else {
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
         }
         break;
 #endif
     default:            /* Invalid */
         MIPS_INVAL("rdhwr");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
     tcg_temp_free(t0);
@@ -13620,7 +13620,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
         LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
                   "\n", ctx->base.pc_next);
 #endif
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         goto out;
     }
 
@@ -13682,7 +13682,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
         break;
     default:
         MIPS_INVAL("Compact branch/jump");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         goto out;
     }
 
@@ -13703,7 +13703,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
             break;
         default:
             MIPS_INVAL("Compact branch/jump");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             goto out;
         }
 
@@ -13826,7 +13826,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
             break;
         default:
             MIPS_INVAL("Compact conditional branch/jump");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             goto out;
         }
 
@@ -14000,7 +14000,7 @@ static void gen_mips16_save(DisasContext *ctx,
         args = 4;
         break;
     default:
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         return;
     }
 
@@ -14096,7 +14096,7 @@ static void gen_mips16_save(DisasContext *ctx,
         astatic = 4;
         break;
     default:
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         return;
     }
 
@@ -14202,7 +14202,7 @@ static void gen_mips16_restore(DisasContext *ctx,
         astatic = 4;
         break;
     default:
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         return;
     }
 
@@ -14233,7 +14233,7 @@ static void gen_addiupc(DisasContext *ctx, int rx, int imm,
     TCGv t0;
 
     if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) {
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         return;
     }
 
@@ -14291,7 +14291,7 @@ static void decode_i64_mips16(DisasContext *ctx,
         check_insn(ctx, ISA_MIPS3);
         check_mips_64(ctx);
         if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) {
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
         } else {
             offset = extended ? offset : offset << 3;
             gen_ld(ctx, OPC_LDPC, ry, 0, offset);
@@ -14368,7 +14368,7 @@ static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
             check_mips_64(ctx);
             gen_shift_imm(ctx, OPC_DSLL, rx, ry, sa);
 #else
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
 #endif
             break;
         case 0x2:
@@ -14396,7 +14396,7 @@ static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
             check_mips_64(ctx);
             gen_arith_imm(ctx, OPC_DADDIU, ry, rx, imm);
 #else
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
 #endif
         } else {
             gen_arith_imm(ctx, OPC_ADDIU, ry, rx, imm);
@@ -14448,7 +14448,7 @@ static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
             }
             break;
         default:
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -14511,7 +14511,7 @@ static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
         break;
 #endif
     default:
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 
@@ -14600,7 +14600,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
             check_mips_64(ctx);
             gen_shift_imm(ctx, OPC_DSLL, rx, ry, sa);
 #else
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
 #endif
             break;
         case 0x2:
@@ -14628,7 +14628,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
                 check_mips_64(ctx);
                 gen_arith_imm(ctx, OPC_DADDIU, ry, rx, imm);
 #else
-                generate_exception_end(ctx, EXCP_RI);
+                gen_reserved_instruction(ctx);
 #endif
             } else {
                 gen_arith_imm(ctx, OPC_ADDIU, ry, rx, imm);
@@ -14712,7 +14712,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
                 gen_arith(ctx, OPC_ADDU, ry, reg32, 0);
                 break;
             default:
-                generate_exception_end(ctx, EXCP_RI);
+                gen_reserved_instruction(ctx);
                 break;
             }
         }
@@ -14802,7 +14802,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
                 break;
 #endif
             default:
-                generate_exception_end(ctx, EXCP_RI);
+                gen_reserved_instruction(ctx);
                 goto done;
             }
 
@@ -14919,7 +14919,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
                 break;
 #endif
             default:
-                generate_exception_end(ctx, EXCP_RI);
+                gen_reserved_instruction(ctx);
                 break;
             }
             break;
@@ -14983,7 +14983,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
             break;
 #endif
         default:
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -14998,7 +14998,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
         break;
 #endif
     default:
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 
@@ -15696,7 +15696,7 @@ static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist,
     TCGv_i32 t2;
 
     if (ctx->hflags & MIPS_HFLAG_BMASK) {
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         return;
     }
 
@@ -15849,7 +15849,7 @@ static void gen_pool16c_insn(DisasContext *ctx)
         }
         break;
     default:
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -15994,7 +15994,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
     TCGv t0, t1;
 
     if (ctx->hflags & MIPS_HFLAG_BMASK || rd == 31) {
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         return;
     }
 
@@ -16006,7 +16006,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
     switch (opc) {
     case LWP:
         if (rd == base) {
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             return;
         }
         tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL);
@@ -16027,7 +16027,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
 #ifdef TARGET_MIPS64
     case LDP:
         if (rd == base) {
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             return;
         }
         tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEQ);
@@ -16372,7 +16372,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
             } else {
                 check_insn(ctx, ISA_MIPS32);
                 if (ctx->hflags & MIPS_HFLAG_SBRI) {
-                    generate_exception_end(ctx, EXCP_RI);
+                    gen_reserved_instruction(ctx);
                 } else {
                     generate_exception_end(ctx, EXCP_DBp);
                 }
@@ -16422,7 +16422,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
     default:
     pool32axf_invalid:
         MIPS_INVAL("pool32axf");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -16691,7 +16691,7 @@ static void gen_pool32fxf(DisasContext *ctx, int rt, int rs)
         break;
     default:
         MIPS_INVAL("pool32fxf");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -16895,12 +16895,12 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
             break;
         case SIGRIE:
             check_insn(ctx, ISA_MIPS32R6);
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         default:
         pool32a_invalid:
                 MIPS_INVAL("pool32a");
-                generate_exception_end(ctx, EXCP_RI);
+                gen_reserved_instruction(ctx);
                 break;
         }
         break;
@@ -16942,7 +16942,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
             break;
         default:
             MIPS_INVAL("pool32b");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -17422,7 +17422,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
             default:
             pool32f_invalid:
                 MIPS_INVAL("pool32f");
-                generate_exception_end(ctx, EXCP_RI);
+                gen_reserved_instruction(ctx);
                 break;
             }
         } else {
@@ -17584,7 +17584,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
             /* Fall through */
         default:
             MIPS_INVAL("pool32i");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -17667,7 +17667,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
         case LD_EVA:
             if (!ctx->eva) {
                 MIPS_INVAL("pool32c ld-eva");
-                generate_exception_end(ctx, EXCP_RI);
+                gen_reserved_instruction(ctx);
                 break;
             }
             check_cp0_enabled(ctx);
@@ -17706,7 +17706,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
         case ST_EVA:
             if (!ctx->eva) {
                 MIPS_INVAL("pool32c st-eva");
-                generate_exception_end(ctx, EXCP_RI);
+                gen_reserved_instruction(ctx);
                 break;
             }
             check_cp0_enabled(ctx);
@@ -17758,7 +17758,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
             break;
         default:
             MIPS_INVAL("pool32c");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -18050,7 +18050,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
         gen_st(ctx, mips32_op, rt, rs, imm);
         break;
     default:
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -18081,7 +18081,7 @@ static int decode_micromips_opc(CPUMIPSState *env, DisasContext *ctx)
         case 7:
         /* LB32, LH32, LWC132, LDC132, LW32 */
             if (ctx->hflags & MIPS_HFLAG_BDS16) {
-                generate_exception_end(ctx, EXCP_RI);
+                gen_reserved_instruction(ctx);
                 return 2;
             }
             break;
@@ -18092,7 +18092,7 @@ static int decode_micromips_opc(CPUMIPSState *env, DisasContext *ctx)
         case 3:
         /* MOVE16, ANDI16, POOL16D, POOL16E, BEQZ16, BNEZ16, B16, LI16 */
             if (ctx->hflags & MIPS_HFLAG_BDS32) {
-                generate_exception_end(ctx, EXCP_RI);
+                gen_reserved_instruction(ctx);
                 return 2;
             }
             break;
@@ -18165,7 +18165,7 @@ static int decode_micromips_opc(CPUMIPSState *env, DisasContext *ctx)
     case POOL16F:
         check_insn_opc_removed(ctx, ISA_MIPS32R6);
         if (ctx->opcode & 1) {
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
         } else {
             /* MOVEP */
             int enc_dest = uMIPS_RD(ctx->opcode);
@@ -18303,7 +18303,7 @@ static int decode_micromips_opc(CPUMIPSState *env, DisasContext *ctx)
     case RES_29:
     case RES_31:
     case RES_39:
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     default:
         decode_micromips32_opc(env, ctx);
@@ -19561,7 +19561,7 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
                     gen_helper_dvpe(t0, cpu_env);
                     gen_store_gpr(t0, rt);
                 } else {
-                    generate_exception_end(ctx, EXCP_RI);
+                    gen_reserved_instruction(ctx);
                 }
                 break;
             case 1:
@@ -19576,7 +19576,7 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
                     gen_helper_evpe(t0, cpu_env);
                     gen_store_gpr(t0, rt);
                 } else {
-                    generate_exception_end(ctx, EXCP_RI);
+                    gen_reserved_instruction(ctx);
                 }
                 break;
             }
@@ -19626,7 +19626,7 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
         break;
 #endif
     default:
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -19667,7 +19667,7 @@ static void gen_pool32axf_1_5_nanomips_insn(DisasContext *ctx, uint32_t opc,
         gen_helper_maq_sa_w_phl(t0, v1_t, v0_t, cpu_env);
         break;
     default:
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 
@@ -19718,7 +19718,7 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
             gen_helper_shilo(t0, v0_t, cpu_env);
             break;
         default:
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -19792,7 +19792,7 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
         }
         break;
     default:
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 
@@ -19830,7 +19830,7 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
             gen_helper_dpsq_s_w_ph(t0, v1, v0, cpu_env);
             break;
         default:
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -19853,7 +19853,7 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
             gen_helper_dpsq_sa_l_w(t0, v0, v1, cpu_env);
             break;
         default:
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -19880,7 +19880,7 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
             gen_helper_mulsa_w_ph(t0, v0, v1, cpu_env);
             break;
         default:
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -19907,12 +19907,12 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
             gen_helper_mulsaq_s_w_ph(t0, v1, v0, cpu_env);
             break;
         default:
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
     default:
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 
@@ -20056,7 +20056,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
             gen_store_gpr(t0, ret);
             break;
         default:
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -20149,7 +20149,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
         }
         break;
     default:
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 
@@ -20292,7 +20292,7 @@ static void gen_pool32axf_4_nanomips_insn(DisasContext *ctx, uint32_t opc,
         gen_bshfl(ctx, OPC_WSBH, ret, rs);
         break;
     default:
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 
@@ -20347,7 +20347,7 @@ static void gen_pool32axf_7_nanomips_insn(DisasContext *ctx, uint32_t opc,
         }
         break;
     default:
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
     tcg_temp_free(t0);
@@ -20444,7 +20444,7 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
             break;
 #endif
         default:
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -20455,7 +20455,7 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
         }
         break;
     default:
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -20488,7 +20488,7 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
     case NM_BBNEZC:
         check_nms(ctx);
         if (imm >= 32 && !(ctx->hflags & MIPS_HFLAG_64)) {
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             goto out;
         } else if (rt == 0 && opc == NM_BBEQZC) {
             /* Unconditional branch */
@@ -20538,7 +20538,7 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
         break;
     default:
         MIPS_INVAL("Immediate Value Compact branch");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         goto out;
     }
 
@@ -20651,7 +20651,7 @@ static void gen_compute_compact_branch_nm(DisasContext *ctx, uint32_t opc,
         break;
     default:
         MIPS_INVAL("Compact branch/jump");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         goto out;
     }
 
@@ -20663,7 +20663,7 @@ static void gen_compute_compact_branch_nm(DisasContext *ctx, uint32_t opc,
             break;
         default:
             MIPS_INVAL("Compact branch/jump");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             goto out;
         }
     } else {
@@ -20724,7 +20724,7 @@ static void gen_compute_compact_branch_nm(DisasContext *ctx, uint32_t opc,
             break;
         default:
             MIPS_INVAL("Compact conditional branch/jump");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             goto out;
         }
 
@@ -20768,7 +20768,7 @@ static void gen_compute_branch_cp1_nm(DisasContext *ctx, uint32_t op,
         break;
     default:
         MIPS_INVAL("cp1 cond branch");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         goto out;
     }
 
@@ -20898,7 +20898,7 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
         }
         break;
     default:
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 
@@ -20915,7 +20915,7 @@ static void gen_pool32f_nanomips_insn(DisasContext *ctx)
     rd = extract32(ctx->opcode, 11, 5);
 
     if (!(ctx->CP0_Config1 & (1 << CP0C1_FP))) {
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         return;
     }
     check_cp1_enabled(ctx);
@@ -20989,7 +20989,7 @@ static void gen_pool32f_nanomips_insn(DisasContext *ctx)
             gen_farith(ctx, OPC_MSUBF_D, rt, rs, rd, 0);
             break;
         default:
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -21178,7 +21178,7 @@ static void gen_pool32f_nanomips_insn(DisasContext *ctx)
                     gen_farith(ctx, OPC_CVT_S_L, -1, rs, rt, 0);
                     break;
                 default:
-                    generate_exception_end(ctx, EXCP_RI);
+                    gen_reserved_instruction(ctx);
                     break;
                 }
                 break;
@@ -21195,12 +21195,12 @@ static void gen_pool32f_nanomips_insn(DisasContext *ctx)
             gen_r6_cmp_d(ctx, extract32(ctx->opcode, 6, 5), rt, rs, rd);
             break;
         default:
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
     default:
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -21726,7 +21726,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
             gen_store_gpr(v1_t, rt);
             break;
         default:
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -21748,7 +21748,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
         }
         break;
     default:
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -21776,13 +21776,13 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
             switch (extract32(ctx->opcode, 19, 2)) {
             case NM_SIGRIE:
             default:
-                generate_exception_end(ctx, EXCP_RI);
+                gen_reserved_instruction(ctx);
                 break;
             case NM_P_SYSCALL:
                 if ((extract32(ctx->opcode, 18, 1)) == NM_SYSCALL) {
                     generate_exception_end(ctx, EXCP_SYSCALL);
                 } else {
-                    generate_exception_end(ctx, EXCP_RI);
+                    gen_reserved_instruction(ctx);
                 }
                 break;
             case NM_BREAK:
@@ -21793,7 +21793,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                     gen_helper_do_semihosting(cpu_env);
                 } else {
                     if (ctx->hflags & MIPS_HFLAG_SBRI) {
-                        generate_exception_end(ctx, EXCP_RI);
+                        gen_reserved_instruction(ctx);
                     } else {
                         generate_exception_end(ctx, EXCP_DBp);
                     }
@@ -21851,12 +21851,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                 gen_pool32axf_nanomips_insn(env, ctx);
                 break;
             default:
-                generate_exception_end(ctx, EXCP_RI);
+                gen_reserved_instruction(ctx);
                 break;
             }
             break;
         default:
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -21875,7 +21875,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
             gen_st(ctx, OPC_SW, rt, 28, extract32(ctx->opcode, 2, 19) << 2);
             break;
         default:
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -21946,7 +21946,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                 }
                 break;
             default:
-                generate_exception_end(ctx, EXCP_RI);
+                gen_reserved_instruction(ctx);
                 break;
             }
             return 6;
@@ -21981,12 +21981,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                     }
                     break;
                 default:
-                    generate_exception_end(ctx, EXCP_RI);
+                    gen_reserved_instruction(ctx);
                     break;
                 }
                 break;
             case NM_P_SR_F:
-                generate_exception_end(ctx, EXCP_RI);
+                gen_reserved_instruction(ctx);
                 break;
             }
             break;
@@ -22074,7 +22074,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                            extract32(ctx->opcode, 6, 5));
                 break;
             default:
-                generate_exception_end(ctx, EXCP_RI);
+                gen_reserved_instruction(ctx);
                 break;
             }
             break;
@@ -22087,12 +22087,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                            extract32(ctx->opcode, 6, 5));
                 break;
             default:
-                generate_exception_end(ctx, EXCP_RI);
+                gen_reserved_instruction(ctx);
                 break;
             }
             break;
         default:
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -22160,7 +22160,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                     gen_st(ctx, OPC_SH, rt, 28, u);
                     break;
                 default:
-                    generate_exception_end(ctx, EXCP_RI);
+                    gen_reserved_instruction(ctx);
                     break;
                 }
                 break;
@@ -22182,7 +22182,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                 }
                 break;
             default:
-                generate_exception_end(ctx, EXCP_RI);
+                gen_reserved_instruction(ctx);
                 break;
             }
         }
@@ -22242,7 +22242,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                 gen_cop1_ldst(ctx, OPC_SDC1, rt, rs, u);
                 break;
             default:
-                generate_exception_end(ctx, EXCP_RI);
+                gen_reserved_instruction(ctx);
                 break;
             }
         }
@@ -22305,7 +22305,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                     }
                     break;
                 default:
-                    generate_exception_end(ctx, EXCP_RI);
+                    gen_reserved_instruction(ctx);
                     break;
                 }
                 break;
@@ -22445,7 +22445,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                         gen_llwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
                         break;
                     default:
-                        generate_exception_end(ctx, EXCP_RI);
+                        gen_reserved_instruction(ctx);
                         break;
                     }
                     break;
@@ -22465,7 +22465,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                                  true);
                         break;
                     default:
-                        generate_exception_end(ctx, EXCP_RI);
+                        gen_reserved_instruction(ctx);
                         break;
                     }
                     break;
@@ -22516,7 +22516,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                 }
                 break;
             default:
-                generate_exception_end(ctx, EXCP_RI);
+                gen_reserved_instruction(ctx);
                 break;
             }
         }
@@ -22560,7 +22560,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
             gen_compute_nanomips_pbalrsc_branch(ctx, rs, rt);
             break;
         default:
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -22595,7 +22595,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                     }
                     break;
                 default:
-                    generate_exception_end(ctx, EXCP_RI);
+                    gen_reserved_instruction(ctx);
                     break;
                 }
                 break;
@@ -22644,7 +22644,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                 }
                 break;
             default:
-                generate_exception_end(ctx, EXCP_RI);
+                gen_reserved_instruction(ctx);
                 break;
             }
         }
@@ -22660,7 +22660,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
         }
         break;
     default:
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
     return 4;
@@ -22699,7 +22699,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
                 if (extract32(ctx->opcode, 2, 1) == 0) {
                     generate_exception_end(ctx, EXCP_SYSCALL);
                 } else {
-                    generate_exception_end(ctx, EXCP_RI);
+                    gen_reserved_instruction(ctx);
                 }
                 break;
             case NM_BREAK16:
@@ -22710,14 +22710,14 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
                     gen_helper_do_semihosting(cpu_env);
                 } else {
                     if (ctx->hflags & MIPS_HFLAG_SBRI) {
-                        generate_exception_end(ctx, EXCP_RI);
+                        gen_reserved_instruction(ctx);
                     } else {
                         generate_exception_end(ctx, EXCP_DBp);
                     }
                 }
                 break;
             default:
-                generate_exception_end(ctx, EXCP_RI);
+                gen_reserved_instruction(ctx);
                 break;
             }
         }
@@ -22756,7 +22756,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
             gen_arith_imm(ctx, OPC_ADDIU, rt, 29, imm);
             break;
         default:
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -22805,7 +22805,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
             gen_r6_muldiv(ctx, R6_OPC_MUL, rt, rs, rt);
             break;
         default:
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -22841,7 +22841,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
             gen_ld(ctx, OPC_LBU, rt, rs, offset);
             break;
         default:
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -22860,7 +22860,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
             gen_ld(ctx, OPC_LHU, rt, rs, offset);
             break;
         default:
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -23639,7 +23639,7 @@ static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc,
                 break;
             default:            /* Invalid */
                 MIPS_INVAL("MASK SHLL.QB");
-                generate_exception_end(ctx, EXCP_RI);
+                gen_reserved_instruction(ctx);
                 break;
             }
             break;
@@ -23754,7 +23754,7 @@ static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc,
             break;
         default:            /* Invalid */
             MIPS_INVAL("MASK SHLL.OB");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -24445,7 +24445,7 @@ static void gen_mipsdsp_append(CPUMIPSState *env, DisasContext *ctx,
             break;
         default:            /* Invalid */
             MIPS_INVAL("MASK APPEND");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -24479,7 +24479,7 @@ static void gen_mipsdsp_append(CPUMIPSState *env, DisasContext *ctx,
             break;
         default:            /* Invalid */
             MIPS_INVAL("MASK DAPPEND");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -24748,7 +24748,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
             break;
         default:
             MIPS_INVAL("special_r6 muldiv");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -24765,7 +24765,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
              */
             gen_cl(ctx, op1, rd, rs);
         } else {
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
         }
         break;
     case R6_OPC_SDBBP:
@@ -24773,7 +24773,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
             gen_helper_do_semihosting(cpu_env);
         } else {
             if (ctx->hflags & MIPS_HFLAG_SBRI) {
-                generate_exception_end(ctx, EXCP_RI);
+                gen_reserved_instruction(ctx);
             } else {
                 generate_exception_end(ctx, EXCP_DBp);
             }
@@ -24794,7 +24794,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
             check_mips_64(ctx);
             gen_cl(ctx, op1, rd, rs);
         } else {
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
         }
         break;
     case OPC_DMULT:
@@ -24817,14 +24817,14 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
             break;
         default:
             MIPS_INVAL("special_r6 muldiv");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
 #endif
     default:            /* Invalid */
         MIPS_INVAL("special_r6");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -24871,7 +24871,7 @@ static void decode_opc_special_tx79(CPUMIPSState *env, DisasContext *ctx)
         break;
     default:            /* Invalid */
         MIPS_INVAL("special_tx79");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -24942,16 +24942,16 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
     case OPC_SPIM:
 #ifdef MIPS_STRICT_STANDARD
         MIPS_INVAL("SPIM");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
 #else
         /* Implemented as RI exception for now. */
         MIPS_INVAL("spim (unofficial)");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
 #endif
         break;
     default:            /* Invalid */
         MIPS_INVAL("special_legacy");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -24973,7 +24973,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
             rs == 0 && rt == 0) { /* PAUSE */
             if ((ctx->insn_flags & ISA_MIPS32R6) &&
                 (ctx->hflags & MIPS_HFLAG_BMASK)) {
-                generate_exception_end(ctx, EXCP_RI);
+                gen_reserved_instruction(ctx);
                 break;
             }
         }
@@ -24993,7 +24993,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
             gen_shift_imm(ctx, op1, rd, rt, sa);
             break;
         default:
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -25019,7 +25019,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
             gen_shift(ctx, op1, rd, rs, rt);
             break;
         default:
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -25053,7 +25053,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
             /* Pmon entry point, also R4010 selsl */
 #ifdef MIPS_STRICT_STANDARD
             MIPS_INVAL("PMON / selsl");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
 #else
             gen_helper_0e0i(pmon, sa);
 #endif
@@ -25094,7 +25094,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
             gen_shift_imm(ctx, op1, rd, rt, sa);
             break;
         default:
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -25112,7 +25112,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
             gen_shift_imm(ctx, op1, rd, rt, sa);
             break;
         default:
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -25144,7 +25144,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
             gen_shift(ctx, op1, rd, rs, rt);
             break;
         default:
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -25209,7 +25209,7 @@ static void gen_mmi_pcpyh(DisasContext *ctx)
     rd = extract32(opcode, 11, 5);
 
     if (unlikely(pd != 0)) {
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
     } else if (rd == 0) {
         /* nop */
     } else if (rt == 0) {
@@ -26416,16 +26416,16 @@ static void decode_opc_mxu__pool00(CPUMIPSState *env, DisasContext *ctx)
     case OPC_MXU_Q8SLT:
         /* TODO: Implement emulation of Q8SLT instruction. */
         MIPS_INVAL("OPC_MXU_Q8SLT");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_Q8SLTU:
         /* TODO: Implement emulation of Q8SLTU instruction. */
         MIPS_INVAL("OPC_MXU_Q8SLTU");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     default:
         MIPS_INVAL("decode_opc_mxu");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -26455,41 +26455,41 @@ static void decode_opc_mxu__pool01(CPUMIPSState *env, DisasContext *ctx)
     case OPC_MXU_S32SLT:
         /* TODO: Implement emulation of S32SLT instruction. */
         MIPS_INVAL("OPC_MXU_S32SLT");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_D16SLT:
         /* TODO: Implement emulation of D16SLT instruction. */
         MIPS_INVAL("OPC_MXU_D16SLT");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_D16AVG:
         /* TODO: Implement emulation of D16AVG instruction. */
         MIPS_INVAL("OPC_MXU_D16AVG");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_D16AVGR:
         /* TODO: Implement emulation of D16AVGR instruction. */
         MIPS_INVAL("OPC_MXU_D16AVGR");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_Q8AVG:
         /* TODO: Implement emulation of Q8AVG instruction. */
         MIPS_INVAL("OPC_MXU_Q8AVG");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_Q8AVGR:
         /* TODO: Implement emulation of Q8AVGR instruction. */
         MIPS_INVAL("OPC_MXU_Q8AVGR");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_Q8ADD:
         /* TODO: Implement emulation of Q8ADD instruction. */
         MIPS_INVAL("OPC_MXU_Q8ADD");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     default:
         MIPS_INVAL("decode_opc_mxu");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -26512,26 +26512,26 @@ static void decode_opc_mxu__pool02(CPUMIPSState *env, DisasContext *ctx)
     case OPC_MXU_S32CPS:
         /* TODO: Implement emulation of S32CPS instruction. */
         MIPS_INVAL("OPC_MXU_S32CPS");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_D16CPS:
         /* TODO: Implement emulation of D16CPS instruction. */
         MIPS_INVAL("OPC_MXU_D16CPS");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_Q8ABD:
         /* TODO: Implement emulation of Q8ABD instruction. */
         MIPS_INVAL("OPC_MXU_Q8ABD");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_Q16SAT:
         /* TODO: Implement emulation of Q16SAT instruction. */
         MIPS_INVAL("OPC_MXU_Q16SAT");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     default:
         MIPS_INVAL("decode_opc_mxu");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -26561,16 +26561,16 @@ static void decode_opc_mxu__pool03(CPUMIPSState *env, DisasContext *ctx)
     case OPC_MXU_D16MULF:
         /* TODO: Implement emulation of D16MULF instruction. */
         MIPS_INVAL("OPC_MXU_D16MULF");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_D16MULE:
         /* TODO: Implement emulation of D16MULE instruction. */
         MIPS_INVAL("OPC_MXU_D16MULE");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     default:
         MIPS_INVAL("decode_opc_mxu");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -26596,7 +26596,7 @@ static void decode_opc_mxu__pool04(CPUMIPSState *env, DisasContext *ctx)
         break;
     default:
         MIPS_INVAL("decode_opc_mxu");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -26619,16 +26619,16 @@ static void decode_opc_mxu__pool05(CPUMIPSState *env, DisasContext *ctx)
     case OPC_MXU_S32STD:
         /* TODO: Implement emulation of S32STD instruction. */
         MIPS_INVAL("OPC_MXU_S32STD");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_S32STDR:
         /* TODO: Implement emulation of S32STDR instruction. */
         MIPS_INVAL("OPC_MXU_S32STDR");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     default:
         MIPS_INVAL("decode_opc_mxu");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -26651,16 +26651,16 @@ static void decode_opc_mxu__pool06(CPUMIPSState *env, DisasContext *ctx)
     case OPC_MXU_S32LDDV:
         /* TODO: Implement emulation of S32LDDV instruction. */
         MIPS_INVAL("OPC_MXU_S32LDDV");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_S32LDDVR:
         /* TODO: Implement emulation of S32LDDVR instruction. */
         MIPS_INVAL("OPC_MXU_S32LDDVR");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     default:
         MIPS_INVAL("decode_opc_mxu");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -26683,16 +26683,16 @@ static void decode_opc_mxu__pool07(CPUMIPSState *env, DisasContext *ctx)
     case OPC_MXU_S32STDV:
         /* TODO: Implement emulation of S32TDV instruction. */
         MIPS_INVAL("OPC_MXU_S32TDV");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_S32STDVR:
         /* TODO: Implement emulation of S32TDVR instruction. */
         MIPS_INVAL("OPC_MXU_S32TDVR");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     default:
         MIPS_INVAL("decode_opc_mxu");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -26715,16 +26715,16 @@ static void decode_opc_mxu__pool08(CPUMIPSState *env, DisasContext *ctx)
     case OPC_MXU_S32LDI:
         /* TODO: Implement emulation of S32LDI instruction. */
         MIPS_INVAL("OPC_MXU_S32LDI");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_S32LDIR:
         /* TODO: Implement emulation of S32LDIR instruction. */
         MIPS_INVAL("OPC_MXU_S32LDIR");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     default:
         MIPS_INVAL("decode_opc_mxu");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -26747,16 +26747,16 @@ static void decode_opc_mxu__pool09(CPUMIPSState *env, DisasContext *ctx)
     case OPC_MXU_S32SDI:
         /* TODO: Implement emulation of S32SDI instruction. */
         MIPS_INVAL("OPC_MXU_S32SDI");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_S32SDIR:
         /* TODO: Implement emulation of S32SDIR instruction. */
         MIPS_INVAL("OPC_MXU_S32SDIR");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     default:
         MIPS_INVAL("decode_opc_mxu");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -26779,16 +26779,16 @@ static void decode_opc_mxu__pool10(CPUMIPSState *env, DisasContext *ctx)
     case OPC_MXU_S32LDIV:
         /* TODO: Implement emulation of S32LDIV instruction. */
         MIPS_INVAL("OPC_MXU_S32LDIV");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_S32LDIVR:
         /* TODO: Implement emulation of S32LDIVR instruction. */
         MIPS_INVAL("OPC_MXU_S32LDIVR");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     default:
         MIPS_INVAL("decode_opc_mxu");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -26811,16 +26811,16 @@ static void decode_opc_mxu__pool11(CPUMIPSState *env, DisasContext *ctx)
     case OPC_MXU_S32SDIV:
         /* TODO: Implement emulation of S32SDIV instruction. */
         MIPS_INVAL("OPC_MXU_S32SDIV");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_S32SDIVR:
         /* TODO: Implement emulation of S32SDIVR instruction. */
         MIPS_INVAL("OPC_MXU_S32SDIVR");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     default:
         MIPS_INVAL("decode_opc_mxu");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -26843,21 +26843,21 @@ static void decode_opc_mxu__pool12(CPUMIPSState *env, DisasContext *ctx)
     case OPC_MXU_D32ACC:
         /* TODO: Implement emulation of D32ACC instruction. */
         MIPS_INVAL("OPC_MXU_D32ACC");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_D32ACCM:
         /* TODO: Implement emulation of D32ACCM instruction. */
         MIPS_INVAL("OPC_MXU_D32ACCM");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_D32ASUM:
         /* TODO: Implement emulation of D32ASUM instruction. */
         MIPS_INVAL("OPC_MXU_D32ASUM");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     default:
         MIPS_INVAL("decode_opc_mxu");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -26880,21 +26880,21 @@ static void decode_opc_mxu__pool13(CPUMIPSState *env, DisasContext *ctx)
     case OPC_MXU_Q16ACC:
         /* TODO: Implement emulation of Q16ACC instruction. */
         MIPS_INVAL("OPC_MXU_Q16ACC");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_Q16ACCM:
         /* TODO: Implement emulation of Q16ACCM instruction. */
         MIPS_INVAL("OPC_MXU_Q16ACCM");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_Q16ASUM:
         /* TODO: Implement emulation of Q16ASUM instruction. */
         MIPS_INVAL("OPC_MXU_Q16ASUM");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     default:
         MIPS_INVAL("decode_opc_mxu");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -26924,21 +26924,21 @@ static void decode_opc_mxu__pool14(CPUMIPSState *env, DisasContext *ctx)
     case OPC_MXU_Q8ADDE:
         /* TODO: Implement emulation of Q8ADDE instruction. */
         MIPS_INVAL("OPC_MXU_Q8ADDE");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_D8SUM:
         /* TODO: Implement emulation of D8SUM instruction. */
         MIPS_INVAL("OPC_MXU_D8SUM");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_D8SUMC:
         /* TODO: Implement emulation of D8SUMC instruction. */
         MIPS_INVAL("OPC_MXU_D8SUMC");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     default:
         MIPS_INVAL("decode_opc_mxu");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -26968,26 +26968,26 @@ static void decode_opc_mxu__pool15(CPUMIPSState *env, DisasContext *ctx)
     case OPC_MXU_S32MUL:
         /* TODO: Implement emulation of S32MUL instruction. */
         MIPS_INVAL("OPC_MXU_S32MUL");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_S32MULU:
         /* TODO: Implement emulation of S32MULU instruction. */
         MIPS_INVAL("OPC_MXU_S32MULU");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_S32EXTR:
         /* TODO: Implement emulation of S32EXTR instruction. */
         MIPS_INVAL("OPC_MXU_S32EXTR");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_S32EXTRV:
         /* TODO: Implement emulation of S32EXTRV instruction. */
         MIPS_INVAL("OPC_MXU_S32EXTRV");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     default:
         MIPS_INVAL("decode_opc_mxu");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -27035,12 +27035,12 @@ static void decode_opc_mxu__pool16(CPUMIPSState *env, DisasContext *ctx)
     case OPC_MXU_D32SARW:
         /* TODO: Implement emulation of D32SARW instruction. */
         MIPS_INVAL("OPC_MXU_D32SARW");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_S32ALN:
         /* TODO: Implement emulation of S32ALN instruction. */
         MIPS_INVAL("OPC_MXU_S32ALN");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_S32ALNI:
         gen_mxu_S32ALNI(ctx);
@@ -27048,7 +27048,7 @@ static void decode_opc_mxu__pool16(CPUMIPSState *env, DisasContext *ctx)
     case OPC_MXU_S32LUI:
         /* TODO: Implement emulation of S32LUI instruction. */
         MIPS_INVAL("OPC_MXU_S32LUI");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_S32NOR:
         gen_mxu_S32NOR(ctx);
@@ -27064,7 +27064,7 @@ static void decode_opc_mxu__pool16(CPUMIPSState *env, DisasContext *ctx)
         break;
     default:
         MIPS_INVAL("decode_opc_mxu");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -27087,31 +27087,31 @@ static void decode_opc_mxu__pool17(CPUMIPSState *env, DisasContext *ctx)
     case OPC_MXU_LXW:
         /* TODO: Implement emulation of LXW instruction. */
         MIPS_INVAL("OPC_MXU_LXW");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_LXH:
         /* TODO: Implement emulation of LXH instruction. */
         MIPS_INVAL("OPC_MXU_LXH");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_LXHU:
         /* TODO: Implement emulation of LXHU instruction. */
         MIPS_INVAL("OPC_MXU_LXHU");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_LXB:
         /* TODO: Implement emulation of LXB instruction. */
         MIPS_INVAL("OPC_MXU_LXB");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_LXBU:
         /* TODO: Implement emulation of LXBU instruction. */
         MIPS_INVAL("OPC_MXU_LXBU");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     default:
         MIPS_INVAL("decode_opc_mxu");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -27133,36 +27133,36 @@ static void decode_opc_mxu__pool18(CPUMIPSState *env, DisasContext *ctx)
     case OPC_MXU_D32SLLV:
         /* TODO: Implement emulation of D32SLLV instruction. */
         MIPS_INVAL("OPC_MXU_D32SLLV");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_D32SLRV:
         /* TODO: Implement emulation of D32SLRV instruction. */
         MIPS_INVAL("OPC_MXU_D32SLRV");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_D32SARV:
         /* TODO: Implement emulation of D32SARV instruction. */
         MIPS_INVAL("OPC_MXU_D32SARV");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_Q16SLLV:
         /* TODO: Implement emulation of Q16SLLV instruction. */
         MIPS_INVAL("OPC_MXU_Q16SLLV");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_Q16SLRV:
         /* TODO: Implement emulation of Q16SLRV instruction. */
         MIPS_INVAL("OPC_MXU_Q16SLRV");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_Q16SARV:
         /* TODO: Implement emulation of Q16SARV instruction. */
         MIPS_INVAL("OPC_MXU_Q16SARV");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     default:
         MIPS_INVAL("decode_opc_mxu");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -27188,7 +27188,7 @@ static void decode_opc_mxu__pool19(CPUMIPSState *env, DisasContext *ctx)
         break;
     default:
         MIPS_INVAL("decode_opc_mxu");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -27211,36 +27211,36 @@ static void decode_opc_mxu__pool20(CPUMIPSState *env, DisasContext *ctx)
     case OPC_MXU_Q8MOVZ:
         /* TODO: Implement emulation of Q8MOVZ instruction. */
         MIPS_INVAL("OPC_MXU_Q8MOVZ");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_Q8MOVN:
         /* TODO: Implement emulation of Q8MOVN instruction. */
         MIPS_INVAL("OPC_MXU_Q8MOVN");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_D16MOVZ:
         /* TODO: Implement emulation of D16MOVZ instruction. */
         MIPS_INVAL("OPC_MXU_D16MOVZ");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_D16MOVN:
         /* TODO: Implement emulation of D16MOVN instruction. */
         MIPS_INVAL("OPC_MXU_D16MOVN");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_S32MOVZ:
         /* TODO: Implement emulation of S32MOVZ instruction. */
         MIPS_INVAL("OPC_MXU_S32MOVZ");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_S32MOVN:
         /* TODO: Implement emulation of S32MOVN instruction. */
         MIPS_INVAL("OPC_MXU_S32MOVN");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     default:
         MIPS_INVAL("decode_opc_mxu");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -27263,16 +27263,16 @@ static void decode_opc_mxu__pool21(CPUMIPSState *env, DisasContext *ctx)
     case OPC_MXU_Q8MAC:
         /* TODO: Implement emulation of Q8MAC instruction. */
         MIPS_INVAL("OPC_MXU_Q8MAC");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     case OPC_MXU_Q8MACSU:
         /* TODO: Implement emulation of Q8MACSU instruction. */
         MIPS_INVAL("OPC_MXU_Q8MACSU");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     default:
         MIPS_INVAL("decode_opc_mxu");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -27331,12 +27331,12 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
         case OPC_MXU_S32MADD:
             /* TODO: Implement emulation of S32MADD instruction. */
             MIPS_INVAL("OPC_MXU_S32MADD");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         case OPC_MXU_S32MADDU:
             /* TODO: Implement emulation of S32MADDU instruction. */
             MIPS_INVAL("OPC_MXU_S32MADDU");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         case OPC_MXU__POOL00:
             decode_opc_mxu__pool00(env, ctx);
@@ -27344,12 +27344,12 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
         case OPC_MXU_S32MSUB:
             /* TODO: Implement emulation of S32MSUB instruction. */
             MIPS_INVAL("OPC_MXU_S32MSUB");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         case OPC_MXU_S32MSUBU:
             /* TODO: Implement emulation of S32MSUBU instruction. */
             MIPS_INVAL("OPC_MXU_S32MSUBU");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         case OPC_MXU__POOL01:
             decode_opc_mxu__pool01(env, ctx);
@@ -27369,27 +27369,27 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
         case OPC_MXU_D16MACF:
             /* TODO: Implement emulation of D16MACF instruction. */
             MIPS_INVAL("OPC_MXU_D16MACF");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         case OPC_MXU_D16MADL:
             /* TODO: Implement emulation of D16MADL instruction. */
             MIPS_INVAL("OPC_MXU_D16MADL");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         case OPC_MXU_S16MAD:
             /* TODO: Implement emulation of S16MAD instruction. */
             MIPS_INVAL("OPC_MXU_S16MAD");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         case OPC_MXU_Q16ADD:
             /* TODO: Implement emulation of Q16ADD instruction. */
             MIPS_INVAL("OPC_MXU_Q16ADD");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         case OPC_MXU_D16MACE:
             /* TODO: Implement emulation of D16MACE instruction. */
             MIPS_INVAL("OPC_MXU_D16MACE");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         case OPC_MXU__POOL04:
             decode_opc_mxu__pool04(env, ctx);
@@ -27418,7 +27418,7 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
         case OPC_MXU_D32ADD:
             /* TODO: Implement emulation of D32ADD instruction. */
             MIPS_INVAL("OPC_MXU_D32ADD");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         case OPC_MXU__POOL12:
             decode_opc_mxu__pool12(env, ctx);
@@ -27432,7 +27432,7 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
         case OPC_MXU_Q8ACCE:
             /* TODO: Implement emulation of Q8ACCE instruction. */
             MIPS_INVAL("OPC_MXU_Q8ACCE");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         case OPC_MXU_S8LDD:
             gen_mxu_s8ldd(ctx);
@@ -27440,17 +27440,17 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
         case OPC_MXU_S8STD:
             /* TODO: Implement emulation of S8STD instruction. */
             MIPS_INVAL("OPC_MXU_S8STD");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         case OPC_MXU_S8LDI:
             /* TODO: Implement emulation of S8LDI instruction. */
             MIPS_INVAL("OPC_MXU_S8LDI");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         case OPC_MXU_S8SDI:
             /* TODO: Implement emulation of S8SDI instruction. */
             MIPS_INVAL("OPC_MXU_S8SDI");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         case OPC_MXU__POOL15:
             decode_opc_mxu__pool15(env, ctx);
@@ -27464,52 +27464,52 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
         case OPC_MXU_S16LDD:
             /* TODO: Implement emulation of S16LDD instruction. */
             MIPS_INVAL("OPC_MXU_S16LDD");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         case OPC_MXU_S16STD:
             /* TODO: Implement emulation of S16STD instruction. */
             MIPS_INVAL("OPC_MXU_S16STD");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         case OPC_MXU_S16LDI:
             /* TODO: Implement emulation of S16LDI instruction. */
             MIPS_INVAL("OPC_MXU_S16LDI");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         case OPC_MXU_S16SDI:
             /* TODO: Implement emulation of S16SDI instruction. */
             MIPS_INVAL("OPC_MXU_S16SDI");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         case OPC_MXU_D32SLL:
             /* TODO: Implement emulation of D32SLL instruction. */
             MIPS_INVAL("OPC_MXU_D32SLL");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         case OPC_MXU_D32SLR:
             /* TODO: Implement emulation of D32SLR instruction. */
             MIPS_INVAL("OPC_MXU_D32SLR");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         case OPC_MXU_D32SARL:
             /* TODO: Implement emulation of D32SARL instruction. */
             MIPS_INVAL("OPC_MXU_D32SARL");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         case OPC_MXU_D32SAR:
             /* TODO: Implement emulation of D32SAR instruction. */
             MIPS_INVAL("OPC_MXU_D32SAR");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         case OPC_MXU_Q16SLL:
             /* TODO: Implement emulation of Q16SLL instruction. */
             MIPS_INVAL("OPC_MXU_Q16SLL");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         case OPC_MXU_Q16SLR:
             /* TODO: Implement emulation of Q16SLR instruction. */
             MIPS_INVAL("OPC_MXU_Q16SLR");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         case OPC_MXU__POOL18:
             decode_opc_mxu__pool18(env, ctx);
@@ -27517,7 +27517,7 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
         case OPC_MXU_Q16SAR:
             /* TODO: Implement emulation of Q16SAR instruction. */
             MIPS_INVAL("OPC_MXU_Q16SAR");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         case OPC_MXU__POOL19:
             decode_opc_mxu__pool19(env, ctx);
@@ -27531,26 +27531,26 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
         case OPC_MXU_Q16SCOP:
             /* TODO: Implement emulation of Q16SCOP instruction. */
             MIPS_INVAL("OPC_MXU_Q16SCOP");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         case OPC_MXU_Q8MADL:
             /* TODO: Implement emulation of Q8MADL instruction. */
             MIPS_INVAL("OPC_MXU_Q8MADL");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         case OPC_MXU_S32SFL:
             /* TODO: Implement emulation of S32SFL instruction. */
             MIPS_INVAL("OPC_MXU_S32SFL");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         case OPC_MXU_Q8SAD:
             /* TODO: Implement emulation of Q8SAD instruction. */
             MIPS_INVAL("OPC_MXU_Q8SAD");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         default:
             MIPS_INVAL("decode_opc_mxu");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
         }
 
         gen_set_label(l_exit);
@@ -27629,7 +27629,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
 #endif
     default:            /* Invalid */
         MIPS_INVAL("special2_legacy");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -27651,7 +27651,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
     case R6_OPC_PREF:
         if (rt >= 24) {
             /* hint codes 24-31 are reserved and signal RI */
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
         }
         /* Treat as NOP. */
         break;
@@ -27690,7 +27690,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
 #ifndef CONFIG_USER_ONLY
     case OPC_GINV:
         if (unlikely(ctx->gi <= 1)) {
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
         }
         check_cp0_enabled(ctx);
         switch ((ctx->opcode >> 6) & 3) {
@@ -27701,7 +27701,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
             gen_helper_0e1i(ginvt, cpu_gpr[rs], extract32(ctx->opcode, 8, 2));
             break;
         default:
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -27742,7 +27742,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
 #endif
     default:            /* Invalid */
         MIPS_INVAL("special3_r6");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -27793,13 +27793,13 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
                 break;
             default:
                 MIPS_INVAL("MASK ADDUH.QB");
-                generate_exception_end(ctx, EXCP_RI);
+                gen_reserved_instruction(ctx);
                 break;
             }
         } else if (ctx->insn_flags & INSN_LOONGSON2E) {
             gen_loongson_integer(ctx, op1, rd, rs, rt);
         } else {
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
         }
         break;
     case OPC_LX_DSP:
@@ -27815,7 +27815,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
             break;
         default:            /* Invalid */
             MIPS_INVAL("MASK LX");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -27846,7 +27846,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
             break;
         default:
             MIPS_INVAL("MASK ABSQ_S.PH");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -27883,7 +27883,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
             break;
         default:            /* Invalid */
             MIPS_INVAL("MASK ADDU.QB");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
 
         }
@@ -27923,7 +27923,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
             break;
         default:            /* Invalid */
             MIPS_INVAL("MASK CMPU.EQ.QB");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -27959,7 +27959,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
             break;
         default:            /* Invalid */
             MIPS_INVAL("MASK DPAW.PH");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -27989,7 +27989,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
             }
         default:            /* Invalid */
             MIPS_INVAL("MASK INSV");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -28024,7 +28024,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
             break;
         default:            /* Invalid */
             MIPS_INVAL("MASK EXTR.W");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -28070,7 +28070,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
             break;
         default:            /* Invalid */
             MIPS_INVAL("MASK ABSQ_S.QH");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -28109,7 +28109,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
             break;
         default:            /* Invalid */
             MIPS_INVAL("MASK ADDU.OB");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -28154,7 +28154,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
             break;
         default:            /* Invalid */
             MIPS_INVAL("MASK CMPU_EQ.OB");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -28191,7 +28191,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
             break;
         default:            /* Invalid */
             MIPS_INVAL("MASK EXTR.W");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -28230,7 +28230,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
             break;
         default:            /* Invalid */
             MIPS_INVAL("MASK DPAQ.W.QH");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -28260,7 +28260,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
         }
         default:            /* Invalid */
             MIPS_INVAL("MASK DINSV");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -28270,7 +28270,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
 #endif
     default:            /* Invalid */
         MIPS_INVAL("special3_legacy");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -28308,11 +28308,11 @@ static void decode_mmi0(CPUMIPSState *env, DisasContext *ctx)
     case MMI_OPC_0_PPACB:     /* TODO: MMI_OPC_0_PPACB */
     case MMI_OPC_0_PEXT5:     /* TODO: MMI_OPC_0_PEXT5 */
     case MMI_OPC_0_PPAC5:     /* TODO: MMI_OPC_0_PPAC5 */
-        generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI0 */
+        gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI0 */
         break;
     default:
         MIPS_INVAL("TX79 MMI class MMI0");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -28340,11 +28340,11 @@ static void decode_mmi1(CPUMIPSState *env, DisasContext *ctx)
     case MMI_OPC_1_PSUBUB:    /* TODO: MMI_OPC_1_PSUBUB */
     case MMI_OPC_1_PEXTUB:    /* TODO: MMI_OPC_1_PEXTUB */
     case MMI_OPC_1_QFSRV:     /* TODO: MMI_OPC_1_QFSRV */
-        generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI1 */
+        gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI1 */
         break;
     default:
         MIPS_INVAL("TX79 MMI class MMI1");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -28375,14 +28375,14 @@ static void decode_mmi2(CPUMIPSState *env, DisasContext *ctx)
     case MMI_OPC_2_PDIVBW:    /* TODO: MMI_OPC_2_PDIVBW */
     case MMI_OPC_2_PEXEW:     /* TODO: MMI_OPC_2_PEXEW */
     case MMI_OPC_2_PROT3W:    /* TODO: MMI_OPC_2_PROT3W */
-        generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI2 */
+        gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI2 */
         break;
     case MMI_OPC_2_PCPYLD:
         gen_mmi_pcpyld(ctx);
         break;
     default:
         MIPS_INVAL("TX79 MMI class MMI2");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -28403,7 +28403,7 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
     case MMI_OPC_3_PNOR:       /* TODO: MMI_OPC_3_PNOR */
     case MMI_OPC_3_PEXCH:      /* TODO: MMI_OPC_3_PEXCH */
     case MMI_OPC_3_PEXCW:      /* TODO: MMI_OPC_3_PEXCW */
-        generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI3 */
+        gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI3 */
         break;
     case MMI_OPC_3_PCPYH:
         gen_mmi_pcpyh(ctx);
@@ -28413,7 +28413,7 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
         break;
     default:
         MIPS_INVAL("TX79 MMI class MMI3");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -28467,23 +28467,23 @@ static void decode_mmi(CPUMIPSState *env, DisasContext *ctx)
     case MMI_OPC_PSLLW:         /* TODO: MMI_OPC_PSLLW */
     case MMI_OPC_PSRLW:         /* TODO: MMI_OPC_PSRLW */
     case MMI_OPC_PSRAW:         /* TODO: MMI_OPC_PSRAW */
-        generate_exception_end(ctx, EXCP_RI);    /* TODO: MMI_OPC_CLASS_MMI */
+        gen_reserved_instruction(ctx);    /* TODO: MMI_OPC_CLASS_MMI */
         break;
     default:
         MIPS_INVAL("TX79 MMI class");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
 
 static void gen_mmi_lq(CPUMIPSState *env, DisasContext *ctx)
 {
-    generate_exception_end(ctx, EXCP_RI);    /* TODO: MMI_OPC_LQ */
+    gen_reserved_instruction(ctx);    /* TODO: MMI_OPC_LQ */
 }
 
 static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset)
 {
-    generate_exception_end(ctx, EXCP_RI);    /* TODO: MMI_OPC_SQ */
+    gen_reserved_instruction(ctx);    /* TODO: MMI_OPC_SQ */
 }
 
 /*
@@ -28691,7 +28691,7 @@ static inline int check_msa_access(DisasContext *ctx)
 {
     if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) &&
                  !(ctx->hflags & MIPS_HFLAG_F64))) {
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         return 0;
     }
 
@@ -28700,7 +28700,7 @@ static inline int check_msa_access(DisasContext *ctx)
             generate_exception_end(ctx, EXCP_MSADIS);
             return 0;
         } else {
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             return 0;
         }
     }
@@ -28757,7 +28757,7 @@ static void gen_msa_branch(CPUMIPSState *env, DisasContext *ctx, uint32_t op1)
     check_msa_access(ctx);
 
     if (ctx->hflags & MIPS_HFLAG_BMASK) {
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         return;
     }
     switch (op1) {
@@ -28832,7 +28832,7 @@ static void gen_msa_i8(CPUMIPSState *env, DisasContext *ctx)
         {
             uint8_t df = (ctx->opcode >> 24) & 0x3;
             if (df == DF_DOUBLE) {
-                generate_exception_end(ctx, EXCP_RI);
+                gen_reserved_instruction(ctx);
             } else {
                 TCGv_i32 tdf = tcg_const_i32(df);
                 gen_helper_msa_shf_df(cpu_env, tdf, twd, tws, ti8);
@@ -28842,7 +28842,7 @@ static void gen_msa_i8(CPUMIPSState *env, DisasContext *ctx)
         break;
     default:
         MIPS_INVAL("MSA instruction");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 
@@ -28914,7 +28914,7 @@ static void gen_msa_i5(CPUMIPSState *env, DisasContext *ctx)
         break;
     default:
         MIPS_INVAL("MSA instruction");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 
@@ -28950,7 +28950,7 @@ static void gen_msa_bit(CPUMIPSState *env, DisasContext *ctx)
         m = dfm & 0x7;
         df = DF_BYTE;
     } else {
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         return;
     }
 
@@ -28998,7 +28998,7 @@ static void gen_msa_bit(CPUMIPSState *env, DisasContext *ctx)
         break;
     default:
         MIPS_INVAL("MSA instruction");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 
@@ -29843,7 +29843,7 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
     case OPC_HSUB_S_df:
     case OPC_HSUB_U_df:
         if (df == DF_BYTE) {
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         switch (MASK_MSA_3R(ctx->opcode)) {
@@ -29981,7 +29981,7 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
         break;
     default:
         MIPS_INVAL("MSA instruction");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
     tcg_temp_free_i32(twd);
@@ -30013,7 +30013,7 @@ static void gen_msa_elm_3e(CPUMIPSState *env, DisasContext *ctx)
         break;
     default:
         MIPS_INVAL("MSA instruction");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 
@@ -30050,12 +30050,12 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df,
 #if !defined(TARGET_MIPS64)
         /* Double format valid only for MIPS64 */
         if (df == DF_DOUBLE) {
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         if ((MASK_MSA_ELM(ctx->opcode) == OPC_COPY_U_df) &&
               (df == DF_WORD)) {
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
 #endif
@@ -30125,7 +30125,7 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df,
         break;
     default:
         MIPS_INVAL("MSA instruction");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
     }
     tcg_temp_free_i32(twd);
     tcg_temp_free_i32(tws);
@@ -30155,7 +30155,7 @@ static void gen_msa_elm(CPUMIPSState *env, DisasContext *ctx)
         gen_msa_elm_3e(env, ctx);
         return;
     } else {
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         return;
     }
 
@@ -30310,7 +30310,7 @@ static void gen_msa_3rf(CPUMIPSState *env, DisasContext *ctx)
         break;
     default:
         MIPS_INVAL("MSA instruction");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 
@@ -30338,7 +30338,7 @@ static void gen_msa_2r(CPUMIPSState *env, DisasContext *ctx)
 #if !defined(TARGET_MIPS64)
         /* Double format valid only for MIPS64 */
         if (df == DF_DOUBLE) {
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
 #endif
@@ -30394,7 +30394,7 @@ static void gen_msa_2r(CPUMIPSState *env, DisasContext *ctx)
         break;
     default:
         MIPS_INVAL("MSA instruction");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 
@@ -30509,7 +30509,7 @@ static void gen_msa_vec_v(CPUMIPSState *env, DisasContext *ctx)
         break;
     default:
         MIPS_INVAL("MSA instruction");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 
@@ -30538,7 +30538,7 @@ static void gen_msa_vec(CPUMIPSState *env, DisasContext *ctx)
         break;
     default:
         MIPS_INVAL("MSA instruction");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -30636,7 +30636,7 @@ static void gen_msa(CPUMIPSState *env, DisasContext *ctx)
         break;
     default:
         MIPS_INVAL("MSA instruction");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 
@@ -30720,7 +30720,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
                     /* OPC_NAL, OPC_BAL */
                     gen_compute_branch(ctx, op1, 4, 0, -1, imm << 2, 4);
                 } else {
-                    generate_exception_end(ctx, EXCP_RI);
+                    gen_reserved_instruction(ctx);
                 }
             } else {
                 gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4);
@@ -30739,7 +30739,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
             break;
         case OPC_SIGRIE:
             check_insn(ctx, ISA_MIPS32R6);
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         case OPC_SYNCI:
             check_insn(ctx, ISA_MIPS32R2);
@@ -30774,7 +30774,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
 #endif
         default:            /* Invalid */
             MIPS_INVAL("regimm");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -30883,7 +30883,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
                     break;
                 default:            /* Invalid */
                     MIPS_INVAL("mfmc0");
-                    generate_exception_end(ctx, EXCP_RI);
+                    gen_reserved_instruction(ctx);
                     break;
                 }
                 tcg_temp_free(t0);
@@ -30900,7 +30900,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
             break;
         default:
             MIPS_INVAL("cp0");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -30936,7 +30936,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
     case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC, OPC_BLEZL */
         if (ctx->insn_flags & ISA_MIPS32R6) {
             if (rt == 0) {
-                generate_exception_end(ctx, EXCP_RI);
+                gen_reserved_instruction(ctx);
                 break;
             }
             /* OPC_BLEZC, OPC_BGEZC, OPC_BGEC */
@@ -30949,7 +30949,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
     case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC, OPC_BGTZL */
         if (ctx->insn_flags & ISA_MIPS32R6) {
             if (rt == 0) {
-                generate_exception_end(ctx, EXCP_RI);
+                gen_reserved_instruction(ctx);
                 break;
             }
             /* OPC_BGTZC, OPC_BLTZC, OPC_BLTC */
@@ -31198,7 +31198,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
             break;
         default:
             MIPS_INVAL("cp1");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             break;
         }
         break;
@@ -31284,7 +31284,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
                 break;
             default:
                 MIPS_INVAL("cp3");
-                generate_exception_end(ctx, EXCP_RI);
+                gen_reserved_instruction(ctx);
                 break;
             }
         } else {
@@ -31349,7 +31349,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
             gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
         } else {
             MIPS_INVAL("major opcode");
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
         }
         break;
 #endif
@@ -31367,7 +31367,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
                 tcg_temp_free(t0);
             }
 #else
-            generate_exception_end(ctx, EXCP_RI);
+            gen_reserved_instruction(ctx);
             MIPS_INVAL("major opcode");
 #endif
         } else {
@@ -31393,7 +31393,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
         break;
     default:            /* Invalid */
         MIPS_INVAL("major opcode");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         break;
     }
 }
@@ -31498,7 +31498,7 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
         ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
         insn_bytes = decode_mips16_opc(env, ctx);
     } else {
-        generate_exception_end(ctx, EXCP_RI);
+        gen_reserved_instruction(ctx);
         g_assert(ctx->base.is_jmp == DISAS_NORETURN);
         return;
     }
-- 
2.26.2



^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 12/16] target/mips/translate: Extract DisasContext structure
  2020-12-14 18:37 ` Philippe Mathieu-Daudé
@ 2020-12-14 18:37   ` Philippe Mathieu-Daudé
  -1 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: kvm, Aurelien Jarno, Huacai Chen, Aleksandar Rikalo, Jiaxun Yang,
	Laurent Vivier, Paolo Bonzini, Philippe Mathieu-Daudé,
	Richard Henderson

Extract DisasContext to a new 'translate.h' header so
different translation files (ISA, ASE, extensions)
can use it.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201207235539.4070364-2-f4bug@amsat.org>
---
 target/mips/translate.h | 50 +++++++++++++++++++++++++++++++++++++++++
 target/mips/translate.c | 38 +------------------------------
 2 files changed, 51 insertions(+), 37 deletions(-)
 create mode 100644 target/mips/translate.h

diff --git a/target/mips/translate.h b/target/mips/translate.h
new file mode 100644
index 00000000000..fcda1a99001
--- /dev/null
+++ b/target/mips/translate.h
@@ -0,0 +1,50 @@
+/*
+ *  MIPS translation routines.
+ *
+ *  Copyright (c) 2004-2005 Jocelyn Mayer
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+#ifndef TARGET_MIPS_TRANSLATE_H
+#define TARGET_MIPS_TRANSLATE_H
+
+#include "exec/translator.h"
+
+typedef struct DisasContext {
+    DisasContextBase base;
+    target_ulong saved_pc;
+    target_ulong page_start;
+    uint32_t opcode;
+    uint64_t insn_flags;
+    int32_t CP0_Config1;
+    int32_t CP0_Config2;
+    int32_t CP0_Config3;
+    int32_t CP0_Config5;
+    /* Routine used to access memory */
+    int mem_idx;
+    MemOp default_tcg_memop_mask;
+    uint32_t hflags, saved_hflags;
+    target_ulong btarget;
+    bool ulri;
+    int kscrexist;
+    bool rxi;
+    int ie;
+    bool bi;
+    bool bp;
+    uint64_t PAMask;
+    bool mvh;
+    bool eva;
+    bool sc;
+    int CP0_LLAddr_shift;
+    bool ps;
+    bool vp;
+    bool cmgcr;
+    bool mrp;
+    bool nan2008;
+    bool abs2008;
+    bool saar;
+    bool mi;
+    int gi;
+} DisasContext;
+
+#endif
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 49570a95615..0db0fce3789 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -36,6 +36,7 @@
 #include "exec/log.h"
 #include "qemu/qemu-print.h"
 #include "fpu_helper.h"
+#include "translate.h"
 
 #define MIPS_DEBUG_DISAS 0
 
@@ -2554,43 +2555,6 @@ static TCGv mxu_CR;
     tcg_temp_free_i32(helper_tmp);                                \
     } while (0)
 
-typedef struct DisasContext {
-    DisasContextBase base;
-    target_ulong saved_pc;
-    target_ulong page_start;
-    uint32_t opcode;
-    uint64_t insn_flags;
-    int32_t CP0_Config1;
-    int32_t CP0_Config2;
-    int32_t CP0_Config3;
-    int32_t CP0_Config5;
-    /* Routine used to access memory */
-    int mem_idx;
-    MemOp default_tcg_memop_mask;
-    uint32_t hflags, saved_hflags;
-    target_ulong btarget;
-    bool ulri;
-    int kscrexist;
-    bool rxi;
-    int ie;
-    bool bi;
-    bool bp;
-    uint64_t PAMask;
-    bool mvh;
-    bool eva;
-    bool sc;
-    int CP0_LLAddr_shift;
-    bool ps;
-    bool vp;
-    bool cmgcr;
-    bool mrp;
-    bool nan2008;
-    bool abs2008;
-    bool saar;
-    bool mi;
-    int gi;
-} DisasContext;
-
 #define DISAS_STOP       DISAS_TARGET_0
 #define DISAS_EXIT       DISAS_TARGET_1
 
-- 
2.26.2


^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 12/16] target/mips/translate: Extract DisasContext structure
@ 2020-12-14 18:37   ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, kvm, Huacai Chen, Richard Henderson,
	Laurent Vivier, Jiaxun Yang, Philippe Mathieu-Daudé,
	Paolo Bonzini, Aurelien Jarno

Extract DisasContext to a new 'translate.h' header so
different translation files (ISA, ASE, extensions)
can use it.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201207235539.4070364-2-f4bug@amsat.org>
---
 target/mips/translate.h | 50 +++++++++++++++++++++++++++++++++++++++++
 target/mips/translate.c | 38 +------------------------------
 2 files changed, 51 insertions(+), 37 deletions(-)
 create mode 100644 target/mips/translate.h

diff --git a/target/mips/translate.h b/target/mips/translate.h
new file mode 100644
index 00000000000..fcda1a99001
--- /dev/null
+++ b/target/mips/translate.h
@@ -0,0 +1,50 @@
+/*
+ *  MIPS translation routines.
+ *
+ *  Copyright (c) 2004-2005 Jocelyn Mayer
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+#ifndef TARGET_MIPS_TRANSLATE_H
+#define TARGET_MIPS_TRANSLATE_H
+
+#include "exec/translator.h"
+
+typedef struct DisasContext {
+    DisasContextBase base;
+    target_ulong saved_pc;
+    target_ulong page_start;
+    uint32_t opcode;
+    uint64_t insn_flags;
+    int32_t CP0_Config1;
+    int32_t CP0_Config2;
+    int32_t CP0_Config3;
+    int32_t CP0_Config5;
+    /* Routine used to access memory */
+    int mem_idx;
+    MemOp default_tcg_memop_mask;
+    uint32_t hflags, saved_hflags;
+    target_ulong btarget;
+    bool ulri;
+    int kscrexist;
+    bool rxi;
+    int ie;
+    bool bi;
+    bool bp;
+    uint64_t PAMask;
+    bool mvh;
+    bool eva;
+    bool sc;
+    int CP0_LLAddr_shift;
+    bool ps;
+    bool vp;
+    bool cmgcr;
+    bool mrp;
+    bool nan2008;
+    bool abs2008;
+    bool saar;
+    bool mi;
+    int gi;
+} DisasContext;
+
+#endif
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 49570a95615..0db0fce3789 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -36,6 +36,7 @@
 #include "exec/log.h"
 #include "qemu/qemu-print.h"
 #include "fpu_helper.h"
+#include "translate.h"
 
 #define MIPS_DEBUG_DISAS 0
 
@@ -2554,43 +2555,6 @@ static TCGv mxu_CR;
     tcg_temp_free_i32(helper_tmp);                                \
     } while (0)
 
-typedef struct DisasContext {
-    DisasContextBase base;
-    target_ulong saved_pc;
-    target_ulong page_start;
-    uint32_t opcode;
-    uint64_t insn_flags;
-    int32_t CP0_Config1;
-    int32_t CP0_Config2;
-    int32_t CP0_Config3;
-    int32_t CP0_Config5;
-    /* Routine used to access memory */
-    int mem_idx;
-    MemOp default_tcg_memop_mask;
-    uint32_t hflags, saved_hflags;
-    target_ulong btarget;
-    bool ulri;
-    int kscrexist;
-    bool rxi;
-    int ie;
-    bool bi;
-    bool bp;
-    uint64_t PAMask;
-    bool mvh;
-    bool eva;
-    bool sc;
-    int CP0_LLAddr_shift;
-    bool ps;
-    bool vp;
-    bool cmgcr;
-    bool mrp;
-    bool nan2008;
-    bool abs2008;
-    bool saar;
-    bool mi;
-    int gi;
-} DisasContext;
-
 #define DISAS_STOP       DISAS_TARGET_0
 #define DISAS_EXIT       DISAS_TARGET_1
 
-- 
2.26.2



^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 13/16] target/mips/translate: Add declarations for generic code
  2020-12-14 18:37 ` Philippe Mathieu-Daudé
@ 2020-12-14 18:37   ` Philippe Mathieu-Daudé
  -1 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: kvm, Aurelien Jarno, Huacai Chen, Aleksandar Rikalo, Jiaxun Yang,
	Laurent Vivier, Paolo Bonzini, Philippe Mathieu-Daudé,
	Richard Henderson

Some CPU translation functions / registers / macros and
definitions can be used by ISA / ASE / extensions out of
the big translate.c file. Declare them in "translate.h".

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201207235539.4070364-3-f4bug@amsat.org>
---
 target/mips/translate.h | 38 ++++++++++++++++++++++++++++++++
 target/mips/translate.c | 48 +++++++++++++----------------------------
 2 files changed, 53 insertions(+), 33 deletions(-)

diff --git a/target/mips/translate.h b/target/mips/translate.h
index fcda1a99001..989d6c43207 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -10,6 +10,8 @@
 
 #include "exec/translator.h"
 
+#define MIPS_DEBUG_DISAS 0
+
 typedef struct DisasContext {
     DisasContextBase base;
     target_ulong saved_pc;
@@ -47,4 +49,40 @@ typedef struct DisasContext {
     int gi;
 } DisasContext;
 
+/* MIPS major opcodes */
+#define MASK_OP_MAJOR(op)   (op & (0x3F << 26))
+
+void generate_exception_err(DisasContext *ctx, int excp, int err);
+void generate_exception_end(DisasContext *ctx, int excp);
+void gen_reserved_instruction(DisasContext *ctx);
+void check_insn(DisasContext *ctx, uint64_t flags);
+#ifdef TARGET_MIPS64
+void check_mips_64(DisasContext *ctx);
+#endif
+
+void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset);
+void gen_load_gpr(TCGv t, int reg);
+void gen_store_gpr(TCGv t, int reg);
+
+extern TCGv cpu_gpr[32], cpu_PC;
+extern TCGv bcond;
+
+#define LOG_DISAS(...)                                                        \
+    do {                                                                      \
+        if (MIPS_DEBUG_DISAS) {                                               \
+            qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__);                 \
+        }                                                                     \
+    } while (0)
+
+#define MIPS_INVAL(op)                                                        \
+    do {                                                                      \
+        if (MIPS_DEBUG_DISAS) {                                               \
+            qemu_log_mask(CPU_LOG_TB_IN_ASM,                                  \
+                          TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \
+                          ctx->base.pc_next, ctx->opcode, op,                 \
+                          ctx->opcode >> 26, ctx->opcode & 0x3F,              \
+                          ((ctx->opcode >> 16) & 0x1F));                      \
+        }                                                                     \
+    } while (0)
+
 #endif
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 0db0fce3789..318642cbcfe 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -38,11 +38,6 @@
 #include "fpu_helper.h"
 #include "translate.h"
 
-#define MIPS_DEBUG_DISAS 0
-
-/* MIPS major opcodes */
-#define MASK_OP_MAJOR(op)       (op & (0x3F << 26))
-
 enum {
     /* indirect opcode tables */
     OPC_SPECIAL  = (0x00 << 26),
@@ -2491,9 +2486,10 @@ enum {
 };
 
 /* global register indices */
-static TCGv cpu_gpr[32], cpu_PC;
+TCGv cpu_gpr[32], cpu_PC;
 static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
-static TCGv cpu_dspctrl, btarget, bcond;
+static TCGv cpu_dspctrl, btarget;
+TCGv bcond;
 static TCGv cpu_lladdr, cpu_llval;
 static TCGv_i32 hflags;
 static TCGv_i32 fpu_fcr0, fpu_fcr31;
@@ -2606,26 +2602,8 @@ static const char * const mxuregnames[] = {
 };
 #endif
 
-#define LOG_DISAS(...)                                                        \
-    do {                                                                      \
-        if (MIPS_DEBUG_DISAS) {                                               \
-            qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__);                 \
-        }                                                                     \
-    } while (0)
-
-#define MIPS_INVAL(op)                                                        \
-    do {                                                                      \
-        if (MIPS_DEBUG_DISAS) {                                               \
-            qemu_log_mask(CPU_LOG_TB_IN_ASM,                                  \
-                          TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \
-                          ctx->base.pc_next, ctx->opcode, op,                 \
-                          ctx->opcode >> 26, ctx->opcode & 0x3F,              \
-                          ((ctx->opcode >> 16) & 0x1F));                      \
-        }                                                                     \
-    } while (0)
-
 /* General purpose registers moves. */
-static inline void gen_load_gpr(TCGv t, int reg)
+void gen_load_gpr(TCGv t, int reg)
 {
     if (reg == 0) {
         tcg_gen_movi_tl(t, 0);
@@ -2634,7 +2612,7 @@ static inline void gen_load_gpr(TCGv t, int reg)
     }
 }
 
-static inline void gen_store_gpr(TCGv t, int reg)
+void gen_store_gpr(TCGv t, int reg)
 {
     if (reg != 0) {
         tcg_gen_mov_tl(cpu_gpr[reg], t);
@@ -2763,7 +2741,7 @@ static inline void restore_cpu_state(CPUMIPSState *env, DisasContext *ctx)
     }
 }
 
-static inline void generate_exception_err(DisasContext *ctx, int excp, int err)
+void generate_exception_err(DisasContext *ctx, int excp, int err)
 {
     TCGv_i32 texcp = tcg_const_i32(excp);
     TCGv_i32 terr = tcg_const_i32(err);
@@ -2779,11 +2757,16 @@ static inline void generate_exception(DisasContext *ctx, int excp)
     gen_helper_0e0i(raise_exception, excp);
 }
 
-static inline void generate_exception_end(DisasContext *ctx, int excp)
+void generate_exception_end(DisasContext *ctx, int excp)
 {
     generate_exception_err(ctx, excp, 0);
 }
 
+void gen_reserved_instruction(DisasContext *ctx)
+{
+    generate_exception_end(ctx, EXCP_RI);
+}
+
 /* Floating point register moves. */
 static void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg)
 {
@@ -3013,7 +2996,7 @@ static inline void check_dsp_r3(DisasContext *ctx)
  * This code generates a "reserved instruction" exception if the
  * CPU does not support the instruction set corresponding to flags.
  */
-static inline void check_insn(DisasContext *ctx, uint64_t flags)
+void check_insn(DisasContext *ctx, uint64_t flags)
 {
     if (unlikely(!(ctx->insn_flags & flags))) {
         gen_reserved_instruction(ctx);
@@ -3064,7 +3047,7 @@ static inline void check_ps(DisasContext *ctx)
  * This code generates a "reserved instruction" exception if 64-bit
  * instructions are not enabled.
  */
-static inline void check_mips_64(DisasContext *ctx)
+void check_mips_64(DisasContext *ctx)
 {
     if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) {
         gen_reserved_instruction(ctx);
@@ -3390,8 +3373,7 @@ OP_LD_ATOMIC(lld, ld64);
 #endif
 #undef OP_LD_ATOMIC
 
-static void gen_base_offset_addr(DisasContext *ctx, TCGv addr,
-                                 int base, int offset)
+void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset)
 {
     if (base == 0) {
         tcg_gen_movi_tl(addr, offset);
-- 
2.26.2


^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 13/16] target/mips/translate: Add declarations for generic code
@ 2020-12-14 18:37   ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, kvm, Huacai Chen, Richard Henderson,
	Laurent Vivier, Jiaxun Yang, Philippe Mathieu-Daudé,
	Paolo Bonzini, Aurelien Jarno

Some CPU translation functions / registers / macros and
definitions can be used by ISA / ASE / extensions out of
the big translate.c file. Declare them in "translate.h".

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201207235539.4070364-3-f4bug@amsat.org>
---
 target/mips/translate.h | 38 ++++++++++++++++++++++++++++++++
 target/mips/translate.c | 48 +++++++++++++----------------------------
 2 files changed, 53 insertions(+), 33 deletions(-)

diff --git a/target/mips/translate.h b/target/mips/translate.h
index fcda1a99001..989d6c43207 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -10,6 +10,8 @@
 
 #include "exec/translator.h"
 
+#define MIPS_DEBUG_DISAS 0
+
 typedef struct DisasContext {
     DisasContextBase base;
     target_ulong saved_pc;
@@ -47,4 +49,40 @@ typedef struct DisasContext {
     int gi;
 } DisasContext;
 
+/* MIPS major opcodes */
+#define MASK_OP_MAJOR(op)   (op & (0x3F << 26))
+
+void generate_exception_err(DisasContext *ctx, int excp, int err);
+void generate_exception_end(DisasContext *ctx, int excp);
+void gen_reserved_instruction(DisasContext *ctx);
+void check_insn(DisasContext *ctx, uint64_t flags);
+#ifdef TARGET_MIPS64
+void check_mips_64(DisasContext *ctx);
+#endif
+
+void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset);
+void gen_load_gpr(TCGv t, int reg);
+void gen_store_gpr(TCGv t, int reg);
+
+extern TCGv cpu_gpr[32], cpu_PC;
+extern TCGv bcond;
+
+#define LOG_DISAS(...)                                                        \
+    do {                                                                      \
+        if (MIPS_DEBUG_DISAS) {                                               \
+            qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__);                 \
+        }                                                                     \
+    } while (0)
+
+#define MIPS_INVAL(op)                                                        \
+    do {                                                                      \
+        if (MIPS_DEBUG_DISAS) {                                               \
+            qemu_log_mask(CPU_LOG_TB_IN_ASM,                                  \
+                          TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \
+                          ctx->base.pc_next, ctx->opcode, op,                 \
+                          ctx->opcode >> 26, ctx->opcode & 0x3F,              \
+                          ((ctx->opcode >> 16) & 0x1F));                      \
+        }                                                                     \
+    } while (0)
+
 #endif
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 0db0fce3789..318642cbcfe 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -38,11 +38,6 @@
 #include "fpu_helper.h"
 #include "translate.h"
 
-#define MIPS_DEBUG_DISAS 0
-
-/* MIPS major opcodes */
-#define MASK_OP_MAJOR(op)       (op & (0x3F << 26))
-
 enum {
     /* indirect opcode tables */
     OPC_SPECIAL  = (0x00 << 26),
@@ -2491,9 +2486,10 @@ enum {
 };
 
 /* global register indices */
-static TCGv cpu_gpr[32], cpu_PC;
+TCGv cpu_gpr[32], cpu_PC;
 static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
-static TCGv cpu_dspctrl, btarget, bcond;
+static TCGv cpu_dspctrl, btarget;
+TCGv bcond;
 static TCGv cpu_lladdr, cpu_llval;
 static TCGv_i32 hflags;
 static TCGv_i32 fpu_fcr0, fpu_fcr31;
@@ -2606,26 +2602,8 @@ static const char * const mxuregnames[] = {
 };
 #endif
 
-#define LOG_DISAS(...)                                                        \
-    do {                                                                      \
-        if (MIPS_DEBUG_DISAS) {                                               \
-            qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__);                 \
-        }                                                                     \
-    } while (0)
-
-#define MIPS_INVAL(op)                                                        \
-    do {                                                                      \
-        if (MIPS_DEBUG_DISAS) {                                               \
-            qemu_log_mask(CPU_LOG_TB_IN_ASM,                                  \
-                          TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \
-                          ctx->base.pc_next, ctx->opcode, op,                 \
-                          ctx->opcode >> 26, ctx->opcode & 0x3F,              \
-                          ((ctx->opcode >> 16) & 0x1F));                      \
-        }                                                                     \
-    } while (0)
-
 /* General purpose registers moves. */
-static inline void gen_load_gpr(TCGv t, int reg)
+void gen_load_gpr(TCGv t, int reg)
 {
     if (reg == 0) {
         tcg_gen_movi_tl(t, 0);
@@ -2634,7 +2612,7 @@ static inline void gen_load_gpr(TCGv t, int reg)
     }
 }
 
-static inline void gen_store_gpr(TCGv t, int reg)
+void gen_store_gpr(TCGv t, int reg)
 {
     if (reg != 0) {
         tcg_gen_mov_tl(cpu_gpr[reg], t);
@@ -2763,7 +2741,7 @@ static inline void restore_cpu_state(CPUMIPSState *env, DisasContext *ctx)
     }
 }
 
-static inline void generate_exception_err(DisasContext *ctx, int excp, int err)
+void generate_exception_err(DisasContext *ctx, int excp, int err)
 {
     TCGv_i32 texcp = tcg_const_i32(excp);
     TCGv_i32 terr = tcg_const_i32(err);
@@ -2779,11 +2757,16 @@ static inline void generate_exception(DisasContext *ctx, int excp)
     gen_helper_0e0i(raise_exception, excp);
 }
 
-static inline void generate_exception_end(DisasContext *ctx, int excp)
+void generate_exception_end(DisasContext *ctx, int excp)
 {
     generate_exception_err(ctx, excp, 0);
 }
 
+void gen_reserved_instruction(DisasContext *ctx)
+{
+    generate_exception_end(ctx, EXCP_RI);
+}
+
 /* Floating point register moves. */
 static void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg)
 {
@@ -3013,7 +2996,7 @@ static inline void check_dsp_r3(DisasContext *ctx)
  * This code generates a "reserved instruction" exception if the
  * CPU does not support the instruction set corresponding to flags.
  */
-static inline void check_insn(DisasContext *ctx, uint64_t flags)
+void check_insn(DisasContext *ctx, uint64_t flags)
 {
     if (unlikely(!(ctx->insn_flags & flags))) {
         gen_reserved_instruction(ctx);
@@ -3064,7 +3047,7 @@ static inline void check_ps(DisasContext *ctx)
  * This code generates a "reserved instruction" exception if 64-bit
  * instructions are not enabled.
  */
-static inline void check_mips_64(DisasContext *ctx)
+void check_mips_64(DisasContext *ctx)
 {
     if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) {
         gen_reserved_instruction(ctx);
@@ -3390,8 +3373,7 @@ OP_LD_ATOMIC(lld, ld64);
 #endif
 #undef OP_LD_ATOMIC
 
-static void gen_base_offset_addr(DisasContext *ctx, TCGv addr,
-                                 int base, int offset)
+void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset)
 {
     if (base == 0) {
         tcg_gen_movi_tl(addr, offset);
-- 
2.26.2



^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 14/16] target/mips: Declare generic FPU functions in 'translate.h'
  2020-12-14 18:37 ` Philippe Mathieu-Daudé
@ 2020-12-14 18:37   ` Philippe Mathieu-Daudé
  -1 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: kvm, Aurelien Jarno, Huacai Chen, Aleksandar Rikalo, Jiaxun Yang,
	Laurent Vivier, Paolo Bonzini, Philippe Mathieu-Daudé

Some FPU translation functions / registers can be used by
ISA / ASE / extensions out of the big translate.c file.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/translate.h |  7 +++++++
 target/mips/translate.c | 12 ++++++------
 2 files changed, 13 insertions(+), 6 deletions(-)

diff --git a/target/mips/translate.h b/target/mips/translate.h
index 989d6c43207..a30fbf21ff9 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -59,12 +59,19 @@ void check_insn(DisasContext *ctx, uint64_t flags);
 #ifdef TARGET_MIPS64
 void check_mips_64(DisasContext *ctx);
 #endif
+void check_cp1_enabled(DisasContext *ctx);
 
 void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset);
 void gen_load_gpr(TCGv t, int reg);
 void gen_store_gpr(TCGv t, int reg);
 
+void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
+void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
+int get_fp_bit(int cc);
+
 extern TCGv cpu_gpr[32], cpu_PC;
+extern TCGv_i32 fpu_fcr0, fpu_fcr31;
+extern TCGv_i64 fpu_f64[32];
 extern TCGv bcond;
 
 #define LOG_DISAS(...)                                                        \
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 318642cbcfe..08ed542f4d4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2492,8 +2492,8 @@ static TCGv cpu_dspctrl, btarget;
 TCGv bcond;
 static TCGv cpu_lladdr, cpu_llval;
 static TCGv_i32 hflags;
-static TCGv_i32 fpu_fcr0, fpu_fcr31;
-static TCGv_i64 fpu_f64[32];
+TCGv_i32 fpu_fcr0, fpu_fcr31;
+TCGv_i64 fpu_f64[32];
 static TCGv_i64 msa_wr_d[64];
 
 #if defined(TARGET_MIPS64)
@@ -2809,7 +2809,7 @@ static void gen_store_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg)
     }
 }
 
-static void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
+void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
 {
     if (ctx->hflags & MIPS_HFLAG_F64) {
         tcg_gen_mov_i64(t, fpu_f64[reg]);
@@ -2818,7 +2818,7 @@ static void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
     }
 }
 
-static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
+void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
 {
     if (ctx->hflags & MIPS_HFLAG_F64) {
         tcg_gen_mov_i64(fpu_f64[reg], t);
@@ -2832,7 +2832,7 @@ static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
     }
 }
 
-static inline int get_fp_bit(int cc)
+int get_fp_bit(int cc)
 {
     if (cc) {
         return 24 + cc;
@@ -2907,7 +2907,7 @@ static inline void check_cp0_enabled(DisasContext *ctx)
     }
 }
 
-static inline void check_cp1_enabled(DisasContext *ctx)
+void check_cp1_enabled(DisasContext *ctx)
 {
     if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) {
         generate_exception_err(ctx, EXCP_CpU, 1);
-- 
2.26.2


^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 14/16] target/mips: Declare generic FPU functions in 'translate.h'
@ 2020-12-14 18:37   ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, kvm, Huacai Chen, Laurent Vivier, Jiaxun Yang,
	Philippe Mathieu-Daudé,
	Paolo Bonzini, Aurelien Jarno

Some FPU translation functions / registers can be used by
ISA / ASE / extensions out of the big translate.c file.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/translate.h |  7 +++++++
 target/mips/translate.c | 12 ++++++------
 2 files changed, 13 insertions(+), 6 deletions(-)

diff --git a/target/mips/translate.h b/target/mips/translate.h
index 989d6c43207..a30fbf21ff9 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -59,12 +59,19 @@ void check_insn(DisasContext *ctx, uint64_t flags);
 #ifdef TARGET_MIPS64
 void check_mips_64(DisasContext *ctx);
 #endif
+void check_cp1_enabled(DisasContext *ctx);
 
 void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset);
 void gen_load_gpr(TCGv t, int reg);
 void gen_store_gpr(TCGv t, int reg);
 
+void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
+void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
+int get_fp_bit(int cc);
+
 extern TCGv cpu_gpr[32], cpu_PC;
+extern TCGv_i32 fpu_fcr0, fpu_fcr31;
+extern TCGv_i64 fpu_f64[32];
 extern TCGv bcond;
 
 #define LOG_DISAS(...)                                                        \
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 318642cbcfe..08ed542f4d4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2492,8 +2492,8 @@ static TCGv cpu_dspctrl, btarget;
 TCGv bcond;
 static TCGv cpu_lladdr, cpu_llval;
 static TCGv_i32 hflags;
-static TCGv_i32 fpu_fcr0, fpu_fcr31;
-static TCGv_i64 fpu_f64[32];
+TCGv_i32 fpu_fcr0, fpu_fcr31;
+TCGv_i64 fpu_f64[32];
 static TCGv_i64 msa_wr_d[64];
 
 #if defined(TARGET_MIPS64)
@@ -2809,7 +2809,7 @@ static void gen_store_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg)
     }
 }
 
-static void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
+void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
 {
     if (ctx->hflags & MIPS_HFLAG_F64) {
         tcg_gen_mov_i64(t, fpu_f64[reg]);
@@ -2818,7 +2818,7 @@ static void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
     }
 }
 
-static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
+void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
 {
     if (ctx->hflags & MIPS_HFLAG_F64) {
         tcg_gen_mov_i64(fpu_f64[reg], t);
@@ -2832,7 +2832,7 @@ static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
     }
 }
 
-static inline int get_fp_bit(int cc)
+int get_fp_bit(int cc)
 {
     if (cc) {
         return 24 + cc;
@@ -2907,7 +2907,7 @@ static inline void check_cp0_enabled(DisasContext *ctx)
     }
 }
 
-static inline void check_cp1_enabled(DisasContext *ctx)
+void check_cp1_enabled(DisasContext *ctx)
 {
     if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) {
         generate_exception_err(ctx, EXCP_CpU, 1);
-- 
2.26.2



^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 15/16] target/mips: Extract FPU specific definitions to translate.h
  2020-12-14 18:37 ` Philippe Mathieu-Daudé
@ 2020-12-14 18:37   ` Philippe Mathieu-Daudé
  -1 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: kvm, Aurelien Jarno, Huacai Chen, Aleksandar Rikalo, Jiaxun Yang,
	Laurent Vivier, Paolo Bonzini, Philippe Mathieu-Daudé

Extract FPU specific definitions that can be used by
ISA / ASE / extensions to translate.h header.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/translate.h | 71 +++++++++++++++++++++++++++++++++++++++++
 target/mips/translate.c | 70 ----------------------------------------
 2 files changed, 71 insertions(+), 70 deletions(-)

diff --git a/target/mips/translate.h b/target/mips/translate.h
index a30fbf21ff9..a9eab69249f 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -52,6 +52,77 @@ typedef struct DisasContext {
 /* MIPS major opcodes */
 #define MASK_OP_MAJOR(op)   (op & (0x3F << 26))
 
+#define OPC_CP1 (0x11 << 26)
+
+/* Coprocessor 1 (rs field) */
+#define MASK_CP1(op)                (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
+
+/* Values for the fmt field in FP instructions */
+enum {
+    /* 0 - 15 are reserved */
+    FMT_S = 16,          /* single fp */
+    FMT_D = 17,          /* double fp */
+    FMT_E = 18,          /* extended fp */
+    FMT_Q = 19,          /* quad fp */
+    FMT_W = 20,          /* 32-bit fixed */
+    FMT_L = 21,          /* 64-bit fixed */
+    FMT_PS = 22,         /* paired single fp */
+    /* 23 - 31 are reserved */
+};
+
+enum {
+    OPC_MFC1     = (0x00 << 21) | OPC_CP1,
+    OPC_DMFC1    = (0x01 << 21) | OPC_CP1,
+    OPC_CFC1     = (0x02 << 21) | OPC_CP1,
+    OPC_MFHC1    = (0x03 << 21) | OPC_CP1,
+    OPC_MTC1     = (0x04 << 21) | OPC_CP1,
+    OPC_DMTC1    = (0x05 << 21) | OPC_CP1,
+    OPC_CTC1     = (0x06 << 21) | OPC_CP1,
+    OPC_MTHC1    = (0x07 << 21) | OPC_CP1,
+    OPC_BC1      = (0x08 << 21) | OPC_CP1, /* bc */
+    OPC_BC1ANY2  = (0x09 << 21) | OPC_CP1,
+    OPC_BC1ANY4  = (0x0A << 21) | OPC_CP1,
+    OPC_BZ_V     = (0x0B << 21) | OPC_CP1,
+    OPC_BNZ_V    = (0x0F << 21) | OPC_CP1,
+    OPC_S_FMT    = (FMT_S << 21) | OPC_CP1,
+    OPC_D_FMT    = (FMT_D << 21) | OPC_CP1,
+    OPC_E_FMT    = (FMT_E << 21) | OPC_CP1,
+    OPC_Q_FMT    = (FMT_Q << 21) | OPC_CP1,
+    OPC_W_FMT    = (FMT_W << 21) | OPC_CP1,
+    OPC_L_FMT    = (FMT_L << 21) | OPC_CP1,
+    OPC_PS_FMT   = (FMT_PS << 21) | OPC_CP1,
+    OPC_BC1EQZ   = (0x09 << 21) | OPC_CP1,
+    OPC_BC1NEZ   = (0x0D << 21) | OPC_CP1,
+    OPC_BZ_B     = (0x18 << 21) | OPC_CP1,
+    OPC_BZ_H     = (0x19 << 21) | OPC_CP1,
+    OPC_BZ_W     = (0x1A << 21) | OPC_CP1,
+    OPC_BZ_D     = (0x1B << 21) | OPC_CP1,
+    OPC_BNZ_B    = (0x1C << 21) | OPC_CP1,
+    OPC_BNZ_H    = (0x1D << 21) | OPC_CP1,
+    OPC_BNZ_W    = (0x1E << 21) | OPC_CP1,
+    OPC_BNZ_D    = (0x1F << 21) | OPC_CP1,
+};
+
+#define MASK_CP1_FUNC(op)           (MASK_CP1(op) | (op & 0x3F))
+#define MASK_BC1(op)                (MASK_CP1(op) | (op & (0x3 << 16)))
+
+enum {
+    OPC_BC1F     = (0x00 << 16) | OPC_BC1,
+    OPC_BC1T     = (0x01 << 16) | OPC_BC1,
+    OPC_BC1FL    = (0x02 << 16) | OPC_BC1,
+    OPC_BC1TL    = (0x03 << 16) | OPC_BC1,
+};
+
+enum {
+    OPC_BC1FANY2     = (0x00 << 16) | OPC_BC1ANY2,
+    OPC_BC1TANY2     = (0x01 << 16) | OPC_BC1ANY2,
+};
+
+enum {
+    OPC_BC1FANY4     = (0x00 << 16) | OPC_BC1ANY4,
+    OPC_BC1TANY4     = (0x01 << 16) | OPC_BC1ANY4,
+};
+
 void generate_exception_err(DisasContext *ctx, int excp, int err);
 void generate_exception_end(DisasContext *ctx, int excp);
 void gen_reserved_instruction(DisasContext *ctx);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 08ed542f4d4..cc876019bf7 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -43,7 +43,6 @@ enum {
     OPC_SPECIAL  = (0x00 << 26),
     OPC_REGIMM   = (0x01 << 26),
     OPC_CP0      = (0x10 << 26),
-    OPC_CP1      = (0x11 << 26),
     OPC_CP2      = (0x12 << 26),
     OPC_CP3      = (0x13 << 26),
     OPC_SPECIAL2 = (0x1C << 26),
@@ -996,75 +995,6 @@ enum {
     OPC_WAIT     = 0x20 | OPC_C0,
 };
 
-/* Coprocessor 1 (rs field) */
-#define MASK_CP1(op)                (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
-
-/* Values for the fmt field in FP instructions */
-enum {
-    /* 0 - 15 are reserved */
-    FMT_S = 16,          /* single fp */
-    FMT_D = 17,          /* double fp */
-    FMT_E = 18,          /* extended fp */
-    FMT_Q = 19,          /* quad fp */
-    FMT_W = 20,          /* 32-bit fixed */
-    FMT_L = 21,          /* 64-bit fixed */
-    FMT_PS = 22,         /* paired single fp */
-    /* 23 - 31 are reserved */
-};
-
-enum {
-    OPC_MFC1     = (0x00 << 21) | OPC_CP1,
-    OPC_DMFC1    = (0x01 << 21) | OPC_CP1,
-    OPC_CFC1     = (0x02 << 21) | OPC_CP1,
-    OPC_MFHC1    = (0x03 << 21) | OPC_CP1,
-    OPC_MTC1     = (0x04 << 21) | OPC_CP1,
-    OPC_DMTC1    = (0x05 << 21) | OPC_CP1,
-    OPC_CTC1     = (0x06 << 21) | OPC_CP1,
-    OPC_MTHC1    = (0x07 << 21) | OPC_CP1,
-    OPC_BC1      = (0x08 << 21) | OPC_CP1, /* bc */
-    OPC_BC1ANY2  = (0x09 << 21) | OPC_CP1,
-    OPC_BC1ANY4  = (0x0A << 21) | OPC_CP1,
-    OPC_BZ_V     = (0x0B << 21) | OPC_CP1,
-    OPC_BNZ_V    = (0x0F << 21) | OPC_CP1,
-    OPC_S_FMT    = (FMT_S << 21) | OPC_CP1,
-    OPC_D_FMT    = (FMT_D << 21) | OPC_CP1,
-    OPC_E_FMT    = (FMT_E << 21) | OPC_CP1,
-    OPC_Q_FMT    = (FMT_Q << 21) | OPC_CP1,
-    OPC_W_FMT    = (FMT_W << 21) | OPC_CP1,
-    OPC_L_FMT    = (FMT_L << 21) | OPC_CP1,
-    OPC_PS_FMT   = (FMT_PS << 21) | OPC_CP1,
-    OPC_BC1EQZ   = (0x09 << 21) | OPC_CP1,
-    OPC_BC1NEZ   = (0x0D << 21) | OPC_CP1,
-    OPC_BZ_B     = (0x18 << 21) | OPC_CP1,
-    OPC_BZ_H     = (0x19 << 21) | OPC_CP1,
-    OPC_BZ_W     = (0x1A << 21) | OPC_CP1,
-    OPC_BZ_D     = (0x1B << 21) | OPC_CP1,
-    OPC_BNZ_B    = (0x1C << 21) | OPC_CP1,
-    OPC_BNZ_H    = (0x1D << 21) | OPC_CP1,
-    OPC_BNZ_W    = (0x1E << 21) | OPC_CP1,
-    OPC_BNZ_D    = (0x1F << 21) | OPC_CP1,
-};
-
-#define MASK_CP1_FUNC(op)           (MASK_CP1(op) | (op & 0x3F))
-#define MASK_BC1(op)                (MASK_CP1(op) | (op & (0x3 << 16)))
-
-enum {
-    OPC_BC1F     = (0x00 << 16) | OPC_BC1,
-    OPC_BC1T     = (0x01 << 16) | OPC_BC1,
-    OPC_BC1FL    = (0x02 << 16) | OPC_BC1,
-    OPC_BC1TL    = (0x03 << 16) | OPC_BC1,
-};
-
-enum {
-    OPC_BC1FANY2     = (0x00 << 16) | OPC_BC1ANY2,
-    OPC_BC1TANY2     = (0x01 << 16) | OPC_BC1ANY2,
-};
-
-enum {
-    OPC_BC1FANY4     = (0x00 << 16) | OPC_BC1ANY4,
-    OPC_BC1TANY4     = (0x01 << 16) | OPC_BC1ANY4,
-};
-
 #define MASK_CP2(op)                (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
 
 enum {
-- 
2.26.2


^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 15/16] target/mips: Extract FPU specific definitions to translate.h
@ 2020-12-14 18:37   ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, kvm, Huacai Chen, Laurent Vivier, Jiaxun Yang,
	Philippe Mathieu-Daudé,
	Paolo Bonzini, Aurelien Jarno

Extract FPU specific definitions that can be used by
ISA / ASE / extensions to translate.h header.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/translate.h | 71 +++++++++++++++++++++++++++++++++++++++++
 target/mips/translate.c | 70 ----------------------------------------
 2 files changed, 71 insertions(+), 70 deletions(-)

diff --git a/target/mips/translate.h b/target/mips/translate.h
index a30fbf21ff9..a9eab69249f 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -52,6 +52,77 @@ typedef struct DisasContext {
 /* MIPS major opcodes */
 #define MASK_OP_MAJOR(op)   (op & (0x3F << 26))
 
+#define OPC_CP1 (0x11 << 26)
+
+/* Coprocessor 1 (rs field) */
+#define MASK_CP1(op)                (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
+
+/* Values for the fmt field in FP instructions */
+enum {
+    /* 0 - 15 are reserved */
+    FMT_S = 16,          /* single fp */
+    FMT_D = 17,          /* double fp */
+    FMT_E = 18,          /* extended fp */
+    FMT_Q = 19,          /* quad fp */
+    FMT_W = 20,          /* 32-bit fixed */
+    FMT_L = 21,          /* 64-bit fixed */
+    FMT_PS = 22,         /* paired single fp */
+    /* 23 - 31 are reserved */
+};
+
+enum {
+    OPC_MFC1     = (0x00 << 21) | OPC_CP1,
+    OPC_DMFC1    = (0x01 << 21) | OPC_CP1,
+    OPC_CFC1     = (0x02 << 21) | OPC_CP1,
+    OPC_MFHC1    = (0x03 << 21) | OPC_CP1,
+    OPC_MTC1     = (0x04 << 21) | OPC_CP1,
+    OPC_DMTC1    = (0x05 << 21) | OPC_CP1,
+    OPC_CTC1     = (0x06 << 21) | OPC_CP1,
+    OPC_MTHC1    = (0x07 << 21) | OPC_CP1,
+    OPC_BC1      = (0x08 << 21) | OPC_CP1, /* bc */
+    OPC_BC1ANY2  = (0x09 << 21) | OPC_CP1,
+    OPC_BC1ANY4  = (0x0A << 21) | OPC_CP1,
+    OPC_BZ_V     = (0x0B << 21) | OPC_CP1,
+    OPC_BNZ_V    = (0x0F << 21) | OPC_CP1,
+    OPC_S_FMT    = (FMT_S << 21) | OPC_CP1,
+    OPC_D_FMT    = (FMT_D << 21) | OPC_CP1,
+    OPC_E_FMT    = (FMT_E << 21) | OPC_CP1,
+    OPC_Q_FMT    = (FMT_Q << 21) | OPC_CP1,
+    OPC_W_FMT    = (FMT_W << 21) | OPC_CP1,
+    OPC_L_FMT    = (FMT_L << 21) | OPC_CP1,
+    OPC_PS_FMT   = (FMT_PS << 21) | OPC_CP1,
+    OPC_BC1EQZ   = (0x09 << 21) | OPC_CP1,
+    OPC_BC1NEZ   = (0x0D << 21) | OPC_CP1,
+    OPC_BZ_B     = (0x18 << 21) | OPC_CP1,
+    OPC_BZ_H     = (0x19 << 21) | OPC_CP1,
+    OPC_BZ_W     = (0x1A << 21) | OPC_CP1,
+    OPC_BZ_D     = (0x1B << 21) | OPC_CP1,
+    OPC_BNZ_B    = (0x1C << 21) | OPC_CP1,
+    OPC_BNZ_H    = (0x1D << 21) | OPC_CP1,
+    OPC_BNZ_W    = (0x1E << 21) | OPC_CP1,
+    OPC_BNZ_D    = (0x1F << 21) | OPC_CP1,
+};
+
+#define MASK_CP1_FUNC(op)           (MASK_CP1(op) | (op & 0x3F))
+#define MASK_BC1(op)                (MASK_CP1(op) | (op & (0x3 << 16)))
+
+enum {
+    OPC_BC1F     = (0x00 << 16) | OPC_BC1,
+    OPC_BC1T     = (0x01 << 16) | OPC_BC1,
+    OPC_BC1FL    = (0x02 << 16) | OPC_BC1,
+    OPC_BC1TL    = (0x03 << 16) | OPC_BC1,
+};
+
+enum {
+    OPC_BC1FANY2     = (0x00 << 16) | OPC_BC1ANY2,
+    OPC_BC1TANY2     = (0x01 << 16) | OPC_BC1ANY2,
+};
+
+enum {
+    OPC_BC1FANY4     = (0x00 << 16) | OPC_BC1ANY4,
+    OPC_BC1TANY4     = (0x01 << 16) | OPC_BC1ANY4,
+};
+
 void generate_exception_err(DisasContext *ctx, int excp, int err);
 void generate_exception_end(DisasContext *ctx, int excp);
 void gen_reserved_instruction(DisasContext *ctx);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 08ed542f4d4..cc876019bf7 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -43,7 +43,6 @@ enum {
     OPC_SPECIAL  = (0x00 << 26),
     OPC_REGIMM   = (0x01 << 26),
     OPC_CP0      = (0x10 << 26),
-    OPC_CP1      = (0x11 << 26),
     OPC_CP2      = (0x12 << 26),
     OPC_CP3      = (0x13 << 26),
     OPC_SPECIAL2 = (0x1C << 26),
@@ -996,75 +995,6 @@ enum {
     OPC_WAIT     = 0x20 | OPC_C0,
 };
 
-/* Coprocessor 1 (rs field) */
-#define MASK_CP1(op)                (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
-
-/* Values for the fmt field in FP instructions */
-enum {
-    /* 0 - 15 are reserved */
-    FMT_S = 16,          /* single fp */
-    FMT_D = 17,          /* double fp */
-    FMT_E = 18,          /* extended fp */
-    FMT_Q = 19,          /* quad fp */
-    FMT_W = 20,          /* 32-bit fixed */
-    FMT_L = 21,          /* 64-bit fixed */
-    FMT_PS = 22,         /* paired single fp */
-    /* 23 - 31 are reserved */
-};
-
-enum {
-    OPC_MFC1     = (0x00 << 21) | OPC_CP1,
-    OPC_DMFC1    = (0x01 << 21) | OPC_CP1,
-    OPC_CFC1     = (0x02 << 21) | OPC_CP1,
-    OPC_MFHC1    = (0x03 << 21) | OPC_CP1,
-    OPC_MTC1     = (0x04 << 21) | OPC_CP1,
-    OPC_DMTC1    = (0x05 << 21) | OPC_CP1,
-    OPC_CTC1     = (0x06 << 21) | OPC_CP1,
-    OPC_MTHC1    = (0x07 << 21) | OPC_CP1,
-    OPC_BC1      = (0x08 << 21) | OPC_CP1, /* bc */
-    OPC_BC1ANY2  = (0x09 << 21) | OPC_CP1,
-    OPC_BC1ANY4  = (0x0A << 21) | OPC_CP1,
-    OPC_BZ_V     = (0x0B << 21) | OPC_CP1,
-    OPC_BNZ_V    = (0x0F << 21) | OPC_CP1,
-    OPC_S_FMT    = (FMT_S << 21) | OPC_CP1,
-    OPC_D_FMT    = (FMT_D << 21) | OPC_CP1,
-    OPC_E_FMT    = (FMT_E << 21) | OPC_CP1,
-    OPC_Q_FMT    = (FMT_Q << 21) | OPC_CP1,
-    OPC_W_FMT    = (FMT_W << 21) | OPC_CP1,
-    OPC_L_FMT    = (FMT_L << 21) | OPC_CP1,
-    OPC_PS_FMT   = (FMT_PS << 21) | OPC_CP1,
-    OPC_BC1EQZ   = (0x09 << 21) | OPC_CP1,
-    OPC_BC1NEZ   = (0x0D << 21) | OPC_CP1,
-    OPC_BZ_B     = (0x18 << 21) | OPC_CP1,
-    OPC_BZ_H     = (0x19 << 21) | OPC_CP1,
-    OPC_BZ_W     = (0x1A << 21) | OPC_CP1,
-    OPC_BZ_D     = (0x1B << 21) | OPC_CP1,
-    OPC_BNZ_B    = (0x1C << 21) | OPC_CP1,
-    OPC_BNZ_H    = (0x1D << 21) | OPC_CP1,
-    OPC_BNZ_W    = (0x1E << 21) | OPC_CP1,
-    OPC_BNZ_D    = (0x1F << 21) | OPC_CP1,
-};
-
-#define MASK_CP1_FUNC(op)           (MASK_CP1(op) | (op & 0x3F))
-#define MASK_BC1(op)                (MASK_CP1(op) | (op & (0x3 << 16)))
-
-enum {
-    OPC_BC1F     = (0x00 << 16) | OPC_BC1,
-    OPC_BC1T     = (0x01 << 16) | OPC_BC1,
-    OPC_BC1FL    = (0x02 << 16) | OPC_BC1,
-    OPC_BC1TL    = (0x03 << 16) | OPC_BC1,
-};
-
-enum {
-    OPC_BC1FANY2     = (0x00 << 16) | OPC_BC1ANY2,
-    OPC_BC1TANY2     = (0x01 << 16) | OPC_BC1ANY2,
-};
-
-enum {
-    OPC_BC1FANY4     = (0x00 << 16) | OPC_BC1ANY4,
-    OPC_BC1TANY4     = (0x01 << 16) | OPC_BC1ANY4,
-};
-
 #define MASK_CP2(op)                (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
 
 enum {
-- 
2.26.2



^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 16/16] target/mips: Only build TCG code when CONFIG_TCG is set
  2020-12-14 18:37 ` Philippe Mathieu-Daudé
@ 2020-12-14 18:37   ` Philippe Mathieu-Daudé
  -1 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: kvm, Aurelien Jarno, Huacai Chen, Aleksandar Rikalo, Jiaxun Yang,
	Laurent Vivier, Paolo Bonzini, Philippe Mathieu-Daudé,
	Richard Henderson

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201206233949.3783184-20-f4bug@amsat.org>
---
 target/mips/meson.build | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/target/mips/meson.build b/target/mips/meson.build
index 5a49951c6d7..596eb1aeeb3 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -1,9 +1,11 @@
 mips_ss = ss.source_set()
 mips_ss.add(files(
   'cpu.c',
+  'gdbstub.c',
+))
+mips_ss.add(when: 'CONFIG_TCG', if_true: files(
   'dsp_helper.c',
   'fpu_helper.c',
-  'gdbstub.c',
   'lmmi_helper.c',
   'msa_helper.c',
   'op_helper.c',
@@ -15,11 +17,13 @@
 mips_softmmu_ss = ss.source_set()
 mips_softmmu_ss.add(files(
   'addr.c',
-  'cp0_helper.c',
   'cp0_timer.c',
   'machine.c',
   'mips-semi.c',
 ))
+mips_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files(
+  'cp0_helper.c',
+))
 
 target_arch += {'mips': mips_ss}
 target_softmmu_arch += {'mips': mips_softmmu_ss}
-- 
2.26.2


^ permalink raw reply	[flat|nested] 47+ messages in thread

* [PATCH v2 16/16] target/mips: Only build TCG code when CONFIG_TCG is set
@ 2020-12-14 18:37   ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 18:37 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, kvm, Huacai Chen, Richard Henderson,
	Laurent Vivier, Jiaxun Yang, Philippe Mathieu-Daudé,
	Paolo Bonzini, Aurelien Jarno

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201206233949.3783184-20-f4bug@amsat.org>
---
 target/mips/meson.build | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/target/mips/meson.build b/target/mips/meson.build
index 5a49951c6d7..596eb1aeeb3 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -1,9 +1,11 @@
 mips_ss = ss.source_set()
 mips_ss.add(files(
   'cpu.c',
+  'gdbstub.c',
+))
+mips_ss.add(when: 'CONFIG_TCG', if_true: files(
   'dsp_helper.c',
   'fpu_helper.c',
-  'gdbstub.c',
   'lmmi_helper.c',
   'msa_helper.c',
   'op_helper.c',
@@ -15,11 +17,13 @@
 mips_softmmu_ss = ss.source_set()
 mips_softmmu_ss.add(files(
   'addr.c',
-  'cp0_helper.c',
   'cp0_timer.c',
   'machine.c',
   'mips-semi.c',
 ))
+mips_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files(
+  'cp0_helper.c',
+))
 
 target_arch += {'mips': mips_ss}
 target_softmmu_arch += {'mips': mips_softmmu_ss}
-- 
2.26.2



^ permalink raw reply	[flat|nested] 47+ messages in thread

* Re: [PATCH v2 01/16] target/mips: Inline cpu_state_reset() in mips_cpu_reset()
  2020-12-14 18:37   ` Philippe Mathieu-Daudé
  (?)
@ 2020-12-15 14:04   ` Richard Henderson
  -1 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2020-12-15 14:04 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel
  Cc: Aleksandar Rikalo, kvm, Huacai Chen, Laurent Vivier, Jiaxun Yang,
	Paolo Bonzini, Aurelien Jarno

On 12/14/20 12:37 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/cpu.c | 26 +++++++++-----------------
>  1 file changed, 9 insertions(+), 17 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

^ permalink raw reply	[flat|nested] 47+ messages in thread

* Re: [PATCH v2 03/16] target/mips: Add !CONFIG_USER_ONLY comment after #endif
  2020-12-14 18:37   ` Philippe Mathieu-Daudé
  (?)
@ 2020-12-15 14:05   ` Richard Henderson
  -1 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2020-12-15 14:05 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel
  Cc: Aleksandar Rikalo, kvm, Huacai Chen, Laurent Vivier, Jiaxun Yang,
	Paolo Bonzini, Aurelien Jarno

On 12/14/20 12:37 PM, Philippe Mathieu-Daudé wrote:
> To help understand ifdef'ry, add comment after #endif.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/helper.c | 13 ++++++++-----
>  1 file changed, 8 insertions(+), 5 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


^ permalink raw reply	[flat|nested] 47+ messages in thread

* Re: [PATCH v2 04/16] target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs
  2020-12-14 18:37   ` Philippe Mathieu-Daudé
  (?)
@ 2020-12-15 14:05   ` Richard Henderson
  -1 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2020-12-15 14:05 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel
  Cc: Aleksandar Rikalo, kvm, Huacai Chen, Laurent Vivier, Jiaxun Yang,
	Paolo Bonzini, Aurelien Jarno

On 12/14/20 12:37 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/helper.c | 2 --
>  1 file changed, 2 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


^ permalink raw reply	[flat|nested] 47+ messages in thread

* Re: [PATCH v2 05/16] target/mips: Extract common helpers from helper.c to common_helper.c
  2020-12-14 18:37   ` Philippe Mathieu-Daudé
  (?)
@ 2020-12-15 14:07   ` Richard Henderson
  2020-12-15 18:25     ` Philippe Mathieu-Daudé
  -1 siblings, 1 reply; 47+ messages in thread
From: Richard Henderson @ 2020-12-15 14:07 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel
  Cc: Aleksandar Rikalo, kvm, Huacai Chen, Laurent Vivier, Jiaxun Yang,
	Paolo Bonzini, Aurelien Jarno

On 12/14/20 12:37 PM, Philippe Mathieu-Daudé wrote:
> The rest of helper.c is TLB related. Extract the non TLB
> specific functions to a new file, so we can rename helper.c
> as tlb_helper.c in the next commit.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/internal.h |   2 +
>  target/mips/cpu.c      | 215 +++++++++++++++++++++++++++++++++++++++--
>  target/mips/helper.c   | 201 --------------------------------------
>  3 files changed, 211 insertions(+), 207 deletions(-)

Subject and comment need updating for cpu.c.  Otherwise,

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


^ permalink raw reply	[flat|nested] 47+ messages in thread

* Re: [PATCH v2 09/16] target/mips: Rename translate_init.c as cpu-defs.c
  2020-12-14 18:37   ` Philippe Mathieu-Daudé
  (?)
@ 2020-12-15 14:07   ` Richard Henderson
  -1 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2020-12-15 14:07 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel
  Cc: Aleksandar Rikalo, kvm, Huacai Chen, Laurent Vivier, Jiaxun Yang,
	Paolo Bonzini, Aurelien Jarno

On 12/14/20 12:37 PM, Philippe Mathieu-Daudé wrote:
> This file is not TCG specific, contains CPU definitions
> and is consumed by cpu.c. Rename it as such.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/cpu.c                                    | 2 +-
>  target/mips/{translate_init.c.inc => cpu-defs.c.inc} | 0
>  2 files changed, 1 insertion(+), 1 deletion(-)
>  rename target/mips/{translate_init.c.inc => cpu-defs.c.inc} (100%)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


^ permalink raw reply	[flat|nested] 47+ messages in thread

* Re: [PATCH v2 10/16] target/mips: Replace gen_exception_err(err=0) by gen_exception_end()
  2020-12-14 18:37   ` Philippe Mathieu-Daudé
  (?)
@ 2020-12-15 14:08   ` Richard Henderson
  -1 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2020-12-15 14:08 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel
  Cc: Aleksandar Rikalo, kvm, Huacai Chen, Laurent Vivier, Jiaxun Yang,
	Paolo Bonzini, Aurelien Jarno

On 12/14/20 12:37 PM, Philippe Mathieu-Daudé wrote:
> generate_exception_err(err=0) is simply generate_exception_end().
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/translate.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


^ permalink raw reply	[flat|nested] 47+ messages in thread

* Re: [PATCH v2 11/16] target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction
  2020-12-14 18:37 ` [PATCH v2 11/16] target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction Philippe Mathieu-Daudé
@ 2020-12-15 14:09   ` Richard Henderson
  0 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2020-12-15 14:09 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel
  Cc: Aleksandar Rikalo, kvm, Huacai Chen, Laurent Vivier, Jiaxun Yang,
	Paolo Bonzini, Aurelien Jarno

On 12/14/20 12:37 PM, Philippe Mathieu-Daudé wrote:
> gen_reserved_instruction() is easier to read than
> generate_exception_end(ctx, EXCP_RI), replace it.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/translate.c | 724 ++++++++++++++++++++--------------------
>  1 file changed, 362 insertions(+), 362 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


^ permalink raw reply	[flat|nested] 47+ messages in thread

* Re: [PATCH v2 14/16] target/mips: Declare generic FPU functions in 'translate.h'
  2020-12-14 18:37   ` Philippe Mathieu-Daudé
  (?)
@ 2020-12-15 14:13   ` Richard Henderson
  -1 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2020-12-15 14:13 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel
  Cc: Aleksandar Rikalo, kvm, Huacai Chen, Laurent Vivier, Jiaxun Yang,
	Paolo Bonzini, Aurelien Jarno

On 12/14/20 12:37 PM, Philippe Mathieu-Daudé wrote:
> Some FPU translation functions / registers can be used by
> ISA / ASE / extensions out of the big translate.c file.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/translate.h |  7 +++++++
>  target/mips/translate.c | 12 ++++++------
>  2 files changed, 13 insertions(+), 6 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


^ permalink raw reply	[flat|nested] 47+ messages in thread

* Re: [PATCH v2 15/16] target/mips: Extract FPU specific definitions to translate.h
  2020-12-14 18:37   ` Philippe Mathieu-Daudé
  (?)
@ 2020-12-15 14:14   ` Richard Henderson
  -1 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2020-12-15 14:14 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, qemu-devel
  Cc: Aleksandar Rikalo, kvm, Huacai Chen, Laurent Vivier, Jiaxun Yang,
	Paolo Bonzini, Aurelien Jarno

On 12/14/20 12:37 PM, Philippe Mathieu-Daudé wrote:
> Extract FPU specific definitions that can be used by
> ISA / ASE / extensions to translate.h header.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/translate.h | 71 +++++++++++++++++++++++++++++++++++++++++
>  target/mips/translate.c | 70 ----------------------------------------
>  2 files changed, 71 insertions(+), 70 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


^ permalink raw reply	[flat|nested] 47+ messages in thread

* Re: [PATCH v2 00/16] target/mips: Boring code reordering + add "translate.h"
  2020-12-14 18:37 ` Philippe Mathieu-Daudé
@ 2020-12-15 14:24   ` no-reply
  -1 siblings, 0 replies; 47+ messages in thread
From: no-reply @ 2020-12-15 14:24 UTC (permalink / raw)
  To: f4bug
  Cc: qemu-devel, kvm, aurelien, chenhuacai, aleksandar.rikalo,
	jiaxun.yang, laurent, pbonzini, f4bug

Patchew URL: https://patchew.org/QEMU/20201214183739.500368-1-f4bug@amsat.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20201214183739.500368-1-f4bug@amsat.org
Subject: [PATCH v2 00/16] target/mips: Boring code reordering + add "translate.h"

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]      patchew/20201204081209.360524-1-ganqixin@huawei.com -> patchew/20201204081209.360524-1-ganqixin@huawei.com
 * [new tag]         patchew/20201214183739.500368-1-f4bug@amsat.org -> patchew/20201214183739.500368-1-f4bug@amsat.org
Switched to a new branch 'test'
b698b2c target/mips: Only build TCG code when CONFIG_TCG is set
2b7ceb2 target/mips: Extract FPU specific definitions to translate.h
c8fb9ca target/mips: Declare generic FPU functions in 'translate.h'
9c72d0c target/mips/translate: Add declarations for generic code
d8f6d1d target/mips/translate: Extract DisasContext structure
e96a937 target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction
bffae20 target/mips: Replace gen_exception_err(err=0) by gen_exception_end()
7319775 target/mips: Rename translate_init.c as cpu-defs.c
b25602b target/mips: Move mmu_init() functions to tlb_helper.c
6219caf target/mips: Fix code style for checkpatch.pl
5be87c5 target/mips: Rename helper.c as tlb_helper.c
051e87c target/mips: Extract common helpers from helper.c to common_helper.c
d10b7c7 target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs
8a5a0b7 target/mips: Add !CONFIG_USER_ONLY comment after #endif
a129631 target/mips: Extract FPU helpers to 'fpu_helper.h'
02da990 target/mips: Inline cpu_state_reset() in mips_cpu_reset()

=== OUTPUT BEGIN ===
1/16 Checking commit 02da9907b334 (target/mips: Inline cpu_state_reset() in mips_cpu_reset())
2/16 Checking commit a129631d782b (target/mips: Extract FPU helpers to 'fpu_helper.h')
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42: 
new file mode 100644

total: 0 errors, 1 warnings, 193 lines checked

Patch 2/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/16 Checking commit 8a5a0b7f9c26 (target/mips: Add !CONFIG_USER_ONLY comment after #endif)
4/16 Checking commit d10b7c71feb1 (target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs)
5/16 Checking commit 051e87cd7a13 (target/mips: Extract common helpers from helper.c to common_helper.c)
ERROR: space prohibited after that '&' (ctx:WxW)
#41: FILE: target/mips/cpu.c:53:
+    cu = (v >> CP0St_CU0) & 0xf;
                           ^

ERROR: space prohibited after that '&' (ctx:WxW)
#42: FILE: target/mips/cpu.c:54:
+    mx = (v >> CP0St_MX) & 0x1;
                          ^

ERROR: space prohibited after that '&' (ctx:WxW)
#43: FILE: target/mips/cpu.c:55:
+    ksu = (v >> CP0St_KSU) & 0x3;
                            ^

ERROR: space prohibited after that '&' (ctx:WxW)
#70: FILE: target/mips/cpu.c:82:
+        uint32_t ksux = (1 << CP0St_KX) & val;
                                         ^

ERROR: space prohibited after that '&' (ctx:WxW)
#78: FILE: target/mips/cpu.c:90:
+        mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
                                                        ^

ERROR: space prohibited after that '&' (ctx:WxW)
#105: FILE: target/mips/cpu.c:117:
+        mask &= ~((1 << CP0Ca_WP) & val);
                                   ^

ERROR: space prohibited after that '&' (ctx:WxW)
#110: FILE: target/mips/cpu.c:122:
+    if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
                                ^

ERROR: space prohibited after that '&' (ctx:WxW)
#120: FILE: target/mips/cpu.c:132:
+        if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
                                    ^

total: 8 errors, 0 warnings, 433 lines checked

Patch 5/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

6/16 Checking commit 5be87c54eeb1 (target/mips: Rename helper.c as tlb_helper.c)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#36: 
rename from target/mips/helper.c

total: 0 errors, 1 warnings, 17 lines checked

Patch 6/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
7/16 Checking commit 6219caf94f98 (target/mips: Fix code style for checkpatch.pl)
8/16 Checking commit b25602b6f0ef (target/mips: Move mmu_init() functions to tlb_helper.c)
9/16 Checking commit 73197755e834 (target/mips: Rename translate_init.c as cpu-defs.c)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#18: 
rename from target/mips/translate_init.c.inc

total: 0 errors, 1 warnings, 8 lines checked

Patch 9/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/16 Checking commit bffae20e0c6f (target/mips: Replace gen_exception_err(err=0) by gen_exception_end())
11/16 Checking commit e96a9374e116 (target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction)
12/16 Checking commit d8f6d1d52d0d (target/mips/translate: Extract DisasContext structure)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#76: 
new file mode 100644

total: 0 errors, 1 warnings, 100 lines checked

Patch 12/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/16 Checking commit 9c72d0c372dd (target/mips/translate: Add declarations for generic code)
14/16 Checking commit c8fb9ca67251 (target/mips: Declare generic FPU functions in 'translate.h')
15/16 Checking commit 2b7ceb2fc467 (target/mips: Extract FPU specific definitions to translate.h)
16/16 Checking commit b698b2cbfecf (target/mips: Only build TCG code when CONFIG_TCG is set)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20201214183739.500368-1-f4bug@amsat.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com

^ permalink raw reply	[flat|nested] 47+ messages in thread

* Re: [PATCH v2 00/16] target/mips: Boring code reordering + add "translate.h"
@ 2020-12-15 14:24   ` no-reply
  0 siblings, 0 replies; 47+ messages in thread
From: no-reply @ 2020-12-15 14:24 UTC (permalink / raw)
  To: f4bug
  Cc: aleksandar.rikalo, kvm, chenhuacai, qemu-devel, jiaxun.yang,
	laurent, pbonzini, aurelien, f4bug

Patchew URL: https://patchew.org/QEMU/20201214183739.500368-1-f4bug@amsat.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20201214183739.500368-1-f4bug@amsat.org
Subject: [PATCH v2 00/16] target/mips: Boring code reordering + add "translate.h"

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]      patchew/20201204081209.360524-1-ganqixin@huawei.com -> patchew/20201204081209.360524-1-ganqixin@huawei.com
 * [new tag]         patchew/20201214183739.500368-1-f4bug@amsat.org -> patchew/20201214183739.500368-1-f4bug@amsat.org
Switched to a new branch 'test'
b698b2c target/mips: Only build TCG code when CONFIG_TCG is set
2b7ceb2 target/mips: Extract FPU specific definitions to translate.h
c8fb9ca target/mips: Declare generic FPU functions in 'translate.h'
9c72d0c target/mips/translate: Add declarations for generic code
d8f6d1d target/mips/translate: Extract DisasContext structure
e96a937 target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction
bffae20 target/mips: Replace gen_exception_err(err=0) by gen_exception_end()
7319775 target/mips: Rename translate_init.c as cpu-defs.c
b25602b target/mips: Move mmu_init() functions to tlb_helper.c
6219caf target/mips: Fix code style for checkpatch.pl
5be87c5 target/mips: Rename helper.c as tlb_helper.c
051e87c target/mips: Extract common helpers from helper.c to common_helper.c
d10b7c7 target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs
8a5a0b7 target/mips: Add !CONFIG_USER_ONLY comment after #endif
a129631 target/mips: Extract FPU helpers to 'fpu_helper.h'
02da990 target/mips: Inline cpu_state_reset() in mips_cpu_reset()

=== OUTPUT BEGIN ===
1/16 Checking commit 02da9907b334 (target/mips: Inline cpu_state_reset() in mips_cpu_reset())
2/16 Checking commit a129631d782b (target/mips: Extract FPU helpers to 'fpu_helper.h')
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42: 
new file mode 100644

total: 0 errors, 1 warnings, 193 lines checked

Patch 2/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/16 Checking commit 8a5a0b7f9c26 (target/mips: Add !CONFIG_USER_ONLY comment after #endif)
4/16 Checking commit d10b7c71feb1 (target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs)
5/16 Checking commit 051e87cd7a13 (target/mips: Extract common helpers from helper.c to common_helper.c)
ERROR: space prohibited after that '&' (ctx:WxW)
#41: FILE: target/mips/cpu.c:53:
+    cu = (v >> CP0St_CU0) & 0xf;
                           ^

ERROR: space prohibited after that '&' (ctx:WxW)
#42: FILE: target/mips/cpu.c:54:
+    mx = (v >> CP0St_MX) & 0x1;
                          ^

ERROR: space prohibited after that '&' (ctx:WxW)
#43: FILE: target/mips/cpu.c:55:
+    ksu = (v >> CP0St_KSU) & 0x3;
                            ^

ERROR: space prohibited after that '&' (ctx:WxW)
#70: FILE: target/mips/cpu.c:82:
+        uint32_t ksux = (1 << CP0St_KX) & val;
                                         ^

ERROR: space prohibited after that '&' (ctx:WxW)
#78: FILE: target/mips/cpu.c:90:
+        mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
                                                        ^

ERROR: space prohibited after that '&' (ctx:WxW)
#105: FILE: target/mips/cpu.c:117:
+        mask &= ~((1 << CP0Ca_WP) & val);
                                   ^

ERROR: space prohibited after that '&' (ctx:WxW)
#110: FILE: target/mips/cpu.c:122:
+    if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
                                ^

ERROR: space prohibited after that '&' (ctx:WxW)
#120: FILE: target/mips/cpu.c:132:
+        if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
                                    ^

total: 8 errors, 0 warnings, 433 lines checked

Patch 5/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

6/16 Checking commit 5be87c54eeb1 (target/mips: Rename helper.c as tlb_helper.c)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#36: 
rename from target/mips/helper.c

total: 0 errors, 1 warnings, 17 lines checked

Patch 6/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
7/16 Checking commit 6219caf94f98 (target/mips: Fix code style for checkpatch.pl)
8/16 Checking commit b25602b6f0ef (target/mips: Move mmu_init() functions to tlb_helper.c)
9/16 Checking commit 73197755e834 (target/mips: Rename translate_init.c as cpu-defs.c)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#18: 
rename from target/mips/translate_init.c.inc

total: 0 errors, 1 warnings, 8 lines checked

Patch 9/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/16 Checking commit bffae20e0c6f (target/mips: Replace gen_exception_err(err=0) by gen_exception_end())
11/16 Checking commit e96a9374e116 (target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction)
12/16 Checking commit d8f6d1d52d0d (target/mips/translate: Extract DisasContext structure)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#76: 
new file mode 100644

total: 0 errors, 1 warnings, 100 lines checked

Patch 12/16 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/16 Checking commit 9c72d0c372dd (target/mips/translate: Add declarations for generic code)
14/16 Checking commit c8fb9ca67251 (target/mips: Declare generic FPU functions in 'translate.h')
15/16 Checking commit 2b7ceb2fc467 (target/mips: Extract FPU specific definitions to translate.h)
16/16 Checking commit b698b2cbfecf (target/mips: Only build TCG code when CONFIG_TCG is set)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20201214183739.500368-1-f4bug@amsat.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com

^ permalink raw reply	[flat|nested] 47+ messages in thread

* Re: [PATCH v2 05/16] target/mips: Extract common helpers from helper.c to common_helper.c
  2020-12-15 14:07   ` Richard Henderson
@ 2020-12-15 18:25     ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-15 18:25 UTC (permalink / raw)
  To: Richard Henderson, qemu-devel
  Cc: Aleksandar Rikalo, kvm, Huacai Chen, Laurent Vivier, Jiaxun Yang,
	Paolo Bonzini, Aurelien Jarno

On 12/15/20 3:07 PM, Richard Henderson wrote:
> On 12/14/20 12:37 PM, Philippe Mathieu-Daudé wrote:
>> The rest of helper.c is TLB related. Extract the non TLB
>> specific functions to a new file, so we can rename helper.c
>> as tlb_helper.c in the next commit.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> ---
>>  target/mips/internal.h |   2 +
>>  target/mips/cpu.c      | 215 +++++++++++++++++++++++++++++++++++++++--
>>  target/mips/helper.c   | 201 --------------------------------------
>>  3 files changed, 211 insertions(+), 207 deletions(-)
> 
> Subject and comment need updating for cpu.c.  Otherwise,
> 
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Oops, fixed as:

  target/mips: Move common helpers from helper.c to cpu.c

  The rest of helper.c is TLB related. Extract the non TLB
  specific functions to cpu.c, so we can rename helper.c as
  tlb_helper.c in the next commit.

Thanks!

Phil.

^ permalink raw reply	[flat|nested] 47+ messages in thread

* Re: [PATCH v2 00/16] target/mips: Boring code reordering + add "translate.h"
  2020-12-15 14:24   ` no-reply
@ 2020-12-15 19:00     ` Philippe Mathieu-Daudé
  -1 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-15 19:00 UTC (permalink / raw)
  To: qemu-devel, no-reply
  Cc: aleksandar.rikalo, kvm, chenhuacai, jiaxun.yang, laurent,
	pbonzini, aurelien

On 12/15/20 3:24 PM, no-reply@patchew.org wrote:
> Patchew URL: https://patchew.org/QEMU/20201214183739.500368-1-f4bug@amsat.org/
> 
> 
> === OUTPUT BEGIN ===
> 1/16 Checking commit 02da9907b334 (target/mips: Inline cpu_state_reset() in mips_cpu_reset())
> 2/16 Checking commit a129631d782b (target/mips: Extract FPU helpers to 'fpu_helper.h')
> WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
> #42: 
> new file mode 100644
> 
> total: 0 errors, 1 warnings, 193 lines checked
> 
> Patch 2/16 has style problems, please review.  If any of these errors
> are false positives report them to the maintainer, see
> CHECKPATCH in MAINTAINERS.
> 3/16 Checking commit 8a5a0b7f9c26 (target/mips: Add !CONFIG_USER_ONLY comment after #endif)
> 4/16 Checking commit d10b7c71feb1 (target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs)
> 5/16 Checking commit 051e87cd7a13 (target/mips: Extract common helpers from helper.c to common_helper.c)
> ERROR: space prohibited after that '&' (ctx:WxW)
> #41: FILE: target/mips/cpu.c:53:
> +    cu = (v >> CP0St_CU0) & 0xf;
>                            ^
> 
> ERROR: space prohibited after that '&' (ctx:WxW)
> #42: FILE: target/mips/cpu.c:54:
> +    mx = (v >> CP0St_MX) & 0x1;
>                           ^
> 
> ERROR: space prohibited after that '&' (ctx:WxW)
> #43: FILE: target/mips/cpu.c:55:
> +    ksu = (v >> CP0St_KSU) & 0x3;
>                             ^
> 
> ERROR: space prohibited after that '&' (ctx:WxW)
> #70: FILE: target/mips/cpu.c:82:
> +        uint32_t ksux = (1 << CP0St_KX) & val;
>                                          ^
> 
> ERROR: space prohibited after that '&' (ctx:WxW)
> #78: FILE: target/mips/cpu.c:90:
> +        mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
>                                                         ^
> 
> ERROR: space prohibited after that '&' (ctx:WxW)
> #105: FILE: target/mips/cpu.c:117:
> +        mask &= ~((1 << CP0Ca_WP) & val);
>                                    ^
> 
> ERROR: space prohibited after that '&' (ctx:WxW)
> #110: FILE: target/mips/cpu.c:122:
> +    if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
>                                 ^
> 
> ERROR: space prohibited after that '&' (ctx:WxW)
> #120: FILE: target/mips/cpu.c:132:
> +        if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
>                                     ^
> 
> total: 8 errors, 0 warnings, 433 lines checked
> 
> Patch 5/16 has style problems, please review.  If any of these errors
> are false positives report them to the maintainer, see
> CHECKPATCH in MAINTAINERS.

All pre-existing issues (code moved).

^ permalink raw reply	[flat|nested] 47+ messages in thread

* Re: [PATCH v2 00/16] target/mips: Boring code reordering + add "translate.h"
@ 2020-12-15 19:00     ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-15 19:00 UTC (permalink / raw)
  To: qemu-devel, no-reply
  Cc: aleksandar.rikalo, kvm, chenhuacai, laurent, jiaxun.yang,
	pbonzini, aurelien

On 12/15/20 3:24 PM, no-reply@patchew.org wrote:
> Patchew URL: https://patchew.org/QEMU/20201214183739.500368-1-f4bug@amsat.org/
> 
> 
> === OUTPUT BEGIN ===
> 1/16 Checking commit 02da9907b334 (target/mips: Inline cpu_state_reset() in mips_cpu_reset())
> 2/16 Checking commit a129631d782b (target/mips: Extract FPU helpers to 'fpu_helper.h')
> WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
> #42: 
> new file mode 100644
> 
> total: 0 errors, 1 warnings, 193 lines checked
> 
> Patch 2/16 has style problems, please review.  If any of these errors
> are false positives report them to the maintainer, see
> CHECKPATCH in MAINTAINERS.
> 3/16 Checking commit 8a5a0b7f9c26 (target/mips: Add !CONFIG_USER_ONLY comment after #endif)
> 4/16 Checking commit d10b7c71feb1 (target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs)
> 5/16 Checking commit 051e87cd7a13 (target/mips: Extract common helpers from helper.c to common_helper.c)
> ERROR: space prohibited after that '&' (ctx:WxW)
> #41: FILE: target/mips/cpu.c:53:
> +    cu = (v >> CP0St_CU0) & 0xf;
>                            ^
> 
> ERROR: space prohibited after that '&' (ctx:WxW)
> #42: FILE: target/mips/cpu.c:54:
> +    mx = (v >> CP0St_MX) & 0x1;
>                           ^
> 
> ERROR: space prohibited after that '&' (ctx:WxW)
> #43: FILE: target/mips/cpu.c:55:
> +    ksu = (v >> CP0St_KSU) & 0x3;
>                             ^
> 
> ERROR: space prohibited after that '&' (ctx:WxW)
> #70: FILE: target/mips/cpu.c:82:
> +        uint32_t ksux = (1 << CP0St_KX) & val;
>                                          ^
> 
> ERROR: space prohibited after that '&' (ctx:WxW)
> #78: FILE: target/mips/cpu.c:90:
> +        mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
>                                                         ^
> 
> ERROR: space prohibited after that '&' (ctx:WxW)
> #105: FILE: target/mips/cpu.c:117:
> +        mask &= ~((1 << CP0Ca_WP) & val);
>                                    ^
> 
> ERROR: space prohibited after that '&' (ctx:WxW)
> #110: FILE: target/mips/cpu.c:122:
> +    if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
>                                 ^
> 
> ERROR: space prohibited after that '&' (ctx:WxW)
> #120: FILE: target/mips/cpu.c:132:
> +        if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
>                                     ^
> 
> total: 8 errors, 0 warnings, 433 lines checked
> 
> Patch 5/16 has style problems, please review.  If any of these errors
> are false positives report them to the maintainer, see
> CHECKPATCH in MAINTAINERS.

All pre-existing issues (code moved).


^ permalink raw reply	[flat|nested] 47+ messages in thread

end of thread, other threads:[~2020-12-15 19:01 UTC | newest]

Thread overview: 47+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-12-14 18:37 [PATCH v2 00/16] target/mips: Boring code reordering + add "translate.h" Philippe Mathieu-Daudé
2020-12-14 18:37 ` Philippe Mathieu-Daudé
2020-12-14 18:37 ` [PATCH v2 01/16] target/mips: Inline cpu_state_reset() in mips_cpu_reset() Philippe Mathieu-Daudé
2020-12-14 18:37   ` Philippe Mathieu-Daudé
2020-12-15 14:04   ` Richard Henderson
2020-12-14 18:37 ` [PATCH v2 02/16] target/mips: Extract FPU helpers to 'fpu_helper.h' Philippe Mathieu-Daudé
2020-12-14 18:37   ` Philippe Mathieu-Daudé
2020-12-14 18:37 ` [PATCH v2 03/16] target/mips: Add !CONFIG_USER_ONLY comment after #endif Philippe Mathieu-Daudé
2020-12-14 18:37   ` Philippe Mathieu-Daudé
2020-12-15 14:05   ` Richard Henderson
2020-12-14 18:37 ` [PATCH v2 04/16] target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs Philippe Mathieu-Daudé
2020-12-14 18:37   ` Philippe Mathieu-Daudé
2020-12-15 14:05   ` Richard Henderson
2020-12-14 18:37 ` [PATCH v2 05/16] target/mips: Extract common helpers from helper.c to common_helper.c Philippe Mathieu-Daudé
2020-12-14 18:37   ` Philippe Mathieu-Daudé
2020-12-15 14:07   ` Richard Henderson
2020-12-15 18:25     ` Philippe Mathieu-Daudé
2020-12-14 18:37 ` [PATCH v2 06/16] target/mips: Rename helper.c as tlb_helper.c Philippe Mathieu-Daudé
2020-12-14 18:37   ` Philippe Mathieu-Daudé
2020-12-14 18:37 ` [PATCH v2 07/16] target/mips: Fix code style for checkpatch.pl Philippe Mathieu-Daudé
2020-12-14 18:37   ` Philippe Mathieu-Daudé
2020-12-14 18:37 ` [PATCH v2 08/16] target/mips: Move mmu_init() functions to tlb_helper.c Philippe Mathieu-Daudé
2020-12-14 18:37   ` Philippe Mathieu-Daudé
2020-12-14 18:37 ` [PATCH v2 09/16] target/mips: Rename translate_init.c as cpu-defs.c Philippe Mathieu-Daudé
2020-12-14 18:37   ` Philippe Mathieu-Daudé
2020-12-15 14:07   ` Richard Henderson
2020-12-14 18:37 ` [PATCH v2 10/16] target/mips: Replace gen_exception_err(err=0) by gen_exception_end() Philippe Mathieu-Daudé
2020-12-14 18:37   ` Philippe Mathieu-Daudé
2020-12-15 14:08   ` Richard Henderson
2020-12-14 18:37 ` [PATCH v2 11/16] target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction Philippe Mathieu-Daudé
2020-12-15 14:09   ` Richard Henderson
2020-12-14 18:37 ` [PATCH v2 12/16] target/mips/translate: Extract DisasContext structure Philippe Mathieu-Daudé
2020-12-14 18:37   ` Philippe Mathieu-Daudé
2020-12-14 18:37 ` [PATCH v2 13/16] target/mips/translate: Add declarations for generic code Philippe Mathieu-Daudé
2020-12-14 18:37   ` Philippe Mathieu-Daudé
2020-12-14 18:37 ` [PATCH v2 14/16] target/mips: Declare generic FPU functions in 'translate.h' Philippe Mathieu-Daudé
2020-12-14 18:37   ` Philippe Mathieu-Daudé
2020-12-15 14:13   ` Richard Henderson
2020-12-14 18:37 ` [PATCH v2 15/16] target/mips: Extract FPU specific definitions to translate.h Philippe Mathieu-Daudé
2020-12-14 18:37   ` Philippe Mathieu-Daudé
2020-12-15 14:14   ` Richard Henderson
2020-12-14 18:37 ` [PATCH v2 16/16] target/mips: Only build TCG code when CONFIG_TCG is set Philippe Mathieu-Daudé
2020-12-14 18:37   ` Philippe Mathieu-Daudé
2020-12-15 14:24 ` [PATCH v2 00/16] target/mips: Boring code reordering + add "translate.h" no-reply
2020-12-15 14:24   ` no-reply
2020-12-15 19:00   ` Philippe Mathieu-Daudé
2020-12-15 19:00     ` Philippe Mathieu-Daudé

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