* [Intel-gfx] [PATCH i-g-t 1/2] i915/gem_exec_params: Assert a 4G object does _not_ fit without 48b
@ 2020-12-15 21:05 Chris Wilson
2020-12-15 21:05 ` [Intel-gfx] [PATCH i-g-t 2/2] i915/gem_softpin: Check full placement control under full-ppgtt Chris Wilson
0 siblings, 1 reply; 4+ messages in thread
From: Chris Wilson @ 2020-12-15 21:05 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev, Chris Wilson
Without opting into 48B addressing, objects are strictly limited to
being placed only the first (4G - 4K). This is to avoid an issue with
stateless 32b addressing being unable to access the last 32b page.
Assert that we do indeed fail to fit in a 4G object without setting the
EXEC_OBJECT_SUPPORTS_48B_ADDRESS flag.
Reported-by: CQ Tang <cq.tang@intel.com>
References:: 48ea1e32c39d ("drm/i915/gen9: Set PIN_ZONE_4G end to 4GB - 1 page")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: CQ Tang <cq.tang@intel.com>
---
tests/i915/gem_exec_params.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/tests/i915/gem_exec_params.c b/tests/i915/gem_exec_params.c
index c405f4eb7..e679c512a 100644
--- a/tests/i915/gem_exec_params.c
+++ b/tests/i915/gem_exec_params.c
@@ -340,7 +340,13 @@ static void test_larger_than_life_batch(int fd)
for_each_engine(e, fd) {
/* Keep the batch_len implicit [0] */
execbuf.flags = eb_ring(e);
- gem_execbuf(fd, &execbuf);
+
+ /* non-48b objects are limited to the low (4G - 4K) */
+ igt_assert_eq(__gem_execbuf(fd, &execbuf), -ENOSPC);
+
+ exec.flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ igt_assert_eq(__gem_execbuf(fd, &execbuf), 0);
+ exec.flags = 0;
}
gem_sync(fd, exec.handle);
--
2.29.2
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^ permalink raw reply related [flat|nested] 4+ messages in thread* [Intel-gfx] [PATCH i-g-t 2/2] i915/gem_softpin: Check full placement control under full-ppgtt
2020-12-15 21:05 [Intel-gfx] [PATCH i-g-t 1/2] i915/gem_exec_params: Assert a 4G object does _not_ fit without 48b Chris Wilson
@ 2020-12-15 21:05 ` Chris Wilson
0 siblings, 0 replies; 4+ messages in thread
From: Chris Wilson @ 2020-12-15 21:05 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev, Chris Wilson
With full-ppgtt, userspacew has complete control over their GTT. Verify
that we can place an object at the very beginning and the very end of
our GTT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/i915/gem_softpin.c | 45 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/tests/i915/gem_softpin.c b/tests/i915/gem_softpin.c
index fcaf8ef30..a530e89d3 100644
--- a/tests/i915/gem_softpin.c
+++ b/tests/i915/gem_softpin.c
@@ -97,6 +97,47 @@ static void test_invalid(int fd)
}
}
+static uint32_t batch_create(int i915, uint64_t *sz)
+{
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ struct drm_i915_gem_create create = {
+ .size = sizeof(bbe),
+ };
+
+ if (igt_ioctl(i915, DRM_IOCTL_I915_GEM_CREATE, &create)) {
+ igt_assert_eq(errno, 0);
+ return 0;
+ }
+
+ gem_write(i915, create.handle, 0, &bbe, sizeof(bbe));
+
+ *sz = create.size;
+ return create.handle;
+}
+
+static void test_zero(int i915)
+{
+ uint64_t sz;
+ struct drm_i915_gem_exec_object2 object = {
+ .handle = batch_create(i915, &sz),
+ .flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS,
+ };
+ struct drm_i915_gem_execbuffer2 execbuf = {
+ .buffers_ptr = to_user_pointer(&object),
+ .buffer_count = 1,
+ };
+
+ /* Under full-ppgtt, we have complete control of the GTT */
+
+ object.offset = 0;
+ gem_execbuf(i915, &execbuf);
+
+ object.offset = gem_aperture_size(i915) - sz;
+ gem_close(i915, object.handle);
+
+ gem_close(i915, object.handle);
+}
+
static void test_softpin(int fd)
{
const uint32_t size = 1024 * 1024;
@@ -559,6 +600,10 @@ igt_main
igt_subtest("invalid")
test_invalid(fd);
+ igt_subtest("zero") {
+ igt_require(gem_uses_full_ppgtt(fd));
+ test_zero(fd);
+ }
igt_subtest("softpin")
test_softpin(fd);
igt_subtest("overlap")
--
2.29.2
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* [Intel-gfx] [PATCH i-g-t 1/2] i915/gem_exec_params: Assert a 4G object does _not_ fit without 48b
@ 2020-12-15 21:06 Chris Wilson
2020-12-15 21:47 ` Tang, CQ
0 siblings, 1 reply; 4+ messages in thread
From: Chris Wilson @ 2020-12-15 21:06 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev, Chris Wilson
Without opting into 48B addressing, objects are strictly limited to
being placed only the first (4G - 4K). This is to avoid an issue with
stateless 32b addressing being unable to access the last 32b page.
Assert that we do indeed fail to fit in a 4G object without setting the
EXEC_OBJECT_SUPPORTS_48B_ADDRESS flag.
Reported-by: CQ Tang <cq.tang@intel.com>
References:: 48ea1e32c39d ("drm/i915/gen9: Set PIN_ZONE_4G end to 4GB - 1 page")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: CQ Tang <cq.tang@intel.com>
---
tests/i915/gem_exec_params.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/tests/i915/gem_exec_params.c b/tests/i915/gem_exec_params.c
index c405f4eb7..e679c512a 100644
--- a/tests/i915/gem_exec_params.c
+++ b/tests/i915/gem_exec_params.c
@@ -340,7 +340,13 @@ static void test_larger_than_life_batch(int fd)
for_each_engine(e, fd) {
/* Keep the batch_len implicit [0] */
execbuf.flags = eb_ring(e);
- gem_execbuf(fd, &execbuf);
+
+ /* non-48b objects are limited to the low (4G - 4K) */
+ igt_assert_eq(__gem_execbuf(fd, &execbuf), -ENOSPC);
+
+ exec.flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ igt_assert_eq(__gem_execbuf(fd, &execbuf), 0);
+ exec.flags = 0;
}
gem_sync(fd, exec.handle);
--
2.29.2
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^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [Intel-gfx] [PATCH i-g-t 1/2] i915/gem_exec_params: Assert a 4G object does _not_ fit without 48b
2020-12-15 21:06 [Intel-gfx] [PATCH i-g-t 1/2] i915/gem_exec_params: Assert a 4G object does _not_ fit without 48b Chris Wilson
@ 2020-12-15 21:47 ` Tang, CQ
0 siblings, 0 replies; 4+ messages in thread
From: Tang, CQ @ 2020-12-15 21:47 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: igt-dev
> -----Original Message-----
> From: Chris Wilson <chris@chris-wilson.co.uk>
> Sent: Tuesday, December 15, 2020 1:07 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: igt-dev@lists.freedesktop.org; Chris Wilson <chris@chris-wilson.co.uk>;
> Tang, CQ <cq.tang@intel.com>
> Subject: [PATCH i-g-t 1/2] i915/gem_exec_params: Assert a 4G object does
> _not_ fit without 48b
>
> Without opting into 48B addressing, objects are strictly limited to being
> placed only the first (4G - 4K). This is to avoid an issue with stateless 32b
> addressing being unable to access the last 32b page.
> Assert that we do indeed fail to fit in a 4G object without setting the
> EXEC_OBJECT_SUPPORTS_48B_ADDRESS flag.
>
> Reported-by: CQ Tang <cq.tang@intel.com>
> References:: 48ea1e32c39d ("drm/i915/gen9: Set PIN_ZONE_4G end to 4GB -
> 1 page")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: CQ Tang <cq.tang@intel.com>
> ---
> tests/i915/gem_exec_params.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/tests/i915/gem_exec_params.c b/tests/i915/gem_exec_params.c
> index c405f4eb7..e679c512a 100644
> --- a/tests/i915/gem_exec_params.c
> +++ b/tests/i915/gem_exec_params.c
> @@ -340,7 +340,13 @@ static void test_larger_than_life_batch(int fd)
> for_each_engine(e, fd) {
> /* Keep the batch_len implicit [0] */
> execbuf.flags = eb_ring(e);
> - gem_execbuf(fd, &execbuf);
> +
> + /* non-48b objects are limited to the low (4G - 4K) */
> + igt_assert_eq(__gem_execbuf(fd, &execbuf), -ENOSPC);
> +
> + exec.flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> + igt_assert_eq(__gem_execbuf(fd, &execbuf), 0);
> + exec.flags = 0;
It is good to test both cases.
Reviewed-by: CQ Tang <cq.tang@intel.com>
> }
>
> gem_sync(fd, exec.handle);
> --
> 2.29.2
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2020-12-15 21:05 [Intel-gfx] [PATCH i-g-t 1/2] i915/gem_exec_params: Assert a 4G object does _not_ fit without 48b Chris Wilson
2020-12-15 21:05 ` [Intel-gfx] [PATCH i-g-t 2/2] i915/gem_softpin: Check full placement control under full-ppgtt Chris Wilson
2020-12-15 21:06 [Intel-gfx] [PATCH i-g-t 1/2] i915/gem_exec_params: Assert a 4G object does _not_ fit without 48b Chris Wilson
2020-12-15 21:47 ` Tang, CQ
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