From: Alexandru Elisei <alexandru.elisei@arm.com> To: drjones@redhat.com, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu Cc: andre.przywara@arm.com, eric.auger@redhat.com, yuzenghui@huawei.com Subject: [kvm-unit-tests PATCH v2 01/12] lib: arm/arm64: gicv3: Add missing barrier when sending IPIs Date: Thu, 17 Dec 2020 14:13:49 +0000 [thread overview] Message-ID: <20201217141400.106137-2-alexandru.elisei@arm.com> (raw) In-Reply-To: <20201217141400.106137-1-alexandru.elisei@arm.com> One common usage for IPIs is for one CPU to write to a shared memory location, send the IPI to kick another CPU, and the receiver to read from the same location. Proper synchronization is needed to make sure that the IPI receiver reads the most recent value and not stale data (for example, the write from the sender CPU might still be in a store buffer). For GICv3, IPIs are generated with a write to the ICC_SGI1R_EL1 register. To make sure the memory stores are observable by other CPUs, we need a wmb() barrier (DSB ST), which waits for stores to complete. From the definition of DSB from ARM DDI 0487F.b, page B2-139: "In addition, no instruction that appears in program order after the DSB instruction can alter any state of the system or perform any part of its functionality until the DSB completes other than: - Being fetched from memory and decoded. - Reading the general-purpose, SIMD and floating-point, Special-purpose, or System registers that are directly or indirectly read without causing side-effects." Similar definition for armv7 (ARM DDI 0406C.d, page A3-150). The DSB instruction is enough to prevent reordering of the GIC register write which comes in program order after the memory access. This also matches what the Linux GICv3 irqchip driver does (commit 21ec30c0ef52 ("irqchip/gic-v3: Use wmb() instead of smb_wmb() in gic_raise_softirq()")). Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> --- lib/arm/gic-v3.c | 6 ++++++ arm/gic.c | 5 +++++ 2 files changed, 11 insertions(+) diff --git a/lib/arm/gic-v3.c b/lib/arm/gic-v3.c index a7e2cb819746..2c067e4e9ba2 100644 --- a/lib/arm/gic-v3.c +++ b/lib/arm/gic-v3.c @@ -77,6 +77,12 @@ void gicv3_ipi_send_mask(int irq, const cpumask_t *dest) assert(irq < 16); + /* + * Ensure stores to Normal memory are visible to other CPUs before + * sending the IPI. + */ + wmb(); + /* * For each cpu in the mask collect its peers, which are also in * the mask, in order to form target lists. diff --git a/arm/gic.c b/arm/gic.c index acb060585fae..fee48f9b4ccb 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -275,6 +275,11 @@ static void gicv3_ipi_send_self(void) static void gicv3_ipi_send_broadcast(void) { + /* + * Ensure stores to Normal memory are visible to other CPUs before + * sending the IPI + */ + wmb(); gicv3_write_sgi1r(1ULL << 40 | IPI_IRQ << 24); isb(); } -- 2.29.2
WARNING: multiple messages have this Message-ID (diff)
From: Alexandru Elisei <alexandru.elisei@arm.com> To: drjones@redhat.com, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu Cc: andre.przywara@arm.com Subject: [kvm-unit-tests PATCH v2 01/12] lib: arm/arm64: gicv3: Add missing barrier when sending IPIs Date: Thu, 17 Dec 2020 14:13:49 +0000 [thread overview] Message-ID: <20201217141400.106137-2-alexandru.elisei@arm.com> (raw) In-Reply-To: <20201217141400.106137-1-alexandru.elisei@arm.com> One common usage for IPIs is for one CPU to write to a shared memory location, send the IPI to kick another CPU, and the receiver to read from the same location. Proper synchronization is needed to make sure that the IPI receiver reads the most recent value and not stale data (for example, the write from the sender CPU might still be in a store buffer). For GICv3, IPIs are generated with a write to the ICC_SGI1R_EL1 register. To make sure the memory stores are observable by other CPUs, we need a wmb() barrier (DSB ST), which waits for stores to complete. From the definition of DSB from ARM DDI 0487F.b, page B2-139: "In addition, no instruction that appears in program order after the DSB instruction can alter any state of the system or perform any part of its functionality until the DSB completes other than: - Being fetched from memory and decoded. - Reading the general-purpose, SIMD and floating-point, Special-purpose, or System registers that are directly or indirectly read without causing side-effects." Similar definition for armv7 (ARM DDI 0406C.d, page A3-150). The DSB instruction is enough to prevent reordering of the GIC register write which comes in program order after the memory access. This also matches what the Linux GICv3 irqchip driver does (commit 21ec30c0ef52 ("irqchip/gic-v3: Use wmb() instead of smb_wmb() in gic_raise_softirq()")). Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> --- lib/arm/gic-v3.c | 6 ++++++ arm/gic.c | 5 +++++ 2 files changed, 11 insertions(+) diff --git a/lib/arm/gic-v3.c b/lib/arm/gic-v3.c index a7e2cb819746..2c067e4e9ba2 100644 --- a/lib/arm/gic-v3.c +++ b/lib/arm/gic-v3.c @@ -77,6 +77,12 @@ void gicv3_ipi_send_mask(int irq, const cpumask_t *dest) assert(irq < 16); + /* + * Ensure stores to Normal memory are visible to other CPUs before + * sending the IPI. + */ + wmb(); + /* * For each cpu in the mask collect its peers, which are also in * the mask, in order to form target lists. diff --git a/arm/gic.c b/arm/gic.c index acb060585fae..fee48f9b4ccb 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -275,6 +275,11 @@ static void gicv3_ipi_send_self(void) static void gicv3_ipi_send_broadcast(void) { + /* + * Ensure stores to Normal memory are visible to other CPUs before + * sending the IPI + */ + wmb(); gicv3_write_sgi1r(1ULL << 40 | IPI_IRQ << 24); isb(); } -- 2.29.2 _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
next prev parent reply other threads:[~2020-12-17 14:15 UTC|newest] Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-12-17 14:13 [kvm-unit-tests PATCH v2 00/12] GIC fixes and improvements Alexandru Elisei 2020-12-17 14:13 ` Alexandru Elisei 2020-12-17 14:13 ` Alexandru Elisei [this message] 2020-12-17 14:13 ` [kvm-unit-tests PATCH v2 01/12] lib: arm/arm64: gicv3: Add missing barrier when sending IPIs Alexandru Elisei 2020-12-18 12:03 ` André Przywara 2020-12-18 12:03 ` André Przywara 2020-12-17 14:13 ` [kvm-unit-tests PATCH v2 02/12] lib: arm/arm64: gicv2: " Alexandru Elisei 2020-12-17 14:13 ` Alexandru Elisei 2020-12-17 14:13 ` [kvm-unit-tests PATCH v2 03/12] arm/arm64: gic: Remove SMP synchronization from ipi_clear_active_handler() Alexandru Elisei 2020-12-17 14:13 ` Alexandru Elisei 2020-12-18 12:04 ` André Przywara 2020-12-18 12:04 ` André Przywara 2020-12-17 14:13 ` [kvm-unit-tests PATCH v2 04/12] arm/arm64: gic: Remove unnecessary synchronization with stats_reset() Alexandru Elisei 2020-12-17 14:13 ` Alexandru Elisei 2020-12-17 14:13 ` [kvm-unit-tests PATCH v2 05/12] arm/arm64: gic: Use correct memory ordering for the IPI test Alexandru Elisei 2020-12-17 14:13 ` Alexandru Elisei 2020-12-18 12:04 ` André Przywara 2020-12-18 12:04 ` André Przywara 2020-12-17 14:13 ` [kvm-unit-tests PATCH v2 06/12] arm/arm64: gic: Check spurious and bad_sender in the active test Alexandru Elisei 2020-12-17 14:13 ` Alexandru Elisei 2020-12-17 14:13 ` [kvm-unit-tests PATCH v2 07/12] arm/arm64: gic: Wait for writes to acked or spurious to complete Alexandru Elisei 2020-12-17 14:13 ` Alexandru Elisei 2020-12-17 14:13 ` [kvm-unit-tests PATCH v2 08/12] arm/arm64: gic: Split check_acked() into two functions Alexandru Elisei 2020-12-17 14:13 ` Alexandru Elisei 2020-12-18 15:52 ` André Przywara 2020-12-18 15:52 ` André Przywara 2021-01-25 17:27 ` Alexandru Elisei 2021-01-25 17:27 ` Alexandru Elisei 2021-01-27 15:10 ` Andre Przywara 2021-01-27 15:10 ` Andre Przywara 2021-01-27 16:00 ` Alexandru Elisei 2021-01-27 16:00 ` Alexandru Elisei 2021-02-16 18:04 ` Andre Przywara 2021-02-16 18:04 ` Andre Przywara 2020-12-17 14:13 ` [kvm-unit-tests PATCH v2 09/12] arm/arm64: gic: Make check_acked() more generic Alexandru Elisei 2020-12-17 14:13 ` Alexandru Elisei 2020-12-18 15:52 ` André Przywara 2020-12-18 15:52 ` André Przywara 2020-12-17 14:13 ` [kvm-unit-tests PATCH v2 10/12] arm64: gic: its-trigger: Don't trigger the LPI while it is pending Alexandru Elisei 2020-12-17 14:13 ` Alexandru Elisei 2020-12-18 18:15 ` André Przywara 2020-12-18 18:15 ` André Przywara 2021-01-25 16:57 ` Alexandru Elisei 2021-01-25 16:57 ` Alexandru Elisei 2020-12-17 14:13 ` [kvm-unit-tests PATCH v2 11/12] lib: arm64: gic-v3-its: Add wmb() barrier before INT command Alexandru Elisei 2020-12-17 14:13 ` Alexandru Elisei 2020-12-18 18:36 ` André Przywara 2020-12-18 18:36 ` André Przywara 2021-01-25 15:16 ` Alexandru Elisei 2021-01-25 15:16 ` Alexandru Elisei 2020-12-17 14:14 ` [kvm-unit-tests PATCH v2 12/12] arm64: gic: Use IPI test checking for the LPI tests Alexandru Elisei 2020-12-17 14:14 ` Alexandru Elisei
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