From: "Alice Guo (OSS)" <alice.guo@oss.nxp.com> To: robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, krzk@kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-imx@nxp.com Subject: [PATCH v8 3/4] arm64: dts: imx8m: add NVMEM provider and consumer to read soc unique ID Date: Fri, 18 Dec 2020 16:37:25 +0800 [thread overview] Message-ID: <20201218083726.16427-3-alice.guo@oss.nxp.com> (raw) In-Reply-To: <20201218083726.16427-1-alice.guo@oss.nxp.com> From: Alice Guo <alice.guo@nxp.com> In order to be able to use NVMEM APIs to read soc unique ID, add the nvmem data cell and name for nvmem-cells to the "soc" node, and add a nvmem node which provides soc unique ID to efuse@30350000. Signed-off-by: Alice Guo <alice.guo@nxp.com> --- Changes for v8: - none Changes for v7: - add Reviewed-by Changes for v6: - leave only the changelog under '---' Changes for v5: - change underscore of device node to hyphen Changes for v4: - delete "stuff" in subject and commit message - add detailed description Changes for v3: - convert register addresses and sizes to hex Changes for v2: - remove the subject prefix "LF-2571-3" arch/arm64/boot/dts/freescale/imx8mm.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/imx8mn.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/imx8mq.dtsi | 6 ++++++ 4 files changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index d457ce815e68..9bee6f1889a4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -261,6 +261,8 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; + nvmem-cells = <&imx8mm_uid>; + nvmem-cell-names = "soc_unique_id"; aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; @@ -518,6 +520,10 @@ #address-cells = <1>; #size-cells = <1>; + imx8mm_uid: unique-id@410 { + reg = <0x4 0x8>; + }; + cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index db50e6e01ac5..b344fdc16534 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -245,6 +245,8 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; + nvmem-cells = <&imx8mn_uid>; + nvmem-cell-names = "soc_unique_id"; aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; @@ -531,6 +533,10 @@ #address-cells = <1>; #size-cells = <1>; + imx8mn_uid: unique-id@410 { + reg = <0x4 0x8>; + }; + cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index ec6ac523ecfc..9401e92f1c84 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -222,6 +222,8 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; + nvmem-cells = <&imx8mp_uid>; + nvmem-cell-names = "soc_unique_id"; aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; @@ -328,6 +330,10 @@ #address-cells = <1>; #size-cells = <1>; + imx8mp_uid: unique-id@420 { + reg = <0x8 0x8>; + }; + cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 9b6d9307e5d7..a2a885f1a07a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -291,6 +291,8 @@ #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; + nvmem-cells = <&imx8mq_uid>; + nvmem-cell-names = "soc_unique_id"; bus@30000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; @@ -555,6 +557,10 @@ #address-cells = <1>; #size-cells = <1>; + imx8mq_uid: soc-uid@410 { + reg = <0x4 0x8>; + }; + cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: "Alice Guo (OSS)" <alice.guo@oss.nxp.com> To: robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, krzk@kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com Subject: [PATCH v8 3/4] arm64: dts: imx8m: add NVMEM provider and consumer to read soc unique ID Date: Fri, 18 Dec 2020 16:37:25 +0800 [thread overview] Message-ID: <20201218083726.16427-3-alice.guo@oss.nxp.com> (raw) In-Reply-To: <20201218083726.16427-1-alice.guo@oss.nxp.com> From: Alice Guo <alice.guo@nxp.com> In order to be able to use NVMEM APIs to read soc unique ID, add the nvmem data cell and name for nvmem-cells to the "soc" node, and add a nvmem node which provides soc unique ID to efuse@30350000. Signed-off-by: Alice Guo <alice.guo@nxp.com> --- Changes for v8: - none Changes for v7: - add Reviewed-by Changes for v6: - leave only the changelog under '---' Changes for v5: - change underscore of device node to hyphen Changes for v4: - delete "stuff" in subject and commit message - add detailed description Changes for v3: - convert register addresses and sizes to hex Changes for v2: - remove the subject prefix "LF-2571-3" arch/arm64/boot/dts/freescale/imx8mm.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/imx8mn.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/imx8mq.dtsi | 6 ++++++ 4 files changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index d457ce815e68..9bee6f1889a4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -261,6 +261,8 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; + nvmem-cells = <&imx8mm_uid>; + nvmem-cell-names = "soc_unique_id"; aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; @@ -518,6 +520,10 @@ #address-cells = <1>; #size-cells = <1>; + imx8mm_uid: unique-id@410 { + reg = <0x4 0x8>; + }; + cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index db50e6e01ac5..b344fdc16534 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -245,6 +245,8 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; + nvmem-cells = <&imx8mn_uid>; + nvmem-cell-names = "soc_unique_id"; aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; @@ -531,6 +533,10 @@ #address-cells = <1>; #size-cells = <1>; + imx8mn_uid: unique-id@410 { + reg = <0x4 0x8>; + }; + cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index ec6ac523ecfc..9401e92f1c84 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -222,6 +222,8 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; + nvmem-cells = <&imx8mp_uid>; + nvmem-cell-names = "soc_unique_id"; aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; @@ -328,6 +330,10 @@ #address-cells = <1>; #size-cells = <1>; + imx8mp_uid: unique-id@420 { + reg = <0x8 0x8>; + }; + cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 9b6d9307e5d7..a2a885f1a07a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -291,6 +291,8 @@ #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; + nvmem-cells = <&imx8mq_uid>; + nvmem-cell-names = "soc_unique_id"; bus@30000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; @@ -555,6 +557,10 @@ #address-cells = <1>; #size-cells = <1>; + imx8mq_uid: soc-uid@410 { + reg = <0x4 0x8>; + }; + cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-12-18 8:39 UTC|newest] Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-12-18 8:37 [PATCH v8 1/4] dt-bindings: soc: imx8m: add DT Binding doc for soc unique ID Alice Guo (OSS) 2020-12-18 8:37 ` Alice Guo (OSS) 2020-12-18 8:37 ` [PATCH v8 2/4] arm64: dts: imx8m: add SoC ID compatible Alice Guo (OSS) 2020-12-18 8:37 ` Alice Guo (OSS) 2020-12-18 8:37 ` Alice Guo (OSS) [this message] 2020-12-18 8:37 ` [PATCH v8 3/4] arm64: dts: imx8m: add NVMEM provider and consumer to read soc unique ID Alice Guo (OSS) 2020-12-19 12:16 ` Krzysztof Kozlowski 2020-12-19 12:16 ` Krzysztof Kozlowski 2020-12-21 3:10 ` Alice Guo (OSS) 2020-12-21 3:10 ` Alice Guo (OSS) 2020-12-21 7:56 ` Krzysztof Kozlowski 2020-12-21 7:56 ` Krzysztof Kozlowski 2020-12-18 8:37 ` [PATCH v8 4/4] soc: imx8m: change to use platform driver Alice Guo (OSS) 2020-12-18 8:37 ` Alice Guo (OSS) 2020-12-19 12:18 ` Krzysztof Kozlowski 2020-12-19 12:18 ` Krzysztof Kozlowski 2020-12-21 2:36 ` Alice Guo (OSS) 2020-12-21 2:36 ` Alice Guo (OSS) 2020-12-18 8:52 ` [PATCH v8 1/4] dt-bindings: soc: imx8m: add DT Binding doc for soc unique ID Krzysztof Kozlowski 2020-12-18 8:52 ` Krzysztof Kozlowski 2020-12-18 9:05 ` Alice Guo (OSS) 2020-12-18 9:05 ` Alice Guo (OSS) 2020-12-18 9:36 ` Krzysztof Kozlowski 2020-12-18 9:36 ` Krzysztof Kozlowski 2020-12-18 10:14 ` Alice Guo (OSS) 2020-12-18 10:14 ` Alice Guo (OSS) 2020-12-18 13:59 ` Rob Herring 2020-12-18 13:59 ` Rob Herring 2020-12-21 9:20 ` Alice Guo (OSS) 2020-12-21 9:20 ` Alice Guo (OSS) 2020-12-21 20:29 ` Rob Herring 2020-12-21 20:29 ` Rob Herring
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