* [PATCH 00/15] tcg/arm: host neon support
@ 2020-12-24 22:44 Richard Henderson
2020-12-24 22:45 ` [PATCH 01/15] tcg/arm: Add host vector framework Richard Henderson
` (14 more replies)
0 siblings, 15 replies; 16+ messages in thread
From: Richard Henderson @ 2020-12-24 22:44 UTC (permalink / raw)
To: qemu-devel
Based-on: 20201217145215.534637-1-richard.henderson@linaro.org
("tcg: Better handling of constants")
Based-on: 20201223060204.576856-1-richard.henderson@linaro.org
("tcg: backend constraints cleanup")
Generate NEON instructions for tcg vector operations.
r~
Richard Henderson (15):
tcg/arm: Add host vector framework
tcg/arm: Implement tcg_out_ld/st for vector types
tcg/arm: Implement tcg_out_mov for vector types
tcg/arm: Implement tcg_out_dup*_vec
tcg: Change parameters for tcg_target_const_match
tcg/arm: Implement minimal vector operations
tcg/arm: Implement andc, orc, abs, neg, not vector operations
tcg/arm: Implement TCG_TARGET_HAS_shi_vec
tcg/arm: Implement TCG_TARGET_HAS_mul_vec
tcg/arm: Implement TCG_TARGET_HAS_sat_vec
tcg/arm: Implement TCG_TARGET_HAS_minmax_vec
tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec
tcg/arm: Implement TCG_TARGET_HAS_shv_vec
tcg/arm: Implement TCG_TARGET_HAS_roti_vec
tcg/arm: Implement TCG_TARGET_HAS_rotv_vec
tcg/arm/tcg-target-conset.h | 10 +
tcg/arm/tcg-target-constr.h | 3 +
tcg/arm/tcg-target.h | 52 +-
tcg/arm/tcg-target.opc.h | 16 +
tcg/tcg.c | 5 +-
tcg/aarch64/tcg-target.c.inc | 5 +-
tcg/arm/tcg-target.c.inc | 956 +++++++++++++++++++++++++++++++++--
tcg/i386/tcg-target.c.inc | 4 +-
tcg/mips/tcg-target.c.inc | 5 +-
tcg/ppc/tcg-target.c.inc | 4 +-
tcg/riscv/tcg-target.c.inc | 4 +-
tcg/s390/tcg-target.c.inc | 5 +-
tcg/sparc/tcg-target.c.inc | 5 +-
tcg/tci/tcg-target.c.inc | 6 +-
14 files changed, 1002 insertions(+), 78 deletions(-)
create mode 100644 tcg/arm/tcg-target.opc.h
--
2.25.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 01/15] tcg/arm: Add host vector framework
2020-12-24 22:44 [PATCH 00/15] tcg/arm: host neon support Richard Henderson
@ 2020-12-24 22:45 ` Richard Henderson
2020-12-24 22:45 ` [PATCH 02/15] tcg/arm: Implement tcg_out_ld/st for vector types Richard Henderson
` (13 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2020-12-24 22:45 UTC (permalink / raw)
To: qemu-devel
Add registers and function stubs. The functionality
is disabled via use_neon_instructions defined to 0.
We must still include results for the mandatory opcodes in
tcg_target_op_def, as all opcodes are checked during tcg init.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target-conset.h | 4 ++
tcg/arm/tcg-target-constr.h | 1 +
tcg/arm/tcg-target.h | 48 ++++++++++++--
tcg/arm/tcg-target.opc.h | 12 ++++
tcg/arm/tcg-target.c.inc | 121 +++++++++++++++++++++++++++++++-----
5 files changed, 163 insertions(+), 23 deletions(-)
create mode 100644 tcg/arm/tcg-target.opc.h
diff --git a/tcg/arm/tcg-target-conset.h b/tcg/arm/tcg-target-conset.h
index 7e972e70e0..dbcae51c4b 100644
--- a/tcg/arm/tcg-target-conset.h
+++ b/tcg/arm/tcg-target-conset.h
@@ -8,11 +8,14 @@ C_O0_I1(r)
C_O0_I2(r, r)
C_O0_I2(r, rIN)
C_O0_I2(s, s)
+C_O0_I2(w, r)
C_O0_I3(s, s, s)
C_O0_I4(r, r, rI, rI)
C_O0_I4(s, s, s, s)
C_O1_I1(r, l)
C_O1_I1(r, r)
+C_O1_I1(w, r)
+C_O1_I1(w, wr)
C_O1_I2(r, 0, rZ)
C_O1_I2(r, l, l)
C_O1_I2(r, r, r)
@@ -21,6 +24,7 @@ C_O1_I2(r, r, rIK)
C_O1_I2(r, r, rIN)
C_O1_I2(r, r, ri)
C_O1_I2(r, rZ, rZ)
+C_O1_I2(w, w, w)
C_O1_I4(r, r, r, rI, rI)
C_O1_I4(r, r, rIN, rIK, 0)
C_O2_I1(r, r, l)
diff --git a/tcg/arm/tcg-target-constr.h b/tcg/arm/tcg-target-constr.h
index 15c5e53406..5f2780decd 100644
--- a/tcg/arm/tcg-target-constr.h
+++ b/tcg/arm/tcg-target-constr.h
@@ -24,6 +24,7 @@
REGS('r', ALL_GENERAL_REGS)
REGS('l', ALL_QLOAD_REGS)
REGS('s', ALL_QSTORE_REGS)
+REGS('w', 0xffff0000u)
CONST('I', TCG_CT_CONST_ARM)
CONST('K', TCG_CT_CONST_INV)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 17e771374d..b40419971e 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -78,19 +78,38 @@ typedef enum {
TCG_REG_R13,
TCG_REG_R14,
TCG_REG_PC,
+
+ TCG_REG_Q0,
+ TCG_REG_Q1,
+ TCG_REG_Q2,
+ TCG_REG_Q3,
+ TCG_REG_Q4,
+ TCG_REG_Q5,
+ TCG_REG_Q6,
+ TCG_REG_Q7,
+ TCG_REG_Q8,
+ TCG_REG_Q9,
+ TCG_REG_Q10,
+ TCG_REG_Q11,
+ TCG_REG_Q12,
+ TCG_REG_Q13,
+ TCG_REG_Q14,
+ TCG_REG_Q15,
+
+ TCG_AREG0 = TCG_REG_R6,
+ TCG_REG_CALL_STACK = TCG_REG_R13,
} TCGReg;
-#define TCG_TARGET_NB_REGS 16
+#define TCG_TARGET_NB_REGS 32
#ifdef __ARM_ARCH_EXT_IDIV__
#define use_idiv_instructions 1
#else
extern bool use_idiv_instructions;
#endif
-
+#define use_neon_instructions 0
/* used for function call generation */
-#define TCG_REG_CALL_STACK TCG_REG_R13
#define TCG_TARGET_STACK_ALIGN 8
#define TCG_TARGET_CALL_ALIGN_ARGS 1
#define TCG_TARGET_CALL_STACK_OFFSET 0
@@ -127,9 +146,26 @@ extern bool use_idiv_instructions;
#define TCG_TARGET_HAS_goto_ptr 1
#define TCG_TARGET_HAS_direct_jump 0
-enum {
- TCG_AREG0 = TCG_REG_R6,
-};
+#define TCG_TARGET_HAS_v64 use_neon_instructions
+#define TCG_TARGET_HAS_v128 use_neon_instructions
+#define TCG_TARGET_HAS_v256 0
+
+#define TCG_TARGET_HAS_andc_vec 0
+#define TCG_TARGET_HAS_orc_vec 0
+#define TCG_TARGET_HAS_not_vec 0
+#define TCG_TARGET_HAS_neg_vec 0
+#define TCG_TARGET_HAS_abs_vec 0
+#define TCG_TARGET_HAS_roti_vec 0
+#define TCG_TARGET_HAS_rots_vec 0
+#define TCG_TARGET_HAS_rotv_vec 0
+#define TCG_TARGET_HAS_shi_vec 0
+#define TCG_TARGET_HAS_shs_vec 0
+#define TCG_TARGET_HAS_shv_vec 0
+#define TCG_TARGET_HAS_mul_vec 0
+#define TCG_TARGET_HAS_sat_vec 0
+#define TCG_TARGET_HAS_minmax_vec 0
+#define TCG_TARGET_HAS_bitsel_vec 0
+#define TCG_TARGET_HAS_cmpsel_vec 0
#define TCG_TARGET_DEFAULT_MO (0)
#define TCG_TARGET_HAS_MEMORY_BSWAP 1
diff --git a/tcg/arm/tcg-target.opc.h b/tcg/arm/tcg-target.opc.h
new file mode 100644
index 0000000000..7a4578e9b4
--- /dev/null
+++ b/tcg/arm/tcg-target.opc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2019 Linaro
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * (at your option) any later version.
+ *
+ * See the COPYING file in the top-level directory for details.
+ *
+ * Target-specific opcodes for host vector expansion. These will be
+ * emitted by tcg_expand_vec_op. For those familiar with GCC internals,
+ * consider these to be UNSPEC with names.
+ */
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 28a31d5339..48966da12f 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -40,22 +40,10 @@ bool use_idiv_instructions;
#ifdef CONFIG_DEBUG_TCG
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
- "%r0",
- "%r1",
- "%r2",
- "%r3",
- "%r4",
- "%r5",
- "%r6",
- "%r7",
- "%r8",
- "%r9",
- "%r10",
- "%r11",
- "%r12",
- "%r13",
- "%r14",
- "%pc",
+ "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
+ "%r8", "%r9", "%r10", "%r11", "%r12", "%sp", "%r14", "%pc",
+ "%q0", "%q1", "%q2", "%q3", "%q4", "%q5", "%q6", "%q7",
+ "%q8", "%q9", "%q10", "%q11", "%q12", "%q13", "%q14", "%q15",
};
#endif
@@ -75,6 +63,23 @@ static const int tcg_target_reg_alloc_order[] = {
TCG_REG_R3,
TCG_REG_R12,
TCG_REG_R14,
+
+ TCG_REG_Q0,
+ TCG_REG_Q1,
+ TCG_REG_Q2,
+ TCG_REG_Q3,
+ TCG_REG_Q4,
+ TCG_REG_Q5,
+ TCG_REG_Q6,
+ TCG_REG_Q7,
+ TCG_REG_Q8,
+ TCG_REG_Q9,
+ TCG_REG_Q10,
+ TCG_REG_Q11,
+ TCG_REG_Q12,
+ TCG_REG_Q13,
+ TCG_REG_Q14,
+ TCG_REG_Q15,
};
static const int tcg_target_call_iarg_regs[4] = {
@@ -85,6 +90,7 @@ static const int tcg_target_call_oarg_regs[2] = {
};
#define TCG_REG_TMP TCG_REG_R12
+#define TCG_VEC_TMP TCG_REG_Q15
enum arm_cond_code_e {
COND_EQ = 0x0,
@@ -2095,6 +2101,22 @@ static int tcg_target_op_def(TCGOpcode op)
case INDEX_op_qemu_st_i64:
return TARGET_LONG_BITS == 32 ? C_O0_I3(s, s, s) : C_O0_I4(s, s, s, s);
+ case INDEX_op_st_vec:
+ return C_O0_I2(w, r);
+ case INDEX_op_ld_vec:
+ case INDEX_op_dupm_vec:
+ return C_O1_I1(w, r);
+ case INDEX_op_dup_vec:
+ return C_O1_I1(w, wr);
+ case INDEX_op_dup2_vec:
+ case INDEX_op_add_vec:
+ case INDEX_op_sub_vec:
+ case INDEX_op_xor_vec:
+ case INDEX_op_or_vec:
+ case INDEX_op_and_vec:
+ case INDEX_op_cmp_vec:
+ return C_O1_I2(w, w, w);
+
default:
g_assert_not_reached();
}
@@ -2104,12 +2126,18 @@ static void tcg_target_init(TCGContext *s)
{
/* Only probe for the platform and capabilities if we havn't already
determined maximum values at compile time. */
-#ifndef use_idiv_instructions
+#if !defined(use_idiv_instructions) || !defined(use_neon_instructions)
{
unsigned long hwcap = qemu_getauxval(AT_HWCAP);
+#ifndef use_idiv_instructions
use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0;
+#endif
+#ifndef use_neon_instructions
+ use_neon_instructions = (hwcap & HWCAP_ARM_NEON) != 0;
+#endif
}
#endif
+
if (__ARM_ARCH < 7) {
const char *pl = (const char *)qemu_getauxval(AT_PLATFORM);
if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') {
@@ -2127,10 +2155,33 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
+ if (use_neon_instructions) {
+ tcg_target_available_regs[TCG_TYPE_V64] = 0xffff0000u;
+ tcg_target_available_regs[TCG_TYPE_V128] = 0xffff0000u;
+
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q0);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q1);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q2);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q3);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q4);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q5);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q6);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q7);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q8);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q9);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q10);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q11);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q12);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q13);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q14);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q15);
+ }
+
s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC);
+ tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP);
}
static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
@@ -2164,6 +2215,42 @@ static inline void tcg_out_movi(TCGContext *s, TCGType type,
tcg_out_movi32(s, COND_AL, ret, arg);
}
+static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
+ TCGReg rd, TCGReg rs)
+{
+ g_assert_not_reached();
+}
+
+static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
+ TCGReg rd, TCGReg base, intptr_t offset)
+{
+ g_assert_not_reached();
+}
+
+static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
+ TCGReg rd, int64_t v64)
+{
+ g_assert_not_reached();
+}
+
+static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+ unsigned vecl, unsigned vece,
+ const TCGArg *args, const int *const_args)
+{
+ g_assert_not_reached();
+}
+
+int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
+{
+ return 0;
+}
+
+void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
+ TCGArg a0, ...)
+{
+ g_assert_not_reached();
+}
+
static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
{
int i;
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 02/15] tcg/arm: Implement tcg_out_ld/st for vector types
2020-12-24 22:44 [PATCH 00/15] tcg/arm: host neon support Richard Henderson
2020-12-24 22:45 ` [PATCH 01/15] tcg/arm: Add host vector framework Richard Henderson
@ 2020-12-24 22:45 ` Richard Henderson
2020-12-24 22:45 ` [PATCH 03/15] tcg/arm: Implement tcg_out_mov " Richard Henderson
` (12 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2020-12-24 22:45 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target.c.inc | 70 ++++++++++++++++++++++++++++++++++++----
1 file changed, 64 insertions(+), 6 deletions(-)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 48966da12f..7122d5f390 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -175,6 +175,9 @@ typedef enum {
INSN_NOP_v6k = 0xe320f000,
/* Otherwise the assembler uses mov r0,r0 */
INSN_NOP_v4 = (COND_AL << 28) | ARITH_MOV,
+
+ INSN_VLD1 = 0xf4200000, /* VLD1 (multiple single elements) */
+ INSN_VST1 = 0xf4000000, /* VST1 (multiple single elements) */
} ARMInsn;
#define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4)
@@ -1073,6 +1076,33 @@ static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args,
}
}
+/*
+ * Note that TCGReg references Q-registers.
+ * Q-regno = 2 * D-regno, so shift left by 1 whlie inserting.
+ */
+static uint32_t encode_vd(TCGReg rd)
+{
+ tcg_debug_assert(rd >= TCG_REG_Q0);
+ return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13);
+}
+
+static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
+ TCGReg rd, TCGReg rn, int offset)
+{
+ if (offset != 0) {
+ if (check_fit_imm(offset) || check_fit_imm(-offset)) {
+ tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB,
+ TCG_REG_TMP, rn, offset, true);
+ } else {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset);
+ tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
+ TCG_REG_TMP, TCG_REG_TMP, rn, 0);
+ }
+ rn = TCG_REG_TMP;
+ }
+ tcg_out32(s, insn | (rn << 16) | encode_vd(rd) | 0xf);
+}
+
#ifdef CONFIG_SOFTMMU
#include "../tcg-ldst.c.inc"
@@ -2184,16 +2214,44 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP);
}
-static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
- TCGReg arg1, intptr_t arg2)
+static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
+ TCGReg arg1, intptr_t arg2)
{
- tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
+ switch (type) {
+ case TCG_TYPE_I32:
+ tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
+ return;
+ case TCG_TYPE_V64:
+ /* regs 1; size 8; align 8 */
+ tcg_out_vldst(s, INSN_VLD1 | 0x7d0, arg, arg1, arg2);
+ return;
+ case TCG_TYPE_V128:
+ /* regs 2; size 8; align 16 */
+ tcg_out_vldst(s, INSN_VLD1 | 0xae0, arg, arg1, arg2);
+ return;
+ default:
+ g_assert_not_reached();
+ }
}
-static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
- TCGReg arg1, intptr_t arg2)
+static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
+ TCGReg arg1, intptr_t arg2)
{
- tcg_out_st32(s, COND_AL, arg, arg1, arg2);
+ switch (type) {
+ case TCG_TYPE_I32:
+ tcg_out_st32(s, COND_AL, arg, arg1, arg2);
+ return;
+ case TCG_TYPE_V64:
+ /* regs 1; size 8; align 8 */
+ tcg_out_vldst(s, INSN_VST1 | 0x7d0, arg, arg1, arg2);
+ return;
+ case TCG_TYPE_V128:
+ /* regs 2; size 8; align 16 */
+ tcg_out_vldst(s, INSN_VST1 | 0xae0, arg, arg1, arg2);
+ return;
+ default:
+ g_assert_not_reached();
+ }
}
static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 03/15] tcg/arm: Implement tcg_out_mov for vector types
2020-12-24 22:44 [PATCH 00/15] tcg/arm: host neon support Richard Henderson
2020-12-24 22:45 ` [PATCH 01/15] tcg/arm: Add host vector framework Richard Henderson
2020-12-24 22:45 ` [PATCH 02/15] tcg/arm: Implement tcg_out_ld/st for vector types Richard Henderson
@ 2020-12-24 22:45 ` Richard Henderson
2020-12-24 22:45 ` [PATCH 04/15] tcg/arm: Implement tcg_out_dup*_vec Richard Henderson
` (11 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2020-12-24 22:45 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target.c.inc | 50 +++++++++++++++++++++++++++++++++++-----
1 file changed, 44 insertions(+), 6 deletions(-)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 7122d5f390..acc8f2c44a 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -178,6 +178,7 @@ typedef enum {
INSN_VLD1 = 0xf4200000, /* VLD1 (multiple single elements) */
INSN_VST1 = 0xf4000000, /* VST1 (multiple single elements) */
+ INSN_VMOV = 0xf2200110, /* VMOV (register) */
} ARMInsn;
#define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4)
@@ -1086,6 +1087,25 @@ static uint32_t encode_vd(TCGReg rd)
return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13);
}
+static uint32_t encode_vn(TCGReg rn)
+{
+ tcg_debug_assert(rn >= TCG_REG_Q0);
+ return (extract32(rn, 3, 1) << 7) | (extract32(rn, 0, 3) << 17);
+}
+
+static uint32_t encode_vm(TCGReg rm)
+{
+ tcg_debug_assert(rm >= TCG_REG_Q0);
+ return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1);
+}
+
+static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece,
+ TCGReg d, TCGReg n, TCGReg m)
+{
+ tcg_out32(s, insn | (vece << 20) | (q << 6) |
+ encode_vd(d) | encode_vn(n) | encode_vm(m));
+}
+
static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
TCGReg rd, TCGReg rn, int offset)
{
@@ -2260,16 +2280,34 @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
return false;
}
-static inline bool tcg_out_mov(TCGContext *s, TCGType type,
- TCGReg ret, TCGReg arg)
+static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
{
- tcg_out_mov_reg(s, COND_AL, ret, arg);
- return true;
+ if (ret == arg) {
+ return true;
+ }
+ switch (type) {
+ case TCG_TYPE_I32:
+ if (ret < TCG_REG_Q0 && arg < TCG_REG_Q0) {
+ tcg_out_mov_reg(s, COND_AL, ret, arg);
+ return true;
+ }
+ return false;
+
+ case TCG_TYPE_V64:
+ case TCG_TYPE_V128:
+ tcg_out_vreg3(s, INSN_VMOV, type - TCG_TYPE_V64, 0, ret, arg, arg);
+ return true;
+
+ default:
+ g_assert_not_reached();
+ }
}
-static inline void tcg_out_movi(TCGContext *s, TCGType type,
- TCGReg ret, tcg_target_long arg)
+static void tcg_out_movi(TCGContext *s, TCGType type,
+ TCGReg ret, tcg_target_long arg)
{
+ tcg_debug_assert(type == TCG_TYPE_I32);
+ tcg_debug_assert(ret < TCG_REG_Q0);
tcg_out_movi32(s, COND_AL, ret, arg);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 04/15] tcg/arm: Implement tcg_out_dup*_vec
2020-12-24 22:44 [PATCH 00/15] tcg/arm: host neon support Richard Henderson
` (2 preceding siblings ...)
2020-12-24 22:45 ` [PATCH 03/15] tcg/arm: Implement tcg_out_mov " Richard Henderson
@ 2020-12-24 22:45 ` Richard Henderson
2020-12-24 22:45 ` [PATCH 05/15] tcg: Change parameters for tcg_target_const_match Richard Henderson
` (10 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2020-12-24 22:45 UTC (permalink / raw)
To: qemu-devel
Most of dupi is copied from tcg/aarch64, which has the same
encoding for AdvSimdExpandImm.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target.c.inc | 282 +++++++++++++++++++++++++++++++++++++--
1 file changed, 274 insertions(+), 8 deletions(-)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index acc8f2c44a..6e9d72289a 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -176,9 +176,14 @@ typedef enum {
/* Otherwise the assembler uses mov r0,r0 */
INSN_NOP_v4 = (COND_AL << 28) | ARITH_MOV,
+ INSN_VDUP_G = 0xee800b10, /* VDUP (ARM core register) */
+ INSN_VDUP_S = 0xf3b00c00, /* VDUP (scalar) */
+ INSN_VLDR_D = 0xed100b00, /* VLDR.64 */
INSN_VLD1 = 0xf4200000, /* VLD1 (multiple single elements) */
+ INSN_VLD1R = 0xf4a00c00, /* VLD1 (single element to all lanes) */
INSN_VST1 = 0xf4000000, /* VST1 (multiple single elements) */
INSN_VMOV = 0xf2200110, /* VMOV (register) */
+ INSN_VMOVI = 0xf2800010, /* VMOV (immediate) */
} ARMInsn;
#define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4)
@@ -197,6 +202,14 @@ static const uint8_t tcg_cond_to_arm_cond[] = {
[TCG_COND_GTU] = COND_HI,
};
+static int encode_imm(uint32_t imm);
+
+/* TCG private relocation type: add with pc+imm8 */
+#define R_ARM_PC8 11
+
+/* TCG private relocation type: vldr with imm8 << 2 */
+#define R_ARM_PC11 12
+
static inline bool reloc_pc24(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
{
ptrdiff_t offset = (tcg_ptr_byte_diff(target, code_ptr) - 8) >> 2;
@@ -225,16 +238,51 @@ static inline bool reloc_pc13(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
return false;
}
+static bool reloc_pc11(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
+{
+ ptrdiff_t offset = (tcg_ptr_byte_diff(target, code_ptr) - 8) / 4;
+
+ if (offset >= -0xff && offset <= 0xff) {
+ tcg_insn_unit insn = *code_ptr;
+ bool u = (offset >= 0);
+ if (!u) {
+ offset = -offset;
+ }
+ insn = deposit32(insn, 23, 1, u);
+ insn = deposit32(insn, 0, 8, offset);
+ *code_ptr = insn;
+ return true;
+ }
+ return false;
+}
+
+static bool reloc_pc8(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
+{
+ ptrdiff_t offset = tcg_ptr_byte_diff(target, code_ptr) - 8;
+ int rot = encode_imm(offset);
+
+ if (rot >= 0) {
+ *code_ptr = deposit32(*code_ptr, 0, 12,
+ rol32(offset, rot) | (rot << 7));
+ return true;
+ }
+ return false;
+}
+
static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
intptr_t value, intptr_t addend)
{
tcg_debug_assert(addend == 0);
-
- if (type == R_ARM_PC24) {
+ switch (type) {
+ case R_ARM_PC24:
return reloc_pc24(code_ptr, (tcg_insn_unit *)value);
- } else if (type == R_ARM_PC13) {
+ case R_ARM_PC13:
return reloc_pc13(code_ptr, (tcg_insn_unit *)value);
- } else {
+ case R_ARM_PC11:
+ return reloc_pc11(code_ptr, (tcg_insn_unit *)value);
+ case R_ARM_PC8:
+ return reloc_pc8(code_ptr, (tcg_insn_unit *)value);
+ default:
g_assert_not_reached();
}
}
@@ -251,7 +299,7 @@ static inline uint32_t rotl(uint32_t val, int n)
/* ARM immediates for ALU instructions are made of an unsigned 8-bit
right-rotated by an even amount between 0 and 30. */
-static inline int encode_imm(uint32_t imm)
+static int encode_imm(uint32_t imm)
{
int shift;
@@ -278,6 +326,79 @@ static inline int check_fit_imm(uint32_t imm)
return encode_imm(imm) >= 0;
}
+/* Return true if v16 is a valid 16-bit shifted immediate. */
+static bool is_shimm16(uint16_t v16, int *cmode, int *imm8)
+{
+ if (v16 == (v16 & 0xff)) {
+ *cmode = 0x8;
+ *imm8 = v16 & 0xff;
+ return true;
+ } else if (v16 == (v16 & 0xff00)) {
+ *cmode = 0xa;
+ *imm8 = v16 >> 8;
+ return true;
+ }
+ return false;
+}
+
+/* Return true if v32 is a valid 32-bit shifted immediate. */
+static bool is_shimm32(uint32_t v32, int *cmode, int *imm8)
+{
+ if (v32 == (v32 & 0xff)) {
+ *cmode = 0x0;
+ *imm8 = v32 & 0xff;
+ return true;
+ } else if (v32 == (v32 & 0xff00)) {
+ *cmode = 0x2;
+ *imm8 = (v32 >> 8) & 0xff;
+ return true;
+ } else if (v32 == (v32 & 0xff0000)) {
+ *cmode = 0x4;
+ *imm8 = (v32 >> 16) & 0xff;
+ return true;
+ } else if (v32 == (v32 & 0xff000000)) {
+ *cmode = 0x6;
+ *imm8 = v32 >> 24;
+ return true;
+ }
+ return false;
+}
+
+/* Return true if v32 is a valid 32-bit shifting ones immediate. */
+static bool is_soimm32(uint32_t v32, int *cmode, int *imm8)
+{
+ if ((v32 & 0xffff00ff) == 0xff) {
+ *cmode = 0xc;
+ *imm8 = (v32 >> 8) & 0xff;
+ return true;
+ } else if ((v32 & 0xff00ffff) == 0xffff) {
+ *cmode = 0xd;
+ *imm8 = (v32 >> 16) & 0xff;
+ return true;
+ }
+ return false;
+}
+
+/*
+ * Return non-zero if v32 can be formed by MOVI+ORR.
+ * Place the parameters for MOVI in (cmode, imm8).
+ * Return the cmode for ORR; the imm8 can be had via extraction from v32.
+ */
+static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8)
+{
+ int i;
+
+ for (i = 6; i > 0; i -= 2) {
+ /* Mask out one byte we can add with ORR. */
+ uint32_t tmp = v32 & ~(0xffu << (i * 4));
+ if (is_shimm32(tmp, cmode, imm8) ||
+ is_soimm32(tmp, cmode, imm8)) {
+ break;
+ }
+ }
+ return i;
+}
+
/* Test if a constant matches the constraint.
* TODO: define constraints for:
*
@@ -1106,6 +1227,15 @@ static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece,
encode_vd(d) | encode_vn(n) | encode_vm(m));
}
+static void tcg_out_vmovi(TCGContext *s, TCGReg rd,
+ int q, int op, int cmode, uint8_t imm8)
+{
+ tcg_out32(s, INSN_VMOVI | encode_vd(rd) | (q << 6) | (op << 5)
+ | (cmode << 8) | extract32(imm8, 0, 4)
+ | (extract32(imm8, 4, 3) << 16)
+ | (extract32(imm8, 7, 1) << 24));
+}
+
static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
TCGReg rd, TCGReg rn, int offset)
{
@@ -2311,22 +2441,158 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
tcg_out_movi32(s, COND_AL, ret, arg);
}
+/* Type is always V128, with I64 elements. */
+static void tcg_out_dup2_vec(TCGContext *s, TCGReg rd, TCGReg rl, TCGReg rh)
+{
+ /* Move high element into place first. */
+ /* VMOV Dd+1, Ds */
+ tcg_out_vreg3(s, INSN_VMOV | (1 << 12), 0, 0, rd, rh, rh);
+ /* Move low element into place; tcg_out_mov will check for nop. */
+ tcg_out_mov(s, TCG_TYPE_V64, rd, rl);
+}
+
static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
TCGReg rd, TCGReg rs)
{
- g_assert_not_reached();
+ int q = type - TCG_TYPE_V64;
+
+ if (vece == MO_64) {
+ if (type == TCG_TYPE_V128) {
+ tcg_out_dup2_vec(s, rd, rs, rs);
+ } else {
+ tcg_out_mov(s, TCG_TYPE_V64, rd, rs);
+ }
+ } else if (rs < TCG_REG_Q0) {
+ int b = (vece == MO_8);
+ int e = (vece == MO_16);
+ tcg_out32(s, INSN_VDUP_G | (b << 22) | (q << 21) | (e << 5) |
+ encode_vn(rd) | (rs << 12));
+ } else {
+ int imm4 = 1 << vece;
+ tcg_out32(s, INSN_VDUP_S | (imm4 << 16) | (q << 6) |
+ encode_vd(rd) | encode_vm(rs));
+ }
+ return true;
}
static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
TCGReg rd, TCGReg base, intptr_t offset)
{
- g_assert_not_reached();
+ if (vece == MO_64) {
+ tcg_out_ld(s, TCG_TYPE_V64, rd, base, offset);
+ if (type == TCG_TYPE_V128) {
+ tcg_out_dup2_vec(s, rd, rd, rd);
+ }
+ } else {
+ int q = type - TCG_TYPE_V64;
+ tcg_out_vldst(s, INSN_VLD1R | (vece << 6) | (q << 5),
+ rd, base, offset);
+ }
+ return true;
}
static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
TCGReg rd, int64_t v64)
{
- g_assert_not_reached();
+ int q = type - TCG_TYPE_V64;
+ int cmode, imm8, i;
+
+ /* Test all bytes equal first. */
+ if (vece == MO_8) {
+ tcg_out_vmovi(s, rd, q, 0, 0xe, v64);
+ return;
+ }
+
+ /*
+ * Test all bytes 0x00 or 0xff second. This can match cases that
+ * might otherwise take 2 or 3 insns for MO_16 or MO_32 below.
+ */
+ for (i = imm8 = 0; i < 8; i++) {
+ uint8_t byte = v64 >> (i * 8);
+ if (byte == 0xff) {
+ imm8 |= 1 << i;
+ } else if (byte != 0) {
+ goto fail_bytes;
+ }
+ }
+ tcg_out_vmovi(s, rd, q, 1, 0xe, imm8);
+ return;
+ fail_bytes:
+
+ /*
+ * Tests for various replications. For each element width, if we
+ * cannot find an expansion there's no point checking a larger
+ * width because we already know by replication it cannot match.
+ */
+ if (vece == MO_16) {
+ uint16_t v16 = v64;
+
+ if (is_shimm16(v16, &cmode, &imm8)) {
+ tcg_out_vmovi(s, rd, q, 0, cmode, imm8);
+ return;
+ }
+ if (is_shimm16(~v16, &cmode, &imm8)) {
+ tcg_out_vmovi(s, rd, q, 1, cmode, imm8);
+ return;
+ }
+
+ /*
+ * Otherwise, all remaining constants can be loaded in two insns:
+ * rd = v16 & 0xff, rd |= v16 & 0xff00.
+ */
+ tcg_out_vmovi(s, rd, q, 0, 0x8, v16 & 0xff);
+ tcg_out_vmovi(s, rd, q, 0, 0xb, v16 >> 8); /* VORR */
+ return;
+ }
+
+ if (vece == MO_32) {
+ uint32_t v32 = v64;
+
+ if (is_shimm32(v32, &cmode, &imm8) ||
+ is_soimm32(v32, &cmode, &imm8)) {
+ tcg_out_vmovi(s, rd, q, 0, cmode, imm8);
+ return;
+ }
+ if (is_shimm32(~v32, &cmode, &imm8) ||
+ is_soimm32(~v32, &cmode, &imm8)) {
+ tcg_out_vmovi(s, rd, q, 1, cmode, imm8);
+ return;
+ }
+
+ /*
+ * Restrict the set of constants to those we can load with
+ * two instructions. Others we load from the pool.
+ */
+ i = is_shimm32_pair(v32, &cmode, &imm8);
+ if (i) {
+ tcg_out_vmovi(s, rd, q, 0, cmode, imm8);
+ tcg_out_vmovi(s, rd, q, 0, i, extract32(v32, i * 4, 8));
+ return;
+ }
+ i = is_shimm32_pair(~v32, &cmode, &imm8);
+ if (i) {
+ tcg_out_vmovi(s, rd, q, 1, cmode, imm8);
+ tcg_out_vmovi(s, rd, q, 1, i, extract32(~v32, i * 4, 8));
+ return;
+ }
+ }
+
+ /*
+ * As a last resort, load from the constant pool.
+ */
+ if (!q || vece == MO_64) {
+ new_pool_l2(s, R_ARM_PC11, s->code_ptr, 0, v64, v64 >> 32);
+ /* VLDR Dd, [pc + offset] */
+ tcg_out32(s, INSN_VLDR_D | encode_vd(rd) | (0xf << 16));
+ if (q) {
+ tcg_out_dup2_vec(s, rd, rd, rd);
+ }
+ } else {
+ new_pool_label(s, (uint32_t)v64, R_ARM_PC8, s->code_ptr, 0);
+ /* add tmp, pc, offset */
+ tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_TMP, TCG_REG_PC, 0);
+ tcg_out_dupm_vec(s, type, MO_32, rd, TCG_REG_TMP, 0);
+ }
}
static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 05/15] tcg: Change parameters for tcg_target_const_match
2020-12-24 22:44 [PATCH 00/15] tcg/arm: host neon support Richard Henderson
` (3 preceding siblings ...)
2020-12-24 22:45 ` [PATCH 04/15] tcg/arm: Implement tcg_out_dup*_vec Richard Henderson
@ 2020-12-24 22:45 ` Richard Henderson
2020-12-24 22:45 ` [PATCH 06/15] tcg/arm: Implement minimal vector operations Richard Henderson
` (9 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2020-12-24 22:45 UTC (permalink / raw)
To: qemu-devel
Change the return value to bool, because that's what is should
have been from the start. Pass the ct mask instead of the whole
TCGArgConstraint, as that's the only part that's relevant.
Change the value argument to int64_t. We will need the extra
width for 32-bit hosts wanting to match vector constants.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg.c | 5 ++---
tcg/aarch64/tcg-target.c.inc | 5 +----
tcg/arm/tcg-target.c.inc | 5 +----
tcg/i386/tcg-target.c.inc | 4 +---
tcg/mips/tcg-target.c.inc | 5 +----
tcg/ppc/tcg-target.c.inc | 4 +---
tcg/riscv/tcg-target.c.inc | 4 +---
tcg/s390/tcg-target.c.inc | 5 +----
tcg/sparc/tcg-target.c.inc | 5 +----
tcg/tci/tcg-target.c.inc | 6 ++----
10 files changed, 12 insertions(+), 36 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 3c0e494a08..73d22ecb26 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -147,8 +147,7 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
TCGReg base, intptr_t ofs);
static void tcg_out_call(TCGContext *s, tcg_insn_unit *target);
-static int tcg_target_const_match(tcg_target_long val, TCGType type,
- const TCGArgConstraint *arg_ct);
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct);
#ifdef TCG_TARGET_NEED_LDST_LABELS
static int tcg_out_ldst_finalize(TCGContext *s);
#endif
@@ -4000,7 +3999,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
ts = arg_temp(arg);
if (ts->val_type == TEMP_VAL_CONST
- && tcg_target_const_match(ts->val, ts->type, arg_ct)) {
+ && tcg_target_const_match(ts->val, ts->type, arg_ct->ct)) {
/* constant is OK for instruction */
const_args[i] = 1;
new_args[i] = ts->val;
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index e52db4a881..84971a285f 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -262,11 +262,8 @@ static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8)
}
}
-static int tcg_target_const_match(tcg_target_long val, TCGType type,
- const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
{
- int ct = arg_ct->ct;
-
if (ct & TCG_CT_CONST) {
return 1;
}
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 6e9d72289a..3eb4456dce 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -407,11 +407,8 @@ static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8)
* mov operand2: values represented with x << (2 * y), x < 0x100
* add, sub, eor...: ditto
*/
-static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
- const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
{
- int ct;
- ct = arg_ct->ct;
if (ct & TCG_CT_CONST) {
return 1;
} else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) {
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 9c16c5cc70..96a296d92e 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -206,10 +206,8 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
#endif
/* test if a constant matches the constraint */
-static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
- const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
{
- int ct = arg_ct->ct;
if (ct & TCG_CT_CONST) {
return 1;
}
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 3542fce752..8fb2d4f422 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -190,11 +190,8 @@ static inline bool is_p2m1(tcg_target_long val)
}
/* test if a constant matches the constraint */
-static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
- const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
{
- int ct;
- ct = arg_ct->ct;
if (ct & TCG_CT_CONST) {
return 1;
} else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 238743f135..aded09315d 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -219,10 +219,8 @@ static bool reloc_pc14(tcg_insn_unit *pc, tcg_insn_unit *target)
}
/* test if a constant matches the constraint */
-static int tcg_target_const_match(tcg_target_long val, TCGType type,
- const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
{
- int ct = arg_ct->ct;
if (ct & TCG_CT_CONST) {
return 1;
}
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 3bc0d1f1b4..3b4a3a7dcf 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -132,10 +132,8 @@ static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
}
/* test if a constant matches the constraint */
-static int tcg_target_const_match(tcg_target_long val, TCGType type,
- const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
{
- int ct = arg_ct->ct;
if (ct & TCG_CT_CONST) {
return 1;
}
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
index 087b4a2f5c..8edb35030a 100644
--- a/tcg/s390/tcg-target.c.inc
+++ b/tcg/s390/tcg-target.c.inc
@@ -403,11 +403,8 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
}
/* Test if a constant matches the constraint. */
-static int tcg_target_const_match(tcg_target_long val, TCGType type,
- const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
{
- int ct = arg_ct->ct;
-
if (ct & TCG_CT_CONST) {
return 1;
}
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
index 85fb6c344c..e44eb9aa4b 100644
--- a/tcg/sparc/tcg-target.c.inc
+++ b/tcg/sparc/tcg-target.c.inc
@@ -320,11 +320,8 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
}
/* test if a constant matches the constraint */
-static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
- const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
{
- int ct = arg_ct->ct;
-
if (ct & TCG_CT_CONST) {
return 1;
}
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index d28133ccb1..4e2f25bbba 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -742,11 +742,9 @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
}
/* Test if a constant matches the constraint. */
-static int tcg_target_const_match(tcg_target_long val, TCGType type,
- const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
{
- /* No need to return 0 or 1, 0 or != 0 is good enough. */
- return arg_ct->ct & TCG_CT_CONST;
+ return ct & TCG_CT_CONST;
}
static void tcg_target_init(TCGContext *s)
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 06/15] tcg/arm: Implement minimal vector operations
2020-12-24 22:44 [PATCH 00/15] tcg/arm: host neon support Richard Henderson
` (4 preceding siblings ...)
2020-12-24 22:45 ` [PATCH 05/15] tcg: Change parameters for tcg_target_const_match Richard Henderson
@ 2020-12-24 22:45 ` Richard Henderson
2020-12-24 22:45 ` [PATCH 07/15] tcg/arm: Implement andc, orc, abs, neg, not " Richard Henderson
` (8 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2020-12-24 22:45 UTC (permalink / raw)
To: qemu-devel
Implementing dup2, add, sub, and, or, xor as the minimal set.
This allows us to actually enable neon in the header file.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target-conset.h | 3 +
tcg/arm/tcg-target-constr.h | 2 +
tcg/arm/tcg-target.h | 6 +-
tcg/arm/tcg-target.c.inc | 203 ++++++++++++++++++++++++++++++++++--
4 files changed, 206 insertions(+), 8 deletions(-)
diff --git a/tcg/arm/tcg-target-conset.h b/tcg/arm/tcg-target-conset.h
index dbcae51c4b..ffcac7c6aa 100644
--- a/tcg/arm/tcg-target-conset.h
+++ b/tcg/arm/tcg-target-conset.h
@@ -25,6 +25,9 @@ C_O1_I2(r, r, rIN)
C_O1_I2(r, r, ri)
C_O1_I2(r, rZ, rZ)
C_O1_I2(w, w, w)
+C_O1_I2(w, w, wO)
+C_O1_I2(w, w, wV)
+C_O1_I2(w, w, wZ)
C_O1_I4(r, r, r, rI, rI)
C_O1_I4(r, r, rIN, rIK, 0)
C_O2_I1(r, r, l)
diff --git a/tcg/arm/tcg-target-constr.h b/tcg/arm/tcg-target-constr.h
index 5f2780decd..f2c8f3dfce 100644
--- a/tcg/arm/tcg-target-constr.h
+++ b/tcg/arm/tcg-target-constr.h
@@ -29,4 +29,6 @@ REGS('w', 0xffff0000u)
CONST('I', TCG_CT_CONST_ARM)
CONST('K', TCG_CT_CONST_INV)
CONST('N', TCG_CT_CONST_NEG)
+CONST('O', TCG_CT_CONST_ORRI)
+CONST('V', TCG_CT_CONST_ANDI)
CONST('Z', TCG_CT_CONST_ZERO)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index b40419971e..d87493364f 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -107,7 +107,11 @@ typedef enum {
#else
extern bool use_idiv_instructions;
#endif
-#define use_neon_instructions 0
+#ifdef __ARM_NEON__
+#define use_neon_instructions 1
+#else
+extern bool use_neon_instructions;
+#endif
/* used for function call generation */
#define TCG_TARGET_STACK_ALIGN 8
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 3eb4456dce..91243b641c 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -30,6 +30,9 @@ int arm_arch = __ARM_ARCH;
#ifndef use_idiv_instructions
bool use_idiv_instructions;
#endif
+#ifndef use_neon_instructions
+bool use_neon_instructions;
+#endif
/* ??? Ought to think about changing CONFIG_SOFTMMU to always defined. */
#ifdef CONFIG_SOFTMMU
@@ -176,6 +179,28 @@ typedef enum {
/* Otherwise the assembler uses mov r0,r0 */
INSN_NOP_v4 = (COND_AL << 28) | ARITH_MOV,
+ INSN_VADD = 0xf2000800,
+ INSN_VAND = 0xf2000110,
+ INSN_VEOR = 0xf3000110,
+ INSN_VORR = 0xf2200110,
+ INSN_VSUB = 0xf3000800,
+
+ INSN_VMVN = 0xf3b00580,
+
+ INSN_VCEQ0 = 0xf3b10100,
+ INSN_VCGT0 = 0xf3b10000,
+ INSN_VCGE0 = 0xf3b10080,
+ INSN_VCLE0 = 0xf3b10180,
+ INSN_VCLT0 = 0xf3b10200,
+
+ INSN_VCEQ = 0xf3000810,
+ INSN_VCGE = 0xf2000310,
+ INSN_VCGT = 0xf2000300,
+ INSN_VCGE_U = 0xf3000310,
+ INSN_VCGT_U = 0xf3000300,
+
+ INSN_VTST = 0xf2000810,
+
INSN_VDUP_G = 0xee800b10, /* VDUP (ARM core register) */
INSN_VDUP_S = 0xf3b00c00, /* VDUP (scalar) */
INSN_VLDR_D = 0xed100b00, /* VLDR.64 */
@@ -291,6 +316,8 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
#define TCG_CT_CONST_INV 0x200
#define TCG_CT_CONST_NEG 0x400
#define TCG_CT_CONST_ZERO 0x800
+#define TCG_CT_CONST_ORRI 0x1000
+#define TCG_CT_CONST_ANDI 0x2000
static inline uint32_t rotl(uint32_t val, int n)
{
@@ -399,6 +426,16 @@ static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8)
return i;
}
+/* Return true if V is a valid 16-bit or 32-bit shifted immediate. */
+static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8)
+{
+ if (v32 == deposit32(v32, 16, 16, v32)) {
+ return is_shimm16(v32, cmode, imm8);
+ } else {
+ return is_shimm32(v32, cmode, imm8);
+ }
+}
+
/* Test if a constant matches the constraint.
* TODO: define constraints for:
*
@@ -419,9 +456,26 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
return 1;
} else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
return 1;
- } else {
- return 0;
}
+
+ switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) {
+ case 0:
+ break;
+ case TCG_CT_CONST_ANDI:
+ val = ~val;
+ /* fallthru */
+ case TCG_CT_CONST_ORRI:
+ if (val == deposit64(val, 32, 32, val)) {
+ int cmode, imm8;
+ return is_shimm1632(val, &cmode, &imm8);
+ }
+ break;
+ default:
+ /* Both bits should not be set for the same insn. */
+ g_assert_not_reached();
+ }
+
+ return 0;
}
static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset)
@@ -1217,6 +1271,13 @@ static uint32_t encode_vm(TCGReg rm)
return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1);
}
+static void tcg_out_vreg2(TCGContext *s, ARMInsn insn, int q, int vece,
+ TCGReg d, TCGReg m)
+{
+ tcg_out32(s, insn | (vece << 18) | (q << 6) |
+ encode_vd(d) | encode_vm(m));
+}
+
static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece,
TCGReg d, TCGReg n, TCGReg m)
{
@@ -2289,10 +2350,13 @@ static int tcg_target_op_def(TCGOpcode op)
case INDEX_op_add_vec:
case INDEX_op_sub_vec:
case INDEX_op_xor_vec:
- case INDEX_op_or_vec:
- case INDEX_op_and_vec:
- case INDEX_op_cmp_vec:
return C_O1_I2(w, w, w);
+ case INDEX_op_or_vec:
+ return C_O1_I2(w, w, wO);
+ case INDEX_op_and_vec:
+ return C_O1_I2(w, w, wV);
+ case INDEX_op_cmp_vec:
+ return C_O1_I2(w, w, wZ);
default:
g_assert_not_reached();
@@ -2592,16 +2656,141 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
}
}
+static const ARMInsn vec_cmp_insn[16] = {
+ [TCG_COND_EQ] = INSN_VCEQ,
+ [TCG_COND_GT] = INSN_VCGT,
+ [TCG_COND_GE] = INSN_VCGE,
+ [TCG_COND_GTU] = INSN_VCGT_U,
+ [TCG_COND_GEU] = INSN_VCGE_U,
+};
+
+static const ARMInsn vec_cmp0_insn[16] = {
+ [TCG_COND_EQ] = INSN_VCEQ0,
+ [TCG_COND_GT] = INSN_VCGT0,
+ [TCG_COND_GE] = INSN_VCGE0,
+ [TCG_COND_LT] = INSN_VCLT0,
+ [TCG_COND_LE] = INSN_VCLE0,
+};
+
static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
unsigned vecl, unsigned vece,
const TCGArg *args, const int *const_args)
{
- g_assert_not_reached();
+ TCGType type = vecl + TCG_TYPE_V64;
+ unsigned q = vecl;
+ TCGArg a0, a1, a2;
+ int cmode, imm8;
+
+ a0 = args[0];
+ a1 = args[1];
+ a2 = args[2];
+
+ switch (opc) {
+ case INDEX_op_ld_vec:
+ tcg_out_ld(s, type, a0, a1, a2);
+ return;
+ case INDEX_op_st_vec:
+ tcg_out_st(s, type, a0, a1, a2);
+ return;
+ case INDEX_op_dupm_vec:
+ tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
+ return;
+ case INDEX_op_dup2_vec:
+ tcg_out_dup2_vec(s, a0, a1, a2);
+ return;
+ case INDEX_op_add_vec:
+ tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2);
+ return;
+ case INDEX_op_sub_vec:
+ tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2);
+ return;
+ case INDEX_op_xor_vec:
+ tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
+ return;
+
+ case INDEX_op_and_vec:
+ if (const_args[2]) {
+ is_shimm1632(~a2, &cmode, &imm8);
+ if (a0 == a1) {
+ tcg_out_vmovi(s, a0, q, 1, cmode | 1, imm8); /* VBICI */
+ return;
+ }
+ tcg_out_vmovi(s, a0, q, 1, cmode, imm8); /* VMVNI */
+ a2 = a0;
+ }
+ tcg_out_vreg3(s, INSN_VAND, q, 0, a0, a1, a2);
+ return;
+
+ case INDEX_op_or_vec:
+ if (const_args[2]) {
+ is_shimm1632(a2, &cmode, &imm8);
+ if (a0 == a1) {
+ tcg_out_vmovi(s, a0, q, 0, cmode | 1, imm8); /* VORI */
+ return;
+ }
+ tcg_out_vmovi(s, a0, q, 0, cmode, imm8); /* VMOVI */
+ a2 = a0;
+ }
+ tcg_out_vreg3(s, INSN_VORR, q, 0, a0, a1, a2);
+ return;
+
+ case INDEX_op_cmp_vec:
+ {
+ TCGCond cond = args[3];
+
+ if (cond == TCG_COND_NE) {
+ if (const_args[2]) {
+ tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a1);
+ } else {
+ tcg_out_vreg3(s, INSN_VCEQ, q, vece, a0, a1, a2);
+ tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0);
+ }
+ } else {
+ ARMInsn insn;
+
+ if (const_args[2]) {
+ insn = vec_cmp0_insn[cond];
+ if (insn) {
+ tcg_out_vreg2(s, insn, q, vece, a0, a1);
+ return;
+ }
+ tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0);
+ a2 = TCG_VEC_TMP;
+ }
+ insn = vec_cmp_insn[cond];
+ if (insn == 0) {
+ TCGArg t;
+ t = a1, a1 = a2, a2 = t;
+ cond = tcg_swap_cond(cond);
+ insn = vec_cmp_insn[cond];
+ tcg_debug_assert(insn != 0);
+ }
+ tcg_out_vreg3(s, insn, q, vece, a0, a1, a2);
+ }
+ }
+ return;
+
+ case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
+ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
+ default:
+ g_assert_not_reached();
+ }
}
int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
{
- return 0;
+ switch (opc) {
+ case INDEX_op_add_vec:
+ case INDEX_op_sub_vec:
+ case INDEX_op_and_vec:
+ case INDEX_op_or_vec:
+ case INDEX_op_xor_vec:
+ return 1;
+ case INDEX_op_cmp_vec:
+ return vece < MO_64;
+ default:
+ return 0;
+ }
}
void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 07/15] tcg/arm: Implement andc, orc, abs, neg, not vector operations
2020-12-24 22:44 [PATCH 00/15] tcg/arm: host neon support Richard Henderson
` (5 preceding siblings ...)
2020-12-24 22:45 ` [PATCH 06/15] tcg/arm: Implement minimal vector operations Richard Henderson
@ 2020-12-24 22:45 ` Richard Henderson
2020-12-24 22:45 ` [PATCH 08/15] tcg/arm: Implement TCG_TARGET_HAS_shi_vec Richard Henderson
` (7 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2020-12-24 22:45 UTC (permalink / raw)
To: qemu-devel
These logical and arithmetic operations are optional, but are
trivial to accomplish with the existing infrastructure.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target-conset.h | 1 +
tcg/arm/tcg-target.h | 10 +++++-----
tcg/arm/tcg-target.c.inc | 38 +++++++++++++++++++++++++++++++++++++
3 files changed, 44 insertions(+), 5 deletions(-)
diff --git a/tcg/arm/tcg-target-conset.h b/tcg/arm/tcg-target-conset.h
index ffcac7c6aa..f32bf44f8b 100644
--- a/tcg/arm/tcg-target-conset.h
+++ b/tcg/arm/tcg-target-conset.h
@@ -15,6 +15,7 @@ C_O0_I4(s, s, s, s)
C_O1_I1(r, l)
C_O1_I1(r, r)
C_O1_I1(w, r)
+C_O1_I1(w, w)
C_O1_I1(w, wr)
C_O1_I2(r, 0, rZ)
C_O1_I2(r, l, l)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index d87493364f..bb9302c616 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -154,11 +154,11 @@ extern bool use_neon_instructions;
#define TCG_TARGET_HAS_v128 use_neon_instructions
#define TCG_TARGET_HAS_v256 0
-#define TCG_TARGET_HAS_andc_vec 0
-#define TCG_TARGET_HAS_orc_vec 0
-#define TCG_TARGET_HAS_not_vec 0
-#define TCG_TARGET_HAS_neg_vec 0
-#define TCG_TARGET_HAS_abs_vec 0
+#define TCG_TARGET_HAS_andc_vec 1
+#define TCG_TARGET_HAS_orc_vec 1
+#define TCG_TARGET_HAS_not_vec 1
+#define TCG_TARGET_HAS_neg_vec 1
+#define TCG_TARGET_HAS_abs_vec 1
#define TCG_TARGET_HAS_roti_vec 0
#define TCG_TARGET_HAS_rots_vec 0
#define TCG_TARGET_HAS_rotv_vec 0
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 91243b641c..88814c6836 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -181,11 +181,15 @@ typedef enum {
INSN_VADD = 0xf2000800,
INSN_VAND = 0xf2000110,
+ INSN_VBIC = 0xf2100110,
INSN_VEOR = 0xf3000110,
+ INSN_VORN = 0xf2300110,
INSN_VORR = 0xf2200110,
INSN_VSUB = 0xf3000800,
+ INSN_VABS = 0xf3b10300,
INSN_VMVN = 0xf3b00580,
+ INSN_VNEG = 0xf3b10380,
INSN_VCEQ0 = 0xf3b10100,
INSN_VCGT0 = 0xf3b10000,
@@ -2346,14 +2350,20 @@ static int tcg_target_op_def(TCGOpcode op)
return C_O1_I1(w, r);
case INDEX_op_dup_vec:
return C_O1_I1(w, wr);
+ case INDEX_op_abs_vec:
+ case INDEX_op_neg_vec:
+ case INDEX_op_not_vec:
+ return C_O1_I1(w, w);
case INDEX_op_dup2_vec:
case INDEX_op_add_vec:
case INDEX_op_sub_vec:
case INDEX_op_xor_vec:
return C_O1_I2(w, w, w);
case INDEX_op_or_vec:
+ case INDEX_op_andc_vec:
return C_O1_I2(w, w, wO);
case INDEX_op_and_vec:
+ case INDEX_op_orc_vec:
return C_O1_I2(w, w, wV);
case INDEX_op_cmp_vec:
return C_O1_I2(w, w, wZ);
@@ -2698,6 +2708,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_dup2_vec:
tcg_out_dup2_vec(s, a0, a1, a2);
return;
+ case INDEX_op_abs_vec:
+ tcg_out_vreg2(s, INSN_VABS, q, vece, a0, a1);
+ return;
+ case INDEX_op_neg_vec:
+ tcg_out_vreg2(s, INSN_VNEG, q, vece, a0, a1);
+ return;
+ case INDEX_op_not_vec:
+ tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a1);
+ return;
case INDEX_op_add_vec:
tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2);
return;
@@ -2708,6 +2727,13 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
return;
+ case INDEX_op_andc_vec:
+ if (!const_args[2]) {
+ tcg_out_vreg3(s, INSN_VBIC, q, 0, a0, a1, a2);
+ return;
+ }
+ a2 = ~a2;
+ /* fall through */
case INDEX_op_and_vec:
if (const_args[2]) {
is_shimm1632(~a2, &cmode, &imm8);
@@ -2721,6 +2747,13 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
tcg_out_vreg3(s, INSN_VAND, q, 0, a0, a1, a2);
return;
+ case INDEX_op_orc_vec:
+ if (!const_args[2]) {
+ tcg_out_vreg3(s, INSN_VORN, q, 0, a0, a1, a2);
+ return;
+ }
+ a2 = ~a2;
+ /* fall through */
case INDEX_op_or_vec:
if (const_args[2]) {
is_shimm1632(a2, &cmode, &imm8);
@@ -2783,10 +2816,15 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_add_vec:
case INDEX_op_sub_vec:
case INDEX_op_and_vec:
+ case INDEX_op_andc_vec:
case INDEX_op_or_vec:
+ case INDEX_op_orc_vec:
case INDEX_op_xor_vec:
+ case INDEX_op_not_vec:
return 1;
+ case INDEX_op_abs_vec:
case INDEX_op_cmp_vec:
+ case INDEX_op_neg_vec:
return vece < MO_64;
default:
return 0;
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 08/15] tcg/arm: Implement TCG_TARGET_HAS_shi_vec
2020-12-24 22:44 [PATCH 00/15] tcg/arm: host neon support Richard Henderson
` (6 preceding siblings ...)
2020-12-24 22:45 ` [PATCH 07/15] tcg/arm: Implement andc, orc, abs, neg, not " Richard Henderson
@ 2020-12-24 22:45 ` Richard Henderson
2020-12-24 22:45 ` [PATCH 09/15] tcg/arm: Implement TCG_TARGET_HAS_mul_vec Richard Henderson
` (6 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2020-12-24 22:45 UTC (permalink / raw)
To: qemu-devel
This consists of the three immediate shifts: shli, shri, sari.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target.h | 2 +-
tcg/arm/tcg-target.c.inc | 27 +++++++++++++++++++++++++++
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index bb9302c616..344b0d3199 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -162,7 +162,7 @@ extern bool use_neon_instructions;
#define TCG_TARGET_HAS_roti_vec 0
#define TCG_TARGET_HAS_rots_vec 0
#define TCG_TARGET_HAS_rotv_vec 0
-#define TCG_TARGET_HAS_shi_vec 0
+#define TCG_TARGET_HAS_shi_vec 1
#define TCG_TARGET_HAS_shs_vec 0
#define TCG_TARGET_HAS_shv_vec 0
#define TCG_TARGET_HAS_mul_vec 0
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 88814c6836..f5d10e262a 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -203,6 +203,10 @@ typedef enum {
INSN_VCGE_U = 0xf3000310,
INSN_VCGT_U = 0xf3000300,
+ INSN_VSHLI = 0xf2800510, /* VSHL (immediate) */
+ INSN_VSARI = 0xf2800010, /* VSHR.S */
+ INSN_VSHRI = 0xf3800010, /* VSHR.U */
+
INSN_VTST = 0xf2000810,
INSN_VDUP_G = 0xee800b10, /* VDUP (ARM core register) */
@@ -1298,6 +1302,14 @@ static void tcg_out_vmovi(TCGContext *s, TCGReg rd,
| (extract32(imm8, 7, 1) << 24));
}
+static void tcg_out_vshifti(TCGContext *s, ARMInsn insn, int q,
+ TCGReg rd, TCGReg rm, int l_imm6)
+{
+ tcg_out32(s, insn | (q << 6) | encode_vd(rd) | encode_vm(rm) |
+ (extract32(l_imm6, 6, 1) << 7) |
+ (extract32(l_imm6, 0, 6) << 16));
+}
+
static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
TCGReg rd, TCGReg rn, int offset)
{
@@ -2353,6 +2365,9 @@ static int tcg_target_op_def(TCGOpcode op)
case INDEX_op_abs_vec:
case INDEX_op_neg_vec:
case INDEX_op_not_vec:
+ case INDEX_op_shli_vec:
+ case INDEX_op_shri_vec:
+ case INDEX_op_sari_vec:
return C_O1_I1(w, w);
case INDEX_op_dup2_vec:
case INDEX_op_add_vec:
@@ -2726,6 +2741,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_xor_vec:
tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
return;
+ case INDEX_op_shli_vec:
+ tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece));
+ return;
+ case INDEX_op_shri_vec:
+ tcg_out_vshifti(s, INSN_VSHRI, q, a0, a1, (16 << vece) - a2);
+ return;
+ case INDEX_op_sari_vec:
+ tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2);
+ return;
case INDEX_op_andc_vec:
if (!const_args[2]) {
@@ -2821,6 +2845,9 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_orc_vec:
case INDEX_op_xor_vec:
case INDEX_op_not_vec:
+ case INDEX_op_shli_vec:
+ case INDEX_op_shri_vec:
+ case INDEX_op_sari_vec:
return 1;
case INDEX_op_abs_vec:
case INDEX_op_cmp_vec:
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 09/15] tcg/arm: Implement TCG_TARGET_HAS_mul_vec
2020-12-24 22:44 [PATCH 00/15] tcg/arm: host neon support Richard Henderson
` (7 preceding siblings ...)
2020-12-24 22:45 ` [PATCH 08/15] tcg/arm: Implement TCG_TARGET_HAS_shi_vec Richard Henderson
@ 2020-12-24 22:45 ` Richard Henderson
2020-12-24 22:45 ` [PATCH 10/15] tcg/arm: Implement TCG_TARGET_HAS_sat_vec Richard Henderson
` (5 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2020-12-24 22:45 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target.h | 2 +-
tcg/arm/tcg-target.c.inc | 6 ++++++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 344b0d3199..8e5b304a5a 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -165,7 +165,7 @@ extern bool use_neon_instructions;
#define TCG_TARGET_HAS_shi_vec 1
#define TCG_TARGET_HAS_shs_vec 0
#define TCG_TARGET_HAS_shv_vec 0
-#define TCG_TARGET_HAS_mul_vec 0
+#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 0
#define TCG_TARGET_HAS_minmax_vec 0
#define TCG_TARGET_HAS_bitsel_vec 0
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index f5d10e262a..d11efc553a 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -186,6 +186,7 @@ typedef enum {
INSN_VORN = 0xf2300110,
INSN_VORR = 0xf2200110,
INSN_VSUB = 0xf3000800,
+ INSN_VMUL = 0xf2000910,
INSN_VABS = 0xf3b10300,
INSN_VMVN = 0xf3b00580,
@@ -2371,6 +2372,7 @@ static int tcg_target_op_def(TCGOpcode op)
return C_O1_I1(w, w);
case INDEX_op_dup2_vec:
case INDEX_op_add_vec:
+ case INDEX_op_mul_vec:
case INDEX_op_sub_vec:
case INDEX_op_xor_vec:
return C_O1_I2(w, w, w);
@@ -2735,6 +2737,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_add_vec:
tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2);
return;
+ case INDEX_op_mul_vec:
+ tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2);
+ return;
case INDEX_op_sub_vec:
tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2);
return;
@@ -2851,6 +2856,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
return 1;
case INDEX_op_abs_vec:
case INDEX_op_cmp_vec:
+ case INDEX_op_mul_vec:
case INDEX_op_neg_vec:
return vece < MO_64;
default:
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 10/15] tcg/arm: Implement TCG_TARGET_HAS_sat_vec
2020-12-24 22:44 [PATCH 00/15] tcg/arm: host neon support Richard Henderson
` (8 preceding siblings ...)
2020-12-24 22:45 ` [PATCH 09/15] tcg/arm: Implement TCG_TARGET_HAS_mul_vec Richard Henderson
@ 2020-12-24 22:45 ` Richard Henderson
2020-12-24 22:45 ` [PATCH 11/15] tcg/arm: Implement TCG_TARGET_HAS_minmax_vec Richard Henderson
` (4 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2020-12-24 22:45 UTC (permalink / raw)
To: qemu-devel
This is saturating add and subtract, signed and unsigned.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target.h | 2 +-
tcg/arm/tcg-target.c.inc | 24 ++++++++++++++++++++++++
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 8e5b304a5a..c41dea2b03 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -166,7 +166,7 @@ extern bool use_neon_instructions;
#define TCG_TARGET_HAS_shs_vec 0
#define TCG_TARGET_HAS_shv_vec 0
#define TCG_TARGET_HAS_mul_vec 1
-#define TCG_TARGET_HAS_sat_vec 0
+#define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 0
#define TCG_TARGET_HAS_bitsel_vec 0
#define TCG_TARGET_HAS_cmpsel_vec 0
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index d11efc553a..a6d9ee929b 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -187,6 +187,10 @@ typedef enum {
INSN_VORR = 0xf2200110,
INSN_VSUB = 0xf3000800,
INSN_VMUL = 0xf2000910,
+ INSN_VQADD = 0xf2000010,
+ INSN_VQADD_U = 0xf3000010,
+ INSN_VQSUB = 0xf2000210,
+ INSN_VQSUB_U = 0xf3000210,
INSN_VABS = 0xf3b10300,
INSN_VMVN = 0xf3b00580,
@@ -2373,7 +2377,11 @@ static int tcg_target_op_def(TCGOpcode op)
case INDEX_op_dup2_vec:
case INDEX_op_add_vec:
case INDEX_op_mul_vec:
+ case INDEX_op_ssadd_vec:
+ case INDEX_op_sssub_vec:
case INDEX_op_sub_vec:
+ case INDEX_op_usadd_vec:
+ case INDEX_op_ussub_vec:
case INDEX_op_xor_vec:
return C_O1_I2(w, w, w);
case INDEX_op_or_vec:
@@ -2743,6 +2751,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_sub_vec:
tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2);
return;
+ case INDEX_op_ssadd_vec:
+ tcg_out_vreg3(s, INSN_VQADD, q, vece, a0, a1, a2);
+ return;
+ case INDEX_op_sssub_vec:
+ tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2);
+ return;
+ case INDEX_op_usadd_vec:
+ tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2);
+ return;
+ case INDEX_op_ussub_vec:
+ tcg_out_vreg3(s, INSN_VQSUB_U, q, vece, a0, a1, a2);
+ return;
case INDEX_op_xor_vec:
tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
return;
@@ -2853,6 +2873,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_shli_vec:
case INDEX_op_shri_vec:
case INDEX_op_sari_vec:
+ case INDEX_op_ssadd_vec:
+ case INDEX_op_sssub_vec:
+ case INDEX_op_usadd_vec:
+ case INDEX_op_ussub_vec:
return 1;
case INDEX_op_abs_vec:
case INDEX_op_cmp_vec:
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 11/15] tcg/arm: Implement TCG_TARGET_HAS_minmax_vec
2020-12-24 22:44 [PATCH 00/15] tcg/arm: host neon support Richard Henderson
` (9 preceding siblings ...)
2020-12-24 22:45 ` [PATCH 10/15] tcg/arm: Implement TCG_TARGET_HAS_sat_vec Richard Henderson
@ 2020-12-24 22:45 ` Richard Henderson
2020-12-24 22:45 ` [PATCH 12/15] tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec Richard Henderson
` (3 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2020-12-24 22:45 UTC (permalink / raw)
To: qemu-devel
This is minimum and maximu, signed and unsigned.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target.h | 2 +-
tcg/arm/tcg-target.c.inc | 24 ++++++++++++++++++++++++
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index c41dea2b03..e3c533f00f 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -167,7 +167,7 @@ extern bool use_neon_instructions;
#define TCG_TARGET_HAS_shv_vec 0
#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 1
-#define TCG_TARGET_HAS_minmax_vec 0
+#define TCG_TARGET_HAS_minmax_vec 1
#define TCG_TARGET_HAS_bitsel_vec 0
#define TCG_TARGET_HAS_cmpsel_vec 0
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index a6d9ee929b..6e17082df2 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -191,6 +191,10 @@ typedef enum {
INSN_VQADD_U = 0xf3000010,
INSN_VQSUB = 0xf2000210,
INSN_VQSUB_U = 0xf3000210,
+ INSN_VMAX = 0xf2000600,
+ INSN_VMAX_U = 0xf3000600,
+ INSN_VMIN = 0xf2000610,
+ INSN_VMIN_U = 0xf3000610,
INSN_VABS = 0xf3b10300,
INSN_VMVN = 0xf3b00580,
@@ -2377,9 +2381,13 @@ static int tcg_target_op_def(TCGOpcode op)
case INDEX_op_dup2_vec:
case INDEX_op_add_vec:
case INDEX_op_mul_vec:
+ case INDEX_op_smax_vec:
+ case INDEX_op_smin_vec:
case INDEX_op_ssadd_vec:
case INDEX_op_sssub_vec:
case INDEX_op_sub_vec:
+ case INDEX_op_umax_vec:
+ case INDEX_op_umin_vec:
case INDEX_op_usadd_vec:
case INDEX_op_ussub_vec:
case INDEX_op_xor_vec:
@@ -2748,6 +2756,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_mul_vec:
tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2);
return;
+ case INDEX_op_smax_vec:
+ tcg_out_vreg3(s, INSN_VMAX, q, vece, a0, a1, a2);
+ return;
+ case INDEX_op_smin_vec:
+ tcg_out_vreg3(s, INSN_VMIN, q, vece, a0, a1, a2);
+ return;
case INDEX_op_sub_vec:
tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2);
return;
@@ -2757,6 +2771,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_sssub_vec:
tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2);
return;
+ case INDEX_op_umax_vec:
+ tcg_out_vreg3(s, INSN_VMAX_U, q, vece, a0, a1, a2);
+ return;
+ case INDEX_op_umin_vec:
+ tcg_out_vreg3(s, INSN_VMIN_U, q, vece, a0, a1, a2);
+ return;
case INDEX_op_usadd_vec:
tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2);
return;
@@ -2882,6 +2902,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_cmp_vec:
case INDEX_op_mul_vec:
case INDEX_op_neg_vec:
+ case INDEX_op_smax_vec:
+ case INDEX_op_smin_vec:
+ case INDEX_op_umax_vec:
+ case INDEX_op_umin_vec:
return vece < MO_64;
default:
return 0;
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 12/15] tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec
2020-12-24 22:44 [PATCH 00/15] tcg/arm: host neon support Richard Henderson
` (10 preceding siblings ...)
2020-12-24 22:45 ` [PATCH 11/15] tcg/arm: Implement TCG_TARGET_HAS_minmax_vec Richard Henderson
@ 2020-12-24 22:45 ` Richard Henderson
2020-12-24 22:45 ` [PATCH 13/15] tcg/arm: Implement TCG_TARGET_HAS_shv_vec Richard Henderson
` (2 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2020-12-24 22:45 UTC (permalink / raw)
To: qemu-devel
NEON has 3 instructions implementing this 4 argument operation,
with each insn overlapping a different logical input onto the
destination register.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target-conset.h | 1 +
tcg/arm/tcg-target.h | 2 +-
tcg/arm/tcg-target.c.inc | 22 ++++++++++++++++++++--
3 files changed, 22 insertions(+), 3 deletions(-)
diff --git a/tcg/arm/tcg-target-conset.h b/tcg/arm/tcg-target-conset.h
index f32bf44f8b..30a5953621 100644
--- a/tcg/arm/tcg-target-conset.h
+++ b/tcg/arm/tcg-target-conset.h
@@ -29,6 +29,7 @@ C_O1_I2(w, w, w)
C_O1_I2(w, w, wO)
C_O1_I2(w, w, wV)
C_O1_I2(w, w, wZ)
+C_O1_I3(w, w, w, w)
C_O1_I4(r, r, r, rI, rI)
C_O1_I4(r, r, rIN, rIK, 0)
C_O2_I1(r, r, l)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index e3c533f00f..7463be8f27 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -168,7 +168,7 @@ extern bool use_neon_instructions;
#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 1
-#define TCG_TARGET_HAS_bitsel_vec 0
+#define TCG_TARGET_HAS_bitsel_vec 1
#define TCG_TARGET_HAS_cmpsel_vec 0
#define TCG_TARGET_DEFAULT_MO (0)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 6e17082df2..aea3d2cf8f 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -216,6 +216,10 @@ typedef enum {
INSN_VSARI = 0xf2800010, /* VSHR.S */
INSN_VSHRI = 0xf3800010, /* VSHR.U */
+ INSN_VBSL = 0xf3100110,
+ INSN_VBIT = 0xf3200110,
+ INSN_VBIF = 0xf3300110,
+
INSN_VTST = 0xf2000810,
INSN_VDUP_G = 0xee800b10, /* VDUP (ARM core register) */
@@ -2400,7 +2404,8 @@ static int tcg_target_op_def(TCGOpcode op)
return C_O1_I2(w, w, wV);
case INDEX_op_cmp_vec:
return C_O1_I2(w, w, wZ);
-
+ case INDEX_op_bitsel_vec:
+ return C_O1_I3(w, w, w, w);
default:
g_assert_not_reached();
}
@@ -2721,7 +2726,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
{
TCGType type = vecl + TCG_TYPE_V64;
unsigned q = vecl;
- TCGArg a0, a1, a2;
+ TCGArg a0, a1, a2, a3;
int cmode, imm8;
a0 = args[0];
@@ -2872,6 +2877,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
}
return;
+ case INDEX_op_bitsel_vec:
+ a3 = args[3];
+ if (a0 == a3) {
+ tcg_out_vreg3(s, INSN_VBIT, q, 0, a0, a2, a1);
+ } else if (a0 == a2) {
+ tcg_out_vreg3(s, INSN_VBIF, q, 0, a0, a3, a1);
+ } else {
+ tcg_out_mov(s, type, a0, a1);
+ tcg_out_vreg3(s, INSN_VBSL, q, 0, a0, a2, a3);
+ }
+ return;
+
case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
default:
@@ -2897,6 +2914,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_sssub_vec:
case INDEX_op_usadd_vec:
case INDEX_op_ussub_vec:
+ case INDEX_op_bitsel_vec:
return 1;
case INDEX_op_abs_vec:
case INDEX_op_cmp_vec:
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 13/15] tcg/arm: Implement TCG_TARGET_HAS_shv_vec
2020-12-24 22:44 [PATCH 00/15] tcg/arm: host neon support Richard Henderson
` (11 preceding siblings ...)
2020-12-24 22:45 ` [PATCH 12/15] tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec Richard Henderson
@ 2020-12-24 22:45 ` Richard Henderson
2020-12-24 22:45 ` [PATCH 14/15] tcg/arm: Implement TCG_TARGET_HAS_roti_vec Richard Henderson
2020-12-24 22:45 ` [PATCH 15/15] tcg/arm: Implement TCG_TARGET_HAS_rotv_vec Richard Henderson
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2020-12-24 22:45 UTC (permalink / raw)
To: qemu-devel
The three vector shift by vector operations are all implemented via
expansion. Therefore do not actually set TCG_TARGET_HAS_shv_vec,
as none of shlv_vec, shrv_vec, sarv_vec may actually appear in the
instruction stream, and therefore also do not appear in tcg_target_op_def.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target.opc.h | 3 ++
tcg/arm/tcg-target.c.inc | 60 +++++++++++++++++++++++++++++++++++++++-
2 files changed, 62 insertions(+), 1 deletion(-)
diff --git a/tcg/arm/tcg-target.opc.h b/tcg/arm/tcg-target.opc.h
index 7a4578e9b4..d19153dcb9 100644
--- a/tcg/arm/tcg-target.opc.h
+++ b/tcg/arm/tcg-target.opc.h
@@ -10,3 +10,6 @@
* emitted by tcg_expand_vec_op. For those familiar with GCC internals,
* consider these to be UNSPEC with names.
*/
+
+DEF(arm_sshl_vec, 1, 2, 0, IMPLVEC)
+DEF(arm_ushl_vec, 1, 2, 0, IMPLVEC)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index aea3d2cf8f..2a664a750d 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -215,6 +215,8 @@ typedef enum {
INSN_VSHLI = 0xf2800510, /* VSHL (immediate) */
INSN_VSARI = 0xf2800010, /* VSHR.S */
INSN_VSHRI = 0xf3800010, /* VSHR.U */
+ INSN_VSHL_S = 0xf2000400, /* VSHL.S (register) */
+ INSN_VSHL_U = 0xf3000400, /* VSHL.U (register) */
INSN_VBSL = 0xf3100110,
INSN_VBIT = 0xf3200110,
@@ -2395,6 +2397,8 @@ static int tcg_target_op_def(TCGOpcode op)
case INDEX_op_usadd_vec:
case INDEX_op_ussub_vec:
case INDEX_op_xor_vec:
+ case INDEX_op_arm_sshl_vec:
+ case INDEX_op_arm_ushl_vec:
return C_O1_I2(w, w, w);
case INDEX_op_or_vec:
case INDEX_op_andc_vec:
@@ -2791,6 +2795,17 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_xor_vec:
tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
return;
+ case INDEX_op_arm_sshl_vec:
+ /*
+ * Note that Vm is the data and Vn is the shift count,
+ * therefore the arguments appear reversed.
+ */
+ tcg_out_vreg3(s, INSN_VSHL_S, q, vece, a0, a2, a1);
+ return;
+ case INDEX_op_arm_ushl_vec:
+ /* See above. */
+ tcg_out_vreg3(s, INSN_VSHL_U, q, vece, a0, a2, a1);
+ return;
case INDEX_op_shli_vec:
tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece));
return;
@@ -2925,6 +2940,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_umax_vec:
case INDEX_op_umin_vec:
return vece < MO_64;
+ case INDEX_op_shlv_vec:
+ case INDEX_op_shrv_vec:
+ case INDEX_op_sarv_vec:
+ return -1;
default:
return 0;
}
@@ -2933,7 +2952,46 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
TCGArg a0, ...)
{
- g_assert_not_reached();
+ va_list va;
+ TCGv_vec v0, v1, v2, t1;
+ TCGArg a2;
+
+ va_start(va, a0);
+ v0 = temp_tcgv_vec(arg_temp(a0));
+ v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
+ a2 = va_arg(va, TCGArg);
+ v2 = temp_tcgv_vec(arg_temp(a2));
+
+ switch (opc) {
+ case INDEX_op_shlv_vec:
+ /*
+ * Merely propagate shlv_vec to arm_ushl_vec.
+ * In this way we don't set TCG_TARGET_HAS_shv_vec
+ * because everything is done via expansion.
+ */
+ vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0),
+ tcgv_vec_arg(v1), tcgv_vec_arg(v2));
+ break;
+
+ case INDEX_op_shrv_vec:
+ case INDEX_op_sarv_vec:
+ /* Right shifts are negative left shifts for NEON. */
+ t1 = tcg_temp_new_vec(type);
+ tcg_gen_neg_vec(vece, t1, v2);
+ if (opc == INDEX_op_shrv_vec) {
+ opc = INDEX_op_arm_ushl_vec;
+ } else {
+ opc = INDEX_op_arm_sshl_vec;
+ }
+ vec_gen_3(opc, type, vece, tcgv_vec_arg(v0),
+ tcgv_vec_arg(v1), tcgv_vec_arg(t1));
+ tcg_temp_free_vec(t1);
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+ va_end(va);
}
static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 14/15] tcg/arm: Implement TCG_TARGET_HAS_roti_vec
2020-12-24 22:44 [PATCH 00/15] tcg/arm: host neon support Richard Henderson
` (12 preceding siblings ...)
2020-12-24 22:45 ` [PATCH 13/15] tcg/arm: Implement TCG_TARGET_HAS_shv_vec Richard Henderson
@ 2020-12-24 22:45 ` Richard Henderson
2020-12-24 22:45 ` [PATCH 15/15] tcg/arm: Implement TCG_TARGET_HAS_rotv_vec Richard Henderson
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2020-12-24 22:45 UTC (permalink / raw)
To: qemu-devel
Implement via expansion, so don't actually set TCG_TARGET_HAS_roti_vec.
For NEON, this is shift-right followed by shift-left-and-insert.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target-conset.h | 1 +
tcg/arm/tcg-target.opc.h | 1 +
tcg/arm/tcg-target.c.inc | 15 +++++++++++++++
3 files changed, 17 insertions(+)
diff --git a/tcg/arm/tcg-target-conset.h b/tcg/arm/tcg-target-conset.h
index 30a5953621..efb63396de 100644
--- a/tcg/arm/tcg-target-conset.h
+++ b/tcg/arm/tcg-target-conset.h
@@ -25,6 +25,7 @@ C_O1_I2(r, r, rIK)
C_O1_I2(r, r, rIN)
C_O1_I2(r, r, ri)
C_O1_I2(r, rZ, rZ)
+C_O1_I2(w, 0, w)
C_O1_I2(w, w, w)
C_O1_I2(w, w, wO)
C_O1_I2(w, w, wV)
diff --git a/tcg/arm/tcg-target.opc.h b/tcg/arm/tcg-target.opc.h
index d19153dcb9..d38af9a808 100644
--- a/tcg/arm/tcg-target.opc.h
+++ b/tcg/arm/tcg-target.opc.h
@@ -11,5 +11,6 @@
* consider these to be UNSPEC with names.
*/
+DEF(arm_sli_vec, 1, 2, 1, IMPLVEC)
DEF(arm_sshl_vec, 1, 2, 0, IMPLVEC)
DEF(arm_ushl_vec, 1, 2, 0, IMPLVEC)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 2a664a750d..5cae6b2749 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -215,6 +215,7 @@ typedef enum {
INSN_VSHLI = 0xf2800510, /* VSHL (immediate) */
INSN_VSARI = 0xf2800010, /* VSHR.S */
INSN_VSHRI = 0xf3800010, /* VSHR.U */
+ INSN_VSLI = 0xf3800510,
INSN_VSHL_S = 0xf2000400, /* VSHL.S (register) */
INSN_VSHL_U = 0xf3000400, /* VSHL.U (register) */
@@ -2400,6 +2401,8 @@ static int tcg_target_op_def(TCGOpcode op)
case INDEX_op_arm_sshl_vec:
case INDEX_op_arm_ushl_vec:
return C_O1_I2(w, w, w);
+ case INDEX_op_arm_sli_vec:
+ return C_O1_I2(w, 0, w);
case INDEX_op_or_vec:
case INDEX_op_andc_vec:
return C_O1_I2(w, w, wO);
@@ -2815,6 +2818,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_sari_vec:
tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2);
return;
+ case INDEX_op_arm_sli_vec:
+ tcg_out_vshifti(s, INSN_VSLI, q, a0, a2, args[3] + (8 << vece));
+ return;
case INDEX_op_andc_vec:
if (!const_args[2]) {
@@ -2943,6 +2949,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_shlv_vec:
case INDEX_op_shrv_vec:
case INDEX_op_sarv_vec:
+ case INDEX_op_rotli_vec:
return -1;
default:
return 0;
@@ -2988,6 +2995,14 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
tcg_temp_free_vec(t1);
break;
+ case INDEX_op_rotli_vec:
+ t1 = tcg_temp_new_vec(type);
+ tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1));
+ vec_gen_4(INDEX_op_arm_sli_vec, type, vece,
+ tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2);
+ tcg_temp_free_vec(t1);
+ break;
+
default:
g_assert_not_reached();
}
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 15/15] tcg/arm: Implement TCG_TARGET_HAS_rotv_vec
2020-12-24 22:44 [PATCH 00/15] tcg/arm: host neon support Richard Henderson
` (13 preceding siblings ...)
2020-12-24 22:45 ` [PATCH 14/15] tcg/arm: Implement TCG_TARGET_HAS_roti_vec Richard Henderson
@ 2020-12-24 22:45 ` Richard Henderson
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2020-12-24 22:45 UTC (permalink / raw)
To: qemu-devel
Implement via expansion, so don't actually set TCG_TARGET_HAS_rotv_vec.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target.c.inc | 33 ++++++++++++++++++++++++++++++++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 5cae6b2749..f107478877 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -2950,6 +2950,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_shrv_vec:
case INDEX_op_sarv_vec:
case INDEX_op_rotli_vec:
+ case INDEX_op_rotlv_vec:
+ case INDEX_op_rotrv_vec:
return -1;
default:
return 0;
@@ -2960,7 +2962,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
TCGArg a0, ...)
{
va_list va;
- TCGv_vec v0, v1, v2, t1;
+ TCGv_vec v0, v1, v2, t1, t2, t3;
TCGArg a2;
va_start(va, a0);
@@ -3003,6 +3005,35 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
tcg_temp_free_vec(t1);
break;
+ case INDEX_op_rotlv_vec:
+ t1 = tcg_temp_new_vec(type);
+ t2 = tcg_constant_vec(type, vece, 8 << vece);
+ tcg_gen_sub_vec(vece, t1, v2, t2);
+ /* Right shifts are negative left shifts for AArch64. */
+ vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1),
+ tcgv_vec_arg(v1), tcgv_vec_arg(t1));
+ vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0),
+ tcgv_vec_arg(v1), tcgv_vec_arg(v2));
+ tcg_gen_or_vec(vece, v0, v0, t1);
+ tcg_temp_free_vec(t1);
+ break;
+
+ case INDEX_op_rotrv_vec:
+ t1 = tcg_temp_new_vec(type);
+ t2 = tcg_temp_new_vec(type);
+ t3 = tcg_constant_vec(type, vece, 8 << vece);
+ tcg_gen_neg_vec(vece, t1, v2);
+ tcg_gen_sub_vec(vece, t2, t3, v2);
+ /* Right shifts are negative left shifts for AArch64. */
+ vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1),
+ tcgv_vec_arg(v1), tcgv_vec_arg(t1));
+ vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t2),
+ tcgv_vec_arg(v1), tcgv_vec_arg(t2));
+ tcg_gen_or_vec(vece, v0, t1, t2);
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+ break;
+
default:
g_assert_not_reached();
}
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
end of thread, other threads:[~2020-12-24 22:59 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-12-24 22:44 [PATCH 00/15] tcg/arm: host neon support Richard Henderson
2020-12-24 22:45 ` [PATCH 01/15] tcg/arm: Add host vector framework Richard Henderson
2020-12-24 22:45 ` [PATCH 02/15] tcg/arm: Implement tcg_out_ld/st for vector types Richard Henderson
2020-12-24 22:45 ` [PATCH 03/15] tcg/arm: Implement tcg_out_mov " Richard Henderson
2020-12-24 22:45 ` [PATCH 04/15] tcg/arm: Implement tcg_out_dup*_vec Richard Henderson
2020-12-24 22:45 ` [PATCH 05/15] tcg: Change parameters for tcg_target_const_match Richard Henderson
2020-12-24 22:45 ` [PATCH 06/15] tcg/arm: Implement minimal vector operations Richard Henderson
2020-12-24 22:45 ` [PATCH 07/15] tcg/arm: Implement andc, orc, abs, neg, not " Richard Henderson
2020-12-24 22:45 ` [PATCH 08/15] tcg/arm: Implement TCG_TARGET_HAS_shi_vec Richard Henderson
2020-12-24 22:45 ` [PATCH 09/15] tcg/arm: Implement TCG_TARGET_HAS_mul_vec Richard Henderson
2020-12-24 22:45 ` [PATCH 10/15] tcg/arm: Implement TCG_TARGET_HAS_sat_vec Richard Henderson
2020-12-24 22:45 ` [PATCH 11/15] tcg/arm: Implement TCG_TARGET_HAS_minmax_vec Richard Henderson
2020-12-24 22:45 ` [PATCH 12/15] tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec Richard Henderson
2020-12-24 22:45 ` [PATCH 13/15] tcg/arm: Implement TCG_TARGET_HAS_shv_vec Richard Henderson
2020-12-24 22:45 ` [PATCH 14/15] tcg/arm: Implement TCG_TARGET_HAS_roti_vec Richard Henderson
2020-12-24 22:45 ` [PATCH 15/15] tcg/arm: Implement TCG_TARGET_HAS_rotv_vec Richard Henderson
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