* [Intel-gfx] [PATCH 00/13] drm/i915/dp: split out pps and aux
@ 2020-12-22 14:49 Jani Nikula
2020-12-22 14:49 ` [Intel-gfx] [PATCH 01/13] drm/i915/pps: abstract panel power sequencer from intel_dp.c Jani Nikula
` (15 more replies)
0 siblings, 16 replies; 35+ messages in thread
From: Jani Nikula @ 2020-12-22 14:49 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Clean up intel_dp.c pre-emptively before Dave gets here. ;)
Split out pps and aux code to intel_pps.[ch] and intel_dp_aux.[ch],
respectively.
This reduces intel_dp.c size by 2k lines:
- 8370 drivers/gpu/drm/i915/display/intel_dp.c
+ 6313 drivers/gpu/drm/i915/display/intel_dp.c
The pps code is pretty messy, so I've first done almost pure code
movement, and added interface cleanups on top in smaller bits for easier
review. The patches can be squashed together, but I figured it's easier
this way. There's still room for improvement, but it's a good start to
move the code to a separate file.
BR,
Jani.
Jani Nikula (13):
drm/i915/pps: abstract panel power sequencer from intel_dp.c
drm/i915/pps: rename pps_{,un}lock -> intel_pps_{,un}lock
drm/i915/pps: rename intel_edp_backlight_* to intel_pps_backlight_*
drm/i915/pps: rename intel_edp_panel_* to intel_pps_*
drm/i915/pps: rename edp_panel_* to intel_pps_*_unlocked
drm/i915/pps: abstract intel_pps_vdd_off_sync
drm/i915/pps: add higher level intel_pps_init() call
drm/i915/pps: abstract intel_pps_reinit()
drm/i915/pps: rename intel_dp_check_edp to
intel_pps_check_power_unlocked
drm/i915/pps: rename intel_power_sequencer_reset to
intel_pps_reset_all
drm/i915/pps: add locked intel_pps_wait_power_cycle
drm/i915/pps: rename vlv_init_panel_power_sequencer to vlv_pps_init
drm/i915/dp: split out aux functionality to intel_dp_aux.c
drivers/gpu/drm/i915/Makefile | 2 +
drivers/gpu/drm/i915/display/intel_ddi.c | 9 +-
.../drm/i915/display/intel_display_power.c | 6 +-
drivers/gpu/drm/i915/display/intel_dp.c | 2235 +----------------
drivers/gpu/drm/i915/display/intel_dp.h | 5 +-
drivers/gpu/drm/i915/display/intel_dp_aux.c | 683 +++++
drivers/gpu/drm/i915/display/intel_dp_aux.h | 18 +
drivers/gpu/drm/i915/display/intel_pps.c | 1393 ++++++++++
drivers/gpu/drm/i915/display/intel_pps.h | 49 +
9 files changed, 2243 insertions(+), 2157 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_dp_aux.c
create mode 100644 drivers/gpu/drm/i915/display/intel_dp_aux.h
create mode 100644 drivers/gpu/drm/i915/display/intel_pps.c
create mode 100644 drivers/gpu/drm/i915/display/intel_pps.h
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* [Intel-gfx] [PATCH 01/13] drm/i915/pps: abstract panel power sequencer from intel_dp.c
2020-12-22 14:49 [Intel-gfx] [PATCH 00/13] drm/i915/dp: split out pps and aux Jani Nikula
@ 2020-12-22 14:49 ` Jani Nikula
2020-12-28 11:22 ` Gupta, Anshuman
2020-12-22 14:49 ` [Intel-gfx] [PATCH 02/13] drm/i915/pps: rename pps_{, un}lock -> intel_pps_{, un}lock Jani Nikula
` (14 subsequent siblings)
15 siblings, 1 reply; 35+ messages in thread
From: Jani Nikula @ 2020-12-22 14:49 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
In a long overdue refactoring, split out all panel sequencer code from
intel_dp.c to new intel_pps.[ch].
The first part is mostly just code movement as-is, without cleanups.
We need to add a vlv_get_dpll() helper to get at the vlv/chv dpll from
pps code.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
.../drm/i915/display/intel_display_power.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 1442 +----------------
drivers/gpu/drm/i915/display/intel_dp.h | 5 +-
drivers/gpu/drm/i915/display/intel_pps.c | 1337 +++++++++++++++
drivers/gpu/drm/i915/display/intel_pps.h | 53 +
7 files changed, 1447 insertions(+), 1394 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_pps.c
create mode 100644 drivers/gpu/drm/i915/display/intel_pps.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 3a439b1d0496..1e26902a86e5 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -250,6 +250,7 @@ i915-y += \
display/intel_lspcon.o \
display/intel_lvds.o \
display/intel_panel.o \
+ display/intel_pps.o \
display/intel_sdvo.o \
display/intel_tv.o \
display/intel_vdsc.o \
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 6863236df1d0..9ddbe8b8730b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -46,6 +46,7 @@
#include "intel_hotplug.h"
#include "intel_lspcon.h"
#include "intel_panel.h"
+#include "intel_pps.h"
#include "intel_psr.h"
#include "intel_sprite.h"
#include "intel_tc.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index d52374f01316..a11bd8213df4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4,7 +4,6 @@
*/
#include "display/intel_crt.h"
-#include "display/intel_dp.h"
#include "i915_drv.h"
#include "i915_irq.h"
@@ -16,6 +15,7 @@
#include "intel_dpio_phy.h"
#include "intel_hotplug.h"
#include "intel_pm.h"
+#include "intel_pps.h"
#include "intel_sideband.h"
#include "intel_tc.h"
#include "intel_vga.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index b2bc0c8c39c7..d4760c478653 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -58,6 +58,7 @@
#include "intel_lspcon.h"
#include "intel_lvds.h"
#include "intel_panel.h"
+#include "intel_pps.h"
#include "intel_psr.h"
#include "intel_sideband.h"
#include "intel_tc.h"
@@ -121,6 +122,11 @@ static const struct dp_link_dpll chv_dpll[] = {
{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
};
+const struct dpll *vlv_get_dpll(struct drm_i915_private *i915)
+{
+ return IS_CHERRYVIEW(i915) ? &chv_dpll[0].dpll : &vlv_dpll[0].dpll;
+}
+
/* Constants for DP DSC configurations */
static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
@@ -145,12 +151,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
static void intel_dp_link_down(struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state);
-static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
-static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
-static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state);
-static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
- enum pipe pipe);
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
/* update sink rates from dpcd */
@@ -854,451 +854,6 @@ static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
dst[i] = src >> ((3-i) * 8);
}
-static void
-intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
-static void
-intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
- bool force_disable_vdd);
-static void
-intel_dp_pps_init(struct intel_dp *intel_dp);
-
-static intel_wakeref_t
-pps_lock(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- intel_wakeref_t wakeref;
-
- /*
- * See intel_power_sequencer_reset() why we need
- * a power domain reference here.
- */
- wakeref = intel_display_power_get(dev_priv,
- intel_aux_power_domain(dp_to_dig_port(intel_dp)));
-
- mutex_lock(&dev_priv->pps_mutex);
-
- return wakeref;
-}
-
-static intel_wakeref_t
-pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-
- mutex_unlock(&dev_priv->pps_mutex);
- intel_display_power_put(dev_priv,
- intel_aux_power_domain(dp_to_dig_port(intel_dp)),
- wakeref);
- return 0;
-}
-
-#define with_pps_lock(dp, wf) \
- for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
-
-static void
-vlv_power_sequencer_kick(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- enum pipe pipe = intel_dp->pps_pipe;
- bool pll_enabled, release_cl_override = false;
- enum dpio_phy phy = DPIO_PHY(pipe);
- enum dpio_channel ch = vlv_pipe_to_channel(pipe);
- u32 DP;
-
- if (drm_WARN(&dev_priv->drm,
- intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN,
- "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n",
- pipe_name(pipe), dig_port->base.base.base.id,
- dig_port->base.base.name))
- return;
-
- drm_dbg_kms(&dev_priv->drm,
- "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",
- pipe_name(pipe), dig_port->base.base.base.id,
- dig_port->base.base.name);
-
- /* Preserve the BIOS-computed detected bit. This is
- * supposed to be read-only.
- */
- DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
- DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
- DP |= DP_PORT_WIDTH(1);
- DP |= DP_LINK_TRAIN_PAT_1;
-
- if (IS_CHERRYVIEW(dev_priv))
- DP |= DP_PIPE_SEL_CHV(pipe);
- else
- DP |= DP_PIPE_SEL(pipe);
-
- pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
-
- /*
- * The DPLL for the pipe must be enabled for this to work.
- * So enable temporarily it if it's not already enabled.
- */
- if (!pll_enabled) {
- release_cl_override = IS_CHERRYVIEW(dev_priv) &&
- !chv_phy_powergate_ch(dev_priv, phy, ch, true);
-
- if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
- &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
- drm_err(&dev_priv->drm,
- "Failed to force on pll for pipe %c!\n",
- pipe_name(pipe));
- return;
- }
- }
-
- /*
- * Similar magic as in intel_dp_enable_port().
- * We _must_ do this port enable + disable trick
- * to make this power sequencer lock onto the port.
- * Otherwise even VDD force bit won't work.
- */
- intel_de_write(dev_priv, intel_dp->output_reg, DP);
- intel_de_posting_read(dev_priv, intel_dp->output_reg);
-
- intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN);
- intel_de_posting_read(dev_priv, intel_dp->output_reg);
-
- intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN);
- intel_de_posting_read(dev_priv, intel_dp->output_reg);
-
- if (!pll_enabled) {
- vlv_force_pll_off(dev_priv, pipe);
-
- if (release_cl_override)
- chv_phy_powergate_ch(dev_priv, phy, ch, false);
- }
-}
-
-static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
-{
- struct intel_encoder *encoder;
- unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
-
- /*
- * We don't have power sequencer currently.
- * Pick one that's not used by other ports.
- */
- for_each_intel_dp(&dev_priv->drm, encoder) {
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
- if (encoder->type == INTEL_OUTPUT_EDP) {
- drm_WARN_ON(&dev_priv->drm,
- intel_dp->active_pipe != INVALID_PIPE &&
- intel_dp->active_pipe !=
- intel_dp->pps_pipe);
-
- if (intel_dp->pps_pipe != INVALID_PIPE)
- pipes &= ~(1 << intel_dp->pps_pipe);
- } else {
- drm_WARN_ON(&dev_priv->drm,
- intel_dp->pps_pipe != INVALID_PIPE);
-
- if (intel_dp->active_pipe != INVALID_PIPE)
- pipes &= ~(1 << intel_dp->active_pipe);
- }
- }
-
- if (pipes == 0)
- return INVALID_PIPE;
-
- return ffs(pipes) - 1;
-}
-
-static enum pipe
-vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- enum pipe pipe;
-
- lockdep_assert_held(&dev_priv->pps_mutex);
-
- /* We should never land here with regular DP ports */
- drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
-
- drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE &&
- intel_dp->active_pipe != intel_dp->pps_pipe);
-
- if (intel_dp->pps_pipe != INVALID_PIPE)
- return intel_dp->pps_pipe;
-
- pipe = vlv_find_free_pps(dev_priv);
-
- /*
- * Didn't find one. This should not happen since there
- * are two power sequencers and up to two eDP ports.
- */
- if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE))
- pipe = PIPE_A;
-
- vlv_steal_power_sequencer(dev_priv, pipe);
- intel_dp->pps_pipe = pipe;
-
- drm_dbg_kms(&dev_priv->drm,
- "picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
- pipe_name(intel_dp->pps_pipe),
- dig_port->base.base.base.id,
- dig_port->base.base.name);
-
- /* init power sequencer on this pipe and port */
- intel_dp_init_panel_power_sequencer(intel_dp);
- intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
-
- /*
- * Even vdd force doesn't work until we've made
- * the power sequencer lock in on the port.
- */
- vlv_power_sequencer_kick(intel_dp);
-
- return intel_dp->pps_pipe;
-}
-
-static int
-bxt_power_sequencer_idx(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- int backlight_controller = dev_priv->vbt.backlight.controller;
-
- lockdep_assert_held(&dev_priv->pps_mutex);
-
- /* We should never land here with regular DP ports */
- drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
-
- if (!intel_dp->pps_reset)
- return backlight_controller;
-
- intel_dp->pps_reset = false;
-
- /*
- * Only the HW needs to be reprogrammed, the SW state is fixed and
- * has been setup during connector init.
- */
- intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
-
- return backlight_controller;
-}
-
-typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
- enum pipe pipe);
-
-static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
- enum pipe pipe)
-{
- return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON;
-}
-
-static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
- enum pipe pipe)
-{
- return intel_de_read(dev_priv, PP_CONTROL(pipe)) & EDP_FORCE_VDD;
-}
-
-static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
- enum pipe pipe)
-{
- return true;
-}
-
-static enum pipe
-vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
- enum port port,
- vlv_pipe_check pipe_check)
-{
- enum pipe pipe;
-
- for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
- u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) &
- PANEL_PORT_SELECT_MASK;
-
- if (port_sel != PANEL_PORT_SELECT_VLV(port))
- continue;
-
- if (!pipe_check(dev_priv, pipe))
- continue;
-
- return pipe;
- }
-
- return INVALID_PIPE;
-}
-
-static void
-vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- enum port port = dig_port->base.port;
-
- lockdep_assert_held(&dev_priv->pps_mutex);
-
- /* try to find a pipe with this port selected */
- /* first pick one where the panel is on */
- intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
- vlv_pipe_has_pp_on);
- /* didn't find one? pick one where vdd is on */
- if (intel_dp->pps_pipe == INVALID_PIPE)
- intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
- vlv_pipe_has_vdd_on);
- /* didn't find one? pick one with just the correct port */
- if (intel_dp->pps_pipe == INVALID_PIPE)
- intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
- vlv_pipe_any);
-
- /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
- if (intel_dp->pps_pipe == INVALID_PIPE) {
- drm_dbg_kms(&dev_priv->drm,
- "no initial power sequencer for [ENCODER:%d:%s]\n",
- dig_port->base.base.base.id,
- dig_port->base.base.name);
- return;
- }
-
- drm_dbg_kms(&dev_priv->drm,
- "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
- dig_port->base.base.base.id,
- dig_port->base.base.name,
- pipe_name(intel_dp->pps_pipe));
-
- intel_dp_init_panel_power_sequencer(intel_dp);
- intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
-}
-
-void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
-{
- struct intel_encoder *encoder;
-
- if (drm_WARN_ON(&dev_priv->drm,
- !(IS_VALLEYVIEW(dev_priv) ||
- IS_CHERRYVIEW(dev_priv) ||
- IS_GEN9_LP(dev_priv))))
- return;
-
- /*
- * We can't grab pps_mutex here due to deadlock with power_domain
- * mutex when power_domain functions are called while holding pps_mutex.
- * That also means that in order to use pps_pipe the code needs to
- * hold both a power domain reference and pps_mutex, and the power domain
- * reference get/put must be done while _not_ holding pps_mutex.
- * pps_{lock,unlock}() do these steps in the correct order, so one
- * should use them always.
- */
-
- for_each_intel_dp(&dev_priv->drm, encoder) {
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
- drm_WARN_ON(&dev_priv->drm,
- intel_dp->active_pipe != INVALID_PIPE);
-
- if (encoder->type != INTEL_OUTPUT_EDP)
- continue;
-
- if (IS_GEN9_LP(dev_priv))
- intel_dp->pps_reset = true;
- else
- intel_dp->pps_pipe = INVALID_PIPE;
- }
-}
-
-struct pps_registers {
- i915_reg_t pp_ctrl;
- i915_reg_t pp_stat;
- i915_reg_t pp_on;
- i915_reg_t pp_off;
- i915_reg_t pp_div;
-};
-
-static void intel_pps_get_registers(struct intel_dp *intel_dp,
- struct pps_registers *regs)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- int pps_idx = 0;
-
- memset(regs, 0, sizeof(*regs));
-
- if (IS_GEN9_LP(dev_priv))
- pps_idx = bxt_power_sequencer_idx(intel_dp);
- else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- pps_idx = vlv_power_sequencer_pipe(intel_dp);
-
- regs->pp_ctrl = PP_CONTROL(pps_idx);
- regs->pp_stat = PP_STATUS(pps_idx);
- regs->pp_on = PP_ON_DELAYS(pps_idx);
- regs->pp_off = PP_OFF_DELAYS(pps_idx);
-
- /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
- if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
- regs->pp_div = INVALID_MMIO_REG;
- else
- regs->pp_div = PP_DIVISOR(pps_idx);
-}
-
-static i915_reg_t
-_pp_ctrl_reg(struct intel_dp *intel_dp)
-{
- struct pps_registers regs;
-
- intel_pps_get_registers(intel_dp, ®s);
-
- return regs.pp_ctrl;
-}
-
-static i915_reg_t
-_pp_stat_reg(struct intel_dp *intel_dp)
-{
- struct pps_registers regs;
-
- intel_pps_get_registers(intel_dp, ®s);
-
- return regs.pp_stat;
-}
-
-static bool edp_have_panel_power(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-
- lockdep_assert_held(&dev_priv->pps_mutex);
-
- if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
- intel_dp->pps_pipe == INVALID_PIPE)
- return false;
-
- return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
-}
-
-static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-
- lockdep_assert_held(&dev_priv->pps_mutex);
-
- if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
- intel_dp->pps_pipe == INVALID_PIPE)
- return false;
-
- return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
-}
-
-static void
-intel_dp_check_edp(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-
- if (!intel_dp_is_edp(intel_dp))
- return;
-
- if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
- drm_WARN(&dev_priv->drm, 1,
- "eDP powered off while attempting aux channel communication.\n");
- drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control 0x%08x\n",
- intel_de_read(dev_priv, _pp_stat_reg(intel_dp)),
- intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)));
- }
-}
-
static u32
intel_dp_aux_wait_done(struct intel_dp *intel_dp)
{
@@ -2907,492 +2462,67 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
*
* IBX PCH and CPU are the same for almost everything,
* except that the CPU DP PLL is configured in this
- * register
- *
- * CPT PCH is quite different, having many bits moved
- * to the TRANS_DP_CTL register instead. That
- * configuration happens (oddly) in ilk_pch_enable
- */
-
- /* Preserve the BIOS-computed detected bit. This is
- * supposed to be read-only.
- */
- intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
-
- /* Handle DP bits in common between all three register formats */
- intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
- intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
-
- /* Split out the IBX/CPU vs CPT settings */
-
- if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
- if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
- intel_dp->DP |= DP_SYNC_HS_HIGH;
- if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
- intel_dp->DP |= DP_SYNC_VS_HIGH;
- intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
-
- if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
- intel_dp->DP |= DP_ENHANCED_FRAMING;
-
- intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
- } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
- u32 trans_dp;
-
- intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
-
- trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe));
- if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
- trans_dp |= TRANS_DP_ENH_FRAMING;
- else
- trans_dp &= ~TRANS_DP_ENH_FRAMING;
- intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe), trans_dp);
- } else {
- if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
- intel_dp->DP |= DP_COLOR_RANGE_16_235;
-
- if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
- intel_dp->DP |= DP_SYNC_HS_HIGH;
- if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
- intel_dp->DP |= DP_SYNC_VS_HIGH;
- intel_dp->DP |= DP_LINK_TRAIN_OFF;
-
- if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
- intel_dp->DP |= DP_ENHANCED_FRAMING;
-
- if (IS_CHERRYVIEW(dev_priv))
- intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
- else
- intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
- }
-}
-
-#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
-#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
-
-#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
-#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
-
-#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
-#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
-
-static void intel_pps_verify_state(struct intel_dp *intel_dp);
-
-static void wait_panel_status(struct intel_dp *intel_dp,
- u32 mask,
- u32 value)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- i915_reg_t pp_stat_reg, pp_ctrl_reg;
-
- lockdep_assert_held(&dev_priv->pps_mutex);
-
- intel_pps_verify_state(intel_dp);
-
- pp_stat_reg = _pp_stat_reg(intel_dp);
- pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
-
- drm_dbg_kms(&dev_priv->drm,
- "mask %08x value %08x status %08x control %08x\n",
- mask, value,
- intel_de_read(dev_priv, pp_stat_reg),
- intel_de_read(dev_priv, pp_ctrl_reg));
-
- if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
- mask, value, 5000))
- drm_err(&dev_priv->drm,
- "Panel status timeout: status %08x control %08x\n",
- intel_de_read(dev_priv, pp_stat_reg),
- intel_de_read(dev_priv, pp_ctrl_reg));
-
- drm_dbg_kms(&dev_priv->drm, "Wait complete\n");
-}
-
-static void wait_panel_on(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
-
- drm_dbg_kms(&i915->drm, "Wait for panel power on\n");
- wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
-}
-
-static void wait_panel_off(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
-
- drm_dbg_kms(&i915->drm, "Wait for panel power off time\n");
- wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
-}
-
-static void wait_panel_power_cycle(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- ktime_t panel_power_on_time;
- s64 panel_power_off_duration;
-
- drm_dbg_kms(&i915->drm, "Wait for panel power cycle\n");
-
- /* take the difference of currrent time and panel power off time
- * and then make panel wait for t11_t12 if needed. */
- panel_power_on_time = ktime_get_boottime();
- panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
-
- /* When we disable the VDD override bit last we have to do the manual
- * wait. */
- if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
- wait_remaining_ms_from_jiffies(jiffies,
- intel_dp->panel_power_cycle_delay - panel_power_off_duration);
-
- wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
-}
-
-static void wait_backlight_on(struct intel_dp *intel_dp)
-{
- wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
- intel_dp->backlight_on_delay);
-}
-
-static void edp_wait_backlight_off(struct intel_dp *intel_dp)
-{
- wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
- intel_dp->backlight_off_delay);
-}
-
-/* Read the current pp_control value, unlocking the register if it
- * is locked
- */
-
-static u32 ilk_get_pp_control(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- u32 control;
-
- lockdep_assert_held(&dev_priv->pps_mutex);
-
- control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
- if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) &&
- (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
- control &= ~PANEL_UNLOCK_MASK;
- control |= PANEL_UNLOCK_REGS;
- }
- return control;
-}
-
-/*
- * Must be paired with edp_panel_vdd_off().
- * Must hold pps_mutex around the whole on/off sequence.
- * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
- */
-static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- u32 pp;
- i915_reg_t pp_stat_reg, pp_ctrl_reg;
- bool need_to_disable = !intel_dp->want_panel_vdd;
-
- lockdep_assert_held(&dev_priv->pps_mutex);
-
- if (!intel_dp_is_edp(intel_dp))
- return false;
-
- cancel_delayed_work(&intel_dp->panel_vdd_work);
- intel_dp->want_panel_vdd = true;
-
- if (edp_have_panel_vdd(intel_dp))
- return need_to_disable;
-
- drm_WARN_ON(&dev_priv->drm, intel_dp->vdd_wakeref);
- intel_dp->vdd_wakeref = intel_display_power_get(dev_priv,
- intel_aux_power_domain(dig_port));
-
- drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n",
- dig_port->base.base.base.id,
- dig_port->base.base.name);
-
- if (!edp_have_panel_power(intel_dp))
- wait_panel_power_cycle(intel_dp);
-
- pp = ilk_get_pp_control(intel_dp);
- pp |= EDP_FORCE_VDD;
-
- pp_stat_reg = _pp_stat_reg(intel_dp);
- pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
-
- intel_de_write(dev_priv, pp_ctrl_reg, pp);
- intel_de_posting_read(dev_priv, pp_ctrl_reg);
- drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
- intel_de_read(dev_priv, pp_stat_reg),
- intel_de_read(dev_priv, pp_ctrl_reg));
- /*
- * If the panel wasn't on, delay before accessing aux channel
- */
- if (!edp_have_panel_power(intel_dp)) {
- drm_dbg_kms(&dev_priv->drm,
- "[ENCODER:%d:%s] panel power wasn't enabled\n",
- dig_port->base.base.base.id,
- dig_port->base.base.name);
- msleep(intel_dp->panel_power_up_delay);
- }
-
- return need_to_disable;
-}
-
-/*
- * Must be paired with intel_edp_panel_vdd_off() or
- * intel_edp_panel_off().
- * Nested calls to these functions are not allowed since
- * we drop the lock. Caller must use some higher level
- * locking to prevent nested calls from other threads.
- */
-void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
-{
- intel_wakeref_t wakeref;
- bool vdd;
-
- if (!intel_dp_is_edp(intel_dp))
- return;
-
- vdd = false;
- with_pps_lock(intel_dp, wakeref)
- vdd = edp_panel_vdd_on(intel_dp);
- I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",
- dp_to_dig_port(intel_dp)->base.base.base.id,
- dp_to_dig_port(intel_dp)->base.base.name);
-}
-
-static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port =
- dp_to_dig_port(intel_dp);
- u32 pp;
- i915_reg_t pp_stat_reg, pp_ctrl_reg;
-
- lockdep_assert_held(&dev_priv->pps_mutex);
-
- drm_WARN_ON(&dev_priv->drm, intel_dp->want_panel_vdd);
-
- if (!edp_have_panel_vdd(intel_dp))
- return;
-
- drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD off\n",
- dig_port->base.base.base.id,
- dig_port->base.base.name);
-
- pp = ilk_get_pp_control(intel_dp);
- pp &= ~EDP_FORCE_VDD;
-
- pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
- pp_stat_reg = _pp_stat_reg(intel_dp);
-
- intel_de_write(dev_priv, pp_ctrl_reg, pp);
- intel_de_posting_read(dev_priv, pp_ctrl_reg);
-
- /* Make sure sequencer is idle before allowing subsequent activity */
- drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
- intel_de_read(dev_priv, pp_stat_reg),
- intel_de_read(dev_priv, pp_ctrl_reg));
-
- if ((pp & PANEL_POWER_ON) == 0)
- intel_dp->panel_power_off_time = ktime_get_boottime();
-
- intel_display_power_put(dev_priv,
- intel_aux_power_domain(dig_port),
- fetch_and_zero(&intel_dp->vdd_wakeref));
-}
-
-static void edp_panel_vdd_work(struct work_struct *__work)
-{
- struct intel_dp *intel_dp =
- container_of(to_delayed_work(__work),
- struct intel_dp, panel_vdd_work);
- intel_wakeref_t wakeref;
-
- with_pps_lock(intel_dp, wakeref) {
- if (!intel_dp->want_panel_vdd)
- edp_panel_vdd_off_sync(intel_dp);
- }
-}
-
-static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
-{
- unsigned long delay;
-
- /*
- * Queue the timer to fire a long time from now (relative to the power
- * down delay) to keep the panel power up across a sequence of
- * operations.
- */
- delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
- schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
-}
-
-/*
- * Must be paired with edp_panel_vdd_on().
- * Must hold pps_mutex around the whole on/off sequence.
- * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
- */
-static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-
- lockdep_assert_held(&dev_priv->pps_mutex);
-
- if (!intel_dp_is_edp(intel_dp))
- return;
-
- I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
- dp_to_dig_port(intel_dp)->base.base.base.id,
- dp_to_dig_port(intel_dp)->base.base.name);
-
- intel_dp->want_panel_vdd = false;
-
- if (sync)
- edp_panel_vdd_off_sync(intel_dp);
- else
- edp_panel_vdd_schedule_off(intel_dp);
-}
-
-static void edp_panel_on(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- u32 pp;
- i915_reg_t pp_ctrl_reg;
-
- lockdep_assert_held(&dev_priv->pps_mutex);
-
- if (!intel_dp_is_edp(intel_dp))
- return;
-
- drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power on\n",
- dp_to_dig_port(intel_dp)->base.base.base.id,
- dp_to_dig_port(intel_dp)->base.base.name);
-
- if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp),
- "[ENCODER:%d:%s] panel power already on\n",
- dp_to_dig_port(intel_dp)->base.base.base.id,
- dp_to_dig_port(intel_dp)->base.base.name))
- return;
-
- wait_panel_power_cycle(intel_dp);
-
- pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
- pp = ilk_get_pp_control(intel_dp);
- if (IS_GEN(dev_priv, 5)) {
- /* ILK workaround: disable reset around power sequence */
- pp &= ~PANEL_POWER_RESET;
- intel_de_write(dev_priv, pp_ctrl_reg, pp);
- intel_de_posting_read(dev_priv, pp_ctrl_reg);
- }
-
- pp |= PANEL_POWER_ON;
- if (!IS_GEN(dev_priv, 5))
- pp |= PANEL_POWER_RESET;
-
- intel_de_write(dev_priv, pp_ctrl_reg, pp);
- intel_de_posting_read(dev_priv, pp_ctrl_reg);
-
- wait_panel_on(intel_dp);
- intel_dp->last_power_on = jiffies;
-
- if (IS_GEN(dev_priv, 5)) {
- pp |= PANEL_POWER_RESET; /* restore panel reset bit */
- intel_de_write(dev_priv, pp_ctrl_reg, pp);
- intel_de_posting_read(dev_priv, pp_ctrl_reg);
- }
-}
-
-void intel_edp_panel_on(struct intel_dp *intel_dp)
-{
- intel_wakeref_t wakeref;
-
- if (!intel_dp_is_edp(intel_dp))
- return;
-
- with_pps_lock(intel_dp, wakeref)
- edp_panel_on(intel_dp);
-}
-
-
-static void edp_panel_off(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- u32 pp;
- i915_reg_t pp_ctrl_reg;
-
- lockdep_assert_held(&dev_priv->pps_mutex);
-
- if (!intel_dp_is_edp(intel_dp))
- return;
-
- drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n",
- dig_port->base.base.base.id, dig_port->base.base.name);
-
- drm_WARN(&dev_priv->drm, !intel_dp->want_panel_vdd,
- "Need [ENCODER:%d:%s] VDD to turn off panel\n",
- dig_port->base.base.base.id, dig_port->base.base.name);
-
- pp = ilk_get_pp_control(intel_dp);
- /* We need to switch off panel power _and_ force vdd, for otherwise some
- * panels get very unhappy and cease to work. */
- pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
- EDP_BLC_ENABLE);
-
- pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
-
- intel_dp->want_panel_vdd = false;
+ * register
+ *
+ * CPT PCH is quite different, having many bits moved
+ * to the TRANS_DP_CTL register instead. That
+ * configuration happens (oddly) in ilk_pch_enable
+ */
- intel_de_write(dev_priv, pp_ctrl_reg, pp);
- intel_de_posting_read(dev_priv, pp_ctrl_reg);
+ /* Preserve the BIOS-computed detected bit. This is
+ * supposed to be read-only.
+ */
+ intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
- wait_panel_off(intel_dp);
- intel_dp->panel_power_off_time = ktime_get_boottime();
+ /* Handle DP bits in common between all three register formats */
+ intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
+ intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
- /* We got a reference when we enabled the VDD. */
- intel_display_power_put(dev_priv,
- intel_aux_power_domain(dig_port),
- fetch_and_zero(&intel_dp->vdd_wakeref));
-}
+ /* Split out the IBX/CPU vs CPT settings */
-void intel_edp_panel_off(struct intel_dp *intel_dp)
-{
- intel_wakeref_t wakeref;
+ if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
+ if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
+ intel_dp->DP |= DP_SYNC_HS_HIGH;
+ if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
+ intel_dp->DP |= DP_SYNC_VS_HIGH;
+ intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
- if (!intel_dp_is_edp(intel_dp))
- return;
+ if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
+ intel_dp->DP |= DP_ENHANCED_FRAMING;
- with_pps_lock(intel_dp, wakeref)
- edp_panel_off(intel_dp);
-}
+ intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
+ } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
+ u32 trans_dp;
-/* Enable backlight in the panel power control. */
-static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- intel_wakeref_t wakeref;
+ intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
- /*
- * If we enable the backlight right away following a panel power
- * on, we may see slight flicker as the panel syncs with the eDP
- * link. So delay a bit to make sure the image is solid before
- * allowing it to appear.
- */
- wait_backlight_on(intel_dp);
+ trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe));
+ if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
+ trans_dp |= TRANS_DP_ENH_FRAMING;
+ else
+ trans_dp &= ~TRANS_DP_ENH_FRAMING;
+ intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe), trans_dp);
+ } else {
+ if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
+ intel_dp->DP |= DP_COLOR_RANGE_16_235;
- with_pps_lock(intel_dp, wakeref) {
- i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
- u32 pp;
+ if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
+ intel_dp->DP |= DP_SYNC_HS_HIGH;
+ if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
+ intel_dp->DP |= DP_SYNC_VS_HIGH;
+ intel_dp->DP |= DP_LINK_TRAIN_OFF;
- pp = ilk_get_pp_control(intel_dp);
- pp |= EDP_BLC_ENABLE;
+ if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
+ intel_dp->DP |= DP_ENHANCED_FRAMING;
- intel_de_write(dev_priv, pp_ctrl_reg, pp);
- intel_de_posting_read(dev_priv, pp_ctrl_reg);
+ if (IS_CHERRYVIEW(dev_priv))
+ intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
+ else
+ intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
}
}
+
/* Enable backlight PWM and backlight PP control. */
void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
@@ -3409,30 +2539,6 @@ void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
_intel_edp_backlight_on(intel_dp);
}
-/* Disable backlight in the panel power control. */
-static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- intel_wakeref_t wakeref;
-
- if (!intel_dp_is_edp(intel_dp))
- return;
-
- with_pps_lock(intel_dp, wakeref) {
- i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
- u32 pp;
-
- pp = ilk_get_pp_control(intel_dp);
- pp &= ~EDP_BLC_ENABLE;
-
- intel_de_write(dev_priv, pp_ctrl_reg, pp);
- intel_de_posting_read(dev_priv, pp_ctrl_reg);
- }
-
- intel_dp->last_backlight_off = jiffies;
- edp_wait_backlight_off(intel_dp);
-}
-
/* Disable backlight PP control and backlight PWM. */
void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
{
@@ -3448,33 +2554,6 @@ void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
intel_panel_disable_backlight(old_conn_state);
}
-/*
- * Hook for controlling the panel power control backlight through the bl_power
- * sysfs attribute. Take care to handle multiple calls.
- */
-static void intel_edp_backlight_power(struct intel_connector *connector,
- bool enable)
-{
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
- struct intel_dp *intel_dp = intel_attached_dp(connector);
- intel_wakeref_t wakeref;
- bool is_enabled;
-
- is_enabled = false;
- with_pps_lock(intel_dp, wakeref)
- is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
- if (is_enabled == enable)
- return;
-
- drm_dbg_kms(&i915->drm, "panel power control backlight %s\n",
- enable ? "enable" : "disable");
-
- if (enable)
- _intel_edp_backlight_on(intel_dp);
- else
- _intel_edp_backlight_off(intel_dp);
-}
-
static void assert_dp_port(struct intel_dp *intel_dp, bool state)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -4139,112 +3218,6 @@ static void g4x_pre_enable_dp(struct intel_atomic_state *state,
ilk_edp_pll_on(intel_dp, pipe_config);
}
-static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
-{
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
- enum pipe pipe = intel_dp->pps_pipe;
- i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
-
- drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
-
- if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B))
- return;
-
- edp_panel_vdd_off_sync(intel_dp);
-
- /*
- * VLV seems to get confused when multiple power sequencers
- * have the same port selected (even if only one has power/vdd
- * enabled). The failure manifests as vlv_wait_port_ready() failing
- * CHV on the other hand doesn't seem to mind having the same port
- * selected in multiple power sequencers, but let's clear the
- * port select always when logically disconnecting a power sequencer
- * from a port.
- */
- drm_dbg_kms(&dev_priv->drm,
- "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n",
- pipe_name(pipe), dig_port->base.base.base.id,
- dig_port->base.base.name);
- intel_de_write(dev_priv, pp_on_reg, 0);
- intel_de_posting_read(dev_priv, pp_on_reg);
-
- intel_dp->pps_pipe = INVALID_PIPE;
-}
-
-static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
- enum pipe pipe)
-{
- struct intel_encoder *encoder;
-
- lockdep_assert_held(&dev_priv->pps_mutex);
-
- for_each_intel_dp(&dev_priv->drm, encoder) {
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
- drm_WARN(&dev_priv->drm, intel_dp->active_pipe == pipe,
- "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",
- pipe_name(pipe), encoder->base.base.id,
- encoder->base.name);
-
- if (intel_dp->pps_pipe != pipe)
- continue;
-
- drm_dbg_kms(&dev_priv->drm,
- "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n",
- pipe_name(pipe), encoder->base.base.id,
- encoder->base.name);
-
- /* make sure vdd is off before we steal it */
- vlv_detach_power_sequencer(intel_dp);
- }
-}
-
-static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state)
-{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-
- lockdep_assert_held(&dev_priv->pps_mutex);
-
- drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
-
- if (intel_dp->pps_pipe != INVALID_PIPE &&
- intel_dp->pps_pipe != crtc->pipe) {
- /*
- * If another power sequencer was being used on this
- * port previously make sure to turn off vdd there while
- * we still have control of it.
- */
- vlv_detach_power_sequencer(intel_dp);
- }
-
- /*
- * We may be stealing the power
- * sequencer from another port.
- */
- vlv_steal_power_sequencer(dev_priv, crtc->pipe);
-
- intel_dp->active_pipe = crtc->pipe;
-
- if (!intel_dp_is_edp(intel_dp))
- return;
-
- /* now it's all ours */
- intel_dp->pps_pipe = crtc->pipe;
-
- drm_dbg_kms(&dev_priv->drm,
- "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",
- pipe_name(intel_dp->pps_pipe), encoder->base.base.id,
- encoder->base.name);
-
- /* init power sequencer on this pipe and port */
- intel_dp_init_panel_power_sequencer(intel_dp);
- intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
-}
-
static void vlv_pre_enable_dp(struct intel_atomic_state *state,
struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config,
@@ -6888,31 +5861,6 @@ void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
wait_panel_power_cycle(intel_dp);
}
-static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-
- lockdep_assert_held(&dev_priv->pps_mutex);
-
- if (!edp_have_panel_vdd(intel_dp))
- return;
-
- /*
- * The VDD bit needs a power domain reference, so if the bit is
- * already enabled when we boot or resume, grab this reference and
- * schedule a vdd off, so we don't hold on to the reference
- * indefinitely.
- */
- drm_dbg_kms(&dev_priv->drm,
- "VDD left on by BIOS, adjusting state tracking\n");
- drm_WARN_ON(&dev_priv->drm, intel_dp->vdd_wakeref);
- intel_dp->vdd_wakeref = intel_display_power_get(dev_priv,
- intel_aux_power_domain(dig_port));
-
- edp_panel_vdd_schedule_off(intel_dp);
-}
-
static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -7118,19 +6066,6 @@ static const struct drm_encoder_funcs intel_dp_enc_funcs = {
.destroy = intel_dp_encoder_destroy,
};
-static bool intel_edp_have_power(struct intel_dp *intel_dp)
-{
- intel_wakeref_t wakeref;
- bool have_power = false;
-
- with_pps_lock(intel_dp, wakeref) {
- have_power = edp_have_panel_power(intel_dp) &&
- edp_have_panel_vdd(intel_dp);
- }
-
- return have_power;
-}
-
enum irqreturn
intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
{
@@ -7234,277 +6169,6 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
}
}
-static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
-{
- intel_dp->panel_power_off_time = ktime_get_boottime();
- intel_dp->last_power_on = jiffies;
- intel_dp->last_backlight_off = jiffies;
-}
-
-static void
-intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- u32 pp_on, pp_off, pp_ctl;
- struct pps_registers regs;
-
- intel_pps_get_registers(intel_dp, ®s);
-
- pp_ctl = ilk_get_pp_control(intel_dp);
-
- /* Ensure PPS is unlocked */
- if (!HAS_DDI(dev_priv))
- intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
-
- pp_on = intel_de_read(dev_priv, regs.pp_on);
- pp_off = intel_de_read(dev_priv, regs.pp_off);
-
- /* Pull timing values out of registers */
- seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
- seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
- seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
- seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
-
- if (i915_mmio_reg_valid(regs.pp_div)) {
- u32 pp_div;
-
- pp_div = intel_de_read(dev_priv, regs.pp_div);
-
- seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
- } else {
- seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
- }
-}
-
-static void
-intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
-{
- DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
- state_name,
- seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
-}
-
-static void
-intel_pps_verify_state(struct intel_dp *intel_dp)
-{
- struct edp_power_seq hw;
- struct edp_power_seq *sw = &intel_dp->pps_delays;
-
- intel_pps_readout_hw_state(intel_dp, &hw);
-
- if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
- hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
- DRM_ERROR("PPS state mismatch\n");
- intel_pps_dump_state("sw", sw);
- intel_pps_dump_state("hw", &hw);
- }
-}
-
-static void
-intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct edp_power_seq cur, vbt, spec,
- *final = &intel_dp->pps_delays;
-
- lockdep_assert_held(&dev_priv->pps_mutex);
-
- /* already initialized? */
- if (final->t11_t12 != 0)
- return;
-
- intel_pps_readout_hw_state(intel_dp, &cur);
-
- intel_pps_dump_state("cur", &cur);
-
- vbt = dev_priv->vbt.edp.pps;
- /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
- * of 500ms appears to be too short. Ocassionally the panel
- * just fails to power back on. Increasing the delay to 800ms
- * seems sufficient to avoid this problem.
- */
- if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
- vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
- drm_dbg_kms(&dev_priv->drm,
- "Increasing T12 panel delay as per the quirk to %d\n",
- vbt.t11_t12);
- }
- /* T11_T12 delay is special and actually in units of 100ms, but zero
- * based in the hw (so we need to add 100 ms). But the sw vbt
- * table multiplies it with 1000 to make it in units of 100usec,
- * too. */
- vbt.t11_t12 += 100 * 10;
-
- /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
- * our hw here, which are all in 100usec. */
- spec.t1_t3 = 210 * 10;
- spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
- spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
- spec.t10 = 500 * 10;
- /* This one is special and actually in units of 100ms, but zero
- * based in the hw (so we need to add 100 ms). But the sw vbt
- * table multiplies it with 1000 to make it in units of 100usec,
- * too. */
- spec.t11_t12 = (510 + 100) * 10;
-
- intel_pps_dump_state("vbt", &vbt);
-
- /* Use the max of the register settings and vbt. If both are
- * unset, fall back to the spec limits. */
-#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
- spec.field : \
- max(cur.field, vbt.field))
- assign_final(t1_t3);
- assign_final(t8);
- assign_final(t9);
- assign_final(t10);
- assign_final(t11_t12);
-#undef assign_final
-
-#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
- intel_dp->panel_power_up_delay = get_delay(t1_t3);
- intel_dp->backlight_on_delay = get_delay(t8);
- intel_dp->backlight_off_delay = get_delay(t9);
- intel_dp->panel_power_down_delay = get_delay(t10);
- intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
-#undef get_delay
-
- drm_dbg_kms(&dev_priv->drm,
- "panel power up delay %d, power down delay %d, power cycle delay %d\n",
- intel_dp->panel_power_up_delay,
- intel_dp->panel_power_down_delay,
- intel_dp->panel_power_cycle_delay);
-
- drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n",
- intel_dp->backlight_on_delay,
- intel_dp->backlight_off_delay);
-
- /*
- * We override the HW backlight delays to 1 because we do manual waits
- * on them. For T8, even BSpec recommends doing it. For T9, if we
- * don't do this, we'll end up waiting for the backlight off delay
- * twice: once when we do the manual sleep, and once when we disable
- * the panel and wait for the PP_STATUS bit to become zero.
- */
- final->t8 = 1;
- final->t9 = 1;
-
- /*
- * HW has only a 100msec granularity for t11_t12 so round it up
- * accordingly.
- */
- final->t11_t12 = roundup(final->t11_t12, 100 * 10);
-}
-
-static void
-intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
- bool force_disable_vdd)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- u32 pp_on, pp_off, port_sel = 0;
- int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
- struct pps_registers regs;
- enum port port = dp_to_dig_port(intel_dp)->base.port;
- const struct edp_power_seq *seq = &intel_dp->pps_delays;
-
- lockdep_assert_held(&dev_priv->pps_mutex);
-
- intel_pps_get_registers(intel_dp, ®s);
-
- /*
- * On some VLV machines the BIOS can leave the VDD
- * enabled even on power sequencers which aren't
- * hooked up to any port. This would mess up the
- * power domain tracking the first time we pick
- * one of these power sequencers for use since
- * edp_panel_vdd_on() would notice that the VDD was
- * already on and therefore wouldn't grab the power
- * domain reference. Disable VDD first to avoid this.
- * This also avoids spuriously turning the VDD on as
- * soon as the new power sequencer gets initialized.
- */
- if (force_disable_vdd) {
- u32 pp = ilk_get_pp_control(intel_dp);
-
- drm_WARN(&dev_priv->drm, pp & PANEL_POWER_ON,
- "Panel power already on\n");
-
- if (pp & EDP_FORCE_VDD)
- drm_dbg_kms(&dev_priv->drm,
- "VDD already on, disabling first\n");
-
- pp &= ~EDP_FORCE_VDD;
-
- intel_de_write(dev_priv, regs.pp_ctrl, pp);
- }
-
- pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
- REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
- pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
- REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
-
- /* Haswell doesn't have any port selection bits for the panel
- * power sequencer any more. */
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- port_sel = PANEL_PORT_SELECT_VLV(port);
- } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
- switch (port) {
- case PORT_A:
- port_sel = PANEL_PORT_SELECT_DPA;
- break;
- case PORT_C:
- port_sel = PANEL_PORT_SELECT_DPC;
- break;
- case PORT_D:
- port_sel = PANEL_PORT_SELECT_DPD;
- break;
- default:
- MISSING_CASE(port);
- break;
- }
- }
-
- pp_on |= port_sel;
-
- intel_de_write(dev_priv, regs.pp_on, pp_on);
- intel_de_write(dev_priv, regs.pp_off, pp_off);
-
- /*
- * Compute the divisor for the pp clock, simply match the Bspec formula.
- */
- if (i915_mmio_reg_valid(regs.pp_div)) {
- intel_de_write(dev_priv, regs.pp_div,
- REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
- } else {
- u32 pp_ctl;
-
- pp_ctl = intel_de_read(dev_priv, regs.pp_ctrl);
- pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
- pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
- intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
- }
-
- drm_dbg_kms(&dev_priv->drm,
- "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
- intel_de_read(dev_priv, regs.pp_on),
- intel_de_read(dev_priv, regs.pp_off),
- i915_mmio_reg_valid(regs.pp_div) ?
- intel_de_read(dev_priv, regs.pp_div) :
- (intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
-}
-
-static void intel_dp_pps_init(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- vlv_initial_power_sequencer_setup(intel_dp);
- } else {
- intel_dp_init_panel_power_sequencer(intel_dp);
- intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
- }
-}
-
/**
* intel_dp_set_drrs_state - program registers for RR switch to take effect
* @dev_priv: i915 device
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index b871a09b6901..87ace5d7f447 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -69,15 +69,11 @@ enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port,
void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
-void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
-void intel_edp_panel_on(struct intel_dp *intel_dp);
-void intel_edp_panel_off(struct intel_dp *intel_dp);
void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
int intel_dp_max_link_rate(struct intel_dp *intel_dp);
int intel_dp_max_lane_count(struct intel_dp *intel_dp);
int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
-void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
u32 intel_dp_pack_aux(const u8 *src, int src_bytes);
void intel_edp_drrs_enable(struct intel_dp *intel_dp,
@@ -143,5 +139,6 @@ bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state);
void intel_dp_sync_state(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
+const struct dpll *vlv_get_dpll(struct drm_i915_private *i915);
#endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
new file mode 100644
index 000000000000..cfe347076031
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -0,0 +1,1337 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "intel_display_types.h"
+#include "intel_dp.h"
+#include "intel_pps.h"
+
+static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
+ enum pipe pipe);
+static void
+intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
+static void
+intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
+ bool force_disable_vdd);
+
+intel_wakeref_t pps_lock(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ intel_wakeref_t wakeref;
+
+ /*
+ * See intel_power_sequencer_reset() why we need
+ * a power domain reference here.
+ */
+ wakeref = intel_display_power_get(dev_priv,
+ intel_aux_power_domain(dp_to_dig_port(intel_dp)));
+
+ mutex_lock(&dev_priv->pps_mutex);
+
+ return wakeref;
+}
+
+intel_wakeref_t pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ mutex_unlock(&dev_priv->pps_mutex);
+ intel_display_power_put(dev_priv,
+ intel_aux_power_domain(dp_to_dig_port(intel_dp)),
+ wakeref);
+ return 0;
+}
+
+static void
+vlv_power_sequencer_kick(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum pipe pipe = intel_dp->pps_pipe;
+ bool pll_enabled, release_cl_override = false;
+ enum dpio_phy phy = DPIO_PHY(pipe);
+ enum dpio_channel ch = vlv_pipe_to_channel(pipe);
+ u32 DP;
+
+ if (drm_WARN(&dev_priv->drm,
+ intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN,
+ "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n",
+ pipe_name(pipe), dig_port->base.base.base.id,
+ dig_port->base.base.name))
+ return;
+
+ drm_dbg_kms(&dev_priv->drm,
+ "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",
+ pipe_name(pipe), dig_port->base.base.base.id,
+ dig_port->base.base.name);
+
+ /* Preserve the BIOS-computed detected bit. This is
+ * supposed to be read-only.
+ */
+ DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
+ DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
+ DP |= DP_PORT_WIDTH(1);
+ DP |= DP_LINK_TRAIN_PAT_1;
+
+ if (IS_CHERRYVIEW(dev_priv))
+ DP |= DP_PIPE_SEL_CHV(pipe);
+ else
+ DP |= DP_PIPE_SEL(pipe);
+
+ pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
+
+ /*
+ * The DPLL for the pipe must be enabled for this to work.
+ * So enable temporarily it if it's not already enabled.
+ */
+ if (!pll_enabled) {
+ release_cl_override = IS_CHERRYVIEW(dev_priv) &&
+ !chv_phy_powergate_ch(dev_priv, phy, ch, true);
+
+ if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(dev_priv))) {
+ drm_err(&dev_priv->drm,
+ "Failed to force on pll for pipe %c!\n",
+ pipe_name(pipe));
+ return;
+ }
+ }
+
+ /*
+ * Similar magic as in intel_dp_enable_port().
+ * We _must_ do this port enable + disable trick
+ * to make this power sequencer lock onto the port.
+ * Otherwise even VDD force bit won't work.
+ */
+ intel_de_write(dev_priv, intel_dp->output_reg, DP);
+ intel_de_posting_read(dev_priv, intel_dp->output_reg);
+
+ intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN);
+ intel_de_posting_read(dev_priv, intel_dp->output_reg);
+
+ intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN);
+ intel_de_posting_read(dev_priv, intel_dp->output_reg);
+
+ if (!pll_enabled) {
+ vlv_force_pll_off(dev_priv, pipe);
+
+ if (release_cl_override)
+ chv_phy_powergate_ch(dev_priv, phy, ch, false);
+ }
+}
+
+static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
+{
+ struct intel_encoder *encoder;
+ unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
+
+ /*
+ * We don't have power sequencer currently.
+ * Pick one that's not used by other ports.
+ */
+ for_each_intel_dp(&dev_priv->drm, encoder) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ if (encoder->type == INTEL_OUTPUT_EDP) {
+ drm_WARN_ON(&dev_priv->drm,
+ intel_dp->active_pipe != INVALID_PIPE &&
+ intel_dp->active_pipe !=
+ intel_dp->pps_pipe);
+
+ if (intel_dp->pps_pipe != INVALID_PIPE)
+ pipes &= ~(1 << intel_dp->pps_pipe);
+ } else {
+ drm_WARN_ON(&dev_priv->drm,
+ intel_dp->pps_pipe != INVALID_PIPE);
+
+ if (intel_dp->active_pipe != INVALID_PIPE)
+ pipes &= ~(1 << intel_dp->active_pipe);
+ }
+ }
+
+ if (pipes == 0)
+ return INVALID_PIPE;
+
+ return ffs(pipes) - 1;
+}
+
+static enum pipe
+vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum pipe pipe;
+
+ lockdep_assert_held(&dev_priv->pps_mutex);
+
+ /* We should never land here with regular DP ports */
+ drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
+
+ drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE &&
+ intel_dp->active_pipe != intel_dp->pps_pipe);
+
+ if (intel_dp->pps_pipe != INVALID_PIPE)
+ return intel_dp->pps_pipe;
+
+ pipe = vlv_find_free_pps(dev_priv);
+
+ /*
+ * Didn't find one. This should not happen since there
+ * are two power sequencers and up to two eDP ports.
+ */
+ if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE))
+ pipe = PIPE_A;
+
+ vlv_steal_power_sequencer(dev_priv, pipe);
+ intel_dp->pps_pipe = pipe;
+
+ drm_dbg_kms(&dev_priv->drm,
+ "picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
+ pipe_name(intel_dp->pps_pipe),
+ dig_port->base.base.base.id,
+ dig_port->base.base.name);
+
+ /* init power sequencer on this pipe and port */
+ intel_dp_init_panel_power_sequencer(intel_dp);
+ intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
+
+ /*
+ * Even vdd force doesn't work until we've made
+ * the power sequencer lock in on the port.
+ */
+ vlv_power_sequencer_kick(intel_dp);
+
+ return intel_dp->pps_pipe;
+}
+
+static int
+bxt_power_sequencer_idx(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ int backlight_controller = dev_priv->vbt.backlight.controller;
+
+ lockdep_assert_held(&dev_priv->pps_mutex);
+
+ /* We should never land here with regular DP ports */
+ drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
+
+ if (!intel_dp->pps_reset)
+ return backlight_controller;
+
+ intel_dp->pps_reset = false;
+
+ /*
+ * Only the HW needs to be reprogrammed, the SW state is fixed and
+ * has been setup during connector init.
+ */
+ intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
+
+ return backlight_controller;
+}
+
+typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
+ enum pipe pipe);
+
+static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
+ enum pipe pipe)
+{
+ return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON;
+}
+
+static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
+ enum pipe pipe)
+{
+ return intel_de_read(dev_priv, PP_CONTROL(pipe)) & EDP_FORCE_VDD;
+}
+
+static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
+ enum pipe pipe)
+{
+ return true;
+}
+
+static enum pipe
+vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
+ enum port port,
+ vlv_pipe_check pipe_check)
+{
+ enum pipe pipe;
+
+ for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
+ u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) &
+ PANEL_PORT_SELECT_MASK;
+
+ if (port_sel != PANEL_PORT_SELECT_VLV(port))
+ continue;
+
+ if (!pipe_check(dev_priv, pipe))
+ continue;
+
+ return pipe;
+ }
+
+ return INVALID_PIPE;
+}
+
+static void
+vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum port port = dig_port->base.port;
+
+ lockdep_assert_held(&dev_priv->pps_mutex);
+
+ /* try to find a pipe with this port selected */
+ /* first pick one where the panel is on */
+ intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
+ vlv_pipe_has_pp_on);
+ /* didn't find one? pick one where vdd is on */
+ if (intel_dp->pps_pipe == INVALID_PIPE)
+ intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
+ vlv_pipe_has_vdd_on);
+ /* didn't find one? pick one with just the correct port */
+ if (intel_dp->pps_pipe == INVALID_PIPE)
+ intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
+ vlv_pipe_any);
+
+ /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
+ if (intel_dp->pps_pipe == INVALID_PIPE) {
+ drm_dbg_kms(&dev_priv->drm,
+ "no initial power sequencer for [ENCODER:%d:%s]\n",
+ dig_port->base.base.base.id,
+ dig_port->base.base.name);
+ return;
+ }
+
+ drm_dbg_kms(&dev_priv->drm,
+ "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
+ dig_port->base.base.base.id,
+ dig_port->base.base.name,
+ pipe_name(intel_dp->pps_pipe));
+
+ intel_dp_init_panel_power_sequencer(intel_dp);
+ intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
+}
+
+void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
+{
+ struct intel_encoder *encoder;
+
+ if (drm_WARN_ON(&dev_priv->drm,
+ !(IS_VALLEYVIEW(dev_priv) ||
+ IS_CHERRYVIEW(dev_priv) ||
+ IS_GEN9_LP(dev_priv))))
+ return;
+
+ /*
+ * We can't grab pps_mutex here due to deadlock with power_domain
+ * mutex when power_domain functions are called while holding pps_mutex.
+ * That also means that in order to use pps_pipe the code needs to
+ * hold both a power domain reference and pps_mutex, and the power domain
+ * reference get/put must be done while _not_ holding pps_mutex.
+ * pps_{lock,unlock}() do these steps in the correct order, so one
+ * should use them always.
+ */
+
+ for_each_intel_dp(&dev_priv->drm, encoder) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ drm_WARN_ON(&dev_priv->drm,
+ intel_dp->active_pipe != INVALID_PIPE);
+
+ if (encoder->type != INTEL_OUTPUT_EDP)
+ continue;
+
+ if (IS_GEN9_LP(dev_priv))
+ intel_dp->pps_reset = true;
+ else
+ intel_dp->pps_pipe = INVALID_PIPE;
+ }
+}
+
+struct pps_registers {
+ i915_reg_t pp_ctrl;
+ i915_reg_t pp_stat;
+ i915_reg_t pp_on;
+ i915_reg_t pp_off;
+ i915_reg_t pp_div;
+};
+
+static void intel_pps_get_registers(struct intel_dp *intel_dp,
+ struct pps_registers *regs)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ int pps_idx = 0;
+
+ memset(regs, 0, sizeof(*regs));
+
+ if (IS_GEN9_LP(dev_priv))
+ pps_idx = bxt_power_sequencer_idx(intel_dp);
+ else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+ pps_idx = vlv_power_sequencer_pipe(intel_dp);
+
+ regs->pp_ctrl = PP_CONTROL(pps_idx);
+ regs->pp_stat = PP_STATUS(pps_idx);
+ regs->pp_on = PP_ON_DELAYS(pps_idx);
+ regs->pp_off = PP_OFF_DELAYS(pps_idx);
+
+ /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
+ if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
+ regs->pp_div = INVALID_MMIO_REG;
+ else
+ regs->pp_div = PP_DIVISOR(pps_idx);
+}
+
+static i915_reg_t
+_pp_ctrl_reg(struct intel_dp *intel_dp)
+{
+ struct pps_registers regs;
+
+ intel_pps_get_registers(intel_dp, ®s);
+
+ return regs.pp_ctrl;
+}
+
+static i915_reg_t
+_pp_stat_reg(struct intel_dp *intel_dp)
+{
+ struct pps_registers regs;
+
+ intel_pps_get_registers(intel_dp, ®s);
+
+ return regs.pp_stat;
+}
+
+static bool edp_have_panel_power(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ lockdep_assert_held(&dev_priv->pps_mutex);
+
+ if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
+ intel_dp->pps_pipe == INVALID_PIPE)
+ return false;
+
+ return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
+}
+
+static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ lockdep_assert_held(&dev_priv->pps_mutex);
+
+ if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
+ intel_dp->pps_pipe == INVALID_PIPE)
+ return false;
+
+ return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
+}
+
+void intel_dp_check_edp(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ if (!intel_dp_is_edp(intel_dp))
+ return;
+
+ if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
+ drm_WARN(&dev_priv->drm, 1,
+ "eDP powered off while attempting aux channel communication.\n");
+ drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control 0x%08x\n",
+ intel_de_read(dev_priv, _pp_stat_reg(intel_dp)),
+ intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)));
+ }
+}
+
+#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
+#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
+
+#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
+#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
+
+#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
+#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
+
+static void intel_pps_verify_state(struct intel_dp *intel_dp);
+
+static void wait_panel_status(struct intel_dp *intel_dp,
+ u32 mask,
+ u32 value)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ i915_reg_t pp_stat_reg, pp_ctrl_reg;
+
+ lockdep_assert_held(&dev_priv->pps_mutex);
+
+ intel_pps_verify_state(intel_dp);
+
+ pp_stat_reg = _pp_stat_reg(intel_dp);
+ pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
+
+ drm_dbg_kms(&dev_priv->drm,
+ "mask %08x value %08x status %08x control %08x\n",
+ mask, value,
+ intel_de_read(dev_priv, pp_stat_reg),
+ intel_de_read(dev_priv, pp_ctrl_reg));
+
+ if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
+ mask, value, 5000))
+ drm_err(&dev_priv->drm,
+ "Panel status timeout: status %08x control %08x\n",
+ intel_de_read(dev_priv, pp_stat_reg),
+ intel_de_read(dev_priv, pp_ctrl_reg));
+
+ drm_dbg_kms(&dev_priv->drm, "Wait complete\n");
+}
+
+static void wait_panel_on(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+ drm_dbg_kms(&i915->drm, "Wait for panel power on\n");
+ wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
+}
+
+static void wait_panel_off(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+ drm_dbg_kms(&i915->drm, "Wait for panel power off time\n");
+ wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
+}
+
+void wait_panel_power_cycle(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ ktime_t panel_power_on_time;
+ s64 panel_power_off_duration;
+
+ drm_dbg_kms(&i915->drm, "Wait for panel power cycle\n");
+
+ /* take the difference of currrent time and panel power off time
+ * and then make panel wait for t11_t12 if needed. */
+ panel_power_on_time = ktime_get_boottime();
+ panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
+
+ /* When we disable the VDD override bit last we have to do the manual
+ * wait. */
+ if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
+ wait_remaining_ms_from_jiffies(jiffies,
+ intel_dp->panel_power_cycle_delay - panel_power_off_duration);
+
+ wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
+}
+
+static void wait_backlight_on(struct intel_dp *intel_dp)
+{
+ wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
+ intel_dp->backlight_on_delay);
+}
+
+static void edp_wait_backlight_off(struct intel_dp *intel_dp)
+{
+ wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
+ intel_dp->backlight_off_delay);
+}
+
+/* Read the current pp_control value, unlocking the register if it
+ * is locked
+ */
+
+static u32 ilk_get_pp_control(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ u32 control;
+
+ lockdep_assert_held(&dev_priv->pps_mutex);
+
+ control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
+ if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) &&
+ (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
+ control &= ~PANEL_UNLOCK_MASK;
+ control |= PANEL_UNLOCK_REGS;
+ }
+ return control;
+}
+
+/*
+ * Must be paired with edp_panel_vdd_off().
+ * Must hold pps_mutex around the whole on/off sequence.
+ * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
+ */
+bool edp_panel_vdd_on(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ u32 pp;
+ i915_reg_t pp_stat_reg, pp_ctrl_reg;
+ bool need_to_disable = !intel_dp->want_panel_vdd;
+
+ lockdep_assert_held(&dev_priv->pps_mutex);
+
+ if (!intel_dp_is_edp(intel_dp))
+ return false;
+
+ cancel_delayed_work(&intel_dp->panel_vdd_work);
+ intel_dp->want_panel_vdd = true;
+
+ if (edp_have_panel_vdd(intel_dp))
+ return need_to_disable;
+
+ drm_WARN_ON(&dev_priv->drm, intel_dp->vdd_wakeref);
+ intel_dp->vdd_wakeref = intel_display_power_get(dev_priv,
+ intel_aux_power_domain(dig_port));
+
+ drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n",
+ dig_port->base.base.base.id,
+ dig_port->base.base.name);
+
+ if (!edp_have_panel_power(intel_dp))
+ wait_panel_power_cycle(intel_dp);
+
+ pp = ilk_get_pp_control(intel_dp);
+ pp |= EDP_FORCE_VDD;
+
+ pp_stat_reg = _pp_stat_reg(intel_dp);
+ pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
+
+ intel_de_write(dev_priv, pp_ctrl_reg, pp);
+ intel_de_posting_read(dev_priv, pp_ctrl_reg);
+ drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
+ intel_de_read(dev_priv, pp_stat_reg),
+ intel_de_read(dev_priv, pp_ctrl_reg));
+ /*
+ * If the panel wasn't on, delay before accessing aux channel
+ */
+ if (!edp_have_panel_power(intel_dp)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "[ENCODER:%d:%s] panel power wasn't enabled\n",
+ dig_port->base.base.base.id,
+ dig_port->base.base.name);
+ msleep(intel_dp->panel_power_up_delay);
+ }
+
+ return need_to_disable;
+}
+
+/*
+ * Must be paired with intel_edp_panel_vdd_off() or
+ * intel_edp_panel_off().
+ * Nested calls to these functions are not allowed since
+ * we drop the lock. Caller must use some higher level
+ * locking to prevent nested calls from other threads.
+ */
+void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
+{
+ intel_wakeref_t wakeref;
+ bool vdd;
+
+ if (!intel_dp_is_edp(intel_dp))
+ return;
+
+ vdd = false;
+ with_pps_lock(intel_dp, wakeref)
+ vdd = edp_panel_vdd_on(intel_dp);
+ I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",
+ dp_to_dig_port(intel_dp)->base.base.base.id,
+ dp_to_dig_port(intel_dp)->base.base.name);
+}
+
+void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port =
+ dp_to_dig_port(intel_dp);
+ u32 pp;
+ i915_reg_t pp_stat_reg, pp_ctrl_reg;
+
+ lockdep_assert_held(&dev_priv->pps_mutex);
+
+ drm_WARN_ON(&dev_priv->drm, intel_dp->want_panel_vdd);
+
+ if (!edp_have_panel_vdd(intel_dp))
+ return;
+
+ drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD off\n",
+ dig_port->base.base.base.id,
+ dig_port->base.base.name);
+
+ pp = ilk_get_pp_control(intel_dp);
+ pp &= ~EDP_FORCE_VDD;
+
+ pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
+ pp_stat_reg = _pp_stat_reg(intel_dp);
+
+ intel_de_write(dev_priv, pp_ctrl_reg, pp);
+ intel_de_posting_read(dev_priv, pp_ctrl_reg);
+
+ /* Make sure sequencer is idle before allowing subsequent activity */
+ drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
+ intel_de_read(dev_priv, pp_stat_reg),
+ intel_de_read(dev_priv, pp_ctrl_reg));
+
+ if ((pp & PANEL_POWER_ON) == 0)
+ intel_dp->panel_power_off_time = ktime_get_boottime();
+
+ intel_display_power_put(dev_priv,
+ intel_aux_power_domain(dig_port),
+ fetch_and_zero(&intel_dp->vdd_wakeref));
+}
+
+void edp_panel_vdd_work(struct work_struct *__work)
+{
+ struct intel_dp *intel_dp =
+ container_of(to_delayed_work(__work),
+ struct intel_dp, panel_vdd_work);
+ intel_wakeref_t wakeref;
+
+ with_pps_lock(intel_dp, wakeref) {
+ if (!intel_dp->want_panel_vdd)
+ edp_panel_vdd_off_sync(intel_dp);
+ }
+}
+
+static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
+{
+ unsigned long delay;
+
+ /*
+ * Queue the timer to fire a long time from now (relative to the power
+ * down delay) to keep the panel power up across a sequence of
+ * operations.
+ */
+ delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
+ schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
+}
+
+/*
+ * Must be paired with edp_panel_vdd_on().
+ * Must hold pps_mutex around the whole on/off sequence.
+ * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
+ */
+void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ lockdep_assert_held(&dev_priv->pps_mutex);
+
+ if (!intel_dp_is_edp(intel_dp))
+ return;
+
+ I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
+ dp_to_dig_port(intel_dp)->base.base.base.id,
+ dp_to_dig_port(intel_dp)->base.base.name);
+
+ intel_dp->want_panel_vdd = false;
+
+ if (sync)
+ edp_panel_vdd_off_sync(intel_dp);
+ else
+ edp_panel_vdd_schedule_off(intel_dp);
+}
+
+void edp_panel_on(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ u32 pp;
+ i915_reg_t pp_ctrl_reg;
+
+ lockdep_assert_held(&dev_priv->pps_mutex);
+
+ if (!intel_dp_is_edp(intel_dp))
+ return;
+
+ drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power on\n",
+ dp_to_dig_port(intel_dp)->base.base.base.id,
+ dp_to_dig_port(intel_dp)->base.base.name);
+
+ if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp),
+ "[ENCODER:%d:%s] panel power already on\n",
+ dp_to_dig_port(intel_dp)->base.base.base.id,
+ dp_to_dig_port(intel_dp)->base.base.name))
+ return;
+
+ wait_panel_power_cycle(intel_dp);
+
+ pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
+ pp = ilk_get_pp_control(intel_dp);
+ if (IS_GEN(dev_priv, 5)) {
+ /* ILK workaround: disable reset around power sequence */
+ pp &= ~PANEL_POWER_RESET;
+ intel_de_write(dev_priv, pp_ctrl_reg, pp);
+ intel_de_posting_read(dev_priv, pp_ctrl_reg);
+ }
+
+ pp |= PANEL_POWER_ON;
+ if (!IS_GEN(dev_priv, 5))
+ pp |= PANEL_POWER_RESET;
+
+ intel_de_write(dev_priv, pp_ctrl_reg, pp);
+ intel_de_posting_read(dev_priv, pp_ctrl_reg);
+
+ wait_panel_on(intel_dp);
+ intel_dp->last_power_on = jiffies;
+
+ if (IS_GEN(dev_priv, 5)) {
+ pp |= PANEL_POWER_RESET; /* restore panel reset bit */
+ intel_de_write(dev_priv, pp_ctrl_reg, pp);
+ intel_de_posting_read(dev_priv, pp_ctrl_reg);
+ }
+}
+
+void intel_edp_panel_on(struct intel_dp *intel_dp)
+{
+ intel_wakeref_t wakeref;
+
+ if (!intel_dp_is_edp(intel_dp))
+ return;
+
+ with_pps_lock(intel_dp, wakeref)
+ edp_panel_on(intel_dp);
+}
+
+void edp_panel_off(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ u32 pp;
+ i915_reg_t pp_ctrl_reg;
+
+ lockdep_assert_held(&dev_priv->pps_mutex);
+
+ if (!intel_dp_is_edp(intel_dp))
+ return;
+
+ drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n",
+ dig_port->base.base.base.id, dig_port->base.base.name);
+
+ drm_WARN(&dev_priv->drm, !intel_dp->want_panel_vdd,
+ "Need [ENCODER:%d:%s] VDD to turn off panel\n",
+ dig_port->base.base.base.id, dig_port->base.base.name);
+
+ pp = ilk_get_pp_control(intel_dp);
+ /* We need to switch off panel power _and_ force vdd, for otherwise some
+ * panels get very unhappy and cease to work. */
+ pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
+ EDP_BLC_ENABLE);
+
+ pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
+
+ intel_dp->want_panel_vdd = false;
+
+ intel_de_write(dev_priv, pp_ctrl_reg, pp);
+ intel_de_posting_read(dev_priv, pp_ctrl_reg);
+
+ wait_panel_off(intel_dp);
+ intel_dp->panel_power_off_time = ktime_get_boottime();
+
+ /* We got a reference when we enabled the VDD. */
+ intel_display_power_put(dev_priv,
+ intel_aux_power_domain(dig_port),
+ fetch_and_zero(&intel_dp->vdd_wakeref));
+}
+
+void intel_edp_panel_off(struct intel_dp *intel_dp)
+{
+ intel_wakeref_t wakeref;
+
+ if (!intel_dp_is_edp(intel_dp))
+ return;
+
+ with_pps_lock(intel_dp, wakeref)
+ edp_panel_off(intel_dp);
+}
+
+/* Enable backlight in the panel power control. */
+void _intel_edp_backlight_on(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ intel_wakeref_t wakeref;
+
+ /*
+ * If we enable the backlight right away following a panel power
+ * on, we may see slight flicker as the panel syncs with the eDP
+ * link. So delay a bit to make sure the image is solid before
+ * allowing it to appear.
+ */
+ wait_backlight_on(intel_dp);
+
+ with_pps_lock(intel_dp, wakeref) {
+ i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
+ u32 pp;
+
+ pp = ilk_get_pp_control(intel_dp);
+ pp |= EDP_BLC_ENABLE;
+
+ intel_de_write(dev_priv, pp_ctrl_reg, pp);
+ intel_de_posting_read(dev_priv, pp_ctrl_reg);
+ }
+}
+
+/* Disable backlight in the panel power control. */
+void _intel_edp_backlight_off(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ intel_wakeref_t wakeref;
+
+ if (!intel_dp_is_edp(intel_dp))
+ return;
+
+ with_pps_lock(intel_dp, wakeref) {
+ i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
+ u32 pp;
+
+ pp = ilk_get_pp_control(intel_dp);
+ pp &= ~EDP_BLC_ENABLE;
+
+ intel_de_write(dev_priv, pp_ctrl_reg, pp);
+ intel_de_posting_read(dev_priv, pp_ctrl_reg);
+ }
+
+ intel_dp->last_backlight_off = jiffies;
+ edp_wait_backlight_off(intel_dp);
+}
+
+/*
+ * Hook for controlling the panel power control backlight through the bl_power
+ * sysfs attribute. Take care to handle multiple calls.
+ */
+void intel_edp_backlight_power(struct intel_connector *connector, bool enable)
+{
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct intel_dp *intel_dp = intel_attached_dp(connector);
+ intel_wakeref_t wakeref;
+ bool is_enabled;
+
+ is_enabled = false;
+ with_pps_lock(intel_dp, wakeref)
+ is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
+ if (is_enabled == enable)
+ return;
+
+ drm_dbg_kms(&i915->drm, "panel power control backlight %s\n",
+ enable ? "enable" : "disable");
+
+ if (enable)
+ _intel_edp_backlight_on(intel_dp);
+ else
+ _intel_edp_backlight_off(intel_dp);
+}
+
+static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+ enum pipe pipe = intel_dp->pps_pipe;
+ i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
+
+ drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
+
+ if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B))
+ return;
+
+ edp_panel_vdd_off_sync(intel_dp);
+
+ /*
+ * VLV seems to get confused when multiple power sequencers
+ * have the same port selected (even if only one has power/vdd
+ * enabled). The failure manifests as vlv_wait_port_ready() failing
+ * CHV on the other hand doesn't seem to mind having the same port
+ * selected in multiple power sequencers, but let's clear the
+ * port select always when logically disconnecting a power sequencer
+ * from a port.
+ */
+ drm_dbg_kms(&dev_priv->drm,
+ "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n",
+ pipe_name(pipe), dig_port->base.base.base.id,
+ dig_port->base.base.name);
+ intel_de_write(dev_priv, pp_on_reg, 0);
+ intel_de_posting_read(dev_priv, pp_on_reg);
+
+ intel_dp->pps_pipe = INVALID_PIPE;
+}
+
+static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
+ enum pipe pipe)
+{
+ struct intel_encoder *encoder;
+
+ lockdep_assert_held(&dev_priv->pps_mutex);
+
+ for_each_intel_dp(&dev_priv->drm, encoder) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ drm_WARN(&dev_priv->drm, intel_dp->active_pipe == pipe,
+ "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",
+ pipe_name(pipe), encoder->base.base.id,
+ encoder->base.name);
+
+ if (intel_dp->pps_pipe != pipe)
+ continue;
+
+ drm_dbg_kms(&dev_priv->drm,
+ "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n",
+ pipe_name(pipe), encoder->base.base.id,
+ encoder->base.name);
+
+ /* make sure vdd is off before we steal it */
+ vlv_detach_power_sequencer(intel_dp);
+ }
+}
+
+void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+ lockdep_assert_held(&dev_priv->pps_mutex);
+
+ drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
+
+ if (intel_dp->pps_pipe != INVALID_PIPE &&
+ intel_dp->pps_pipe != crtc->pipe) {
+ /*
+ * If another power sequencer was being used on this
+ * port previously make sure to turn off vdd there while
+ * we still have control of it.
+ */
+ vlv_detach_power_sequencer(intel_dp);
+ }
+
+ /*
+ * We may be stealing the power
+ * sequencer from another port.
+ */
+ vlv_steal_power_sequencer(dev_priv, crtc->pipe);
+
+ intel_dp->active_pipe = crtc->pipe;
+
+ if (!intel_dp_is_edp(intel_dp))
+ return;
+
+ /* now it's all ours */
+ intel_dp->pps_pipe = crtc->pipe;
+
+ drm_dbg_kms(&dev_priv->drm,
+ "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",
+ pipe_name(intel_dp->pps_pipe), encoder->base.base.id,
+ encoder->base.name);
+
+ /* init power sequencer on this pipe and port */
+ intel_dp_init_panel_power_sequencer(intel_dp);
+ intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
+}
+
+void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+
+ lockdep_assert_held(&dev_priv->pps_mutex);
+
+ if (!edp_have_panel_vdd(intel_dp))
+ return;
+
+ /*
+ * The VDD bit needs a power domain reference, so if the bit is
+ * already enabled when we boot or resume, grab this reference and
+ * schedule a vdd off, so we don't hold on to the reference
+ * indefinitely.
+ */
+ drm_dbg_kms(&dev_priv->drm,
+ "VDD left on by BIOS, adjusting state tracking\n");
+ drm_WARN_ON(&dev_priv->drm, intel_dp->vdd_wakeref);
+ intel_dp->vdd_wakeref = intel_display_power_get(dev_priv,
+ intel_aux_power_domain(dig_port));
+
+ edp_panel_vdd_schedule_off(intel_dp);
+}
+
+bool intel_edp_have_power(struct intel_dp *intel_dp)
+{
+ intel_wakeref_t wakeref;
+ bool have_power = false;
+
+ with_pps_lock(intel_dp, wakeref) {
+ have_power = edp_have_panel_power(intel_dp) &&
+ edp_have_panel_vdd(intel_dp);
+ }
+
+ return have_power;
+}
+
+void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
+{
+ intel_dp->panel_power_off_time = ktime_get_boottime();
+ intel_dp->last_power_on = jiffies;
+ intel_dp->last_backlight_off = jiffies;
+}
+
+static void
+intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ u32 pp_on, pp_off, pp_ctl;
+ struct pps_registers regs;
+
+ intel_pps_get_registers(intel_dp, ®s);
+
+ pp_ctl = ilk_get_pp_control(intel_dp);
+
+ /* Ensure PPS is unlocked */
+ if (!HAS_DDI(dev_priv))
+ intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
+
+ pp_on = intel_de_read(dev_priv, regs.pp_on);
+ pp_off = intel_de_read(dev_priv, regs.pp_off);
+
+ /* Pull timing values out of registers */
+ seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
+ seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
+ seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
+ seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
+
+ if (i915_mmio_reg_valid(regs.pp_div)) {
+ u32 pp_div;
+
+ pp_div = intel_de_read(dev_priv, regs.pp_div);
+
+ seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
+ } else {
+ seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
+ }
+}
+
+static void
+intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
+{
+ DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
+ state_name,
+ seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
+}
+
+static void
+intel_pps_verify_state(struct intel_dp *intel_dp)
+{
+ struct edp_power_seq hw;
+ struct edp_power_seq *sw = &intel_dp->pps_delays;
+
+ intel_pps_readout_hw_state(intel_dp, &hw);
+
+ if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
+ hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
+ DRM_ERROR("PPS state mismatch\n");
+ intel_pps_dump_state("sw", sw);
+ intel_pps_dump_state("hw", &hw);
+ }
+}
+
+static void
+intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct edp_power_seq cur, vbt, spec,
+ *final = &intel_dp->pps_delays;
+
+ lockdep_assert_held(&dev_priv->pps_mutex);
+
+ /* already initialized? */
+ if (final->t11_t12 != 0)
+ return;
+
+ intel_pps_readout_hw_state(intel_dp, &cur);
+
+ intel_pps_dump_state("cur", &cur);
+
+ vbt = dev_priv->vbt.edp.pps;
+ /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
+ * of 500ms appears to be too short. Ocassionally the panel
+ * just fails to power back on. Increasing the delay to 800ms
+ * seems sufficient to avoid this problem.
+ */
+ if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
+ vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
+ drm_dbg_kms(&dev_priv->drm,
+ "Increasing T12 panel delay as per the quirk to %d\n",
+ vbt.t11_t12);
+ }
+ /* T11_T12 delay is special and actually in units of 100ms, but zero
+ * based in the hw (so we need to add 100 ms). But the sw vbt
+ * table multiplies it with 1000 to make it in units of 100usec,
+ * too. */
+ vbt.t11_t12 += 100 * 10;
+
+ /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
+ * our hw here, which are all in 100usec. */
+ spec.t1_t3 = 210 * 10;
+ spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
+ spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
+ spec.t10 = 500 * 10;
+ /* This one is special and actually in units of 100ms, but zero
+ * based in the hw (so we need to add 100 ms). But the sw vbt
+ * table multiplies it with 1000 to make it in units of 100usec,
+ * too. */
+ spec.t11_t12 = (510 + 100) * 10;
+
+ intel_pps_dump_state("vbt", &vbt);
+
+ /* Use the max of the register settings and vbt. If both are
+ * unset, fall back to the spec limits. */
+#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
+ spec.field : \
+ max(cur.field, vbt.field))
+ assign_final(t1_t3);
+ assign_final(t8);
+ assign_final(t9);
+ assign_final(t10);
+ assign_final(t11_t12);
+#undef assign_final
+
+#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
+ intel_dp->panel_power_up_delay = get_delay(t1_t3);
+ intel_dp->backlight_on_delay = get_delay(t8);
+ intel_dp->backlight_off_delay = get_delay(t9);
+ intel_dp->panel_power_down_delay = get_delay(t10);
+ intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
+#undef get_delay
+
+ drm_dbg_kms(&dev_priv->drm,
+ "panel power up delay %d, power down delay %d, power cycle delay %d\n",
+ intel_dp->panel_power_up_delay,
+ intel_dp->panel_power_down_delay,
+ intel_dp->panel_power_cycle_delay);
+
+ drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n",
+ intel_dp->backlight_on_delay,
+ intel_dp->backlight_off_delay);
+
+ /*
+ * We override the HW backlight delays to 1 because we do manual waits
+ * on them. For T8, even BSpec recommends doing it. For T9, if we
+ * don't do this, we'll end up waiting for the backlight off delay
+ * twice: once when we do the manual sleep, and once when we disable
+ * the panel and wait for the PP_STATUS bit to become zero.
+ */
+ final->t8 = 1;
+ final->t9 = 1;
+
+ /*
+ * HW has only a 100msec granularity for t11_t12 so round it up
+ * accordingly.
+ */
+ final->t11_t12 = roundup(final->t11_t12, 100 * 10);
+}
+
+static void
+intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
+ bool force_disable_vdd)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ u32 pp_on, pp_off, port_sel = 0;
+ int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
+ struct pps_registers regs;
+ enum port port = dp_to_dig_port(intel_dp)->base.port;
+ const struct edp_power_seq *seq = &intel_dp->pps_delays;
+
+ lockdep_assert_held(&dev_priv->pps_mutex);
+
+ intel_pps_get_registers(intel_dp, ®s);
+
+ /*
+ * On some VLV machines the BIOS can leave the VDD
+ * enabled even on power sequencers which aren't
+ * hooked up to any port. This would mess up the
+ * power domain tracking the first time we pick
+ * one of these power sequencers for use since
+ * edp_panel_vdd_on() would notice that the VDD was
+ * already on and therefore wouldn't grab the power
+ * domain reference. Disable VDD first to avoid this.
+ * This also avoids spuriously turning the VDD on as
+ * soon as the new power sequencer gets initialized.
+ */
+ if (force_disable_vdd) {
+ u32 pp = ilk_get_pp_control(intel_dp);
+
+ drm_WARN(&dev_priv->drm, pp & PANEL_POWER_ON,
+ "Panel power already on\n");
+
+ if (pp & EDP_FORCE_VDD)
+ drm_dbg_kms(&dev_priv->drm,
+ "VDD already on, disabling first\n");
+
+ pp &= ~EDP_FORCE_VDD;
+
+ intel_de_write(dev_priv, regs.pp_ctrl, pp);
+ }
+
+ pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
+ REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
+ pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
+ REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
+
+ /* Haswell doesn't have any port selection bits for the panel
+ * power sequencer any more. */
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+ port_sel = PANEL_PORT_SELECT_VLV(port);
+ } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
+ switch (port) {
+ case PORT_A:
+ port_sel = PANEL_PORT_SELECT_DPA;
+ break;
+ case PORT_C:
+ port_sel = PANEL_PORT_SELECT_DPC;
+ break;
+ case PORT_D:
+ port_sel = PANEL_PORT_SELECT_DPD;
+ break;
+ default:
+ MISSING_CASE(port);
+ break;
+ }
+ }
+
+ pp_on |= port_sel;
+
+ intel_de_write(dev_priv, regs.pp_on, pp_on);
+ intel_de_write(dev_priv, regs.pp_off, pp_off);
+
+ /*
+ * Compute the divisor for the pp clock, simply match the Bspec formula.
+ */
+ if (i915_mmio_reg_valid(regs.pp_div)) {
+ intel_de_write(dev_priv, regs.pp_div,
+ REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
+ } else {
+ u32 pp_ctl;
+
+ pp_ctl = intel_de_read(dev_priv, regs.pp_ctrl);
+ pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
+ pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
+ intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
+ }
+
+ drm_dbg_kms(&dev_priv->drm,
+ "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
+ intel_de_read(dev_priv, regs.pp_on),
+ intel_de_read(dev_priv, regs.pp_off),
+ i915_mmio_reg_valid(regs.pp_div) ?
+ intel_de_read(dev_priv, regs.pp_div) :
+ (intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
+}
+
+void intel_dp_pps_init(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+ vlv_initial_power_sequencer_setup(intel_dp);
+ } else {
+ intel_dp_init_panel_power_sequencer(intel_dp);
+ intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
+ }
+}
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
new file mode 100644
index 000000000000..76d5cc565501
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#ifndef __INTEL_PPS_H__
+#define __INTEL_PPS_H__
+
+#include <linux/types.h>
+
+#include "intel_wakeref.h"
+
+struct drm_i915_private;
+struct intel_connector;
+struct intel_crtc_state;
+struct intel_dp;
+struct intel_encoder;
+
+intel_wakeref_t pps_lock(struct intel_dp *intel_dp);
+intel_wakeref_t pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref);
+
+#define with_pps_lock(dp, wf) \
+ for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
+
+void intel_dp_check_edp(struct intel_dp *intel_dp);
+void _intel_edp_backlight_on(struct intel_dp *intel_dp);
+void _intel_edp_backlight_off(struct intel_dp *intel_dp);
+void intel_edp_backlight_power(struct intel_connector *connector, bool enable);
+
+bool edp_panel_vdd_on(struct intel_dp *intel_dp);
+void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
+void edp_panel_vdd_off_sync(struct intel_dp *intel_dp);
+void edp_panel_on(struct intel_dp *intel_dp);
+void edp_panel_off(struct intel_dp *intel_dp);
+void edp_panel_vdd_work(struct work_struct *__work);
+
+void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
+void intel_edp_panel_on(struct intel_dp *intel_dp);
+void intel_edp_panel_off(struct intel_dp *intel_dp);
+bool intel_edp_have_power(struct intel_dp *intel_dp);
+
+void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp);
+
+void wait_panel_power_cycle(struct intel_dp *intel_dp);
+
+void intel_dp_pps_init(struct intel_dp *intel_dp);
+void intel_power_sequencer_reset(struct drm_i915_private *i915);
+void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp);
+
+void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
+
+#endif /* __INTEL_PPS_H__ */
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Intel-gfx] [PATCH 02/13] drm/i915/pps: rename pps_{, un}lock -> intel_pps_{, un}lock
2020-12-22 14:49 [Intel-gfx] [PATCH 00/13] drm/i915/dp: split out pps and aux Jani Nikula
2020-12-22 14:49 ` [Intel-gfx] [PATCH 01/13] drm/i915/pps: abstract panel power sequencer from intel_dp.c Jani Nikula
@ 2020-12-22 14:49 ` Jani Nikula
2020-12-28 10:57 ` Gupta, Anshuman
2020-12-22 14:49 ` [Intel-gfx] [PATCH 03/13] drm/i915/pps: rename intel_edp_backlight_* to intel_pps_backlight_* Jani Nikula
` (13 subsequent siblings)
15 siblings, 1 reply; 35+ messages in thread
From: Jani Nikula @ 2020-12-22 14:49 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Start following the usual naming pattern for functions.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 20 ++++++++++----------
drivers/gpu/drm/i915/display/intel_pps.c | 21 +++++++++++----------
drivers/gpu/drm/i915/display/intel_pps.h | 8 ++++----
3 files changed, 25 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d4760c478653..0870872fb594 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1030,7 +1030,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
aux_domain = intel_aux_power_domain(dig_port);
aux_wakeref = intel_display_power_get(i915, aux_domain);
- pps_wakeref = pps_lock(intel_dp);
+ pps_wakeref = intel_pps_lock(intel_dp);
/*
* We will be called with VDD already enabled for dpcd/edid/oui reads.
@@ -1182,7 +1182,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
if (vdd)
edp_panel_vdd_off(intel_dp, false);
- pps_unlock(intel_dp, pps_wakeref);
+ intel_pps_unlock(intel_dp, pps_wakeref);
intel_display_power_put_async(i915, aux_domain, aux_wakeref);
if (is_tc_port)
@@ -3153,7 +3153,7 @@ static void intel_enable_dp(struct intel_atomic_state *state,
if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN))
return;
- with_pps_lock(intel_dp, wakeref) {
+ with_intel_pps_lock(intel_dp, wakeref) {
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_init_panel_power_sequencer(encoder, pipe_config);
@@ -3719,7 +3719,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
intel_wakeref_t wakeref;
- with_pps_lock(intel_dp, wakeref)
+ with_intel_pps_lock(intel_dp, wakeref)
intel_dp->active_pipe = INVALID_PIPE;
}
}
@@ -5817,7 +5817,7 @@ void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
* vdd might still be enabled do to the delayed vdd off.
* Make sure vdd is actually turned off here.
*/
- with_pps_lock(intel_dp, wakeref)
+ with_intel_pps_lock(intel_dp, wakeref)
edp_panel_vdd_off_sync(intel_dp);
}
@@ -5845,7 +5845,7 @@ void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
* Make sure vdd is actually turned off here.
*/
cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
- with_pps_lock(intel_dp, wakeref)
+ with_intel_pps_lock(intel_dp, wakeref)
edp_panel_vdd_off_sync(intel_dp);
}
@@ -5857,7 +5857,7 @@ void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
if (!intel_dp_is_edp(intel_dp))
return;
- with_pps_lock(intel_dp, wakeref)
+ with_intel_pps_lock(intel_dp, wakeref)
wait_panel_power_cycle(intel_dp);
}
@@ -5889,7 +5889,7 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder)
!intel_dp_is_edp(intel_dp))
return;
- with_pps_lock(intel_dp, wakeref) {
+ with_intel_pps_lock(intel_dp, wakeref) {
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
intel_dp->active_pipe = vlv_active_pipe(intel_dp);
@@ -6628,7 +6628,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
return false;
}
- with_pps_lock(intel_dp, wakeref) {
+ with_intel_pps_lock(intel_dp, wakeref) {
intel_dp_init_panel_power_timestamps(intel_dp);
intel_dp_pps_init(intel_dp);
intel_edp_panel_vdd_sanitize(intel_dp);
@@ -6705,7 +6705,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
* vdd might still be enabled do to the delayed vdd off.
* Make sure vdd is actually turned off here.
*/
- with_pps_lock(intel_dp, wakeref)
+ with_intel_pps_lock(intel_dp, wakeref)
edp_panel_vdd_off_sync(intel_dp);
return false;
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index cfe347076031..9b0c432552b7 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -16,7 +16,7 @@ static void
intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
bool force_disable_vdd);
-intel_wakeref_t pps_lock(struct intel_dp *intel_dp)
+intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
intel_wakeref_t wakeref;
@@ -33,7 +33,8 @@ intel_wakeref_t pps_lock(struct intel_dp *intel_dp)
return wakeref;
}
-intel_wakeref_t pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
+intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp,
+ intel_wakeref_t wakeref)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -633,7 +634,7 @@ void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
return;
vdd = false;
- with_pps_lock(intel_dp, wakeref)
+ with_intel_pps_lock(intel_dp, wakeref)
vdd = edp_panel_vdd_on(intel_dp);
I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",
dp_to_dig_port(intel_dp)->base.base.base.id,
@@ -688,7 +689,7 @@ void edp_panel_vdd_work(struct work_struct *__work)
struct intel_dp, panel_vdd_work);
intel_wakeref_t wakeref;
- with_pps_lock(intel_dp, wakeref) {
+ with_intel_pps_lock(intel_dp, wakeref) {
if (!intel_dp->want_panel_vdd)
edp_panel_vdd_off_sync(intel_dp);
}
@@ -789,7 +790,7 @@ void intel_edp_panel_on(struct intel_dp *intel_dp)
if (!intel_dp_is_edp(intel_dp))
return;
- with_pps_lock(intel_dp, wakeref)
+ with_intel_pps_lock(intel_dp, wakeref)
edp_panel_on(intel_dp);
}
@@ -841,7 +842,7 @@ void intel_edp_panel_off(struct intel_dp *intel_dp)
if (!intel_dp_is_edp(intel_dp))
return;
- with_pps_lock(intel_dp, wakeref)
+ with_intel_pps_lock(intel_dp, wakeref)
edp_panel_off(intel_dp);
}
@@ -859,7 +860,7 @@ void _intel_edp_backlight_on(struct intel_dp *intel_dp)
*/
wait_backlight_on(intel_dp);
- with_pps_lock(intel_dp, wakeref) {
+ with_intel_pps_lock(intel_dp, wakeref) {
i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
u32 pp;
@@ -880,7 +881,7 @@ void _intel_edp_backlight_off(struct intel_dp *intel_dp)
if (!intel_dp_is_edp(intel_dp))
return;
- with_pps_lock(intel_dp, wakeref) {
+ with_intel_pps_lock(intel_dp, wakeref) {
i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
u32 pp;
@@ -907,7 +908,7 @@ void intel_edp_backlight_power(struct intel_connector *connector, bool enable)
bool is_enabled;
is_enabled = false;
- with_pps_lock(intel_dp, wakeref)
+ with_intel_pps_lock(intel_dp, wakeref)
is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
if (is_enabled == enable)
return;
@@ -1057,7 +1058,7 @@ bool intel_edp_have_power(struct intel_dp *intel_dp)
intel_wakeref_t wakeref;
bool have_power = false;
- with_pps_lock(intel_dp, wakeref) {
+ with_intel_pps_lock(intel_dp, wakeref) {
have_power = edp_have_panel_power(intel_dp) &&
edp_have_panel_vdd(intel_dp);
}
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
index 76d5cc565501..f44e6ce9e8c1 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -16,11 +16,11 @@ struct intel_crtc_state;
struct intel_dp;
struct intel_encoder;
-intel_wakeref_t pps_lock(struct intel_dp *intel_dp);
-intel_wakeref_t pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref);
+intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp);
+intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref);
-#define with_pps_lock(dp, wf) \
- for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
+#define with_intel_pps_lock(dp, wf) \
+ for ((wf) = intel_pps_lock(dp); (wf); (wf) = intel_pps_unlock((dp), (wf)))
void intel_dp_check_edp(struct intel_dp *intel_dp);
void _intel_edp_backlight_on(struct intel_dp *intel_dp);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Intel-gfx] [PATCH 03/13] drm/i915/pps: rename intel_edp_backlight_* to intel_pps_backlight_*
2020-12-22 14:49 [Intel-gfx] [PATCH 00/13] drm/i915/dp: split out pps and aux Jani Nikula
2020-12-22 14:49 ` [Intel-gfx] [PATCH 01/13] drm/i915/pps: abstract panel power sequencer from intel_dp.c Jani Nikula
2020-12-22 14:49 ` [Intel-gfx] [PATCH 02/13] drm/i915/pps: rename pps_{, un}lock -> intel_pps_{, un}lock Jani Nikula
@ 2020-12-22 14:49 ` Jani Nikula
2020-12-29 6:12 ` Anshuman Gupta
2020-12-22 14:49 ` [Intel-gfx] [PATCH 04/13] drm/i915/pps: rename intel_edp_panel_* to intel_pps_* Jani Nikula
` (12 subsequent siblings)
15 siblings, 1 reply; 35+ messages in thread
From: Jani Nikula @ 2020-12-22 14:49 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Follow the usual naming pattern for functions.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 6 +++---
drivers/gpu/drm/i915/display/intel_pps.c | 10 +++++-----
drivers/gpu/drm/i915/display/intel_pps.h | 6 +++---
3 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0870872fb594..9813fb7e109c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2536,7 +2536,7 @@ void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
drm_dbg_kms(&i915->drm, "\n");
intel_panel_enable_backlight(crtc_state, conn_state);
- _intel_edp_backlight_on(intel_dp);
+ intel_pps_backlight_on(intel_dp);
}
/* Disable backlight PP control and backlight PWM. */
@@ -2550,7 +2550,7 @@ void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
drm_dbg_kms(&i915->drm, "\n");
- _intel_edp_backlight_off(intel_dp);
+ intel_pps_backlight_off(intel_dp);
intel_panel_disable_backlight(old_conn_state);
}
@@ -6688,7 +6688,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
}
intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
- intel_connector->panel.backlight.power = intel_edp_backlight_power;
+ intel_connector->panel.backlight.power = intel_pps_backlight_power;
intel_panel_setup_backlight(connector, pipe);
if (fixed_mode) {
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 9b0c432552b7..0edda87dee94 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -847,7 +847,7 @@ void intel_edp_panel_off(struct intel_dp *intel_dp)
}
/* Enable backlight in the panel power control. */
-void _intel_edp_backlight_on(struct intel_dp *intel_dp)
+void intel_pps_backlight_on(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
intel_wakeref_t wakeref;
@@ -873,7 +873,7 @@ void _intel_edp_backlight_on(struct intel_dp *intel_dp)
}
/* Disable backlight in the panel power control. */
-void _intel_edp_backlight_off(struct intel_dp *intel_dp)
+void intel_pps_backlight_off(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
intel_wakeref_t wakeref;
@@ -900,7 +900,7 @@ void _intel_edp_backlight_off(struct intel_dp *intel_dp)
* Hook for controlling the panel power control backlight through the bl_power
* sysfs attribute. Take care to handle multiple calls.
*/
-void intel_edp_backlight_power(struct intel_connector *connector, bool enable)
+void intel_pps_backlight_power(struct intel_connector *connector, bool enable)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_dp *intel_dp = intel_attached_dp(connector);
@@ -917,9 +917,9 @@ void intel_edp_backlight_power(struct intel_connector *connector, bool enable)
enable ? "enable" : "disable");
if (enable)
- _intel_edp_backlight_on(intel_dp);
+ intel_pps_backlight_on(intel_dp);
else
- _intel_edp_backlight_off(intel_dp);
+ intel_pps_backlight_off(intel_dp);
}
static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
index f44e6ce9e8c1..81e4e9fc3cf5 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -23,9 +23,9 @@ intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wake
for ((wf) = intel_pps_lock(dp); (wf); (wf) = intel_pps_unlock((dp), (wf)))
void intel_dp_check_edp(struct intel_dp *intel_dp);
-void _intel_edp_backlight_on(struct intel_dp *intel_dp);
-void _intel_edp_backlight_off(struct intel_dp *intel_dp);
-void intel_edp_backlight_power(struct intel_connector *connector, bool enable);
+void intel_pps_backlight_on(struct intel_dp *intel_dp);
+void intel_pps_backlight_off(struct intel_dp *intel_dp);
+void intel_pps_backlight_power(struct intel_connector *connector, bool enable);
bool edp_panel_vdd_on(struct intel_dp *intel_dp);
void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Intel-gfx] [PATCH 04/13] drm/i915/pps: rename intel_edp_panel_* to intel_pps_*
2020-12-22 14:49 [Intel-gfx] [PATCH 00/13] drm/i915/dp: split out pps and aux Jani Nikula
` (2 preceding siblings ...)
2020-12-22 14:49 ` [Intel-gfx] [PATCH 03/13] drm/i915/pps: rename intel_edp_backlight_* to intel_pps_backlight_* Jani Nikula
@ 2020-12-22 14:49 ` Jani Nikula
2020-12-29 6:15 ` Anshuman Gupta
2020-12-22 14:49 ` [Intel-gfx] [PATCH 05/13] drm/i915/pps: rename edp_panel_* to intel_pps_*_unlocked Jani Nikula
` (11 subsequent siblings)
15 siblings, 1 reply; 35+ messages in thread
From: Jani Nikula @ 2020-12-22 14:49 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Follow the usual naming pattern for functions. We don't need to repeat
"panel" here.
Follow the usual naming pattern for functions.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++++----
drivers/gpu/drm/i915/display/intel_dp.c | 10 +++++-----
drivers/gpu/drm/i915/display/intel_pps.c | 18 +++++++++---------
drivers/gpu/drm/i915/display/intel_pps.h | 11 +++++------
4 files changed, 23 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 9ddbe8b8730b..83300ee8c3fd 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3556,7 +3556,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
*/
/* 2. Enable Panel Power if PPS is required */
- intel_edp_panel_on(intel_dp);
+ intel_pps_on(intel_dp);
/*
* 3. For non-TBT Type-C ports, set FIA lane count
@@ -3695,7 +3695,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
crtc_state->port_clock,
crtc_state->lane_count);
- intel_edp_panel_on(intel_dp);
+ intel_pps_on(intel_dp);
intel_ddi_clk_select(encoder, crtc_state);
@@ -3937,8 +3937,8 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
if (INTEL_GEN(dev_priv) >= 12)
intel_ddi_disable_pipe_clock(old_crtc_state);
- intel_edp_panel_vdd_on(intel_dp);
- intel_edp_panel_off(intel_dp);
+ intel_pps_vdd_on(intel_dp);
+ intel_pps_off(intel_dp);
if (!intel_phy_is_tc(dev_priv, phy) ||
dig_port->tc_mode != TC_PORT_TBT_ALT)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9813fb7e109c..2052ee228077 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2947,10 +2947,10 @@ static void intel_disable_dp(struct intel_atomic_state *state,
/* Make sure the panel is off before trying to change the mode. But also
* ensure that we have vdd while we switch off the panel. */
- intel_edp_panel_vdd_on(intel_dp);
+ intel_pps_vdd_on(intel_dp);
intel_edp_backlight_off(old_conn_state);
intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
- intel_edp_panel_off(intel_dp);
+ intel_pps_off(intel_dp);
}
static void g4x_disable_dp(struct intel_atomic_state *state,
@@ -5899,7 +5899,7 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder)
* something nasty with it.
*/
intel_dp_pps_init(intel_dp);
- intel_edp_panel_vdd_sanitize(intel_dp);
+ intel_pps_vdd_sanitize(intel_dp);
}
}
}
@@ -6073,7 +6073,7 @@ intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
struct intel_dp *intel_dp = &dig_port->dp;
if (dig_port->base.type == INTEL_OUTPUT_EDP &&
- (long_hpd || !intel_edp_have_power(intel_dp))) {
+ (long_hpd || !intel_pps_have_power(intel_dp))) {
/*
* vdd off can generate a long/short pulse on eDP which
* would require vdd on to handle it, and thus we
@@ -6631,7 +6631,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
with_intel_pps_lock(intel_dp, wakeref) {
intel_dp_init_panel_power_timestamps(intel_dp);
intel_dp_pps_init(intel_dp);
- intel_edp_panel_vdd_sanitize(intel_dp);
+ intel_pps_vdd_sanitize(intel_dp);
}
/* Cache DPCD and EDID for edp. */
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 0edda87dee94..1f8ea3c41440 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -561,7 +561,7 @@ static u32 ilk_get_pp_control(struct intel_dp *intel_dp)
/*
* Must be paired with edp_panel_vdd_off().
* Must hold pps_mutex around the whole on/off sequence.
- * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
+ * Can be nested with intel_pps_vdd_{on,off}() calls.
*/
bool edp_panel_vdd_on(struct intel_dp *intel_dp)
{
@@ -619,13 +619,13 @@ bool edp_panel_vdd_on(struct intel_dp *intel_dp)
}
/*
- * Must be paired with intel_edp_panel_vdd_off() or
- * intel_edp_panel_off().
+ * Must be paired with intel_pps_vdd_off() or
+ * intel_pps_off().
* Nested calls to these functions are not allowed since
* we drop the lock. Caller must use some higher level
* locking to prevent nested calls from other threads.
*/
-void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
+void intel_pps_vdd_on(struct intel_dp *intel_dp)
{
intel_wakeref_t wakeref;
bool vdd;
@@ -711,7 +711,7 @@ static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
/*
* Must be paired with edp_panel_vdd_on().
* Must hold pps_mutex around the whole on/off sequence.
- * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
+ * Can be nested with intel_pps_vdd_{on,off}() calls.
*/
void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
{
@@ -783,7 +783,7 @@ void edp_panel_on(struct intel_dp *intel_dp)
}
}
-void intel_edp_panel_on(struct intel_dp *intel_dp)
+void intel_pps_on(struct intel_dp *intel_dp)
{
intel_wakeref_t wakeref;
@@ -835,7 +835,7 @@ void edp_panel_off(struct intel_dp *intel_dp)
fetch_and_zero(&intel_dp->vdd_wakeref));
}
-void intel_edp_panel_off(struct intel_dp *intel_dp)
+void intel_pps_off(struct intel_dp *intel_dp)
{
intel_wakeref_t wakeref;
@@ -1028,7 +1028,7 @@ void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
}
-void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
+void intel_pps_vdd_sanitize(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -1053,7 +1053,7 @@ void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
edp_panel_vdd_schedule_off(intel_dp);
}
-bool intel_edp_have_power(struct intel_dp *intel_dp)
+bool intel_pps_have_power(struct intel_dp *intel_dp)
{
intel_wakeref_t wakeref;
bool have_power = false;
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
index 81e4e9fc3cf5..69f670678d0e 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -34,12 +34,11 @@ void edp_panel_on(struct intel_dp *intel_dp);
void edp_panel_off(struct intel_dp *intel_dp);
void edp_panel_vdd_work(struct work_struct *__work);
-void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
-void intel_edp_panel_on(struct intel_dp *intel_dp);
-void intel_edp_panel_off(struct intel_dp *intel_dp);
-bool intel_edp_have_power(struct intel_dp *intel_dp);
-
-void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp);
+void intel_pps_vdd_sanitize(struct intel_dp *intel_dp);
+void intel_pps_vdd_on(struct intel_dp *intel_dp);
+void intel_pps_on(struct intel_dp *intel_dp);
+void intel_pps_off(struct intel_dp *intel_dp);
+bool intel_pps_have_power(struct intel_dp *intel_dp);
void wait_panel_power_cycle(struct intel_dp *intel_dp);
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Intel-gfx] [PATCH 05/13] drm/i915/pps: rename edp_panel_* to intel_pps_*_unlocked
2020-12-22 14:49 [Intel-gfx] [PATCH 00/13] drm/i915/dp: split out pps and aux Jani Nikula
` (3 preceding siblings ...)
2020-12-22 14:49 ` [Intel-gfx] [PATCH 04/13] drm/i915/pps: rename intel_edp_panel_* to intel_pps_* Jani Nikula
@ 2020-12-22 14:49 ` Jani Nikula
2020-12-29 6:35 ` Anshuman Gupta
2020-12-22 14:49 ` [Intel-gfx] [PATCH 06/13] drm/i915/pps: abstract intel_pps_vdd_off_sync Jani Nikula
` (10 subsequent siblings)
15 siblings, 1 reply; 35+ messages in thread
From: Jani Nikula @ 2020-12-22 14:49 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Follow the usual naming pattern for functions, both for the prefix and
the _unlocked suffix for functions that expect the lock to be held when
calling.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 16 +++++++--------
drivers/gpu/drm/i915/display/intel_pps.c | 26 ++++++++++++------------
drivers/gpu/drm/i915/display/intel_pps.h | 10 ++++-----
3 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 2052ee228077..f2794cc4292a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1038,7 +1038,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
* to turn it off. But for eg. i2c-dev access we need to turn it on/off
* ourselves.
*/
- vdd = edp_panel_vdd_on(intel_dp);
+ vdd = intel_pps_vdd_on_unlocked(intel_dp);
/* dp aux is extremely sensitive to irq latency, hence request the
* lowest possible wakeup latency and so prevent the cpu from going into
@@ -1180,7 +1180,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
if (vdd)
- edp_panel_vdd_off(intel_dp, false);
+ intel_pps_vdd_off_unlocked(intel_dp, false);
intel_pps_unlock(intel_dp, pps_wakeref);
intel_display_power_put_async(i915, aux_domain, aux_wakeref);
@@ -3159,9 +3159,9 @@ static void intel_enable_dp(struct intel_atomic_state *state,
intel_dp_enable_port(intel_dp, pipe_config);
- edp_panel_vdd_on(intel_dp);
- edp_panel_on(intel_dp);
- edp_panel_vdd_off(intel_dp, true);
+ intel_pps_vdd_on_unlocked(intel_dp);
+ intel_pps_on_unlocked(intel_dp);
+ intel_pps_vdd_off_unlocked(intel_dp, true);
}
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
@@ -5818,7 +5818,7 @@ void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
* Make sure vdd is actually turned off here.
*/
with_intel_pps_lock(intel_dp, wakeref)
- edp_panel_vdd_off_sync(intel_dp);
+ intel_pps_vdd_off_sync_unlocked(intel_dp);
}
intel_dp_aux_fini(intel_dp);
@@ -5846,7 +5846,7 @@ void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
*/
cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
with_intel_pps_lock(intel_dp, wakeref)
- edp_panel_vdd_off_sync(intel_dp);
+ intel_pps_vdd_off_sync_unlocked(intel_dp);
}
void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
@@ -6706,7 +6706,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
* Make sure vdd is actually turned off here.
*/
with_intel_pps_lock(intel_dp, wakeref)
- edp_panel_vdd_off_sync(intel_dp);
+ intel_pps_vdd_off_sync_unlocked(intel_dp);
return false;
}
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 1f8ea3c41440..01c9e69f4e3a 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -559,11 +559,11 @@ static u32 ilk_get_pp_control(struct intel_dp *intel_dp)
}
/*
- * Must be paired with edp_panel_vdd_off().
+ * Must be paired with intel_pps_vdd_off_unlocked().
* Must hold pps_mutex around the whole on/off sequence.
* Can be nested with intel_pps_vdd_{on,off}() calls.
*/
-bool edp_panel_vdd_on(struct intel_dp *intel_dp)
+bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -635,13 +635,13 @@ void intel_pps_vdd_on(struct intel_dp *intel_dp)
vdd = false;
with_intel_pps_lock(intel_dp, wakeref)
- vdd = edp_panel_vdd_on(intel_dp);
+ vdd = intel_pps_vdd_on_unlocked(intel_dp);
I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",
dp_to_dig_port(intel_dp)->base.base.base.id,
dp_to_dig_port(intel_dp)->base.base.name);
}
-void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
+void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *dig_port =
@@ -691,7 +691,7 @@ void edp_panel_vdd_work(struct work_struct *__work)
with_intel_pps_lock(intel_dp, wakeref) {
if (!intel_dp->want_panel_vdd)
- edp_panel_vdd_off_sync(intel_dp);
+ intel_pps_vdd_off_sync_unlocked(intel_dp);
}
}
@@ -713,7 +713,7 @@ static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
* Must hold pps_mutex around the whole on/off sequence.
* Can be nested with intel_pps_vdd_{on,off}() calls.
*/
-void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
+void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -729,12 +729,12 @@ void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
intel_dp->want_panel_vdd = false;
if (sync)
- edp_panel_vdd_off_sync(intel_dp);
+ intel_pps_vdd_off_sync_unlocked(intel_dp);
else
edp_panel_vdd_schedule_off(intel_dp);
}
-void edp_panel_on(struct intel_dp *intel_dp)
+void intel_pps_on_unlocked(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u32 pp;
@@ -791,10 +791,10 @@ void intel_pps_on(struct intel_dp *intel_dp)
return;
with_intel_pps_lock(intel_dp, wakeref)
- edp_panel_on(intel_dp);
+ intel_pps_on_unlocked(intel_dp);
}
-void edp_panel_off(struct intel_dp *intel_dp)
+void intel_pps_off_unlocked(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -843,7 +843,7 @@ void intel_pps_off(struct intel_dp *intel_dp)
return;
with_intel_pps_lock(intel_dp, wakeref)
- edp_panel_off(intel_dp);
+ intel_pps_off_unlocked(intel_dp);
}
/* Enable backlight in the panel power control. */
@@ -934,7 +934,7 @@ static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B))
return;
- edp_panel_vdd_off_sync(intel_dp);
+ intel_pps_vdd_off_sync_unlocked(intel_dp);
/*
* VLV seems to get confused when multiple power sequencers
@@ -1249,7 +1249,7 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
* hooked up to any port. This would mess up the
* power domain tracking the first time we pick
* one of these power sequencers for use since
- * edp_panel_vdd_on() would notice that the VDD was
+ * intel_pps_vdd_on_unlocked() would notice that the VDD was
* already on and therefore wouldn't grab the power
* domain reference. Disable VDD first to avoid this.
* This also avoids spuriously turning the VDD on as
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
index 69f670678d0e..e7f0473be9a7 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -27,11 +27,11 @@ void intel_pps_backlight_on(struct intel_dp *intel_dp);
void intel_pps_backlight_off(struct intel_dp *intel_dp);
void intel_pps_backlight_power(struct intel_connector *connector, bool enable);
-bool edp_panel_vdd_on(struct intel_dp *intel_dp);
-void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
-void edp_panel_vdd_off_sync(struct intel_dp *intel_dp);
-void edp_panel_on(struct intel_dp *intel_dp);
-void edp_panel_off(struct intel_dp *intel_dp);
+bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp);
+void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);
+void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp);
+void intel_pps_on_unlocked(struct intel_dp *intel_dp);
+void intel_pps_off_unlocked(struct intel_dp *intel_dp);
void edp_panel_vdd_work(struct work_struct *__work);
void intel_pps_vdd_sanitize(struct intel_dp *intel_dp);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Intel-gfx] [PATCH 06/13] drm/i915/pps: abstract intel_pps_vdd_off_sync
2020-12-22 14:49 [Intel-gfx] [PATCH 00/13] drm/i915/dp: split out pps and aux Jani Nikula
` (4 preceding siblings ...)
2020-12-22 14:49 ` [Intel-gfx] [PATCH 05/13] drm/i915/pps: rename edp_panel_* to intel_pps_*_unlocked Jani Nikula
@ 2020-12-22 14:49 ` Jani Nikula
2020-12-29 6:47 ` Anshuman Gupta
2020-12-22 14:49 ` [Intel-gfx] [PATCH 07/13] drm/i915/pps: add higher level intel_pps_init() call Jani Nikula
` (9 subsequent siblings)
15 siblings, 1 reply; 35+ messages in thread
From: Jani Nikula @ 2020-12-22 14:49 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Add a locked version of intel_pps_vdd_off_sync_unlocked() that does
everything the callers expect it to.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 31 +++---------------------
drivers/gpu/drm/i915/display/intel_pps.c | 17 ++++++++++++-
drivers/gpu/drm/i915/display/intel_pps.h | 2 +-
3 files changed, 20 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f2794cc4292a..1a34c9351c30 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5809,17 +5809,8 @@ void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
struct intel_dp *intel_dp = &dig_port->dp;
intel_dp_mst_encoder_cleanup(dig_port);
- if (intel_dp_is_edp(intel_dp)) {
- intel_wakeref_t wakeref;
- cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
- /*
- * vdd might still be enabled do to the delayed vdd off.
- * Make sure vdd is actually turned off here.
- */
- with_intel_pps_lock(intel_dp, wakeref)
- intel_pps_vdd_off_sync_unlocked(intel_dp);
- }
+ intel_pps_vdd_off_sync(intel_dp);
intel_dp_aux_fini(intel_dp);
}
@@ -5835,18 +5826,8 @@ static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
{
struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
- intel_wakeref_t wakeref;
-
- if (!intel_dp_is_edp(intel_dp))
- return;
- /*
- * vdd might still be enabled do to the delayed vdd off.
- * Make sure vdd is actually turned off here.
- */
- cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
- with_intel_pps_lock(intel_dp, wakeref)
- intel_pps_vdd_off_sync_unlocked(intel_dp);
+ intel_pps_vdd_off_sync(intel_dp);
}
void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
@@ -6700,13 +6681,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
return true;
out_vdd_off:
- cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
- /*
- * vdd might still be enabled do to the delayed vdd off.
- * Make sure vdd is actually turned off here.
- */
- with_intel_pps_lock(intel_dp, wakeref)
- intel_pps_vdd_off_sync_unlocked(intel_dp);
+ intel_pps_vdd_off_sync(intel_dp);
return false;
}
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 01c9e69f4e3a..acd6d0092bc6 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -641,7 +641,7 @@ void intel_pps_vdd_on(struct intel_dp *intel_dp)
dp_to_dig_port(intel_dp)->base.base.name);
}
-void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
+static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *dig_port =
@@ -682,6 +682,21 @@ void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
fetch_and_zero(&intel_dp->vdd_wakeref));
}
+void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
+{
+ intel_wakeref_t wakeref;
+ if (!intel_dp_is_edp(intel_dp))
+ return;
+
+ cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
+ /*
+ * vdd might still be enabled do to the delayed vdd off.
+ * Make sure vdd is actually turned off here.
+ */
+ with_intel_pps_lock(intel_dp, wakeref)
+ intel_pps_vdd_off_sync_unlocked(intel_dp);
+}
+
void edp_panel_vdd_work(struct work_struct *__work)
{
struct intel_dp *intel_dp =
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
index e7f0473be9a7..3cab183658c6 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -29,7 +29,6 @@ void intel_pps_backlight_power(struct intel_connector *connector, bool enable);
bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp);
void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);
-void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp);
void intel_pps_on_unlocked(struct intel_dp *intel_dp);
void intel_pps_off_unlocked(struct intel_dp *intel_dp);
void edp_panel_vdd_work(struct work_struct *__work);
@@ -38,6 +37,7 @@ void intel_pps_vdd_sanitize(struct intel_dp *intel_dp);
void intel_pps_vdd_on(struct intel_dp *intel_dp);
void intel_pps_on(struct intel_dp *intel_dp);
void intel_pps_off(struct intel_dp *intel_dp);
+void intel_pps_vdd_off_sync(struct intel_dp *intel_dp);
bool intel_pps_have_power(struct intel_dp *intel_dp);
void wait_panel_power_cycle(struct intel_dp *intel_dp);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Intel-gfx] [PATCH 07/13] drm/i915/pps: add higher level intel_pps_init() call
2020-12-22 14:49 [Intel-gfx] [PATCH 00/13] drm/i915/dp: split out pps and aux Jani Nikula
` (5 preceding siblings ...)
2020-12-22 14:49 ` [Intel-gfx] [PATCH 06/13] drm/i915/pps: abstract intel_pps_vdd_off_sync Jani Nikula
@ 2020-12-22 14:49 ` Jani Nikula
2020-12-29 6:53 ` Anshuman Gupta
2020-12-22 14:49 ` [Intel-gfx] [PATCH 08/13] drm/i915/pps: abstract intel_pps_reinit() Jani Nikula
` (8 subsequent siblings)
15 siblings, 1 reply; 35+ messages in thread
From: Jani Nikula @ 2020-12-22 14:49 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Add a new init call to be called only once, unlike some of the other
various init calls. This lets us hide more functions within intel_pps.c.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 9 +--------
drivers/gpu/drm/i915/display/intel_pps.c | 17 +++++++++++++++--
drivers/gpu/drm/i915/display/intel_pps.h | 3 +--
3 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 1a34c9351c30..de2642d5be3b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6586,14 +6586,11 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
struct drm_display_mode *downclock_mode = NULL;
bool has_dpcd;
enum pipe pipe = INVALID_PIPE;
- intel_wakeref_t wakeref;
struct edid *edid;
if (!intel_dp_is_edp(intel_dp))
return true;
- INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
-
/*
* On IBX/CPT we may get here with LVDS already registered. Since the
* driver uses the only internal power sequencer available for both
@@ -6609,11 +6606,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
return false;
}
- with_intel_pps_lock(intel_dp, wakeref) {
- intel_dp_init_panel_power_timestamps(intel_dp);
- intel_dp_pps_init(intel_dp);
- intel_pps_vdd_sanitize(intel_dp);
- }
+ intel_pps_init(intel_dp);
/* Cache DPCD and EDID for edp. */
has_dpcd = intel_edp_init_dpcd(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index acd6d0092bc6..651c79ce4bdd 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -697,7 +697,7 @@ void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
intel_pps_vdd_off_sync_unlocked(intel_dp);
}
-void edp_panel_vdd_work(struct work_struct *__work)
+static void edp_panel_vdd_work(struct work_struct *__work)
{
struct intel_dp *intel_dp =
container_of(to_delayed_work(__work),
@@ -1081,7 +1081,7 @@ bool intel_pps_have_power(struct intel_dp *intel_dp)
return have_power;
}
-void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
+static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
{
intel_dp->panel_power_off_time = ktime_get_boottime();
intel_dp->last_power_on = jiffies;
@@ -1351,3 +1351,16 @@ void intel_dp_pps_init(struct intel_dp *intel_dp)
intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
}
}
+
+void intel_pps_init(struct intel_dp *intel_dp)
+{
+ intel_wakeref_t wakeref;
+
+ INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
+
+ with_intel_pps_lock(intel_dp, wakeref) {
+ intel_dp_init_panel_power_timestamps(intel_dp);
+ intel_dp_pps_init(intel_dp);
+ intel_pps_vdd_sanitize(intel_dp);
+ }
+}
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
index 3cab183658c6..53c0fafd1440 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -31,7 +31,6 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp);
void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);
void intel_pps_on_unlocked(struct intel_dp *intel_dp);
void intel_pps_off_unlocked(struct intel_dp *intel_dp);
-void edp_panel_vdd_work(struct work_struct *__work);
void intel_pps_vdd_sanitize(struct intel_dp *intel_dp);
void intel_pps_vdd_on(struct intel_dp *intel_dp);
@@ -42,9 +41,9 @@ bool intel_pps_have_power(struct intel_dp *intel_dp);
void wait_panel_power_cycle(struct intel_dp *intel_dp);
+void intel_pps_init(struct intel_dp *intel_dp);
void intel_dp_pps_init(struct intel_dp *intel_dp);
void intel_power_sequencer_reset(struct drm_i915_private *i915);
-void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp);
void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Intel-gfx] [PATCH 08/13] drm/i915/pps: abstract intel_pps_reinit()
2020-12-22 14:49 [Intel-gfx] [PATCH 00/13] drm/i915/dp: split out pps and aux Jani Nikula
` (6 preceding siblings ...)
2020-12-22 14:49 ` [Intel-gfx] [PATCH 07/13] drm/i915/pps: add higher level intel_pps_init() call Jani Nikula
@ 2020-12-22 14:49 ` Jani Nikula
2020-12-29 6:59 ` Anshuman Gupta
2020-12-22 14:49 ` [Intel-gfx] [PATCH 09/13] drm/i915/pps: rename intel_dp_check_edp to intel_pps_check_power_unlocked Jani Nikula
` (7 subsequent siblings)
15 siblings, 1 reply; 35+ messages in thread
From: Jani Nikula @ 2020-12-22 14:49 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Add a "reinit" call to hide some more pps functions, and clean up the
callers. A minor functional change is not holding the pps lock across
the whole operation in intel_dp_encoder_reset, but instead doing it in
two steps.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 20 +++++---------------
drivers/gpu/drm/i915/display/intel_pps.c | 21 +++++++++++++++++++--
drivers/gpu/drm/i915/display/intel_pps.h | 3 +--
3 files changed, 25 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index de2642d5be3b..334ba1775cd3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5859,30 +5859,20 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->dev);
struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
- intel_wakeref_t wakeref;
if (!HAS_DDI(dev_priv))
intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
intel_dp->reset_link_params = true;
- if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
- !intel_dp_is_edp(intel_dp))
- return;
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+ intel_wakeref_t wakeref;
- with_intel_pps_lock(intel_dp, wakeref) {
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+ with_intel_pps_lock(intel_dp, wakeref)
intel_dp->active_pipe = vlv_active_pipe(intel_dp);
-
- if (intel_dp_is_edp(intel_dp)) {
- /*
- * Reinit the power sequencer, in case BIOS did
- * something nasty with it.
- */
- intel_dp_pps_init(intel_dp);
- intel_pps_vdd_sanitize(intel_dp);
- }
}
+
+ intel_pps_reinit(intel_dp);
}
static int intel_modeset_tile_group(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 651c79ce4bdd..3e62d1450682 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -1043,7 +1043,7 @@ void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
}
-void intel_pps_vdd_sanitize(struct intel_dp *intel_dp)
+static void intel_pps_vdd_sanitize(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -1340,7 +1340,7 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
(intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
}
-void intel_dp_pps_init(struct intel_dp *intel_dp)
+static void intel_dp_pps_init(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1352,6 +1352,23 @@ void intel_dp_pps_init(struct intel_dp *intel_dp)
}
}
+void intel_pps_reinit(struct intel_dp *intel_dp)
+{
+ intel_wakeref_t wakeref;
+
+ if (!intel_dp_is_edp(intel_dp))
+ return;
+
+ with_intel_pps_lock(intel_dp, wakeref) {
+ /*
+ * Reinit the power sequencer, in case BIOS did something nasty
+ * with it.
+ */
+ intel_dp_pps_init(intel_dp);
+ intel_pps_vdd_sanitize(intel_dp);
+ }
+}
+
void intel_pps_init(struct intel_dp *intel_dp)
{
intel_wakeref_t wakeref;
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
index 53c0fafd1440..4780b59a59df 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -32,7 +32,6 @@ void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);
void intel_pps_on_unlocked(struct intel_dp *intel_dp);
void intel_pps_off_unlocked(struct intel_dp *intel_dp);
-void intel_pps_vdd_sanitize(struct intel_dp *intel_dp);
void intel_pps_vdd_on(struct intel_dp *intel_dp);
void intel_pps_on(struct intel_dp *intel_dp);
void intel_pps_off(struct intel_dp *intel_dp);
@@ -42,7 +41,7 @@ bool intel_pps_have_power(struct intel_dp *intel_dp);
void wait_panel_power_cycle(struct intel_dp *intel_dp);
void intel_pps_init(struct intel_dp *intel_dp);
-void intel_dp_pps_init(struct intel_dp *intel_dp);
+void intel_pps_reinit(struct intel_dp *intel_dp);
void intel_power_sequencer_reset(struct drm_i915_private *i915);
void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Intel-gfx] [PATCH 09/13] drm/i915/pps: rename intel_dp_check_edp to intel_pps_check_power_unlocked
2020-12-22 14:49 [Intel-gfx] [PATCH 00/13] drm/i915/dp: split out pps and aux Jani Nikula
` (7 preceding siblings ...)
2020-12-22 14:49 ` [Intel-gfx] [PATCH 08/13] drm/i915/pps: abstract intel_pps_reinit() Jani Nikula
@ 2020-12-22 14:49 ` Jani Nikula
2020-12-29 7:04 ` Anshuman Gupta
2020-12-22 14:49 ` [Intel-gfx] [PATCH 10/13] drm/i915/pps: rename intel_power_sequencer_reset to intel_pps_reset_all Jani Nikula
` (6 subsequent siblings)
15 siblings, 1 reply; 35+ messages in thread
From: Jani Nikula @ 2020-12-22 14:49 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Follow the usual naming pattern for functions.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_pps.c | 2 +-
drivers/gpu/drm/i915/display/intel_pps.h | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 334ba1775cd3..65406d4ccdbe 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1046,7 +1046,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
*/
cpu_latency_qos_update_request(&i915->pm_qos, 0);
- intel_dp_check_edp(intel_dp);
+ intel_pps_check_power_unlocked(intel_dp);
/* Try to wait for any previous AUX channel activity */
for (try = 0; try < 3; try++) {
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 3e62d1450682..dfd6722bc40e 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -431,7 +431,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
}
-void intel_dp_check_edp(struct intel_dp *intel_dp)
+void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
index 4780b59a59df..8dda282abd42 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -22,7 +22,6 @@ intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wake
#define with_intel_pps_lock(dp, wf) \
for ((wf) = intel_pps_lock(dp); (wf); (wf) = intel_pps_unlock((dp), (wf)))
-void intel_dp_check_edp(struct intel_dp *intel_dp);
void intel_pps_backlight_on(struct intel_dp *intel_dp);
void intel_pps_backlight_off(struct intel_dp *intel_dp);
void intel_pps_backlight_power(struct intel_connector *connector, bool enable);
@@ -31,6 +30,7 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp);
void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);
void intel_pps_on_unlocked(struct intel_dp *intel_dp);
void intel_pps_off_unlocked(struct intel_dp *intel_dp);
+void intel_pps_check_power_unlocked(struct intel_dp *intel_dp);
void intel_pps_vdd_on(struct intel_dp *intel_dp);
void intel_pps_on(struct intel_dp *intel_dp);
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Intel-gfx] [PATCH 10/13] drm/i915/pps: rename intel_power_sequencer_reset to intel_pps_reset_all
2020-12-22 14:49 [Intel-gfx] [PATCH 00/13] drm/i915/dp: split out pps and aux Jani Nikula
` (8 preceding siblings ...)
2020-12-22 14:49 ` [Intel-gfx] [PATCH 09/13] drm/i915/pps: rename intel_dp_check_edp to intel_pps_check_power_unlocked Jani Nikula
@ 2020-12-22 14:49 ` Jani Nikula
2020-12-29 7:53 ` Anshuman Gupta
2020-12-22 14:49 ` [Intel-gfx] [PATCH 11/13] drm/i915/pps: add locked intel_pps_wait_power_cycle Jani Nikula
` (5 subsequent siblings)
15 siblings, 1 reply; 35+ messages in thread
From: Jani Nikula @ 2020-12-22 14:49 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Follow the usual naming pattern for functions. "reset all" because it
iterates over all DP encoders.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4 ++--
drivers/gpu/drm/i915/display/intel_pps.c | 5 ++---
drivers/gpu/drm/i915/display/intel_pps.h | 2 +-
3 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index a11bd8213df4..c11c37c65d86 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -936,7 +936,7 @@ static void bxt_enable_dc9(struct drm_i915_private *dev_priv)
* because PPS registers are always on.
*/
if (!HAS_PCH_SPLIT(dev_priv))
- intel_power_sequencer_reset(dev_priv);
+ intel_pps_reset_all(dev_priv);
gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
}
@@ -1446,7 +1446,7 @@ static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
/* make sure we're done processing display irqs */
intel_synchronize_irq(dev_priv);
- intel_power_sequencer_reset(dev_priv);
+ intel_pps_reset_all(dev_priv);
/* Prevent us from re-enabling polling on accident in late suspend */
if (!dev_priv->drm.dev->power.is_suspended)
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index dfd6722bc40e..ceb6de9e7aff 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -22,8 +22,7 @@ intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp)
intel_wakeref_t wakeref;
/*
- * See intel_power_sequencer_reset() why we need
- * a power domain reference here.
+ * See intel_pps_reset_all() why we need a power domain reference here.
*/
wakeref = intel_display_power_get(dev_priv,
intel_aux_power_domain(dp_to_dig_port(intel_dp)));
@@ -316,7 +315,7 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
}
-void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
+void intel_pps_reset_all(struct drm_i915_private *dev_priv)
{
struct intel_encoder *encoder;
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
index 8dda282abd42..451d5125b2b7 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -42,7 +42,7 @@ void wait_panel_power_cycle(struct intel_dp *intel_dp);
void intel_pps_init(struct intel_dp *intel_dp);
void intel_pps_reinit(struct intel_dp *intel_dp);
-void intel_power_sequencer_reset(struct drm_i915_private *i915);
+void intel_pps_reset_all(struct drm_i915_private *i915);
void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Intel-gfx] [PATCH 11/13] drm/i915/pps: add locked intel_pps_wait_power_cycle
2020-12-22 14:49 [Intel-gfx] [PATCH 00/13] drm/i915/dp: split out pps and aux Jani Nikula
` (9 preceding siblings ...)
2020-12-22 14:49 ` [Intel-gfx] [PATCH 10/13] drm/i915/pps: rename intel_power_sequencer_reset to intel_pps_reset_all Jani Nikula
@ 2020-12-22 14:49 ` Jani Nikula
2020-12-29 7:59 ` Anshuman Gupta
2020-12-22 14:49 ` [Intel-gfx] [PATCH 12/13] drm/i915/pps: rename vlv_init_panel_power_sequencer to vlv_pps_init Jani Nikula
` (4 subsequent siblings)
15 siblings, 1 reply; 35+ messages in thread
From: Jani Nikula @ 2020-12-22 14:49 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Prefer keeping the unlocked variants hidden if possible.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 7 +------
drivers/gpu/drm/i915/display/intel_pps.c | 13 ++++++++++++-
drivers/gpu/drm/i915/display/intel_pps.h | 3 +--
3 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 65406d4ccdbe..bc3a447f5992 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5833,13 +5833,8 @@ void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
{
struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
- intel_wakeref_t wakeref;
-
- if (!intel_dp_is_edp(intel_dp))
- return;
- with_intel_pps_lock(intel_dp, wakeref)
- wait_panel_power_cycle(intel_dp);
+ intel_pps_wait_power_cycle(intel_dp);
}
static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index ceb6de9e7aff..ceb74967f2b4 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -503,7 +503,7 @@ static void wait_panel_off(struct intel_dp *intel_dp)
wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
}
-void wait_panel_power_cycle(struct intel_dp *intel_dp)
+static void wait_panel_power_cycle(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
ktime_t panel_power_on_time;
@@ -525,6 +525,17 @@ void wait_panel_power_cycle(struct intel_dp *intel_dp)
wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
}
+void intel_pps_wait_power_cycle(struct intel_dp *intel_dp)
+{
+ intel_wakeref_t wakeref;
+
+ if (!intel_dp_is_edp(intel_dp))
+ return;
+
+ with_intel_pps_lock(intel_dp, wakeref)
+ wait_panel_power_cycle(intel_dp);
+}
+
static void wait_backlight_on(struct intel_dp *intel_dp)
{
wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
index 451d5125b2b7..c8766b777501 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -37,8 +37,7 @@ void intel_pps_on(struct intel_dp *intel_dp);
void intel_pps_off(struct intel_dp *intel_dp);
void intel_pps_vdd_off_sync(struct intel_dp *intel_dp);
bool intel_pps_have_power(struct intel_dp *intel_dp);
-
-void wait_panel_power_cycle(struct intel_dp *intel_dp);
+void intel_pps_wait_power_cycle(struct intel_dp *intel_dp);
void intel_pps_init(struct intel_dp *intel_dp);
void intel_pps_reinit(struct intel_dp *intel_dp);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Intel-gfx] [PATCH 12/13] drm/i915/pps: rename vlv_init_panel_power_sequencer to vlv_pps_init
2020-12-22 14:49 [Intel-gfx] [PATCH 00/13] drm/i915/dp: split out pps and aux Jani Nikula
` (10 preceding siblings ...)
2020-12-22 14:49 ` [Intel-gfx] [PATCH 11/13] drm/i915/pps: add locked intel_pps_wait_power_cycle Jani Nikula
@ 2020-12-22 14:49 ` Jani Nikula
2020-12-29 8:01 ` Anshuman Gupta
2020-12-22 14:49 ` [Intel-gfx] [PATCH 13/13] drm/i915/dp: split out aux functionality to intel_dp_aux.c Jani Nikula
` (3 subsequent siblings)
15 siblings, 1 reply; 35+ messages in thread
From: Jani Nikula @ 2020-12-22 14:49 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
This function is a bit of an outlier, but try to change to a name that
is more in line with the rest of the intel_pps functions.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_pps.c | 4 ++--
drivers/gpu/drm/i915/display/intel_pps.h | 4 ++--
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index bc3a447f5992..c49ada31363b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3155,7 +3155,7 @@ static void intel_enable_dp(struct intel_atomic_state *state,
with_intel_pps_lock(intel_dp, wakeref) {
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- vlv_init_panel_power_sequencer(encoder, pipe_config);
+ vlv_pps_init(encoder, pipe_config);
intel_dp_enable_port(intel_dp, pipe_config);
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index ceb74967f2b4..492abf372167 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -1008,8 +1008,8 @@ static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
}
}
-void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state)
+void vlv_pps_init(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
index c8766b777501..d9cd57b5b828 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -43,7 +43,7 @@ void intel_pps_init(struct intel_dp *intel_dp);
void intel_pps_reinit(struct intel_dp *intel_dp);
void intel_pps_reset_all(struct drm_i915_private *i915);
-void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state);
+void vlv_pps_init(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
#endif /* __INTEL_PPS_H__ */
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Intel-gfx] [PATCH 13/13] drm/i915/dp: split out aux functionality to intel_dp_aux.c
2020-12-22 14:49 [Intel-gfx] [PATCH 00/13] drm/i915/dp: split out pps and aux Jani Nikula
` (11 preceding siblings ...)
2020-12-22 14:49 ` [Intel-gfx] [PATCH 12/13] drm/i915/pps: rename vlv_init_panel_power_sequencer to vlv_pps_init Jani Nikula
@ 2020-12-22 14:49 ` Jani Nikula
2020-12-22 15:57 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: split out pps and aux Patchwork
` (2 subsequent siblings)
15 siblings, 0 replies; 35+ messages in thread
From: Jani Nikula @ 2020-12-22 14:49 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Split out the DP aux functionality to a new intel_dp_aux.[ch]. This is a
surprisingly clean cut.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 676 +------------------
drivers/gpu/drm/i915/display/intel_dp_aux.c | 683 ++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp_aux.h | 18 +
4 files changed, 703 insertions(+), 675 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_dp_aux.c
create mode 100644 drivers/gpu/drm/i915/display/intel_dp_aux.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 1e26902a86e5..c5cafaea7527 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -237,6 +237,7 @@ i915-y += \
display/intel_crt.o \
display/intel_ddi.o \
display/intel_dp.o \
+ display/intel_dp_aux.o \
display/intel_dp_aux_backlight.o \
display/intel_dp_hdcp.o \
display/intel_dp_link_training.o \
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c49ada31363b..86cb7671ebf4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -41,13 +41,13 @@
#include "i915_debugfs.h"
#include "i915_drv.h"
-#include "i915_trace.h"
#include "intel_atomic.h"
#include "intel_audio.h"
#include "intel_connector.h"
#include "intel_ddi.h"
#include "intel_display_types.h"
#include "intel_dp.h"
+#include "intel_dp_aux.h"
#include "intel_dp_link_training.h"
#include "intel_dp_mst.h"
#include "intel_dpio_phy.h"
@@ -833,680 +833,6 @@ intel_dp_mode_valid(struct drm_connector *connector,
return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
}
-u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
-{
- int i;
- u32 v = 0;
-
- if (src_bytes > 4)
- src_bytes = 4;
- for (i = 0; i < src_bytes; i++)
- v |= ((u32)src[i]) << ((3 - i) * 8);
- return v;
-}
-
-static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
-{
- int i;
- if (dst_bytes > 4)
- dst_bytes = 4;
- for (i = 0; i < dst_bytes; i++)
- dst[i] = src >> ((3-i) * 8);
-}
-
-static u32
-intel_dp_aux_wait_done(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
- const unsigned int timeout_ms = 10;
- u32 status;
- bool done;
-
-#define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
- done = wait_event_timeout(i915->gmbus_wait_queue, C,
- msecs_to_jiffies_timeout(timeout_ms));
-
- /* just trace the final value */
- trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
-
- if (!done)
- drm_err(&i915->drm,
- "%s: did not complete or timeout within %ums (status 0x%08x)\n",
- intel_dp->aux.name, timeout_ms, status);
-#undef C
-
- return status;
-}
-
-static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-
- if (index)
- return 0;
-
- /*
- * The clock divider is based off the hrawclk, and would like to run at
- * 2MHz. So, take the hrawclk value and divide by 2000 and use that
- */
- return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000);
-}
-
-static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- u32 freq;
-
- if (index)
- return 0;
-
- /*
- * The clock divider is based off the cdclk or PCH rawclk, and would
- * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
- * divide by 2000 and use that
- */
- if (dig_port->aux_ch == AUX_CH_A)
- freq = dev_priv->cdclk.hw.cdclk;
- else
- freq = RUNTIME_INFO(dev_priv)->rawclk_freq;
- return DIV_ROUND_CLOSEST(freq, 2000);
-}
-
-static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-
- if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
- /* Workaround for non-ULT HSW */
- switch (index) {
- case 0: return 63;
- case 1: return 72;
- default: return 0;
- }
- }
-
- return ilk_get_aux_clock_divider(intel_dp, index);
-}
-
-static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
-{
- /*
- * SKL doesn't need us to program the AUX clock divider (Hardware will
- * derive the clock from CDCLK automatically). We still implement the
- * get_aux_clock_divider vfunc to plug-in into the existing code.
- */
- return index ? 0 : 1;
-}
-
-static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
- int send_bytes,
- u32 aux_clock_divider)
-{
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- struct drm_i915_private *dev_priv =
- to_i915(dig_port->base.base.dev);
- u32 precharge, timeout;
-
- if (IS_GEN(dev_priv, 6))
- precharge = 3;
- else
- precharge = 5;
-
- if (IS_BROADWELL(dev_priv))
- timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
- else
- timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
-
- return DP_AUX_CH_CTL_SEND_BUSY |
- DP_AUX_CH_CTL_DONE |
- DP_AUX_CH_CTL_INTERRUPT |
- DP_AUX_CH_CTL_TIME_OUT_ERROR |
- timeout |
- DP_AUX_CH_CTL_RECEIVE_ERROR |
- (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
- (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
- (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
-}
-
-static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
- int send_bytes,
- u32 unused)
-{
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- struct drm_i915_private *i915 =
- to_i915(dig_port->base.base.dev);
- enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
- u32 ret;
-
- ret = DP_AUX_CH_CTL_SEND_BUSY |
- DP_AUX_CH_CTL_DONE |
- DP_AUX_CH_CTL_INTERRUPT |
- DP_AUX_CH_CTL_TIME_OUT_ERROR |
- DP_AUX_CH_CTL_TIME_OUT_MAX |
- DP_AUX_CH_CTL_RECEIVE_ERROR |
- (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
- DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
- DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
-
- if (intel_phy_is_tc(i915, phy) &&
- dig_port->tc_mode == TC_PORT_TBT_ALT)
- ret |= DP_AUX_CH_CTL_TBT_IO;
-
- return ret;
-}
-
-static int
-intel_dp_aux_xfer(struct intel_dp *intel_dp,
- const u8 *send, int send_bytes,
- u8 *recv, int recv_size,
- u32 aux_send_ctl_flags)
-{
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- struct drm_i915_private *i915 =
- to_i915(dig_port->base.base.dev);
- struct intel_uncore *uncore = &i915->uncore;
- enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
- bool is_tc_port = intel_phy_is_tc(i915, phy);
- i915_reg_t ch_ctl, ch_data[5];
- u32 aux_clock_divider;
- enum intel_display_power_domain aux_domain;
- intel_wakeref_t aux_wakeref;
- intel_wakeref_t pps_wakeref;
- int i, ret, recv_bytes;
- int try, clock = 0;
- u32 status;
- bool vdd;
-
- ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
- for (i = 0; i < ARRAY_SIZE(ch_data); i++)
- ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
-
- if (is_tc_port)
- intel_tc_port_lock(dig_port);
-
- aux_domain = intel_aux_power_domain(dig_port);
-
- aux_wakeref = intel_display_power_get(i915, aux_domain);
- pps_wakeref = intel_pps_lock(intel_dp);
-
- /*
- * We will be called with VDD already enabled for dpcd/edid/oui reads.
- * In such cases we want to leave VDD enabled and it's up to upper layers
- * to turn it off. But for eg. i2c-dev access we need to turn it on/off
- * ourselves.
- */
- vdd = intel_pps_vdd_on_unlocked(intel_dp);
-
- /* dp aux is extremely sensitive to irq latency, hence request the
- * lowest possible wakeup latency and so prevent the cpu from going into
- * deep sleep states.
- */
- cpu_latency_qos_update_request(&i915->pm_qos, 0);
-
- intel_pps_check_power_unlocked(intel_dp);
-
- /* Try to wait for any previous AUX channel activity */
- for (try = 0; try < 3; try++) {
- status = intel_uncore_read_notrace(uncore, ch_ctl);
- if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
- break;
- msleep(1);
- }
- /* just trace the final value */
- trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
-
- if (try == 3) {
- const u32 status = intel_uncore_read(uncore, ch_ctl);
-
- if (status != intel_dp->aux_busy_last_status) {
- drm_WARN(&i915->drm, 1,
- "%s: not started (status 0x%08x)\n",
- intel_dp->aux.name, status);
- intel_dp->aux_busy_last_status = status;
- }
-
- ret = -EBUSY;
- goto out;
- }
-
- /* Only 5 data registers! */
- if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) {
- ret = -E2BIG;
- goto out;
- }
-
- while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
- u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
- send_bytes,
- aux_clock_divider);
-
- send_ctl |= aux_send_ctl_flags;
-
- /* Must try at least 3 times according to DP spec */
- for (try = 0; try < 5; try++) {
- /* Load the send data into the aux channel data registers */
- for (i = 0; i < send_bytes; i += 4)
- intel_uncore_write(uncore,
- ch_data[i >> 2],
- intel_dp_pack_aux(send + i,
- send_bytes - i));
-
- /* Send the command and wait for it to complete */
- intel_uncore_write(uncore, ch_ctl, send_ctl);
-
- status = intel_dp_aux_wait_done(intel_dp);
-
- /* Clear done status and any errors */
- intel_uncore_write(uncore,
- ch_ctl,
- status |
- DP_AUX_CH_CTL_DONE |
- DP_AUX_CH_CTL_TIME_OUT_ERROR |
- DP_AUX_CH_CTL_RECEIVE_ERROR);
-
- /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
- * 400us delay required for errors and timeouts
- * Timeout errors from the HW already meet this
- * requirement so skip to next iteration
- */
- if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
- continue;
-
- if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
- usleep_range(400, 500);
- continue;
- }
- if (status & DP_AUX_CH_CTL_DONE)
- goto done;
- }
- }
-
- if ((status & DP_AUX_CH_CTL_DONE) == 0) {
- drm_err(&i915->drm, "%s: not done (status 0x%08x)\n",
- intel_dp->aux.name, status);
- ret = -EBUSY;
- goto out;
- }
-
-done:
- /* Check for timeout or receive error.
- * Timeouts occur when the sink is not connected
- */
- if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
- drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n",
- intel_dp->aux.name, status);
- ret = -EIO;
- goto out;
- }
-
- /* Timeouts occur when the device isn't connected, so they're
- * "normal" -- don't fill the kernel log with these */
- if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
- drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n",
- intel_dp->aux.name, status);
- ret = -ETIMEDOUT;
- goto out;
- }
-
- /* Unload any bytes sent back from the other side */
- recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
- DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
-
- /*
- * By BSpec: "Message sizes of 0 or >20 are not allowed."
- * We have no idea of what happened so we return -EBUSY so
- * drm layer takes care for the necessary retries.
- */
- if (recv_bytes == 0 || recv_bytes > 20) {
- drm_dbg_kms(&i915->drm,
- "%s: Forbidden recv_bytes = %d on aux transaction\n",
- intel_dp->aux.name, recv_bytes);
- ret = -EBUSY;
- goto out;
- }
-
- if (recv_bytes > recv_size)
- recv_bytes = recv_size;
-
- for (i = 0; i < recv_bytes; i += 4)
- intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]),
- recv + i, recv_bytes - i);
-
- ret = recv_bytes;
-out:
- cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
-
- if (vdd)
- intel_pps_vdd_off_unlocked(intel_dp, false);
-
- intel_pps_unlock(intel_dp, pps_wakeref);
- intel_display_power_put_async(i915, aux_domain, aux_wakeref);
-
- if (is_tc_port)
- intel_tc_port_unlock(dig_port);
-
- return ret;
-}
-
-#define BARE_ADDRESS_SIZE 3
-#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
-
-static void
-intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
- const struct drm_dp_aux_msg *msg)
-{
- txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
- txbuf[1] = (msg->address >> 8) & 0xff;
- txbuf[2] = msg->address & 0xff;
- txbuf[3] = msg->size - 1;
-}
-
-static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg)
-{
- /*
- * If we're trying to send the HDCP Aksv, we need to set a the Aksv
- * select bit to inform the hardware to send the Aksv after our header
- * since we can't access that data from software.
- */
- if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE &&
- msg->address == DP_AUX_HDCP_AKSV)
- return DP_AUX_CH_CTL_AUX_AKSV_SELECT;
-
- return 0;
-}
-
-static ssize_t
-intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
-{
- struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- u8 txbuf[20], rxbuf[20];
- size_t txsize, rxsize;
- u32 flags = intel_dp_aux_xfer_flags(msg);
- int ret;
-
- intel_dp_aux_header(txbuf, msg);
-
- switch (msg->request & ~DP_AUX_I2C_MOT) {
- case DP_AUX_NATIVE_WRITE:
- case DP_AUX_I2C_WRITE:
- case DP_AUX_I2C_WRITE_STATUS_UPDATE:
- txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
- rxsize = 2; /* 0 or 1 data bytes */
-
- if (drm_WARN_ON(&i915->drm, txsize > 20))
- return -E2BIG;
-
- drm_WARN_ON(&i915->drm, !msg->buffer != !msg->size);
-
- if (msg->buffer)
- memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
-
- ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
- rxbuf, rxsize, flags);
- if (ret > 0) {
- msg->reply = rxbuf[0] >> 4;
-
- if (ret > 1) {
- /* Number of bytes written in a short write. */
- ret = clamp_t(int, rxbuf[1], 0, msg->size);
- } else {
- /* Return payload size. */
- ret = msg->size;
- }
- }
- break;
-
- case DP_AUX_NATIVE_READ:
- case DP_AUX_I2C_READ:
- txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
- rxsize = msg->size + 1;
-
- if (drm_WARN_ON(&i915->drm, rxsize > 20))
- return -E2BIG;
-
- ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
- rxbuf, rxsize, flags);
- if (ret > 0) {
- msg->reply = rxbuf[0] >> 4;
- /*
- * Assume happy day, and copy the data. The caller is
- * expected to check msg->reply before touching it.
- *
- * Return payload size.
- */
- ret--;
- memcpy(msg->buffer, rxbuf + 1, ret);
- }
- break;
-
- default:
- ret = -EINVAL;
- break;
- }
-
- return ret;
-}
-
-
-static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- enum aux_ch aux_ch = dig_port->aux_ch;
-
- switch (aux_ch) {
- case AUX_CH_B:
- case AUX_CH_C:
- case AUX_CH_D:
- return DP_AUX_CH_CTL(aux_ch);
- default:
- MISSING_CASE(aux_ch);
- return DP_AUX_CH_CTL(AUX_CH_B);
- }
-}
-
-static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- enum aux_ch aux_ch = dig_port->aux_ch;
-
- switch (aux_ch) {
- case AUX_CH_B:
- case AUX_CH_C:
- case AUX_CH_D:
- return DP_AUX_CH_DATA(aux_ch, index);
- default:
- MISSING_CASE(aux_ch);
- return DP_AUX_CH_DATA(AUX_CH_B, index);
- }
-}
-
-static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- enum aux_ch aux_ch = dig_port->aux_ch;
-
- switch (aux_ch) {
- case AUX_CH_A:
- return DP_AUX_CH_CTL(aux_ch);
- case AUX_CH_B:
- case AUX_CH_C:
- case AUX_CH_D:
- return PCH_DP_AUX_CH_CTL(aux_ch);
- default:
- MISSING_CASE(aux_ch);
- return DP_AUX_CH_CTL(AUX_CH_A);
- }
-}
-
-static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- enum aux_ch aux_ch = dig_port->aux_ch;
-
- switch (aux_ch) {
- case AUX_CH_A:
- return DP_AUX_CH_DATA(aux_ch, index);
- case AUX_CH_B:
- case AUX_CH_C:
- case AUX_CH_D:
- return PCH_DP_AUX_CH_DATA(aux_ch, index);
- default:
- MISSING_CASE(aux_ch);
- return DP_AUX_CH_DATA(AUX_CH_A, index);
- }
-}
-
-static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- enum aux_ch aux_ch = dig_port->aux_ch;
-
- switch (aux_ch) {
- case AUX_CH_A:
- case AUX_CH_B:
- case AUX_CH_C:
- case AUX_CH_D:
- case AUX_CH_E:
- case AUX_CH_F:
- return DP_AUX_CH_CTL(aux_ch);
- default:
- MISSING_CASE(aux_ch);
- return DP_AUX_CH_CTL(AUX_CH_A);
- }
-}
-
-static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- enum aux_ch aux_ch = dig_port->aux_ch;
-
- switch (aux_ch) {
- case AUX_CH_A:
- case AUX_CH_B:
- case AUX_CH_C:
- case AUX_CH_D:
- case AUX_CH_E:
- case AUX_CH_F:
- return DP_AUX_CH_DATA(aux_ch, index);
- default:
- MISSING_CASE(aux_ch);
- return DP_AUX_CH_DATA(AUX_CH_A, index);
- }
-}
-
-static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- enum aux_ch aux_ch = dig_port->aux_ch;
-
- switch (aux_ch) {
- case AUX_CH_A:
- case AUX_CH_B:
- case AUX_CH_C:
- case AUX_CH_USBC1:
- case AUX_CH_USBC2:
- case AUX_CH_USBC3:
- case AUX_CH_USBC4:
- case AUX_CH_USBC5:
- case AUX_CH_USBC6:
- return DP_AUX_CH_CTL(aux_ch);
- default:
- MISSING_CASE(aux_ch);
- return DP_AUX_CH_CTL(AUX_CH_A);
- }
-}
-
-static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- enum aux_ch aux_ch = dig_port->aux_ch;
-
- switch (aux_ch) {
- case AUX_CH_A:
- case AUX_CH_B:
- case AUX_CH_C:
- case AUX_CH_USBC1:
- case AUX_CH_USBC2:
- case AUX_CH_USBC3:
- case AUX_CH_USBC4:
- case AUX_CH_USBC5:
- case AUX_CH_USBC6:
- return DP_AUX_CH_DATA(aux_ch, index);
- default:
- MISSING_CASE(aux_ch);
- return DP_AUX_CH_DATA(AUX_CH_A, index);
- }
-}
-
-static void
-intel_dp_aux_fini(struct intel_dp *intel_dp)
-{
- kfree(intel_dp->aux.name);
-}
-
-static void
-intel_dp_aux_init(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- struct intel_encoder *encoder = &dig_port->base;
- enum aux_ch aux_ch = dig_port->aux_ch;
-
- if (INTEL_GEN(dev_priv) >= 12) {
- intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
- intel_dp->aux_ch_data_reg = tgl_aux_data_reg;
- } else if (INTEL_GEN(dev_priv) >= 9) {
- intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
- intel_dp->aux_ch_data_reg = skl_aux_data_reg;
- } else if (HAS_PCH_SPLIT(dev_priv)) {
- intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
- intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
- } else {
- intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
- intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
- }
-
- if (INTEL_GEN(dev_priv) >= 9)
- intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
- else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
- intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
- else if (HAS_PCH_SPLIT(dev_priv))
- intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
- else
- intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
-
- if (INTEL_GEN(dev_priv) >= 9)
- intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
- else
- intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
-
- drm_dp_aux_init(&intel_dp->aux);
-
- /* Failure to allocate our preferred name is not critical */
- if (INTEL_GEN(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
- intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s",
- aux_ch - AUX_CH_USBC1 + '1',
- encoder->base.name);
- else
- intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s",
- aux_ch_name(aux_ch),
- encoder->base.name);
-
- intel_dp->aux.transfer = intel_dp_aux_transfer;
-}
-
bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
{
int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
new file mode 100644
index 000000000000..89294c144c47
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -0,0 +1,683 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "i915_trace.h"
+#include "intel_display_types.h"
+#include "intel_dp_aux.h"
+#include "intel_pps.h"
+#include "intel_tc.h"
+
+u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
+{
+ int i;
+ u32 v = 0;
+
+ if (src_bytes > 4)
+ src_bytes = 4;
+ for (i = 0; i < src_bytes; i++)
+ v |= ((u32)src[i]) << ((3 - i) * 8);
+ return v;
+}
+
+static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
+{
+ int i;
+ if (dst_bytes > 4)
+ dst_bytes = 4;
+ for (i = 0; i < dst_bytes; i++)
+ dst[i] = src >> ((3-i) * 8);
+}
+
+static u32
+intel_dp_aux_wait_done(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
+ const unsigned int timeout_ms = 10;
+ u32 status;
+ bool done;
+
+#define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
+ done = wait_event_timeout(i915->gmbus_wait_queue, C,
+ msecs_to_jiffies_timeout(timeout_ms));
+
+ /* just trace the final value */
+ trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
+
+ if (!done)
+ drm_err(&i915->drm,
+ "%s: did not complete or timeout within %ums (status 0x%08x)\n",
+ intel_dp->aux.name, timeout_ms, status);
+#undef C
+
+ return status;
+}
+
+static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ if (index)
+ return 0;
+
+ /*
+ * The clock divider is based off the hrawclk, and would like to run at
+ * 2MHz. So, take the hrawclk value and divide by 2000 and use that
+ */
+ return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000);
+}
+
+static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ u32 freq;
+
+ if (index)
+ return 0;
+
+ /*
+ * The clock divider is based off the cdclk or PCH rawclk, and would
+ * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
+ * divide by 2000 and use that
+ */
+ if (dig_port->aux_ch == AUX_CH_A)
+ freq = dev_priv->cdclk.hw.cdclk;
+ else
+ freq = RUNTIME_INFO(dev_priv)->rawclk_freq;
+ return DIV_ROUND_CLOSEST(freq, 2000);
+}
+
+static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+
+ if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
+ /* Workaround for non-ULT HSW */
+ switch (index) {
+ case 0: return 63;
+ case 1: return 72;
+ default: return 0;
+ }
+ }
+
+ return ilk_get_aux_clock_divider(intel_dp, index);
+}
+
+static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
+{
+ /*
+ * SKL doesn't need us to program the AUX clock divider (Hardware will
+ * derive the clock from CDCLK automatically). We still implement the
+ * get_aux_clock_divider vfunc to plug-in into the existing code.
+ */
+ return index ? 0 : 1;
+}
+
+static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
+ int send_bytes,
+ u32 aux_clock_divider)
+{
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct drm_i915_private *dev_priv =
+ to_i915(dig_port->base.base.dev);
+ u32 precharge, timeout;
+
+ if (IS_GEN(dev_priv, 6))
+ precharge = 3;
+ else
+ precharge = 5;
+
+ if (IS_BROADWELL(dev_priv))
+ timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
+ else
+ timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
+
+ return DP_AUX_CH_CTL_SEND_BUSY |
+ DP_AUX_CH_CTL_DONE |
+ DP_AUX_CH_CTL_INTERRUPT |
+ DP_AUX_CH_CTL_TIME_OUT_ERROR |
+ timeout |
+ DP_AUX_CH_CTL_RECEIVE_ERROR |
+ (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
+ (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
+ (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
+}
+
+static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
+ int send_bytes,
+ u32 unused)
+{
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct drm_i915_private *i915 =
+ to_i915(dig_port->base.base.dev);
+ enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
+ u32 ret;
+
+ ret = DP_AUX_CH_CTL_SEND_BUSY |
+ DP_AUX_CH_CTL_DONE |
+ DP_AUX_CH_CTL_INTERRUPT |
+ DP_AUX_CH_CTL_TIME_OUT_ERROR |
+ DP_AUX_CH_CTL_TIME_OUT_MAX |
+ DP_AUX_CH_CTL_RECEIVE_ERROR |
+ (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
+ DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
+ DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
+
+ if (intel_phy_is_tc(i915, phy) &&
+ dig_port->tc_mode == TC_PORT_TBT_ALT)
+ ret |= DP_AUX_CH_CTL_TBT_IO;
+
+ return ret;
+}
+
+static int
+intel_dp_aux_xfer(struct intel_dp *intel_dp,
+ const u8 *send, int send_bytes,
+ u8 *recv, int recv_size,
+ u32 aux_send_ctl_flags)
+{
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct drm_i915_private *i915 =
+ to_i915(dig_port->base.base.dev);
+ struct intel_uncore *uncore = &i915->uncore;
+ enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
+ bool is_tc_port = intel_phy_is_tc(i915, phy);
+ i915_reg_t ch_ctl, ch_data[5];
+ u32 aux_clock_divider;
+ enum intel_display_power_domain aux_domain;
+ intel_wakeref_t aux_wakeref;
+ intel_wakeref_t pps_wakeref;
+ int i, ret, recv_bytes;
+ int try, clock = 0;
+ u32 status;
+ bool vdd;
+
+ ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
+ for (i = 0; i < ARRAY_SIZE(ch_data); i++)
+ ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
+
+ if (is_tc_port)
+ intel_tc_port_lock(dig_port);
+
+ aux_domain = intel_aux_power_domain(dig_port);
+
+ aux_wakeref = intel_display_power_get(i915, aux_domain);
+ pps_wakeref = intel_pps_lock(intel_dp);
+
+ /*
+ * We will be called with VDD already enabled for dpcd/edid/oui reads.
+ * In such cases we want to leave VDD enabled and it's up to upper layers
+ * to turn it off. But for eg. i2c-dev access we need to turn it on/off
+ * ourselves.
+ */
+ vdd = intel_pps_vdd_on_unlocked(intel_dp);
+
+ /* dp aux is extremely sensitive to irq latency, hence request the
+ * lowest possible wakeup latency and so prevent the cpu from going into
+ * deep sleep states.
+ */
+ cpu_latency_qos_update_request(&i915->pm_qos, 0);
+
+ intel_pps_check_power_unlocked(intel_dp);
+
+ /* Try to wait for any previous AUX channel activity */
+ for (try = 0; try < 3; try++) {
+ status = intel_uncore_read_notrace(uncore, ch_ctl);
+ if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
+ break;
+ msleep(1);
+ }
+ /* just trace the final value */
+ trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
+
+ if (try == 3) {
+ const u32 status = intel_uncore_read(uncore, ch_ctl);
+
+ if (status != intel_dp->aux_busy_last_status) {
+ drm_WARN(&i915->drm, 1,
+ "%s: not started (status 0x%08x)\n",
+ intel_dp->aux.name, status);
+ intel_dp->aux_busy_last_status = status;
+ }
+
+ ret = -EBUSY;
+ goto out;
+ }
+
+ /* Only 5 data registers! */
+ if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) {
+ ret = -E2BIG;
+ goto out;
+ }
+
+ while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
+ u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
+ send_bytes,
+ aux_clock_divider);
+
+ send_ctl |= aux_send_ctl_flags;
+
+ /* Must try at least 3 times according to DP spec */
+ for (try = 0; try < 5; try++) {
+ /* Load the send data into the aux channel data registers */
+ for (i = 0; i < send_bytes; i += 4)
+ intel_uncore_write(uncore,
+ ch_data[i >> 2],
+ intel_dp_pack_aux(send + i,
+ send_bytes - i));
+
+ /* Send the command and wait for it to complete */
+ intel_uncore_write(uncore, ch_ctl, send_ctl);
+
+ status = intel_dp_aux_wait_done(intel_dp);
+
+ /* Clear done status and any errors */
+ intel_uncore_write(uncore,
+ ch_ctl,
+ status |
+ DP_AUX_CH_CTL_DONE |
+ DP_AUX_CH_CTL_TIME_OUT_ERROR |
+ DP_AUX_CH_CTL_RECEIVE_ERROR);
+
+ /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
+ * 400us delay required for errors and timeouts
+ * Timeout errors from the HW already meet this
+ * requirement so skip to next iteration
+ */
+ if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
+ continue;
+
+ if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
+ usleep_range(400, 500);
+ continue;
+ }
+ if (status & DP_AUX_CH_CTL_DONE)
+ goto done;
+ }
+ }
+
+ if ((status & DP_AUX_CH_CTL_DONE) == 0) {
+ drm_err(&i915->drm, "%s: not done (status 0x%08x)\n",
+ intel_dp->aux.name, status);
+ ret = -EBUSY;
+ goto out;
+ }
+
+done:
+ /* Check for timeout or receive error.
+ * Timeouts occur when the sink is not connected
+ */
+ if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
+ drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n",
+ intel_dp->aux.name, status);
+ ret = -EIO;
+ goto out;
+ }
+
+ /* Timeouts occur when the device isn't connected, so they're
+ * "normal" -- don't fill the kernel log with these */
+ if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
+ drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n",
+ intel_dp->aux.name, status);
+ ret = -ETIMEDOUT;
+ goto out;
+ }
+
+ /* Unload any bytes sent back from the other side */
+ recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
+ DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
+
+ /*
+ * By BSpec: "Message sizes of 0 or >20 are not allowed."
+ * We have no idea of what happened so we return -EBUSY so
+ * drm layer takes care for the necessary retries.
+ */
+ if (recv_bytes == 0 || recv_bytes > 20) {
+ drm_dbg_kms(&i915->drm,
+ "%s: Forbidden recv_bytes = %d on aux transaction\n",
+ intel_dp->aux.name, recv_bytes);
+ ret = -EBUSY;
+ goto out;
+ }
+
+ if (recv_bytes > recv_size)
+ recv_bytes = recv_size;
+
+ for (i = 0; i < recv_bytes; i += 4)
+ intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]),
+ recv + i, recv_bytes - i);
+
+ ret = recv_bytes;
+out:
+ cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
+
+ if (vdd)
+ intel_pps_vdd_off_unlocked(intel_dp, false);
+
+ intel_pps_unlock(intel_dp, pps_wakeref);
+ intel_display_power_put_async(i915, aux_domain, aux_wakeref);
+
+ if (is_tc_port)
+ intel_tc_port_unlock(dig_port);
+
+ return ret;
+}
+
+#define BARE_ADDRESS_SIZE 3
+#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
+
+static void
+intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
+ const struct drm_dp_aux_msg *msg)
+{
+ txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
+ txbuf[1] = (msg->address >> 8) & 0xff;
+ txbuf[2] = msg->address & 0xff;
+ txbuf[3] = msg->size - 1;
+}
+
+static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg)
+{
+ /*
+ * If we're trying to send the HDCP Aksv, we need to set a the Aksv
+ * select bit to inform the hardware to send the Aksv after our header
+ * since we can't access that data from software.
+ */
+ if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE &&
+ msg->address == DP_AUX_HDCP_AKSV)
+ return DP_AUX_CH_CTL_AUX_AKSV_SELECT;
+
+ return 0;
+}
+
+static ssize_t
+intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
+{
+ struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ u8 txbuf[20], rxbuf[20];
+ size_t txsize, rxsize;
+ u32 flags = intel_dp_aux_xfer_flags(msg);
+ int ret;
+
+ intel_dp_aux_header(txbuf, msg);
+
+ switch (msg->request & ~DP_AUX_I2C_MOT) {
+ case DP_AUX_NATIVE_WRITE:
+ case DP_AUX_I2C_WRITE:
+ case DP_AUX_I2C_WRITE_STATUS_UPDATE:
+ txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
+ rxsize = 2; /* 0 or 1 data bytes */
+
+ if (drm_WARN_ON(&i915->drm, txsize > 20))
+ return -E2BIG;
+
+ drm_WARN_ON(&i915->drm, !msg->buffer != !msg->size);
+
+ if (msg->buffer)
+ memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
+
+ ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
+ rxbuf, rxsize, flags);
+ if (ret > 0) {
+ msg->reply = rxbuf[0] >> 4;
+
+ if (ret > 1) {
+ /* Number of bytes written in a short write. */
+ ret = clamp_t(int, rxbuf[1], 0, msg->size);
+ } else {
+ /* Return payload size. */
+ ret = msg->size;
+ }
+ }
+ break;
+
+ case DP_AUX_NATIVE_READ:
+ case DP_AUX_I2C_READ:
+ txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
+ rxsize = msg->size + 1;
+
+ if (drm_WARN_ON(&i915->drm, rxsize > 20))
+ return -E2BIG;
+
+ ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
+ rxbuf, rxsize, flags);
+ if (ret > 0) {
+ msg->reply = rxbuf[0] >> 4;
+ /*
+ * Assume happy day, and copy the data. The caller is
+ * expected to check msg->reply before touching it.
+ *
+ * Return payload size.
+ */
+ ret--;
+ memcpy(msg->buffer, rxbuf + 1, ret);
+ }
+ break;
+
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
+
+static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum aux_ch aux_ch = dig_port->aux_ch;
+
+ switch (aux_ch) {
+ case AUX_CH_B:
+ case AUX_CH_C:
+ case AUX_CH_D:
+ return DP_AUX_CH_CTL(aux_ch);
+ default:
+ MISSING_CASE(aux_ch);
+ return DP_AUX_CH_CTL(AUX_CH_B);
+ }
+}
+
+static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum aux_ch aux_ch = dig_port->aux_ch;
+
+ switch (aux_ch) {
+ case AUX_CH_B:
+ case AUX_CH_C:
+ case AUX_CH_D:
+ return DP_AUX_CH_DATA(aux_ch, index);
+ default:
+ MISSING_CASE(aux_ch);
+ return DP_AUX_CH_DATA(AUX_CH_B, index);
+ }
+}
+
+static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum aux_ch aux_ch = dig_port->aux_ch;
+
+ switch (aux_ch) {
+ case AUX_CH_A:
+ return DP_AUX_CH_CTL(aux_ch);
+ case AUX_CH_B:
+ case AUX_CH_C:
+ case AUX_CH_D:
+ return PCH_DP_AUX_CH_CTL(aux_ch);
+ default:
+ MISSING_CASE(aux_ch);
+ return DP_AUX_CH_CTL(AUX_CH_A);
+ }
+}
+
+static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum aux_ch aux_ch = dig_port->aux_ch;
+
+ switch (aux_ch) {
+ case AUX_CH_A:
+ return DP_AUX_CH_DATA(aux_ch, index);
+ case AUX_CH_B:
+ case AUX_CH_C:
+ case AUX_CH_D:
+ return PCH_DP_AUX_CH_DATA(aux_ch, index);
+ default:
+ MISSING_CASE(aux_ch);
+ return DP_AUX_CH_DATA(AUX_CH_A, index);
+ }
+}
+
+static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum aux_ch aux_ch = dig_port->aux_ch;
+
+ switch (aux_ch) {
+ case AUX_CH_A:
+ case AUX_CH_B:
+ case AUX_CH_C:
+ case AUX_CH_D:
+ case AUX_CH_E:
+ case AUX_CH_F:
+ return DP_AUX_CH_CTL(aux_ch);
+ default:
+ MISSING_CASE(aux_ch);
+ return DP_AUX_CH_CTL(AUX_CH_A);
+ }
+}
+
+static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum aux_ch aux_ch = dig_port->aux_ch;
+
+ switch (aux_ch) {
+ case AUX_CH_A:
+ case AUX_CH_B:
+ case AUX_CH_C:
+ case AUX_CH_D:
+ case AUX_CH_E:
+ case AUX_CH_F:
+ return DP_AUX_CH_DATA(aux_ch, index);
+ default:
+ MISSING_CASE(aux_ch);
+ return DP_AUX_CH_DATA(AUX_CH_A, index);
+ }
+}
+
+static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum aux_ch aux_ch = dig_port->aux_ch;
+
+ switch (aux_ch) {
+ case AUX_CH_A:
+ case AUX_CH_B:
+ case AUX_CH_C:
+ case AUX_CH_USBC1:
+ case AUX_CH_USBC2:
+ case AUX_CH_USBC3:
+ case AUX_CH_USBC4:
+ case AUX_CH_USBC5:
+ case AUX_CH_USBC6:
+ return DP_AUX_CH_CTL(aux_ch);
+ default:
+ MISSING_CASE(aux_ch);
+ return DP_AUX_CH_CTL(AUX_CH_A);
+ }
+}
+
+static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum aux_ch aux_ch = dig_port->aux_ch;
+
+ switch (aux_ch) {
+ case AUX_CH_A:
+ case AUX_CH_B:
+ case AUX_CH_C:
+ case AUX_CH_USBC1:
+ case AUX_CH_USBC2:
+ case AUX_CH_USBC3:
+ case AUX_CH_USBC4:
+ case AUX_CH_USBC5:
+ case AUX_CH_USBC6:
+ return DP_AUX_CH_DATA(aux_ch, index);
+ default:
+ MISSING_CASE(aux_ch);
+ return DP_AUX_CH_DATA(AUX_CH_A, index);
+ }
+}
+
+void intel_dp_aux_fini(struct intel_dp *intel_dp)
+{
+ kfree(intel_dp->aux.name);
+}
+
+void intel_dp_aux_init(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct intel_encoder *encoder = &dig_port->base;
+ enum aux_ch aux_ch = dig_port->aux_ch;
+
+ if (INTEL_GEN(dev_priv) >= 12) {
+ intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
+ intel_dp->aux_ch_data_reg = tgl_aux_data_reg;
+ } else if (INTEL_GEN(dev_priv) >= 9) {
+ intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
+ intel_dp->aux_ch_data_reg = skl_aux_data_reg;
+ } else if (HAS_PCH_SPLIT(dev_priv)) {
+ intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
+ intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
+ } else {
+ intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
+ intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
+ }
+
+ if (INTEL_GEN(dev_priv) >= 9)
+ intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
+ else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
+ intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
+ else if (HAS_PCH_SPLIT(dev_priv))
+ intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
+ else
+ intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
+
+ if (INTEL_GEN(dev_priv) >= 9)
+ intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
+ else
+ intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
+
+ drm_dp_aux_init(&intel_dp->aux);
+
+ /* Failure to allocate our preferred name is not critical */
+ if (INTEL_GEN(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
+ intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s",
+ aux_ch - AUX_CH_USBC1 + '1',
+ encoder->base.name);
+ else
+ intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s",
+ aux_ch_name(aux_ch),
+ encoder->base.name);
+
+ intel_dp->aux.transfer = intel_dp_aux_transfer;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.h b/drivers/gpu/drm/i915/display/intel_dp_aux.h
new file mode 100644
index 000000000000..cea58dd86c49
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#ifndef __INTEL_DP_AUX_H__
+#define __INTEL_DP_AUX_H__
+
+#include <linux/types.h>
+
+struct intel_dp;
+
+u32 intel_dp_pack_aux(const u8 *src, int src_bytes);
+
+void intel_dp_aux_fini(struct intel_dp *intel_dp);
+void intel_dp_aux_init(struct intel_dp *intel_dp);
+
+#endif /* __INTEL_DP_AUX_H__ */
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: split out pps and aux
2020-12-22 14:49 [Intel-gfx] [PATCH 00/13] drm/i915/dp: split out pps and aux Jani Nikula
` (12 preceding siblings ...)
2020-12-22 14:49 ` [Intel-gfx] [PATCH 13/13] drm/i915/dp: split out aux functionality to intel_dp_aux.c Jani Nikula
@ 2020-12-22 15:57 ` Patchwork
2020-12-22 16:26 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-12-22 21:02 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
15 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2020-12-22 15:57 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dp: split out pps and aux
URL : https://patchwork.freedesktop.org/series/85167/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
45bed4116194 drm/i915/pps: abstract panel power sequencer from intel_dp.c
-:1085: CHECK:LINE_SPACING: Please don't use multiple blank lines
#1085: FILE: drivers/gpu/drm/i915/display/intel_dp.c:2525:
+
-:1625: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#1625:
new file mode 100644
-:2078: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#2078: FILE: drivers/gpu/drm/i915/display/intel_pps.c:449:
+#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
-:2079: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#2079: FILE: drivers/gpu/drm/i915/display/intel_pps.c:450:
+#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
-:2079: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#2079: FILE: drivers/gpu/drm/i915/display/intel_pps.c:450:
+#define IDLE_ON_VALUE ^I(PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)$
-:2084: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#2084: FILE: drivers/gpu/drm/i915/display/intel_pps.c:455:
+#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
-:2085: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#2085: FILE: drivers/gpu/drm/i915/display/intel_pps.c:456:
+#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
-:2090: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#2090: FILE: drivers/gpu/drm/i915/display/intel_pps.c:461:
+static void wait_panel_status(struct intel_dp *intel_dp,
+ u32 mask,
-:2144: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#2144: FILE: drivers/gpu/drm/i915/display/intel_pps.c:515:
+ * and then make panel wait for t11_t12 if needed. */
-:2146: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#2146: FILE: drivers/gpu/drm/i915/display/intel_pps.c:517:
+ panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
-:2149: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#2149: FILE: drivers/gpu/drm/i915/display/intel_pps.c:520:
+ * wait. */
-:2152: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#2152: FILE: drivers/gpu/drm/i915/display/intel_pps.c:523:
+ intel_dp->panel_power_cycle_delay - panel_power_off_duration);
-:2152: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#2152: FILE: drivers/gpu/drm/i915/display/intel_pps.c:523:
+ wait_remaining_ms_from_jiffies(jiffies,
+ intel_dp->panel_power_cycle_delay - panel_power_off_duration);
-:2446: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#2446: FILE: drivers/gpu/drm/i915/display/intel_pps.c:817:
+ * panels get very unhappy and cease to work. */
-:2795: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#2795: FILE: drivers/gpu/drm/i915/display/intel_pps.c:1166:
+ * too. */
-:2799: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#2799: FILE: drivers/gpu/drm/i915/display/intel_pps.c:1170:
+ * our hw here, which are all in 100usec. */
-:2807: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#2807: FILE: drivers/gpu/drm/i915/display/intel_pps.c:1178:
+ * too. */
-:2813: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#2813: FILE: drivers/gpu/drm/i915/display/intel_pps.c:1184:
+ * unset, fall back to the spec limits. */
-:2814: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#2814: FILE: drivers/gpu/drm/i915/display/intel_pps.c:1185:
+#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
+ spec.field : \
+ max(cur.field, vbt.field))
-:2814: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'field' - possible side-effects?
#2814: FILE: drivers/gpu/drm/i915/display/intel_pps.c:1185:
+#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
+ spec.field : \
+ max(cur.field, vbt.field))
-:2814: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'field' may be better as '(field)' to avoid precedence issues
#2814: FILE: drivers/gpu/drm/i915/display/intel_pps.c:1185:
+#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
+ spec.field : \
+ max(cur.field, vbt.field))
-:2824: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'field' may be better as '(field)' to avoid precedence issues
#2824: FILE: drivers/gpu/drm/i915/display/intel_pps.c:1195:
+#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
-:2907: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#2907: FILE: drivers/gpu/drm/i915/display/intel_pps.c:1278:
+ * power sequencer any more. */
-:2937: WARNING:LONG_LINE: line length of 176 exceeds 100 columns
#2937: FILE: drivers/gpu/drm/i915/display/intel_pps.c:1308:
+ REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
-:2943: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#2943: FILE: drivers/gpu/drm/i915/display/intel_pps.c:1314:
+ pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
-:2994: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dp' - possible side-effects?
#2994: FILE: drivers/gpu/drm/i915/display/intel_pps.h:22:
+#define with_pps_lock(dp, wf) \
+ for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
-:2994: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'wf' - possible side-effects?
#2994: FILE: drivers/gpu/drm/i915/display/intel_pps.h:22:
+#define with_pps_lock(dp, wf) \
+ for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
total: 1 errors, 18 warnings, 8 checks, 2961 lines checked
9a2c6754aeaf drm/i915/pps: rename pps_{, un}lock -> intel_pps_{, un}lock
-:214: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dp' - possible side-effects?
#214: FILE: drivers/gpu/drm/i915/display/intel_pps.h:22:
+#define with_intel_pps_lock(dp, wf) \
+ for ((wf) = intel_pps_lock(dp); (wf); (wf) = intel_pps_unlock((dp), (wf)))
-:214: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'wf' - possible side-effects?
#214: FILE: drivers/gpu/drm/i915/display/intel_pps.h:22:
+#define with_intel_pps_lock(dp, wf) \
+ for ((wf) = intel_pps_lock(dp); (wf); (wf) = intel_pps_unlock((dp), (wf)))
total: 0 errors, 0 warnings, 2 checks, 176 lines checked
2e71006628ff drm/i915/pps: rename intel_edp_backlight_* to intel_pps_backlight_*
3eb2eaf1f0f6 drm/i915/pps: rename intel_edp_panel_* to intel_pps_*
7ba0bb014e1c drm/i915/pps: rename edp_panel_* to intel_pps_*_unlocked
dbfb9a73ee69 drm/i915/pps: abstract intel_pps_vdd_off_sync
-:89: WARNING:LINE_SPACING: Missing a blank line after declarations
#89: FILE: drivers/gpu/drm/i915/display/intel_pps.c:688:
+ intel_wakeref_t wakeref;
+ if (!intel_dp_is_edp(intel_dp))
total: 0 errors, 1 warnings, 0 checks, 94 lines checked
857aa036bd25 drm/i915/pps: add higher level intel_pps_init() call
9240c60d4690 drm/i915/pps: abstract intel_pps_reinit()
ae78e7086fd8 drm/i915/pps: rename intel_dp_check_edp to intel_pps_check_power_unlocked
21d5787f6bf8 drm/i915/pps: rename intel_power_sequencer_reset to intel_pps_reset_all
1c7a761d30cc drm/i915/pps: add locked intel_pps_wait_power_cycle
438af86b0216 drm/i915/pps: rename vlv_init_panel_power_sequencer to vlv_pps_init
72d1cd923095 drm/i915/dp: split out aux functionality to intel_dp_aux.c
-:724: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#724:
new file mode 100644
-:756: WARNING:LINE_SPACING: Missing a blank line after declarations
#756: FILE: drivers/gpu/drm/i915/display/intel_dp_aux.c:28:
+ int i;
+ if (dst_bytes > 4)
-:759: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
#759: FILE: drivers/gpu/drm/i915/display/intel_dp_aux.c:31:
+ dst[i] = src >> ((3-i) * 8);
^
-:771: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#771: FILE: drivers/gpu/drm/i915/display/intel_dp_aux.c:43:
+#define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
-:961: WARNING:MSLEEP: msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.rst
#961: FILE: drivers/gpu/drm/i915/display/intel_dp_aux.c:233:
+ msleep(1);
-:1051: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#1051: FILE: drivers/gpu/drm/i915/display/intel_dp_aux.c:323:
+ * "normal" -- don't fill the kernel log with these */
-:1199: CHECK:LINE_SPACING: Please don't use multiple blank lines
#1199: FILE: drivers/gpu/drm/i915/display/intel_dp_aux.c:471:
+
+
total: 0 errors, 5 warnings, 2 checks, 1402 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: split out pps and aux
2020-12-22 14:49 [Intel-gfx] [PATCH 00/13] drm/i915/dp: split out pps and aux Jani Nikula
` (13 preceding siblings ...)
2020-12-22 15:57 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: split out pps and aux Patchwork
@ 2020-12-22 16:26 ` Patchwork
2020-12-22 21:02 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
15 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2020-12-22 16:26 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
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== Series Details ==
Series: drm/i915/dp: split out pps and aux
URL : https://patchwork.freedesktop.org/series/85167/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9513 -> Patchwork_19198
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/index.html
Known issues
------------
Here are the changes found in Patchwork_19198 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@semaphore:
- fi-bsw-nick: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/fi-bsw-nick/igt@amdgpu/amd_basic@semaphore.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka: [PASS][2] -> [DMESG-FAIL][3] ([i915#2291] / [i915#541])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
* igt@prime_self_import@basic-with_two_bos:
- fi-tgl-y: [PASS][4] -> [DMESG-WARN][5] ([i915#402])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
#### Possible fixes ####
* igt@debugfs_test@read_all_entries:
- fi-tgl-y: [DMESG-WARN][6] ([i915#402]) -> [PASS][7] +1 similar issue
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/fi-tgl-y/igt@debugfs_test@read_all_entries.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/fi-tgl-y/igt@debugfs_test@read_all_entries.html
* igt@i915_selftest@live@gem_contexts:
- fi-bsw-nick: [INCOMPLETE][8] ([i915#2369]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/fi-bsw-nick/igt@i915_selftest@live@gem_contexts.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/fi-bsw-nick/igt@i915_selftest@live@gem_contexts.html
* igt@i915_selftest@live@hugepages:
- fi-bsw-nick: [DMESG-WARN][10] ([i915#2826]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/fi-bsw-nick/igt@i915_selftest@live@hugepages.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/fi-bsw-nick/igt@i915_selftest@live@hugepages.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2369]: https://gitlab.freedesktop.org/drm/intel/issues/2369
[i915#2826]: https://gitlab.freedesktop.org/drm/intel/issues/2826
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Participating hosts (43 -> 38)
------------------------------
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9513 -> Patchwork_19198
CI-20190529: 20190529
CI_DRM_9513: 983dd11753c6e853d43cd82b3a9e28d9ca84e972 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5916: 2100c6efd2de767a876977ae1a8a6366e4beb643 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19198: 72d1cd92309524f5dbd7ec79fdfc9d54309c271b @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
72d1cd923095 drm/i915/dp: split out aux functionality to intel_dp_aux.c
438af86b0216 drm/i915/pps: rename vlv_init_panel_power_sequencer to vlv_pps_init
1c7a761d30cc drm/i915/pps: add locked intel_pps_wait_power_cycle
21d5787f6bf8 drm/i915/pps: rename intel_power_sequencer_reset to intel_pps_reset_all
ae78e7086fd8 drm/i915/pps: rename intel_dp_check_edp to intel_pps_check_power_unlocked
9240c60d4690 drm/i915/pps: abstract intel_pps_reinit()
857aa036bd25 drm/i915/pps: add higher level intel_pps_init() call
dbfb9a73ee69 drm/i915/pps: abstract intel_pps_vdd_off_sync
7ba0bb014e1c drm/i915/pps: rename edp_panel_* to intel_pps_*_unlocked
3eb2eaf1f0f6 drm/i915/pps: rename intel_edp_panel_* to intel_pps_*
2e71006628ff drm/i915/pps: rename intel_edp_backlight_* to intel_pps_backlight_*
9a2c6754aeaf drm/i915/pps: rename pps_{, un}lock -> intel_pps_{, un}lock
45bed4116194 drm/i915/pps: abstract panel power sequencer from intel_dp.c
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/index.html
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dp: split out pps and aux
2020-12-22 14:49 [Intel-gfx] [PATCH 00/13] drm/i915/dp: split out pps and aux Jani Nikula
` (14 preceding siblings ...)
2020-12-22 16:26 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-12-22 21:02 ` Patchwork
15 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2020-12-22 21:02 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
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== Series Details ==
Series: drm/i915/dp: split out pps and aux
URL : https://patchwork.freedesktop.org/series/85167/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9513_full -> Patchwork_19198_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_19198_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19198_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_19198_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_whisper@basic-queues-forked:
- shard-glk: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-glk6/igt@gem_exec_whisper@basic-queues-forked.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-glk7/igt@gem_exec_whisper@basic-queues-forked.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_exec_fair@basic-none-share@rcs0}:
- shard-iclb: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-iclb8/igt@gem_exec_fair@basic-none-share@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-iclb3/igt@gem_exec_fair@basic-none-share@rcs0.html
* {igt@gem_exec_fair@basic-pace-solo@rcs0}:
- shard-tglb: [PASS][5] -> [FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-tglb3/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-tglb3/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* {igt@gem_exec_fair@basic-pace@rcs0}:
- shard-kbl: [PASS][7] -> [FAIL][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-kbl4/igt@gem_exec_fair@basic-pace@rcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-kbl4/igt@gem_exec_fair@basic-pace@rcs0.html
Known issues
------------
Here are the changes found in Patchwork_19198_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_sseu@invalid-args:
- shard-tglb: NOTRUN -> [SKIP][9] ([i915#280])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-tglb8/igt@gem_ctx_sseu@invalid-args.html
* igt@gem_mmap_gtt@coherency:
- shard-tglb: NOTRUN -> [SKIP][10] ([fdo#111656])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-tglb8/igt@gem_mmap_gtt@coherency.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][11] ([fdo#111615])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-tglb8/igt@kms_big_fb@yf-tiled-8bpp-rotate-270.html
* igt@kms_big_joiner@basic:
- shard-skl: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#2705])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-skl6/igt@kms_big_joiner@basic.html
* igt@kms_color@pipe-b-ctm-0-75:
- shard-tglb: NOTRUN -> [FAIL][13] ([i915#1149] / [i915#315])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-tglb8/igt@kms_color@pipe-b-ctm-0-75.html
* igt@kms_color_chamelium@pipe-c-ctm-negative:
- shard-skl: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +4 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-skl6/igt@kms_color_chamelium@pipe-c-ctm-negative.html
* igt@kms_color_chamelium@pipe-c-ctm-red-to-blue:
- shard-tglb: NOTRUN -> [SKIP][15] ([fdo#109284] / [fdo#111827]) +2 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-tglb8/igt@kms_color_chamelium@pipe-c-ctm-red-to-blue.html
* igt@kms_content_protection@mei_interface:
- shard-tglb: NOTRUN -> [SKIP][16] ([fdo#111828])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-tglb8/igt@kms_content_protection@mei_interface.html
* igt@kms_cursor_crc@pipe-b-cursor-64x21-random:
- shard-skl: [PASS][17] -> [FAIL][18] ([i915#54]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-skl8/igt@kms_cursor_crc@pipe-b-cursor-64x21-random.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-skl2/igt@kms_cursor_crc@pipe-b-cursor-64x21-random.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-skl: [PASS][19] -> [INCOMPLETE][20] ([i915#300])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-skl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-skl8/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge:
- shard-skl: NOTRUN -> [SKIP][21] ([fdo#109271]) +48 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-skl4/igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-hsw: [PASS][22] -> [FAIL][23] ([i915#96])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-hsw7/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-hsw8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
* igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-edp1:
- shard-tglb: NOTRUN -> [FAIL][24] ([i915#2122])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-tglb8/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-edp1.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-move:
- shard-tglb: NOTRUN -> [SKIP][25] ([fdo#111825]) +10 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-move.html
* igt@kms_hdr@static-swap:
- shard-tglb: NOTRUN -> [SKIP][26] ([i915#1187])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-tglb8/igt@kms_hdr@static-swap.html
* igt@kms_pipe_b_c_ivb@disable-pipe-b-enable-pipe-c:
- shard-tglb: NOTRUN -> [SKIP][27] ([fdo#109289]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-tglb8/igt@kms_pipe_b_c_ivb@disable-pipe-b-enable-pipe-c.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][28] -> [FAIL][29] ([fdo#108145] / [i915#265]) +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][30] -> [SKIP][31] ([fdo#109441]) +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-iclb8/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@prime_nv_test@i915_import_cpu_mmap:
- shard-tglb: NOTRUN -> [SKIP][32] ([fdo#109291])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-tglb8/igt@prime_nv_test@i915_import_cpu_mmap.html
#### Possible fixes ####
* {igt@gem_exec_balancer@fairslice}:
- shard-iclb: [FAIL][33] ([i915#2802]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-iclb2/igt@gem_exec_balancer@fairslice.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-iclb8/igt@gem_exec_balancer@fairslice.html
* {igt@gem_exec_fair@basic-none@vecs0}:
- shard-iclb: [FAIL][35] -> [PASS][36] +2 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-iclb4/igt@gem_exec_fair@basic-none@vecs0.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-iclb1/igt@gem_exec_fair@basic-none@vecs0.html
* {igt@gem_exec_fair@basic-pace@vecs0}:
- shard-kbl: [FAIL][37] -> [PASS][38] +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html
* {igt@gem_exec_schedule@u-fairslice@rcs0}:
- shard-skl: [DMESG-WARN][39] ([i915#1610]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-skl8/igt@gem_exec_schedule@u-fairslice@rcs0.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-skl9/igt@gem_exec_schedule@u-fairslice@rcs0.html
* {igt@gem_exec_schedule@u-fairslice@vcs1}:
- shard-tglb: [DMESG-WARN][41] ([i915#2803]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-tglb2/igt@gem_exec_schedule@u-fairslice@vcs1.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-tglb8/igt@gem_exec_schedule@u-fairslice@vcs1.html
* igt@gem_exec_suspend@basic-s3:
- shard-skl: [INCOMPLETE][43] ([i915#198]) -> [PASS][44] +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-skl9/igt@gem_exec_suspend@basic-s3.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-skl4/igt@gem_exec_suspend@basic-s3.html
* igt@gem_exec_whisper@basic-fds-priority-all:
- shard-glk: [DMESG-WARN][45] ([i915#118] / [i915#95]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-glk7/igt@gem_exec_whisper@basic-fds-priority-all.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-glk4/igt@gem_exec_whisper@basic-fds-priority-all.html
* {igt@gem_vm_create@destroy-race}:
- shard-tglb: [TIMEOUT][47] ([i915#2795]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-tglb3/igt@gem_vm_create@destroy-race.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-tglb7/igt@gem_vm_create@destroy-race.html
* igt@kms_async_flips@test-time-stamp:
- shard-tglb: [FAIL][49] ([i915#2597]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-tglb5/igt@kms_async_flips@test-time-stamp.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-tglb3/igt@kms_async_flips@test-time-stamp.html
* igt@kms_cursor_crc@pipe-b-cursor-128x128-onscreen:
- shard-skl: [FAIL][51] ([i915#54]) -> [PASS][52] +1 similar issue
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-skl10/igt@kms_cursor_crc@pipe-b-cursor-128x128-onscreen.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-skl3/igt@kms_cursor_crc@pipe-b-cursor-128x128-onscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-256x85-sliding:
- shard-kbl: [DMESG-WARN][53] ([i915#165]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-256x85-sliding.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-kbl3/igt@kms_cursor_crc@pipe-c-cursor-256x85-sliding.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][55] ([i915#1188]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-skl10/igt@kms_hdr@bpc-switch-dpms.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-skl1/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-snb: [SKIP][57] ([fdo#109271]) -> [PASS][58] +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-snb4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-snb5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [FAIL][59] ([fdo#108145] / [i915#265]) -> [PASS][60] +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][61] ([fdo#109441]) -> [PASS][62] +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-iclb7/igt@kms_psr@psr2_sprite_plane_move.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_psr@suspend:
- shard-tglb: [SKIP][63] ([i915#668]) -> [PASS][64] +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-tglb8/igt@kms_psr@suspend.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-tglb3/igt@kms_psr@suspend.html
* igt@perf@blocking:
- shard-skl: [FAIL][65] ([i915#1542]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-skl9/igt@perf@blocking.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-skl1/igt@perf@blocking.html
#### Warnings ####
* igt@runner@aborted:
- shard-hsw: [FAIL][67] ([i915#2295]) -> [FAIL][68] ([i915#2295] / [i915#483])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-hsw7/igt@runner@aborted.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-hsw1/igt@runner@aborted.html
- shard-glk: ([FAIL][69], [FAIL][70]) ([i915#2295] / [i915#483] / [k.org#202321]) -> ([FAIL][71], [FAIL][72]) ([i915#2295] / [k.org#202321])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-glk9/igt@runner@aborted.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-glk3/igt@runner@aborted.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-glk6/igt@runner@aborted.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-glk4/igt@runner@aborted.html
- shard-tglb: ([FAIL][73], [FAIL][74], [FAIL][75]) ([i915#1602] / [i915#2295] / [i915#2426]) -> ([FAIL][76], [FAIL][77]) ([i915#1602] / [i915#2295])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-tglb2/igt@runner@aborted.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-tglb2/igt@runner@aborted.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-tglb8/igt@runner@aborted.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-tglb8/igt@runner@aborted.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-tglb8/igt@runner@aborted.html
- shard-skl: ([FAIL][78], [FAIL][79]) ([i915#2295] / [i915#2426]) -> ([FAIL][80], [FAIL][81]) ([i915#1814] / [i915#2029] / [i915#2426])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-skl8/igt@runner@aborted.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9513/shard-skl1/igt@runner@aborted.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-skl8/igt@runner@aborted.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/shard-skl9/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#111828]: https://bugs.freedesktop.org/show_bug.cgi?id=111828
[i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1187]: https://gitlab.freedesktop.org/drm/intel/issues/1187
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2597]: https://gitlab.freedesktop.org/drm/intel/issues/2597
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#2795]: https://gitlab.freedesktop.org/drm/intel/issues/2795
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2802]: https://gitlab.freedesktop.org/drm/intel/issues/2802
[i915#2803]: https://gitlab.freedesktop.org/drm/intel/issues/2803
[i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300
[i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
[i915#483]: https://gitlab.freedesktop.org/drm/intel/issues/483
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[i915#96]: https://gitlab.freedesktop.org/drm/intel/issues/96
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_9513 -> Patchwork_19198
CI-20190529: 20190529
CI_DRM_9513: 983dd11753c6e853d43cd82b3a9e28d9ca84e972 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5916: 2100c6efd2de767a876977ae1a8a6366e4beb643 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19198: 72d1cd92309524f5dbd7ec79fdfc9d54309c271b @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19198/index.html
[-- Attachment #1.2: Type: text/html, Size: 22355 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-gfx] [PATCH 02/13] drm/i915/pps: rename pps_{, un}lock -> intel_pps_{, un}lock
2020-12-22 14:49 ` [Intel-gfx] [PATCH 02/13] drm/i915/pps: rename pps_{, un}lock -> intel_pps_{, un}lock Jani Nikula
@ 2020-12-28 10:57 ` Gupta, Anshuman
0 siblings, 0 replies; 35+ messages in thread
From: Gupta, Anshuman @ 2020-12-28 10:57 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Nikula, Jani
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Tuesday, December 22, 2020 8:20 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>
> Subject: [Intel-gfx] [PATCH 02/13] drm/i915/pps: rename pps_{, un}lock ->
> intel_pps_{, un}lock
>
> Start following the usual naming pattern for functions.
LGTM.
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 20 ++++++++++----------
> drivers/gpu/drm/i915/display/intel_pps.c | 21 +++++++++++----------
> drivers/gpu/drm/i915/display/intel_pps.h | 8 ++++----
> 3 files changed, 25 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index d4760c478653..0870872fb594 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1030,7 +1030,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> aux_domain = intel_aux_power_domain(dig_port);
>
> aux_wakeref = intel_display_power_get(i915, aux_domain);
> - pps_wakeref = pps_lock(intel_dp);
> + pps_wakeref = intel_pps_lock(intel_dp);
>
> /*
> * We will be called with VDD already enabled for dpcd/edid/oui
> reads.
> @@ -1182,7 +1182,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> if (vdd)
> edp_panel_vdd_off(intel_dp, false);
>
> - pps_unlock(intel_dp, pps_wakeref);
> + intel_pps_unlock(intel_dp, pps_wakeref);
> intel_display_power_put_async(i915, aux_domain, aux_wakeref);
>
> if (is_tc_port)
> @@ -3153,7 +3153,7 @@ static void intel_enable_dp(struct
> intel_atomic_state *state,
> if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN))
> return;
>
> - with_pps_lock(intel_dp, wakeref) {
> + with_intel_pps_lock(intel_dp, wakeref) {
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_init_panel_power_sequencer(encoder,
> pipe_config);
>
> @@ -3719,7 +3719,7 @@ intel_dp_link_down(struct intel_encoder
> *encoder,
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> intel_wakeref_t wakeref;
>
> - with_pps_lock(intel_dp, wakeref)
> + with_intel_pps_lock(intel_dp, wakeref)
> intel_dp->active_pipe = INVALID_PIPE;
> }
> }
> @@ -5817,7 +5817,7 @@ void intel_dp_encoder_flush_work(struct
> drm_encoder *encoder)
> * vdd might still be enabled do to the delayed vdd off.
> * Make sure vdd is actually turned off here.
> */
> - with_pps_lock(intel_dp, wakeref)
> + with_intel_pps_lock(intel_dp, wakeref)
> edp_panel_vdd_off_sync(intel_dp);
> }
>
> @@ -5845,7 +5845,7 @@ void intel_dp_encoder_suspend(struct
> intel_encoder *intel_encoder)
> * Make sure vdd is actually turned off here.
> */
> cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
> - with_pps_lock(intel_dp, wakeref)
> + with_intel_pps_lock(intel_dp, wakeref)
> edp_panel_vdd_off_sync(intel_dp);
> }
>
> @@ -5857,7 +5857,7 @@ void intel_dp_encoder_shutdown(struct
> intel_encoder *intel_encoder)
> if (!intel_dp_is_edp(intel_dp))
> return;
>
> - with_pps_lock(intel_dp, wakeref)
> + with_intel_pps_lock(intel_dp, wakeref)
> wait_panel_power_cycle(intel_dp);
> }
>
> @@ -5889,7 +5889,7 @@ void intel_dp_encoder_reset(struct
> drm_encoder *encoder)
> !intel_dp_is_edp(intel_dp))
> return;
>
> - with_pps_lock(intel_dp, wakeref) {
> + with_intel_pps_lock(intel_dp, wakeref) {
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> intel_dp->active_pipe = vlv_active_pipe(intel_dp);
>
> @@ -6628,7 +6628,7 @@ static bool intel_edp_init_connector(struct
> intel_dp *intel_dp,
> return false;
> }
>
> - with_pps_lock(intel_dp, wakeref) {
> + with_intel_pps_lock(intel_dp, wakeref) {
> intel_dp_init_panel_power_timestamps(intel_dp);
> intel_dp_pps_init(intel_dp);
> intel_edp_panel_vdd_sanitize(intel_dp);
> @@ -6705,7 +6705,7 @@ static bool intel_edp_init_connector(struct
> intel_dp *intel_dp,
> * vdd might still be enabled do to the delayed vdd off.
> * Make sure vdd is actually turned off here.
> */
> - with_pps_lock(intel_dp, wakeref)
> + with_intel_pps_lock(intel_dp, wakeref)
> edp_panel_vdd_off_sync(intel_dp);
>
> return false;
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
> b/drivers/gpu/drm/i915/display/intel_pps.c
> index cfe347076031..9b0c432552b7 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -16,7 +16,7 @@ static void
> intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
> bool force_disable_vdd);
>
> -intel_wakeref_t pps_lock(struct intel_dp *intel_dp)
> +intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> intel_wakeref_t wakeref;
> @@ -33,7 +33,8 @@ intel_wakeref_t pps_lock(struct intel_dp *intel_dp)
> return wakeref;
> }
>
> -intel_wakeref_t pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t
> wakeref)
> +intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp,
> + intel_wakeref_t wakeref)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> @@ -633,7 +634,7 @@ void intel_edp_panel_vdd_on(struct intel_dp
> *intel_dp)
> return;
>
> vdd = false;
> - with_pps_lock(intel_dp, wakeref)
> + with_intel_pps_lock(intel_dp, wakeref)
> vdd = edp_panel_vdd_on(intel_dp);
> I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already
> requested on\n",
> dp_to_dig_port(intel_dp)->base.base.base.id,
> @@ -688,7 +689,7 @@ void edp_panel_vdd_work(struct work_struct
> *__work)
> struct intel_dp, panel_vdd_work);
> intel_wakeref_t wakeref;
>
> - with_pps_lock(intel_dp, wakeref) {
> + with_intel_pps_lock(intel_dp, wakeref) {
> if (!intel_dp->want_panel_vdd)
> edp_panel_vdd_off_sync(intel_dp);
> }
> @@ -789,7 +790,7 @@ void intel_edp_panel_on(struct intel_dp *intel_dp)
> if (!intel_dp_is_edp(intel_dp))
> return;
>
> - with_pps_lock(intel_dp, wakeref)
> + with_intel_pps_lock(intel_dp, wakeref)
> edp_panel_on(intel_dp);
> }
>
> @@ -841,7 +842,7 @@ void intel_edp_panel_off(struct intel_dp *intel_dp)
> if (!intel_dp_is_edp(intel_dp))
> return;
>
> - with_pps_lock(intel_dp, wakeref)
> + with_intel_pps_lock(intel_dp, wakeref)
> edp_panel_off(intel_dp);
> }
>
> @@ -859,7 +860,7 @@ void _intel_edp_backlight_on(struct intel_dp
> *intel_dp)
> */
> wait_backlight_on(intel_dp);
>
> - with_pps_lock(intel_dp, wakeref) {
> + with_intel_pps_lock(intel_dp, wakeref) {
> i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
> u32 pp;
>
> @@ -880,7 +881,7 @@ void _intel_edp_backlight_off(struct intel_dp
> *intel_dp)
> if (!intel_dp_is_edp(intel_dp))
> return;
>
> - with_pps_lock(intel_dp, wakeref) {
> + with_intel_pps_lock(intel_dp, wakeref) {
> i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
> u32 pp;
>
> @@ -907,7 +908,7 @@ void intel_edp_backlight_power(struct
> intel_connector *connector, bool enable)
> bool is_enabled;
>
> is_enabled = false;
> - with_pps_lock(intel_dp, wakeref)
> + with_intel_pps_lock(intel_dp, wakeref)
> is_enabled = ilk_get_pp_control(intel_dp) &
> EDP_BLC_ENABLE;
> if (is_enabled == enable)
> return;
> @@ -1057,7 +1058,7 @@ bool intel_edp_have_power(struct intel_dp
> *intel_dp)
> intel_wakeref_t wakeref;
> bool have_power = false;
>
> - with_pps_lock(intel_dp, wakeref) {
> + with_intel_pps_lock(intel_dp, wakeref) {
> have_power = edp_have_panel_power(intel_dp) &&
>
> edp_have_panel_vdd(intel_dp);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.h
> b/drivers/gpu/drm/i915/display/intel_pps.h
> index 76d5cc565501..f44e6ce9e8c1 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.h
> +++ b/drivers/gpu/drm/i915/display/intel_pps.h
> @@ -16,11 +16,11 @@ struct intel_crtc_state; struct intel_dp; struct
> intel_encoder;
>
> -intel_wakeref_t pps_lock(struct intel_dp *intel_dp); -intel_wakeref_t
> pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref);
> +intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp);
> +intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp,
> +intel_wakeref_t wakeref);
>
> -#define with_pps_lock(dp, wf)
> \
> - for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
> +#define with_intel_pps_lock(dp, wf)
> \
> + for ((wf) = intel_pps_lock(dp); (wf); (wf) = intel_pps_unlock((dp),
> +(wf)))
>
> void intel_dp_check_edp(struct intel_dp *intel_dp); void
> _intel_edp_backlight_on(struct intel_dp *intel_dp);
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-gfx] [PATCH 01/13] drm/i915/pps: abstract panel power sequencer from intel_dp.c
2020-12-22 14:49 ` [Intel-gfx] [PATCH 01/13] drm/i915/pps: abstract panel power sequencer from intel_dp.c Jani Nikula
@ 2020-12-28 11:22 ` Gupta, Anshuman
2021-01-04 14:46 ` Jani Nikula
0 siblings, 1 reply; 35+ messages in thread
From: Gupta, Anshuman @ 2020-12-28 11:22 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Nikula, Jani
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Tuesday, December 22, 2020 8:20 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>
> Subject: [Intel-gfx] [PATCH 01/13] drm/i915/pps: abstract panel power
> sequencer from intel_dp.c
>
> In a long overdue refactoring, split out all panel sequencer code from
> intel_dp.c to new intel_pps.[ch].
>
> The first part is mostly just code movement as-is, without cleanups.
>
> We need to add a vlv_get_dpll() helper to get at the vlv/chv dpll from
> pps code.
IMHO functions intel_dp_init_panel_power_sequencer, intel_dp_init_panel_power_sequencer_registers,
intel_dp_pps_init suits a intel_edp_* prefix.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
> .../drm/i915/display/intel_display_power.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 1442 +----------------
> drivers/gpu/drm/i915/display/intel_dp.h | 5 +-
> drivers/gpu/drm/i915/display/intel_pps.c | 1337 +++++++++++++++
> drivers/gpu/drm/i915/display/intel_pps.h | 53 +
> 7 files changed, 1447 insertions(+), 1394 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_pps.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_pps.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile
> b/drivers/gpu/drm/i915/Makefile
> index 3a439b1d0496..1e26902a86e5 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -250,6 +250,7 @@ i915-y += \
> display/intel_lspcon.o \
> display/intel_lvds.o \
> display/intel_panel.o \
> + display/intel_pps.o \
> display/intel_sdvo.o \
> display/intel_tv.o \
> display/intel_vdsc.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 6863236df1d0..9ddbe8b8730b 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -46,6 +46,7 @@
> #include "intel_hotplug.h"
> #include "intel_lspcon.h"
> #include "intel_panel.h"
> +#include "intel_pps.h"
> #include "intel_psr.h"
> #include "intel_sprite.h"
> #include "intel_tc.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index d52374f01316..a11bd8213df4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -4,7 +4,6 @@
> */
>
> #include "display/intel_crt.h"
> -#include "display/intel_dp.h"
>
> #include "i915_drv.h"
> #include "i915_irq.h"
> @@ -16,6 +15,7 @@
> #include "intel_dpio_phy.h"
> #include "intel_hotplug.h"
> #include "intel_pm.h"
> +#include "intel_pps.h"
> #include "intel_sideband.h"
> #include "intel_tc.h"
> #include "intel_vga.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index b2bc0c8c39c7..d4760c478653 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -58,6 +58,7 @@
> #include "intel_lspcon.h"
> #include "intel_lvds.h"
> #include "intel_panel.h"
> +#include "intel_pps.h"
> #include "intel_psr.h"
> #include "intel_sideband.h"
> #include "intel_tc.h"
> @@ -121,6 +122,11 @@ static const struct dp_link_dpll chv_dpll[] = {
> { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
> };
>
> +const struct dpll *vlv_get_dpll(struct drm_i915_private *i915)
> +{
> + return IS_CHERRYVIEW(i915) ? &chv_dpll[0].dpll : &vlv_dpll[0].dpll;
> +}
> +
> /* Constants for DP DSC configurations */
> static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
>
> @@ -145,12 +151,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
>
> static void intel_dp_link_down(struct intel_encoder *encoder,
> const struct intel_crtc_state *old_crtc_state);
> -static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
> -static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
> -static void vlv_init_panel_power_sequencer(struct intel_encoder
> *encoder,
> - const struct intel_crtc_state
> *crtc_state);
> -static void vlv_steal_power_sequencer(struct drm_i915_private
> *dev_priv,
> - enum pipe pipe);
> static void intel_dp_unset_edid(struct intel_dp *intel_dp);
>
> /* update sink rates from dpcd */
> @@ -854,451 +854,6 @@ static void intel_dp_unpack_aux(u32 src, u8
> *dst, int dst_bytes)
> dst[i] = src >> ((3-i) * 8);
> }
>
> -static void
> -intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
> -static void
> -intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
> - bool force_disable_vdd);
> -static void
> -intel_dp_pps_init(struct intel_dp *intel_dp);
> -
> -static intel_wakeref_t
> -pps_lock(struct intel_dp *intel_dp)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - intel_wakeref_t wakeref;
> -
> - /*
> - * See intel_power_sequencer_reset() why we need
> - * a power domain reference here.
> - */
> - wakeref = intel_display_power_get(dev_priv,
> -
> intel_aux_power_domain(dp_to_dig_port(intel_dp)));
> -
> - mutex_lock(&dev_priv->pps_mutex);
> -
> - return wakeref;
> -}
> -
> -static intel_wakeref_t
> -pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> -
> - mutex_unlock(&dev_priv->pps_mutex);
> - intel_display_power_put(dev_priv,
> -
> intel_aux_power_domain(dp_to_dig_port(intel_dp)),
> - wakeref);
> - return 0;
> -}
> -
> -#define with_pps_lock(dp, wf) \
> - for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
> -
> -static void
> -vlv_power_sequencer_kick(struct intel_dp *intel_dp)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - enum pipe pipe = intel_dp->pps_pipe;
> - bool pll_enabled, release_cl_override = false;
> - enum dpio_phy phy = DPIO_PHY(pipe);
> - enum dpio_channel ch = vlv_pipe_to_channel(pipe);
> - u32 DP;
> -
> - if (drm_WARN(&dev_priv->drm,
> - intel_de_read(dev_priv, intel_dp->output_reg) &
> DP_PORT_EN,
> - "skipping pipe %c power sequencer kick due to
> [ENCODER:%d:%s] being active\n",
> - pipe_name(pipe), dig_port->base.base.base.id,
> - dig_port->base.base.name))
> - return;
> -
> - drm_dbg_kms(&dev_priv->drm,
> - "kicking pipe %c power sequencer for
> [ENCODER:%d:%s]\n",
> - pipe_name(pipe), dig_port->base.base.base.id,
> - dig_port->base.base.name);
> -
> - /* Preserve the BIOS-computed detected bit. This is
> - * supposed to be read-only.
> - */
> - DP = intel_de_read(dev_priv, intel_dp->output_reg) &
> DP_DETECTED;
> - DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
> - DP |= DP_PORT_WIDTH(1);
> - DP |= DP_LINK_TRAIN_PAT_1;
> -
> - if (IS_CHERRYVIEW(dev_priv))
> - DP |= DP_PIPE_SEL_CHV(pipe);
> - else
> - DP |= DP_PIPE_SEL(pipe);
> -
> - pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) &
> DPLL_VCO_ENABLE;
> -
> - /*
> - * The DPLL for the pipe must be enabled for this to work.
> - * So enable temporarily it if it's not already enabled.
> - */
> - if (!pll_enabled) {
> - release_cl_override = IS_CHERRYVIEW(dev_priv) &&
> - !chv_phy_powergate_ch(dev_priv, phy, ch, true);
> -
> - if (vlv_force_pll_on(dev_priv, pipe,
> IS_CHERRYVIEW(dev_priv) ?
> - &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
> - drm_err(&dev_priv->drm,
> - "Failed to force on pll for pipe %c!\n",
> - pipe_name(pipe));
> - return;
> - }
> - }
> -
> - /*
> - * Similar magic as in intel_dp_enable_port().
> - * We _must_ do this port enable + disable trick
> - * to make this power sequencer lock onto the port.
> - * Otherwise even VDD force bit won't work.
> - */
> - intel_de_write(dev_priv, intel_dp->output_reg, DP);
> - intel_de_posting_read(dev_priv, intel_dp->output_reg);
> -
> - intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN);
> - intel_de_posting_read(dev_priv, intel_dp->output_reg);
> -
> - intel_de_write(dev_priv, intel_dp->output_reg, DP &
> ~DP_PORT_EN);
> - intel_de_posting_read(dev_priv, intel_dp->output_reg);
> -
> - if (!pll_enabled) {
> - vlv_force_pll_off(dev_priv, pipe);
> -
> - if (release_cl_override)
> - chv_phy_powergate_ch(dev_priv, phy, ch, false);
> - }
> -}
> -
> -static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
> -{
> - struct intel_encoder *encoder;
> - unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
> -
> - /*
> - * We don't have power sequencer currently.
> - * Pick one that's not used by other ports.
> - */
> - for_each_intel_dp(&dev_priv->drm, encoder) {
> - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> -
> - if (encoder->type == INTEL_OUTPUT_EDP) {
> - drm_WARN_ON(&dev_priv->drm,
> - intel_dp->active_pipe != INVALID_PIPE
> &&
> - intel_dp->active_pipe !=
> - intel_dp->pps_pipe);
> -
> - if (intel_dp->pps_pipe != INVALID_PIPE)
> - pipes &= ~(1 << intel_dp->pps_pipe);
> - } else {
> - drm_WARN_ON(&dev_priv->drm,
> - intel_dp->pps_pipe != INVALID_PIPE);
> -
> - if (intel_dp->active_pipe != INVALID_PIPE)
> - pipes &= ~(1 << intel_dp->active_pipe);
> - }
> - }
> -
> - if (pipes == 0)
> - return INVALID_PIPE;
> -
> - return ffs(pipes) - 1;
> -}
> -
> -static enum pipe
> -vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - enum pipe pipe;
> -
> - lockdep_assert_held(&dev_priv->pps_mutex);
> -
> - /* We should never land here with regular DP ports */
> - drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
> -
> - drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe !=
> INVALID_PIPE &&
> - intel_dp->active_pipe != intel_dp->pps_pipe);
> -
> - if (intel_dp->pps_pipe != INVALID_PIPE)
> - return intel_dp->pps_pipe;
> -
> - pipe = vlv_find_free_pps(dev_priv);
> -
> - /*
> - * Didn't find one. This should not happen since there
> - * are two power sequencers and up to two eDP ports.
> - */
> - if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE))
> - pipe = PIPE_A;
> -
> - vlv_steal_power_sequencer(dev_priv, pipe);
> - intel_dp->pps_pipe = pipe;
> -
> - drm_dbg_kms(&dev_priv->drm,
> - "picked pipe %c power sequencer for
> [ENCODER:%d:%s]\n",
> - pipe_name(intel_dp->pps_pipe),
> - dig_port->base.base.base.id,
> - dig_port->base.base.name);
> -
> - /* init power sequencer on this pipe and port */
> - intel_dp_init_panel_power_sequencer(intel_dp);
> - intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
> -
> - /*
> - * Even vdd force doesn't work until we've made
> - * the power sequencer lock in on the port.
> - */
> - vlv_power_sequencer_kick(intel_dp);
> -
> - return intel_dp->pps_pipe;
> -}
> -
> -static int
> -bxt_power_sequencer_idx(struct intel_dp *intel_dp)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - int backlight_controller = dev_priv->vbt.backlight.controller;
> -
> - lockdep_assert_held(&dev_priv->pps_mutex);
> -
> - /* We should never land here with regular DP ports */
> - drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
> -
> - if (!intel_dp->pps_reset)
> - return backlight_controller;
> -
> - intel_dp->pps_reset = false;
> -
> - /*
> - * Only the HW needs to be reprogrammed, the SW state is fixed
> and
> - * has been setup during connector init.
> - */
> - intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
> -
> - return backlight_controller;
> -}
> -
> -typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
> - enum pipe pipe);
> -
> -static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
> - enum pipe pipe)
> -{
> - return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON;
> -}
> -
> -static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
> - enum pipe pipe)
> -{
> - return intel_de_read(dev_priv, PP_CONTROL(pipe)) &
> EDP_FORCE_VDD;
> -}
> -
> -static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
> - enum pipe pipe)
> -{
> - return true;
> -}
> -
> -static enum pipe
> -vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
> - enum port port,
> - vlv_pipe_check pipe_check)
> -{
> - enum pipe pipe;
> -
> - for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
> - u32 port_sel = intel_de_read(dev_priv,
> PP_ON_DELAYS(pipe)) &
> - PANEL_PORT_SELECT_MASK;
> -
> - if (port_sel != PANEL_PORT_SELECT_VLV(port))
> - continue;
> -
> - if (!pipe_check(dev_priv, pipe))
> - continue;
> -
> - return pipe;
> - }
> -
> - return INVALID_PIPE;
> -}
> -
> -static void
> -vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - enum port port = dig_port->base.port;
> -
> - lockdep_assert_held(&dev_priv->pps_mutex);
> -
> - /* try to find a pipe with this port selected */
> - /* first pick one where the panel is on */
> - intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
> - vlv_pipe_has_pp_on);
> - /* didn't find one? pick one where vdd is on */
> - if (intel_dp->pps_pipe == INVALID_PIPE)
> - intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
> -
> vlv_pipe_has_vdd_on);
> - /* didn't find one? pick one with just the correct port */
> - if (intel_dp->pps_pipe == INVALID_PIPE)
> - intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
> - vlv_pipe_any);
> -
> - /* didn't find one? just let vlv_power_sequencer_pipe() pick one
> when needed */
> - if (intel_dp->pps_pipe == INVALID_PIPE) {
> - drm_dbg_kms(&dev_priv->drm,
> - "no initial power sequencer for
> [ENCODER:%d:%s]\n",
> - dig_port->base.base.base.id,
> - dig_port->base.base.name);
> - return;
> - }
> -
> - drm_dbg_kms(&dev_priv->drm,
> - "initial power sequencer for [ENCODER:%d:%s]: pipe
> %c\n",
> - dig_port->base.base.base.id,
> - dig_port->base.base.name,
> - pipe_name(intel_dp->pps_pipe));
> -
> - intel_dp_init_panel_power_sequencer(intel_dp);
> - intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
> -}
> -
> -void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
> -{
> - struct intel_encoder *encoder;
> -
> - if (drm_WARN_ON(&dev_priv->drm,
> - !(IS_VALLEYVIEW(dev_priv) ||
> - IS_CHERRYVIEW(dev_priv) ||
> - IS_GEN9_LP(dev_priv))))
> - return;
> -
> - /*
> - * We can't grab pps_mutex here due to deadlock with
> power_domain
> - * mutex when power_domain functions are called while holding
> pps_mutex.
> - * That also means that in order to use pps_pipe the code needs to
> - * hold both a power domain reference and pps_mutex, and the
> power domain
> - * reference get/put must be done while _not_ holding pps_mutex.
> - * pps_{lock,unlock}() do these steps in the correct order, so one
> - * should use them always.
> - */
> -
> - for_each_intel_dp(&dev_priv->drm, encoder) {
> - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> -
> - drm_WARN_ON(&dev_priv->drm,
> - intel_dp->active_pipe != INVALID_PIPE);
> -
> - if (encoder->type != INTEL_OUTPUT_EDP)
> - continue;
> -
> - if (IS_GEN9_LP(dev_priv))
> - intel_dp->pps_reset = true;
> - else
> - intel_dp->pps_pipe = INVALID_PIPE;
> - }
> -}
> -
> -struct pps_registers {
> - i915_reg_t pp_ctrl;
> - i915_reg_t pp_stat;
> - i915_reg_t pp_on;
> - i915_reg_t pp_off;
> - i915_reg_t pp_div;
> -};
> -
> -static void intel_pps_get_registers(struct intel_dp *intel_dp,
> - struct pps_registers *regs)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - int pps_idx = 0;
> -
> - memset(regs, 0, sizeof(*regs));
> -
> - if (IS_GEN9_LP(dev_priv))
> - pps_idx = bxt_power_sequencer_idx(intel_dp);
> - else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> - pps_idx = vlv_power_sequencer_pipe(intel_dp);
> -
> - regs->pp_ctrl = PP_CONTROL(pps_idx);
> - regs->pp_stat = PP_STATUS(pps_idx);
> - regs->pp_on = PP_ON_DELAYS(pps_idx);
> - regs->pp_off = PP_OFF_DELAYS(pps_idx);
> -
> - /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
> - if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >=
> PCH_CNP)
> - regs->pp_div = INVALID_MMIO_REG;
> - else
> - regs->pp_div = PP_DIVISOR(pps_idx);
> -}
> -
> -static i915_reg_t
> -_pp_ctrl_reg(struct intel_dp *intel_dp)
> -{
> - struct pps_registers regs;
> -
> - intel_pps_get_registers(intel_dp, ®s);
> -
> - return regs.pp_ctrl;
> -}
> -
> -static i915_reg_t
> -_pp_stat_reg(struct intel_dp *intel_dp)
> -{
> - struct pps_registers regs;
> -
> - intel_pps_get_registers(intel_dp, ®s);
> -
> - return regs.pp_stat;
> -}
> -
> -static bool edp_have_panel_power(struct intel_dp *intel_dp)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> -
> - lockdep_assert_held(&dev_priv->pps_mutex);
> -
> - if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> - intel_dp->pps_pipe == INVALID_PIPE)
> - return false;
> -
> - return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON)
> != 0;
> -}
> -
> -static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> -
> - lockdep_assert_held(&dev_priv->pps_mutex);
> -
> - if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> - intel_dp->pps_pipe == INVALID_PIPE)
> - return false;
> -
> - return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) &
> EDP_FORCE_VDD;
> -}
> -
> -static void
> -intel_dp_check_edp(struct intel_dp *intel_dp)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> -
> - if (!intel_dp_is_edp(intel_dp))
> - return;
> -
> - if (!edp_have_panel_power(intel_dp) &&
> !edp_have_panel_vdd(intel_dp)) {
> - drm_WARN(&dev_priv->drm, 1,
> - "eDP powered off while attempting aux channel
> communication.\n");
> - drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control
> 0x%08x\n",
> - intel_de_read(dev_priv, _pp_stat_reg(intel_dp)),
> - intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)));
> - }
> -}
> -
> static u32
> intel_dp_aux_wait_done(struct intel_dp *intel_dp)
> {
> @@ -2907,492 +2462,67 @@ static void intel_dp_prepare(struct
> intel_encoder *encoder,
> *
> * IBX PCH and CPU are the same for almost everything,
> * except that the CPU DP PLL is configured in this
> - * register
> - *
> - * CPT PCH is quite different, having many bits moved
> - * to the TRANS_DP_CTL register instead. That
> - * configuration happens (oddly) in ilk_pch_enable
> - */
> -
> - /* Preserve the BIOS-computed detected bit. This is
> - * supposed to be read-only.
> - */
> - intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) &
> DP_DETECTED;
> -
> - /* Handle DP bits in common between all three register formats */
> - intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
> - intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
> -
> - /* Split out the IBX/CPU vs CPT settings */
> -
> - if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
> - if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
> - intel_dp->DP |= DP_SYNC_HS_HIGH;
> - if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
> - intel_dp->DP |= DP_SYNC_VS_HIGH;
> - intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
> -
> - if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> - intel_dp->DP |= DP_ENHANCED_FRAMING;
> -
> - intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
> - } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
> - u32 trans_dp;
> -
> - intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
> -
> - trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc-
> >pipe));
> - if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> - trans_dp |= TRANS_DP_ENH_FRAMING;
> - else
> - trans_dp &= ~TRANS_DP_ENH_FRAMING;
> - intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe),
> trans_dp);
> - } else {
> - if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
> - intel_dp->DP |= DP_COLOR_RANGE_16_235;
> -
> - if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
> - intel_dp->DP |= DP_SYNC_HS_HIGH;
> - if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
> - intel_dp->DP |= DP_SYNC_VS_HIGH;
> - intel_dp->DP |= DP_LINK_TRAIN_OFF;
> -
> - if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> - intel_dp->DP |= DP_ENHANCED_FRAMING;
> -
> - if (IS_CHERRYVIEW(dev_priv))
> - intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
> - else
> - intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
> - }
> -}
> -
> -#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0
> | PP_SEQUENCE_STATE_MASK)
> -#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0
> | PP_SEQUENCE_STATE_ON_IDLE)
> -
> -#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0
> | 0)
> -#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0
> | 0)
> -
> -#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK |
> PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
> -#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0
> | PP_SEQUENCE_STATE_OFF_IDLE)
> -
> -static void intel_pps_verify_state(struct intel_dp *intel_dp);
> -
> -static void wait_panel_status(struct intel_dp *intel_dp,
> - u32 mask,
> - u32 value)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - i915_reg_t pp_stat_reg, pp_ctrl_reg;
> -
> - lockdep_assert_held(&dev_priv->pps_mutex);
> -
> - intel_pps_verify_state(intel_dp);
> -
> - pp_stat_reg = _pp_stat_reg(intel_dp);
> - pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
> -
> - drm_dbg_kms(&dev_priv->drm,
> - "mask %08x value %08x status %08x control %08x\n",
> - mask, value,
> - intel_de_read(dev_priv, pp_stat_reg),
> - intel_de_read(dev_priv, pp_ctrl_reg));
> -
> - if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
> - mask, value, 5000))
> - drm_err(&dev_priv->drm,
> - "Panel status timeout: status %08x control %08x\n",
> - intel_de_read(dev_priv, pp_stat_reg),
> - intel_de_read(dev_priv, pp_ctrl_reg));
> -
> - drm_dbg_kms(&dev_priv->drm, "Wait complete\n");
> -}
> -
> -static void wait_panel_on(struct intel_dp *intel_dp)
> -{
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> -
> - drm_dbg_kms(&i915->drm, "Wait for panel power on\n");
> - wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
> -}
> -
> -static void wait_panel_off(struct intel_dp *intel_dp)
> -{
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> -
> - drm_dbg_kms(&i915->drm, "Wait for panel power off time\n");
> - wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
> -}
> -
> -static void wait_panel_power_cycle(struct intel_dp *intel_dp)
> -{
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> - ktime_t panel_power_on_time;
> - s64 panel_power_off_duration;
> -
> - drm_dbg_kms(&i915->drm, "Wait for panel power cycle\n");
> -
> - /* take the difference of currrent time and panel power off time
> - * and then make panel wait for t11_t12 if needed. */
> - panel_power_on_time = ktime_get_boottime();
> - panel_power_off_duration =
> ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
> -
> - /* When we disable the VDD override bit last we have to do the
> manual
> - * wait. */
> - if (panel_power_off_duration < (s64)intel_dp-
> >panel_power_cycle_delay)
> - wait_remaining_ms_from_jiffies(jiffies,
> - intel_dp->panel_power_cycle_delay -
> panel_power_off_duration);
> -
> - wait_panel_status(intel_dp, IDLE_CYCLE_MASK,
> IDLE_CYCLE_VALUE);
> -}
> -
> -static void wait_backlight_on(struct intel_dp *intel_dp)
> -{
> - wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
> - intel_dp->backlight_on_delay);
> -}
> -
> -static void edp_wait_backlight_off(struct intel_dp *intel_dp)
> -{
> - wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
> - intel_dp->backlight_off_delay);
> -}
> -
> -/* Read the current pp_control value, unlocking the register if it
> - * is locked
> - */
> -
> -static u32 ilk_get_pp_control(struct intel_dp *intel_dp)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - u32 control;
> -
> - lockdep_assert_held(&dev_priv->pps_mutex);
> -
> - control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
> - if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) &&
> - (control & PANEL_UNLOCK_MASK) !=
> PANEL_UNLOCK_REGS)) {
> - control &= ~PANEL_UNLOCK_MASK;
> - control |= PANEL_UNLOCK_REGS;
> - }
> - return control;
> -}
> -
> -/*
> - * Must be paired with edp_panel_vdd_off().
> - * Must hold pps_mutex around the whole on/off sequence.
> - * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
> - */
> -static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - u32 pp;
> - i915_reg_t pp_stat_reg, pp_ctrl_reg;
> - bool need_to_disable = !intel_dp->want_panel_vdd;
> -
> - lockdep_assert_held(&dev_priv->pps_mutex);
> -
> - if (!intel_dp_is_edp(intel_dp))
> - return false;
> -
> - cancel_delayed_work(&intel_dp->panel_vdd_work);
> - intel_dp->want_panel_vdd = true;
> -
> - if (edp_have_panel_vdd(intel_dp))
> - return need_to_disable;
> -
> - drm_WARN_ON(&dev_priv->drm, intel_dp->vdd_wakeref);
> - intel_dp->vdd_wakeref = intel_display_power_get(dev_priv,
> -
> intel_aux_power_domain(dig_port));
> -
> - drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD
> on\n",
> - dig_port->base.base.base.id,
> - dig_port->base.base.name);
> -
> - if (!edp_have_panel_power(intel_dp))
> - wait_panel_power_cycle(intel_dp);
> -
> - pp = ilk_get_pp_control(intel_dp);
> - pp |= EDP_FORCE_VDD;
> -
> - pp_stat_reg = _pp_stat_reg(intel_dp);
> - pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
> -
> - intel_de_write(dev_priv, pp_ctrl_reg, pp);
> - intel_de_posting_read(dev_priv, pp_ctrl_reg);
> - drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x
> PP_CONTROL: 0x%08x\n",
> - intel_de_read(dev_priv, pp_stat_reg),
> - intel_de_read(dev_priv, pp_ctrl_reg));
> - /*
> - * If the panel wasn't on, delay before accessing aux channel
> - */
> - if (!edp_have_panel_power(intel_dp)) {
> - drm_dbg_kms(&dev_priv->drm,
> - "[ENCODER:%d:%s] panel power wasn't
> enabled\n",
> - dig_port->base.base.base.id,
> - dig_port->base.base.name);
> - msleep(intel_dp->panel_power_up_delay);
> - }
> -
> - return need_to_disable;
> -}
> -
> -/*
> - * Must be paired with intel_edp_panel_vdd_off() or
> - * intel_edp_panel_off().
> - * Nested calls to these functions are not allowed since
> - * we drop the lock. Caller must use some higher level
> - * locking to prevent nested calls from other threads.
> - */
> -void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
> -{
> - intel_wakeref_t wakeref;
> - bool vdd;
> -
> - if (!intel_dp_is_edp(intel_dp))
> - return;
> -
> - vdd = false;
> - with_pps_lock(intel_dp, wakeref)
> - vdd = edp_panel_vdd_on(intel_dp);
> - I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already
> requested on\n",
> - dp_to_dig_port(intel_dp)->base.base.base.id,
> - dp_to_dig_port(intel_dp)->base.base.name);
> -}
> -
> -static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - struct intel_digital_port *dig_port =
> - dp_to_dig_port(intel_dp);
> - u32 pp;
> - i915_reg_t pp_stat_reg, pp_ctrl_reg;
> -
> - lockdep_assert_held(&dev_priv->pps_mutex);
> -
> - drm_WARN_ON(&dev_priv->drm, intel_dp->want_panel_vdd);
> -
> - if (!edp_have_panel_vdd(intel_dp))
> - return;
> -
> - drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD
> off\n",
> - dig_port->base.base.base.id,
> - dig_port->base.base.name);
> -
> - pp = ilk_get_pp_control(intel_dp);
> - pp &= ~EDP_FORCE_VDD;
> -
> - pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
> - pp_stat_reg = _pp_stat_reg(intel_dp);
> -
> - intel_de_write(dev_priv, pp_ctrl_reg, pp);
> - intel_de_posting_read(dev_priv, pp_ctrl_reg);
> -
> - /* Make sure sequencer is idle before allowing subsequent activity
> */
> - drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x
> PP_CONTROL: 0x%08x\n",
> - intel_de_read(dev_priv, pp_stat_reg),
> - intel_de_read(dev_priv, pp_ctrl_reg));
> -
> - if ((pp & PANEL_POWER_ON) == 0)
> - intel_dp->panel_power_off_time = ktime_get_boottime();
> -
> - intel_display_power_put(dev_priv,
> - intel_aux_power_domain(dig_port),
> - fetch_and_zero(&intel_dp->vdd_wakeref));
> -}
> -
> -static void edp_panel_vdd_work(struct work_struct *__work)
> -{
> - struct intel_dp *intel_dp =
> - container_of(to_delayed_work(__work),
> - struct intel_dp, panel_vdd_work);
> - intel_wakeref_t wakeref;
> -
> - with_pps_lock(intel_dp, wakeref) {
> - if (!intel_dp->want_panel_vdd)
> - edp_panel_vdd_off_sync(intel_dp);
> - }
> -}
> -
> -static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
> -{
> - unsigned long delay;
> -
> - /*
> - * Queue the timer to fire a long time from now (relative to the
> power
> - * down delay) to keep the panel power up across a sequence of
> - * operations.
> - */
> - delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
> - schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
> -}
> -
> -/*
> - * Must be paired with edp_panel_vdd_on().
> - * Must hold pps_mutex around the whole on/off sequence.
> - * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
> - */
> -static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> -
> - lockdep_assert_held(&dev_priv->pps_mutex);
> -
> - if (!intel_dp_is_edp(intel_dp))
> - return;
> -
> - I915_STATE_WARN(!intel_dp->want_panel_vdd,
> "[ENCODER:%d:%s] VDD not forced on",
> - dp_to_dig_port(intel_dp)->base.base.base.id,
> - dp_to_dig_port(intel_dp)->base.base.name);
> -
> - intel_dp->want_panel_vdd = false;
> -
> - if (sync)
> - edp_panel_vdd_off_sync(intel_dp);
> - else
> - edp_panel_vdd_schedule_off(intel_dp);
> -}
> -
> -static void edp_panel_on(struct intel_dp *intel_dp)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - u32 pp;
> - i915_reg_t pp_ctrl_reg;
> -
> - lockdep_assert_held(&dev_priv->pps_mutex);
> -
> - if (!intel_dp_is_edp(intel_dp))
> - return;
> -
> - drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel
> power on\n",
> - dp_to_dig_port(intel_dp)->base.base.base.id,
> - dp_to_dig_port(intel_dp)->base.base.name);
> -
> - if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp),
> - "[ENCODER:%d:%s] panel power already on\n",
> - dp_to_dig_port(intel_dp)->base.base.base.id,
> - dp_to_dig_port(intel_dp)->base.base.name))
> - return;
> -
> - wait_panel_power_cycle(intel_dp);
> -
> - pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
> - pp = ilk_get_pp_control(intel_dp);
> - if (IS_GEN(dev_priv, 5)) {
> - /* ILK workaround: disable reset around power sequence */
> - pp &= ~PANEL_POWER_RESET;
> - intel_de_write(dev_priv, pp_ctrl_reg, pp);
> - intel_de_posting_read(dev_priv, pp_ctrl_reg);
> - }
> -
> - pp |= PANEL_POWER_ON;
> - if (!IS_GEN(dev_priv, 5))
> - pp |= PANEL_POWER_RESET;
> -
> - intel_de_write(dev_priv, pp_ctrl_reg, pp);
> - intel_de_posting_read(dev_priv, pp_ctrl_reg);
> -
> - wait_panel_on(intel_dp);
> - intel_dp->last_power_on = jiffies;
> -
> - if (IS_GEN(dev_priv, 5)) {
> - pp |= PANEL_POWER_RESET; /* restore panel reset bit */
> - intel_de_write(dev_priv, pp_ctrl_reg, pp);
> - intel_de_posting_read(dev_priv, pp_ctrl_reg);
> - }
> -}
> -
> -void intel_edp_panel_on(struct intel_dp *intel_dp)
> -{
> - intel_wakeref_t wakeref;
> -
> - if (!intel_dp_is_edp(intel_dp))
> - return;
> -
> - with_pps_lock(intel_dp, wakeref)
> - edp_panel_on(intel_dp);
> -}
> -
> -
> -static void edp_panel_off(struct intel_dp *intel_dp)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - u32 pp;
> - i915_reg_t pp_ctrl_reg;
> -
> - lockdep_assert_held(&dev_priv->pps_mutex);
> -
> - if (!intel_dp_is_edp(intel_dp))
> - return;
> -
> - drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel
> power off\n",
> - dig_port->base.base.base.id, dig_port->base.base.name);
> -
> - drm_WARN(&dev_priv->drm, !intel_dp->want_panel_vdd,
> - "Need [ENCODER:%d:%s] VDD to turn off panel\n",
> - dig_port->base.base.base.id, dig_port->base.base.name);
> -
> - pp = ilk_get_pp_control(intel_dp);
> - /* We need to switch off panel power _and_ force vdd, for
> otherwise some
> - * panels get very unhappy and cease to work. */
> - pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET |
> EDP_FORCE_VDD |
> - EDP_BLC_ENABLE);
> -
> - pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
> -
> - intel_dp->want_panel_vdd = false;
> + * register
> + *
> + * CPT PCH is quite different, having many bits moved
> + * to the TRANS_DP_CTL register instead. That
> + * configuration happens (oddly) in ilk_pch_enable
> + */
>
> - intel_de_write(dev_priv, pp_ctrl_reg, pp);
> - intel_de_posting_read(dev_priv, pp_ctrl_reg);
> + /* Preserve the BIOS-computed detected bit. This is
> + * supposed to be read-only.
> + */
> + intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) &
> DP_DETECTED;
>
> - wait_panel_off(intel_dp);
> - intel_dp->panel_power_off_time = ktime_get_boottime();
> + /* Handle DP bits in common between all three register formats */
> + intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
> + intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
>
> - /* We got a reference when we enabled the VDD. */
> - intel_display_power_put(dev_priv,
> - intel_aux_power_domain(dig_port),
> - fetch_and_zero(&intel_dp->vdd_wakeref));
> -}
> + /* Split out the IBX/CPU vs CPT settings */
>
> -void intel_edp_panel_off(struct intel_dp *intel_dp)
> -{
> - intel_wakeref_t wakeref;
> + if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
> + if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
> + intel_dp->DP |= DP_SYNC_HS_HIGH;
> + if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
> + intel_dp->DP |= DP_SYNC_VS_HIGH;
> + intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
>
> - if (!intel_dp_is_edp(intel_dp))
> - return;
> + if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> + intel_dp->DP |= DP_ENHANCED_FRAMING;
>
> - with_pps_lock(intel_dp, wakeref)
> - edp_panel_off(intel_dp);
> -}
> + intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
> + } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
> + u32 trans_dp;
>
> -/* Enable backlight in the panel power control. */
> -static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - intel_wakeref_t wakeref;
> + intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
>
> - /*
> - * If we enable the backlight right away following a panel power
> - * on, we may see slight flicker as the panel syncs with the eDP
> - * link. So delay a bit to make sure the image is solid before
> - * allowing it to appear.
> - */
> - wait_backlight_on(intel_dp);
> + trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc-
> >pipe));
> + if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> + trans_dp |= TRANS_DP_ENH_FRAMING;
> + else
> + trans_dp &= ~TRANS_DP_ENH_FRAMING;
> + intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe),
> trans_dp);
> + } else {
> + if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
> + intel_dp->DP |= DP_COLOR_RANGE_16_235;
>
> - with_pps_lock(intel_dp, wakeref) {
> - i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
> - u32 pp;
> + if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
> + intel_dp->DP |= DP_SYNC_HS_HIGH;
> + if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
> + intel_dp->DP |= DP_SYNC_VS_HIGH;
> + intel_dp->DP |= DP_LINK_TRAIN_OFF;
>
> - pp = ilk_get_pp_control(intel_dp);
> - pp |= EDP_BLC_ENABLE;
> + if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> + intel_dp->DP |= DP_ENHANCED_FRAMING;
>
> - intel_de_write(dev_priv, pp_ctrl_reg, pp);
> - intel_de_posting_read(dev_priv, pp_ctrl_reg);
> + if (IS_CHERRYVIEW(dev_priv))
> + intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
> + else
> + intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
> }
> }
>
> +
> /* Enable backlight PWM and backlight PP control. */
> void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state)
> @@ -3409,30 +2539,6 @@ void intel_edp_backlight_on(const struct
> intel_crtc_state *crtc_state,
> _intel_edp_backlight_on(intel_dp);
> }
>
> -/* Disable backlight in the panel power control. */
> -static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - intel_wakeref_t wakeref;
> -
> - if (!intel_dp_is_edp(intel_dp))
> - return;
> -
> - with_pps_lock(intel_dp, wakeref) {
> - i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
> - u32 pp;
> -
> - pp = ilk_get_pp_control(intel_dp);
> - pp &= ~EDP_BLC_ENABLE;
> -
> - intel_de_write(dev_priv, pp_ctrl_reg, pp);
> - intel_de_posting_read(dev_priv, pp_ctrl_reg);
> - }
> -
> - intel_dp->last_backlight_off = jiffies;
> - edp_wait_backlight_off(intel_dp);
> -}
> -
> /* Disable backlight PP control and backlight PWM. */
> void intel_edp_backlight_off(const struct drm_connector_state
> *old_conn_state)
> {
> @@ -3448,33 +2554,6 @@ void intel_edp_backlight_off(const struct
> drm_connector_state *old_conn_state)
> intel_panel_disable_backlight(old_conn_state);
> }
>
> -/*
> - * Hook for controlling the panel power control backlight through the
> bl_power
> - * sysfs attribute. Take care to handle multiple calls.
> - */
> -static void intel_edp_backlight_power(struct intel_connector *connector,
> - bool enable)
> -{
> - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> - struct intel_dp *intel_dp = intel_attached_dp(connector);
> - intel_wakeref_t wakeref;
> - bool is_enabled;
> -
> - is_enabled = false;
> - with_pps_lock(intel_dp, wakeref)
> - is_enabled = ilk_get_pp_control(intel_dp) &
> EDP_BLC_ENABLE;
> - if (is_enabled == enable)
> - return;
> -
> - drm_dbg_kms(&i915->drm, "panel power control backlight %s\n",
> - enable ? "enable" : "disable");
> -
> - if (enable)
> - _intel_edp_backlight_on(intel_dp);
> - else
> - _intel_edp_backlight_off(intel_dp);
> -}
> -
> static void assert_dp_port(struct intel_dp *intel_dp, bool state)
> {
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> @@ -4139,112 +3218,6 @@ static void g4x_pre_enable_dp(struct
> intel_atomic_state *state,
> ilk_edp_pll_on(intel_dp, pipe_config);
> }
>
> -static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
> -{
> - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - struct drm_i915_private *dev_priv = to_i915(dig_port-
> >base.base.dev);
> - enum pipe pipe = intel_dp->pps_pipe;
> - i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
> -
> - drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe !=
> INVALID_PIPE);
> -
> - if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe !=
> PIPE_B))
> - return;
> -
> - edp_panel_vdd_off_sync(intel_dp);
> -
> - /*
> - * VLV seems to get confused when multiple power sequencers
> - * have the same port selected (even if only one has power/vdd
> - * enabled). The failure manifests as vlv_wait_port_ready() failing
> - * CHV on the other hand doesn't seem to mind having the same
> port
> - * selected in multiple power sequencers, but let's clear the
> - * port select always when logically disconnecting a power
> sequencer
> - * from a port.
> - */
> - drm_dbg_kms(&dev_priv->drm,
> - "detaching pipe %c power sequencer from
> [ENCODER:%d:%s]\n",
> - pipe_name(pipe), dig_port->base.base.base.id,
> - dig_port->base.base.name);
> - intel_de_write(dev_priv, pp_on_reg, 0);
> - intel_de_posting_read(dev_priv, pp_on_reg);
> -
> - intel_dp->pps_pipe = INVALID_PIPE;
> -}
> -
> -static void vlv_steal_power_sequencer(struct drm_i915_private
> *dev_priv,
> - enum pipe pipe)
> -{
> - struct intel_encoder *encoder;
> -
> - lockdep_assert_held(&dev_priv->pps_mutex);
> -
> - for_each_intel_dp(&dev_priv->drm, encoder) {
> - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> -
> - drm_WARN(&dev_priv->drm, intel_dp->active_pipe ==
> pipe,
> - "stealing pipe %c power sequencer from active
> [ENCODER:%d:%s]\n",
> - pipe_name(pipe), encoder->base.base.id,
> - encoder->base.name);
> -
> - if (intel_dp->pps_pipe != pipe)
> - continue;
> -
> - drm_dbg_kms(&dev_priv->drm,
> - "stealing pipe %c power sequencer from
> [ENCODER:%d:%s]\n",
> - pipe_name(pipe), encoder->base.base.id,
> - encoder->base.name);
> -
> - /* make sure vdd is off before we steal it */
> - vlv_detach_power_sequencer(intel_dp);
> - }
> -}
> -
> -static void vlv_init_panel_power_sequencer(struct intel_encoder
> *encoder,
> - const struct intel_crtc_state
> *crtc_state)
> -{
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -
> - lockdep_assert_held(&dev_priv->pps_mutex);
> -
> - drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe !=
> INVALID_PIPE);
> -
> - if (intel_dp->pps_pipe != INVALID_PIPE &&
> - intel_dp->pps_pipe != crtc->pipe) {
> - /*
> - * If another power sequencer was being used on this
> - * port previously make sure to turn off vdd there while
> - * we still have control of it.
> - */
> - vlv_detach_power_sequencer(intel_dp);
> - }
> -
> - /*
> - * We may be stealing the power
> - * sequencer from another port.
> - */
> - vlv_steal_power_sequencer(dev_priv, crtc->pipe);
> -
> - intel_dp->active_pipe = crtc->pipe;
> -
> - if (!intel_dp_is_edp(intel_dp))
> - return;
> -
> - /* now it's all ours */
> - intel_dp->pps_pipe = crtc->pipe;
> -
> - drm_dbg_kms(&dev_priv->drm,
> - "initializing pipe %c power sequencer for
> [ENCODER:%d:%s]\n",
> - pipe_name(intel_dp->pps_pipe), encoder->base.base.id,
> - encoder->base.name);
> -
> - /* init power sequencer on this pipe and port */
> - intel_dp_init_panel_power_sequencer(intel_dp);
> - intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
> -}
> -
> static void vlv_pre_enable_dp(struct intel_atomic_state *state,
> struct intel_encoder *encoder,
> const struct intel_crtc_state *pipe_config,
> @@ -6888,31 +5861,6 @@ void intel_dp_encoder_shutdown(struct
> intel_encoder *intel_encoder)
> wait_panel_power_cycle(intel_dp);
> }
>
> -static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> -
> - lockdep_assert_held(&dev_priv->pps_mutex);
> -
> - if (!edp_have_panel_vdd(intel_dp))
> - return;
> -
> - /*
> - * The VDD bit needs a power domain reference, so if the bit is
> - * already enabled when we boot or resume, grab this reference and
> - * schedule a vdd off, so we don't hold on to the reference
> - * indefinitely.
> - */
> - drm_dbg_kms(&dev_priv->drm,
> - "VDD left on by BIOS, adjusting state tracking\n");
> - drm_WARN_ON(&dev_priv->drm, intel_dp->vdd_wakeref);
> - intel_dp->vdd_wakeref = intel_display_power_get(dev_priv,
> -
> intel_aux_power_domain(dig_port));
> -
> - edp_panel_vdd_schedule_off(intel_dp);
> -}
> -
> static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> @@ -7118,19 +6066,6 @@ static const struct drm_encoder_funcs
> intel_dp_enc_funcs = {
> .destroy = intel_dp_encoder_destroy,
> };
>
> -static bool intel_edp_have_power(struct intel_dp *intel_dp)
> -{
> - intel_wakeref_t wakeref;
> - bool have_power = false;
> -
> - with_pps_lock(intel_dp, wakeref) {
> - have_power = edp_have_panel_power(intel_dp) &&
> -
> edp_have_panel_vdd(intel_dp);
> - }
> -
> - return have_power;
> -}
> -
> enum irqreturn
> intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
> {
> @@ -7234,277 +6169,6 @@ intel_dp_add_properties(struct intel_dp
> *intel_dp, struct drm_connector *connect
> }
> }
>
> -static void intel_dp_init_panel_power_timestamps(struct intel_dp
> *intel_dp)
> -{
> - intel_dp->panel_power_off_time = ktime_get_boottime();
> - intel_dp->last_power_on = jiffies;
> - intel_dp->last_backlight_off = jiffies;
> -}
> -
> -static void
> -intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct
> edp_power_seq *seq)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - u32 pp_on, pp_off, pp_ctl;
> - struct pps_registers regs;
> -
> - intel_pps_get_registers(intel_dp, ®s);
> -
> - pp_ctl = ilk_get_pp_control(intel_dp);
> -
> - /* Ensure PPS is unlocked */
> - if (!HAS_DDI(dev_priv))
> - intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
> -
> - pp_on = intel_de_read(dev_priv, regs.pp_on);
> - pp_off = intel_de_read(dev_priv, regs.pp_off);
> -
> - /* Pull timing values out of registers */
> - seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK,
> pp_on);
> - seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK,
> pp_on);
> - seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK,
> pp_off);
> - seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK,
> pp_off);
> -
> - if (i915_mmio_reg_valid(regs.pp_div)) {
> - u32 pp_div;
> -
> - pp_div = intel_de_read(dev_priv, regs.pp_div);
> -
> - seq->t11_t12 =
> REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
> - } else {
> - seq->t11_t12 =
> REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
> - }
> -}
> -
> -static void
> -intel_pps_dump_state(const char *state_name, const struct
> edp_power_seq *seq)
> -{
> - DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12
> %d\n",
> - state_name,
> - seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
> -}
> -
> -static void
> -intel_pps_verify_state(struct intel_dp *intel_dp)
> -{
> - struct edp_power_seq hw;
> - struct edp_power_seq *sw = &intel_dp->pps_delays;
> -
> - intel_pps_readout_hw_state(intel_dp, &hw);
> -
> - if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
> - hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
> - DRM_ERROR("PPS state mismatch\n");
> - intel_pps_dump_state("sw", sw);
> - intel_pps_dump_state("hw", &hw);
> - }
> -}
> -
> -static void
> -intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - struct edp_power_seq cur, vbt, spec,
> - *final = &intel_dp->pps_delays;
> -
> - lockdep_assert_held(&dev_priv->pps_mutex);
> -
> - /* already initialized? */
> - if (final->t11_t12 != 0)
> - return;
> -
> - intel_pps_readout_hw_state(intel_dp, &cur);
> -
> - intel_pps_dump_state("cur", &cur);
> -
> - vbt = dev_priv->vbt.edp.pps;
> - /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
> - * of 500ms appears to be too short. Ocassionally the panel
> - * just fails to power back on. Increasing the delay to 800ms
> - * seems sufficient to avoid this problem.
> - */
> - if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
> - vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
> - drm_dbg_kms(&dev_priv->drm,
> - "Increasing T12 panel delay as per the quirk to
> %d\n",
> - vbt.t11_t12);
> - }
> - /* T11_T12 delay is special and actually in units of 100ms, but zero
> - * based in the hw (so we need to add 100 ms). But the sw vbt
> - * table multiplies it with 1000 to make it in units of 100usec,
> - * too. */
> - vbt.t11_t12 += 100 * 10;
> -
> - /* Upper limits from eDP 1.3 spec. Note that we use the clunky
> units of
> - * our hw here, which are all in 100usec. */
> - spec.t1_t3 = 210 * 10;
> - spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
> - spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
> - spec.t10 = 500 * 10;
> - /* This one is special and actually in units of 100ms, but zero
> - * based in the hw (so we need to add 100 ms). But the sw vbt
> - * table multiplies it with 1000 to make it in units of 100usec,
> - * too. */
> - spec.t11_t12 = (510 + 100) * 10;
> -
> - intel_pps_dump_state("vbt", &vbt);
> -
> - /* Use the max of the register settings and vbt. If both are
> - * unset, fall back to the spec limits. */
> -#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ?
> \
> - spec.field : \
> - max(cur.field, vbt.field))
> - assign_final(t1_t3);
> - assign_final(t8);
> - assign_final(t9);
> - assign_final(t10);
> - assign_final(t11_t12);
> -#undef assign_final
> -
> -#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
> - intel_dp->panel_power_up_delay = get_delay(t1_t3);
> - intel_dp->backlight_on_delay = get_delay(t8);
> - intel_dp->backlight_off_delay = get_delay(t9);
> - intel_dp->panel_power_down_delay = get_delay(t10);
> - intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
> -#undef get_delay
> -
> - drm_dbg_kms(&dev_priv->drm,
> - "panel power up delay %d, power down delay %d, power
> cycle delay %d\n",
> - intel_dp->panel_power_up_delay,
> - intel_dp->panel_power_down_delay,
> - intel_dp->panel_power_cycle_delay);
> -
> - drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay
> %d\n",
> - intel_dp->backlight_on_delay,
> - intel_dp->backlight_off_delay);
> -
> - /*
> - * We override the HW backlight delays to 1 because we do manual
> waits
> - * on them. For T8, even BSpec recommends doing it. For T9, if we
> - * don't do this, we'll end up waiting for the backlight off delay
> - * twice: once when we do the manual sleep, and once when we
> disable
> - * the panel and wait for the PP_STATUS bit to become zero.
> - */
> - final->t8 = 1;
> - final->t9 = 1;
> -
> - /*
> - * HW has only a 100msec granularity for t11_t12 so round it up
> - * accordingly.
> - */
> - final->t11_t12 = roundup(final->t11_t12, 100 * 10);
> -}
> -
> -static void
> -intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
> - bool force_disable_vdd)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - u32 pp_on, pp_off, port_sel = 0;
> - int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
> - struct pps_registers regs;
> - enum port port = dp_to_dig_port(intel_dp)->base.port;
> - const struct edp_power_seq *seq = &intel_dp->pps_delays;
> -
> - lockdep_assert_held(&dev_priv->pps_mutex);
> -
> - intel_pps_get_registers(intel_dp, ®s);
> -
> - /*
> - * On some VLV machines the BIOS can leave the VDD
> - * enabled even on power sequencers which aren't
> - * hooked up to any port. This would mess up the
> - * power domain tracking the first time we pick
> - * one of these power sequencers for use since
> - * edp_panel_vdd_on() would notice that the VDD was
> - * already on and therefore wouldn't grab the power
> - * domain reference. Disable VDD first to avoid this.
> - * This also avoids spuriously turning the VDD on as
> - * soon as the new power sequencer gets initialized.
> - */
> - if (force_disable_vdd) {
> - u32 pp = ilk_get_pp_control(intel_dp);
> -
> - drm_WARN(&dev_priv->drm, pp & PANEL_POWER_ON,
> - "Panel power already on\n");
> -
> - if (pp & EDP_FORCE_VDD)
> - drm_dbg_kms(&dev_priv->drm,
> - "VDD already on, disabling first\n");
> -
> - pp &= ~EDP_FORCE_VDD;
> -
> - intel_de_write(dev_priv, regs.pp_ctrl, pp);
> - }
> -
> - pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq-
> >t1_t3) |
> - REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq-
> >t8);
> - pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq-
> >t9) |
> - REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK,
> seq->t10);
> -
> - /* Haswell doesn't have any port selection bits for the panel
> - * power sequencer any more. */
> - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> - port_sel = PANEL_PORT_SELECT_VLV(port);
> - } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
> - switch (port) {
> - case PORT_A:
> - port_sel = PANEL_PORT_SELECT_DPA;
> - break;
> - case PORT_C:
> - port_sel = PANEL_PORT_SELECT_DPC;
> - break;
> - case PORT_D:
> - port_sel = PANEL_PORT_SELECT_DPD;
> - break;
> - default:
> - MISSING_CASE(port);
> - break;
> - }
> - }
> -
> - pp_on |= port_sel;
> -
> - intel_de_write(dev_priv, regs.pp_on, pp_on);
> - intel_de_write(dev_priv, regs.pp_off, pp_off);
> -
> - /*
> - * Compute the divisor for the pp clock, simply match the Bspec
> formula.
> - */
> - if (i915_mmio_reg_valid(regs.pp_div)) {
> - intel_de_write(dev_priv, regs.pp_div,
> -
> REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) |
> REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK,
> DIV_ROUND_UP(seq->t11_t12, 1000)));
> - } else {
> - u32 pp_ctl;
> -
> - pp_ctl = intel_de_read(dev_priv, regs.pp_ctrl);
> - pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
> - pp_ctl |=
> REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq-
> >t11_t12, 1000));
> - intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
> - }
> -
> - drm_dbg_kms(&dev_priv->drm,
> - "panel power sequencer register settings: PP_ON %#x,
> PP_OFF %#x, PP_DIV %#x\n",
> - intel_de_read(dev_priv, regs.pp_on),
> - intel_de_read(dev_priv, regs.pp_off),
> - i915_mmio_reg_valid(regs.pp_div) ?
> - intel_de_read(dev_priv, regs.pp_div) :
> - (intel_de_read(dev_priv, regs.pp_ctrl) &
> BXT_POWER_CYCLE_DELAY_MASK));
> -}
> -
> -static void intel_dp_pps_init(struct intel_dp *intel_dp)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> -
> - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> - vlv_initial_power_sequencer_setup(intel_dp);
> - } else {
> - intel_dp_init_panel_power_sequencer(intel_dp);
> - intel_dp_init_panel_power_sequencer_registers(intel_dp,
> false);
> - }
> -}
> -
> /**
> * intel_dp_set_drrs_state - program registers for RR switch to take effect
> * @dev_priv: i915 device
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index b871a09b6901..87ace5d7f447 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -69,15 +69,11 @@ enum irqreturn intel_dp_hpd_pulse(struct
> intel_digital_port *dig_port,
> void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state);
> void intel_edp_backlight_off(const struct drm_connector_state
> *conn_state);
> -void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
> -void intel_edp_panel_on(struct intel_dp *intel_dp);
> -void intel_edp_panel_off(struct intel_dp *intel_dp);
> void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
> void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
> int intel_dp_max_link_rate(struct intel_dp *intel_dp);
> int intel_dp_max_lane_count(struct intel_dp *intel_dp);
> int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
> -void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
> u32 intel_dp_pack_aux(const u8 *src, int src_bytes);
>
> void intel_edp_drrs_enable(struct intel_dp *intel_dp,
> @@ -143,5 +139,6 @@ bool intel_dp_initial_fastset_check(struct
> intel_encoder *encoder,
> struct intel_crtc_state *crtc_state);
> void intel_dp_sync_state(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> +const struct dpll *vlv_get_dpll(struct drm_i915_private *i915);
>
> #endif /* __INTEL_DP_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
> b/drivers/gpu/drm/i915/display/intel_pps.c
> new file mode 100644
> index 000000000000..cfe347076031
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -0,0 +1,1337 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2020 Intel Corporation
> + */
> +
> +#include "i915_drv.h"
> +#include "intel_display_types.h"
> +#include "intel_dp.h"
> +#include "intel_pps.h"
> +
> +static void vlv_steal_power_sequencer(struct drm_i915_private
> *dev_priv,
> + enum pipe pipe);
> +static void
> +intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
> +static void
> +intel_dp_init_panel_power_sequencer_registers(struct intel_dp
> *intel_dp,
> + bool force_disable_vdd);
> +
> +intel_wakeref_t pps_lock(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + intel_wakeref_t wakeref;
> +
> + /*
> + * See intel_power_sequencer_reset() why we need
> + * a power domain reference here.
> + */
> + wakeref = intel_display_power_get(dev_priv,
> +
> intel_aux_power_domain(dp_to_dig_port(intel_dp)));
> +
> + mutex_lock(&dev_priv->pps_mutex);
> +
> + return wakeref;
> +}
> +
> +intel_wakeref_t pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t
> wakeref)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + mutex_unlock(&dev_priv->pps_mutex);
> + intel_display_power_put(dev_priv,
> +
> intel_aux_power_domain(dp_to_dig_port(intel_dp)),
> + wakeref);
> + return 0;
> +}
> +
> +static void
> +vlv_power_sequencer_kick(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + enum pipe pipe = intel_dp->pps_pipe;
> + bool pll_enabled, release_cl_override = false;
> + enum dpio_phy phy = DPIO_PHY(pipe);
> + enum dpio_channel ch = vlv_pipe_to_channel(pipe);
> + u32 DP;
> +
> + if (drm_WARN(&dev_priv->drm,
> + intel_de_read(dev_priv, intel_dp->output_reg) &
> DP_PORT_EN,
> + "skipping pipe %c power sequencer kick due to
> [ENCODER:%d:%s] being active\n",
> + pipe_name(pipe), dig_port->base.base.base.id,
> + dig_port->base.base.name))
> + return;
> +
> + drm_dbg_kms(&dev_priv->drm,
> + "kicking pipe %c power sequencer for
> [ENCODER:%d:%s]\n",
> + pipe_name(pipe), dig_port->base.base.base.id,
> + dig_port->base.base.name);
> +
> + /* Preserve the BIOS-computed detected bit. This is
> + * supposed to be read-only.
> + */
> + DP = intel_de_read(dev_priv, intel_dp->output_reg) &
> DP_DETECTED;
> + DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
> + DP |= DP_PORT_WIDTH(1);
> + DP |= DP_LINK_TRAIN_PAT_1;
> +
> + if (IS_CHERRYVIEW(dev_priv))
> + DP |= DP_PIPE_SEL_CHV(pipe);
> + else
> + DP |= DP_PIPE_SEL(pipe);
> +
> + pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) &
> DPLL_VCO_ENABLE;
> +
> + /*
> + * The DPLL for the pipe must be enabled for this to work.
> + * So enable temporarily it if it's not already enabled.
> + */
> + if (!pll_enabled) {
> + release_cl_override = IS_CHERRYVIEW(dev_priv) &&
> + !chv_phy_powergate_ch(dev_priv, phy, ch, true);
> +
> + if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(dev_priv)))
> {
> + drm_err(&dev_priv->drm,
> + "Failed to force on pll for pipe %c!\n",
> + pipe_name(pipe));
> + return;
> + }
> + }
> +
> + /*
> + * Similar magic as in intel_dp_enable_port().
> + * We _must_ do this port enable + disable trick
> + * to make this power sequencer lock onto the port.
> + * Otherwise even VDD force bit won't work.
> + */
> + intel_de_write(dev_priv, intel_dp->output_reg, DP);
> + intel_de_posting_read(dev_priv, intel_dp->output_reg);
> +
> + intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN);
> + intel_de_posting_read(dev_priv, intel_dp->output_reg);
> +
> + intel_de_write(dev_priv, intel_dp->output_reg, DP &
> ~DP_PORT_EN);
> + intel_de_posting_read(dev_priv, intel_dp->output_reg);
> +
> + if (!pll_enabled) {
> + vlv_force_pll_off(dev_priv, pipe);
> +
> + if (release_cl_override)
> + chv_phy_powergate_ch(dev_priv, phy, ch, false);
> + }
> +}
> +
> +static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
> +{
> + struct intel_encoder *encoder;
> + unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
> +
> + /*
> + * We don't have power sequencer currently.
> + * Pick one that's not used by other ports.
> + */
> + for_each_intel_dp(&dev_priv->drm, encoder) {
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> + if (encoder->type == INTEL_OUTPUT_EDP) {
> + drm_WARN_ON(&dev_priv->drm,
> + intel_dp->active_pipe != INVALID_PIPE
> &&
> + intel_dp->active_pipe !=
> + intel_dp->pps_pipe);
> +
> + if (intel_dp->pps_pipe != INVALID_PIPE)
> + pipes &= ~(1 << intel_dp->pps_pipe);
> + } else {
> + drm_WARN_ON(&dev_priv->drm,
> + intel_dp->pps_pipe != INVALID_PIPE);
> +
> + if (intel_dp->active_pipe != INVALID_PIPE)
> + pipes &= ~(1 << intel_dp->active_pipe);
> + }
> + }
> +
> + if (pipes == 0)
> + return INVALID_PIPE;
> +
> + return ffs(pipes) - 1;
> +}
> +
> +static enum pipe
> +vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + enum pipe pipe;
> +
> + lockdep_assert_held(&dev_priv->pps_mutex);
> +
> + /* We should never land here with regular DP ports */
> + drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
> +
> + drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe !=
> INVALID_PIPE &&
> + intel_dp->active_pipe != intel_dp->pps_pipe);
> +
> + if (intel_dp->pps_pipe != INVALID_PIPE)
> + return intel_dp->pps_pipe;
> +
> + pipe = vlv_find_free_pps(dev_priv);
> +
> + /*
> + * Didn't find one. This should not happen since there
> + * are two power sequencers and up to two eDP ports.
> + */
> + if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE))
> + pipe = PIPE_A;
> +
> + vlv_steal_power_sequencer(dev_priv, pipe);
> + intel_dp->pps_pipe = pipe;
> +
> + drm_dbg_kms(&dev_priv->drm,
> + "picked pipe %c power sequencer for
> [ENCODER:%d:%s]\n",
> + pipe_name(intel_dp->pps_pipe),
> + dig_port->base.base.base.id,
> + dig_port->base.base.name);
> +
> + /* init power sequencer on this pipe and port */
> + intel_dp_init_panel_power_sequencer(intel_dp);
> + intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
> +
> + /*
> + * Even vdd force doesn't work until we've made
> + * the power sequencer lock in on the port.
> + */
> + vlv_power_sequencer_kick(intel_dp);
> +
> + return intel_dp->pps_pipe;
> +}
> +
> +static int
> +bxt_power_sequencer_idx(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + int backlight_controller = dev_priv->vbt.backlight.controller;
> +
> + lockdep_assert_held(&dev_priv->pps_mutex);
> +
> + /* We should never land here with regular DP ports */
> + drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
> +
> + if (!intel_dp->pps_reset)
> + return backlight_controller;
> +
> + intel_dp->pps_reset = false;
> +
> + /*
> + * Only the HW needs to be reprogrammed, the SW state is fixed
> and
> + * has been setup during connector init.
> + */
> + intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
> +
> + return backlight_controller;
> +}
> +
> +typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
> + enum pipe pipe);
> +
> +static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
> + enum pipe pipe)
> +{
> + return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON;
> +}
> +
> +static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
> + enum pipe pipe)
> +{
> + return intel_de_read(dev_priv, PP_CONTROL(pipe)) &
> EDP_FORCE_VDD;
> +}
> +
> +static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
> + enum pipe pipe)
> +{
> + return true;
> +}
> +
> +static enum pipe
> +vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
> + enum port port,
> + vlv_pipe_check pipe_check)
> +{
> + enum pipe pipe;
> +
> + for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
> + u32 port_sel = intel_de_read(dev_priv,
> PP_ON_DELAYS(pipe)) &
> + PANEL_PORT_SELECT_MASK;
> +
> + if (port_sel != PANEL_PORT_SELECT_VLV(port))
> + continue;
> +
> + if (!pipe_check(dev_priv, pipe))
> + continue;
> +
> + return pipe;
> + }
> +
> + return INVALID_PIPE;
> +}
> +
> +static void
> +vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + enum port port = dig_port->base.port;
> +
> + lockdep_assert_held(&dev_priv->pps_mutex);
> +
> + /* try to find a pipe with this port selected */
> + /* first pick one where the panel is on */
> + intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
> + vlv_pipe_has_pp_on);
> + /* didn't find one? pick one where vdd is on */
> + if (intel_dp->pps_pipe == INVALID_PIPE)
> + intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
> +
> vlv_pipe_has_vdd_on);
> + /* didn't find one? pick one with just the correct port */
> + if (intel_dp->pps_pipe == INVALID_PIPE)
> + intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
> + vlv_pipe_any);
> +
> + /* didn't find one? just let vlv_power_sequencer_pipe() pick one
> when needed */
> + if (intel_dp->pps_pipe == INVALID_PIPE) {
> + drm_dbg_kms(&dev_priv->drm,
> + "no initial power sequencer for
> [ENCODER:%d:%s]\n",
> + dig_port->base.base.base.id,
> + dig_port->base.base.name);
> + return;
> + }
> +
> + drm_dbg_kms(&dev_priv->drm,
> + "initial power sequencer for [ENCODER:%d:%s]: pipe
> %c\n",
> + dig_port->base.base.base.id,
> + dig_port->base.base.name,
> + pipe_name(intel_dp->pps_pipe));
> +
> + intel_dp_init_panel_power_sequencer(intel_dp);
> + intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
> +}
> +
> +void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
> +{
> + struct intel_encoder *encoder;
> +
> + if (drm_WARN_ON(&dev_priv->drm,
> + !(IS_VALLEYVIEW(dev_priv) ||
> + IS_CHERRYVIEW(dev_priv) ||
> + IS_GEN9_LP(dev_priv))))
> + return;
> +
> + /*
> + * We can't grab pps_mutex here due to deadlock with
> power_domain
> + * mutex when power_domain functions are called while holding
> pps_mutex.
> + * That also means that in order to use pps_pipe the code needs to
> + * hold both a power domain reference and pps_mutex, and the
> power domain
> + * reference get/put must be done while _not_ holding pps_mutex.
> + * pps_{lock,unlock}() do these steps in the correct order, so one
> + * should use them always.
> + */
> +
> + for_each_intel_dp(&dev_priv->drm, encoder) {
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> + drm_WARN_ON(&dev_priv->drm,
> + intel_dp->active_pipe != INVALID_PIPE);
> +
> + if (encoder->type != INTEL_OUTPUT_EDP)
> + continue;
> +
> + if (IS_GEN9_LP(dev_priv))
> + intel_dp->pps_reset = true;
> + else
> + intel_dp->pps_pipe = INVALID_PIPE;
> + }
> +}
> +
> +struct pps_registers {
> + i915_reg_t pp_ctrl;
> + i915_reg_t pp_stat;
> + i915_reg_t pp_on;
> + i915_reg_t pp_off;
> + i915_reg_t pp_div;
> +};
> +
> +static void intel_pps_get_registers(struct intel_dp *intel_dp,
> + struct pps_registers *regs)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + int pps_idx = 0;
> +
> + memset(regs, 0, sizeof(*regs));
> +
> + if (IS_GEN9_LP(dev_priv))
> + pps_idx = bxt_power_sequencer_idx(intel_dp);
> + else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> + pps_idx = vlv_power_sequencer_pipe(intel_dp);
> +
> + regs->pp_ctrl = PP_CONTROL(pps_idx);
> + regs->pp_stat = PP_STATUS(pps_idx);
> + regs->pp_on = PP_ON_DELAYS(pps_idx);
> + regs->pp_off = PP_OFF_DELAYS(pps_idx);
> +
> + /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
> + if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >=
> PCH_CNP)
> + regs->pp_div = INVALID_MMIO_REG;
> + else
> + regs->pp_div = PP_DIVISOR(pps_idx);
> +}
> +
> +static i915_reg_t
> +_pp_ctrl_reg(struct intel_dp *intel_dp)
> +{
> + struct pps_registers regs;
> +
> + intel_pps_get_registers(intel_dp, ®s);
> +
> + return regs.pp_ctrl;
> +}
> +
> +static i915_reg_t
> +_pp_stat_reg(struct intel_dp *intel_dp)
> +{
> + struct pps_registers regs;
> +
> + intel_pps_get_registers(intel_dp, ®s);
> +
> + return regs.pp_stat;
> +}
> +
> +static bool edp_have_panel_power(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + lockdep_assert_held(&dev_priv->pps_mutex);
> +
> + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> + intel_dp->pps_pipe == INVALID_PIPE)
> + return false;
> +
> + return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON)
> != 0;
> +}
> +
> +static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + lockdep_assert_held(&dev_priv->pps_mutex);
> +
> + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> + intel_dp->pps_pipe == INVALID_PIPE)
> + return false;
> +
> + return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) &
> EDP_FORCE_VDD;
> +}
> +
> +void intel_dp_check_edp(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + if (!intel_dp_is_edp(intel_dp))
> + return;
> +
> + if (!edp_have_panel_power(intel_dp) &&
> !edp_have_panel_vdd(intel_dp)) {
> + drm_WARN(&dev_priv->drm, 1,
> + "eDP powered off while attempting aux channel
> communication.\n");
> + drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control
> 0x%08x\n",
> + intel_de_read(dev_priv, _pp_stat_reg(intel_dp)),
> + intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)));
> + }
> +}
> +
> +#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0
> | PP_SEQUENCE_STATE_MASK)
> +#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0
> | PP_SEQUENCE_STATE_ON_IDLE)
> +
> +#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0
> | 0)
> +#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0
> | 0)
> +
> +#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK |
> PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
> +#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0
> | PP_SEQUENCE_STATE_OFF_IDLE)
> +
> +static void intel_pps_verify_state(struct intel_dp *intel_dp);
> +
> +static void wait_panel_status(struct intel_dp *intel_dp,
> + u32 mask,
> + u32 value)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + i915_reg_t pp_stat_reg, pp_ctrl_reg;
> +
> + lockdep_assert_held(&dev_priv->pps_mutex);
> +
> + intel_pps_verify_state(intel_dp);
> +
> + pp_stat_reg = _pp_stat_reg(intel_dp);
> + pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
> +
> + drm_dbg_kms(&dev_priv->drm,
> + "mask %08x value %08x status %08x control %08x\n",
> + mask, value,
> + intel_de_read(dev_priv, pp_stat_reg),
> + intel_de_read(dev_priv, pp_ctrl_reg));
> +
> + if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
> + mask, value, 5000))
> + drm_err(&dev_priv->drm,
> + "Panel status timeout: status %08x control %08x\n",
> + intel_de_read(dev_priv, pp_stat_reg),
> + intel_de_read(dev_priv, pp_ctrl_reg));
> +
> + drm_dbg_kms(&dev_priv->drm, "Wait complete\n");
> +}
> +
> +static void wait_panel_on(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> +
> + drm_dbg_kms(&i915->drm, "Wait for panel power on\n");
> + wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
> +}
> +
> +static void wait_panel_off(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> +
> + drm_dbg_kms(&i915->drm, "Wait for panel power off time\n");
> + wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
> +}
> +
> +void wait_panel_power_cycle(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> + ktime_t panel_power_on_time;
> + s64 panel_power_off_duration;
> +
> + drm_dbg_kms(&i915->drm, "Wait for panel power cycle\n");
> +
> + /* take the difference of currrent time and panel power off time
> + * and then make panel wait for t11_t12 if needed. */
> + panel_power_on_time = ktime_get_boottime();
> + panel_power_off_duration =
> ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
> +
> + /* When we disable the VDD override bit last we have to do the
> manual
> + * wait. */
> + if (panel_power_off_duration < (s64)intel_dp-
> >panel_power_cycle_delay)
> + wait_remaining_ms_from_jiffies(jiffies,
> + intel_dp->panel_power_cycle_delay -
> panel_power_off_duration);
> +
> + wait_panel_status(intel_dp, IDLE_CYCLE_MASK,
> IDLE_CYCLE_VALUE);
> +}
> +
> +static void wait_backlight_on(struct intel_dp *intel_dp)
> +{
> + wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
> + intel_dp->backlight_on_delay);
> +}
> +
> +static void edp_wait_backlight_off(struct intel_dp *intel_dp)
> +{
> + wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
> + intel_dp->backlight_off_delay);
> +}
> +
> +/* Read the current pp_control value, unlocking the register if it
> + * is locked
> + */
> +
> +static u32 ilk_get_pp_control(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + u32 control;
> +
> + lockdep_assert_held(&dev_priv->pps_mutex);
> +
> + control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
> + if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) &&
> + (control & PANEL_UNLOCK_MASK) !=
> PANEL_UNLOCK_REGS)) {
> + control &= ~PANEL_UNLOCK_MASK;
> + control |= PANEL_UNLOCK_REGS;
> + }
> + return control;
> +}
> +
> +/*
> + * Must be paired with edp_panel_vdd_off().
> + * Must hold pps_mutex around the whole on/off sequence.
> + * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
> + */
> +bool edp_panel_vdd_on(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + u32 pp;
> + i915_reg_t pp_stat_reg, pp_ctrl_reg;
> + bool need_to_disable = !intel_dp->want_panel_vdd;
> +
> + lockdep_assert_held(&dev_priv->pps_mutex);
> +
> + if (!intel_dp_is_edp(intel_dp))
> + return false;
> +
> + cancel_delayed_work(&intel_dp->panel_vdd_work);
> + intel_dp->want_panel_vdd = true;
> +
> + if (edp_have_panel_vdd(intel_dp))
> + return need_to_disable;
> +
> + drm_WARN_ON(&dev_priv->drm, intel_dp->vdd_wakeref);
> + intel_dp->vdd_wakeref = intel_display_power_get(dev_priv,
> +
> intel_aux_power_domain(dig_port));
> +
> + drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD
> on\n",
> + dig_port->base.base.base.id,
> + dig_port->base.base.name);
> +
> + if (!edp_have_panel_power(intel_dp))
> + wait_panel_power_cycle(intel_dp);
> +
> + pp = ilk_get_pp_control(intel_dp);
> + pp |= EDP_FORCE_VDD;
> +
> + pp_stat_reg = _pp_stat_reg(intel_dp);
> + pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
> +
> + intel_de_write(dev_priv, pp_ctrl_reg, pp);
> + intel_de_posting_read(dev_priv, pp_ctrl_reg);
> + drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x
> PP_CONTROL: 0x%08x\n",
> + intel_de_read(dev_priv, pp_stat_reg),
> + intel_de_read(dev_priv, pp_ctrl_reg));
> + /*
> + * If the panel wasn't on, delay before accessing aux channel
> + */
> + if (!edp_have_panel_power(intel_dp)) {
> + drm_dbg_kms(&dev_priv->drm,
> + "[ENCODER:%d:%s] panel power wasn't
> enabled\n",
> + dig_port->base.base.base.id,
> + dig_port->base.base.name);
> + msleep(intel_dp->panel_power_up_delay);
> + }
> +
> + return need_to_disable;
> +}
> +
> +/*
> + * Must be paired with intel_edp_panel_vdd_off() or
> + * intel_edp_panel_off().
> + * Nested calls to these functions are not allowed since
> + * we drop the lock. Caller must use some higher level
> + * locking to prevent nested calls from other threads.
> + */
> +void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
> +{
> + intel_wakeref_t wakeref;
> + bool vdd;
> +
> + if (!intel_dp_is_edp(intel_dp))
> + return;
> +
> + vdd = false;
> + with_pps_lock(intel_dp, wakeref)
> + vdd = edp_panel_vdd_on(intel_dp);
> + I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already
> requested on\n",
> + dp_to_dig_port(intel_dp)->base.base.base.id,
> + dp_to_dig_port(intel_dp)->base.base.name);
> +}
> +
> +void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct intel_digital_port *dig_port =
> + dp_to_dig_port(intel_dp);
> + u32 pp;
> + i915_reg_t pp_stat_reg, pp_ctrl_reg;
> +
> + lockdep_assert_held(&dev_priv->pps_mutex);
> +
> + drm_WARN_ON(&dev_priv->drm, intel_dp->want_panel_vdd);
> +
> + if (!edp_have_panel_vdd(intel_dp))
> + return;
> +
> + drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD
> off\n",
> + dig_port->base.base.base.id,
> + dig_port->base.base.name);
> +
> + pp = ilk_get_pp_control(intel_dp);
> + pp &= ~EDP_FORCE_VDD;
> +
> + pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
> + pp_stat_reg = _pp_stat_reg(intel_dp);
> +
> + intel_de_write(dev_priv, pp_ctrl_reg, pp);
> + intel_de_posting_read(dev_priv, pp_ctrl_reg);
> +
> + /* Make sure sequencer is idle before allowing subsequent activity
> */
> + drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x
> PP_CONTROL: 0x%08x\n",
> + intel_de_read(dev_priv, pp_stat_reg),
> + intel_de_read(dev_priv, pp_ctrl_reg));
> +
> + if ((pp & PANEL_POWER_ON) == 0)
> + intel_dp->panel_power_off_time = ktime_get_boottime();
> +
> + intel_display_power_put(dev_priv,
> + intel_aux_power_domain(dig_port),
> + fetch_and_zero(&intel_dp->vdd_wakeref));
> +}
> +
> +void edp_panel_vdd_work(struct work_struct *__work)
> +{
> + struct intel_dp *intel_dp =
> + container_of(to_delayed_work(__work),
> + struct intel_dp, panel_vdd_work);
> + intel_wakeref_t wakeref;
> +
> + with_pps_lock(intel_dp, wakeref) {
> + if (!intel_dp->want_panel_vdd)
> + edp_panel_vdd_off_sync(intel_dp);
> + }
> +}
> +
> +static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
> +{
> + unsigned long delay;
> +
> + /*
> + * Queue the timer to fire a long time from now (relative to the
> power
> + * down delay) to keep the panel power up across a sequence of
> + * operations.
> + */
> + delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
> + schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
> +}
> +
> +/*
> + * Must be paired with edp_panel_vdd_on().
> + * Must hold pps_mutex around the whole on/off sequence.
> + * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
> + */
> +void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + lockdep_assert_held(&dev_priv->pps_mutex);
> +
> + if (!intel_dp_is_edp(intel_dp))
> + return;
> +
> + I915_STATE_WARN(!intel_dp->want_panel_vdd,
> "[ENCODER:%d:%s] VDD not forced on",
> + dp_to_dig_port(intel_dp)->base.base.base.id,
> + dp_to_dig_port(intel_dp)->base.base.name);
> +
> + intel_dp->want_panel_vdd = false;
> +
> + if (sync)
> + edp_panel_vdd_off_sync(intel_dp);
> + else
> + edp_panel_vdd_schedule_off(intel_dp);
> +}
> +
> +void edp_panel_on(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + u32 pp;
> + i915_reg_t pp_ctrl_reg;
> +
> + lockdep_assert_held(&dev_priv->pps_mutex);
> +
> + if (!intel_dp_is_edp(intel_dp))
> + return;
> +
> + drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel
> power on\n",
> + dp_to_dig_port(intel_dp)->base.base.base.id,
> + dp_to_dig_port(intel_dp)->base.base.name);
> +
> + if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp),
> + "[ENCODER:%d:%s] panel power already on\n",
> + dp_to_dig_port(intel_dp)->base.base.base.id,
> + dp_to_dig_port(intel_dp)->base.base.name))
> + return;
> +
> + wait_panel_power_cycle(intel_dp);
> +
> + pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
> + pp = ilk_get_pp_control(intel_dp);
> + if (IS_GEN(dev_priv, 5)) {
> + /* ILK workaround: disable reset around power sequence */
> + pp &= ~PANEL_POWER_RESET;
> + intel_de_write(dev_priv, pp_ctrl_reg, pp);
> + intel_de_posting_read(dev_priv, pp_ctrl_reg);
> + }
> +
> + pp |= PANEL_POWER_ON;
> + if (!IS_GEN(dev_priv, 5))
> + pp |= PANEL_POWER_RESET;
> +
> + intel_de_write(dev_priv, pp_ctrl_reg, pp);
> + intel_de_posting_read(dev_priv, pp_ctrl_reg);
> +
> + wait_panel_on(intel_dp);
> + intel_dp->last_power_on = jiffies;
> +
> + if (IS_GEN(dev_priv, 5)) {
> + pp |= PANEL_POWER_RESET; /* restore panel reset bit */
> + intel_de_write(dev_priv, pp_ctrl_reg, pp);
> + intel_de_posting_read(dev_priv, pp_ctrl_reg);
> + }
> +}
> +
> +void intel_edp_panel_on(struct intel_dp *intel_dp)
> +{
> + intel_wakeref_t wakeref;
> +
> + if (!intel_dp_is_edp(intel_dp))
> + return;
> +
> + with_pps_lock(intel_dp, wakeref)
> + edp_panel_on(intel_dp);
> +}
> +
> +void edp_panel_off(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + u32 pp;
> + i915_reg_t pp_ctrl_reg;
> +
> + lockdep_assert_held(&dev_priv->pps_mutex);
> +
> + if (!intel_dp_is_edp(intel_dp))
> + return;
> +
> + drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel
> power off\n",
> + dig_port->base.base.base.id, dig_port->base.base.name);
> +
> + drm_WARN(&dev_priv->drm, !intel_dp->want_panel_vdd,
> + "Need [ENCODER:%d:%s] VDD to turn off panel\n",
> + dig_port->base.base.base.id, dig_port->base.base.name);
> +
> + pp = ilk_get_pp_control(intel_dp);
> + /* We need to switch off panel power _and_ force vdd, for
> otherwise some
> + * panels get very unhappy and cease to work. */
> + pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET |
> EDP_FORCE_VDD |
> + EDP_BLC_ENABLE);
> +
> + pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
> +
> + intel_dp->want_panel_vdd = false;
> +
> + intel_de_write(dev_priv, pp_ctrl_reg, pp);
> + intel_de_posting_read(dev_priv, pp_ctrl_reg);
> +
> + wait_panel_off(intel_dp);
> + intel_dp->panel_power_off_time = ktime_get_boottime();
> +
> + /* We got a reference when we enabled the VDD. */
> + intel_display_power_put(dev_priv,
> + intel_aux_power_domain(dig_port),
> + fetch_and_zero(&intel_dp->vdd_wakeref));
> +}
> +
> +void intel_edp_panel_off(struct intel_dp *intel_dp)
> +{
> + intel_wakeref_t wakeref;
> +
> + if (!intel_dp_is_edp(intel_dp))
> + return;
> +
> + with_pps_lock(intel_dp, wakeref)
> + edp_panel_off(intel_dp);
> +}
> +
> +/* Enable backlight in the panel power control. */
> +void _intel_edp_backlight_on(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + intel_wakeref_t wakeref;
> +
> + /*
> + * If we enable the backlight right away following a panel power
> + * on, we may see slight flicker as the panel syncs with the eDP
> + * link. So delay a bit to make sure the image is solid before
> + * allowing it to appear.
> + */
> + wait_backlight_on(intel_dp);
> +
> + with_pps_lock(intel_dp, wakeref) {
> + i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
> + u32 pp;
> +
> + pp = ilk_get_pp_control(intel_dp);
> + pp |= EDP_BLC_ENABLE;
> +
> + intel_de_write(dev_priv, pp_ctrl_reg, pp);
> + intel_de_posting_read(dev_priv, pp_ctrl_reg);
> + }
> +}
> +
> +/* Disable backlight in the panel power control. */
> +void _intel_edp_backlight_off(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + intel_wakeref_t wakeref;
> +
> + if (!intel_dp_is_edp(intel_dp))
> + return;
> +
> + with_pps_lock(intel_dp, wakeref) {
> + i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
> + u32 pp;
> +
> + pp = ilk_get_pp_control(intel_dp);
> + pp &= ~EDP_BLC_ENABLE;
> +
> + intel_de_write(dev_priv, pp_ctrl_reg, pp);
> + intel_de_posting_read(dev_priv, pp_ctrl_reg);
> + }
> +
> + intel_dp->last_backlight_off = jiffies;
> + edp_wait_backlight_off(intel_dp);
> +}
> +
> +/*
> + * Hook for controlling the panel power control backlight through the
> bl_power
> + * sysfs attribute. Take care to handle multiple calls.
> + */
> +void intel_edp_backlight_power(struct intel_connector *connector, bool
> enable)
> +{
> + struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct intel_dp *intel_dp = intel_attached_dp(connector);
> + intel_wakeref_t wakeref;
> + bool is_enabled;
> +
> + is_enabled = false;
> + with_pps_lock(intel_dp, wakeref)
> + is_enabled = ilk_get_pp_control(intel_dp) &
> EDP_BLC_ENABLE;
> + if (is_enabled == enable)
> + return;
> +
> + drm_dbg_kms(&i915->drm, "panel power control backlight %s\n",
> + enable ? "enable" : "disable");
> +
> + if (enable)
> + _intel_edp_backlight_on(intel_dp);
> + else
> + _intel_edp_backlight_off(intel_dp);
> +}
> +
> +static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
> +{
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + struct drm_i915_private *dev_priv = to_i915(dig_port-
> >base.base.dev);
> + enum pipe pipe = intel_dp->pps_pipe;
> + i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
> +
> + drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe !=
> INVALID_PIPE);
> +
> + if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe !=
> PIPE_B))
> + return;
> +
> + edp_panel_vdd_off_sync(intel_dp);
> +
> + /*
> + * VLV seems to get confused when multiple power sequencers
> + * have the same port selected (even if only one has power/vdd
> + * enabled). The failure manifests as vlv_wait_port_ready() failing
> + * CHV on the other hand doesn't seem to mind having the same
> port
> + * selected in multiple power sequencers, but let's clear the
> + * port select always when logically disconnecting a power
> sequencer
> + * from a port.
> + */
> + drm_dbg_kms(&dev_priv->drm,
> + "detaching pipe %c power sequencer from
> [ENCODER:%d:%s]\n",
> + pipe_name(pipe), dig_port->base.base.base.id,
> + dig_port->base.base.name);
> + intel_de_write(dev_priv, pp_on_reg, 0);
> + intel_de_posting_read(dev_priv, pp_on_reg);
> +
> + intel_dp->pps_pipe = INVALID_PIPE;
> +}
> +
> +static void vlv_steal_power_sequencer(struct drm_i915_private
> *dev_priv,
> + enum pipe pipe)
> +{
> + struct intel_encoder *encoder;
> +
> + lockdep_assert_held(&dev_priv->pps_mutex);
> +
> + for_each_intel_dp(&dev_priv->drm, encoder) {
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> + drm_WARN(&dev_priv->drm, intel_dp->active_pipe ==
> pipe,
> + "stealing pipe %c power sequencer from active
> [ENCODER:%d:%s]\n",
> + pipe_name(pipe), encoder->base.base.id,
> + encoder->base.name);
> +
> + if (intel_dp->pps_pipe != pipe)
> + continue;
> +
> + drm_dbg_kms(&dev_priv->drm,
> + "stealing pipe %c power sequencer from
> [ENCODER:%d:%s]\n",
> + pipe_name(pipe), encoder->base.base.id,
> + encoder->base.name);
> +
> + /* make sure vdd is off before we steal it */
> + vlv_detach_power_sequencer(intel_dp);
> + }
> +}
> +
> +void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +
> + lockdep_assert_held(&dev_priv->pps_mutex);
> +
> + drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe !=
> INVALID_PIPE);
> +
> + if (intel_dp->pps_pipe != INVALID_PIPE &&
> + intel_dp->pps_pipe != crtc->pipe) {
> + /*
> + * If another power sequencer was being used on this
> + * port previously make sure to turn off vdd there while
> + * we still have control of it.
> + */
> + vlv_detach_power_sequencer(intel_dp);
> + }
> +
> + /*
> + * We may be stealing the power
> + * sequencer from another port.
> + */
> + vlv_steal_power_sequencer(dev_priv, crtc->pipe);
> +
> + intel_dp->active_pipe = crtc->pipe;
> +
> + if (!intel_dp_is_edp(intel_dp))
> + return;
> +
> + /* now it's all ours */
> + intel_dp->pps_pipe = crtc->pipe;
> +
> + drm_dbg_kms(&dev_priv->drm,
> + "initializing pipe %c power sequencer for
> [ENCODER:%d:%s]\n",
> + pipe_name(intel_dp->pps_pipe), encoder->base.base.id,
> + encoder->base.name);
> +
> + /* init power sequencer on this pipe and port */
> + intel_dp_init_panel_power_sequencer(intel_dp);
> + intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
> +}
> +
> +void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> +
> + lockdep_assert_held(&dev_priv->pps_mutex);
> +
> + if (!edp_have_panel_vdd(intel_dp))
> + return;
> +
> + /*
> + * The VDD bit needs a power domain reference, so if the bit is
> + * already enabled when we boot or resume, grab this reference and
> + * schedule a vdd off, so we don't hold on to the reference
> + * indefinitely.
> + */
> + drm_dbg_kms(&dev_priv->drm,
> + "VDD left on by BIOS, adjusting state tracking\n");
> + drm_WARN_ON(&dev_priv->drm, intel_dp->vdd_wakeref);
> + intel_dp->vdd_wakeref = intel_display_power_get(dev_priv,
> +
> intel_aux_power_domain(dig_port));
> +
> + edp_panel_vdd_schedule_off(intel_dp);
> +}
> +
> +bool intel_edp_have_power(struct intel_dp *intel_dp)
> +{
> + intel_wakeref_t wakeref;
> + bool have_power = false;
> +
> + with_pps_lock(intel_dp, wakeref) {
> + have_power = edp_have_panel_power(intel_dp) &&
> +
> edp_have_panel_vdd(intel_dp);
> + }
> +
> + return have_power;
> +}
> +
> +void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> +{
> + intel_dp->panel_power_off_time = ktime_get_boottime();
> + intel_dp->last_power_on = jiffies;
> + intel_dp->last_backlight_off = jiffies;
> +}
> +
> +static void
> +intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct
> edp_power_seq *seq)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + u32 pp_on, pp_off, pp_ctl;
> + struct pps_registers regs;
> +
> + intel_pps_get_registers(intel_dp, ®s);
> +
> + pp_ctl = ilk_get_pp_control(intel_dp);
> +
> + /* Ensure PPS is unlocked */
> + if (!HAS_DDI(dev_priv))
> + intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
> +
> + pp_on = intel_de_read(dev_priv, regs.pp_on);
> + pp_off = intel_de_read(dev_priv, regs.pp_off);
> +
> + /* Pull timing values out of registers */
> + seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK,
> pp_on);
> + seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK,
> pp_on);
> + seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK,
> pp_off);
> + seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK,
> pp_off);
> +
> + if (i915_mmio_reg_valid(regs.pp_div)) {
> + u32 pp_div;
> +
> + pp_div = intel_de_read(dev_priv, regs.pp_div);
> +
> + seq->t11_t12 =
> REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
> + } else {
> + seq->t11_t12 =
> REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
> + }
> +}
> +
> +static void
> +intel_pps_dump_state(const char *state_name, const struct
> edp_power_seq *seq)
> +{
> + DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12
> %d\n",
> + state_name,
> + seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
> +}
> +
> +static void
> +intel_pps_verify_state(struct intel_dp *intel_dp)
> +{
> + struct edp_power_seq hw;
> + struct edp_power_seq *sw = &intel_dp->pps_delays;
> +
> + intel_pps_readout_hw_state(intel_dp, &hw);
> +
> + if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
> + hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
> + DRM_ERROR("PPS state mismatch\n");
> + intel_pps_dump_state("sw", sw);
> + intel_pps_dump_state("hw", &hw);
> + }
> +}
> +
> +static void
> +intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct edp_power_seq cur, vbt, spec,
> + *final = &intel_dp->pps_delays;
> +
> + lockdep_assert_held(&dev_priv->pps_mutex);
> +
> + /* already initialized? */
> + if (final->t11_t12 != 0)
> + return;
> +
> + intel_pps_readout_hw_state(intel_dp, &cur);
> +
> + intel_pps_dump_state("cur", &cur);
> +
> + vbt = dev_priv->vbt.edp.pps;
> + /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
> + * of 500ms appears to be too short. Ocassionally the panel
> + * just fails to power back on. Increasing the delay to 800ms
> + * seems sufficient to avoid this problem.
> + */
> + if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
> + vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
> + drm_dbg_kms(&dev_priv->drm,
> + "Increasing T12 panel delay as per the quirk to
> %d\n",
> + vbt.t11_t12);
> + }
> + /* T11_T12 delay is special and actually in units of 100ms, but zero
> + * based in the hw (so we need to add 100 ms). But the sw vbt
> + * table multiplies it with 1000 to make it in units of 100usec,
> + * too. */
> + vbt.t11_t12 += 100 * 10;
> +
> + /* Upper limits from eDP 1.3 spec. Note that we use the clunky
> units of
> + * our hw here, which are all in 100usec. */
> + spec.t1_t3 = 210 * 10;
> + spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
> + spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
> + spec.t10 = 500 * 10;
> + /* This one is special and actually in units of 100ms, but zero
> + * based in the hw (so we need to add 100 ms). But the sw vbt
> + * table multiplies it with 1000 to make it in units of 100usec,
> + * too. */
> + spec.t11_t12 = (510 + 100) * 10;
> +
> + intel_pps_dump_state("vbt", &vbt);
> +
> + /* Use the max of the register settings and vbt. If both are
> + * unset, fall back to the spec limits. */
> +#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ?
> \
> + spec.field : \
> + max(cur.field, vbt.field))
> + assign_final(t1_t3);
> + assign_final(t8);
> + assign_final(t9);
> + assign_final(t10);
> + assign_final(t11_t12);
> +#undef assign_final
> +
> +#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
> + intel_dp->panel_power_up_delay = get_delay(t1_t3);
> + intel_dp->backlight_on_delay = get_delay(t8);
> + intel_dp->backlight_off_delay = get_delay(t9);
> + intel_dp->panel_power_down_delay = get_delay(t10);
> + intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
> +#undef get_delay
> +
> + drm_dbg_kms(&dev_priv->drm,
> + "panel power up delay %d, power down delay %d, power
> cycle delay %d\n",
> + intel_dp->panel_power_up_delay,
> + intel_dp->panel_power_down_delay,
> + intel_dp->panel_power_cycle_delay);
> +
> + drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay
> %d\n",
> + intel_dp->backlight_on_delay,
> + intel_dp->backlight_off_delay);
> +
> + /*
> + * We override the HW backlight delays to 1 because we do manual
> waits
> + * on them. For T8, even BSpec recommends doing it. For T9, if we
> + * don't do this, we'll end up waiting for the backlight off delay
> + * twice: once when we do the manual sleep, and once when we
> disable
> + * the panel and wait for the PP_STATUS bit to become zero.
> + */
> + final->t8 = 1;
> + final->t9 = 1;
> +
> + /*
> + * HW has only a 100msec granularity for t11_t12 so round it up
> + * accordingly.
> + */
> + final->t11_t12 = roundup(final->t11_t12, 100 * 10);
> +}
> +
> +static void
> +intel_dp_init_panel_power_sequencer_registers(struct intel_dp
> *intel_dp,
> + bool force_disable_vdd)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + u32 pp_on, pp_off, port_sel = 0;
> + int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
> + struct pps_registers regs;
> + enum port port = dp_to_dig_port(intel_dp)->base.port;
> + const struct edp_power_seq *seq = &intel_dp->pps_delays;
> +
> + lockdep_assert_held(&dev_priv->pps_mutex);
> +
> + intel_pps_get_registers(intel_dp, ®s);
> +
> + /*
> + * On some VLV machines the BIOS can leave the VDD
> + * enabled even on power sequencers which aren't
> + * hooked up to any port. This would mess up the
> + * power domain tracking the first time we pick
> + * one of these power sequencers for use since
> + * edp_panel_vdd_on() would notice that the VDD was
> + * already on and therefore wouldn't grab the power
> + * domain reference. Disable VDD first to avoid this.
> + * This also avoids spuriously turning the VDD on as
> + * soon as the new power sequencer gets initialized.
> + */
> + if (force_disable_vdd) {
> + u32 pp = ilk_get_pp_control(intel_dp);
> +
> + drm_WARN(&dev_priv->drm, pp & PANEL_POWER_ON,
> + "Panel power already on\n");
> +
> + if (pp & EDP_FORCE_VDD)
> + drm_dbg_kms(&dev_priv->drm,
> + "VDD already on, disabling first\n");
> +
> + pp &= ~EDP_FORCE_VDD;
> +
> + intel_de_write(dev_priv, regs.pp_ctrl, pp);
> + }
> +
> + pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq-
> >t1_t3) |
> + REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq-
> >t8);
> + pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq-
> >t9) |
> + REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK,
> seq->t10);
> +
> + /* Haswell doesn't have any port selection bits for the panel
> + * power sequencer any more. */
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> + port_sel = PANEL_PORT_SELECT_VLV(port);
> + } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
> + switch (port) {
> + case PORT_A:
> + port_sel = PANEL_PORT_SELECT_DPA;
> + break;
> + case PORT_C:
> + port_sel = PANEL_PORT_SELECT_DPC;
> + break;
> + case PORT_D:
> + port_sel = PANEL_PORT_SELECT_DPD;
> + break;
> + default:
> + MISSING_CASE(port);
> + break;
> + }
> + }
> +
> + pp_on |= port_sel;
> +
> + intel_de_write(dev_priv, regs.pp_on, pp_on);
> + intel_de_write(dev_priv, regs.pp_off, pp_off);
> +
> + /*
> + * Compute the divisor for the pp clock, simply match the Bspec
> formula.
> + */
> + if (i915_mmio_reg_valid(regs.pp_div)) {
> + intel_de_write(dev_priv, regs.pp_div,
> +
> REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) |
> REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK,
> DIV_ROUND_UP(seq->t11_t12, 1000)));
> + } else {
> + u32 pp_ctl;
> +
> + pp_ctl = intel_de_read(dev_priv, regs.pp_ctrl);
> + pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
> + pp_ctl |=
> REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq-
> >t11_t12, 1000));
> + intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
> + }
> +
> + drm_dbg_kms(&dev_priv->drm,
> + "panel power sequencer register settings: PP_ON %#x,
> PP_OFF %#x, PP_DIV %#x\n",
> + intel_de_read(dev_priv, regs.pp_on),
> + intel_de_read(dev_priv, regs.pp_off),
> + i915_mmio_reg_valid(regs.pp_div) ?
> + intel_de_read(dev_priv, regs.pp_div) :
> + (intel_de_read(dev_priv, regs.pp_ctrl) &
> BXT_POWER_CYCLE_DELAY_MASK));
> +}
> +
> +void intel_dp_pps_init(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> + vlv_initial_power_sequencer_setup(intel_dp);
> + } else {
> + intel_dp_init_panel_power_sequencer(intel_dp);
> + intel_dp_init_panel_power_sequencer_registers(intel_dp,
> false);
> + }
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.h
> b/drivers/gpu/drm/i915/display/intel_pps.h
> new file mode 100644
> index 000000000000..76d5cc565501
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_pps.h
> @@ -0,0 +1,53 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2020 Intel Corporation
> + */
> +
> +#ifndef __INTEL_PPS_H__
> +#define __INTEL_PPS_H__
> +
> +#include <linux/types.h>
> +
> +#include "intel_wakeref.h"
> +
> +struct drm_i915_private;
> +struct intel_connector;
> +struct intel_crtc_state;
> +struct intel_dp;
> +struct intel_encoder;
> +
> +intel_wakeref_t pps_lock(struct intel_dp *intel_dp);
> +intel_wakeref_t pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t
> wakeref);
> +
> +#define with_pps_lock(dp, wf)
> \
> + for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
> +
> +void intel_dp_check_edp(struct intel_dp *intel_dp);
> +void _intel_edp_backlight_on(struct intel_dp *intel_dp);
> +void _intel_edp_backlight_off(struct intel_dp *intel_dp);
> +void intel_edp_backlight_power(struct intel_connector *connector, bool
> enable);
> +
> +bool edp_panel_vdd_on(struct intel_dp *intel_dp);
> +void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
> +void edp_panel_vdd_off_sync(struct intel_dp *intel_dp);
> +void edp_panel_on(struct intel_dp *intel_dp);
> +void edp_panel_off(struct intel_dp *intel_dp);
> +void edp_panel_vdd_work(struct work_struct *__work);
> +
> +void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
> +void intel_edp_panel_on(struct intel_dp *intel_dp);
> +void intel_edp_panel_off(struct intel_dp *intel_dp);
> +bool intel_edp_have_power(struct intel_dp *intel_dp);
> +
> +void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp);
> +
> +void wait_panel_power_cycle(struct intel_dp *intel_dp);
> +
> +void intel_dp_pps_init(struct intel_dp *intel_dp);
> +void intel_power_sequencer_reset(struct drm_i915_private *i915);
> +void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp);
> +
> +void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state);
> +
> +#endif /* __INTEL_PPS_H__ */
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-gfx] [PATCH 03/13] drm/i915/pps: rename intel_edp_backlight_* to intel_pps_backlight_*
2020-12-22 14:49 ` [Intel-gfx] [PATCH 03/13] drm/i915/pps: rename intel_edp_backlight_* to intel_pps_backlight_* Jani Nikula
@ 2020-12-29 6:12 ` Anshuman Gupta
0 siblings, 0 replies; 35+ messages in thread
From: Anshuman Gupta @ 2020-12-29 6:12 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On 2020-12-22 at 20:19:43 +0530, Jani Nikula wrote:
> Follow the usual naming pattern for functions.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Looks good to me.
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 6 +++---
> drivers/gpu/drm/i915/display/intel_pps.c | 10 +++++-----
> drivers/gpu/drm/i915/display/intel_pps.h | 6 +++---
> 3 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0870872fb594..9813fb7e109c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2536,7 +2536,7 @@ void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
> drm_dbg_kms(&i915->drm, "\n");
>
> intel_panel_enable_backlight(crtc_state, conn_state);
> - _intel_edp_backlight_on(intel_dp);
> + intel_pps_backlight_on(intel_dp);
> }
>
> /* Disable backlight PP control and backlight PWM. */
> @@ -2550,7 +2550,7 @@ void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
>
> drm_dbg_kms(&i915->drm, "\n");
>
> - _intel_edp_backlight_off(intel_dp);
> + intel_pps_backlight_off(intel_dp);
> intel_panel_disable_backlight(old_conn_state);
> }
>
> @@ -6688,7 +6688,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
> }
>
> intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
> - intel_connector->panel.backlight.power = intel_edp_backlight_power;
> + intel_connector->panel.backlight.power = intel_pps_backlight_power;
> intel_panel_setup_backlight(connector, pipe);
>
> if (fixed_mode) {
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> index 9b0c432552b7..0edda87dee94 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -847,7 +847,7 @@ void intel_edp_panel_off(struct intel_dp *intel_dp)
> }
>
> /* Enable backlight in the panel power control. */
> -void _intel_edp_backlight_on(struct intel_dp *intel_dp)
> +void intel_pps_backlight_on(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> intel_wakeref_t wakeref;
> @@ -873,7 +873,7 @@ void _intel_edp_backlight_on(struct intel_dp *intel_dp)
> }
>
> /* Disable backlight in the panel power control. */
> -void _intel_edp_backlight_off(struct intel_dp *intel_dp)
> +void intel_pps_backlight_off(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> intel_wakeref_t wakeref;
> @@ -900,7 +900,7 @@ void _intel_edp_backlight_off(struct intel_dp *intel_dp)
> * Hook for controlling the panel power control backlight through the bl_power
> * sysfs attribute. Take care to handle multiple calls.
> */
> -void intel_edp_backlight_power(struct intel_connector *connector, bool enable)
> +void intel_pps_backlight_power(struct intel_connector *connector, bool enable)
> {
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> struct intel_dp *intel_dp = intel_attached_dp(connector);
> @@ -917,9 +917,9 @@ void intel_edp_backlight_power(struct intel_connector *connector, bool enable)
> enable ? "enable" : "disable");
>
> if (enable)
> - _intel_edp_backlight_on(intel_dp);
> + intel_pps_backlight_on(intel_dp);
> else
> - _intel_edp_backlight_off(intel_dp);
> + intel_pps_backlight_off(intel_dp);
> }
>
> static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
> index f44e6ce9e8c1..81e4e9fc3cf5 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.h
> +++ b/drivers/gpu/drm/i915/display/intel_pps.h
> @@ -23,9 +23,9 @@ intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wake
> for ((wf) = intel_pps_lock(dp); (wf); (wf) = intel_pps_unlock((dp), (wf)))
>
> void intel_dp_check_edp(struct intel_dp *intel_dp);
> -void _intel_edp_backlight_on(struct intel_dp *intel_dp);
> -void _intel_edp_backlight_off(struct intel_dp *intel_dp);
> -void intel_edp_backlight_power(struct intel_connector *connector, bool enable);
> +void intel_pps_backlight_on(struct intel_dp *intel_dp);
> +void intel_pps_backlight_off(struct intel_dp *intel_dp);
> +void intel_pps_backlight_power(struct intel_connector *connector, bool enable);
>
> bool edp_panel_vdd_on(struct intel_dp *intel_dp);
> void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-gfx] [PATCH 04/13] drm/i915/pps: rename intel_edp_panel_* to intel_pps_*
2020-12-22 14:49 ` [Intel-gfx] [PATCH 04/13] drm/i915/pps: rename intel_edp_panel_* to intel_pps_* Jani Nikula
@ 2020-12-29 6:15 ` Anshuman Gupta
2021-01-08 17:45 ` Jani Nikula
0 siblings, 1 reply; 35+ messages in thread
From: Anshuman Gupta @ 2020-12-29 6:15 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On 2020-12-22 at 20:19:44 +0530, Jani Nikula wrote:
> Follow the usual naming pattern for functions. We don't need to repeat
> "panel" here.
>
> Follow the usual naming pattern for functions.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++++----
> drivers/gpu/drm/i915/display/intel_dp.c | 10 +++++-----
> drivers/gpu/drm/i915/display/intel_pps.c | 18 +++++++++---------
> drivers/gpu/drm/i915/display/intel_pps.h | 11 +++++------
> 4 files changed, 23 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 9ddbe8b8730b..83300ee8c3fd 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3556,7 +3556,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
> */
>
> /* 2. Enable Panel Power if PPS is required */
> - intel_edp_panel_on(intel_dp);
> + intel_pps_on(intel_dp);
>
> /*
> * 3. For non-TBT Type-C ports, set FIA lane count
> @@ -3695,7 +3695,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
> crtc_state->port_clock,
> crtc_state->lane_count);
>
> - intel_edp_panel_on(intel_dp);
> + intel_pps_on(intel_dp);
>
> intel_ddi_clk_select(encoder, crtc_state);
>
> @@ -3937,8 +3937,8 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
> if (INTEL_GEN(dev_priv) >= 12)
> intel_ddi_disable_pipe_clock(old_crtc_state);
>
> - intel_edp_panel_vdd_on(intel_dp);
> - intel_edp_panel_off(intel_dp);
> + intel_pps_vdd_on(intel_dp);
> + intel_pps_off(intel_dp);
>
> if (!intel_phy_is_tc(dev_priv, phy) ||
> dig_port->tc_mode != TC_PORT_TBT_ALT)
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 9813fb7e109c..2052ee228077 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2947,10 +2947,10 @@ static void intel_disable_dp(struct intel_atomic_state *state,
>
> /* Make sure the panel is off before trying to change the mode. But also
> * ensure that we have vdd while we switch off the panel. */
> - intel_edp_panel_vdd_on(intel_dp);
> + intel_pps_vdd_on(intel_dp);
> intel_edp_backlight_off(old_conn_state);
> intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
> - intel_edp_panel_off(intel_dp);
> + intel_pps_off(intel_dp);
> }
>
> static void g4x_disable_dp(struct intel_atomic_state *state,
> @@ -5899,7 +5899,7 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder)
> * something nasty with it.
> */
> intel_dp_pps_init(intel_dp);
> - intel_edp_panel_vdd_sanitize(intel_dp);
> + intel_pps_vdd_sanitize(intel_dp);
> }
> }
> }
> @@ -6073,7 +6073,7 @@ intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
> struct intel_dp *intel_dp = &dig_port->dp;
>
> if (dig_port->base.type == INTEL_OUTPUT_EDP &&
> - (long_hpd || !intel_edp_have_power(intel_dp))) {
> + (long_hpd || !intel_pps_have_power(intel_dp))) {
> /*
> * vdd off can generate a long/short pulse on eDP which
> * would require vdd on to handle it, and thus we
> @@ -6631,7 +6631,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
> with_intel_pps_lock(intel_dp, wakeref) {
> intel_dp_init_panel_power_timestamps(intel_dp);
> intel_dp_pps_init(intel_dp);
> - intel_edp_panel_vdd_sanitize(intel_dp);
> + intel_pps_vdd_sanitize(intel_dp);
> }
>
> /* Cache DPCD and EDID for edp. */
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> index 0edda87dee94..1f8ea3c41440 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -561,7 +561,7 @@ static u32 ilk_get_pp_control(struct intel_dp *intel_dp)
> /*
> * Must be paired with edp_panel_vdd_off().
> * Must hold pps_mutex around the whole on/off sequence.
> - * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
> + * Can be nested with intel_pps_vdd_{on,off}() calls.
> */
> bool edp_panel_vdd_on(struct intel_dp *intel_dp)
> {
> @@ -619,13 +619,13 @@ bool edp_panel_vdd_on(struct intel_dp *intel_dp)
> }
>
> /*
> - * Must be paired with intel_edp_panel_vdd_off() or
> - * intel_edp_panel_off().
> + * Must be paired with intel_pps_vdd_off() or
IMHO can we change the comment, there is no function with name intel_pps_vdd_off()
Thanks,
Anshuman.
> + * intel_pps_off().
> * Nested calls to these functions are not allowed since
> * we drop the lock. Caller must use some higher level
> * locking to prevent nested calls from other threads.
> */
> -void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
> +void intel_pps_vdd_on(struct intel_dp *intel_dp)
> {
> intel_wakeref_t wakeref;
> bool vdd;
> @@ -711,7 +711,7 @@ static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
> /*
> * Must be paired with edp_panel_vdd_on().
> * Must hold pps_mutex around the whole on/off sequence.
> - * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
> + * Can be nested with intel_pps_vdd_{on,off}() calls.
> */
> void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
> {
> @@ -783,7 +783,7 @@ void edp_panel_on(struct intel_dp *intel_dp)
> }
> }
>
> -void intel_edp_panel_on(struct intel_dp *intel_dp)
> +void intel_pps_on(struct intel_dp *intel_dp)
> {
> intel_wakeref_t wakeref;
>
> @@ -835,7 +835,7 @@ void edp_panel_off(struct intel_dp *intel_dp)
> fetch_and_zero(&intel_dp->vdd_wakeref));
> }
>
> -void intel_edp_panel_off(struct intel_dp *intel_dp)
> +void intel_pps_off(struct intel_dp *intel_dp)
> {
> intel_wakeref_t wakeref;
>
> @@ -1028,7 +1028,7 @@ void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
> intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
> }
>
> -void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
> +void intel_pps_vdd_sanitize(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> @@ -1053,7 +1053,7 @@ void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
> edp_panel_vdd_schedule_off(intel_dp);
> }
>
> -bool intel_edp_have_power(struct intel_dp *intel_dp)
> +bool intel_pps_have_power(struct intel_dp *intel_dp)
> {
> intel_wakeref_t wakeref;
> bool have_power = false;
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
> index 81e4e9fc3cf5..69f670678d0e 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.h
> +++ b/drivers/gpu/drm/i915/display/intel_pps.h
> @@ -34,12 +34,11 @@ void edp_panel_on(struct intel_dp *intel_dp);
> void edp_panel_off(struct intel_dp *intel_dp);
> void edp_panel_vdd_work(struct work_struct *__work);
>
> -void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
> -void intel_edp_panel_on(struct intel_dp *intel_dp);
> -void intel_edp_panel_off(struct intel_dp *intel_dp);
> -bool intel_edp_have_power(struct intel_dp *intel_dp);
> -
> -void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp);
> +void intel_pps_vdd_sanitize(struct intel_dp *intel_dp);
> +void intel_pps_vdd_on(struct intel_dp *intel_dp);
> +void intel_pps_on(struct intel_dp *intel_dp);
> +void intel_pps_off(struct intel_dp *intel_dp);
> +bool intel_pps_have_power(struct intel_dp *intel_dp);
>
> void wait_panel_power_cycle(struct intel_dp *intel_dp);
>
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-gfx] [PATCH 05/13] drm/i915/pps: rename edp_panel_* to intel_pps_*_unlocked
2020-12-22 14:49 ` [Intel-gfx] [PATCH 05/13] drm/i915/pps: rename edp_panel_* to intel_pps_*_unlocked Jani Nikula
@ 2020-12-29 6:35 ` Anshuman Gupta
0 siblings, 0 replies; 35+ messages in thread
From: Anshuman Gupta @ 2020-12-29 6:35 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On 2020-12-22 at 20:19:45 +0530, Jani Nikula wrote:
> Follow the usual naming pattern for functions, both for the prefix and
> the _unlocked suffix for functions that expect the lock to be held when
IMHO referring * pps lock * would be good in commit log.
Thanks,
Anshuman.
> calling.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 16 +++++++--------
> drivers/gpu/drm/i915/display/intel_pps.c | 26 ++++++++++++------------
> drivers/gpu/drm/i915/display/intel_pps.h | 10 ++++-----
> 3 files changed, 26 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 2052ee228077..f2794cc4292a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1038,7 +1038,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> * to turn it off. But for eg. i2c-dev access we need to turn it on/off
> * ourselves.
> */
> - vdd = edp_panel_vdd_on(intel_dp);
> + vdd = intel_pps_vdd_on_unlocked(intel_dp);
>
> /* dp aux is extremely sensitive to irq latency, hence request the
> * lowest possible wakeup latency and so prevent the cpu from going into
> @@ -1180,7 +1180,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
>
> if (vdd)
> - edp_panel_vdd_off(intel_dp, false);
> + intel_pps_vdd_off_unlocked(intel_dp, false);
>
> intel_pps_unlock(intel_dp, pps_wakeref);
> intel_display_power_put_async(i915, aux_domain, aux_wakeref);
> @@ -3159,9 +3159,9 @@ static void intel_enable_dp(struct intel_atomic_state *state,
>
> intel_dp_enable_port(intel_dp, pipe_config);
>
> - edp_panel_vdd_on(intel_dp);
> - edp_panel_on(intel_dp);
> - edp_panel_vdd_off(intel_dp, true);
> + intel_pps_vdd_on_unlocked(intel_dp);
> + intel_pps_on_unlocked(intel_dp);
> + intel_pps_vdd_off_unlocked(intel_dp, true);
> }
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> @@ -5818,7 +5818,7 @@ void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
> * Make sure vdd is actually turned off here.
> */
> with_intel_pps_lock(intel_dp, wakeref)
> - edp_panel_vdd_off_sync(intel_dp);
> + intel_pps_vdd_off_sync_unlocked(intel_dp);
> }
>
> intel_dp_aux_fini(intel_dp);
> @@ -5846,7 +5846,7 @@ void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
> */
> cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
> with_intel_pps_lock(intel_dp, wakeref)
> - edp_panel_vdd_off_sync(intel_dp);
> + intel_pps_vdd_off_sync_unlocked(intel_dp);
> }
>
> void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
> @@ -6706,7 +6706,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
> * Make sure vdd is actually turned off here.
> */
> with_intel_pps_lock(intel_dp, wakeref)
> - edp_panel_vdd_off_sync(intel_dp);
> + intel_pps_vdd_off_sync_unlocked(intel_dp);
>
> return false;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> index 1f8ea3c41440..01c9e69f4e3a 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -559,11 +559,11 @@ static u32 ilk_get_pp_control(struct intel_dp *intel_dp)
> }
>
> /*
> - * Must be paired with edp_panel_vdd_off().
> + * Must be paired with intel_pps_vdd_off_unlocked().
> * Must hold pps_mutex around the whole on/off sequence.
> * Can be nested with intel_pps_vdd_{on,off}() calls.
> */
> -bool edp_panel_vdd_on(struct intel_dp *intel_dp)
> +bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> @@ -635,13 +635,13 @@ void intel_pps_vdd_on(struct intel_dp *intel_dp)
>
> vdd = false;
> with_intel_pps_lock(intel_dp, wakeref)
> - vdd = edp_panel_vdd_on(intel_dp);
> + vdd = intel_pps_vdd_on_unlocked(intel_dp);
> I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",
> dp_to_dig_port(intel_dp)->base.base.base.id,
> dp_to_dig_port(intel_dp)->base.base.name);
> }
>
> -void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
> +void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> struct intel_digital_port *dig_port =
> @@ -691,7 +691,7 @@ void edp_panel_vdd_work(struct work_struct *__work)
>
> with_intel_pps_lock(intel_dp, wakeref) {
> if (!intel_dp->want_panel_vdd)
> - edp_panel_vdd_off_sync(intel_dp);
> + intel_pps_vdd_off_sync_unlocked(intel_dp);
> }
> }
>
> @@ -713,7 +713,7 @@ static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
> * Must hold pps_mutex around the whole on/off sequence.
> * Can be nested with intel_pps_vdd_{on,off}() calls.
> */
> -void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
> +void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> @@ -729,12 +729,12 @@ void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
> intel_dp->want_panel_vdd = false;
>
> if (sync)
> - edp_panel_vdd_off_sync(intel_dp);
> + intel_pps_vdd_off_sync_unlocked(intel_dp);
> else
> edp_panel_vdd_schedule_off(intel_dp);
> }
>
> -void edp_panel_on(struct intel_dp *intel_dp)
> +void intel_pps_on_unlocked(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> u32 pp;
> @@ -791,10 +791,10 @@ void intel_pps_on(struct intel_dp *intel_dp)
> return;
>
> with_intel_pps_lock(intel_dp, wakeref)
> - edp_panel_on(intel_dp);
> + intel_pps_on_unlocked(intel_dp);
> }
>
> -void edp_panel_off(struct intel_dp *intel_dp)
> +void intel_pps_off_unlocked(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> @@ -843,7 +843,7 @@ void intel_pps_off(struct intel_dp *intel_dp)
> return;
>
> with_intel_pps_lock(intel_dp, wakeref)
> - edp_panel_off(intel_dp);
> + intel_pps_off_unlocked(intel_dp);
> }
>
> /* Enable backlight in the panel power control. */
> @@ -934,7 +934,7 @@ static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
> if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B))
> return;
>
> - edp_panel_vdd_off_sync(intel_dp);
> + intel_pps_vdd_off_sync_unlocked(intel_dp);
>
> /*
> * VLV seems to get confused when multiple power sequencers
> @@ -1249,7 +1249,7 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
> * hooked up to any port. This would mess up the
> * power domain tracking the first time we pick
> * one of these power sequencers for use since
> - * edp_panel_vdd_on() would notice that the VDD was
> + * intel_pps_vdd_on_unlocked() would notice that the VDD was
> * already on and therefore wouldn't grab the power
> * domain reference. Disable VDD first to avoid this.
> * This also avoids spuriously turning the VDD on as
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
> index 69f670678d0e..e7f0473be9a7 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.h
> +++ b/drivers/gpu/drm/i915/display/intel_pps.h
> @@ -27,11 +27,11 @@ void intel_pps_backlight_on(struct intel_dp *intel_dp);
> void intel_pps_backlight_off(struct intel_dp *intel_dp);
> void intel_pps_backlight_power(struct intel_connector *connector, bool enable);
>
> -bool edp_panel_vdd_on(struct intel_dp *intel_dp);
> -void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
> -void edp_panel_vdd_off_sync(struct intel_dp *intel_dp);
> -void edp_panel_on(struct intel_dp *intel_dp);
> -void edp_panel_off(struct intel_dp *intel_dp);
> +bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp);
> +void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);
> +void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp);
> +void intel_pps_on_unlocked(struct intel_dp *intel_dp);
> +void intel_pps_off_unlocked(struct intel_dp *intel_dp);
> void edp_panel_vdd_work(struct work_struct *__work);
>
> void intel_pps_vdd_sanitize(struct intel_dp *intel_dp);
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-gfx] [PATCH 06/13] drm/i915/pps: abstract intel_pps_vdd_off_sync
2020-12-22 14:49 ` [Intel-gfx] [PATCH 06/13] drm/i915/pps: abstract intel_pps_vdd_off_sync Jani Nikula
@ 2020-12-29 6:47 ` Anshuman Gupta
2021-01-08 17:46 ` Jani Nikula
0 siblings, 1 reply; 35+ messages in thread
From: Anshuman Gupta @ 2020-12-29 6:47 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On 2020-12-22 at 20:19:46 +0530, Jani Nikula wrote:
> Add a locked version of intel_pps_vdd_off_sync_unlocked() that does
> everything the callers expect it to.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 31 +++---------------------
> drivers/gpu/drm/i915/display/intel_pps.c | 17 ++++++++++++-
> drivers/gpu/drm/i915/display/intel_pps.h | 2 +-
> 3 files changed, 20 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index f2794cc4292a..1a34c9351c30 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5809,17 +5809,8 @@ void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
> struct intel_dp *intel_dp = &dig_port->dp;
>
> intel_dp_mst_encoder_cleanup(dig_port);
> - if (intel_dp_is_edp(intel_dp)) {
> - intel_wakeref_t wakeref;
>
> - cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
> - /*
> - * vdd might still be enabled do to the delayed vdd off.
> - * Make sure vdd is actually turned off here.
> - */
> - with_intel_pps_lock(intel_dp, wakeref)
> - intel_pps_vdd_off_sync_unlocked(intel_dp);
> - }
> + intel_pps_vdd_off_sync(intel_dp);
>
> intel_dp_aux_fini(intel_dp);
> }
> @@ -5835,18 +5826,8 @@ static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
> void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
> {
> struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
> - intel_wakeref_t wakeref;
> -
> - if (!intel_dp_is_edp(intel_dp))
> - return;
>
> - /*
> - * vdd might still be enabled do to the delayed vdd off.
> - * Make sure vdd is actually turned off here.
> - */
> - cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
> - with_intel_pps_lock(intel_dp, wakeref)
> - intel_pps_vdd_off_sync_unlocked(intel_dp);
> + intel_pps_vdd_off_sync(intel_dp);
> }
>
> void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
> @@ -6700,13 +6681,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
> return true;
>
> out_vdd_off:
> - cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
> - /*
> - * vdd might still be enabled do to the delayed vdd off.
> - * Make sure vdd is actually turned off here.
> - */
> - with_intel_pps_lock(intel_dp, wakeref)
> - intel_pps_vdd_off_sync_unlocked(intel_dp);
> + intel_pps_vdd_off_sync(intel_dp);
>
> return false;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> index 01c9e69f4e3a..acd6d0092bc6 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -641,7 +641,7 @@ void intel_pps_vdd_on(struct intel_dp *intel_dp)
> dp_to_dig_port(intel_dp)->base.base.name);
> }
>
> -void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
> +static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> struct intel_digital_port *dig_port =
> @@ -682,6 +682,21 @@ void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
> fetch_and_zero(&intel_dp->vdd_wakeref));
> }
>
> +void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
> +{
> + intel_wakeref_t wakeref;
> + if (!intel_dp_is_edp(intel_dp))
> + return;
> +
> + cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
> + /*
> + * vdd might still be enabled do to the delayed vdd off.
I belive there is a typo here "do -> due"
Thanks,
Anshuman.
> + * Make sure vdd is actually turned off here.
> + */
> + with_intel_pps_lock(intel_dp, wakeref)
> + intel_pps_vdd_off_sync_unlocked(intel_dp);
> +}
> +
> void edp_panel_vdd_work(struct work_struct *__work)
> {
> struct intel_dp *intel_dp =
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
> index e7f0473be9a7..3cab183658c6 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.h
> +++ b/drivers/gpu/drm/i915/display/intel_pps.h
> @@ -29,7 +29,6 @@ void intel_pps_backlight_power(struct intel_connector *connector, bool enable);
>
> bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp);
> void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);
> -void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp);
> void intel_pps_on_unlocked(struct intel_dp *intel_dp);
> void intel_pps_off_unlocked(struct intel_dp *intel_dp);
> void edp_panel_vdd_work(struct work_struct *__work);
> @@ -38,6 +37,7 @@ void intel_pps_vdd_sanitize(struct intel_dp *intel_dp);
> void intel_pps_vdd_on(struct intel_dp *intel_dp);
> void intel_pps_on(struct intel_dp *intel_dp);
> void intel_pps_off(struct intel_dp *intel_dp);
> +void intel_pps_vdd_off_sync(struct intel_dp *intel_dp);
> bool intel_pps_have_power(struct intel_dp *intel_dp);
>
> void wait_panel_power_cycle(struct intel_dp *intel_dp);
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-gfx] [PATCH 07/13] drm/i915/pps: add higher level intel_pps_init() call
2020-12-22 14:49 ` [Intel-gfx] [PATCH 07/13] drm/i915/pps: add higher level intel_pps_init() call Jani Nikula
@ 2020-12-29 6:53 ` Anshuman Gupta
0 siblings, 0 replies; 35+ messages in thread
From: Anshuman Gupta @ 2020-12-29 6:53 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On 2020-12-22 at 20:19:47 +0530, Jani Nikula wrote:
> Add a new init call to be called only once, unlike some of the other
> various init calls. This lets us hide more functions within intel_pps.c.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Looks good to me.
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 9 +--------
> drivers/gpu/drm/i915/display/intel_pps.c | 17 +++++++++++++++--
> drivers/gpu/drm/i915/display/intel_pps.h | 3 +--
> 3 files changed, 17 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 1a34c9351c30..de2642d5be3b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6586,14 +6586,11 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
> struct drm_display_mode *downclock_mode = NULL;
> bool has_dpcd;
> enum pipe pipe = INVALID_PIPE;
> - intel_wakeref_t wakeref;
> struct edid *edid;
>
> if (!intel_dp_is_edp(intel_dp))
> return true;
>
> - INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
> -
> /*
> * On IBX/CPT we may get here with LVDS already registered. Since the
> * driver uses the only internal power sequencer available for both
> @@ -6609,11 +6606,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
> return false;
> }
>
> - with_intel_pps_lock(intel_dp, wakeref) {
> - intel_dp_init_panel_power_timestamps(intel_dp);
> - intel_dp_pps_init(intel_dp);
> - intel_pps_vdd_sanitize(intel_dp);
> - }
> + intel_pps_init(intel_dp);
>
> /* Cache DPCD and EDID for edp. */
> has_dpcd = intel_edp_init_dpcd(intel_dp);
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> index acd6d0092bc6..651c79ce4bdd 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -697,7 +697,7 @@ void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
> intel_pps_vdd_off_sync_unlocked(intel_dp);
> }
>
> -void edp_panel_vdd_work(struct work_struct *__work)
> +static void edp_panel_vdd_work(struct work_struct *__work)
> {
> struct intel_dp *intel_dp =
> container_of(to_delayed_work(__work),
> @@ -1081,7 +1081,7 @@ bool intel_pps_have_power(struct intel_dp *intel_dp)
> return have_power;
> }
>
> -void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> +static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> {
> intel_dp->panel_power_off_time = ktime_get_boottime();
> intel_dp->last_power_on = jiffies;
> @@ -1351,3 +1351,16 @@ void intel_dp_pps_init(struct intel_dp *intel_dp)
> intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
> }
> }
> +
> +void intel_pps_init(struct intel_dp *intel_dp)
> +{
> + intel_wakeref_t wakeref;
> +
> + INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
> +
> + with_intel_pps_lock(intel_dp, wakeref) {
> + intel_dp_init_panel_power_timestamps(intel_dp);
> + intel_dp_pps_init(intel_dp);
> + intel_pps_vdd_sanitize(intel_dp);
> + }
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
> index 3cab183658c6..53c0fafd1440 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.h
> +++ b/drivers/gpu/drm/i915/display/intel_pps.h
> @@ -31,7 +31,6 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp);
> void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);
> void intel_pps_on_unlocked(struct intel_dp *intel_dp);
> void intel_pps_off_unlocked(struct intel_dp *intel_dp);
> -void edp_panel_vdd_work(struct work_struct *__work);
>
> void intel_pps_vdd_sanitize(struct intel_dp *intel_dp);
> void intel_pps_vdd_on(struct intel_dp *intel_dp);
> @@ -42,9 +41,9 @@ bool intel_pps_have_power(struct intel_dp *intel_dp);
>
> void wait_panel_power_cycle(struct intel_dp *intel_dp);
>
> +void intel_pps_init(struct intel_dp *intel_dp);
> void intel_dp_pps_init(struct intel_dp *intel_dp);
> void intel_power_sequencer_reset(struct drm_i915_private *i915);
> -void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp);
>
> void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-gfx] [PATCH 08/13] drm/i915/pps: abstract intel_pps_reinit()
2020-12-22 14:49 ` [Intel-gfx] [PATCH 08/13] drm/i915/pps: abstract intel_pps_reinit() Jani Nikula
@ 2020-12-29 6:59 ` Anshuman Gupta
0 siblings, 0 replies; 35+ messages in thread
From: Anshuman Gupta @ 2020-12-29 6:59 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On 2020-12-22 at 20:19:48 +0530, Jani Nikula wrote:
> Add a "reinit" call to hide some more pps functions, and clean up the
> callers. A minor functional change is not holding the pps lock across
> the whole operation in intel_dp_encoder_reset, but instead doing it in
> two steps.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Looks good to me.
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 20 +++++---------------
> drivers/gpu/drm/i915/display/intel_pps.c | 21 +++++++++++++++++++--
> drivers/gpu/drm/i915/display/intel_pps.h | 3 +--
> 3 files changed, 25 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index de2642d5be3b..334ba1775cd3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5859,30 +5859,20 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->dev);
> struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
> - intel_wakeref_t wakeref;
>
> if (!HAS_DDI(dev_priv))
> intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
>
> intel_dp->reset_link_params = true;
>
> - if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
> - !intel_dp_is_edp(intel_dp))
> - return;
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> + intel_wakeref_t wakeref;
>
> - with_intel_pps_lock(intel_dp, wakeref) {
> - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> + with_intel_pps_lock(intel_dp, wakeref)
> intel_dp->active_pipe = vlv_active_pipe(intel_dp);
> -
> - if (intel_dp_is_edp(intel_dp)) {
> - /*
> - * Reinit the power sequencer, in case BIOS did
> - * something nasty with it.
> - */
> - intel_dp_pps_init(intel_dp);
> - intel_pps_vdd_sanitize(intel_dp);
> - }
> }
> +
> + intel_pps_reinit(intel_dp);
> }
>
> static int intel_modeset_tile_group(struct intel_atomic_state *state,
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> index 651c79ce4bdd..3e62d1450682 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -1043,7 +1043,7 @@ void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
> intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
> }
>
> -void intel_pps_vdd_sanitize(struct intel_dp *intel_dp)
> +static void intel_pps_vdd_sanitize(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> @@ -1340,7 +1340,7 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
> (intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
> }
>
> -void intel_dp_pps_init(struct intel_dp *intel_dp)
> +static void intel_dp_pps_init(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> @@ -1352,6 +1352,23 @@ void intel_dp_pps_init(struct intel_dp *intel_dp)
> }
> }
>
> +void intel_pps_reinit(struct intel_dp *intel_dp)
> +{
> + intel_wakeref_t wakeref;
> +
> + if (!intel_dp_is_edp(intel_dp))
> + return;
> +
> + with_intel_pps_lock(intel_dp, wakeref) {
> + /*
> + * Reinit the power sequencer, in case BIOS did something nasty
> + * with it.
> + */
> + intel_dp_pps_init(intel_dp);
> + intel_pps_vdd_sanitize(intel_dp);
> + }
> +}
> +
> void intel_pps_init(struct intel_dp *intel_dp)
> {
> intel_wakeref_t wakeref;
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
> index 53c0fafd1440..4780b59a59df 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.h
> +++ b/drivers/gpu/drm/i915/display/intel_pps.h
> @@ -32,7 +32,6 @@ void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);
> void intel_pps_on_unlocked(struct intel_dp *intel_dp);
> void intel_pps_off_unlocked(struct intel_dp *intel_dp);
>
> -void intel_pps_vdd_sanitize(struct intel_dp *intel_dp);
> void intel_pps_vdd_on(struct intel_dp *intel_dp);
> void intel_pps_on(struct intel_dp *intel_dp);
> void intel_pps_off(struct intel_dp *intel_dp);
> @@ -42,7 +41,7 @@ bool intel_pps_have_power(struct intel_dp *intel_dp);
> void wait_panel_power_cycle(struct intel_dp *intel_dp);
>
> void intel_pps_init(struct intel_dp *intel_dp);
> -void intel_dp_pps_init(struct intel_dp *intel_dp);
> +void intel_pps_reinit(struct intel_dp *intel_dp);
> void intel_power_sequencer_reset(struct drm_i915_private *i915);
>
> void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-gfx] [PATCH 09/13] drm/i915/pps: rename intel_dp_check_edp to intel_pps_check_power_unlocked
2020-12-22 14:49 ` [Intel-gfx] [PATCH 09/13] drm/i915/pps: rename intel_dp_check_edp to intel_pps_check_power_unlocked Jani Nikula
@ 2020-12-29 7:04 ` Anshuman Gupta
2021-01-08 10:33 ` Jani Nikula
0 siblings, 1 reply; 35+ messages in thread
From: Anshuman Gupta @ 2020-12-29 7:04 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On 2020-12-22 at 20:19:49 +0530, Jani Nikula wrote:
> Follow the usual naming pattern for functions.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> drivers/gpu/drm/i915/display/intel_pps.c | 2 +-
> drivers/gpu/drm/i915/display/intel_pps.h | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 334ba1775cd3..65406d4ccdbe 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1046,7 +1046,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> */
> cpu_latency_qos_update_request(&i915->pm_qos, 0);
>
> - intel_dp_check_edp(intel_dp);
> + intel_pps_check_power_unlocked(intel_dp);
>
> /* Try to wait for any previous AUX channel activity */
> for (try = 0; try < 3; try++) {
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> index 3e62d1450682..dfd6722bc40e 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -431,7 +431,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
> return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
> }
>
> -void intel_dp_check_edp(struct intel_dp *intel_dp)
> +void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
IMHO comment to take pps_lock would be useful here.
Thanks,
Anshuman.
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
> index 4780b59a59df..8dda282abd42 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.h
> +++ b/drivers/gpu/drm/i915/display/intel_pps.h
> @@ -22,7 +22,6 @@ intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wake
> #define with_intel_pps_lock(dp, wf) \
> for ((wf) = intel_pps_lock(dp); (wf); (wf) = intel_pps_unlock((dp), (wf)))
>
> -void intel_dp_check_edp(struct intel_dp *intel_dp);
> void intel_pps_backlight_on(struct intel_dp *intel_dp);
> void intel_pps_backlight_off(struct intel_dp *intel_dp);
> void intel_pps_backlight_power(struct intel_connector *connector, bool enable);
> @@ -31,6 +30,7 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp);
> void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);
> void intel_pps_on_unlocked(struct intel_dp *intel_dp);
> void intel_pps_off_unlocked(struct intel_dp *intel_dp);
> +void intel_pps_check_power_unlocked(struct intel_dp *intel_dp);
>
> void intel_pps_vdd_on(struct intel_dp *intel_dp);
> void intel_pps_on(struct intel_dp *intel_dp);
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-gfx] [PATCH 10/13] drm/i915/pps: rename intel_power_sequencer_reset to intel_pps_reset_all
2020-12-22 14:49 ` [Intel-gfx] [PATCH 10/13] drm/i915/pps: rename intel_power_sequencer_reset to intel_pps_reset_all Jani Nikula
@ 2020-12-29 7:53 ` Anshuman Gupta
0 siblings, 0 replies; 35+ messages in thread
From: Anshuman Gupta @ 2020-12-29 7:53 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On 2020-12-22 at 20:19:50 +0530, Jani Nikula wrote:
> Follow the usual naming pattern for functions. "reset all" because it
> iterates over all DP encoders.
Looks good to me.
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 4 ++--
> drivers/gpu/drm/i915/display/intel_pps.c | 5 ++---
> drivers/gpu/drm/i915/display/intel_pps.h | 2 +-
> 3 files changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index a11bd8213df4..c11c37c65d86 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -936,7 +936,7 @@ static void bxt_enable_dc9(struct drm_i915_private *dev_priv)
> * because PPS registers are always on.
> */
> if (!HAS_PCH_SPLIT(dev_priv))
> - intel_power_sequencer_reset(dev_priv);
> + intel_pps_reset_all(dev_priv);
> gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
> }
>
> @@ -1446,7 +1446,7 @@ static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
> /* make sure we're done processing display irqs */
> intel_synchronize_irq(dev_priv);
>
> - intel_power_sequencer_reset(dev_priv);
> + intel_pps_reset_all(dev_priv);
>
> /* Prevent us from re-enabling polling on accident in late suspend */
> if (!dev_priv->drm.dev->power.is_suspended)
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> index dfd6722bc40e..ceb6de9e7aff 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -22,8 +22,7 @@ intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp)
> intel_wakeref_t wakeref;
>
> /*
> - * See intel_power_sequencer_reset() why we need
> - * a power domain reference here.
> + * See intel_pps_reset_all() why we need a power domain reference here.
> */
> wakeref = intel_display_power_get(dev_priv,
> intel_aux_power_domain(dp_to_dig_port(intel_dp)));
> @@ -316,7 +315,7 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
> intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
> }
>
> -void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
> +void intel_pps_reset_all(struct drm_i915_private *dev_priv)
> {
> struct intel_encoder *encoder;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
> index 8dda282abd42..451d5125b2b7 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.h
> +++ b/drivers/gpu/drm/i915/display/intel_pps.h
> @@ -42,7 +42,7 @@ void wait_panel_power_cycle(struct intel_dp *intel_dp);
>
> void intel_pps_init(struct intel_dp *intel_dp);
> void intel_pps_reinit(struct intel_dp *intel_dp);
> -void intel_power_sequencer_reset(struct drm_i915_private *i915);
> +void intel_pps_reset_all(struct drm_i915_private *i915);
>
> void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-gfx] [PATCH 11/13] drm/i915/pps: add locked intel_pps_wait_power_cycle
2020-12-22 14:49 ` [Intel-gfx] [PATCH 11/13] drm/i915/pps: add locked intel_pps_wait_power_cycle Jani Nikula
@ 2020-12-29 7:59 ` Anshuman Gupta
0 siblings, 0 replies; 35+ messages in thread
From: Anshuman Gupta @ 2020-12-29 7:59 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On 2020-12-22 at 20:19:51 +0530, Jani Nikula wrote:
> Prefer keeping the unlocked variants hidden if possible.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 7 +------
> drivers/gpu/drm/i915/display/intel_pps.c | 13 ++++++++++++-
> drivers/gpu/drm/i915/display/intel_pps.h | 3 +--
> 3 files changed, 14 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 65406d4ccdbe..bc3a447f5992 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5833,13 +5833,8 @@ void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
> void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
> {
> struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
> - intel_wakeref_t wakeref;
> -
> - if (!intel_dp_is_edp(intel_dp))
> - return;
>
> - with_intel_pps_lock(intel_dp, wakeref)
> - wait_panel_power_cycle(intel_dp);
> + intel_pps_wait_power_cycle(intel_dp);
> }
>
> static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> index ceb6de9e7aff..ceb74967f2b4 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -503,7 +503,7 @@ static void wait_panel_off(struct intel_dp *intel_dp)
> wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
> }
>
> -void wait_panel_power_cycle(struct intel_dp *intel_dp)
> +static void wait_panel_power_cycle(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> ktime_t panel_power_on_time;
> @@ -525,6 +525,17 @@ void wait_panel_power_cycle(struct intel_dp *intel_dp)
> wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
> }
>
> +void intel_pps_wait_power_cycle(struct intel_dp *intel_dp)
> +{
> + intel_wakeref_t wakeref;
> +
> + if (!intel_dp_is_edp(intel_dp))
> + return;
> +
> + with_intel_pps_lock(intel_dp, wakeref)
> + wait_panel_power_cycle(intel_dp);
> +}
> +
> static void wait_backlight_on(struct intel_dp *intel_dp)
> {
> wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
> index 451d5125b2b7..c8766b777501 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.h
> +++ b/drivers/gpu/drm/i915/display/intel_pps.h
> @@ -37,8 +37,7 @@ void intel_pps_on(struct intel_dp *intel_dp);
> void intel_pps_off(struct intel_dp *intel_dp);
> void intel_pps_vdd_off_sync(struct intel_dp *intel_dp);
> bool intel_pps_have_power(struct intel_dp *intel_dp);
> -
> -void wait_panel_power_cycle(struct intel_dp *intel_dp);
> +void intel_pps_wait_power_cycle(struct intel_dp *intel_dp);
>
> void intel_pps_init(struct intel_dp *intel_dp);
> void intel_pps_reinit(struct intel_dp *intel_dp);
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-gfx] [PATCH 12/13] drm/i915/pps: rename vlv_init_panel_power_sequencer to vlv_pps_init
2020-12-22 14:49 ` [Intel-gfx] [PATCH 12/13] drm/i915/pps: rename vlv_init_panel_power_sequencer to vlv_pps_init Jani Nikula
@ 2020-12-29 8:01 ` Anshuman Gupta
0 siblings, 0 replies; 35+ messages in thread
From: Anshuman Gupta @ 2020-12-29 8:01 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On 2020-12-22 at 20:19:52 +0530, Jani Nikula wrote:
> This function is a bit of an outlier, but try to change to a name that
> is more in line with the rest of the intel_pps functions.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> drivers/gpu/drm/i915/display/intel_pps.c | 4 ++--
> drivers/gpu/drm/i915/display/intel_pps.h | 4 ++--
> 3 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index bc3a447f5992..c49ada31363b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3155,7 +3155,7 @@ static void intel_enable_dp(struct intel_atomic_state *state,
>
> with_intel_pps_lock(intel_dp, wakeref) {
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> - vlv_init_panel_power_sequencer(encoder, pipe_config);
> + vlv_pps_init(encoder, pipe_config);
>
> intel_dp_enable_port(intel_dp, pipe_config);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> index ceb74967f2b4..492abf372167 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -1008,8 +1008,8 @@ static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
> }
> }
>
> -void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
> - const struct intel_crtc_state *crtc_state)
> +void vlv_pps_init(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
> index c8766b777501..d9cd57b5b828 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.h
> +++ b/drivers/gpu/drm/i915/display/intel_pps.h
> @@ -43,7 +43,7 @@ void intel_pps_init(struct intel_dp *intel_dp);
> void intel_pps_reinit(struct intel_dp *intel_dp);
> void intel_pps_reset_all(struct drm_i915_private *i915);
>
> -void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
> - const struct intel_crtc_state *crtc_state);
> +void vlv_pps_init(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state);
>
> #endif /* __INTEL_PPS_H__ */
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-gfx] [PATCH 01/13] drm/i915/pps: abstract panel power sequencer from intel_dp.c
2020-12-28 11:22 ` Gupta, Anshuman
@ 2021-01-04 14:46 ` Jani Nikula
2021-01-08 17:44 ` Jani Nikula
0 siblings, 1 reply; 35+ messages in thread
From: Jani Nikula @ 2021-01-04 14:46 UTC (permalink / raw)
To: Gupta, Anshuman, intel-gfx
On Mon, 28 Dec 2020, "Gupta, Anshuman" <anshuman.gupta@intel.com> wrote:
>> -----Original Message-----
>> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
>> Nikula
>> Sent: Tuesday, December 22, 2020 8:20 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani <jani.nikula@intel.com>
>> Subject: [Intel-gfx] [PATCH 01/13] drm/i915/pps: abstract panel power
>> sequencer from intel_dp.c
>>
>> In a long overdue refactoring, split out all panel sequencer code from
>> intel_dp.c to new intel_pps.[ch].
>>
>> The first part is mostly just code movement as-is, without cleanups.
>>
>> We need to add a vlv_get_dpll() helper to get at the vlv/chv dpll from
>> pps code.
> IMHO functions intel_dp_init_panel_power_sequencer, intel_dp_init_panel_power_sequencer_registers,
> intel_dp_pps_init suits a intel_edp_* prefix.
This patch just moves code. The rename would be a separate change on
top. Possibly with intel_pps prefix instead because they're not so much
about dp or edp as about pps.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-gfx] [PATCH 09/13] drm/i915/pps: rename intel_dp_check_edp to intel_pps_check_power_unlocked
2020-12-29 7:04 ` Anshuman Gupta
@ 2021-01-08 10:33 ` Jani Nikula
2021-01-08 10:59 ` Gupta, Anshuman
0 siblings, 1 reply; 35+ messages in thread
From: Jani Nikula @ 2021-01-08 10:33 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
On Tue, 29 Dec 2020, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
> On 2020-12-22 at 20:19:49 +0530, Jani Nikula wrote:
>> Follow the usual naming pattern for functions.
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
>> drivers/gpu/drm/i915/display/intel_pps.c | 2 +-
>> drivers/gpu/drm/i915/display/intel_pps.h | 2 +-
>> 3 files changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 334ba1775cd3..65406d4ccdbe 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -1046,7 +1046,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>> */
>> cpu_latency_qos_update_request(&i915->pm_qos, 0);
>>
>> - intel_dp_check_edp(intel_dp);
>> + intel_pps_check_power_unlocked(intel_dp);
>>
>> /* Try to wait for any previous AUX channel activity */
>> for (try = 0; try < 3; try++) {
>> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
>> index 3e62d1450682..dfd6722bc40e 100644
>> --- a/drivers/gpu/drm/i915/display/intel_pps.c
>> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
>> @@ -431,7 +431,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
>> return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
>> }
>>
>> -void intel_dp_check_edp(struct intel_dp *intel_dp)
>> +void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
> IMHO comment to take pps_lock would be useful here.
Part of the point of this change is to name it _unlocked to highlight it
does not take the lock, i.e. you should be aware of locking. You see
this pattern all over the kernel. It's self-documenting code.
Moreover, after the edp check, the calls here have:
lockdep_assert_held(&dev_priv->pps_mutex);
which both documents the requirement as well as ensures the proper usage
in lockdep builds. I don't think a comment adds any value.
BR,
Jani.
> Thanks,
> Anshuman.
>> {
>> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
>> index 4780b59a59df..8dda282abd42 100644
>> --- a/drivers/gpu/drm/i915/display/intel_pps.h
>> +++ b/drivers/gpu/drm/i915/display/intel_pps.h
>> @@ -22,7 +22,6 @@ intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wake
>> #define with_intel_pps_lock(dp, wf) \
>> for ((wf) = intel_pps_lock(dp); (wf); (wf) = intel_pps_unlock((dp), (wf)))
>>
>> -void intel_dp_check_edp(struct intel_dp *intel_dp);
>> void intel_pps_backlight_on(struct intel_dp *intel_dp);
>> void intel_pps_backlight_off(struct intel_dp *intel_dp);
>> void intel_pps_backlight_power(struct intel_connector *connector, bool enable);
>> @@ -31,6 +30,7 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp);
>> void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);
>> void intel_pps_on_unlocked(struct intel_dp *intel_dp);
>> void intel_pps_off_unlocked(struct intel_dp *intel_dp);
>> +void intel_pps_check_power_unlocked(struct intel_dp *intel_dp);
>>
>> void intel_pps_vdd_on(struct intel_dp *intel_dp);
>> void intel_pps_on(struct intel_dp *intel_dp);
>> --
>> 2.20.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-gfx] [PATCH 09/13] drm/i915/pps: rename intel_dp_check_edp to intel_pps_check_power_unlocked
2021-01-08 10:33 ` Jani Nikula
@ 2021-01-08 10:59 ` Gupta, Anshuman
0 siblings, 0 replies; 35+ messages in thread
From: Gupta, Anshuman @ 2021-01-08 10:59 UTC (permalink / raw)
To: Nikula, Jani; +Cc: intel-gfx
> -----Original Message-----
> From: Jani Nikula <jani.nikula@intel.com>
> Sent: Friday, January 8, 2021 4:04 PM
> To: Gupta, Anshuman <anshuman.gupta@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 09/13] drm/i915/pps: rename
> intel_dp_check_edp to intel_pps_check_power_unlocked
>
> On Tue, 29 Dec 2020, Anshuman Gupta <anshuman.gupta@intel.com>
> wrote:
> > On 2020-12-22 at 20:19:49 +0530, Jani Nikula wrote:
> >> Follow the usual naming pattern for functions.
> >>
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> >> drivers/gpu/drm/i915/display/intel_pps.c | 2 +-
> >> drivers/gpu/drm/i915/display/intel_pps.h | 2 +-
> >> 3 files changed, 3 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> >> b/drivers/gpu/drm/i915/display/intel_dp.c
> >> index 334ba1775cd3..65406d4ccdbe 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> >> @@ -1046,7 +1046,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> >> */
> >> cpu_latency_qos_update_request(&i915->pm_qos, 0);
> >>
> >> - intel_dp_check_edp(intel_dp);
> >> + intel_pps_check_power_unlocked(intel_dp);
> >>
> >> /* Try to wait for any previous AUX channel activity */
> >> for (try = 0; try < 3; try++) {
> >> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
> >> b/drivers/gpu/drm/i915/display/intel_pps.c
> >> index 3e62d1450682..dfd6722bc40e 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> >> @@ -431,7 +431,7 @@ static bool edp_have_panel_vdd(struct intel_dp
> *intel_dp)
> >> return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) &
> >> EDP_FORCE_VDD; }
> >>
> >> -void intel_dp_check_edp(struct intel_dp *intel_dp)
> >> +void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
> > IMHO comment to take pps_lock would be useful here.
>
> Part of the point of this change is to name it _unlocked to highlight it does
> not take the lock, i.e. you should be aware of locking. You see this pattern
> all over the kernel. It's self-documenting code.
>
> Moreover, after the edp check, the calls here have:
>
> lockdep_assert_held(&dev_priv->pps_mutex);
>
> which both documents the requirement as well as ensures the proper usage
> in lockdep builds. I don't think a comment adds any value.
Agreeing with you on this.
Patch looks good to me.
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
>
> BR,
> Jani.
>
>
> > Thanks,
> > Anshuman.
> >> {
> >> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_pps.h
> >> b/drivers/gpu/drm/i915/display/intel_pps.h
> >> index 4780b59a59df..8dda282abd42 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_pps.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_pps.h
> >> @@ -22,7 +22,6 @@ intel_wakeref_t intel_pps_unlock(struct intel_dp
> *intel_dp, intel_wakeref_t wake
> >> #define with_intel_pps_lock(dp, wf)
> \
> >> for ((wf) = intel_pps_lock(dp); (wf); (wf) = intel_pps_unlock((dp),
> >> (wf)))
> >>
> >> -void intel_dp_check_edp(struct intel_dp *intel_dp); void
> >> intel_pps_backlight_on(struct intel_dp *intel_dp); void
> >> intel_pps_backlight_off(struct intel_dp *intel_dp); void
> >> intel_pps_backlight_power(struct intel_connector *connector, bool
> >> enable); @@ -31,6 +30,7 @@ bool intel_pps_vdd_on_unlocked(struct
> >> intel_dp *intel_dp); void intel_pps_vdd_off_unlocked(struct intel_dp
> >> *intel_dp, bool sync); void intel_pps_on_unlocked(struct intel_dp
> >> *intel_dp); void intel_pps_off_unlocked(struct intel_dp *intel_dp);
> >> +void intel_pps_check_power_unlocked(struct intel_dp *intel_dp);
> >>
> >> void intel_pps_vdd_on(struct intel_dp *intel_dp); void
> >> intel_pps_on(struct intel_dp *intel_dp);
> >> --
> >> 2.20.1
> >>
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-gfx] [PATCH 01/13] drm/i915/pps: abstract panel power sequencer from intel_dp.c
2021-01-04 14:46 ` Jani Nikula
@ 2021-01-08 17:44 ` Jani Nikula
0 siblings, 0 replies; 35+ messages in thread
From: Jani Nikula @ 2021-01-08 17:44 UTC (permalink / raw)
To: Gupta, Anshuman, intel-gfx
On Mon, 04 Jan 2021, Jani Nikula <jani.nikula@intel.com> wrote:
> On Mon, 28 Dec 2020, "Gupta, Anshuman" <anshuman.gupta@intel.com> wrote:
>>> -----Original Message-----
>>> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
>>> Nikula
>>> Sent: Tuesday, December 22, 2020 8:20 PM
>>> To: intel-gfx@lists.freedesktop.org
>>> Cc: Nikula, Jani <jani.nikula@intel.com>
>>> Subject: [Intel-gfx] [PATCH 01/13] drm/i915/pps: abstract panel power
>>> sequencer from intel_dp.c
>>>
>>> In a long overdue refactoring, split out all panel sequencer code from
>>> intel_dp.c to new intel_pps.[ch].
>>>
>>> The first part is mostly just code movement as-is, without cleanups.
>>>
>>> We need to add a vlv_get_dpll() helper to get at the vlv/chv dpll from
>>> pps code.
>> IMHO functions intel_dp_init_panel_power_sequencer, intel_dp_init_panel_power_sequencer_registers,
>> intel_dp_pps_init suits a intel_edp_* prefix.
>
> This patch just moves code. The rename would be a separate change on
> top. Possibly with intel_pps prefix instead because they're not so much
> about dp or edp as about pps.
I've added some additional renames in v2.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-gfx] [PATCH 04/13] drm/i915/pps: rename intel_edp_panel_* to intel_pps_*
2020-12-29 6:15 ` Anshuman Gupta
@ 2021-01-08 17:45 ` Jani Nikula
0 siblings, 0 replies; 35+ messages in thread
From: Jani Nikula @ 2021-01-08 17:45 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
On Tue, 29 Dec 2020, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
>> /*
>> - * Must be paired with intel_edp_panel_vdd_off() or
>> - * intel_edp_panel_off().
>> + * Must be paired with intel_pps_vdd_off() or
> IMHO can we change the comment, there is no function with name intel_pps_vdd_off()
Fixed in v2.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-gfx] [PATCH 06/13] drm/i915/pps: abstract intel_pps_vdd_off_sync
2020-12-29 6:47 ` Anshuman Gupta
@ 2021-01-08 17:46 ` Jani Nikula
0 siblings, 0 replies; 35+ messages in thread
From: Jani Nikula @ 2021-01-08 17:46 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
On Tue, 29 Dec 2020, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
> On 2020-12-22 at 20:19:46 +0530, Jani Nikula wrote:
>> Add a locked version of intel_pps_vdd_off_sync_unlocked() that does
>> everything the callers expect it to.
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_dp.c | 31 +++---------------------
>> drivers/gpu/drm/i915/display/intel_pps.c | 17 ++++++++++++-
>> drivers/gpu/drm/i915/display/intel_pps.h | 2 +-
>> 3 files changed, 20 insertions(+), 30 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index f2794cc4292a..1a34c9351c30 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -5809,17 +5809,8 @@ void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
>> struct intel_dp *intel_dp = &dig_port->dp;
>>
>> intel_dp_mst_encoder_cleanup(dig_port);
>> - if (intel_dp_is_edp(intel_dp)) {
>> - intel_wakeref_t wakeref;
>>
>> - cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
>> - /*
>> - * vdd might still be enabled do to the delayed vdd off.
>> - * Make sure vdd is actually turned off here.
>> - */
>> - with_intel_pps_lock(intel_dp, wakeref)
>> - intel_pps_vdd_off_sync_unlocked(intel_dp);
>> - }
>> + intel_pps_vdd_off_sync(intel_dp);
>>
>> intel_dp_aux_fini(intel_dp);
>> }
>> @@ -5835,18 +5826,8 @@ static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
>> void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
>> {
>> struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
>> - intel_wakeref_t wakeref;
>> -
>> - if (!intel_dp_is_edp(intel_dp))
>> - return;
>>
>> - /*
>> - * vdd might still be enabled do to the delayed vdd off.
>> - * Make sure vdd is actually turned off here.
>> - */
>> - cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
>> - with_intel_pps_lock(intel_dp, wakeref)
>> - intel_pps_vdd_off_sync_unlocked(intel_dp);
>> + intel_pps_vdd_off_sync(intel_dp);
>> }
>>
>> void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
>> @@ -6700,13 +6681,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
>> return true;
>>
>> out_vdd_off:
>> - cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
>> - /*
>> - * vdd might still be enabled do to the delayed vdd off.
>> - * Make sure vdd is actually turned off here.
>> - */
>> - with_intel_pps_lock(intel_dp, wakeref)
>> - intel_pps_vdd_off_sync_unlocked(intel_dp);
>> + intel_pps_vdd_off_sync(intel_dp);
>>
>> return false;
>> }
>> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
>> index 01c9e69f4e3a..acd6d0092bc6 100644
>> --- a/drivers/gpu/drm/i915/display/intel_pps.c
>> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
>> @@ -641,7 +641,7 @@ void intel_pps_vdd_on(struct intel_dp *intel_dp)
>> dp_to_dig_port(intel_dp)->base.base.name);
>> }
>>
>> -void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
>> +static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
>> {
>> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>> struct intel_digital_port *dig_port =
>> @@ -682,6 +682,21 @@ void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
>> fetch_and_zero(&intel_dp->vdd_wakeref));
>> }
>>
>> +void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
>> +{
>> + intel_wakeref_t wakeref;
>> + if (!intel_dp_is_edp(intel_dp))
>> + return;
>> +
>> + cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
>> + /*
>> + * vdd might still be enabled do to the delayed vdd off.
> I belive there is a typo here "do -> due"
I just copy-pasted this over, but fixed in v2.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
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^ permalink raw reply [flat|nested] 35+ messages in thread
end of thread, other threads:[~2021-01-08 17:46 UTC | newest]
Thread overview: 35+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-12-22 14:49 [Intel-gfx] [PATCH 00/13] drm/i915/dp: split out pps and aux Jani Nikula
2020-12-22 14:49 ` [Intel-gfx] [PATCH 01/13] drm/i915/pps: abstract panel power sequencer from intel_dp.c Jani Nikula
2020-12-28 11:22 ` Gupta, Anshuman
2021-01-04 14:46 ` Jani Nikula
2021-01-08 17:44 ` Jani Nikula
2020-12-22 14:49 ` [Intel-gfx] [PATCH 02/13] drm/i915/pps: rename pps_{, un}lock -> intel_pps_{, un}lock Jani Nikula
2020-12-28 10:57 ` Gupta, Anshuman
2020-12-22 14:49 ` [Intel-gfx] [PATCH 03/13] drm/i915/pps: rename intel_edp_backlight_* to intel_pps_backlight_* Jani Nikula
2020-12-29 6:12 ` Anshuman Gupta
2020-12-22 14:49 ` [Intel-gfx] [PATCH 04/13] drm/i915/pps: rename intel_edp_panel_* to intel_pps_* Jani Nikula
2020-12-29 6:15 ` Anshuman Gupta
2021-01-08 17:45 ` Jani Nikula
2020-12-22 14:49 ` [Intel-gfx] [PATCH 05/13] drm/i915/pps: rename edp_panel_* to intel_pps_*_unlocked Jani Nikula
2020-12-29 6:35 ` Anshuman Gupta
2020-12-22 14:49 ` [Intel-gfx] [PATCH 06/13] drm/i915/pps: abstract intel_pps_vdd_off_sync Jani Nikula
2020-12-29 6:47 ` Anshuman Gupta
2021-01-08 17:46 ` Jani Nikula
2020-12-22 14:49 ` [Intel-gfx] [PATCH 07/13] drm/i915/pps: add higher level intel_pps_init() call Jani Nikula
2020-12-29 6:53 ` Anshuman Gupta
2020-12-22 14:49 ` [Intel-gfx] [PATCH 08/13] drm/i915/pps: abstract intel_pps_reinit() Jani Nikula
2020-12-29 6:59 ` Anshuman Gupta
2020-12-22 14:49 ` [Intel-gfx] [PATCH 09/13] drm/i915/pps: rename intel_dp_check_edp to intel_pps_check_power_unlocked Jani Nikula
2020-12-29 7:04 ` Anshuman Gupta
2021-01-08 10:33 ` Jani Nikula
2021-01-08 10:59 ` Gupta, Anshuman
2020-12-22 14:49 ` [Intel-gfx] [PATCH 10/13] drm/i915/pps: rename intel_power_sequencer_reset to intel_pps_reset_all Jani Nikula
2020-12-29 7:53 ` Anshuman Gupta
2020-12-22 14:49 ` [Intel-gfx] [PATCH 11/13] drm/i915/pps: add locked intel_pps_wait_power_cycle Jani Nikula
2020-12-29 7:59 ` Anshuman Gupta
2020-12-22 14:49 ` [Intel-gfx] [PATCH 12/13] drm/i915/pps: rename vlv_init_panel_power_sequencer to vlv_pps_init Jani Nikula
2020-12-29 8:01 ` Anshuman Gupta
2020-12-22 14:49 ` [Intel-gfx] [PATCH 13/13] drm/i915/dp: split out aux functionality to intel_dp_aux.c Jani Nikula
2020-12-22 15:57 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: split out pps and aux Patchwork
2020-12-22 16:26 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-12-22 21:02 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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