* [PATCH 0/9] Add RISC-V semihosting 0.2. Finish ARM semihosting 2.0 @ 2021-01-07 17:07 ` Keith Packard 0 siblings, 0 replies; 24+ messages in thread From: Keith Packard via @ 2021-01-07 17:07 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-riscv, Sagar Karandikar, Bastian Koppelmann, Laurent Vivier, qemu-arm, Alistair Francis, Palmer Dabbelt, Alex Bennée This series adds support for RISC-V Semihosting, version 0.2 as specified here: https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 This specification references the ARM semihosting release 2.0 as specified here: https://static.docs.arm.com/100863/0200/semihosting.pdf That specification includes several semihosting calls which were not previously implemented. This series includes implementations for the remaining calls so that both RISC-V and ARM versions are now complete. Tests for release 2.0 can be found in picolibc on the semihost-2.0-all branch: https://github.com/picolibc/picolibc/tree/semihost-2.0-all These tests uncovered a bug in the SYS_HEAPINFO implementation for ARM, which has been fixed in this series as well. The series is structured as follows: 1. Move shared semihosting files 2. Change public common semihosting APIs 3. Change internal semihosting interfaces 4. Fix SYS_HEAPINFO crash on ARM 5-6. Add RISC-V semihosting implementation 7-9. Add missing semihosting operations from release 2.0 ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 0/9] Add RISC-V semihosting 0.2. Finish ARM semihosting 2.0 @ 2021-01-07 17:07 ` Keith Packard 0 siblings, 0 replies; 24+ messages in thread From: Keith Packard @ 2021-01-07 17:07 UTC (permalink / raw) To: qemu-devel Cc: Alex Bennée, Alistair Francis, Bastian Koppelmann, Laurent Vivier, Palmer Dabbelt, Peter Maydell, qemu-arm, qemu-riscv, Sagar Karandikar This series adds support for RISC-V Semihosting, version 0.2 as specified here: https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 This specification references the ARM semihosting release 2.0 as specified here: https://static.docs.arm.com/100863/0200/semihosting.pdf That specification includes several semihosting calls which were not previously implemented. This series includes implementations for the remaining calls so that both RISC-V and ARM versions are now complete. Tests for release 2.0 can be found in picolibc on the semihost-2.0-all branch: https://github.com/picolibc/picolibc/tree/semihost-2.0-all These tests uncovered a bug in the SYS_HEAPINFO implementation for ARM, which has been fixed in this series as well. The series is structured as follows: 1. Move shared semihosting files 2. Change public common semihosting APIs 3. Change internal semihosting interfaces 4. Fix SYS_HEAPINFO crash on ARM 5-6. Add RISC-V semihosting implementation 7-9. Add missing semihosting operations from release 2.0 ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 1/9] semihosting: Move ARM semihosting code to shared directories 2021-01-07 17:07 ` Keith Packard @ 2021-01-07 17:07 ` Keith Packard -1 siblings, 0 replies; 24+ messages in thread From: Keith Packard via @ 2021-01-07 17:07 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, Keith Packard, qemu-riscv, Sagar Karandikar, Bastian Koppelmann, Laurent Vivier, qemu-arm, Alistair Francis, Palmer Dabbelt, Alex Bennée This commit renames two files which provide ARM semihosting support so that they can be shared by other architectures: 1. target/arm/arm-semi.c -> hw/semihosting/common-semi.c 2. linux-user/arm/semihost.c -> linux-user/semihost.c The build system was modified use a new config variable, CONFIG_ARM_COMPATIBLE_SEMIHOSTING, which has been added to the ARM softmmu and linux-user default configs. The contents of the source files has not been changed in this patch. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> ---- v2 Place common-semi.c name in arm_ss, just as arm-semi.c was v3 Create CONFIG_ARM_COMPATIBLE_SEMIHOSTING and assign in arm config files v4 Also update aarch64_be default config v5 Also update armeb default config --- default-configs/devices/arm-softmmu.mak | 1 + default-configs/targets/aarch64-linux-user.mak | 1 + default-configs/targets/aarch64_be-linux-user.mak | 1 + default-configs/targets/arm-linux-user.mak | 1 + default-configs/targets/armeb-linux-user.mak | 1 + hw/semihosting/Kconfig | 3 +++ target/arm/arm-semi.c => hw/semihosting/common-semi.c | 0 hw/semihosting/meson.build | 3 +++ linux-user/arm/meson.build | 3 --- linux-user/meson.build | 1 + linux-user/{arm => }/semihost.c | 0 target/arm/meson.build | 2 -- 12 files changed, 12 insertions(+), 5 deletions(-) rename target/arm/arm-semi.c => hw/semihosting/common-semi.c (100%) rename linux-user/{arm => }/semihost.c (100%) diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak index 08a32123b4..0500156a0c 100644 --- a/default-configs/devices/arm-softmmu.mak +++ b/default-configs/devices/arm-softmmu.mak @@ -42,4 +42,5 @@ CONFIG_FSL_IMX25=y CONFIG_FSL_IMX7=y CONFIG_FSL_IMX6UL=y CONFIG_SEMIHOSTING=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y CONFIG_ALLWINNER_H3=y diff --git a/default-configs/targets/aarch64-linux-user.mak b/default-configs/targets/aarch64-linux-user.mak index 163c9209f4..4713253709 100644 --- a/default-configs/targets/aarch64-linux-user.mak +++ b/default-configs/targets/aarch64-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=aarch64 TARGET_BASE_ARCH=arm TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml TARGET_HAS_BFLT=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/default-configs/targets/aarch64_be-linux-user.mak b/default-configs/targets/aarch64_be-linux-user.mak index 4c953cf8c5..fae831558d 100644 --- a/default-configs/targets/aarch64_be-linux-user.mak +++ b/default-configs/targets/aarch64_be-linux-user.mak @@ -3,3 +3,4 @@ TARGET_BASE_ARCH=arm TARGET_WORDS_BIGENDIAN=y TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml TARGET_HAS_BFLT=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/default-configs/targets/arm-linux-user.mak b/default-configs/targets/arm-linux-user.mak index c7cd872e86..e741ffd4d3 100644 --- a/default-configs/targets/arm-linux-user.mak +++ b/default-configs/targets/arm-linux-user.mak @@ -3,3 +3,4 @@ TARGET_SYSTBL_ABI=common,oabi TARGET_SYSTBL=syscall.tbl TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml TARGET_HAS_BFLT=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/default-configs/targets/armeb-linux-user.mak b/default-configs/targets/armeb-linux-user.mak index 79bf10e99b..255e44e8b0 100644 --- a/default-configs/targets/armeb-linux-user.mak +++ b/default-configs/targets/armeb-linux-user.mak @@ -4,3 +4,4 @@ TARGET_SYSTBL=syscall.tbl TARGET_WORDS_BIGENDIAN=y TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml TARGET_HAS_BFLT=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/hw/semihosting/Kconfig b/hw/semihosting/Kconfig index efe0a30734..4c30dc6b16 100644 --- a/hw/semihosting/Kconfig +++ b/hw/semihosting/Kconfig @@ -1,3 +1,6 @@ config SEMIHOSTING bool + +config ARM_COMPATIBLE_SEMIHOSTING + bool diff --git a/target/arm/arm-semi.c b/hw/semihosting/common-semi.c similarity index 100% rename from target/arm/arm-semi.c rename to hw/semihosting/common-semi.c diff --git a/hw/semihosting/meson.build b/hw/semihosting/meson.build index f40ac574c4..5b4a170270 100644 --- a/hw/semihosting/meson.build +++ b/hw/semihosting/meson.build @@ -2,3 +2,6 @@ specific_ss.add(when: 'CONFIG_SEMIHOSTING', if_true: files( 'config.c', 'console.c', )) + +specific_ss.add(when: ['CONFIG_ARM_COMPATIBLE_SEMIHOSTING'], + if_true: files('common-semi.c')) diff --git a/linux-user/arm/meson.build b/linux-user/arm/meson.build index 432984b58e..5a93c925cf 100644 --- a/linux-user/arm/meson.build +++ b/linux-user/arm/meson.build @@ -1,6 +1,3 @@ -linux_user_ss.add(when: 'TARGET_AARCH64', if_true: files('semihost.c')) -linux_user_ss.add(when: 'TARGET_ARM', if_true: files('semihost.c')) - subdir('nwfpe') syscall_nr_generators += { diff --git a/linux-user/meson.build b/linux-user/meson.build index 2b94e4ba24..7fe28d659e 100644 --- a/linux-user/meson.build +++ b/linux-user/meson.build @@ -16,6 +16,7 @@ linux_user_ss.add(rt) linux_user_ss.add(when: 'TARGET_HAS_BFLT', if_true: files('flatload.c')) linux_user_ss.add(when: 'TARGET_I386', if_true: files('vm86.c')) +linux_user_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING', if_true: files('semihost.c')) syscall_nr_generators = {} diff --git a/linux-user/arm/semihost.c b/linux-user/semihost.c similarity index 100% rename from linux-user/arm/semihost.c rename to linux-user/semihost.c diff --git a/target/arm/meson.build b/target/arm/meson.build index f5de2a77b8..15b936c101 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -32,8 +32,6 @@ arm_ss.add(files( )) arm_ss.add(zlib) -arm_ss.add(when: 'CONFIG_TCG', if_true: files('arm-semi.c')) - arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c')) arm_ss.add(when: 'TARGET_AARCH64', if_true: files( -- 2.29.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 1/9] semihosting: Move ARM semihosting code to shared directories @ 2021-01-07 17:07 ` Keith Packard 0 siblings, 0 replies; 24+ messages in thread From: Keith Packard @ 2021-01-07 17:07 UTC (permalink / raw) To: qemu-devel Cc: Alex Bennée, Alistair Francis, Bastian Koppelmann, Laurent Vivier, Palmer Dabbelt, Peter Maydell, qemu-arm, qemu-riscv, Sagar Karandikar, Keith Packard, Alistair Francis This commit renames two files which provide ARM semihosting support so that they can be shared by other architectures: 1. target/arm/arm-semi.c -> hw/semihosting/common-semi.c 2. linux-user/arm/semihost.c -> linux-user/semihost.c The build system was modified use a new config variable, CONFIG_ARM_COMPATIBLE_SEMIHOSTING, which has been added to the ARM softmmu and linux-user default configs. The contents of the source files has not been changed in this patch. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> ---- v2 Place common-semi.c name in arm_ss, just as arm-semi.c was v3 Create CONFIG_ARM_COMPATIBLE_SEMIHOSTING and assign in arm config files v4 Also update aarch64_be default config v5 Also update armeb default config --- default-configs/devices/arm-softmmu.mak | 1 + default-configs/targets/aarch64-linux-user.mak | 1 + default-configs/targets/aarch64_be-linux-user.mak | 1 + default-configs/targets/arm-linux-user.mak | 1 + default-configs/targets/armeb-linux-user.mak | 1 + hw/semihosting/Kconfig | 3 +++ target/arm/arm-semi.c => hw/semihosting/common-semi.c | 0 hw/semihosting/meson.build | 3 +++ linux-user/arm/meson.build | 3 --- linux-user/meson.build | 1 + linux-user/{arm => }/semihost.c | 0 target/arm/meson.build | 2 -- 12 files changed, 12 insertions(+), 5 deletions(-) rename target/arm/arm-semi.c => hw/semihosting/common-semi.c (100%) rename linux-user/{arm => }/semihost.c (100%) diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak index 08a32123b4..0500156a0c 100644 --- a/default-configs/devices/arm-softmmu.mak +++ b/default-configs/devices/arm-softmmu.mak @@ -42,4 +42,5 @@ CONFIG_FSL_IMX25=y CONFIG_FSL_IMX7=y CONFIG_FSL_IMX6UL=y CONFIG_SEMIHOSTING=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y CONFIG_ALLWINNER_H3=y diff --git a/default-configs/targets/aarch64-linux-user.mak b/default-configs/targets/aarch64-linux-user.mak index 163c9209f4..4713253709 100644 --- a/default-configs/targets/aarch64-linux-user.mak +++ b/default-configs/targets/aarch64-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=aarch64 TARGET_BASE_ARCH=arm TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml TARGET_HAS_BFLT=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/default-configs/targets/aarch64_be-linux-user.mak b/default-configs/targets/aarch64_be-linux-user.mak index 4c953cf8c5..fae831558d 100644 --- a/default-configs/targets/aarch64_be-linux-user.mak +++ b/default-configs/targets/aarch64_be-linux-user.mak @@ -3,3 +3,4 @@ TARGET_BASE_ARCH=arm TARGET_WORDS_BIGENDIAN=y TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml TARGET_HAS_BFLT=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/default-configs/targets/arm-linux-user.mak b/default-configs/targets/arm-linux-user.mak index c7cd872e86..e741ffd4d3 100644 --- a/default-configs/targets/arm-linux-user.mak +++ b/default-configs/targets/arm-linux-user.mak @@ -3,3 +3,4 @@ TARGET_SYSTBL_ABI=common,oabi TARGET_SYSTBL=syscall.tbl TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml TARGET_HAS_BFLT=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/default-configs/targets/armeb-linux-user.mak b/default-configs/targets/armeb-linux-user.mak index 79bf10e99b..255e44e8b0 100644 --- a/default-configs/targets/armeb-linux-user.mak +++ b/default-configs/targets/armeb-linux-user.mak @@ -4,3 +4,4 @@ TARGET_SYSTBL=syscall.tbl TARGET_WORDS_BIGENDIAN=y TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml TARGET_HAS_BFLT=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/hw/semihosting/Kconfig b/hw/semihosting/Kconfig index efe0a30734..4c30dc6b16 100644 --- a/hw/semihosting/Kconfig +++ b/hw/semihosting/Kconfig @@ -1,3 +1,6 @@ config SEMIHOSTING bool + +config ARM_COMPATIBLE_SEMIHOSTING + bool diff --git a/target/arm/arm-semi.c b/hw/semihosting/common-semi.c similarity index 100% rename from target/arm/arm-semi.c rename to hw/semihosting/common-semi.c diff --git a/hw/semihosting/meson.build b/hw/semihosting/meson.build index f40ac574c4..5b4a170270 100644 --- a/hw/semihosting/meson.build +++ b/hw/semihosting/meson.build @@ -2,3 +2,6 @@ specific_ss.add(when: 'CONFIG_SEMIHOSTING', if_true: files( 'config.c', 'console.c', )) + +specific_ss.add(when: ['CONFIG_ARM_COMPATIBLE_SEMIHOSTING'], + if_true: files('common-semi.c')) diff --git a/linux-user/arm/meson.build b/linux-user/arm/meson.build index 432984b58e..5a93c925cf 100644 --- a/linux-user/arm/meson.build +++ b/linux-user/arm/meson.build @@ -1,6 +1,3 @@ -linux_user_ss.add(when: 'TARGET_AARCH64', if_true: files('semihost.c')) -linux_user_ss.add(when: 'TARGET_ARM', if_true: files('semihost.c')) - subdir('nwfpe') syscall_nr_generators += { diff --git a/linux-user/meson.build b/linux-user/meson.build index 2b94e4ba24..7fe28d659e 100644 --- a/linux-user/meson.build +++ b/linux-user/meson.build @@ -16,6 +16,7 @@ linux_user_ss.add(rt) linux_user_ss.add(when: 'TARGET_HAS_BFLT', if_true: files('flatload.c')) linux_user_ss.add(when: 'TARGET_I386', if_true: files('vm86.c')) +linux_user_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING', if_true: files('semihost.c')) syscall_nr_generators = {} diff --git a/linux-user/arm/semihost.c b/linux-user/semihost.c similarity index 100% rename from linux-user/arm/semihost.c rename to linux-user/semihost.c diff --git a/target/arm/meson.build b/target/arm/meson.build index f5de2a77b8..15b936c101 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -32,8 +32,6 @@ arm_ss.add(files( )) arm_ss.add(zlib) -arm_ss.add(when: 'CONFIG_TCG', if_true: files('arm-semi.c')) - arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c')) arm_ss.add(when: 'TARGET_AARCH64', if_true: files( -- 2.29.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 2/9] semihosting: Change common-semi API to be architecture-independent 2021-01-07 17:07 ` Keith Packard @ 2021-01-07 17:07 ` Keith Packard -1 siblings, 0 replies; 24+ messages in thread From: Keith Packard via @ 2021-01-07 17:07 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, Keith Packard, qemu-riscv, Sagar Karandikar, Bastian Koppelmann, Laurent Vivier, qemu-arm, Alistair Francis, Palmer Dabbelt, Alex Bennée The public API is now defined in hw/semihosting/common-semi.h. do_common_semihosting takes CPUState * instead of CPUARMState *. All internal functions have been renamed common_semi_ instead of arm_semi_ or arm_. Aside from the API change, there are no functional changes in this patch. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20201214200713.3886611-3-keithp@keithp.com> --- hw/semihosting/common-semi.c | 16 ++++++++++------ hw/semihosting/common-semi.h | 36 +++++++++++++++++++++++++++++++++++ linux-user/aarch64/cpu_loop.c | 3 ++- linux-user/arm/cpu_loop.c | 3 ++- target/arm/cpu.h | 8 -------- target/arm/helper.c | 5 +++-- target/arm/m_helper.c | 7 ++++++- 7 files changed, 59 insertions(+), 19 deletions(-) create mode 100644 hw/semihosting/common-semi.h diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index f7b7bff522..74f09c038c 100644 --- a/hw/semihosting/common-semi.c +++ b/hw/semihosting/common-semi.c @@ -1,10 +1,14 @@ /* - * Arm "Angel" semihosting syscalls + * Semihosting support for systems modeled on the Arm "Angel" + * semihosting syscalls design. * * Copyright (c) 2005, 2007 CodeSourcery. * Copyright (c) 2019 Linaro * Written by Paul Brook. * + * Copyright © 2020 by Keith Packard <keithp@keithp.com> + * Adapted for systems other than ARM, including RISC-V, by Keith Packard + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -373,12 +377,12 @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb, * do anything with its return value, because it is not necessarily * the result of the syscall, but could just be the old value of X0. * The only thing safe to do with this is that the callers of - * do_arm_semihosting() will write it straight back into X0. + * do_common_semihosting() will write it straight back into X0. * (In linux-user mode, the callback will have happened before * gdb_do_syscallv() returns.) * * We should tidy this up so neither this function nor - * do_arm_semihosting() return a value, so the mistake of + * do_common_semihosting() return a value, so the mistake of * doing something with the return value is not possible to make. */ @@ -675,10 +679,10 @@ static const GuestFDFunctions guestfd_fns[] = { * leave the register unchanged. We use 0xdeadbeef as the return value * when there isn't a defined return value for the call. */ -target_ulong do_arm_semihosting(CPUARMState *env) +target_ulong do_common_semihosting(CPUState *cs) { - ARMCPU *cpu = env_archcpu(env); - CPUState *cs = env_cpu(env); + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; target_ulong args; target_ulong arg0, arg1, arg2, arg3; char * s; diff --git a/hw/semihosting/common-semi.h b/hw/semihosting/common-semi.h new file mode 100644 index 0000000000..bc53e92c79 --- /dev/null +++ b/hw/semihosting/common-semi.h @@ -0,0 +1,36 @@ +/* + * Semihosting support for systems modeled on the Arm "Angel" + * semihosting syscalls design. + * + * Copyright (c) 2005, 2007 CodeSourcery. + * Copyright (c) 2019 Linaro + * Written by Paul Brook. + * + * Copyright © 2020 by Keith Packard <keithp@keithp.com> + * Adapted for systems other than ARM, including RISC-V, by Keith Packard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see <http://www.gnu.org/licenses/>. + * + * ARM Semihosting is documented in: + * Semihosting for AArch32 and AArch64 Release 2.0 + * https://static.docs.arm.com/100863/0200/semihosting.pdf + * + */ + +#ifndef COMMON_SEMI_H +#define COMMON_SEMI_H + +target_ulong do_common_semihosting(CPUState *cs); + +#endif /* COMMON_SEMI_H */ diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index bbe9fefca8..42b9c15f53 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -22,6 +22,7 @@ #include "qemu.h" #include "cpu_loop-common.h" #include "qemu/guest-random.h" +#include "hw/semihosting/common-semi.h" #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r = get_user_u32((x), (gaddr)); \ @@ -129,7 +130,7 @@ void cpu_loop(CPUARMState *env) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; case EXCP_SEMIHOST: - env->xregs[0] = do_arm_semihosting(env); + env->xregs[0] = do_common_semihosting(cs); env->pc += 4; break; case EXCP_YIELD: diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index 3d272b56ef..cadfb7fa43 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -22,6 +22,7 @@ #include "qemu.h" #include "elf.h" #include "cpu_loop-common.h" +#include "hw/semihosting/common-semi.h" #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r = get_user_u32((x), (gaddr)); \ @@ -421,7 +422,7 @@ void cpu_loop(CPUARMState *env) } break; case EXCP_SEMIHOST: - env->regs[0] = do_arm_semihosting(env); + env->regs[0] = do_common_semihosting(cs); env->regs[15] += env->thumb ? 2 : 4; break; case EXCP_INTERRUPT: diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7e6c881a7e..49d9a314db 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1068,14 +1068,6 @@ static inline void aarch64_sve_change_el(CPUARMState *env, int o, static inline void aarch64_add_sve_properties(Object *obj) { } #endif -#if !defined(CONFIG_TCG) -static inline target_ulong do_arm_semihosting(CPUARMState *env) -{ - g_assert_not_reached(); -} -#else -target_ulong do_arm_semihosting(CPUARMState *env); -#endif void aarch64_sync_32_to_64(CPUARMState *env); void aarch64_sync_64_to_32(CPUARMState *env); diff --git a/target/arm/helper.c b/target/arm/helper.c index 2d0d4cd1e1..8b6f14e22b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -34,6 +34,7 @@ #ifdef CONFIG_TCG #include "arm_ldst.h" #include "exec/cpu_ldst.h" +#include "hw/semihosting/common-semi.h" #endif #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ @@ -9875,13 +9876,13 @@ static void handle_semihosting(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "...handling as semihosting call 0x%" PRIx64 "\n", env->xregs[0]); - env->xregs[0] = do_arm_semihosting(env); + env->xregs[0] = do_common_semihosting(cs); env->pc += 4; } else { qemu_log_mask(CPU_LOG_INT, "...handling as semihosting call 0x%x\n", env->regs[0]); - env->regs[0] = do_arm_semihosting(env); + env->regs[0] = do_common_semihosting(cs); env->regs[15] += env->thumb ? 2 : 4; } } diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 643dcafb83..6176003029 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -31,6 +31,7 @@ #ifdef CONFIG_TCG #include "arm_ldst.h" #include "exec/cpu_ldst.h" +#include "hw/semihosting/common-semi.h" #endif static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, @@ -2306,7 +2307,11 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "...handling as semihosting call 0x%x\n", env->regs[0]); - env->regs[0] = do_arm_semihosting(env); +#ifdef CONFIG_TCG + env->regs[0] = do_common_semihosting(cs); +#else + g_assert_not_reached(); +#endif env->regs[15] += env->thumb ? 2 : 4; return; case EXCP_BKPT: -- 2.29.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 2/9] semihosting: Change common-semi API to be architecture-independent @ 2021-01-07 17:07 ` Keith Packard 0 siblings, 0 replies; 24+ messages in thread From: Keith Packard @ 2021-01-07 17:07 UTC (permalink / raw) To: qemu-devel Cc: Alex Bennée, Alistair Francis, Bastian Koppelmann, Laurent Vivier, Palmer Dabbelt, Peter Maydell, qemu-arm, qemu-riscv, Sagar Karandikar, Keith Packard, Alistair Francis The public API is now defined in hw/semihosting/common-semi.h. do_common_semihosting takes CPUState * instead of CPUARMState *. All internal functions have been renamed common_semi_ instead of arm_semi_ or arm_. Aside from the API change, there are no functional changes in this patch. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20201214200713.3886611-3-keithp@keithp.com> --- hw/semihosting/common-semi.c | 16 ++++++++++------ hw/semihosting/common-semi.h | 36 +++++++++++++++++++++++++++++++++++ linux-user/aarch64/cpu_loop.c | 3 ++- linux-user/arm/cpu_loop.c | 3 ++- target/arm/cpu.h | 8 -------- target/arm/helper.c | 5 +++-- target/arm/m_helper.c | 7 ++++++- 7 files changed, 59 insertions(+), 19 deletions(-) create mode 100644 hw/semihosting/common-semi.h diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index f7b7bff522..74f09c038c 100644 --- a/hw/semihosting/common-semi.c +++ b/hw/semihosting/common-semi.c @@ -1,10 +1,14 @@ /* - * Arm "Angel" semihosting syscalls + * Semihosting support for systems modeled on the Arm "Angel" + * semihosting syscalls design. * * Copyright (c) 2005, 2007 CodeSourcery. * Copyright (c) 2019 Linaro * Written by Paul Brook. * + * Copyright © 2020 by Keith Packard <keithp@keithp.com> + * Adapted for systems other than ARM, including RISC-V, by Keith Packard + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -373,12 +377,12 @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb, * do anything with its return value, because it is not necessarily * the result of the syscall, but could just be the old value of X0. * The only thing safe to do with this is that the callers of - * do_arm_semihosting() will write it straight back into X0. + * do_common_semihosting() will write it straight back into X0. * (In linux-user mode, the callback will have happened before * gdb_do_syscallv() returns.) * * We should tidy this up so neither this function nor - * do_arm_semihosting() return a value, so the mistake of + * do_common_semihosting() return a value, so the mistake of * doing something with the return value is not possible to make. */ @@ -675,10 +679,10 @@ static const GuestFDFunctions guestfd_fns[] = { * leave the register unchanged. We use 0xdeadbeef as the return value * when there isn't a defined return value for the call. */ -target_ulong do_arm_semihosting(CPUARMState *env) +target_ulong do_common_semihosting(CPUState *cs) { - ARMCPU *cpu = env_archcpu(env); - CPUState *cs = env_cpu(env); + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; target_ulong args; target_ulong arg0, arg1, arg2, arg3; char * s; diff --git a/hw/semihosting/common-semi.h b/hw/semihosting/common-semi.h new file mode 100644 index 0000000000..bc53e92c79 --- /dev/null +++ b/hw/semihosting/common-semi.h @@ -0,0 +1,36 @@ +/* + * Semihosting support for systems modeled on the Arm "Angel" + * semihosting syscalls design. + * + * Copyright (c) 2005, 2007 CodeSourcery. + * Copyright (c) 2019 Linaro + * Written by Paul Brook. + * + * Copyright © 2020 by Keith Packard <keithp@keithp.com> + * Adapted for systems other than ARM, including RISC-V, by Keith Packard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see <http://www.gnu.org/licenses/>. + * + * ARM Semihosting is documented in: + * Semihosting for AArch32 and AArch64 Release 2.0 + * https://static.docs.arm.com/100863/0200/semihosting.pdf + * + */ + +#ifndef COMMON_SEMI_H +#define COMMON_SEMI_H + +target_ulong do_common_semihosting(CPUState *cs); + +#endif /* COMMON_SEMI_H */ diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index bbe9fefca8..42b9c15f53 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -22,6 +22,7 @@ #include "qemu.h" #include "cpu_loop-common.h" #include "qemu/guest-random.h" +#include "hw/semihosting/common-semi.h" #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r = get_user_u32((x), (gaddr)); \ @@ -129,7 +130,7 @@ void cpu_loop(CPUARMState *env) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; case EXCP_SEMIHOST: - env->xregs[0] = do_arm_semihosting(env); + env->xregs[0] = do_common_semihosting(cs); env->pc += 4; break; case EXCP_YIELD: diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index 3d272b56ef..cadfb7fa43 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -22,6 +22,7 @@ #include "qemu.h" #include "elf.h" #include "cpu_loop-common.h" +#include "hw/semihosting/common-semi.h" #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r = get_user_u32((x), (gaddr)); \ @@ -421,7 +422,7 @@ void cpu_loop(CPUARMState *env) } break; case EXCP_SEMIHOST: - env->regs[0] = do_arm_semihosting(env); + env->regs[0] = do_common_semihosting(cs); env->regs[15] += env->thumb ? 2 : 4; break; case EXCP_INTERRUPT: diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7e6c881a7e..49d9a314db 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1068,14 +1068,6 @@ static inline void aarch64_sve_change_el(CPUARMState *env, int o, static inline void aarch64_add_sve_properties(Object *obj) { } #endif -#if !defined(CONFIG_TCG) -static inline target_ulong do_arm_semihosting(CPUARMState *env) -{ - g_assert_not_reached(); -} -#else -target_ulong do_arm_semihosting(CPUARMState *env); -#endif void aarch64_sync_32_to_64(CPUARMState *env); void aarch64_sync_64_to_32(CPUARMState *env); diff --git a/target/arm/helper.c b/target/arm/helper.c index 2d0d4cd1e1..8b6f14e22b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -34,6 +34,7 @@ #ifdef CONFIG_TCG #include "arm_ldst.h" #include "exec/cpu_ldst.h" +#include "hw/semihosting/common-semi.h" #endif #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ @@ -9875,13 +9876,13 @@ static void handle_semihosting(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "...handling as semihosting call 0x%" PRIx64 "\n", env->xregs[0]); - env->xregs[0] = do_arm_semihosting(env); + env->xregs[0] = do_common_semihosting(cs); env->pc += 4; } else { qemu_log_mask(CPU_LOG_INT, "...handling as semihosting call 0x%x\n", env->regs[0]); - env->regs[0] = do_arm_semihosting(env); + env->regs[0] = do_common_semihosting(cs); env->regs[15] += env->thumb ? 2 : 4; } } diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 643dcafb83..6176003029 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -31,6 +31,7 @@ #ifdef CONFIG_TCG #include "arm_ldst.h" #include "exec/cpu_ldst.h" +#include "hw/semihosting/common-semi.h" #endif static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, @@ -2306,7 +2307,11 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "...handling as semihosting call 0x%x\n", env->regs[0]); - env->regs[0] = do_arm_semihosting(env); +#ifdef CONFIG_TCG + env->regs[0] = do_common_semihosting(cs); +#else + g_assert_not_reached(); +#endif env->regs[15] += env->thumb ? 2 : 4; return; case EXCP_BKPT: -- 2.29.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 3/9] semihosting: Change internal common-semi interfaces to use CPUState * 2021-01-07 17:07 ` Keith Packard @ 2021-01-07 17:07 ` Keith Packard -1 siblings, 0 replies; 24+ messages in thread From: Keith Packard via @ 2021-01-07 17:07 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, Keith Packard, qemu-riscv, Sagar Karandikar, Bastian Koppelmann, Laurent Vivier, qemu-arm, Alistair Francis, Palmer Dabbelt, Alex Bennée This makes all of the internal interfaces architecture-independent and renames the internal functions to use the 'common_semi' prefix instead of 'arm' or 'arm_semi'. To do this, some new architecture-specific internal helper functions were created: static inline target_ulong common_semi_arg(CPUState *cs, int argno) Returns the argno'th semihosting argument, where argno can be either 0 or 1. static inline void common_semi_set_ret(CPUState *cs, target_ulong ret) Sets the semihosting return value. static inline bool common_semi_sys_exit_extended(CPUState *cs, int nr) This detects whether the specified semihosting call, which is either TARGET_SYS_EXIT or TARGET_SYS_EXIT_EXTENDED should be executed using the TARGET_SYS_EXIT_EXTENDED semantics. static inline target_ulong common_semi_rambase(CPUState *cs) Returns the base of RAM region used for heap and stack. This is used to construct plausible values for the SYS_HEAPINFO call. In addition, several existing functions have been changed to flag areas of code which are architecture specific: static target_ulong common_semi_flen_buf(CPUState *cs) Returns the current stack pointer minus 64, which is where a stat structure will be placed on the stack #define GET_ARG(n) This fetches arguments from the semihosting command's argument block. The address of this is available implicitly through the local 'args' variable. This is *mostly* architecture independent, but does depend on the current ABI's notion of the size of a 'long' parameter, which may need run-time checks (as it does on AARCH64) #define SET_ARG(n, val) This mirrors GET_ARG and stores data back into the argument block. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> ---- v2: Add common_semi_rambase hook to get memory address for SYS_HEAPINFO call. Message-Id: <20201214200713.3886611-4-keithp@keithp.com> --- hw/semihosting/common-semi.c | 351 +++++++++++++++++++---------------- 1 file changed, 187 insertions(+), 164 deletions(-) diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index 74f09c038c..33c82f73b1 100644 --- a/hw/semihosting/common-semi.c +++ b/hw/semihosting/common-semi.c @@ -32,15 +32,18 @@ #include "cpu.h" #include "hw/semihosting/semihost.h" #include "hw/semihosting/console.h" +#include "hw/semihosting/common-semi.h" #include "qemu/log.h" #ifdef CONFIG_USER_ONLY #include "qemu.h" -#define ARM_ANGEL_HEAP_SIZE (128 * 1024 * 1024) +#define COMMON_SEMI_HEAP_SIZE (128 * 1024 * 1024) #else #include "exec/gdbstub.h" #include "qemu/cutils.h" +#ifdef TARGET_ARM #include "hw/arm/boot.h" +#endif #include "hw/boards.h" #endif @@ -134,6 +137,50 @@ typedef struct GuestFD { static GArray *guestfd_array; +#ifdef TARGET_ARM +static inline target_ulong +common_semi_arg(CPUState *cs, int argno) +{ + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + if (is_a64(env)) { + return env->xregs[argno]; + } else { + return env->regs[argno]; + } +} + +static inline void +common_semi_set_ret(CPUState *cs, target_ulong ret) +{ + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + if (is_a64(env)) { + env->xregs[0] = ret; + } else { + env->regs[0] = ret; + } +} + +static inline bool +common_semi_sys_exit_extended(CPUState *cs, int nr) +{ + return (nr == TARGET_SYS_EXIT_EXTENDED || is_a64(cs->env_ptr)); +} + +#ifndef CONFIG_USER_ONLY +#include "hw/arm/boot.h" +static inline target_ulong +common_semi_rambase(CPUState *cs) +{ + CPUArchState *env = cs->env_ptr; + const struct arm_boot_info *info = env->boot_info; + return info->loader_start; +} +#endif + +#endif /* TARGET_ARM */ + /* * Allocate a new guest file descriptor and return it; if we * couldn't allocate a new fd then return -1. @@ -239,11 +286,10 @@ static target_ulong syscall_err; #include "exec/softmmu-semi.h" #endif -static inline uint32_t set_swi_errno(CPUARMState *env, uint32_t code) +static inline uint32_t set_swi_errno(CPUState *cs, uint32_t code) { if (code == (uint32_t)-1) { #ifdef CONFIG_USER_ONLY - CPUState *cs = env_cpu(env); TaskState *ts = cs->opaque; ts->swi_errno = errno; @@ -254,10 +300,9 @@ static inline uint32_t set_swi_errno(CPUARMState *env, uint32_t code) return code; } -static inline uint32_t get_swi_errno(CPUARMState *env) +static inline uint32_t get_swi_errno(CPUState *cs) { #ifdef CONFIG_USER_ONLY - CPUState *cs = env_cpu(env); TaskState *ts = cs->opaque; return ts->swi_errno; @@ -266,24 +311,22 @@ static inline uint32_t get_swi_errno(CPUARMState *env) #endif } -static target_ulong arm_semi_syscall_len; +static target_ulong common_semi_syscall_len; -static void arm_semi_cb(CPUState *cs, target_ulong ret, target_ulong err) +static void common_semi_cb(CPUState *cs, target_ulong ret, target_ulong err) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - target_ulong reg0 = is_a64(env) ? env->xregs[0] : env->regs[0]; + target_ulong reg0 = common_semi_arg(cs, 0); if (ret == (target_ulong)-1) { errno = err; - set_swi_errno(env, -1); + set_swi_errno(cs, -1); reg0 = ret; } else { /* Fixup syscalls that use nonstardard return conventions. */ switch (reg0) { case TARGET_SYS_WRITE: case TARGET_SYS_READ: - reg0 = arm_semi_syscall_len - ret; + reg0 = common_semi_syscall_len - ret; break; case TARGET_SYS_SEEK: reg0 = 0; @@ -293,77 +336,66 @@ static void arm_semi_cb(CPUState *cs, target_ulong ret, target_ulong err) break; } } - if (is_a64(env)) { - env->xregs[0] = reg0; - } else { - env->regs[0] = reg0; - } + common_semi_set_ret(cs, reg0); } -static target_ulong arm_flen_buf(ARMCPU *cpu) +static target_ulong common_semi_flen_buf(CPUState *cs) { + target_ulong sp; +#ifdef TARGET_ARM /* Return an address in target memory of 64 bytes where the remote * gdb should write its stat struct. (The format of this structure * is defined by GDB's remote protocol and is not target-specific.) * We put this on the guest's stack just below SP. */ + ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; - target_ulong sp; if (is_a64(env)) { sp = env->xregs[31]; } else { sp = env->regs[13]; } +#endif return sp - 64; } -static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err) +static void +common_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; /* The size is always stored in big-endian order, extract the value. We assume the size always fit in 32 bits. */ uint32_t size; - cpu_memory_rw_debug(cs, arm_flen_buf(cpu) + 32, (uint8_t *)&size, 4, 0); + cpu_memory_rw_debug(cs, common_semi_flen_buf(cs) + 32, + (uint8_t *)&size, 4, 0); size = be32_to_cpu(size); - if (is_a64(env)) { - env->xregs[0] = size; - } else { - env->regs[0] = size; - } + common_semi_set_ret(cs, size); errno = err; - set_swi_errno(env, -1); + set_swi_errno(cs, -1); } -static int arm_semi_open_guestfd; +static int common_semi_open_guestfd; -static void arm_semi_open_cb(CPUState *cs, target_ulong ret, target_ulong err) +static void +common_semi_open_cb(CPUState *cs, target_ulong ret, target_ulong err) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; if (ret == (target_ulong)-1) { errno = err; - set_swi_errno(env, -1); - dealloc_guestfd(arm_semi_open_guestfd); + set_swi_errno(cs, -1); + dealloc_guestfd(common_semi_open_guestfd); } else { - associate_guestfd(arm_semi_open_guestfd, ret); - ret = arm_semi_open_guestfd; - } - - if (is_a64(env)) { - env->xregs[0] = ret; - } else { - env->regs[0] = ret; + associate_guestfd(common_semi_open_guestfd, ret); + ret = common_semi_open_guestfd; } + common_semi_set_ret(cs, ret); } -static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb, - const char *fmt, ...) +static target_ulong +common_semi_gdb_syscall(CPUState *cs, gdb_syscall_complete_cb cb, + const char *fmt, ...) { va_list va; - CPUARMState *env = &cpu->env; va_start(va, fmt); gdb_do_syscallv(cb, fmt, va); @@ -386,7 +418,7 @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb, * doing something with the return value is not possible to make. */ - return is_a64(env) ? env->xregs[0] : env->regs[0]; + return common_semi_arg(cs, 0); } /* @@ -395,20 +427,18 @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb, * do the work and return the required return value for the guest, * setting the guest errno if appropriate. */ -typedef uint32_t sys_closefn(ARMCPU *cpu, GuestFD *gf); -typedef uint32_t sys_writefn(ARMCPU *cpu, GuestFD *gf, +typedef uint32_t sys_closefn(CPUState *cs, GuestFD *gf); +typedef uint32_t sys_writefn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len); -typedef uint32_t sys_readfn(ARMCPU *cpu, GuestFD *gf, +typedef uint32_t sys_readfn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len); -typedef uint32_t sys_isattyfn(ARMCPU *cpu, GuestFD *gf); -typedef uint32_t sys_seekfn(ARMCPU *cpu, GuestFD *gf, +typedef uint32_t sys_isattyfn(CPUState *cs, GuestFD *gf); +typedef uint32_t sys_seekfn(CPUState *cs, GuestFD *gf, target_ulong offset); -typedef uint32_t sys_flenfn(ARMCPU *cpu, GuestFD *gf); +typedef uint32_t sys_flenfn(CPUState *cs, GuestFD *gf); -static uint32_t host_closefn(ARMCPU *cpu, GuestFD *gf) +static uint32_t host_closefn(CPUState *cs, GuestFD *gf) { - CPUARMState *env = &cpu->env; - /* * Only close the underlying host fd if it's one we opened on behalf * of the guest in SYS_OPEN. @@ -418,20 +448,21 @@ static uint32_t host_closefn(ARMCPU *cpu, GuestFD *gf) gf->hostfd == STDERR_FILENO) { return 0; } - return set_swi_errno(env, close(gf->hostfd)); + return set_swi_errno(cs, close(gf->hostfd)); } -static uint32_t host_writefn(ARMCPU *cpu, GuestFD *gf, +static uint32_t host_writefn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len) { + CPUArchState *env = cs->env_ptr; uint32_t ret; - CPUARMState *env = &cpu->env; char *s = lock_user(VERIFY_READ, buf, len, 1); + (void) env; /* Used in arm softmmu lock_user implicitly */ if (!s) { /* Return bytes not written on error */ return len; } - ret = set_swi_errno(env, write(gf->hostfd, s, len)); + ret = set_swi_errno(cs, write(gf->hostfd, s, len)); unlock_user(s, buf, 0); if (ret == (uint32_t)-1) { ret = 0; @@ -440,18 +471,19 @@ static uint32_t host_writefn(ARMCPU *cpu, GuestFD *gf, return len - ret; } -static uint32_t host_readfn(ARMCPU *cpu, GuestFD *gf, +static uint32_t host_readfn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len) { + CPUArchState *env = cs->env_ptr; uint32_t ret; - CPUARMState *env = &cpu->env; char *s = lock_user(VERIFY_WRITE, buf, len, 0); + (void) env; /* Used in arm softmmu lock_user implicitly */ if (!s) { /* return bytes not read */ return len; } do { - ret = set_swi_errno(env, read(gf->hostfd, s, len)); + ret = set_swi_errno(cs, read(gf->hostfd, s, len)); } while (ret == -1 && errno == EINTR); unlock_user(s, buf, len); if (ret == (uint32_t)-1) { @@ -461,68 +493,66 @@ static uint32_t host_readfn(ARMCPU *cpu, GuestFD *gf, return len - ret; } -static uint32_t host_isattyfn(ARMCPU *cpu, GuestFD *gf) +static uint32_t host_isattyfn(CPUState *cs, GuestFD *gf) { return isatty(gf->hostfd); } -static uint32_t host_seekfn(ARMCPU *cpu, GuestFD *gf, target_ulong offset) +static uint32_t host_seekfn(CPUState *cs, GuestFD *gf, target_ulong offset) { - CPUARMState *env = &cpu->env; - uint32_t ret = set_swi_errno(env, lseek(gf->hostfd, offset, SEEK_SET)); + uint32_t ret = set_swi_errno(cs, lseek(gf->hostfd, offset, SEEK_SET)); if (ret == (uint32_t)-1) { return -1; } return 0; } -static uint32_t host_flenfn(ARMCPU *cpu, GuestFD *gf) +static uint32_t host_flenfn(CPUState *cs, GuestFD *gf) { - CPUARMState *env = &cpu->env; struct stat buf; - uint32_t ret = set_swi_errno(env, fstat(gf->hostfd, &buf)); + uint32_t ret = set_swi_errno(cs, fstat(gf->hostfd, &buf)); if (ret == (uint32_t)-1) { return -1; } return buf.st_size; } -static uint32_t gdb_closefn(ARMCPU *cpu, GuestFD *gf) +static uint32_t gdb_closefn(CPUState *cs, GuestFD *gf) { - return arm_gdb_syscall(cpu, arm_semi_cb, "close,%x", gf->hostfd); + return common_semi_gdb_syscall(cs, common_semi_cb, "close,%x", gf->hostfd); } -static uint32_t gdb_writefn(ARMCPU *cpu, GuestFD *gf, +static uint32_t gdb_writefn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len) { - arm_semi_syscall_len = len; - return arm_gdb_syscall(cpu, arm_semi_cb, "write,%x,%x,%x", - gf->hostfd, buf, len); + common_semi_syscall_len = len; + return common_semi_gdb_syscall(cs, common_semi_cb, "write,%x,%x,%x", + gf->hostfd, buf, len); } -static uint32_t gdb_readfn(ARMCPU *cpu, GuestFD *gf, +static uint32_t gdb_readfn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len) { - arm_semi_syscall_len = len; - return arm_gdb_syscall(cpu, arm_semi_cb, "read,%x,%x,%x", - gf->hostfd, buf, len); + common_semi_syscall_len = len; + return common_semi_gdb_syscall(cs, common_semi_cb, "read,%x,%x,%x", + gf->hostfd, buf, len); } -static uint32_t gdb_isattyfn(ARMCPU *cpu, GuestFD *gf) +static uint32_t gdb_isattyfn(CPUState *cs, GuestFD *gf) { - return arm_gdb_syscall(cpu, arm_semi_cb, "isatty,%x", gf->hostfd); + return common_semi_gdb_syscall(cs, common_semi_cb, "isatty,%x", gf->hostfd); } -static uint32_t gdb_seekfn(ARMCPU *cpu, GuestFD *gf, target_ulong offset) +static uint32_t gdb_seekfn(CPUState *cs, GuestFD *gf, target_ulong offset) { - return arm_gdb_syscall(cpu, arm_semi_cb, "lseek,%x,%x,0", - gf->hostfd, offset); + return common_semi_gdb_syscall(cs, common_semi_cb, "lseek,%x,%x,0", + gf->hostfd, offset); } -static uint32_t gdb_flenfn(ARMCPU *cpu, GuestFD *gf) +static uint32_t gdb_flenfn(CPUState *cs, GuestFD *gf) { - return arm_gdb_syscall(cpu, arm_semi_flen_cb, "fstat,%x,%x", - gf->hostfd, arm_flen_buf(cpu)); + return common_semi_gdb_syscall(cs, common_semi_flen_cb, "fstat,%x,%x", + gf->hostfd, common_semi_flen_buf(cs)); } #define SHFB_MAGIC_0 0x53 @@ -551,31 +581,29 @@ static void init_featurefile_guestfd(int guestfd) gf->featurefile_offset = 0; } -static uint32_t featurefile_closefn(ARMCPU *cpu, GuestFD *gf) +static uint32_t featurefile_closefn(CPUState *cs, GuestFD *gf) { /* Nothing to do */ return 0; } -static uint32_t featurefile_writefn(ARMCPU *cpu, GuestFD *gf, +static uint32_t featurefile_writefn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len) { /* This fd can never be open for writing */ - CPUARMState *env = &cpu->env; errno = EBADF; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } -static uint32_t featurefile_readfn(ARMCPU *cpu, GuestFD *gf, +static uint32_t featurefile_readfn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len) { + CPUArchState *env = cs->env_ptr; uint32_t i; -#ifndef CONFIG_USER_ONLY - CPUARMState *env = &cpu->env; -#endif char *s; + (void) env; /* Used in arm softmmu lock_user implicitly */ s = lock_user(VERIFY_WRITE, buf, len, 0); if (!s) { return len; @@ -595,19 +623,19 @@ static uint32_t featurefile_readfn(ARMCPU *cpu, GuestFD *gf, return len - i; } -static uint32_t featurefile_isattyfn(ARMCPU *cpu, GuestFD *gf) +static uint32_t featurefile_isattyfn(CPUState *cs, GuestFD *gf) { return 0; } -static uint32_t featurefile_seekfn(ARMCPU *cpu, GuestFD *gf, +static uint32_t featurefile_seekfn(CPUState *cs, GuestFD *gf, target_ulong offset) { gf->featurefile_offset = offset; return 0; } -static uint32_t featurefile_flenfn(ARMCPU *cpu, GuestFD *gf) +static uint32_t featurefile_flenfn(CPUState *cs, GuestFD *gf) { return sizeof(featurefile_data); } @@ -651,16 +679,17 @@ static const GuestFDFunctions guestfd_fns[] = { /* Read the input value from the argument block; fail the semihosting * call if the memory read fails. */ +#ifdef TARGET_ARM #define GET_ARG(n) do { \ if (is_a64(env)) { \ if (get_user_u64(arg ## n, args + (n) * 8)) { \ errno = EFAULT; \ - return set_swi_errno(env, -1); \ + return set_swi_errno(cs, -1); \ } \ } else { \ if (get_user_u32(arg ## n, args + (n) * 4)) { \ errno = EFAULT; \ - return set_swi_errno(env, -1); \ + return set_swi_errno(cs, -1); \ } \ } \ } while (0) @@ -669,6 +698,7 @@ static const GuestFDFunctions guestfd_fns[] = { (is_a64(env) ? \ put_user_u64(val, args + (n) * 8) : \ put_user_u32(val, args + (n) * 4)) +#endif /* * Do a semihosting call. @@ -681,8 +711,7 @@ static const GuestFDFunctions guestfd_fns[] = { */ target_ulong do_common_semihosting(CPUState *cs) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; + CPUArchState *env = cs->env_ptr; target_ulong args; target_ulong arg0, arg1, arg2, arg3; char * s; @@ -691,14 +720,9 @@ target_ulong do_common_semihosting(CPUState *cs) uint32_t len; GuestFD *gf; - if (is_a64(env)) { - /* Note that the syscall number is in W0, not X0 */ - nr = env->xregs[0] & 0xffffffffU; - args = env->xregs[1]; - } else { - nr = env->regs[0]; - args = env->regs[1]; - } + (void) env; /* Used implicitly by arm lock_user macro */ + nr = common_semi_arg(cs, 0) & 0xffffffffU; + args = common_semi_arg(cs, 1); switch (nr) { case TARGET_SYS_OPEN: @@ -711,19 +735,19 @@ target_ulong do_common_semihosting(CPUState *cs) s = lock_user_string(arg0); if (!s) { errno = EFAULT; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } if (arg1 >= 12) { unlock_user(s, arg0, 0); errno = EINVAL; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } guestfd = alloc_guestfd(); if (guestfd < 0) { unlock_user(s, arg0, 0); errno = EMFILE; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } if (strcmp(s, ":tt") == 0) { @@ -752,18 +776,19 @@ target_ulong do_common_semihosting(CPUState *cs) if (arg1 != 0 && arg1 != 1) { dealloc_guestfd(guestfd); errno = EACCES; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } init_featurefile_guestfd(guestfd); return guestfd; } if (use_gdb_syscalls()) { - arm_semi_open_guestfd = guestfd; - ret = arm_gdb_syscall(cpu, arm_semi_open_cb, "open,%s,%x,1a4", arg0, - (int)arg2 + 1, gdb_open_modeflags[arg1]); + common_semi_open_guestfd = guestfd; + ret = common_semi_gdb_syscall(cs, common_semi_open_cb, + "open,%s,%x,1a4", arg0, (int)arg2 + 1, + gdb_open_modeflags[arg1]); } else { - ret = set_swi_errno(env, open(s, open_modeflags[arg1], 0644)); + ret = set_swi_errno(cs, open(s, open_modeflags[arg1], 0644)); if (ret == (uint32_t)-1) { dealloc_guestfd(guestfd); } else { @@ -780,17 +805,17 @@ target_ulong do_common_semihosting(CPUState *cs) gf = get_guestfd(arg0); if (!gf) { errno = EBADF; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } - ret = guestfd_fns[gf->type].closefn(cpu, gf); + ret = guestfd_fns[gf->type].closefn(cs, gf); dealloc_guestfd(arg0); return ret; case TARGET_SYS_WRITEC: - qemu_semihosting_console_outc(env, args); + qemu_semihosting_console_outc(cs->env_ptr, args); return 0xdeadbeef; case TARGET_SYS_WRITE0: - return qemu_semihosting_console_outs(env, args); + return qemu_semihosting_console_outs(cs->env_ptr, args); case TARGET_SYS_WRITE: GET_ARG(0); GET_ARG(1); @@ -800,10 +825,10 @@ target_ulong do_common_semihosting(CPUState *cs) gf = get_guestfd(arg0); if (!gf) { errno = EBADF; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } - return guestfd_fns[gf->type].writefn(cpu, gf, arg1, len); + return guestfd_fns[gf->type].writefn(cs, gf, arg1, len); case TARGET_SYS_READ: GET_ARG(0); GET_ARG(1); @@ -813,22 +838,22 @@ target_ulong do_common_semihosting(CPUState *cs) gf = get_guestfd(arg0); if (!gf) { errno = EBADF; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } - return guestfd_fns[gf->type].readfn(cpu, gf, arg1, len); + return guestfd_fns[gf->type].readfn(cs, gf, arg1, len); case TARGET_SYS_READC: - return qemu_semihosting_console_inc(env); + return qemu_semihosting_console_inc(cs->env_ptr); case TARGET_SYS_ISTTY: GET_ARG(0); gf = get_guestfd(arg0); if (!gf) { errno = EBADF; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } - return guestfd_fns[gf->type].isattyfn(cpu, gf); + return guestfd_fns[gf->type].isattyfn(cs, gf); case TARGET_SYS_SEEK: GET_ARG(0); GET_ARG(1); @@ -836,20 +861,20 @@ target_ulong do_common_semihosting(CPUState *cs) gf = get_guestfd(arg0); if (!gf) { errno = EBADF; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } - return guestfd_fns[gf->type].seekfn(cpu, gf, arg1); + return guestfd_fns[gf->type].seekfn(cs, gf, arg1); case TARGET_SYS_FLEN: GET_ARG(0); gf = get_guestfd(arg0); if (!gf) { errno = EBADF; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } - return guestfd_fns[gf->type].flenfn(cpu, gf); + return guestfd_fns[gf->type].flenfn(cs, gf); case TARGET_SYS_TMPNAM: qemu_log_mask(LOG_UNIMP, "%s: SYS_TMPNAM not implemented", __func__); return -1; @@ -857,15 +882,15 @@ target_ulong do_common_semihosting(CPUState *cs) GET_ARG(0); GET_ARG(1); if (use_gdb_syscalls()) { - ret = arm_gdb_syscall(cpu, arm_semi_cb, "unlink,%s", - arg0, (int)arg1 + 1); + ret = common_semi_gdb_syscall(cs, common_semi_cb, "unlink,%s", + arg0, (int)arg1 + 1); } else { s = lock_user_string(arg0); if (!s) { errno = EFAULT; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } - ret = set_swi_errno(env, remove(s)); + ret = set_swi_errno(cs, remove(s)); unlock_user(s, arg0, 0); } return ret; @@ -875,17 +900,18 @@ target_ulong do_common_semihosting(CPUState *cs) GET_ARG(2); GET_ARG(3); if (use_gdb_syscalls()) { - return arm_gdb_syscall(cpu, arm_semi_cb, "rename,%s,%s", - arg0, (int)arg1 + 1, arg2, (int)arg3 + 1); + return common_semi_gdb_syscall(cs, common_semi_cb, "rename,%s,%s", + arg0, (int)arg1 + 1, arg2, + (int)arg3 + 1); } else { char *s2; s = lock_user_string(arg0); s2 = lock_user_string(arg2); if (!s || !s2) { errno = EFAULT; - ret = set_swi_errno(env, -1); + ret = set_swi_errno(cs, -1); } else { - ret = set_swi_errno(env, rename(s, s2)); + ret = set_swi_errno(cs, rename(s, s2)); } if (s2) unlock_user(s2, arg2, 0); @@ -896,25 +922,25 @@ target_ulong do_common_semihosting(CPUState *cs) case TARGET_SYS_CLOCK: return clock() / (CLOCKS_PER_SEC / 100); case TARGET_SYS_TIME: - return set_swi_errno(env, time(NULL)); + return set_swi_errno(cs, time(NULL)); case TARGET_SYS_SYSTEM: GET_ARG(0); GET_ARG(1); if (use_gdb_syscalls()) { - return arm_gdb_syscall(cpu, arm_semi_cb, "system,%s", - arg0, (int)arg1 + 1); + return common_semi_gdb_syscall(cs, common_semi_cb, "system,%s", + arg0, (int)arg1 + 1); } else { s = lock_user_string(arg0); if (!s) { errno = EFAULT; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } - ret = set_swi_errno(env, system(s)); + ret = set_swi_errno(cs, system(s)); unlock_user(s, arg0, 0); return ret; } case TARGET_SYS_ERRNO: - return get_swi_errno(env); + return get_swi_errno(cs); case TARGET_SYS_GET_CMDLINE: { /* Build a command-line from the original argv. @@ -966,21 +992,21 @@ target_ulong do_common_semihosting(CPUState *cs) if (output_size > input_size) { /* Not enough space to store command-line arguments. */ errno = E2BIG; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } /* Adjust the command-line length. */ if (SET_ARG(1, output_size - 1)) { /* Couldn't write back to argument block */ errno = EFAULT; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } /* Lock the buffer on the ARM side. */ output_buffer = lock_user(VERIFY_WRITE, arg0, output_size, 0); if (!output_buffer) { errno = EFAULT; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } /* Copy the command-line arguments. */ @@ -996,7 +1022,7 @@ target_ulong do_common_semihosting(CPUState *cs) if (copy_from_user(output_buffer, ts->info->arg_start, output_size)) { errno = EFAULT; - status = set_swi_errno(env, -1); + status = set_swi_errno(cs, -1); goto out; } @@ -1021,8 +1047,7 @@ target_ulong do_common_semihosting(CPUState *cs) #ifdef CONFIG_USER_ONLY TaskState *ts = cs->opaque; #else - const struct arm_boot_info *info = env->boot_info; - target_ulong rambase = info->loader_start; + target_ulong rambase = common_semi_rambase(cs); #endif GET_ARG(0); @@ -1036,7 +1061,7 @@ target_ulong do_common_semihosting(CPUState *cs) abi_ulong ret; ts->heap_base = do_brk(0); - limit = ts->heap_base + ARM_ANGEL_HEAP_SIZE; + limit = ts->heap_base + COMMON_SEMI_HEAP_SIZE; /* Try a big heap, and reduce the size if that fails. */ for (;;) { ret = do_brk(limit); @@ -1064,23 +1089,19 @@ target_ulong do_common_semihosting(CPUState *cs) for (i = 0; i < ARRAY_SIZE(retvals); i++) { bool fail; - if (is_a64(env)) { - fail = put_user_u64(retvals[i], arg0 + i * 8); - } else { - fail = put_user_u32(retvals[i], arg0 + i * 4); - } + fail = SET_ARG(i, retvals[i]); if (fail) { /* Couldn't write back to argument block */ errno = EFAULT; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } } return 0; } case TARGET_SYS_EXIT: case TARGET_SYS_EXIT_EXTENDED: - if (nr == TARGET_SYS_EXIT_EXTENDED || is_a64(env)) { + if (common_semi_sys_exit_extended(cs, nr)) { /* * The A64 version of SYS_EXIT takes a parameter block, * so the application-exit type can return a subcode which @@ -1105,7 +1126,7 @@ target_ulong do_common_semihosting(CPUState *cs) */ ret = (args == ADP_Stopped_ApplicationExit) ? 0 : 1; } - gdb_exit(env, ret); + gdb_exit(cs->env_ptr, ret); exit(ret); case TARGET_SYS_SYNCCACHE: /* @@ -1113,9 +1134,11 @@ target_ulong do_common_semihosting(CPUState *cs) * virtual address range. This is a nop for us since we don't * implement caches. This is only present on A64. */ - if (is_a64(env)) { +#ifdef TARGET_ARM + if (is_a64(cs->env_ptr)) { return 0; } +#endif /* fall through -- invalid for A32/T32 */ default: fprintf(stderr, "qemu: Unsupported SemiHosting SWI 0x%02x\n", nr); -- 2.29.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 3/9] semihosting: Change internal common-semi interfaces to use CPUState * @ 2021-01-07 17:07 ` Keith Packard 0 siblings, 0 replies; 24+ messages in thread From: Keith Packard @ 2021-01-07 17:07 UTC (permalink / raw) To: qemu-devel Cc: Alex Bennée, Alistair Francis, Bastian Koppelmann, Laurent Vivier, Palmer Dabbelt, Peter Maydell, qemu-arm, qemu-riscv, Sagar Karandikar, Keith Packard, Alistair Francis This makes all of the internal interfaces architecture-independent and renames the internal functions to use the 'common_semi' prefix instead of 'arm' or 'arm_semi'. To do this, some new architecture-specific internal helper functions were created: static inline target_ulong common_semi_arg(CPUState *cs, int argno) Returns the argno'th semihosting argument, where argno can be either 0 or 1. static inline void common_semi_set_ret(CPUState *cs, target_ulong ret) Sets the semihosting return value. static inline bool common_semi_sys_exit_extended(CPUState *cs, int nr) This detects whether the specified semihosting call, which is either TARGET_SYS_EXIT or TARGET_SYS_EXIT_EXTENDED should be executed using the TARGET_SYS_EXIT_EXTENDED semantics. static inline target_ulong common_semi_rambase(CPUState *cs) Returns the base of RAM region used for heap and stack. This is used to construct plausible values for the SYS_HEAPINFO call. In addition, several existing functions have been changed to flag areas of code which are architecture specific: static target_ulong common_semi_flen_buf(CPUState *cs) Returns the current stack pointer minus 64, which is where a stat structure will be placed on the stack #define GET_ARG(n) This fetches arguments from the semihosting command's argument block. The address of this is available implicitly through the local 'args' variable. This is *mostly* architecture independent, but does depend on the current ABI's notion of the size of a 'long' parameter, which may need run-time checks (as it does on AARCH64) #define SET_ARG(n, val) This mirrors GET_ARG and stores data back into the argument block. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> ---- v2: Add common_semi_rambase hook to get memory address for SYS_HEAPINFO call. Message-Id: <20201214200713.3886611-4-keithp@keithp.com> --- hw/semihosting/common-semi.c | 351 +++++++++++++++++++---------------- 1 file changed, 187 insertions(+), 164 deletions(-) diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index 74f09c038c..33c82f73b1 100644 --- a/hw/semihosting/common-semi.c +++ b/hw/semihosting/common-semi.c @@ -32,15 +32,18 @@ #include "cpu.h" #include "hw/semihosting/semihost.h" #include "hw/semihosting/console.h" +#include "hw/semihosting/common-semi.h" #include "qemu/log.h" #ifdef CONFIG_USER_ONLY #include "qemu.h" -#define ARM_ANGEL_HEAP_SIZE (128 * 1024 * 1024) +#define COMMON_SEMI_HEAP_SIZE (128 * 1024 * 1024) #else #include "exec/gdbstub.h" #include "qemu/cutils.h" +#ifdef TARGET_ARM #include "hw/arm/boot.h" +#endif #include "hw/boards.h" #endif @@ -134,6 +137,50 @@ typedef struct GuestFD { static GArray *guestfd_array; +#ifdef TARGET_ARM +static inline target_ulong +common_semi_arg(CPUState *cs, int argno) +{ + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + if (is_a64(env)) { + return env->xregs[argno]; + } else { + return env->regs[argno]; + } +} + +static inline void +common_semi_set_ret(CPUState *cs, target_ulong ret) +{ + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + if (is_a64(env)) { + env->xregs[0] = ret; + } else { + env->regs[0] = ret; + } +} + +static inline bool +common_semi_sys_exit_extended(CPUState *cs, int nr) +{ + return (nr == TARGET_SYS_EXIT_EXTENDED || is_a64(cs->env_ptr)); +} + +#ifndef CONFIG_USER_ONLY +#include "hw/arm/boot.h" +static inline target_ulong +common_semi_rambase(CPUState *cs) +{ + CPUArchState *env = cs->env_ptr; + const struct arm_boot_info *info = env->boot_info; + return info->loader_start; +} +#endif + +#endif /* TARGET_ARM */ + /* * Allocate a new guest file descriptor and return it; if we * couldn't allocate a new fd then return -1. @@ -239,11 +286,10 @@ static target_ulong syscall_err; #include "exec/softmmu-semi.h" #endif -static inline uint32_t set_swi_errno(CPUARMState *env, uint32_t code) +static inline uint32_t set_swi_errno(CPUState *cs, uint32_t code) { if (code == (uint32_t)-1) { #ifdef CONFIG_USER_ONLY - CPUState *cs = env_cpu(env); TaskState *ts = cs->opaque; ts->swi_errno = errno; @@ -254,10 +300,9 @@ static inline uint32_t set_swi_errno(CPUARMState *env, uint32_t code) return code; } -static inline uint32_t get_swi_errno(CPUARMState *env) +static inline uint32_t get_swi_errno(CPUState *cs) { #ifdef CONFIG_USER_ONLY - CPUState *cs = env_cpu(env); TaskState *ts = cs->opaque; return ts->swi_errno; @@ -266,24 +311,22 @@ static inline uint32_t get_swi_errno(CPUARMState *env) #endif } -static target_ulong arm_semi_syscall_len; +static target_ulong common_semi_syscall_len; -static void arm_semi_cb(CPUState *cs, target_ulong ret, target_ulong err) +static void common_semi_cb(CPUState *cs, target_ulong ret, target_ulong err) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - target_ulong reg0 = is_a64(env) ? env->xregs[0] : env->regs[0]; + target_ulong reg0 = common_semi_arg(cs, 0); if (ret == (target_ulong)-1) { errno = err; - set_swi_errno(env, -1); + set_swi_errno(cs, -1); reg0 = ret; } else { /* Fixup syscalls that use nonstardard return conventions. */ switch (reg0) { case TARGET_SYS_WRITE: case TARGET_SYS_READ: - reg0 = arm_semi_syscall_len - ret; + reg0 = common_semi_syscall_len - ret; break; case TARGET_SYS_SEEK: reg0 = 0; @@ -293,77 +336,66 @@ static void arm_semi_cb(CPUState *cs, target_ulong ret, target_ulong err) break; } } - if (is_a64(env)) { - env->xregs[0] = reg0; - } else { - env->regs[0] = reg0; - } + common_semi_set_ret(cs, reg0); } -static target_ulong arm_flen_buf(ARMCPU *cpu) +static target_ulong common_semi_flen_buf(CPUState *cs) { + target_ulong sp; +#ifdef TARGET_ARM /* Return an address in target memory of 64 bytes where the remote * gdb should write its stat struct. (The format of this structure * is defined by GDB's remote protocol and is not target-specific.) * We put this on the guest's stack just below SP. */ + ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; - target_ulong sp; if (is_a64(env)) { sp = env->xregs[31]; } else { sp = env->regs[13]; } +#endif return sp - 64; } -static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err) +static void +common_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; /* The size is always stored in big-endian order, extract the value. We assume the size always fit in 32 bits. */ uint32_t size; - cpu_memory_rw_debug(cs, arm_flen_buf(cpu) + 32, (uint8_t *)&size, 4, 0); + cpu_memory_rw_debug(cs, common_semi_flen_buf(cs) + 32, + (uint8_t *)&size, 4, 0); size = be32_to_cpu(size); - if (is_a64(env)) { - env->xregs[0] = size; - } else { - env->regs[0] = size; - } + common_semi_set_ret(cs, size); errno = err; - set_swi_errno(env, -1); + set_swi_errno(cs, -1); } -static int arm_semi_open_guestfd; +static int common_semi_open_guestfd; -static void arm_semi_open_cb(CPUState *cs, target_ulong ret, target_ulong err) +static void +common_semi_open_cb(CPUState *cs, target_ulong ret, target_ulong err) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; if (ret == (target_ulong)-1) { errno = err; - set_swi_errno(env, -1); - dealloc_guestfd(arm_semi_open_guestfd); + set_swi_errno(cs, -1); + dealloc_guestfd(common_semi_open_guestfd); } else { - associate_guestfd(arm_semi_open_guestfd, ret); - ret = arm_semi_open_guestfd; - } - - if (is_a64(env)) { - env->xregs[0] = ret; - } else { - env->regs[0] = ret; + associate_guestfd(common_semi_open_guestfd, ret); + ret = common_semi_open_guestfd; } + common_semi_set_ret(cs, ret); } -static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb, - const char *fmt, ...) +static target_ulong +common_semi_gdb_syscall(CPUState *cs, gdb_syscall_complete_cb cb, + const char *fmt, ...) { va_list va; - CPUARMState *env = &cpu->env; va_start(va, fmt); gdb_do_syscallv(cb, fmt, va); @@ -386,7 +418,7 @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb, * doing something with the return value is not possible to make. */ - return is_a64(env) ? env->xregs[0] : env->regs[0]; + return common_semi_arg(cs, 0); } /* @@ -395,20 +427,18 @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb, * do the work and return the required return value for the guest, * setting the guest errno if appropriate. */ -typedef uint32_t sys_closefn(ARMCPU *cpu, GuestFD *gf); -typedef uint32_t sys_writefn(ARMCPU *cpu, GuestFD *gf, +typedef uint32_t sys_closefn(CPUState *cs, GuestFD *gf); +typedef uint32_t sys_writefn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len); -typedef uint32_t sys_readfn(ARMCPU *cpu, GuestFD *gf, +typedef uint32_t sys_readfn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len); -typedef uint32_t sys_isattyfn(ARMCPU *cpu, GuestFD *gf); -typedef uint32_t sys_seekfn(ARMCPU *cpu, GuestFD *gf, +typedef uint32_t sys_isattyfn(CPUState *cs, GuestFD *gf); +typedef uint32_t sys_seekfn(CPUState *cs, GuestFD *gf, target_ulong offset); -typedef uint32_t sys_flenfn(ARMCPU *cpu, GuestFD *gf); +typedef uint32_t sys_flenfn(CPUState *cs, GuestFD *gf); -static uint32_t host_closefn(ARMCPU *cpu, GuestFD *gf) +static uint32_t host_closefn(CPUState *cs, GuestFD *gf) { - CPUARMState *env = &cpu->env; - /* * Only close the underlying host fd if it's one we opened on behalf * of the guest in SYS_OPEN. @@ -418,20 +448,21 @@ static uint32_t host_closefn(ARMCPU *cpu, GuestFD *gf) gf->hostfd == STDERR_FILENO) { return 0; } - return set_swi_errno(env, close(gf->hostfd)); + return set_swi_errno(cs, close(gf->hostfd)); } -static uint32_t host_writefn(ARMCPU *cpu, GuestFD *gf, +static uint32_t host_writefn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len) { + CPUArchState *env = cs->env_ptr; uint32_t ret; - CPUARMState *env = &cpu->env; char *s = lock_user(VERIFY_READ, buf, len, 1); + (void) env; /* Used in arm softmmu lock_user implicitly */ if (!s) { /* Return bytes not written on error */ return len; } - ret = set_swi_errno(env, write(gf->hostfd, s, len)); + ret = set_swi_errno(cs, write(gf->hostfd, s, len)); unlock_user(s, buf, 0); if (ret == (uint32_t)-1) { ret = 0; @@ -440,18 +471,19 @@ static uint32_t host_writefn(ARMCPU *cpu, GuestFD *gf, return len - ret; } -static uint32_t host_readfn(ARMCPU *cpu, GuestFD *gf, +static uint32_t host_readfn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len) { + CPUArchState *env = cs->env_ptr; uint32_t ret; - CPUARMState *env = &cpu->env; char *s = lock_user(VERIFY_WRITE, buf, len, 0); + (void) env; /* Used in arm softmmu lock_user implicitly */ if (!s) { /* return bytes not read */ return len; } do { - ret = set_swi_errno(env, read(gf->hostfd, s, len)); + ret = set_swi_errno(cs, read(gf->hostfd, s, len)); } while (ret == -1 && errno == EINTR); unlock_user(s, buf, len); if (ret == (uint32_t)-1) { @@ -461,68 +493,66 @@ static uint32_t host_readfn(ARMCPU *cpu, GuestFD *gf, return len - ret; } -static uint32_t host_isattyfn(ARMCPU *cpu, GuestFD *gf) +static uint32_t host_isattyfn(CPUState *cs, GuestFD *gf) { return isatty(gf->hostfd); } -static uint32_t host_seekfn(ARMCPU *cpu, GuestFD *gf, target_ulong offset) +static uint32_t host_seekfn(CPUState *cs, GuestFD *gf, target_ulong offset) { - CPUARMState *env = &cpu->env; - uint32_t ret = set_swi_errno(env, lseek(gf->hostfd, offset, SEEK_SET)); + uint32_t ret = set_swi_errno(cs, lseek(gf->hostfd, offset, SEEK_SET)); if (ret == (uint32_t)-1) { return -1; } return 0; } -static uint32_t host_flenfn(ARMCPU *cpu, GuestFD *gf) +static uint32_t host_flenfn(CPUState *cs, GuestFD *gf) { - CPUARMState *env = &cpu->env; struct stat buf; - uint32_t ret = set_swi_errno(env, fstat(gf->hostfd, &buf)); + uint32_t ret = set_swi_errno(cs, fstat(gf->hostfd, &buf)); if (ret == (uint32_t)-1) { return -1; } return buf.st_size; } -static uint32_t gdb_closefn(ARMCPU *cpu, GuestFD *gf) +static uint32_t gdb_closefn(CPUState *cs, GuestFD *gf) { - return arm_gdb_syscall(cpu, arm_semi_cb, "close,%x", gf->hostfd); + return common_semi_gdb_syscall(cs, common_semi_cb, "close,%x", gf->hostfd); } -static uint32_t gdb_writefn(ARMCPU *cpu, GuestFD *gf, +static uint32_t gdb_writefn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len) { - arm_semi_syscall_len = len; - return arm_gdb_syscall(cpu, arm_semi_cb, "write,%x,%x,%x", - gf->hostfd, buf, len); + common_semi_syscall_len = len; + return common_semi_gdb_syscall(cs, common_semi_cb, "write,%x,%x,%x", + gf->hostfd, buf, len); } -static uint32_t gdb_readfn(ARMCPU *cpu, GuestFD *gf, +static uint32_t gdb_readfn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len) { - arm_semi_syscall_len = len; - return arm_gdb_syscall(cpu, arm_semi_cb, "read,%x,%x,%x", - gf->hostfd, buf, len); + common_semi_syscall_len = len; + return common_semi_gdb_syscall(cs, common_semi_cb, "read,%x,%x,%x", + gf->hostfd, buf, len); } -static uint32_t gdb_isattyfn(ARMCPU *cpu, GuestFD *gf) +static uint32_t gdb_isattyfn(CPUState *cs, GuestFD *gf) { - return arm_gdb_syscall(cpu, arm_semi_cb, "isatty,%x", gf->hostfd); + return common_semi_gdb_syscall(cs, common_semi_cb, "isatty,%x", gf->hostfd); } -static uint32_t gdb_seekfn(ARMCPU *cpu, GuestFD *gf, target_ulong offset) +static uint32_t gdb_seekfn(CPUState *cs, GuestFD *gf, target_ulong offset) { - return arm_gdb_syscall(cpu, arm_semi_cb, "lseek,%x,%x,0", - gf->hostfd, offset); + return common_semi_gdb_syscall(cs, common_semi_cb, "lseek,%x,%x,0", + gf->hostfd, offset); } -static uint32_t gdb_flenfn(ARMCPU *cpu, GuestFD *gf) +static uint32_t gdb_flenfn(CPUState *cs, GuestFD *gf) { - return arm_gdb_syscall(cpu, arm_semi_flen_cb, "fstat,%x,%x", - gf->hostfd, arm_flen_buf(cpu)); + return common_semi_gdb_syscall(cs, common_semi_flen_cb, "fstat,%x,%x", + gf->hostfd, common_semi_flen_buf(cs)); } #define SHFB_MAGIC_0 0x53 @@ -551,31 +581,29 @@ static void init_featurefile_guestfd(int guestfd) gf->featurefile_offset = 0; } -static uint32_t featurefile_closefn(ARMCPU *cpu, GuestFD *gf) +static uint32_t featurefile_closefn(CPUState *cs, GuestFD *gf) { /* Nothing to do */ return 0; } -static uint32_t featurefile_writefn(ARMCPU *cpu, GuestFD *gf, +static uint32_t featurefile_writefn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len) { /* This fd can never be open for writing */ - CPUARMState *env = &cpu->env; errno = EBADF; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } -static uint32_t featurefile_readfn(ARMCPU *cpu, GuestFD *gf, +static uint32_t featurefile_readfn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len) { + CPUArchState *env = cs->env_ptr; uint32_t i; -#ifndef CONFIG_USER_ONLY - CPUARMState *env = &cpu->env; -#endif char *s; + (void) env; /* Used in arm softmmu lock_user implicitly */ s = lock_user(VERIFY_WRITE, buf, len, 0); if (!s) { return len; @@ -595,19 +623,19 @@ static uint32_t featurefile_readfn(ARMCPU *cpu, GuestFD *gf, return len - i; } -static uint32_t featurefile_isattyfn(ARMCPU *cpu, GuestFD *gf) +static uint32_t featurefile_isattyfn(CPUState *cs, GuestFD *gf) { return 0; } -static uint32_t featurefile_seekfn(ARMCPU *cpu, GuestFD *gf, +static uint32_t featurefile_seekfn(CPUState *cs, GuestFD *gf, target_ulong offset) { gf->featurefile_offset = offset; return 0; } -static uint32_t featurefile_flenfn(ARMCPU *cpu, GuestFD *gf) +static uint32_t featurefile_flenfn(CPUState *cs, GuestFD *gf) { return sizeof(featurefile_data); } @@ -651,16 +679,17 @@ static const GuestFDFunctions guestfd_fns[] = { /* Read the input value from the argument block; fail the semihosting * call if the memory read fails. */ +#ifdef TARGET_ARM #define GET_ARG(n) do { \ if (is_a64(env)) { \ if (get_user_u64(arg ## n, args + (n) * 8)) { \ errno = EFAULT; \ - return set_swi_errno(env, -1); \ + return set_swi_errno(cs, -1); \ } \ } else { \ if (get_user_u32(arg ## n, args + (n) * 4)) { \ errno = EFAULT; \ - return set_swi_errno(env, -1); \ + return set_swi_errno(cs, -1); \ } \ } \ } while (0) @@ -669,6 +698,7 @@ static const GuestFDFunctions guestfd_fns[] = { (is_a64(env) ? \ put_user_u64(val, args + (n) * 8) : \ put_user_u32(val, args + (n) * 4)) +#endif /* * Do a semihosting call. @@ -681,8 +711,7 @@ static const GuestFDFunctions guestfd_fns[] = { */ target_ulong do_common_semihosting(CPUState *cs) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; + CPUArchState *env = cs->env_ptr; target_ulong args; target_ulong arg0, arg1, arg2, arg3; char * s; @@ -691,14 +720,9 @@ target_ulong do_common_semihosting(CPUState *cs) uint32_t len; GuestFD *gf; - if (is_a64(env)) { - /* Note that the syscall number is in W0, not X0 */ - nr = env->xregs[0] & 0xffffffffU; - args = env->xregs[1]; - } else { - nr = env->regs[0]; - args = env->regs[1]; - } + (void) env; /* Used implicitly by arm lock_user macro */ + nr = common_semi_arg(cs, 0) & 0xffffffffU; + args = common_semi_arg(cs, 1); switch (nr) { case TARGET_SYS_OPEN: @@ -711,19 +735,19 @@ target_ulong do_common_semihosting(CPUState *cs) s = lock_user_string(arg0); if (!s) { errno = EFAULT; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } if (arg1 >= 12) { unlock_user(s, arg0, 0); errno = EINVAL; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } guestfd = alloc_guestfd(); if (guestfd < 0) { unlock_user(s, arg0, 0); errno = EMFILE; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } if (strcmp(s, ":tt") == 0) { @@ -752,18 +776,19 @@ target_ulong do_common_semihosting(CPUState *cs) if (arg1 != 0 && arg1 != 1) { dealloc_guestfd(guestfd); errno = EACCES; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } init_featurefile_guestfd(guestfd); return guestfd; } if (use_gdb_syscalls()) { - arm_semi_open_guestfd = guestfd; - ret = arm_gdb_syscall(cpu, arm_semi_open_cb, "open,%s,%x,1a4", arg0, - (int)arg2 + 1, gdb_open_modeflags[arg1]); + common_semi_open_guestfd = guestfd; + ret = common_semi_gdb_syscall(cs, common_semi_open_cb, + "open,%s,%x,1a4", arg0, (int)arg2 + 1, + gdb_open_modeflags[arg1]); } else { - ret = set_swi_errno(env, open(s, open_modeflags[arg1], 0644)); + ret = set_swi_errno(cs, open(s, open_modeflags[arg1], 0644)); if (ret == (uint32_t)-1) { dealloc_guestfd(guestfd); } else { @@ -780,17 +805,17 @@ target_ulong do_common_semihosting(CPUState *cs) gf = get_guestfd(arg0); if (!gf) { errno = EBADF; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } - ret = guestfd_fns[gf->type].closefn(cpu, gf); + ret = guestfd_fns[gf->type].closefn(cs, gf); dealloc_guestfd(arg0); return ret; case TARGET_SYS_WRITEC: - qemu_semihosting_console_outc(env, args); + qemu_semihosting_console_outc(cs->env_ptr, args); return 0xdeadbeef; case TARGET_SYS_WRITE0: - return qemu_semihosting_console_outs(env, args); + return qemu_semihosting_console_outs(cs->env_ptr, args); case TARGET_SYS_WRITE: GET_ARG(0); GET_ARG(1); @@ -800,10 +825,10 @@ target_ulong do_common_semihosting(CPUState *cs) gf = get_guestfd(arg0); if (!gf) { errno = EBADF; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } - return guestfd_fns[gf->type].writefn(cpu, gf, arg1, len); + return guestfd_fns[gf->type].writefn(cs, gf, arg1, len); case TARGET_SYS_READ: GET_ARG(0); GET_ARG(1); @@ -813,22 +838,22 @@ target_ulong do_common_semihosting(CPUState *cs) gf = get_guestfd(arg0); if (!gf) { errno = EBADF; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } - return guestfd_fns[gf->type].readfn(cpu, gf, arg1, len); + return guestfd_fns[gf->type].readfn(cs, gf, arg1, len); case TARGET_SYS_READC: - return qemu_semihosting_console_inc(env); + return qemu_semihosting_console_inc(cs->env_ptr); case TARGET_SYS_ISTTY: GET_ARG(0); gf = get_guestfd(arg0); if (!gf) { errno = EBADF; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } - return guestfd_fns[gf->type].isattyfn(cpu, gf); + return guestfd_fns[gf->type].isattyfn(cs, gf); case TARGET_SYS_SEEK: GET_ARG(0); GET_ARG(1); @@ -836,20 +861,20 @@ target_ulong do_common_semihosting(CPUState *cs) gf = get_guestfd(arg0); if (!gf) { errno = EBADF; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } - return guestfd_fns[gf->type].seekfn(cpu, gf, arg1); + return guestfd_fns[gf->type].seekfn(cs, gf, arg1); case TARGET_SYS_FLEN: GET_ARG(0); gf = get_guestfd(arg0); if (!gf) { errno = EBADF; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } - return guestfd_fns[gf->type].flenfn(cpu, gf); + return guestfd_fns[gf->type].flenfn(cs, gf); case TARGET_SYS_TMPNAM: qemu_log_mask(LOG_UNIMP, "%s: SYS_TMPNAM not implemented", __func__); return -1; @@ -857,15 +882,15 @@ target_ulong do_common_semihosting(CPUState *cs) GET_ARG(0); GET_ARG(1); if (use_gdb_syscalls()) { - ret = arm_gdb_syscall(cpu, arm_semi_cb, "unlink,%s", - arg0, (int)arg1 + 1); + ret = common_semi_gdb_syscall(cs, common_semi_cb, "unlink,%s", + arg0, (int)arg1 + 1); } else { s = lock_user_string(arg0); if (!s) { errno = EFAULT; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } - ret = set_swi_errno(env, remove(s)); + ret = set_swi_errno(cs, remove(s)); unlock_user(s, arg0, 0); } return ret; @@ -875,17 +900,18 @@ target_ulong do_common_semihosting(CPUState *cs) GET_ARG(2); GET_ARG(3); if (use_gdb_syscalls()) { - return arm_gdb_syscall(cpu, arm_semi_cb, "rename,%s,%s", - arg0, (int)arg1 + 1, arg2, (int)arg3 + 1); + return common_semi_gdb_syscall(cs, common_semi_cb, "rename,%s,%s", + arg0, (int)arg1 + 1, arg2, + (int)arg3 + 1); } else { char *s2; s = lock_user_string(arg0); s2 = lock_user_string(arg2); if (!s || !s2) { errno = EFAULT; - ret = set_swi_errno(env, -1); + ret = set_swi_errno(cs, -1); } else { - ret = set_swi_errno(env, rename(s, s2)); + ret = set_swi_errno(cs, rename(s, s2)); } if (s2) unlock_user(s2, arg2, 0); @@ -896,25 +922,25 @@ target_ulong do_common_semihosting(CPUState *cs) case TARGET_SYS_CLOCK: return clock() / (CLOCKS_PER_SEC / 100); case TARGET_SYS_TIME: - return set_swi_errno(env, time(NULL)); + return set_swi_errno(cs, time(NULL)); case TARGET_SYS_SYSTEM: GET_ARG(0); GET_ARG(1); if (use_gdb_syscalls()) { - return arm_gdb_syscall(cpu, arm_semi_cb, "system,%s", - arg0, (int)arg1 + 1); + return common_semi_gdb_syscall(cs, common_semi_cb, "system,%s", + arg0, (int)arg1 + 1); } else { s = lock_user_string(arg0); if (!s) { errno = EFAULT; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } - ret = set_swi_errno(env, system(s)); + ret = set_swi_errno(cs, system(s)); unlock_user(s, arg0, 0); return ret; } case TARGET_SYS_ERRNO: - return get_swi_errno(env); + return get_swi_errno(cs); case TARGET_SYS_GET_CMDLINE: { /* Build a command-line from the original argv. @@ -966,21 +992,21 @@ target_ulong do_common_semihosting(CPUState *cs) if (output_size > input_size) { /* Not enough space to store command-line arguments. */ errno = E2BIG; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } /* Adjust the command-line length. */ if (SET_ARG(1, output_size - 1)) { /* Couldn't write back to argument block */ errno = EFAULT; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } /* Lock the buffer on the ARM side. */ output_buffer = lock_user(VERIFY_WRITE, arg0, output_size, 0); if (!output_buffer) { errno = EFAULT; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } /* Copy the command-line arguments. */ @@ -996,7 +1022,7 @@ target_ulong do_common_semihosting(CPUState *cs) if (copy_from_user(output_buffer, ts->info->arg_start, output_size)) { errno = EFAULT; - status = set_swi_errno(env, -1); + status = set_swi_errno(cs, -1); goto out; } @@ -1021,8 +1047,7 @@ target_ulong do_common_semihosting(CPUState *cs) #ifdef CONFIG_USER_ONLY TaskState *ts = cs->opaque; #else - const struct arm_boot_info *info = env->boot_info; - target_ulong rambase = info->loader_start; + target_ulong rambase = common_semi_rambase(cs); #endif GET_ARG(0); @@ -1036,7 +1061,7 @@ target_ulong do_common_semihosting(CPUState *cs) abi_ulong ret; ts->heap_base = do_brk(0); - limit = ts->heap_base + ARM_ANGEL_HEAP_SIZE; + limit = ts->heap_base + COMMON_SEMI_HEAP_SIZE; /* Try a big heap, and reduce the size if that fails. */ for (;;) { ret = do_brk(limit); @@ -1064,23 +1089,19 @@ target_ulong do_common_semihosting(CPUState *cs) for (i = 0; i < ARRAY_SIZE(retvals); i++) { bool fail; - if (is_a64(env)) { - fail = put_user_u64(retvals[i], arg0 + i * 8); - } else { - fail = put_user_u32(retvals[i], arg0 + i * 4); - } + fail = SET_ARG(i, retvals[i]); if (fail) { /* Couldn't write back to argument block */ errno = EFAULT; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } } return 0; } case TARGET_SYS_EXIT: case TARGET_SYS_EXIT_EXTENDED: - if (nr == TARGET_SYS_EXIT_EXTENDED || is_a64(env)) { + if (common_semi_sys_exit_extended(cs, nr)) { /* * The A64 version of SYS_EXIT takes a parameter block, * so the application-exit type can return a subcode which @@ -1105,7 +1126,7 @@ target_ulong do_common_semihosting(CPUState *cs) */ ret = (args == ADP_Stopped_ApplicationExit) ? 0 : 1; } - gdb_exit(env, ret); + gdb_exit(cs->env_ptr, ret); exit(ret); case TARGET_SYS_SYNCCACHE: /* @@ -1113,9 +1134,11 @@ target_ulong do_common_semihosting(CPUState *cs) * virtual address range. This is a nop for us since we don't * implement caches. This is only present on A64. */ - if (is_a64(env)) { +#ifdef TARGET_ARM + if (is_a64(cs->env_ptr)) { return 0; } +#endif /* fall through -- invalid for A32/T32 */ default: fprintf(stderr, "qemu: Unsupported SemiHosting SWI 0x%02x\n", nr); -- 2.29.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 4/9] semihosting: Support SYS_HEAPINFO when env->boot_info is not set 2021-01-07 17:07 ` Keith Packard @ 2021-01-07 17:07 ` Keith Packard -1 siblings, 0 replies; 24+ messages in thread From: Keith Packard via @ 2021-01-07 17:07 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, Keith Packard, qemu-riscv, Sagar Karandikar, Bastian Koppelmann, Laurent Vivier, qemu-arm, Alistair Francis, Palmer Dabbelt, Alex Bennée env->boot_info is only set in some ARM startup paths, so we cannot rely on it to support the SYS_HEAPINFO semihosting function. When not available, fallback to finding a RAM memory region containing the current stack and use the base of that. Signed-off-by: Keith Packard <keithp@keithp.com> Message-Id: <20201214200713.3886611-5-keithp@keithp.com> --- hw/semihosting/common-semi.c | 43 +++++++++++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index 33c82f73b1..f09deff4d3 100644 --- a/hw/semihosting/common-semi.c +++ b/hw/semihosting/common-semi.c @@ -137,6 +137,36 @@ typedef struct GuestFD { static GArray *guestfd_array; +#ifndef CONFIG_USER_ONLY +#include "exec/address-spaces.h" +/* + * Find the base of a RAM region containing the specified address + */ +static inline hwaddr +common_semi_find_region_base(hwaddr addr) +{ + MemoryRegion *subregion; + + /* + * Find the chunk of R/W memory containing the address. This is + * used for the SYS_HEAPINFO semihosting call, which should + * probably be using information from the loaded application. + */ + QTAILQ_FOREACH(subregion, &get_system_memory()->subregions, + subregions_link) { + if (subregion->ram && !subregion->readonly) { + Int128 top128 = int128_add(int128_make64(subregion->addr), + subregion->size); + Int128 addr128 = int128_make64(addr); + if (subregion->addr <= addr && int128_lt(addr128, top128)) { + return subregion->addr; + } + } + } + return 0; +} +#endif + #ifdef TARGET_ARM static inline target_ulong common_semi_arg(CPUState *cs, int argno) @@ -175,7 +205,18 @@ common_semi_rambase(CPUState *cs) { CPUArchState *env = cs->env_ptr; const struct arm_boot_info *info = env->boot_info; - return info->loader_start; + target_ulong sp; + + if (info) { + return info->loader_start; + } + + if (is_a64(env)) { + sp = env->xregs[31]; + } else { + sp = env->regs[13]; + } + return common_semi_find_region_base(sp); } #endif -- 2.29.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 4/9] semihosting: Support SYS_HEAPINFO when env->boot_info is not set @ 2021-01-07 17:07 ` Keith Packard 0 siblings, 0 replies; 24+ messages in thread From: Keith Packard @ 2021-01-07 17:07 UTC (permalink / raw) To: qemu-devel Cc: Alex Bennée, Alistair Francis, Bastian Koppelmann, Laurent Vivier, Palmer Dabbelt, Peter Maydell, qemu-arm, qemu-riscv, Sagar Karandikar, Keith Packard env->boot_info is only set in some ARM startup paths, so we cannot rely on it to support the SYS_HEAPINFO semihosting function. When not available, fallback to finding a RAM memory region containing the current stack and use the base of that. Signed-off-by: Keith Packard <keithp@keithp.com> Message-Id: <20201214200713.3886611-5-keithp@keithp.com> --- hw/semihosting/common-semi.c | 43 +++++++++++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index 33c82f73b1..f09deff4d3 100644 --- a/hw/semihosting/common-semi.c +++ b/hw/semihosting/common-semi.c @@ -137,6 +137,36 @@ typedef struct GuestFD { static GArray *guestfd_array; +#ifndef CONFIG_USER_ONLY +#include "exec/address-spaces.h" +/* + * Find the base of a RAM region containing the specified address + */ +static inline hwaddr +common_semi_find_region_base(hwaddr addr) +{ + MemoryRegion *subregion; + + /* + * Find the chunk of R/W memory containing the address. This is + * used for the SYS_HEAPINFO semihosting call, which should + * probably be using information from the loaded application. + */ + QTAILQ_FOREACH(subregion, &get_system_memory()->subregions, + subregions_link) { + if (subregion->ram && !subregion->readonly) { + Int128 top128 = int128_add(int128_make64(subregion->addr), + subregion->size); + Int128 addr128 = int128_make64(addr); + if (subregion->addr <= addr && int128_lt(addr128, top128)) { + return subregion->addr; + } + } + } + return 0; +} +#endif + #ifdef TARGET_ARM static inline target_ulong common_semi_arg(CPUState *cs, int argno) @@ -175,7 +205,18 @@ common_semi_rambase(CPUState *cs) { CPUArchState *env = cs->env_ptr; const struct arm_boot_info *info = env->boot_info; - return info->loader_start; + target_ulong sp; + + if (info) { + return info->loader_start; + } + + if (is_a64(env)) { + sp = env->xregs[31]; + } else { + sp = env->regs[13]; + } + return common_semi_find_region_base(sp); } #endif -- 2.29.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 5/9] riscv: Add semihosting support 2021-01-07 17:07 ` Keith Packard @ 2021-01-07 17:07 ` Keith Packard -1 siblings, 0 replies; 24+ messages in thread From: Keith Packard via @ 2021-01-07 17:07 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, Keith Packard, qemu-riscv, Sagar Karandikar, Bastian Koppelmann, Laurent Vivier, qemu-arm, Alistair Francis, Palmer Dabbelt, Alex Bennée Adapt the arm semihosting support code for RISCV. This implementation is based on the standard for RISC-V semihosting version 0.2 as documented in https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 Signed-off-by: Keith Packard <keithp@keithp.com> Message-Id: <20201214200713.3886611-6-keithp@keithp.com> --- default-configs/devices/riscv32-softmmu.mak | 2 + default-configs/devices/riscv64-softmmu.mak | 2 + .../targets/riscv32-linux-user.mak | 1 + .../targets/riscv64-linux-user.mak | 1 + hw/semihosting/common-semi.c | 82 ++++++++++++++++++- hw/semihosting/common-semi.h | 5 +- linux-user/qemu.h | 4 +- linux-user/semihost.c | 8 +- qemu-options.hx | 10 ++- target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 10 +++ .../riscv/insn_trans/trans_privileged.c.inc | 37 ++++++++- target/riscv/translate.c | 11 +++ 13 files changed, 162 insertions(+), 12 deletions(-) diff --git a/default-configs/devices/riscv32-softmmu.mak b/default-configs/devices/riscv32-softmmu.mak index 94a236c9c2..d847bd5692 100644 --- a/default-configs/devices/riscv32-softmmu.mak +++ b/default-configs/devices/riscv32-softmmu.mak @@ -3,6 +3,8 @@ # Uncomment the following lines to disable these optional devices: # #CONFIG_PCI_DEVICES=n +CONFIG_SEMIHOSTING=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y # Boards: # diff --git a/default-configs/devices/riscv64-softmmu.mak b/default-configs/devices/riscv64-softmmu.mak index 76b6195648..d5eec75f05 100644 --- a/default-configs/devices/riscv64-softmmu.mak +++ b/default-configs/devices/riscv64-softmmu.mak @@ -3,6 +3,8 @@ # Uncomment the following lines to disable these optional devices: # #CONFIG_PCI_DEVICES=n +CONFIG_SEMIHOSTING=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y # Boards: # diff --git a/default-configs/targets/riscv32-linux-user.mak b/default-configs/targets/riscv32-linux-user.mak index dfb259e8aa..6a9d1b1bc1 100644 --- a/default-configs/targets/riscv32-linux-user.mak +++ b/default-configs/targets/riscv32-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=riscv32 TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-csr.xml gdb-xml/riscv-32bit-virtual.xml +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/default-configs/targets/riscv64-linux-user.mak b/default-configs/targets/riscv64-linux-user.mak index b13895f3b0..0a92849a1b 100644 --- a/default-configs/targets/riscv64-linux-user.mak +++ b/default-configs/targets/riscv64-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=riscv64 TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-csr.xml gdb-xml/riscv-64bit-virtual.xml +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index f09deff4d3..f0cf5f10f5 100644 --- a/hw/semihosting/common-semi.c +++ b/hw/semihosting/common-semi.c @@ -1,6 +1,6 @@ /* * Semihosting support for systems modeled on the Arm "Angel" - * semihosting syscalls design. + * semihosting syscalls design. This includes Arm and RISC-V processors * * Copyright (c) 2005, 2007 CodeSourcery. * Copyright (c) 2019 Linaro @@ -25,6 +25,10 @@ * ARM Semihosting is documented in: * Semihosting for AArch32 and AArch64 Release 2.0 * https://static.docs.arm.com/100863/0200/semihosting.pdf + * + * RISC-V Semihosting is documented in: + * RISC-V Semihosting + * https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc */ #include "qemu/osdep.h" @@ -222,6 +226,42 @@ common_semi_rambase(CPUState *cs) #endif /* TARGET_ARM */ +#ifdef TARGET_RISCV +static inline target_ulong +common_semi_arg(CPUState *cs, int argno) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + return env->gpr[xA0 + argno]; +} + +static inline void +common_semi_set_ret(CPUState *cs, target_ulong ret) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + env->gpr[xA0] = ret; +} + +static inline bool +common_semi_sys_exit_extended(CPUState *cs, int nr) +{ + return (nr == TARGET_SYS_EXIT_EXTENDED || sizeof(target_ulong) == 8); +} + +#ifndef CONFIG_USER_ONLY + +static inline target_ulong +common_semi_rambase(CPUState *cs) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + return common_semi_find_region_base(env->gpr[xSP]); +} +#endif + +#endif + /* * Allocate a new guest file descriptor and return it; if we * couldn't allocate a new fd then return -1. @@ -398,6 +438,12 @@ static target_ulong common_semi_flen_buf(CPUState *cs) sp = env->regs[13]; } #endif +#ifdef TARGET_RISCV + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + + sp = env->gpr[xSP]; +#endif return sp - 64; } @@ -741,6 +787,37 @@ static const GuestFDFunctions guestfd_fns[] = { put_user_u32(val, args + (n) * 4)) #endif +#ifdef TARGET_RISCV + +/* + * get_user_ual is defined as get_user_u32 in softmmu-semi.h, + * we need a macro that fetches a target_ulong + */ +#define get_user_utl(arg, p) \ + ((sizeof(target_ulong) == 8) ? \ + get_user_u64(arg, p) : \ + get_user_u32(arg, p)) + +/* + * put_user_ual is defined as put_user_u32 in softmmu-semi.h, + * we need a macro that stores a target_ulong + */ +#define put_user_utl(arg, p) \ + ((sizeof(target_ulong) == 8) ? \ + put_user_u64(arg, p) : \ + put_user_u32(arg, p)) + +#define GET_ARG(n) do { \ + if (get_user_utl(arg ## n, args + (n) * sizeof(target_ulong))) { \ + errno = EFAULT; \ + return set_swi_errno(cs, -1); \ + } \ + } while (0) + +#define SET_ARG(n, val) \ + put_user_utl(val, args + (n) * sizeof(target_ulong)) +#endif + /* * Do a semihosting call. * @@ -1179,6 +1256,9 @@ target_ulong do_common_semihosting(CPUState *cs) if (is_a64(cs->env_ptr)) { return 0; } +#endif +#ifdef TARGET_RISCV + return 0; #endif /* fall through -- invalid for A32/T32 */ default: diff --git a/hw/semihosting/common-semi.h b/hw/semihosting/common-semi.h index bc53e92c79..0bfab1c669 100644 --- a/hw/semihosting/common-semi.h +++ b/hw/semihosting/common-semi.h @@ -1,6 +1,6 @@ /* * Semihosting support for systems modeled on the Arm "Angel" - * semihosting syscalls design. + * semihosting syscalls design. This includes Arm and RISC-V processors * * Copyright (c) 2005, 2007 CodeSourcery. * Copyright (c) 2019 Linaro @@ -26,6 +26,9 @@ * Semihosting for AArch32 and AArch64 Release 2.0 * https://static.docs.arm.com/100863/0200/semihosting.pdf * + * RISC-V Semihosting is documented in: + * RISC-V Semihosting + * https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc */ #ifndef COMMON_SEMI_H diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 534753ca12..17aa992165 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -109,6 +109,8 @@ typedef struct TaskState { /* FPA state */ FPA11 fpa; # endif +#endif +#if defined(TARGET_ARM) || defined(TARGET_RISCV) int swi_errno; #endif #if defined(TARGET_I386) && !defined(TARGET_X86_64) @@ -122,7 +124,7 @@ typedef struct TaskState { #ifdef TARGET_M68K abi_ulong tp_value; #endif -#if defined(TARGET_ARM) || defined(TARGET_M68K) +#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_RISCV) /* Extra fields for semihosted binaries. */ abi_ulong heap_base; abi_ulong heap_limit; diff --git a/linux-user/semihost.c b/linux-user/semihost.c index a1f0f6050e..c0015ee7f6 100644 --- a/linux-user/semihost.c +++ b/linux-user/semihost.c @@ -1,11 +1,11 @@ /* - * ARM Semihosting Console Support + * ARM Compatible Semihosting Console Support. * * Copyright (c) 2019 Linaro Ltd * - * Currently ARM is unique in having support for semihosting support - * in linux-user. So for now we implement the common console API but - * just for arm linux-user. + * Currently ARM and RISC-V are unique in having support for + * semihosting support in linux-user. So for now we implement the + * common console API but just for arm and risc-v linux-user. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/qemu-options.hx b/qemu-options.hx index 459c916d3d..cc6c3af936 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -4190,10 +4190,10 @@ ERST DEF("semihosting", 0, QEMU_OPTION_semihosting, "-semihosting semihosting mode\n", QEMU_ARCH_ARM | QEMU_ARCH_M68K | QEMU_ARCH_XTENSA | QEMU_ARCH_LM32 | - QEMU_ARCH_MIPS | QEMU_ARCH_NIOS2) + QEMU_ARCH_MIPS | QEMU_ARCH_NIOS2 | QEMU_ARCH_RISCV) SRST ``-semihosting`` - Enable semihosting mode (ARM, M68K, Xtensa, MIPS, Nios II only). + Enable semihosting mode (ARM, M68K, Xtensa, MIPS, Nios II, RISC-V only). Note that this allows guest direct access to the host filesystem, so should only be used with a trusted guest OS. @@ -4205,10 +4205,10 @@ DEF("semihosting-config", HAS_ARG, QEMU_OPTION_semihosting_config, "-semihosting-config [enable=on|off][,target=native|gdb|auto][,chardev=id][,arg=str[,...]]\n" \ " semihosting configuration\n", QEMU_ARCH_ARM | QEMU_ARCH_M68K | QEMU_ARCH_XTENSA | QEMU_ARCH_LM32 | -QEMU_ARCH_MIPS | QEMU_ARCH_NIOS2) +QEMU_ARCH_MIPS | QEMU_ARCH_NIOS2 | QEMU_ARCH_RISCV) SRST ``-semihosting-config [enable=on|off][,target=native|gdb|auto][,chardev=id][,arg=str[,...]]`` - Enable and configure semihosting (ARM, M68K, Xtensa, MIPS, Nios II + Enable and configure semihosting (ARM, M68K, Xtensa, MIPS, Nios II, RISC-V only). Note that this allows guest direct access to the host filesystem, so @@ -4223,6 +4223,8 @@ SRST open/read/write/seek/select. Tensilica baremetal libc for ISS and linux platform "sim" use this interface. + On RISC-V this implements the standard semihosting API, version 0.2. + ``target=native|gdb|auto`` Defines where the semihosting calls will be addressed, to QEMU (``native``) or to GDB (``gdb``). The default is ``auto``, which diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index b41e8836c3..4196ef8b69 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -542,6 +542,7 @@ #define RISCV_EXCP_INST_PAGE_FAULT 0xc /* since: priv-1.10.0 */ #define RISCV_EXCP_LOAD_PAGE_FAULT 0xd /* since: priv-1.10.0 */ #define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0 */ +#define RISCV_EXCP_SEMIHOST 0x10 #define RISCV_EXCP_INST_GUEST_PAGE_FAULT 0x14 #define RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT 0x15 #define RISCV_EXCP_VIRT_INSTRUCTION_FAULT 0x16 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index a2afb95fa1..f8350f5f78 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "tcg/tcg-op.h" #include "trace.h" +#include "hw/semihosting/common-semi.h" int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) { @@ -847,6 +848,15 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong htval = 0; target_ulong mtval2 = 0; + if (cause == RISCV_EXCP_SEMIHOST) { + if (env->priv >= PRV_S) { + env->gpr[xA0] = do_common_semihosting(cs); + env->pc += 4; + return; + } + cause = RISCV_EXCP_BREAKPOINT; + } + if (!async) { /* set tval to badaddr for traps with address information */ switch (cause) { diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc index 2a61a853bf..32312be202 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -29,7 +29,42 @@ static bool trans_ecall(DisasContext *ctx, arg_ecall *a) static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a) { - generate_exception(ctx, RISCV_EXCP_BREAKPOINT); + target_ulong ebreak_addr = ctx->base.pc_next; + target_ulong pre_addr = ebreak_addr - 4; + target_ulong post_addr = ebreak_addr + 4; + uint32_t pre = 0; + uint32_t ebreak = 0; + uint32_t post = 0; + + /* + * The RISC-V semihosting spec specifies the following + * three-instruction sequence to flag a semihosting call: + * + * slli zero, zero, 0x1f 0x01f01013 + * ebreak 0x00100073 + * srai zero, zero, 0x7 0x40705013 + * + * The two shift operations on the zero register are no-ops, used + * here to signify a semihosting exception, rather than a breakpoint. + * + * Uncompressed instructions are required so that the sequence is easy + * to validate. + * + * The three instructions are required to lie in the same page so + * that no exception will be raised when fetching them. + */ + + if ((pre_addr & TARGET_PAGE_MASK) == (post_addr & TARGET_PAGE_MASK)) { + pre = opcode_at(&ctx->base, pre_addr); + ebreak = opcode_at(&ctx->base, ebreak_addr); + post = opcode_at(&ctx->base, post_addr); + } + + if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) { + generate_exception(ctx, RISCV_EXCP_SEMIHOST); + } else { + generate_exception(ctx, RISCV_EXCP_BREAKPOINT); + } exit_tb(ctx); /* no chaining */ ctx->base.is_jmp = DISAS_NORETURN; return true; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 554d52a4be..0f28b5f41e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -64,6 +64,7 @@ typedef struct DisasContext { uint16_t vlen; uint16_t mlen; bool vl_eq_vlmax; + CPUState *cs; } DisasContext; #ifdef TARGET_RISCV64 @@ -747,6 +748,15 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, return true; } +static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); + CPUState *cpu = ctx->cs; + CPURISCVState *env = cpu->env_ptr; + + return cpu_ldl_code(env, pc); +} + /* Include insn module translation function */ #include "insn_trans/trans_rvi.c.inc" #include "insn_trans/trans_rvm.c.inc" @@ -814,6 +824,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL); ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul); ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); + ctx->cs = cs; } static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) -- 2.29.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 5/9] riscv: Add semihosting support @ 2021-01-07 17:07 ` Keith Packard 0 siblings, 0 replies; 24+ messages in thread From: Keith Packard @ 2021-01-07 17:07 UTC (permalink / raw) To: qemu-devel Cc: Alex Bennée, Alistair Francis, Bastian Koppelmann, Laurent Vivier, Palmer Dabbelt, Peter Maydell, qemu-arm, qemu-riscv, Sagar Karandikar, Keith Packard Adapt the arm semihosting support code for RISCV. This implementation is based on the standard for RISC-V semihosting version 0.2 as documented in https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 Signed-off-by: Keith Packard <keithp@keithp.com> Message-Id: <20201214200713.3886611-6-keithp@keithp.com> --- default-configs/devices/riscv32-softmmu.mak | 2 + default-configs/devices/riscv64-softmmu.mak | 2 + .../targets/riscv32-linux-user.mak | 1 + .../targets/riscv64-linux-user.mak | 1 + hw/semihosting/common-semi.c | 82 ++++++++++++++++++- hw/semihosting/common-semi.h | 5 +- linux-user/qemu.h | 4 +- linux-user/semihost.c | 8 +- qemu-options.hx | 10 ++- target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 10 +++ .../riscv/insn_trans/trans_privileged.c.inc | 37 ++++++++- target/riscv/translate.c | 11 +++ 13 files changed, 162 insertions(+), 12 deletions(-) diff --git a/default-configs/devices/riscv32-softmmu.mak b/default-configs/devices/riscv32-softmmu.mak index 94a236c9c2..d847bd5692 100644 --- a/default-configs/devices/riscv32-softmmu.mak +++ b/default-configs/devices/riscv32-softmmu.mak @@ -3,6 +3,8 @@ # Uncomment the following lines to disable these optional devices: # #CONFIG_PCI_DEVICES=n +CONFIG_SEMIHOSTING=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y # Boards: # diff --git a/default-configs/devices/riscv64-softmmu.mak b/default-configs/devices/riscv64-softmmu.mak index 76b6195648..d5eec75f05 100644 --- a/default-configs/devices/riscv64-softmmu.mak +++ b/default-configs/devices/riscv64-softmmu.mak @@ -3,6 +3,8 @@ # Uncomment the following lines to disable these optional devices: # #CONFIG_PCI_DEVICES=n +CONFIG_SEMIHOSTING=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y # Boards: # diff --git a/default-configs/targets/riscv32-linux-user.mak b/default-configs/targets/riscv32-linux-user.mak index dfb259e8aa..6a9d1b1bc1 100644 --- a/default-configs/targets/riscv32-linux-user.mak +++ b/default-configs/targets/riscv32-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=riscv32 TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-csr.xml gdb-xml/riscv-32bit-virtual.xml +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/default-configs/targets/riscv64-linux-user.mak b/default-configs/targets/riscv64-linux-user.mak index b13895f3b0..0a92849a1b 100644 --- a/default-configs/targets/riscv64-linux-user.mak +++ b/default-configs/targets/riscv64-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=riscv64 TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-csr.xml gdb-xml/riscv-64bit-virtual.xml +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index f09deff4d3..f0cf5f10f5 100644 --- a/hw/semihosting/common-semi.c +++ b/hw/semihosting/common-semi.c @@ -1,6 +1,6 @@ /* * Semihosting support for systems modeled on the Arm "Angel" - * semihosting syscalls design. + * semihosting syscalls design. This includes Arm and RISC-V processors * * Copyright (c) 2005, 2007 CodeSourcery. * Copyright (c) 2019 Linaro @@ -25,6 +25,10 @@ * ARM Semihosting is documented in: * Semihosting for AArch32 and AArch64 Release 2.0 * https://static.docs.arm.com/100863/0200/semihosting.pdf + * + * RISC-V Semihosting is documented in: + * RISC-V Semihosting + * https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc */ #include "qemu/osdep.h" @@ -222,6 +226,42 @@ common_semi_rambase(CPUState *cs) #endif /* TARGET_ARM */ +#ifdef TARGET_RISCV +static inline target_ulong +common_semi_arg(CPUState *cs, int argno) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + return env->gpr[xA0 + argno]; +} + +static inline void +common_semi_set_ret(CPUState *cs, target_ulong ret) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + env->gpr[xA0] = ret; +} + +static inline bool +common_semi_sys_exit_extended(CPUState *cs, int nr) +{ + return (nr == TARGET_SYS_EXIT_EXTENDED || sizeof(target_ulong) == 8); +} + +#ifndef CONFIG_USER_ONLY + +static inline target_ulong +common_semi_rambase(CPUState *cs) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + return common_semi_find_region_base(env->gpr[xSP]); +} +#endif + +#endif + /* * Allocate a new guest file descriptor and return it; if we * couldn't allocate a new fd then return -1. @@ -398,6 +438,12 @@ static target_ulong common_semi_flen_buf(CPUState *cs) sp = env->regs[13]; } #endif +#ifdef TARGET_RISCV + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + + sp = env->gpr[xSP]; +#endif return sp - 64; } @@ -741,6 +787,37 @@ static const GuestFDFunctions guestfd_fns[] = { put_user_u32(val, args + (n) * 4)) #endif +#ifdef TARGET_RISCV + +/* + * get_user_ual is defined as get_user_u32 in softmmu-semi.h, + * we need a macro that fetches a target_ulong + */ +#define get_user_utl(arg, p) \ + ((sizeof(target_ulong) == 8) ? \ + get_user_u64(arg, p) : \ + get_user_u32(arg, p)) + +/* + * put_user_ual is defined as put_user_u32 in softmmu-semi.h, + * we need a macro that stores a target_ulong + */ +#define put_user_utl(arg, p) \ + ((sizeof(target_ulong) == 8) ? \ + put_user_u64(arg, p) : \ + put_user_u32(arg, p)) + +#define GET_ARG(n) do { \ + if (get_user_utl(arg ## n, args + (n) * sizeof(target_ulong))) { \ + errno = EFAULT; \ + return set_swi_errno(cs, -1); \ + } \ + } while (0) + +#define SET_ARG(n, val) \ + put_user_utl(val, args + (n) * sizeof(target_ulong)) +#endif + /* * Do a semihosting call. * @@ -1179,6 +1256,9 @@ target_ulong do_common_semihosting(CPUState *cs) if (is_a64(cs->env_ptr)) { return 0; } +#endif +#ifdef TARGET_RISCV + return 0; #endif /* fall through -- invalid for A32/T32 */ default: diff --git a/hw/semihosting/common-semi.h b/hw/semihosting/common-semi.h index bc53e92c79..0bfab1c669 100644 --- a/hw/semihosting/common-semi.h +++ b/hw/semihosting/common-semi.h @@ -1,6 +1,6 @@ /* * Semihosting support for systems modeled on the Arm "Angel" - * semihosting syscalls design. + * semihosting syscalls design. This includes Arm and RISC-V processors * * Copyright (c) 2005, 2007 CodeSourcery. * Copyright (c) 2019 Linaro @@ -26,6 +26,9 @@ * Semihosting for AArch32 and AArch64 Release 2.0 * https://static.docs.arm.com/100863/0200/semihosting.pdf * + * RISC-V Semihosting is documented in: + * RISC-V Semihosting + * https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc */ #ifndef COMMON_SEMI_H diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 534753ca12..17aa992165 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -109,6 +109,8 @@ typedef struct TaskState { /* FPA state */ FPA11 fpa; # endif +#endif +#if defined(TARGET_ARM) || defined(TARGET_RISCV) int swi_errno; #endif #if defined(TARGET_I386) && !defined(TARGET_X86_64) @@ -122,7 +124,7 @@ typedef struct TaskState { #ifdef TARGET_M68K abi_ulong tp_value; #endif -#if defined(TARGET_ARM) || defined(TARGET_M68K) +#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_RISCV) /* Extra fields for semihosted binaries. */ abi_ulong heap_base; abi_ulong heap_limit; diff --git a/linux-user/semihost.c b/linux-user/semihost.c index a1f0f6050e..c0015ee7f6 100644 --- a/linux-user/semihost.c +++ b/linux-user/semihost.c @@ -1,11 +1,11 @@ /* - * ARM Semihosting Console Support + * ARM Compatible Semihosting Console Support. * * Copyright (c) 2019 Linaro Ltd * - * Currently ARM is unique in having support for semihosting support - * in linux-user. So for now we implement the common console API but - * just for arm linux-user. + * Currently ARM and RISC-V are unique in having support for + * semihosting support in linux-user. So for now we implement the + * common console API but just for arm and risc-v linux-user. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/qemu-options.hx b/qemu-options.hx index 459c916d3d..cc6c3af936 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -4190,10 +4190,10 @@ ERST DEF("semihosting", 0, QEMU_OPTION_semihosting, "-semihosting semihosting mode\n", QEMU_ARCH_ARM | QEMU_ARCH_M68K | QEMU_ARCH_XTENSA | QEMU_ARCH_LM32 | - QEMU_ARCH_MIPS | QEMU_ARCH_NIOS2) + QEMU_ARCH_MIPS | QEMU_ARCH_NIOS2 | QEMU_ARCH_RISCV) SRST ``-semihosting`` - Enable semihosting mode (ARM, M68K, Xtensa, MIPS, Nios II only). + Enable semihosting mode (ARM, M68K, Xtensa, MIPS, Nios II, RISC-V only). Note that this allows guest direct access to the host filesystem, so should only be used with a trusted guest OS. @@ -4205,10 +4205,10 @@ DEF("semihosting-config", HAS_ARG, QEMU_OPTION_semihosting_config, "-semihosting-config [enable=on|off][,target=native|gdb|auto][,chardev=id][,arg=str[,...]]\n" \ " semihosting configuration\n", QEMU_ARCH_ARM | QEMU_ARCH_M68K | QEMU_ARCH_XTENSA | QEMU_ARCH_LM32 | -QEMU_ARCH_MIPS | QEMU_ARCH_NIOS2) +QEMU_ARCH_MIPS | QEMU_ARCH_NIOS2 | QEMU_ARCH_RISCV) SRST ``-semihosting-config [enable=on|off][,target=native|gdb|auto][,chardev=id][,arg=str[,...]]`` - Enable and configure semihosting (ARM, M68K, Xtensa, MIPS, Nios II + Enable and configure semihosting (ARM, M68K, Xtensa, MIPS, Nios II, RISC-V only). Note that this allows guest direct access to the host filesystem, so @@ -4223,6 +4223,8 @@ SRST open/read/write/seek/select. Tensilica baremetal libc for ISS and linux platform "sim" use this interface. + On RISC-V this implements the standard semihosting API, version 0.2. + ``target=native|gdb|auto`` Defines where the semihosting calls will be addressed, to QEMU (``native``) or to GDB (``gdb``). The default is ``auto``, which diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index b41e8836c3..4196ef8b69 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -542,6 +542,7 @@ #define RISCV_EXCP_INST_PAGE_FAULT 0xc /* since: priv-1.10.0 */ #define RISCV_EXCP_LOAD_PAGE_FAULT 0xd /* since: priv-1.10.0 */ #define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0 */ +#define RISCV_EXCP_SEMIHOST 0x10 #define RISCV_EXCP_INST_GUEST_PAGE_FAULT 0x14 #define RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT 0x15 #define RISCV_EXCP_VIRT_INSTRUCTION_FAULT 0x16 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index a2afb95fa1..f8350f5f78 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "tcg/tcg-op.h" #include "trace.h" +#include "hw/semihosting/common-semi.h" int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) { @@ -847,6 +848,15 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong htval = 0; target_ulong mtval2 = 0; + if (cause == RISCV_EXCP_SEMIHOST) { + if (env->priv >= PRV_S) { + env->gpr[xA0] = do_common_semihosting(cs); + env->pc += 4; + return; + } + cause = RISCV_EXCP_BREAKPOINT; + } + if (!async) { /* set tval to badaddr for traps with address information */ switch (cause) { diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc index 2a61a853bf..32312be202 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -29,7 +29,42 @@ static bool trans_ecall(DisasContext *ctx, arg_ecall *a) static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a) { - generate_exception(ctx, RISCV_EXCP_BREAKPOINT); + target_ulong ebreak_addr = ctx->base.pc_next; + target_ulong pre_addr = ebreak_addr - 4; + target_ulong post_addr = ebreak_addr + 4; + uint32_t pre = 0; + uint32_t ebreak = 0; + uint32_t post = 0; + + /* + * The RISC-V semihosting spec specifies the following + * three-instruction sequence to flag a semihosting call: + * + * slli zero, zero, 0x1f 0x01f01013 + * ebreak 0x00100073 + * srai zero, zero, 0x7 0x40705013 + * + * The two shift operations on the zero register are no-ops, used + * here to signify a semihosting exception, rather than a breakpoint. + * + * Uncompressed instructions are required so that the sequence is easy + * to validate. + * + * The three instructions are required to lie in the same page so + * that no exception will be raised when fetching them. + */ + + if ((pre_addr & TARGET_PAGE_MASK) == (post_addr & TARGET_PAGE_MASK)) { + pre = opcode_at(&ctx->base, pre_addr); + ebreak = opcode_at(&ctx->base, ebreak_addr); + post = opcode_at(&ctx->base, post_addr); + } + + if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) { + generate_exception(ctx, RISCV_EXCP_SEMIHOST); + } else { + generate_exception(ctx, RISCV_EXCP_BREAKPOINT); + } exit_tb(ctx); /* no chaining */ ctx->base.is_jmp = DISAS_NORETURN; return true; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 554d52a4be..0f28b5f41e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -64,6 +64,7 @@ typedef struct DisasContext { uint16_t vlen; uint16_t mlen; bool vl_eq_vlmax; + CPUState *cs; } DisasContext; #ifdef TARGET_RISCV64 @@ -747,6 +748,15 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, return true; } +static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); + CPUState *cpu = ctx->cs; + CPURISCVState *env = cpu->env_ptr; + + return cpu_ldl_code(env, pc); +} + /* Include insn module translation function */ #include "insn_trans/trans_rvi.c.inc" #include "insn_trans/trans_rvm.c.inc" @@ -814,6 +824,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL); ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul); ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); + ctx->cs = cs; } static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) -- 2.29.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 6/9] riscv: Add semihosting support for user mode 2021-01-07 17:07 ` Keith Packard @ 2021-01-07 17:07 ` Keith Packard -1 siblings, 0 replies; 24+ messages in thread From: Keith Packard via @ 2021-01-07 17:07 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, Keith Packard, qemu-riscv, Sagar Karandikar, Bastian Koppelmann, Laurent Vivier, qemu-arm, Alistair Francis, Palmer Dabbelt, Kito Cheng, Alex Bennée From: Kito Cheng <kito.cheng@sifive.com> This could made testing more easier and ARM/AArch64 has supported on their linux user mode too, so I think it should be reasonable. Verified GCC testsuite with newlib/semihosting. Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Reviewed-by: Keith Packard <keithp@keithp.com> Message-Id: <20201214200713.3886611-7-keithp@keithp.com> --- linux-user/riscv/cpu_loop.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index aa9e437875..9665dabb09 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -23,6 +23,7 @@ #include "qemu.h" #include "cpu_loop-common.h" #include "elf.h" +#include "hw/semihosting/common-semi.h" void cpu_loop(CPURISCVState *env) { @@ -91,6 +92,10 @@ void cpu_loop(CPURISCVState *env) sigcode = TARGET_SEGV_MAPERR; sigaddr = env->badaddr; break; + case RISCV_EXCP_SEMIHOST: + env->gpr[xA0] = do_common_semihosting(cs); + env->pc += 4; + break; case EXCP_DEBUG: gdbstep: signum = TARGET_SIGTRAP; -- 2.29.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 6/9] riscv: Add semihosting support for user mode @ 2021-01-07 17:07 ` Keith Packard 0 siblings, 0 replies; 24+ messages in thread From: Keith Packard @ 2021-01-07 17:07 UTC (permalink / raw) To: qemu-devel Cc: Alex Bennée, Alistair Francis, Bastian Koppelmann, Laurent Vivier, Palmer Dabbelt, Peter Maydell, qemu-arm, qemu-riscv, Sagar Karandikar, Kito Cheng, Keith Packard From: Kito Cheng <kito.cheng@sifive.com> This could made testing more easier and ARM/AArch64 has supported on their linux user mode too, so I think it should be reasonable. Verified GCC testsuite with newlib/semihosting. Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Reviewed-by: Keith Packard <keithp@keithp.com> Message-Id: <20201214200713.3886611-7-keithp@keithp.com> --- linux-user/riscv/cpu_loop.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index aa9e437875..9665dabb09 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -23,6 +23,7 @@ #include "qemu.h" #include "cpu_loop-common.h" #include "elf.h" +#include "hw/semihosting/common-semi.h" void cpu_loop(CPURISCVState *env) { @@ -91,6 +92,10 @@ void cpu_loop(CPURISCVState *env) sigcode = TARGET_SEGV_MAPERR; sigaddr = env->badaddr; break; + case RISCV_EXCP_SEMIHOST: + env->gpr[xA0] = do_common_semihosting(cs); + env->pc += 4; + break; case EXCP_DEBUG: gdbstep: signum = TARGET_SIGTRAP; -- 2.29.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 7/9] semihosting: Implement SYS_ELAPSED and SYS_TICKFREQ 2021-01-07 17:07 ` Keith Packard @ 2021-01-07 17:07 ` Keith Packard -1 siblings, 0 replies; 24+ messages in thread From: Keith Packard via @ 2021-01-07 17:07 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, Keith Packard, qemu-riscv, Sagar Karandikar, Bastian Koppelmann, Laurent Vivier, qemu-arm, Alistair Francis, Palmer Dabbelt, Alex Bennée These are part of Semihosting for AArch32 and AArch64 Release 2.0 Signed-off-by: Keith Packard <keithp@keithp.com> Message-Id: <20201214200713.3886611-8-keithp@keithp.com> --- hw/semihosting/common-semi.c | 16 ++++++++++++++++ include/qemu/timer.h | 2 ++ util/qemu-timer-common.c | 4 ++++ 3 files changed, 22 insertions(+) diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index f0cf5f10f5..b1368d945c 100644 --- a/hw/semihosting/common-semi.c +++ b/hw/semihosting/common-semi.c @@ -38,6 +38,7 @@ #include "hw/semihosting/console.h" #include "hw/semihosting/common-semi.h" #include "qemu/log.h" +#include "qemu/timer.h" #ifdef CONFIG_USER_ONLY #include "qemu.h" @@ -73,6 +74,8 @@ #define TARGET_SYS_EXIT 0x18 #define TARGET_SYS_SYNCCACHE 0x19 #define TARGET_SYS_EXIT_EXTENDED 0x20 +#define TARGET_SYS_ELAPSED 0x30 +#define TARGET_SYS_TICKFREQ 0x31 /* ADP_Stopped_ApplicationExit is used for exit(0), * anything else is implemented as exit(1) */ @@ -837,6 +840,7 @@ target_ulong do_common_semihosting(CPUState *cs) uint32_t ret; uint32_t len; GuestFD *gf; + int64_t elapsed; (void) env; /* Used implicitly by arm lock_user macro */ nr = common_semi_arg(cs, 0) & 0xffffffffU; @@ -1246,6 +1250,18 @@ target_ulong do_common_semihosting(CPUState *cs) } gdb_exit(cs->env_ptr, ret); exit(ret); + case TARGET_SYS_ELAPSED: + elapsed = get_clock() - clock_start; + if (sizeof(target_ulong) == 8) { + SET_ARG(0, elapsed); + } else { + SET_ARG(0, (uint32_t) elapsed); + SET_ARG(1, (uint32_t) (elapsed >> 32)); + } + return 0; + case TARGET_SYS_TICKFREQ: + /* qemu always uses nsec */ + return 1000000000; case TARGET_SYS_SYNCCACHE: /* * Clean the D-cache and invalidate the I-cache for the specified diff --git a/include/qemu/timer.h b/include/qemu/timer.h index bdecc5b41f..ca6fae51f1 100644 --- a/include/qemu/timer.h +++ b/include/qemu/timer.h @@ -806,6 +806,8 @@ static inline int64_t get_clock_realtime(void) return tv.tv_sec * 1000000000LL + (tv.tv_usec * 1000); } +extern int64_t clock_start; + /* Warning: don't insert tracepoints into these functions, they are also used by simpletrace backend and tracepoints would cause an infinite recursion! */ diff --git a/util/qemu-timer-common.c b/util/qemu-timer-common.c index baf3317f74..cc1326f726 100644 --- a/util/qemu-timer-common.c +++ b/util/qemu-timer-common.c @@ -27,6 +27,8 @@ /***********************************************************/ /* real time host monotonic timer */ +int64_t clock_start; + #ifdef _WIN32 int64_t clock_freq; @@ -41,6 +43,7 @@ static void __attribute__((constructor)) init_get_clock(void) exit(1); } clock_freq = freq.QuadPart; + clock_start = get_clock(); } #else @@ -55,5 +58,6 @@ static void __attribute__((constructor)) init_get_clock(void) if (clock_gettime(CLOCK_MONOTONIC, &ts) == 0) { use_rt_clock = 1; } + clock_start = get_clock(); } #endif -- 2.29.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 7/9] semihosting: Implement SYS_ELAPSED and SYS_TICKFREQ @ 2021-01-07 17:07 ` Keith Packard 0 siblings, 0 replies; 24+ messages in thread From: Keith Packard @ 2021-01-07 17:07 UTC (permalink / raw) To: qemu-devel Cc: Alex Bennée, Alistair Francis, Bastian Koppelmann, Laurent Vivier, Palmer Dabbelt, Peter Maydell, qemu-arm, qemu-riscv, Sagar Karandikar, Keith Packard These are part of Semihosting for AArch32 and AArch64 Release 2.0 Signed-off-by: Keith Packard <keithp@keithp.com> Message-Id: <20201214200713.3886611-8-keithp@keithp.com> --- hw/semihosting/common-semi.c | 16 ++++++++++++++++ include/qemu/timer.h | 2 ++ util/qemu-timer-common.c | 4 ++++ 3 files changed, 22 insertions(+) diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index f0cf5f10f5..b1368d945c 100644 --- a/hw/semihosting/common-semi.c +++ b/hw/semihosting/common-semi.c @@ -38,6 +38,7 @@ #include "hw/semihosting/console.h" #include "hw/semihosting/common-semi.h" #include "qemu/log.h" +#include "qemu/timer.h" #ifdef CONFIG_USER_ONLY #include "qemu.h" @@ -73,6 +74,8 @@ #define TARGET_SYS_EXIT 0x18 #define TARGET_SYS_SYNCCACHE 0x19 #define TARGET_SYS_EXIT_EXTENDED 0x20 +#define TARGET_SYS_ELAPSED 0x30 +#define TARGET_SYS_TICKFREQ 0x31 /* ADP_Stopped_ApplicationExit is used for exit(0), * anything else is implemented as exit(1) */ @@ -837,6 +840,7 @@ target_ulong do_common_semihosting(CPUState *cs) uint32_t ret; uint32_t len; GuestFD *gf; + int64_t elapsed; (void) env; /* Used implicitly by arm lock_user macro */ nr = common_semi_arg(cs, 0) & 0xffffffffU; @@ -1246,6 +1250,18 @@ target_ulong do_common_semihosting(CPUState *cs) } gdb_exit(cs->env_ptr, ret); exit(ret); + case TARGET_SYS_ELAPSED: + elapsed = get_clock() - clock_start; + if (sizeof(target_ulong) == 8) { + SET_ARG(0, elapsed); + } else { + SET_ARG(0, (uint32_t) elapsed); + SET_ARG(1, (uint32_t) (elapsed >> 32)); + } + return 0; + case TARGET_SYS_TICKFREQ: + /* qemu always uses nsec */ + return 1000000000; case TARGET_SYS_SYNCCACHE: /* * Clean the D-cache and invalidate the I-cache for the specified diff --git a/include/qemu/timer.h b/include/qemu/timer.h index bdecc5b41f..ca6fae51f1 100644 --- a/include/qemu/timer.h +++ b/include/qemu/timer.h @@ -806,6 +806,8 @@ static inline int64_t get_clock_realtime(void) return tv.tv_sec * 1000000000LL + (tv.tv_usec * 1000); } +extern int64_t clock_start; + /* Warning: don't insert tracepoints into these functions, they are also used by simpletrace backend and tracepoints would cause an infinite recursion! */ diff --git a/util/qemu-timer-common.c b/util/qemu-timer-common.c index baf3317f74..cc1326f726 100644 --- a/util/qemu-timer-common.c +++ b/util/qemu-timer-common.c @@ -27,6 +27,8 @@ /***********************************************************/ /* real time host monotonic timer */ +int64_t clock_start; + #ifdef _WIN32 int64_t clock_freq; @@ -41,6 +43,7 @@ static void __attribute__((constructor)) init_get_clock(void) exit(1); } clock_freq = freq.QuadPart; + clock_start = get_clock(); } #else @@ -55,5 +58,6 @@ static void __attribute__((constructor)) init_get_clock(void) if (clock_gettime(CLOCK_MONOTONIC, &ts) == 0) { use_rt_clock = 1; } + clock_start = get_clock(); } #endif -- 2.29.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 8/9] semihosting: Implement SYS_TMPNAM 2021-01-07 17:07 ` Keith Packard @ 2021-01-07 17:07 ` Keith Packard -1 siblings, 0 replies; 24+ messages in thread From: Keith Packard via @ 2021-01-07 17:07 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, Keith Packard, qemu-riscv, Sagar Karandikar, Bastian Koppelmann, Laurent Vivier, qemu-arm, Alistair Francis, Palmer Dabbelt, Alex Bennée Part of Semihosting for AArch32 and AArch64 Release 2.0 Signed-off-by: Keith Packard <keithp@keithp.com> Message-Id: <20201214200713.3886611-9-keithp@keithp.com> --- hw/semihosting/common-semi.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index b1368d945c..b0648c3812 100644 --- a/hw/semihosting/common-semi.c +++ b/hw/semihosting/common-semi.c @@ -835,6 +835,7 @@ target_ulong do_common_semihosting(CPUState *cs) CPUArchState *env = cs->env_ptr; target_ulong args; target_ulong arg0, arg1, arg2, arg3; + target_ulong ul_ret; char * s; int nr; uint32_t ret; @@ -998,8 +999,24 @@ target_ulong do_common_semihosting(CPUState *cs) return guestfd_fns[gf->type].flenfn(cs, gf); case TARGET_SYS_TMPNAM: - qemu_log_mask(LOG_UNIMP, "%s: SYS_TMPNAM not implemented", __func__); - return -1; + GET_ARG(0); + GET_ARG(1); + GET_ARG(2); + if (asprintf(&s, "/tmp/qemu-%x%02x", getpid(), + (int) (arg1 & 0xff)) < 0) { + return -1; + } + ul_ret = (target_ulong) -1; + + /* Make sure there's enough space in the buffer */ + if (strlen(s) < arg2) { + char *output = lock_user(VERIFY_WRITE, arg0, arg2, 0); + strcpy(output, s); + unlock_user(output, arg0, arg2); + ul_ret = 0; + } + free(s); + return ul_ret; case TARGET_SYS_REMOVE: GET_ARG(0); GET_ARG(1); -- 2.29.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 8/9] semihosting: Implement SYS_TMPNAM @ 2021-01-07 17:07 ` Keith Packard 0 siblings, 0 replies; 24+ messages in thread From: Keith Packard @ 2021-01-07 17:07 UTC (permalink / raw) To: qemu-devel Cc: Alex Bennée, Alistair Francis, Bastian Koppelmann, Laurent Vivier, Palmer Dabbelt, Peter Maydell, qemu-arm, qemu-riscv, Sagar Karandikar, Keith Packard Part of Semihosting for AArch32 and AArch64 Release 2.0 Signed-off-by: Keith Packard <keithp@keithp.com> Message-Id: <20201214200713.3886611-9-keithp@keithp.com> --- hw/semihosting/common-semi.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index b1368d945c..b0648c3812 100644 --- a/hw/semihosting/common-semi.c +++ b/hw/semihosting/common-semi.c @@ -835,6 +835,7 @@ target_ulong do_common_semihosting(CPUState *cs) CPUArchState *env = cs->env_ptr; target_ulong args; target_ulong arg0, arg1, arg2, arg3; + target_ulong ul_ret; char * s; int nr; uint32_t ret; @@ -998,8 +999,24 @@ target_ulong do_common_semihosting(CPUState *cs) return guestfd_fns[gf->type].flenfn(cs, gf); case TARGET_SYS_TMPNAM: - qemu_log_mask(LOG_UNIMP, "%s: SYS_TMPNAM not implemented", __func__); - return -1; + GET_ARG(0); + GET_ARG(1); + GET_ARG(2); + if (asprintf(&s, "/tmp/qemu-%x%02x", getpid(), + (int) (arg1 & 0xff)) < 0) { + return -1; + } + ul_ret = (target_ulong) -1; + + /* Make sure there's enough space in the buffer */ + if (strlen(s) < arg2) { + char *output = lock_user(VERIFY_WRITE, arg0, arg2, 0); + strcpy(output, s); + unlock_user(output, arg0, arg2); + ul_ret = 0; + } + free(s); + return ul_ret; case TARGET_SYS_REMOVE: GET_ARG(0); GET_ARG(1); -- 2.29.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 9/9] semihosting: Implement SYS_ISERROR 2021-01-07 17:07 ` Keith Packard @ 2021-01-07 17:07 ` Keith Packard -1 siblings, 0 replies; 24+ messages in thread From: Keith Packard via @ 2021-01-07 17:07 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, Keith Packard, qemu-riscv, Sagar Karandikar, Bastian Koppelmann, Laurent Vivier, qemu-arm, Alistair Francis, Palmer Dabbelt, Alex Bennée Part of Semihosting for AArch32 and AArch64 Release 2.0 Signed-off-by: Keith Packard <keithp@keithp.com> Message-Id: <20201214200713.3886611-10-keithp@keithp.com> --- hw/semihosting/common-semi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index b0648c3812..abc15bf219 100644 --- a/hw/semihosting/common-semi.c +++ b/hw/semihosting/common-semi.c @@ -59,6 +59,7 @@ #define TARGET_SYS_WRITE 0x05 #define TARGET_SYS_READ 0x06 #define TARGET_SYS_READC 0x07 +#define TARGET_SYS_ISERROR 0x08 #define TARGET_SYS_ISTTY 0x09 #define TARGET_SYS_SEEK 0x0a #define TARGET_SYS_FLEN 0x0c @@ -967,6 +968,9 @@ target_ulong do_common_semihosting(CPUState *cs) return guestfd_fns[gf->type].readfn(cs, gf, arg1, len); case TARGET_SYS_READC: return qemu_semihosting_console_inc(cs->env_ptr); + case TARGET_SYS_ISERROR: + GET_ARG(0); + return (target_long) arg0 < 0 ? 1 : 0; case TARGET_SYS_ISTTY: GET_ARG(0); -- 2.29.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 9/9] semihosting: Implement SYS_ISERROR @ 2021-01-07 17:07 ` Keith Packard 0 siblings, 0 replies; 24+ messages in thread From: Keith Packard @ 2021-01-07 17:07 UTC (permalink / raw) To: qemu-devel Cc: Alex Bennée, Alistair Francis, Bastian Koppelmann, Laurent Vivier, Palmer Dabbelt, Peter Maydell, qemu-arm, qemu-riscv, Sagar Karandikar, Keith Packard Part of Semihosting for AArch32 and AArch64 Release 2.0 Signed-off-by: Keith Packard <keithp@keithp.com> Message-Id: <20201214200713.3886611-10-keithp@keithp.com> --- hw/semihosting/common-semi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index b0648c3812..abc15bf219 100644 --- a/hw/semihosting/common-semi.c +++ b/hw/semihosting/common-semi.c @@ -59,6 +59,7 @@ #define TARGET_SYS_WRITE 0x05 #define TARGET_SYS_READ 0x06 #define TARGET_SYS_READC 0x07 +#define TARGET_SYS_ISERROR 0x08 #define TARGET_SYS_ISTTY 0x09 #define TARGET_SYS_SEEK 0x0a #define TARGET_SYS_FLEN 0x0c @@ -967,6 +968,9 @@ target_ulong do_common_semihosting(CPUState *cs) return guestfd_fns[gf->type].readfn(cs, gf, arg1, len); case TARGET_SYS_READC: return qemu_semihosting_console_inc(cs->env_ptr); + case TARGET_SYS_ISERROR: + GET_ARG(0); + return (target_long) arg0 < 0 ? 1 : 0; case TARGET_SYS_ISTTY: GET_ARG(0); -- 2.29.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 0/9] Add RISC-V semihosting 0.2. Finish ARM semihosting 2.0 2021-01-07 17:07 ` Keith Packard @ 2021-01-08 22:32 ` Alex Bennée -1 siblings, 0 replies; 24+ messages in thread From: Alex Bennée @ 2021-01-08 22:32 UTC (permalink / raw) To: Keith Packard Cc: Peter Maydell, qemu-riscv, Sagar Karandikar, Bastian Koppelmann, qemu-devel, Laurent Vivier, qemu-arm, Palmer Dabbelt, Alistair Francis Keith Packard <keithp@keithp.com> writes: > This series adds support for RISC-V Semihosting, version 0.2 as > specified here: > > https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 > > This specification references the ARM semihosting release 2.0 as > specified here: > > https://static.docs.arm.com/100863/0200/semihosting.pdf > > That specification includes several semihosting calls which were not > previously implemented. This series includes implementations for the > remaining calls so that both RISC-V and ARM versions are now complete. > > Tests for release 2.0 can be found in picolibc on the semihost-2.0-all > branch: > > https://github.com/picolibc/picolibc/tree/semihost-2.0-all > > These tests uncovered a bug in the SYS_HEAPINFO implementation for > ARM, which has been fixed in this series as well. > > The series is structured as follows: > > 1. Move shared semihosting files > 2. Change public common semihosting APIs > 3. Change internal semihosting interfaces > 4. Fix SYS_HEAPINFO crash on ARM > 5-6. Add RISC-V semihosting implementation > 7-9. Add missing semihosting operations from release 2.0 Queued to semihosting/next, thanks. -- Alex Bennée ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 0/9] Add RISC-V semihosting 0.2. Finish ARM semihosting 2.0 @ 2021-01-08 22:32 ` Alex Bennée 0 siblings, 0 replies; 24+ messages in thread From: Alex Bennée @ 2021-01-08 22:32 UTC (permalink / raw) To: Keith Packard Cc: qemu-devel, Alistair Francis, Bastian Koppelmann, Laurent Vivier, Palmer Dabbelt, Peter Maydell, qemu-arm, qemu-riscv, Sagar Karandikar Keith Packard <keithp@keithp.com> writes: > This series adds support for RISC-V Semihosting, version 0.2 as > specified here: > > https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 > > This specification references the ARM semihosting release 2.0 as > specified here: > > https://static.docs.arm.com/100863/0200/semihosting.pdf > > That specification includes several semihosting calls which were not > previously implemented. This series includes implementations for the > remaining calls so that both RISC-V and ARM versions are now complete. > > Tests for release 2.0 can be found in picolibc on the semihost-2.0-all > branch: > > https://github.com/picolibc/picolibc/tree/semihost-2.0-all > > These tests uncovered a bug in the SYS_HEAPINFO implementation for > ARM, which has been fixed in this series as well. > > The series is structured as follows: > > 1. Move shared semihosting files > 2. Change public common semihosting APIs > 3. Change internal semihosting interfaces > 4. Fix SYS_HEAPINFO crash on ARM > 5-6. Add RISC-V semihosting implementation > 7-9. Add missing semihosting operations from release 2.0 Queued to semihosting/next, thanks. -- Alex Bennée ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 0/8] Add RISC-V semihosting 0.2. Finish ARM semihosting 2.0
@ 2020-12-14 14:58 Alex Bennée
2020-12-14 20:07 ` [PATCH 0/9] " Keith Packard via
0 siblings, 1 reply; 24+ messages in thread
From: Alex Bennée @ 2020-12-14 14:58 UTC (permalink / raw)
To: Keith Packard
Cc: Peter Maydell, qemu-riscv, Sagar Karandikar, Bastian Koppelmann,
qemu-devel, Laurent Vivier, qemu-arm, Palmer Dabbelt,
Alistair Francis
Alex Bennée <alex.bennee@linaro.org> writes:
> Keith Packard <keithp@keithp.com> writes:
>
>> This series adds support for RISC-V Semihosting, version 0.2 as
>> specified here:
>>
>> https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2
>>
>> This specification references the ARM semihosting release 2.0 as specified here:
>>
>> https://static.docs.arm.com/100863/0200/semihosting.pdf
>>
>> That specification includes several semihosting calls which were not
>> previously implemented. This series includes implementations for the
>> remaining calls so that both RISC-V and ARM versions are now complete.
>>
>> Tests for release 2.0 can be found in picolibc on the semihost-2.0-all
>> branch:
>>
>> https://github.com/picolibc/picolibc/tree/semihost-2.0-all
>>
>> These tests uncovered a bug in the SYS_HEAPINFO implementation for
>> ARM, which has been fixed in this series as well.
>>
>> The series is structured as follows:
>>
>> 1. Move shared semihosting files
>> 2. Change public common semihosting APIs
>> 3. Change internal semihosting interfaces
>> 4. Fix SYS_HEAPINFO crash on ARM
>> 5. Add RISC-V semihosting implementation
>> 6-8. Add missing semihosting operations from release 2.0
>>
>> Signed-off-by: Keith Packard <keithp@keithp.com>
>
> Queued to semihosting/next, thanks.
Hmm scratch that... it fails in a number of linux-user only builds with:
/usr/bin/ld: libqemu-aarch64_be-linux-user.fa.p/linux-user_aarch64_cpu_loop.c.o: in function `cpu_loop':
/builds/stsquad/qemu/build/../linux-user/aarch64/cpu_loop.c:133: undefined reference to `do_common_semihosting'
collect2: error: ld returned 1 exit status
[651/2871] Compiling C object libqemu-alpha-linux-user.fa.p/target_alpha_translate.c.o
ninja: build stopped: subcommand failed.
As well as a chunk of the various cross builds, see:
https://gitlab.com/stsquad/qemu/-/pipelines/229443833/failures
On the next re-spin could you include Kito Cheng's patch for linux-user
support and also drop the version numbering from the commit titles so I
don't have to file them off again.
Thanks,
--
Alex Bennée
^ permalink raw reply [flat|nested] 24+ messages in thread* [PATCH 0/9] Add RISC-V semihosting 0.2. Finish ARM semihosting 2.0 2020-12-14 14:58 [PATCH 0/8] " Alex Bennée @ 2020-12-14 20:07 ` Keith Packard via 2020-12-14 20:07 ` Keith Packard 0 siblings, 1 reply; 24+ messages in thread From: Keith Packard via @ 2020-12-14 20:07 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, Keith Packard, qemu-riscv, Sagar Karandikar, Bastian Koppelmann, Laurent Vivier, qemu-arm, Alistair Francis, Palmer Dabbelt, Alex Bennée This series adds support for RISC-V Semihosting, version 0.2 as specified here: https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 This specification references the ARM semihosting release 2.0 as specified here: https://static.docs.arm.com/100863/0200/semihosting.pdf That specification includes several semihosting calls which were not previously implemented. This series includes implementations for the remaining calls so that both RISC-V and ARM versions are now complete. Tests for release 2.0 can be found in picolibc on the semihost-2.0-all branch: https://github.com/picolibc/picolibc/tree/semihost-2.0-all These tests uncovered a bug in the SYS_HEAPINFO implementation for ARM, which has been fixed in this series as well. The series is structured as follows: 1. Move shared semihosting files 2. Change public common semihosting APIs 3. Change internal semihosting interfaces 4. Fix SYS_HEAPINFO crash on ARM 5-6. Add RISC-V semihosting implementation 7-9. Add missing semihosting operations from release 2.0 Signed-off-by: Keith Packard <keithp@keithp.com> ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 4/9] semihosting: Support SYS_HEAPINFO when env->boot_info is not set 2020-12-14 20:07 ` [PATCH 0/9] " Keith Packard via @ 2020-12-14 20:07 ` Keith Packard 0 siblings, 0 replies; 24+ messages in thread From: Keith Packard via @ 2020-12-14 20:07 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, Keith Packard, qemu-riscv, Sagar Karandikar, Bastian Koppelmann, Laurent Vivier, qemu-arm, Alistair Francis, Palmer Dabbelt, Alex Bennée env->boot_info is only set in some ARM startup paths, so we cannot rely on it to support the SYS_HEAPINFO semihosting function. When not available, fallback to finding a RAM memory region containing the current stack and use the base of that. Signed-off-by: Keith Packard <keithp@keithp.com> --- v2 Explicitly convert 64-bits to 128-bits in find_region_base for hosts that don't have native 128-bit int type. --- hw/semihosting/common-semi.c | 43 +++++++++++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index 33c82f73b1..f09deff4d3 100644 --- a/hw/semihosting/common-semi.c +++ b/hw/semihosting/common-semi.c @@ -137,6 +137,36 @@ typedef struct GuestFD { static GArray *guestfd_array; +#ifndef CONFIG_USER_ONLY +#include "exec/address-spaces.h" +/* + * Find the base of a RAM region containing the specified address + */ +static inline hwaddr +common_semi_find_region_base(hwaddr addr) +{ + MemoryRegion *subregion; + + /* + * Find the chunk of R/W memory containing the address. This is + * used for the SYS_HEAPINFO semihosting call, which should + * probably be using information from the loaded application. + */ + QTAILQ_FOREACH(subregion, &get_system_memory()->subregions, + subregions_link) { + if (subregion->ram && !subregion->readonly) { + Int128 top128 = int128_add(int128_make64(subregion->addr), + subregion->size); + Int128 addr128 = int128_make64(addr); + if (subregion->addr <= addr && int128_lt(addr128, top128)) { + return subregion->addr; + } + } + } + return 0; +} +#endif + #ifdef TARGET_ARM static inline target_ulong common_semi_arg(CPUState *cs, int argno) @@ -175,7 +205,18 @@ common_semi_rambase(CPUState *cs) { CPUArchState *env = cs->env_ptr; const struct arm_boot_info *info = env->boot_info; - return info->loader_start; + target_ulong sp; + + if (info) { + return info->loader_start; + } + + if (is_a64(env)) { + sp = env->xregs[31]; + } else { + sp = env->regs[13]; + } + return common_semi_find_region_base(sp); } #endif -- 2.29.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 4/9] semihosting: Support SYS_HEAPINFO when env->boot_info is not set @ 2020-12-14 20:07 ` Keith Packard 0 siblings, 0 replies; 24+ messages in thread From: Keith Packard @ 2020-12-14 20:07 UTC (permalink / raw) To: qemu-devel Cc: Alex Bennée, Alistair Francis, Bastian Koppelmann, Laurent Vivier, Palmer Dabbelt, Peter Maydell, qemu-arm, qemu-riscv, Sagar Karandikar, Keith Packard env->boot_info is only set in some ARM startup paths, so we cannot rely on it to support the SYS_HEAPINFO semihosting function. When not available, fallback to finding a RAM memory region containing the current stack and use the base of that. Signed-off-by: Keith Packard <keithp@keithp.com> --- v2 Explicitly convert 64-bits to 128-bits in find_region_base for hosts that don't have native 128-bit int type. --- hw/semihosting/common-semi.c | 43 +++++++++++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index 33c82f73b1..f09deff4d3 100644 --- a/hw/semihosting/common-semi.c +++ b/hw/semihosting/common-semi.c @@ -137,6 +137,36 @@ typedef struct GuestFD { static GArray *guestfd_array; +#ifndef CONFIG_USER_ONLY +#include "exec/address-spaces.h" +/* + * Find the base of a RAM region containing the specified address + */ +static inline hwaddr +common_semi_find_region_base(hwaddr addr) +{ + MemoryRegion *subregion; + + /* + * Find the chunk of R/W memory containing the address. This is + * used for the SYS_HEAPINFO semihosting call, which should + * probably be using information from the loaded application. + */ + QTAILQ_FOREACH(subregion, &get_system_memory()->subregions, + subregions_link) { + if (subregion->ram && !subregion->readonly) { + Int128 top128 = int128_add(int128_make64(subregion->addr), + subregion->size); + Int128 addr128 = int128_make64(addr); + if (subregion->addr <= addr && int128_lt(addr128, top128)) { + return subregion->addr; + } + } + } + return 0; +} +#endif + #ifdef TARGET_ARM static inline target_ulong common_semi_arg(CPUState *cs, int argno) @@ -175,7 +205,18 @@ common_semi_rambase(CPUState *cs) { CPUArchState *env = cs->env_ptr; const struct arm_boot_info *info = env->boot_info; - return info->loader_start; + target_ulong sp; + + if (info) { + return info->loader_start; + } + + if (is_a64(env)) { + sp = env->xregs[31]; + } else { + sp = env->regs[13]; + } + return common_semi_find_region_base(sp); } #endif -- 2.29.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
end of thread, other threads:[~2021-01-08 22:34 UTC | newest] Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-01-07 17:07 [PATCH 0/9] Add RISC-V semihosting 0.2. Finish ARM semihosting 2.0 Keith Packard via 2021-01-07 17:07 ` Keith Packard 2021-01-07 17:07 ` [PATCH 1/9] semihosting: Move ARM semihosting code to shared directories Keith Packard via 2021-01-07 17:07 ` Keith Packard 2021-01-07 17:07 ` [PATCH 2/9] semihosting: Change common-semi API to be architecture-independent Keith Packard via 2021-01-07 17:07 ` Keith Packard 2021-01-07 17:07 ` [PATCH 3/9] semihosting: Change internal common-semi interfaces to use CPUState * Keith Packard via 2021-01-07 17:07 ` Keith Packard 2021-01-07 17:07 ` [PATCH 4/9] semihosting: Support SYS_HEAPINFO when env->boot_info is not set Keith Packard via 2021-01-07 17:07 ` Keith Packard 2021-01-07 17:07 ` [PATCH 5/9] riscv: Add semihosting support Keith Packard via 2021-01-07 17:07 ` Keith Packard 2021-01-07 17:07 ` [PATCH 6/9] riscv: Add semihosting support for user mode Keith Packard via 2021-01-07 17:07 ` Keith Packard 2021-01-07 17:07 ` [PATCH 7/9] semihosting: Implement SYS_ELAPSED and SYS_TICKFREQ Keith Packard via 2021-01-07 17:07 ` Keith Packard 2021-01-07 17:07 ` [PATCH 8/9] semihosting: Implement SYS_TMPNAM Keith Packard via 2021-01-07 17:07 ` Keith Packard 2021-01-07 17:07 ` [PATCH 9/9] semihosting: Implement SYS_ISERROR Keith Packard via 2021-01-07 17:07 ` Keith Packard 2021-01-08 22:32 ` [PATCH 0/9] Add RISC-V semihosting 0.2. Finish ARM semihosting 2.0 Alex Bennée 2021-01-08 22:32 ` Alex Bennée -- strict thread matches above, loose matches on Subject: below -- 2020-12-14 14:58 [PATCH 0/8] " Alex Bennée 2020-12-14 20:07 ` [PATCH 0/9] " Keith Packard via 2020-12-14 20:07 ` [PATCH 4/9] semihosting: Support SYS_HEAPINFO when env->boot_info is not set Keith Packard via 2020-12-14 20:07 ` Keith Packard
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