[PATCH] drm/msm: Only enable A6xx LLCC code on A6xx

[PATCH] drm/msm: Only enable A6xx LLCC code on A6xx

[Konrad Dybcio]

Using this code on A5xx (and probably older too) causes a
smmu bug.

Fixes: 474dadb8b0d5 ("drm/msm/a6xx: Add support for using system cache(LLC)")
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
---
 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 21 ++++++++++++---------
 drivers/gpu/drm/msm/adreno/adreno_gpu.h |  5 +++++
 2 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 6cf9975e951e..f09175698827 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -191,8 +191,6 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu,
 		struct platform_device *pdev)
 {
 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
-	struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
-	struct io_pgtable_domain_attr pgtbl_cfg;
 	struct iommu_domain *iommu;
 	struct msm_mmu *mmu;
 	struct msm_gem_address_space *aspace;
@@ -202,13 +200,18 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu,
 	if (!iommu)
 		return NULL;
 
-	/*
-	 * This allows GPU to set the bus attributes required to use system
-	 * cache on behalf of the iommu page table walker.
-	 */
-	if (!IS_ERR(a6xx_gpu->htw_llc_slice)) {
-		pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
-		iommu_domain_set_attr(iommu, DOMAIN_ATTR_IO_PGTABLE_CFG, &pgtbl_cfg);
+
+	if (adreno_is_a6xx(adreno_gpu)) {
+		struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
+		struct io_pgtable_domain_attr pgtbl_cfg;
+		/*
+		* This allows GPU to set the bus attributes required to use system
+		* cache on behalf of the iommu page table walker.
+		*/
+		if (!IS_ERR(a6xx_gpu->htw_llc_slice)) {
+			pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
+			iommu_domain_set_attr(iommu, DOMAIN_ATTR_IO_PGTABLE_CFG, &pgtbl_cfg);
+		}
 	}
 
 	mmu = msm_iommu_new(&pdev->dev, iommu);
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 4574d85c5680..08421fa54a50 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -226,6 +226,11 @@ static inline int adreno_is_a540(struct adreno_gpu *gpu)
 	return gpu->revn == 540;
 }
 
+static inline bool adreno_is_a6xx(struct adreno_gpu *gpu)
+{
+	return ((gpu->revn < 700 && gpu->revn > 599));
+}
+
 static inline int adreno_is_a618(struct adreno_gpu *gpu)
 {
        return gpu->revn == 618;
-- 
2.29.2

[PATCH] drm/msm: Only enable A6xx LLCC code on A6xx

[Konrad Dybcio]

Using this code on A5xx (and probably older too) causes a
smmu bug.

Fixes: 474dadb8b0d5 ("drm/msm/a6xx: Add support for using system cache(LLC)")
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
---
 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 21 ++++++++++++---------
 drivers/gpu/drm/msm/adreno/adreno_gpu.h |  5 +++++
 2 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 6cf9975e951e..f09175698827 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -191,8 +191,6 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu,
 		struct platform_device *pdev)
 {
 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
-	struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
-	struct io_pgtable_domain_attr pgtbl_cfg;
 	struct iommu_domain *iommu;
 	struct msm_mmu *mmu;
 	struct msm_gem_address_space *aspace;
@@ -202,13 +200,18 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu,
 	if (!iommu)
 		return NULL;
 
-	/*
-	 * This allows GPU to set the bus attributes required to use system
-	 * cache on behalf of the iommu page table walker.
-	 */
-	if (!IS_ERR(a6xx_gpu->htw_llc_slice)) {
-		pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
-		iommu_domain_set_attr(iommu, DOMAIN_ATTR_IO_PGTABLE_CFG, &pgtbl_cfg);
+
+	if (adreno_is_a6xx(adreno_gpu)) {
+		struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
+		struct io_pgtable_domain_attr pgtbl_cfg;
+		/*
+		* This allows GPU to set the bus attributes required to use system
+		* cache on behalf of the iommu page table walker.
+		*/
+		if (!IS_ERR(a6xx_gpu->htw_llc_slice)) {
+			pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
+			iommu_domain_set_attr(iommu, DOMAIN_ATTR_IO_PGTABLE_CFG, &pgtbl_cfg);
+		}
 	}
 
 	mmu = msm_iommu_new(&pdev->dev, iommu);
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 4574d85c5680..08421fa54a50 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -226,6 +226,11 @@ static inline int adreno_is_a540(struct adreno_gpu *gpu)
 	return gpu->revn == 540;
 }
 
+static inline bool adreno_is_a6xx(struct adreno_gpu *gpu)
+{
+	return ((gpu->revn < 700 && gpu->revn > 599));
+}
+
 static inline int adreno_is_a618(struct adreno_gpu *gpu)
 {
        return gpu->revn == 618;
-- 
2.29.2

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Re: [PATCH] drm/msm: Only enable A6xx LLCC code on A6xx

[Jordan Crouse]

On Mon, Jan 04, 2021 at 08:30:41PM +0100, Konrad Dybcio wrote:
> Using this code on A5xx (and probably older too) causes a
> smmu bug.
> 
> Fixes: 474dadb8b0d5 ("drm/msm/a6xx: Add support for using system cache(LLC)")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>

Yep, I can see how this would be not ideal.

Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>

> ---
>  drivers/gpu/drm/msm/adreno/adreno_gpu.c | 21 ++++++++++++---------
>  drivers/gpu/drm/msm/adreno/adreno_gpu.h |  5 +++++
>  2 files changed, 17 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> index 6cf9975e951e..f09175698827 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> @@ -191,8 +191,6 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu,
>  		struct platform_device *pdev)
>  {
>  	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> -	struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
> -	struct io_pgtable_domain_attr pgtbl_cfg;
>  	struct iommu_domain *iommu;
>  	struct msm_mmu *mmu;
>  	struct msm_gem_address_space *aspace;
> @@ -202,13 +200,18 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu,
>  	if (!iommu)
>  		return NULL;
>  
> -	/*
> -	 * This allows GPU to set the bus attributes required to use system
> -	 * cache on behalf of the iommu page table walker.
> -	 */
> -	if (!IS_ERR(a6xx_gpu->htw_llc_slice)) {
> -		pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
> -		iommu_domain_set_attr(iommu, DOMAIN_ATTR_IO_PGTABLE_CFG, &pgtbl_cfg);
> +
> +	if (adreno_is_a6xx(adreno_gpu)) {
> +		struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
> +		struct io_pgtable_domain_attr pgtbl_cfg;
> +		/*
> +		* This allows GPU to set the bus attributes required to use system
> +		* cache on behalf of the iommu page table walker.
> +		*/
> +		if (!IS_ERR(a6xx_gpu->htw_llc_slice)) {
> +			pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
> +			iommu_domain_set_attr(iommu, DOMAIN_ATTR_IO_PGTABLE_CFG, &pgtbl_cfg);
> +		}
>  	}
>  
>  	mmu = msm_iommu_new(&pdev->dev, iommu);
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index 4574d85c5680..08421fa54a50 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -226,6 +226,11 @@ static inline int adreno_is_a540(struct adreno_gpu *gpu)
>  	return gpu->revn == 540;
>  }
>  
> +static inline bool adreno_is_a6xx(struct adreno_gpu *gpu)
> +{
> +	return ((gpu->revn < 700 && gpu->revn > 599));
> +}
> +
>  static inline int adreno_is_a618(struct adreno_gpu *gpu)
>  {
>         return gpu->revn == 618;
> -- 
> 2.29.2
> 

-- 
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH] drm/msm: Only enable A6xx LLCC code on A6xx

[Jordan Crouse]

On Mon, Jan 04, 2021 at 08:30:41PM +0100, Konrad Dybcio wrote:
> Using this code on A5xx (and probably older too) causes a
> smmu bug.
> 
> Fixes: 474dadb8b0d5 ("drm/msm/a6xx: Add support for using system cache(LLC)")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>

Yep, I can see how this would be not ideal.

Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>

> ---
>  drivers/gpu/drm/msm/adreno/adreno_gpu.c | 21 ++++++++++++---------
>  drivers/gpu/drm/msm/adreno/adreno_gpu.h |  5 +++++
>  2 files changed, 17 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> index 6cf9975e951e..f09175698827 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> @@ -191,8 +191,6 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu,
>  		struct platform_device *pdev)
>  {
>  	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> -	struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
> -	struct io_pgtable_domain_attr pgtbl_cfg;
>  	struct iommu_domain *iommu;
>  	struct msm_mmu *mmu;
>  	struct msm_gem_address_space *aspace;
> @@ -202,13 +200,18 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu,
>  	if (!iommu)
>  		return NULL;
>  
> -	/*
> -	 * This allows GPU to set the bus attributes required to use system
> -	 * cache on behalf of the iommu page table walker.
> -	 */
> -	if (!IS_ERR(a6xx_gpu->htw_llc_slice)) {
> -		pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
> -		iommu_domain_set_attr(iommu, DOMAIN_ATTR_IO_PGTABLE_CFG, &pgtbl_cfg);
> +
> +	if (adreno_is_a6xx(adreno_gpu)) {
> +		struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
> +		struct io_pgtable_domain_attr pgtbl_cfg;
> +		/*
> +		* This allows GPU to set the bus attributes required to use system
> +		* cache on behalf of the iommu page table walker.
> +		*/
> +		if (!IS_ERR(a6xx_gpu->htw_llc_slice)) {
> +			pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
> +			iommu_domain_set_attr(iommu, DOMAIN_ATTR_IO_PGTABLE_CFG, &pgtbl_cfg);
> +		}
>  	}
>  
>  	mmu = msm_iommu_new(&pdev->dev, iommu);
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index 4574d85c5680..08421fa54a50 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -226,6 +226,11 @@ static inline int adreno_is_a540(struct adreno_gpu *gpu)
>  	return gpu->revn == 540;
>  }
>  
> +static inline bool adreno_is_a6xx(struct adreno_gpu *gpu)
> +{
> +	return ((gpu->revn < 700 && gpu->revn > 599));
> +}
> +
>  static inline int adreno_is_a618(struct adreno_gpu *gpu)
>  {
>         return gpu->revn == 618;
> -- 
> 2.29.2
> 

-- 
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a Linux Foundation Collaborative Project
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Re: [PATCH] drm/msm: Only enable A6xx LLCC code on A6xx

[Sai Prakash Ranjan]

On 2021-01-05 01:00, Konrad Dybcio wrote:
> Using this code on A5xx (and probably older too) causes a
> smmu bug.
> 
> Fixes: 474dadb8b0d5 ("drm/msm/a6xx: Add support for using system 
> cache(LLC)")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> Tested-by: AngeloGioacchino Del Regno 
> <angelogioacchino.delregno@somainline.org>
> ---

Reviewed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>

>  drivers/gpu/drm/msm/adreno/adreno_gpu.c | 21 ++++++++++++---------
>  drivers/gpu/drm/msm/adreno/adreno_gpu.h |  5 +++++
>  2 files changed, 17 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> index 6cf9975e951e..f09175698827 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> @@ -191,8 +191,6 @@ adreno_iommu_create_address_space(struct msm_gpu 
> *gpu,
>  		struct platform_device *pdev)
>  {
>  	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> -	struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
> -	struct io_pgtable_domain_attr pgtbl_cfg;
>  	struct iommu_domain *iommu;
>  	struct msm_mmu *mmu;
>  	struct msm_gem_address_space *aspace;
> @@ -202,13 +200,18 @@ adreno_iommu_create_address_space(struct msm_gpu 
> *gpu,
>  	if (!iommu)
>  		return NULL;
> 
> -	/*
> -	 * This allows GPU to set the bus attributes required to use system
> -	 * cache on behalf of the iommu page table walker.
> -	 */
> -	if (!IS_ERR(a6xx_gpu->htw_llc_slice)) {
> -		pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
> -		iommu_domain_set_attr(iommu, DOMAIN_ATTR_IO_PGTABLE_CFG, 
> &pgtbl_cfg);
> +
> +	if (adreno_is_a6xx(adreno_gpu)) {
> +		struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
> +		struct io_pgtable_domain_attr pgtbl_cfg;
> +		/*
> +		* This allows GPU to set the bus attributes required to use system
> +		* cache on behalf of the iommu page table walker.
> +		*/
> +		if (!IS_ERR(a6xx_gpu->htw_llc_slice)) {
> +			pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
> +			iommu_domain_set_attr(iommu, DOMAIN_ATTR_IO_PGTABLE_CFG, 
> &pgtbl_cfg);
> +		}
>  	}
> 
>  	mmu = msm_iommu_new(&pdev->dev, iommu);
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index 4574d85c5680..08421fa54a50 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -226,6 +226,11 @@ static inline int adreno_is_a540(struct adreno_gpu 
> *gpu)
>  	return gpu->revn == 540;
>  }
> 
> +static inline bool adreno_is_a6xx(struct adreno_gpu *gpu)
> +{
> +	return ((gpu->revn < 700 && gpu->revn > 599));
> +}
> +
>  static inline int adreno_is_a618(struct adreno_gpu *gpu)
>  {
>         return gpu->revn == 618;

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a 
member
of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH] drm/msm: Only enable A6xx LLCC code on A6xx

[Sai Prakash Ranjan]

On 2021-01-05 01:00, Konrad Dybcio wrote:
> Using this code on A5xx (and probably older too) causes a
> smmu bug.
> 
> Fixes: 474dadb8b0d5 ("drm/msm/a6xx: Add support for using system 
> cache(LLC)")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> Tested-by: AngeloGioacchino Del Regno 
> <angelogioacchino.delregno@somainline.org>
> ---

Reviewed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>

>  drivers/gpu/drm/msm/adreno/adreno_gpu.c | 21 ++++++++++++---------
>  drivers/gpu/drm/msm/adreno/adreno_gpu.h |  5 +++++
>  2 files changed, 17 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> index 6cf9975e951e..f09175698827 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> @@ -191,8 +191,6 @@ adreno_iommu_create_address_space(struct msm_gpu 
> *gpu,
>  		struct platform_device *pdev)
>  {
>  	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> -	struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
> -	struct io_pgtable_domain_attr pgtbl_cfg;
>  	struct iommu_domain *iommu;
>  	struct msm_mmu *mmu;
>  	struct msm_gem_address_space *aspace;
> @@ -202,13 +200,18 @@ adreno_iommu_create_address_space(struct msm_gpu 
> *gpu,
>  	if (!iommu)
>  		return NULL;
> 
> -	/*
> -	 * This allows GPU to set the bus attributes required to use system
> -	 * cache on behalf of the iommu page table walker.
> -	 */
> -	if (!IS_ERR(a6xx_gpu->htw_llc_slice)) {
> -		pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
> -		iommu_domain_set_attr(iommu, DOMAIN_ATTR_IO_PGTABLE_CFG, 
> &pgtbl_cfg);
> +
> +	if (adreno_is_a6xx(adreno_gpu)) {
> +		struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
> +		struct io_pgtable_domain_attr pgtbl_cfg;
> +		/*
> +		* This allows GPU to set the bus attributes required to use system
> +		* cache on behalf of the iommu page table walker.
> +		*/
> +		if (!IS_ERR(a6xx_gpu->htw_llc_slice)) {
> +			pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
> +			iommu_domain_set_attr(iommu, DOMAIN_ATTR_IO_PGTABLE_CFG, 
> &pgtbl_cfg);
> +		}
>  	}
> 
>  	mmu = msm_iommu_new(&pdev->dev, iommu);
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index 4574d85c5680..08421fa54a50 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -226,6 +226,11 @@ static inline int adreno_is_a540(struct adreno_gpu 
> *gpu)
>  	return gpu->revn == 540;
>  }
> 
> +static inline bool adreno_is_a6xx(struct adreno_gpu *gpu)
> +{
> +	return ((gpu->revn < 700 && gpu->revn > 599));
> +}
> +
>  static inline int adreno_is_a618(struct adreno_gpu *gpu)
>  {
>         return gpu->revn == 618;

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a 
member
of Code Aurora Forum, hosted by The Linux Foundation
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Re: [PATCH] drm/msm: Only enable A6xx LLCC code on A6xx

[Rob Clark]

On Wed, Jan 6, 2021 at 8:50 PM Sai Prakash Ranjan
<saiprakash.ranjan@codeaurora.org> wrote:
>
> On 2021-01-05 01:00, Konrad Dybcio wrote:
> > Using this code on A5xx (and probably older too) causes a
> > smmu bug.
> >
> > Fixes: 474dadb8b0d5 ("drm/msm/a6xx: Add support for using system
> > cache(LLC)")
> > Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> > Tested-by: AngeloGioacchino Del Regno
> > <angelogioacchino.delregno@somainline.org>
> > ---
>
> Reviewed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
>
> >  drivers/gpu/drm/msm/adreno/adreno_gpu.c | 21 ++++++++++++---------
> >  drivers/gpu/drm/msm/adreno/adreno_gpu.h |  5 +++++
> >  2 files changed, 17 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> > b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> > index 6cf9975e951e..f09175698827 100644
> > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> > @@ -191,8 +191,6 @@ adreno_iommu_create_address_space(struct msm_gpu
> > *gpu,
> >               struct platform_device *pdev)
> >  {
> >       struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> > -     struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
> > -     struct io_pgtable_domain_attr pgtbl_cfg;
> >       struct iommu_domain *iommu;
> >       struct msm_mmu *mmu;
> >       struct msm_gem_address_space *aspace;
> > @@ -202,13 +200,18 @@ adreno_iommu_create_address_space(struct msm_gpu
> > *gpu,
> >       if (!iommu)
> >               return NULL;
> >
> > -     /*
> > -      * This allows GPU to set the bus attributes required to use system
> > -      * cache on behalf of the iommu page table walker.
> > -      */
> > -     if (!IS_ERR(a6xx_gpu->htw_llc_slice)) {
> > -             pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
> > -             iommu_domain_set_attr(iommu, DOMAIN_ATTR_IO_PGTABLE_CFG,
> > &pgtbl_cfg);
> > +
> > +     if (adreno_is_a6xx(adreno_gpu)) {
> > +             struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
> > +             struct io_pgtable_domain_attr pgtbl_cfg;
> > +             /*
> > +             * This allows GPU to set the bus attributes required to use system
> > +             * cache on behalf of the iommu page table walker.
> > +             */
> > +             if (!IS_ERR(a6xx_gpu->htw_llc_slice)) {
> > +                     pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
> > +                     iommu_domain_set_attr(iommu, DOMAIN_ATTR_IO_PGTABLE_CFG,
> > &pgtbl_cfg);
> > +             }

I'm applying for -fixes as this is an obvious problem..  But kinda
thinking that we should try to move it into an a6xx specific
create_address_space() (or wrapper for the generic fxn)

Sai/Jordan, could I talk one of you into trying to clean this up
better for next cycle?

BR,
-R

> >       }
> >
> >       mmu = msm_iommu_new(&pdev->dev, iommu);
> > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > index 4574d85c5680..08421fa54a50 100644
> > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > @@ -226,6 +226,11 @@ static inline int adreno_is_a540(struct adreno_gpu
> > *gpu)
> >       return gpu->revn == 540;
> >  }
> >
> > +static inline bool adreno_is_a6xx(struct adreno_gpu *gpu)
> > +{
> > +     return ((gpu->revn < 700 && gpu->revn > 599));
> > +}
> > +
> >  static inline int adreno_is_a618(struct adreno_gpu *gpu)
> >  {
> >         return gpu->revn == 618;
>
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
> member
> of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH] drm/msm: Only enable A6xx LLCC code on A6xx

[Rob Clark]

On Wed, Jan 6, 2021 at 8:50 PM Sai Prakash Ranjan
<saiprakash.ranjan@codeaurora.org> wrote:
>
> On 2021-01-05 01:00, Konrad Dybcio wrote:
> > Using this code on A5xx (and probably older too) causes a
> > smmu bug.
> >
> > Fixes: 474dadb8b0d5 ("drm/msm/a6xx: Add support for using system
> > cache(LLC)")
> > Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> > Tested-by: AngeloGioacchino Del Regno
> > <angelogioacchino.delregno@somainline.org>
> > ---
>
> Reviewed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
>
> >  drivers/gpu/drm/msm/adreno/adreno_gpu.c | 21 ++++++++++++---------
> >  drivers/gpu/drm/msm/adreno/adreno_gpu.h |  5 +++++
> >  2 files changed, 17 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> > b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> > index 6cf9975e951e..f09175698827 100644
> > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> > @@ -191,8 +191,6 @@ adreno_iommu_create_address_space(struct msm_gpu
> > *gpu,
> >               struct platform_device *pdev)
> >  {
> >       struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> > -     struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
> > -     struct io_pgtable_domain_attr pgtbl_cfg;
> >       struct iommu_domain *iommu;
> >       struct msm_mmu *mmu;
> >       struct msm_gem_address_space *aspace;
> > @@ -202,13 +200,18 @@ adreno_iommu_create_address_space(struct msm_gpu
> > *gpu,
> >       if (!iommu)
> >               return NULL;
> >
> > -     /*
> > -      * This allows GPU to set the bus attributes required to use system
> > -      * cache on behalf of the iommu page table walker.
> > -      */
> > -     if (!IS_ERR(a6xx_gpu->htw_llc_slice)) {
> > -             pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
> > -             iommu_domain_set_attr(iommu, DOMAIN_ATTR_IO_PGTABLE_CFG,
> > &pgtbl_cfg);
> > +
> > +     if (adreno_is_a6xx(adreno_gpu)) {
> > +             struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
> > +             struct io_pgtable_domain_attr pgtbl_cfg;
> > +             /*
> > +             * This allows GPU to set the bus attributes required to use system
> > +             * cache on behalf of the iommu page table walker.
> > +             */
> > +             if (!IS_ERR(a6xx_gpu->htw_llc_slice)) {
> > +                     pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
> > +                     iommu_domain_set_attr(iommu, DOMAIN_ATTR_IO_PGTABLE_CFG,
> > &pgtbl_cfg);
> > +             }

I'm applying for -fixes as this is an obvious problem..  But kinda
thinking that we should try to move it into an a6xx specific
create_address_space() (or wrapper for the generic fxn)

Sai/Jordan, could I talk one of you into trying to clean this up
better for next cycle?

BR,
-R

> >       }
> >
> >       mmu = msm_iommu_new(&pdev->dev, iommu);
> > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > index 4574d85c5680..08421fa54a50 100644
> > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > @@ -226,6 +226,11 @@ static inline int adreno_is_a540(struct adreno_gpu
> > *gpu)
> >       return gpu->revn == 540;
> >  }
> >
> > +static inline bool adreno_is_a6xx(struct adreno_gpu *gpu)
> > +{
> > +     return ((gpu->revn < 700 && gpu->revn > 599));
> > +}
> > +
> >  static inline int adreno_is_a618(struct adreno_gpu *gpu)
> >  {
> >         return gpu->revn == 618;
>
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
> member
> of Code Aurora Forum, hosted by The Linux Foundation
_______________________________________________
dri-devel mailing list
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Re: [PATCH] drm/msm: Only enable A6xx LLCC code on A6xx

[Sai Prakash Ranjan]

Hi Rob, Konrad,

On 2021-01-07 22:56, Rob Clark wrote:
> On Wed, Jan 6, 2021 at 8:50 PM Sai Prakash Ranjan
> <saiprakash.ranjan@codeaurora.org> wrote:
>>
>> On 2021-01-05 01:00, Konrad Dybcio wrote:
>> > Using this code on A5xx (and probably older too) causes a
>> > smmu bug.
>> >
>> > Fixes: 474dadb8b0d5 ("drm/msm/a6xx: Add support for using system
>> > cache(LLC)")
>> > Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>> > Tested-by: AngeloGioacchino Del Regno
>> > <angelogioacchino.delregno@somainline.org>
>> > ---
>>
>> Reviewed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
>>
>> >  drivers/gpu/drm/msm/adreno/adreno_gpu.c | 21 ++++++++++++---------
>> >  drivers/gpu/drm/msm/adreno/adreno_gpu.h |  5 +++++
>> >  2 files changed, 17 insertions(+), 9 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>> > b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>> > index 6cf9975e951e..f09175698827 100644
>> > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>> > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>> > @@ -191,8 +191,6 @@ adreno_iommu_create_address_space(struct msm_gpu
>> > *gpu,
>> >               struct platform_device *pdev)
>> >  {
>> >       struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
>> > -     struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
>> > -     struct io_pgtable_domain_attr pgtbl_cfg;
>> >       struct iommu_domain *iommu;
>> >       struct msm_mmu *mmu;
> >       struct msm_gem_address_space *aspace;
>> > @@ -202,13 +200,18 @@ adreno_iommu_create_address_space(struct msm_gpu
>> > *gpu,
>> >       if (!iommu)
>> >               return NULL;
>> >
>> > -     /*
>> > -      * This allows GPU to set the bus attributes required to use system
>> > -      * cache on behalf of the iommu page table walker.
>> > -      */
>> > -     if (!IS_ERR(a6xx_gpu->htw_llc_slice)) {
>> > -             pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
>> > -             iommu_domain_set_attr(iommu, DOMAIN_ATTR_IO_PGTABLE_CFG,
>> > &pgtbl_cfg);
>> > +
>> > +     if (adreno_is_a6xx(adreno_gpu)) {
>> > +             struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
>> > +             struct io_pgtable_domain_attr pgtbl_cfg;
>> > +             /*
>> > +             * This allows GPU to set the bus attributes required to use system
>> > +             * cache on behalf of the iommu page table walker.
>> > +             */
>> > +             if (!IS_ERR(a6xx_gpu->htw_llc_slice)) {
>> > +                     pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
>> > +                     iommu_domain_set_attr(iommu, DOMAIN_ATTR_IO_PGTABLE_CFG,
>> > &pgtbl_cfg);
>> > +             }
>
> I'm applying for -fixes as this is an obvious problem..  But kinda
> thinking that we should try to move it into an a6xx specific
> create_address_space() (or wrapper for the generic fxn)
>
> Sai/Jordan, could I talk one of you into trying to clean this up
> better for next cycle?
>

Looking more closely(sorry I should have before), the quirk setting
is already guarded by htw_llc_slice check but what is happening here is
that check is not proper when LLCC is disabled i.e., CONFIG_QCOM_LLCC=n.
When LLCC is disabled, htw_llc_slice is set to NULL and the !IS_ERR
check passes because it doesn't take care of NULL and quirk is
set causing bugs. So the proper fix would be to use IS_ERR_OR_NULL for
the check.

Konrad, can you please test this below change without your change?

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 130661898546..3b798e883f82 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1117,7 +1117,7 @@ static void a6xx_llc_slices_init(struct platform_device *pdev,
        a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU);
        a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW);

-       if (IS_ERR(a6xx_gpu->llc_slice) && IS_ERR(a6xx_gpu->htw_llc_slice))
+       if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice))
                a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
 }

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 6cf9975e951e..dbd5cacddb9c 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -206,7 +206,7 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu,
         * This allows GPU to set the bus attributes required to use system
         * cache on behalf of the iommu page table walker.
         */
-       if (!IS_ERR(a6xx_gpu->htw_llc_slice)) {
+       if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice)) {
                pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
                iommu_domain_set_attr(iommu, DOMAIN_ATTR_IO_PGTABLE_CFG, &pgtbl_cfg);
        }


Thanks,
Sai

--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH] drm/msm: Only enable A6xx LLCC code on A6xx

[Sai Prakash Ranjan]

Hi Rob, Konrad,

On 2021-01-07 22:56, Rob Clark wrote:
> On Wed, Jan 6, 2021 at 8:50 PM Sai Prakash Ranjan
> <saiprakash.ranjan@codeaurora.org> wrote:
>>
>> On 2021-01-05 01:00, Konrad Dybcio wrote:
>> > Using this code on A5xx (and probably older too) causes a
>> > smmu bug.
>> >
>> > Fixes: 474dadb8b0d5 ("drm/msm/a6xx: Add support for using system
>> > cache(LLC)")
>> > Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>> > Tested-by: AngeloGioacchino Del Regno
>> > <angelogioacchino.delregno@somainline.org>
>> > ---
>>
>> Reviewed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
>>
>> >  drivers/gpu/drm/msm/adreno/adreno_gpu.c | 21 ++++++++++++---------
>> >  drivers/gpu/drm/msm/adreno/adreno_gpu.h |  5 +++++
>> >  2 files changed, 17 insertions(+), 9 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>> > b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>> > index 6cf9975e951e..f09175698827 100644
>> > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>> > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>> > @@ -191,8 +191,6 @@ adreno_iommu_create_address_space(struct msm_gpu
>> > *gpu,
>> >               struct platform_device *pdev)
>> >  {
>> >       struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
>> > -     struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
>> > -     struct io_pgtable_domain_attr pgtbl_cfg;
>> >       struct iommu_domain *iommu;
>> >       struct msm_mmu *mmu;
> >       struct msm_gem_address_space *aspace;
>> > @@ -202,13 +200,18 @@ adreno_iommu_create_address_space(struct msm_gpu
>> > *gpu,
>> >       if (!iommu)
>> >               return NULL;
>> >
>> > -     /*
>> > -      * This allows GPU to set the bus attributes required to use system
>> > -      * cache on behalf of the iommu page table walker.
>> > -      */
>> > -     if (!IS_ERR(a6xx_gpu->htw_llc_slice)) {
>> > -             pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
>> > -             iommu_domain_set_attr(iommu, DOMAIN_ATTR_IO_PGTABLE_CFG,
>> > &pgtbl_cfg);
>> > +
>> > +     if (adreno_is_a6xx(adreno_gpu)) {
>> > +             struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
>> > +             struct io_pgtable_domain_attr pgtbl_cfg;
>> > +             /*
>> > +             * This allows GPU to set the bus attributes required to use system
>> > +             * cache on behalf of the iommu page table walker.
>> > +             */
>> > +             if (!IS_ERR(a6xx_gpu->htw_llc_slice)) {
>> > +                     pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
>> > +                     iommu_domain_set_attr(iommu, DOMAIN_ATTR_IO_PGTABLE_CFG,
>> > &pgtbl_cfg);
>> > +             }
>
> I'm applying for -fixes as this is an obvious problem..  But kinda
> thinking that we should try to move it into an a6xx specific
> create_address_space() (or wrapper for the generic fxn)
>
> Sai/Jordan, could I talk one of you into trying to clean this up
> better for next cycle?
>

Looking more closely(sorry I should have before), the quirk setting
is already guarded by htw_llc_slice check but what is happening here is
that check is not proper when LLCC is disabled i.e., CONFIG_QCOM_LLCC=n.
When LLCC is disabled, htw_llc_slice is set to NULL and the !IS_ERR
check passes because it doesn't take care of NULL and quirk is
set causing bugs. So the proper fix would be to use IS_ERR_OR_NULL for
the check.

Konrad, can you please test this below change without your change?

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 130661898546..3b798e883f82 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1117,7 +1117,7 @@ static void a6xx_llc_slices_init(struct platform_device *pdev,
        a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU);
        a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW);

-       if (IS_ERR(a6xx_gpu->llc_slice) && IS_ERR(a6xx_gpu->htw_llc_slice))
+       if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice))
                a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
 }

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 6cf9975e951e..dbd5cacddb9c 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -206,7 +206,7 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu,
         * This allows GPU to set the bus attributes required to use system
         * cache on behalf of the iommu page table walker.
         */
-       if (!IS_ERR(a6xx_gpu->htw_llc_slice)) {
+       if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice)) {
                pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
                iommu_domain_set_attr(iommu, DOMAIN_ATTR_IO_PGTABLE_CFG, &pgtbl_cfg);
        }


Thanks,
Sai

--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
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Re: [PATCH] drm/msm: Only enable A6xx LLCC code on A6xx

[Konrad Dybcio]

> Konrad, can you please test this below change without your change?

This brings no difference, a BUG still happens. We're still calling to_a6xx_gpu on ANY device that's probed! Too bad it won't turn my A330 into an A640..

Also, relying on disabling LLCC in the config is out of question as it makes the arm32 kernel not compile with DRM/MSM and it just removes the functionality on devices with a6xx.. (unless somebody removes the dependency on it, which in my opinion is even worse and will cause more problems for developers!).

The bigger question is how and why did that piece of code ever make it to adreno_gpu.c and not a6xx_gpu.c?

To solve it in a cleaner way I propose to move it to an a6xx-specific file, or if it's going to be used with next-gen GPUs, perhaps manage calling of this code via an adreno quirk/feature in adreno_device.c. Now that I think about it, A5xx GPMU en/disable could probably managed like that, instead of using tons of if-statements for each GPU model that has it..

While we're at it, do ALL (and I truly do mean ALL, including the low-end ones, this will be important later on) A6xx GPUs make use of that feature?

Konrad

Re: [PATCH] drm/msm: Only enable A6xx LLCC code on A6xx

[Konrad Dybcio]

> Konrad, can you please test this below change without your change?

This brings no difference, a BUG still happens. We're still calling to_a6xx_gpu on ANY device that's probed! Too bad it won't turn my A330 into an A640..

Also, relying on disabling LLCC in the config is out of question as it makes the arm32 kernel not compile with DRM/MSM and it just removes the functionality on devices with a6xx.. (unless somebody removes the dependency on it, which in my opinion is even worse and will cause more problems for developers!).

The bigger question is how and why did that piece of code ever make it to adreno_gpu.c and not a6xx_gpu.c?

To solve it in a cleaner way I propose to move it to an a6xx-specific file, or if it's going to be used with next-gen GPUs, perhaps manage calling of this code via an adreno quirk/feature in adreno_device.c. Now that I think about it, A5xx GPMU en/disable could probably managed like that, instead of using tons of if-statements for each GPU model that has it..

While we're at it, do ALL (and I truly do mean ALL, including the low-end ones, this will be important later on) A6xx GPUs make use of that feature?

Konrad

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Re: [PATCH] drm/msm: Only enable A6xx LLCC code on A6xx

[Sai Prakash Ranjan]

On 2021-01-08 19:09, Konrad Dybcio wrote:
>> Konrad, can you please test this below change without your change?
> 
> This brings no difference, a BUG still happens. We're still calling
> to_a6xx_gpu on ANY device that's probed! Too bad it won't turn my A330
> into an A640..
> 
> Also, relying on disabling LLCC in the config is out of question as it
> makes the arm32 kernel not compile with DRM/MSM and it just removes
> the functionality on devices with a6xx.. (unless somebody removes the
> dependency on it, which in my opinion is even worse and will cause
> more problems for developers!).
> 

Disabling LLCC is not the suggestion, I was under the impression that
was the cause here for the smmu bug. Anyways, the check for llc slice
in case llcc is disabled is not correct as well. I will send a patch for
that as well.

> The bigger question is how and why did that piece of code ever make it
> to adreno_gpu.c and not a6xx_gpu.c?
> 

My mistake, I will move it.

> To solve it in a cleaner way I propose to move it to an a6xx-specific
> file, or if it's going to be used with next-gen GPUs, perhaps manage
> calling of this code via an adreno quirk/feature in adreno_device.c.
> Now that I think about it, A5xx GPMU en/disable could probably managed
> like that, instead of using tons of if-statements for each GPU model
> that has it..
> 
> While we're at it, do ALL (and I truly do mean ALL, including the
> low-end ones, this will be important later on) A6xx GPUs make use of
> that feature?
> 

I do not have a list of all A6XX GPUs with me currently, but from what
I know, A618, A630, A640, A650 has the support.

Thanks,
Sai

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a 
member
of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH] drm/msm: Only enable A6xx LLCC code on A6xx

[Sai Prakash Ranjan]

On 2021-01-08 19:09, Konrad Dybcio wrote:
>> Konrad, can you please test this below change without your change?
> 
> This brings no difference, a BUG still happens. We're still calling
> to_a6xx_gpu on ANY device that's probed! Too bad it won't turn my A330
> into an A640..
> 
> Also, relying on disabling LLCC in the config is out of question as it
> makes the arm32 kernel not compile with DRM/MSM and it just removes
> the functionality on devices with a6xx.. (unless somebody removes the
> dependency on it, which in my opinion is even worse and will cause
> more problems for developers!).
> 

Disabling LLCC is not the suggestion, I was under the impression that
was the cause here for the smmu bug. Anyways, the check for llc slice
in case llcc is disabled is not correct as well. I will send a patch for
that as well.

> The bigger question is how and why did that piece of code ever make it
> to adreno_gpu.c and not a6xx_gpu.c?
> 

My mistake, I will move it.

> To solve it in a cleaner way I propose to move it to an a6xx-specific
> file, or if it's going to be used with next-gen GPUs, perhaps manage
> calling of this code via an adreno quirk/feature in adreno_device.c.
> Now that I think about it, A5xx GPMU en/disable could probably managed
> like that, instead of using tons of if-statements for each GPU model
> that has it..
> 
> While we're at it, do ALL (and I truly do mean ALL, including the
> low-end ones, this will be important later on) A6xx GPUs make use of
> that feature?
> 

I do not have a list of all A6XX GPUs with me currently, but from what
I know, A618, A630, A640, A650 has the support.

Thanks,
Sai

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a 
member
of Code Aurora Forum, hosted by The Linux Foundation
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [Freedreno] [PATCH] drm/msm: Only enable A6xx LLCC code on A6xx

[Rob Clark]

On Fri, Jan 8, 2021 at 6:05 AM Sai Prakash Ranjan
<saiprakash.ranjan@codeaurora.org> wrote:
>
> On 2021-01-08 19:09, Konrad Dybcio wrote:
> >> Konrad, can you please test this below change without your change?
> >
> > This brings no difference, a BUG still happens. We're still calling
> > to_a6xx_gpu on ANY device that's probed! Too bad it won't turn my A330
> > into an A640..
> >
> > Also, relying on disabling LLCC in the config is out of question as it
> > makes the arm32 kernel not compile with DRM/MSM and it just removes
> > the functionality on devices with a6xx.. (unless somebody removes the
> > dependency on it, which in my opinion is even worse and will cause
> > more problems for developers!).
> >
>
> Disabling LLCC is not the suggestion, I was under the impression that
> was the cause here for the smmu bug. Anyways, the check for llc slice
> in case llcc is disabled is not correct as well. I will send a patch for
> that as well.
>
> > The bigger question is how and why did that piece of code ever make it
> > to adreno_gpu.c and not a6xx_gpu.c?
> >
>
> My mistake, I will move it.

Thanks, since we don't have kernel-CI coverage for gpu, and there
probably isn't one person who has all the different devices supported
(or enough hours in the day to test them all), it is probably
better/safer to keep things in the backend code that is specific to a
given generation.

> > To solve it in a cleaner way I propose to move it to an a6xx-specific
> > file, or if it's going to be used with next-gen GPUs, perhaps manage
> > calling of this code via an adreno quirk/feature in adreno_device.c.
> > Now that I think about it, A5xx GPMU en/disable could probably managed
> > like that, instead of using tons of if-statements for each GPU model
> > that has it..
> >
> > While we're at it, do ALL (and I truly do mean ALL, including the
> > low-end ones, this will be important later on) A6xx GPUs make use of
> > that feature?
> >
>
> I do not have a list of all A6XX GPUs with me currently, but from what
> I know, A618, A630, A640, A650 has the support.
>

From the PoV of bringing up new a6xx, we should probably consider that
some of them may not *yet* have LLCC enabled.  I have an 8cx laptop
and once I find time to get the display working, the next step would
be bringing up a680.. and I'd probably like to start without LLCC..

BR,
-R

> Thanks,
> Sai
>
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
> member
> of Code Aurora Forum, hosted by The Linux Foundation
> _______________________________________________
> Freedreno mailing list
> Freedreno@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/freedreno

Re: [Freedreno] [PATCH] drm/msm: Only enable A6xx LLCC code on A6xx

[Rob Clark]

On Fri, Jan 8, 2021 at 6:05 AM Sai Prakash Ranjan
<saiprakash.ranjan@codeaurora.org> wrote:
>
> On 2021-01-08 19:09, Konrad Dybcio wrote:
> >> Konrad, can you please test this below change without your change?
> >
> > This brings no difference, a BUG still happens. We're still calling
> > to_a6xx_gpu on ANY device that's probed! Too bad it won't turn my A330
> > into an A640..
> >
> > Also, relying on disabling LLCC in the config is out of question as it
> > makes the arm32 kernel not compile with DRM/MSM and it just removes
> > the functionality on devices with a6xx.. (unless somebody removes the
> > dependency on it, which in my opinion is even worse and will cause
> > more problems for developers!).
> >
>
> Disabling LLCC is not the suggestion, I was under the impression that
> was the cause here for the smmu bug. Anyways, the check for llc slice
> in case llcc is disabled is not correct as well. I will send a patch for
> that as well.
>
> > The bigger question is how and why did that piece of code ever make it
> > to adreno_gpu.c and not a6xx_gpu.c?
> >
>
> My mistake, I will move it.

Thanks, since we don't have kernel-CI coverage for gpu, and there
probably isn't one person who has all the different devices supported
(or enough hours in the day to test them all), it is probably
better/safer to keep things in the backend code that is specific to a
given generation.

> > To solve it in a cleaner way I propose to move it to an a6xx-specific
> > file, or if it's going to be used with next-gen GPUs, perhaps manage
> > calling of this code via an adreno quirk/feature in adreno_device.c.
> > Now that I think about it, A5xx GPMU en/disable could probably managed
> > like that, instead of using tons of if-statements for each GPU model
> > that has it..
> >
> > While we're at it, do ALL (and I truly do mean ALL, including the
> > low-end ones, this will be important later on) A6xx GPUs make use of
> > that feature?
> >
>
> I do not have a list of all A6XX GPUs with me currently, but from what
> I know, A618, A630, A640, A650 has the support.
>

From the PoV of bringing up new a6xx, we should probably consider that
some of them may not *yet* have LLCC enabled.  I have an 8cx laptop
and once I find time to get the display working, the next step would
be bringing up a680.. and I'd probably like to start without LLCC..

BR,
-R

> Thanks,
> Sai
>
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
> member
> of Code Aurora Forum, hosted by The Linux Foundation
> _______________________________________________
> Freedreno mailing list
> Freedreno@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/freedreno
_______________________________________________
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Re: [Freedreno] [PATCH] drm/msm: Only enable A6xx LLCC code on A6xx

[Sai Prakash Ranjan]

Hi Rob,

On 2021-01-08 22:16, Rob Clark wrote:
> On Fri, Jan 8, 2021 at 6:05 AM Sai Prakash Ranjan
> <saiprakash.ranjan@codeaurora.org> wrote:
>> 
>> On 2021-01-08 19:09, Konrad Dybcio wrote:
>> >> Konrad, can you please test this below change without your change?
>> >
>> > This brings no difference, a BUG still happens. We're still calling
>> > to_a6xx_gpu on ANY device that's probed! Too bad it won't turn my A330
>> > into an A640..
>> >
>> > Also, relying on disabling LLCC in the config is out of question as it
>> > makes the arm32 kernel not compile with DRM/MSM and it just removes
>> > the functionality on devices with a6xx.. (unless somebody removes the
>> > dependency on it, which in my opinion is even worse and will cause
>> > more problems for developers!).
>> >
>> 
>> Disabling LLCC is not the suggestion, I was under the impression that
>> was the cause here for the smmu bug. Anyways, the check for llc slice
>> in case llcc is disabled is not correct as well. I will send a patch 
>> for
>> that as well.
>> 
>> > The bigger question is how and why did that piece of code ever make it
>> > to adreno_gpu.c and not a6xx_gpu.c?
>> >
>> 
>> My mistake, I will move it.
> 
> Thanks, since we don't have kernel-CI coverage for gpu, and there
> probably isn't one person who has all the different devices supported
> (or enough hours in the day to test them all), it is probably
> better/safer to keep things in the backend code that is specific to a
> given generation.
> 

Agreed, I will post this change soon and will introduce some feature
check as well because we will need it for iommu prot flag as per 
discussion
here - 
https://lore.kernel.org/lkml/20210108181830.GA5457@willie-the-truck/

>> > To solve it in a cleaner way I propose to move it to an a6xx-specific
>> > file, or if it's going to be used with next-gen GPUs, perhaps manage
>> > calling of this code via an adreno quirk/feature in adreno_device.c.
>> > Now that I think about it, A5xx GPMU en/disable could probably managed
>> > like that, instead of using tons of if-statements for each GPU model
>> > that has it..
>> >
>> > While we're at it, do ALL (and I truly do mean ALL, including the
>> > low-end ones, this will be important later on) A6xx GPUs make use of
>> > that feature?
>> >
>> 
>> I do not have a list of all A6XX GPUs with me currently, but from what
>> I know, A618, A630, A640, A650 has the support.
>> 
> 
> From the PoV of bringing up new a6xx, we should probably consider that
> some of them may not *yet* have LLCC enabled.  I have an 8cx laptop
> and once I find time to get the display working, the next step would
> be bringing up a680.. and I'd probably like to start without LLCC..
> 

Right, once I move the LLCC code to a6xx specific address space 
creation,
without LLCC slices for GPU specified in qcom llcc driver, we will not
be using it.

Thanks,
Sai

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a 
member
of Code Aurora Forum, hosted by The Linux Foundation

Re: [Freedreno] [PATCH] drm/msm: Only enable A6xx LLCC code on A6xx

[Sai Prakash Ranjan]

Hi Rob,

On 2021-01-08 22:16, Rob Clark wrote:
> On Fri, Jan 8, 2021 at 6:05 AM Sai Prakash Ranjan
> <saiprakash.ranjan@codeaurora.org> wrote:
>> 
>> On 2021-01-08 19:09, Konrad Dybcio wrote:
>> >> Konrad, can you please test this below change without your change?
>> >
>> > This brings no difference, a BUG still happens. We're still calling
>> > to_a6xx_gpu on ANY device that's probed! Too bad it won't turn my A330
>> > into an A640..
>> >
>> > Also, relying on disabling LLCC in the config is out of question as it
>> > makes the arm32 kernel not compile with DRM/MSM and it just removes
>> > the functionality on devices with a6xx.. (unless somebody removes the
>> > dependency on it, which in my opinion is even worse and will cause
>> > more problems for developers!).
>> >
>> 
>> Disabling LLCC is not the suggestion, I was under the impression that
>> was the cause here for the smmu bug. Anyways, the check for llc slice
>> in case llcc is disabled is not correct as well. I will send a patch 
>> for
>> that as well.
>> 
>> > The bigger question is how and why did that piece of code ever make it
>> > to adreno_gpu.c and not a6xx_gpu.c?
>> >
>> 
>> My mistake, I will move it.
> 
> Thanks, since we don't have kernel-CI coverage for gpu, and there
> probably isn't one person who has all the different devices supported
> (or enough hours in the day to test them all), it is probably
> better/safer to keep things in the backend code that is specific to a
> given generation.
> 

Agreed, I will post this change soon and will introduce some feature
check as well because we will need it for iommu prot flag as per 
discussion
here - 
https://lore.kernel.org/lkml/20210108181830.GA5457@willie-the-truck/

>> > To solve it in a cleaner way I propose to move it to an a6xx-specific
>> > file, or if it's going to be used with next-gen GPUs, perhaps manage
>> > calling of this code via an adreno quirk/feature in adreno_device.c.
>> > Now that I think about it, A5xx GPMU en/disable could probably managed
>> > like that, instead of using tons of if-statements for each GPU model
>> > that has it..
>> >
>> > While we're at it, do ALL (and I truly do mean ALL, including the
>> > low-end ones, this will be important later on) A6xx GPUs make use of
>> > that feature?
>> >
>> 
>> I do not have a list of all A6XX GPUs with me currently, but from what
>> I know, A618, A630, A640, A650 has the support.
>> 
> 
> From the PoV of bringing up new a6xx, we should probably consider that
> some of them may not *yet* have LLCC enabled.  I have an 8cx laptop
> and once I find time to get the display working, the next step would
> be bringing up a680.. and I'd probably like to start without LLCC..
> 

Right, once I move the LLCC code to a6xx specific address space 
creation,
without LLCC slices for GPU specified in qcom llcc driver, we will not
be using it.

Thanks,
Sai

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a 
member
of Code Aurora Forum, hosted by The Linux Foundation
_______________________________________________
dri-devel mailing list
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https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [Freedreno] [PATCH] drm/msm: Only enable A6xx LLCC code on A6xx

[Jordan Crouse]

On Mon, Jan 11, 2021 at 09:54:12AM +0530, Sai Prakash Ranjan wrote:
> Hi Rob,
> 
> On 2021-01-08 22:16, Rob Clark wrote:
> >On Fri, Jan 8, 2021 at 6:05 AM Sai Prakash Ranjan
> ><saiprakash.ranjan@codeaurora.org> wrote:
> >>
> >>On 2021-01-08 19:09, Konrad Dybcio wrote:
> >>>> Konrad, can you please test this below change without your change?
> >>>
> >>> This brings no difference, a BUG still happens. We're still calling
> >>> to_a6xx_gpu on ANY device that's probed! Too bad it won't turn my A330
> >>> into an A640..
> >>>
> >>> Also, relying on disabling LLCC in the config is out of question as it
> >>> makes the arm32 kernel not compile with DRM/MSM and it just removes
> >>> the functionality on devices with a6xx.. (unless somebody removes the
> >>> dependency on it, which in my opinion is even worse and will cause
> >>> more problems for developers!).
> >>>
> >>
> >>Disabling LLCC is not the suggestion, I was under the impression that
> >>was the cause here for the smmu bug. Anyways, the check for llc slice
> >>in case llcc is disabled is not correct as well. I will send a patch for
> >>that as well.
> >>
> >>> The bigger question is how and why did that piece of code ever make it
> >>> to adreno_gpu.c and not a6xx_gpu.c?
> >>>
> >>
> >>My mistake, I will move it.
> >
> >Thanks, since we don't have kernel-CI coverage for gpu, and there
> >probably isn't one person who has all the different devices supported
> >(or enough hours in the day to test them all), it is probably
> >better/safer to keep things in the backend code that is specific to a
> >given generation.
> >
> 
> Agreed, I will post this change soon and will introduce some feature
> check as well because we will need it for iommu prot flag as per discussion
> here - https://lore.kernel.org/lkml/20210108181830.GA5457@willie-the-truck/
> 
> >>> To solve it in a cleaner way I propose to move it to an a6xx-specific
> >>> file, or if it's going to be used with next-gen GPUs, perhaps manage
> >>> calling of this code via an adreno quirk/feature in adreno_device.c.
> >>> Now that I think about it, A5xx GPMU en/disable could probably managed
> >>> like that, instead of using tons of if-statements for each GPU model
> >>> that has it..
> >>>
> >>> While we're at it, do ALL (and I truly do mean ALL, including the
> >>> low-end ones, this will be important later on) A6xx GPUs make use of
> >>> that feature?
> >>>
> >>
> >>I do not have a list of all A6XX GPUs with me currently, but from what
> >>I know, A618, A630, A640, A650 has the support.
> >>
> >
> >From the PoV of bringing up new a6xx, we should probably consider that
> >some of them may not *yet* have LLCC enabled.  I have an 8cx laptop
> >and once I find time to get the display working, the next step would
> >be bringing up a680.. and I'd probably like to start without LLCC..
> >
> 
> Right, once I move the LLCC code to a6xx specific address space creation,
> without LLCC slices for GPU specified in qcom llcc driver, we will not
> be using it.

Right. The problem here was that we were assuming an a6xx container in generic
code. Testing the existence of LLCC or not is a different problem but it is my
understanding that if we set the attribute without LLCC enabled it just gets
ignored. Is that correct Sai?

Jordan

> Thanks,
> Sai
> 
> -- 
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation

-- 
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [Freedreno] [PATCH] drm/msm: Only enable A6xx LLCC code on A6xx

[Jordan Crouse]

On Mon, Jan 11, 2021 at 09:54:12AM +0530, Sai Prakash Ranjan wrote:
> Hi Rob,
> 
> On 2021-01-08 22:16, Rob Clark wrote:
> >On Fri, Jan 8, 2021 at 6:05 AM Sai Prakash Ranjan
> ><saiprakash.ranjan@codeaurora.org> wrote:
> >>
> >>On 2021-01-08 19:09, Konrad Dybcio wrote:
> >>>> Konrad, can you please test this below change without your change?
> >>>
> >>> This brings no difference, a BUG still happens. We're still calling
> >>> to_a6xx_gpu on ANY device that's probed! Too bad it won't turn my A330
> >>> into an A640..
> >>>
> >>> Also, relying on disabling LLCC in the config is out of question as it
> >>> makes the arm32 kernel not compile with DRM/MSM and it just removes
> >>> the functionality on devices with a6xx.. (unless somebody removes the
> >>> dependency on it, which in my opinion is even worse and will cause
> >>> more problems for developers!).
> >>>
> >>
> >>Disabling LLCC is not the suggestion, I was under the impression that
> >>was the cause here for the smmu bug. Anyways, the check for llc slice
> >>in case llcc is disabled is not correct as well. I will send a patch for
> >>that as well.
> >>
> >>> The bigger question is how and why did that piece of code ever make it
> >>> to adreno_gpu.c and not a6xx_gpu.c?
> >>>
> >>
> >>My mistake, I will move it.
> >
> >Thanks, since we don't have kernel-CI coverage for gpu, and there
> >probably isn't one person who has all the different devices supported
> >(or enough hours in the day to test them all), it is probably
> >better/safer to keep things in the backend code that is specific to a
> >given generation.
> >
> 
> Agreed, I will post this change soon and will introduce some feature
> check as well because we will need it for iommu prot flag as per discussion
> here - https://lore.kernel.org/lkml/20210108181830.GA5457@willie-the-truck/
> 
> >>> To solve it in a cleaner way I propose to move it to an a6xx-specific
> >>> file, or if it's going to be used with next-gen GPUs, perhaps manage
> >>> calling of this code via an adreno quirk/feature in adreno_device.c.
> >>> Now that I think about it, A5xx GPMU en/disable could probably managed
> >>> like that, instead of using tons of if-statements for each GPU model
> >>> that has it..
> >>>
> >>> While we're at it, do ALL (and I truly do mean ALL, including the
> >>> low-end ones, this will be important later on) A6xx GPUs make use of
> >>> that feature?
> >>>
> >>
> >>I do not have a list of all A6XX GPUs with me currently, but from what
> >>I know, A618, A630, A640, A650 has the support.
> >>
> >
> >From the PoV of bringing up new a6xx, we should probably consider that
> >some of them may not *yet* have LLCC enabled.  I have an 8cx laptop
> >and once I find time to get the display working, the next step would
> >be bringing up a680.. and I'd probably like to start without LLCC..
> >
> 
> Right, once I move the LLCC code to a6xx specific address space creation,
> without LLCC slices for GPU specified in qcom llcc driver, we will not
> be using it.

Right. The problem here was that we were assuming an a6xx container in generic
code. Testing the existence of LLCC or not is a different problem but it is my
understanding that if we set the attribute without LLCC enabled it just gets
ignored. Is that correct Sai?

Jordan

> Thanks,
> Sai
> 
> -- 
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation

-- 
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
_______________________________________________
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Re: [Freedreno] [PATCH] drm/msm: Only enable A6xx LLCC code on A6xx

[Sai Prakash Ranjan]

Hi Jordan,

On 2021-01-11 21:41, Jordan Crouse wrote:
> On Mon, Jan 11, 2021 at 09:54:12AM +0530, Sai Prakash Ranjan wrote:
>> Hi Rob,
>> 
>> On 2021-01-08 22:16, Rob Clark wrote:
>> >On Fri, Jan 8, 2021 at 6:05 AM Sai Prakash Ranjan
>> ><saiprakash.ranjan@codeaurora.org> wrote:
>> >>
>> >>On 2021-01-08 19:09, Konrad Dybcio wrote:
>> >>>> Konrad, can you please test this below change without your change?
>> >>>
>> >>> This brings no difference, a BUG still happens. We're still calling
>> >>> to_a6xx_gpu on ANY device that's probed! Too bad it won't turn my A330
>> >>> into an A640..
>> >>>
>> >>> Also, relying on disabling LLCC in the config is out of question as it
>> >>> makes the arm32 kernel not compile with DRM/MSM and it just removes
>> >>> the functionality on devices with a6xx.. (unless somebody removes the
>> >>> dependency on it, which in my opinion is even worse and will cause
>> >>> more problems for developers!).
>> >>>
>> >>
>> >>Disabling LLCC is not the suggestion, I was under the impression that
>> >>was the cause here for the smmu bug. Anyways, the check for llc slice
>> >>in case llcc is disabled is not correct as well. I will send a patch for
>> >>that as well.
>> >>
>> >>> The bigger question is how and why did that piece of code ever make it
>> >>> to adreno_gpu.c and not a6xx_gpu.c?
>> >>>
>> >>
>> >>My mistake, I will move it.
>> >
>> >Thanks, since we don't have kernel-CI coverage for gpu, and there
>> >probably isn't one person who has all the different devices supported
>> >(or enough hours in the day to test them all), it is probably
>> >better/safer to keep things in the backend code that is specific to a
>> >given generation.
>> >
>> 
>> Agreed, I will post this change soon and will introduce some feature
>> check as well because we will need it for iommu prot flag as per 
>> discussion
>> here - 
>> https://lore.kernel.org/lkml/20210108181830.GA5457@willie-the-truck/
>> 
>> >>> To solve it in a cleaner way I propose to move it to an a6xx-specific
>> >>> file, or if it's going to be used with next-gen GPUs, perhaps manage
>> >>> calling of this code via an adreno quirk/feature in adreno_device.c.
>> >>> Now that I think about it, A5xx GPMU en/disable could probably managed
>> >>> like that, instead of using tons of if-statements for each GPU model
>> >>> that has it..
>> >>>
>> >>> While we're at it, do ALL (and I truly do mean ALL, including the
>> >>> low-end ones, this will be important later on) A6xx GPUs make use of
>> >>> that feature?
>> >>>
>> >>
>> >>I do not have a list of all A6XX GPUs with me currently, but from what
>> >>I know, A618, A630, A640, A650 has the support.
>> >>
>> >
>> >From the PoV of bringing up new a6xx, we should probably consider that
>> >some of them may not *yet* have LLCC enabled.  I have an 8cx laptop
>> >and once I find time to get the display working, the next step would
>> >be bringing up a680.. and I'd probably like to start without LLCC..
>> >
>> 
>> Right, once I move the LLCC code to a6xx specific address space 
>> creation,
>> without LLCC slices for GPU specified in qcom llcc driver, we will not
>> be using it.
> 
> Right. The problem here was that we were assuming an a6xx container in 
> generic
> code. Testing the existence of LLCC or not is a different problem but 
> it is my
> understanding that if we set the attribute without LLCC enabled it just 
> gets
> ignored. Is that correct Sai?
> 

Yes that is correct, I just confirmed now with LLCC team.

Thanks,
Sai

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Re: [Freedreno] [PATCH] drm/msm: Only enable A6xx LLCC code on A6xx

[Sai Prakash Ranjan]

Hi Jordan,

On 2021-01-11 21:41, Jordan Crouse wrote:
> On Mon, Jan 11, 2021 at 09:54:12AM +0530, Sai Prakash Ranjan wrote:
>> Hi Rob,
>> 
>> On 2021-01-08 22:16, Rob Clark wrote:
>> >On Fri, Jan 8, 2021 at 6:05 AM Sai Prakash Ranjan
>> ><saiprakash.ranjan@codeaurora.org> wrote:
>> >>
>> >>On 2021-01-08 19:09, Konrad Dybcio wrote:
>> >>>> Konrad, can you please test this below change without your change?
>> >>>
>> >>> This brings no difference, a BUG still happens. We're still calling
>> >>> to_a6xx_gpu on ANY device that's probed! Too bad it won't turn my A330
>> >>> into an A640..
>> >>>
>> >>> Also, relying on disabling LLCC in the config is out of question as it
>> >>> makes the arm32 kernel not compile with DRM/MSM and it just removes
>> >>> the functionality on devices with a6xx.. (unless somebody removes the
>> >>> dependency on it, which in my opinion is even worse and will cause
>> >>> more problems for developers!).
>> >>>
>> >>
>> >>Disabling LLCC is not the suggestion, I was under the impression that
>> >>was the cause here for the smmu bug. Anyways, the check for llc slice
>> >>in case llcc is disabled is not correct as well. I will send a patch for
>> >>that as well.
>> >>
>> >>> The bigger question is how and why did that piece of code ever make it
>> >>> to adreno_gpu.c and not a6xx_gpu.c?
>> >>>
>> >>
>> >>My mistake, I will move it.
>> >
>> >Thanks, since we don't have kernel-CI coverage for gpu, and there
>> >probably isn't one person who has all the different devices supported
>> >(or enough hours in the day to test them all), it is probably
>> >better/safer to keep things in the backend code that is specific to a
>> >given generation.
>> >
>> 
>> Agreed, I will post this change soon and will introduce some feature
>> check as well because we will need it for iommu prot flag as per 
>> discussion
>> here - 
>> https://lore.kernel.org/lkml/20210108181830.GA5457@willie-the-truck/
>> 
>> >>> To solve it in a cleaner way I propose to move it to an a6xx-specific
>> >>> file, or if it's going to be used with next-gen GPUs, perhaps manage
>> >>> calling of this code via an adreno quirk/feature in adreno_device.c.
>> >>> Now that I think about it, A5xx GPMU en/disable could probably managed
>> >>> like that, instead of using tons of if-statements for each GPU model
>> >>> that has it..
>> >>>
>> >>> While we're at it, do ALL (and I truly do mean ALL, including the
>> >>> low-end ones, this will be important later on) A6xx GPUs make use of
>> >>> that feature?
>> >>>
>> >>
>> >>I do not have a list of all A6XX GPUs with me currently, but from what
>> >>I know, A618, A630, A640, A650 has the support.
>> >>
>> >
>> >From the PoV of bringing up new a6xx, we should probably consider that
>> >some of them may not *yet* have LLCC enabled.  I have an 8cx laptop
>> >and once I find time to get the display working, the next step would
>> >be bringing up a680.. and I'd probably like to start without LLCC..
>> >
>> 
>> Right, once I move the LLCC code to a6xx specific address space 
>> creation,
>> without LLCC slices for GPU specified in qcom llcc driver, we will not
>> be using it.
> 
> Right. The problem here was that we were assuming an a6xx container in 
> generic
> code. Testing the existence of LLCC or not is a different problem but 
> it is my
> understanding that if we set the attribute without LLCC enabled it just 
> gets
> ignored. Is that correct Sai?
> 

Yes that is correct, I just confirmed now with LLCC team.

Thanks,
Sai

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a 
member
of Code Aurora Forum, hosted by The Linux Foundation
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Re: [PATCH] drm/msm: Only enable A6xx LLCC code on A6xx

[patchwork-bot+linux-arm-msm]

Hello:

This patch was applied to qcom/linux.git (refs/heads/for-next):

On Mon,  4 Jan 2021 20:30:41 +0100 you wrote:
> Using this code on A5xx (and probably older too) causes a
> smmu bug.
> 
> Fixes: 474dadb8b0d5 ("drm/msm/a6xx: Add support for using system cache(LLC)")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
> 
> [...]

Here is the summary with links:
  - drm/msm: Only enable A6xx LLCC code on A6xx
    https://git.kernel.org/qcom/c/00fd44a1a470

You are awesome, thank you!
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