From: frank.chang@sifive.com
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Frank Chang <frank.chang@sifive.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Subject: [PATCH v6 26/72] target/riscv: rvv-1.0: floating-point square-root instruction
Date: Tue, 12 Jan 2021 17:39:00 +0800 [thread overview]
Message-ID: <20210112093950.17530-27-frank.chang@sifive.com> (raw)
In-Reply-To: <20210112093950.17530-1-frank.chang@sifive.com>
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e11666f16df..c0053cfb828 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -538,7 +538,7 @@ vfwmsac_vv 111110 . ..... ..... 001 ..... 1010111 @r_vm
vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm
vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm
vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm
-vfsqrt_v 100011 . ..... 00000 001 ..... 1010111 @r2_vm
+vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm
vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm
vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm
vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: frank.chang@sifive.com
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Frank Chang <frank.chang@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Subject: [PATCH v6 26/72] target/riscv: rvv-1.0: floating-point square-root instruction
Date: Tue, 12 Jan 2021 17:39:00 +0800 [thread overview]
Message-ID: <20210112093950.17530-27-frank.chang@sifive.com> (raw)
In-Reply-To: <20210112093950.17530-1-frank.chang@sifive.com>
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e11666f16df..c0053cfb828 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -538,7 +538,7 @@ vfwmsac_vv 111110 . ..... ..... 001 ..... 1010111 @r_vm
vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm
vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm
vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm
-vfsqrt_v 100011 . ..... 00000 001 ..... 1010111 @r2_vm
+vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm
vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm
vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm
vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm
--
2.17.1
next prev parent reply other threads:[~2021-01-12 10:04 UTC|newest]
Thread overview: 213+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-12 9:38 [PATCH v6 00/72] support vector extension v1.0 frank.chang
2021-01-12 9:38 ` [PATCH v6 01/72] target/riscv: drop vector 0.7.1 and add 1.0 support frank.chang
2021-01-12 9:38 ` frank.chang
2021-01-12 9:38 ` [PATCH v6 02/72] target/riscv: Use FIELD_EX32() to extract wd field frank.chang
2021-01-12 9:38 ` frank.chang
2021-01-19 16:34 ` Alistair Francis
2021-01-19 16:34 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 03/72] target/riscv: rvv-1.0: add mstatus VS field frank.chang
2021-01-12 9:38 ` frank.chang
2021-01-19 16:36 ` Alistair Francis
2021-01-19 16:36 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 04/72] target/riscv: rvv-1.0: add sstatus " frank.chang
2021-01-12 9:38 ` frank.chang
2021-01-19 16:36 ` Alistair Francis
2021-01-19 16:36 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 05/72] target/riscv: rvv-1.0: introduce writable misa.v field frank.chang
2021-01-12 9:38 ` frank.chang
2021-01-19 16:37 ` Alistair Francis
2021-01-19 16:37 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 06/72] target/riscv: rvv-1.0: add translation-time vector context status frank.chang
2021-01-12 9:38 ` frank.chang
2021-01-19 18:47 ` Alistair Francis
2021-01-19 18:47 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 07/72] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers frank.chang
2021-01-12 9:38 ` frank.chang
2021-01-19 16:47 ` Alistair Francis
2021-01-19 16:47 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 08/72] target/riscv: rvv-1.0: add vcsr register frank.chang
2021-01-12 9:38 ` frank.chang
2021-01-19 17:38 ` Alistair Francis
2021-01-19 17:38 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 09/72] target/riscv: rvv-1.0: add vlenb register frank.chang
2021-01-12 9:38 ` frank.chang
2021-01-19 17:39 ` Alistair Francis
2021-01-19 17:39 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 10/72] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers frank.chang
2021-01-12 9:38 ` frank.chang
2021-01-19 17:40 ` Alistair Francis
2021-01-19 17:40 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 11/72] target/riscv: rvv-1.0: remove MLEN calculations frank.chang
2021-01-12 9:38 ` frank.chang
2021-01-19 17:41 ` Alistair Francis
2021-01-19 17:41 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 12/72] target/riscv: rvv-1.0: add fractional LMUL frank.chang
2021-01-12 9:38 ` frank.chang
2021-01-19 18:43 ` Alistair Francis
2021-01-19 18:43 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 13/72] target/riscv: rvv-1.0: add VMA and VTA frank.chang
2021-01-12 9:38 ` frank.chang
2021-01-19 18:51 ` Alistair Francis
2021-01-19 18:51 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 14/72] target/riscv: rvv-1.0: update check functions frank.chang
2021-01-12 9:38 ` frank.chang
2021-01-28 21:15 ` Alistair Francis
2021-01-28 21:15 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 15/72] target/riscv: introduce more imm value modes in translator functions frank.chang
2021-01-12 9:38 ` frank.chang
2021-01-19 18:55 ` Alistair Francis
2021-01-19 18:55 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 16/72] target/riscv: rvv:1.0: add translation-time nan-box helper function frank.chang
2021-01-12 9:38 ` frank.chang
2021-01-19 18:58 ` Alistair Francis
2021-01-19 18:58 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 17/72] target/riscv: rvv-1.0: configure instructions frank.chang
2021-01-12 9:38 ` frank.chang
2021-01-19 18:59 ` Alistair Francis
2021-01-19 18:59 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 18/72] target/riscv: rvv-1.0: stride load and store instructions frank.chang
2021-01-12 9:38 ` frank.chang
2021-01-19 19:03 ` Alistair Francis
2021-01-19 19:03 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 19/72] target/riscv: rvv-1.0: index " frank.chang
2021-01-12 9:38 ` frank.chang
2021-01-19 19:09 ` Alistair Francis
2021-01-19 19:09 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 20/72] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns frank.chang
2021-01-12 9:38 ` frank.chang
2021-01-19 19:22 ` Alistair Francis
2021-01-19 19:22 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 21/72] target/riscv: rvv-1.0: fault-only-first unit stride load frank.chang
2021-01-12 9:38 ` frank.chang
2021-01-19 19:19 ` Alistair Francis
2021-01-19 19:19 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 22/72] target/riscv: rvv-1.0: amo operations frank.chang
2021-01-12 9:38 ` frank.chang
2021-01-25 23:19 ` Alistair Francis
2021-01-25 23:19 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 23/72] target/riscv: rvv-1.0: load/store whole register instructions frank.chang
2021-01-12 9:38 ` frank.chang
2021-01-25 23:24 ` Alistair Francis
2021-01-25 23:24 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 24/72] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns frank.chang
2021-01-12 9:38 ` frank.chang
2021-01-25 23:33 ` Alistair Francis
2021-01-25 23:33 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 25/72] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation frank.chang
2021-01-12 9:38 ` frank.chang
2021-01-25 23:42 ` Alistair Francis
2021-01-25 23:42 ` Alistair Francis
2021-01-12 9:39 ` frank.chang [this message]
2021-01-12 9:39 ` [PATCH v6 26/72] target/riscv: rvv-1.0: floating-point square-root instruction frank.chang
2021-01-25 23:49 ` Alistair Francis
2021-01-25 23:49 ` Alistair Francis
2021-01-12 9:39 ` [PATCH v6 27/72] target/riscv: rvv-1.0: floating-point classify instructions frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-25 23:50 ` Alistair Francis
2021-01-25 23:50 ` Alistair Francis
2021-01-12 9:39 ` [PATCH v6 28/72] target/riscv: rvv-1.0: mask population count instruction frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 29/72] target/riscv: rvv-1.0: find-first-set mask bit instruction frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 30/72] target/riscv: rvv-1.0: set-X-first mask bit instructions frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 31/72] target/riscv: rvv-1.0: iota instruction frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 32/72] target/riscv: rvv-1.0: element index instruction frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 33/72] target/riscv: rvv-1.0: allow load element with sign-extended frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 34/72] target/riscv: rvv-1.0: register gather instructions frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-28 21:18 ` Alistair Francis
2021-01-28 21:18 ` Alistair Francis
2021-01-12 9:39 ` [PATCH v6 35/72] target/riscv: rvv-1.0: integer scalar move instructions frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 36/72] target/riscv: rvv-1.0: floating-point move instruction frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-28 21:20 ` Alistair Francis
2021-01-28 21:20 ` Alistair Francis
2021-01-12 9:39 ` [PATCH v6 37/72] target/riscv: rvv-1.0: floating-point scalar move instructions frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 38/72] target/riscv: rvv-1.0: whole register " frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 39/72] target/riscv: rvv-1.0: integer extension instructions frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 40/72] target/riscv: rvv-1.0: single-width averaging add and subtract instructions frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 41/72] target/riscv: rvv-1.0: single-width bit shift instructions frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 42/72] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 43/72] target/riscv: rvv-1.0: narrowing integer right shift instructions frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 44/72] target/riscv: rvv-1.0: widening integer multiply-add instructions frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 45/72] target/riscv: rvv-1.0: single-width saturating add and subtract instructions frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 46/72] target/riscv: rvv-1.0: integer comparison instructions frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 47/72] target/riscv: rvv-1.0: floating-point compare instructions frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 48/72] target/riscv: rvv-1.0: mask-register logical instructions frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 49/72] target/riscv: rvv-1.0: slide instructions frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 50/72] target/riscv: rvv-1.0: floating-point " frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 51/72] target/riscv: rvv-1.0: narrowing fixed-point clip instructions frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 52/72] target/riscv: rvv-1.0: single-width floating-point reduction frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 53/72] target/riscv: rvv-1.0: widening floating-point reduction instructions frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 54/72] target/riscv: rvv-1.0: single-width scaling shift instructions frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 55/72] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 56/72] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 57/72] target/riscv: rvv-1.0: remove integer extract instruction frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 58/72] target/riscv: rvv-1.0: floating-point min/max instructions frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 59/72] target/riscv: introduce floating-point rounding mode enum frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 60/72] target/riscv: rvv-1.0: floating-point/integer type-convert instructions frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 61/72] target/riscv: rvv-1.0: widening floating-point/integer type-convert frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 62/72] target/riscv: add "set round to odd" rounding mode helper function frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 63/72] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 64/72] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 65/72] target/riscv: rvv-1.0: implement vstart CSR frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 66/72] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 67/72] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-28 21:27 ` Alistair Francis
2021-01-28 21:27 ` Alistair Francis
2021-01-12 9:39 ` [PATCH v6 68/72] target/riscv: gdb: modify gdb csr xml file to align with csr register map frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-25 23:53 ` Alistair Francis
2021-01-25 23:53 ` Alistair Francis
2021-01-26 7:43 ` Frank Chang
2021-01-26 7:43 ` Frank Chang
2021-01-12 9:39 ` [PATCH v6 69/72] target/riscv: gdb: support vector registers for rv64 & rv32 frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 70/72] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 71/72] target/riscv: rvv-1.0: floating-point reciprocal " frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 9:39 ` [PATCH v6 72/72] target/riscv: set mstatus.SD bit when writing fp CSRs frank.chang
2021-01-12 9:39 ` frank.chang
2021-01-12 11:10 ` [PATCH v6 00/72] support vector extension v1.0 no-reply
2021-01-12 11:10 ` no-reply
2021-01-19 19:11 ` Alistair Francis
2021-01-19 19:11 ` Alistair Francis
2021-01-26 6:14 ` Frank Chang
2021-01-26 6:14 ` Frank Chang
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