From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>, Frank Chang <frank.chang@sifive.com>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Richard Henderson <richard.henderson@linaro.org>, Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v6 37/72] target/riscv: rvv-1.0: floating-point scalar move instructions Date: Tue, 12 Jan 2021 17:39:11 +0800 [thread overview] Message-ID: <20210112093950.17530-38-frank.chang@sifive.com> (raw) In-Reply-To: <20210112093950.17530-1-frank.chang@sifive.com> From: Frank Chang <frank.chang@sifive.com> NaN-boxed the scalar floating-point register based on RVV 1.0's rules. Signed-off-by: Frank Chang <frank.chang@sifive.com> --- target/riscv/insn32.decode | 4 +-- target/riscv/insn_trans/trans_rvv.c.inc | 39 +++++++++++++------------ target/riscv/internals.h | 5 ---- 3 files changed, 22 insertions(+), 26 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index f26723a4d27..8516a12b126 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -612,8 +612,8 @@ vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2 vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r -vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd -vfmv_s_f 001101 1 00000 ..... 101 ..... 1010111 @r2 +vfmv_f_s 010000 1 ..... 00000 001 ..... 1010111 @r2rd +vfmv_s_f 010000 1 00000 ..... 101 ..... 1010111 @r2 vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm vslideup_vi 001110 . ..... ..... 011 ..... 1010111 @r_vm vslide1up_vx 001110 . ..... ..... 110 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 7ac7d6a2b92..63e31299b3b 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3282,14 +3282,20 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a) /* Floating-Point Scalar Move Instructions */ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a) { - if (!s->vill && has_ext(s, RVF) && - (s->mstatus_fs != 0) && (s->sew != 0)) { - unsigned int len = 8 << s->sew; + if (require_rvv(s) && + require_rvf(s) && + vext_check_isa_ill(s)) { + unsigned int ofs = (8 << s->sew); + unsigned int len = 64 - ofs; + TCGv_i64 t_nan; vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0, false); - if (len < 64) { - tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], - MAKE_64BIT_MASK(len, 64 - len)); + /* NaN-box f[rd] as necessary for SEW */ + if (len) { + t_nan = tcg_const_i64(UINT64_MAX); + tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], + t_nan, ofs, len); + tcg_temp_free_i64(t_nan); } mark_fs_dirty(s); @@ -3301,25 +3307,20 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a) /* vfmv.s.f vd, rs1 # vd[0] = rs1 (vs2=0) */ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a) { - if (!s->vill && has_ext(s, RVF) && (s->sew != 0)) { - TCGv_i64 t1; + if (require_rvv(s) && + require_rvf(s) && + vext_check_isa_ill(s)) { /* The instructions ignore LMUL and vector register group. */ - uint32_t vlmax = s->vlen >> 3; + TCGv_i64 t1; + TCGLabel *over = gen_new_label(); /* if vl == 0, skip vector register write back */ - TCGLabel *over = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - /* zeroed all elements */ - tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), vlmax, vlmax, 0); - - /* NaN-box f[rs1] as necessary for SEW */ + /* NaN-box f[rs1] */ t1 = tcg_temp_new_i64(); - if (s->sew == MO_64 && !has_ext(s, RVD)) { - tcg_gen_ori_i64(t1, cpu_fpr[a->rs1], MAKE_64BIT_MASK(32, 32)); - } else { - tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); - } + do_nanbox(s, t1, cpu_fpr[a->rs1]); + vec_element_storei(s, a->rd, 0, t1); tcg_temp_free_i64(t1); mark_vs_dirty(s); diff --git a/target/riscv/internals.h b/target/riscv/internals.h index c3bbeea9a94..959b81b3016 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -32,11 +32,6 @@ target_ulong fclass_h(uint64_t frs1); target_ulong fclass_s(uint64_t frs1); target_ulong fclass_d(uint64_t frs1); -#define SEW8 0 -#define SEW16 1 -#define SEW32 2 -#define SEW64 3 - #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_riscv_cpu; #endif -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Frank Chang <frank.chang@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Richard Henderson <richard.henderson@linaro.org>, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v6 37/72] target/riscv: rvv-1.0: floating-point scalar move instructions Date: Tue, 12 Jan 2021 17:39:11 +0800 [thread overview] Message-ID: <20210112093950.17530-38-frank.chang@sifive.com> (raw) In-Reply-To: <20210112093950.17530-1-frank.chang@sifive.com> From: Frank Chang <frank.chang@sifive.com> NaN-boxed the scalar floating-point register based on RVV 1.0's rules. Signed-off-by: Frank Chang <frank.chang@sifive.com> --- target/riscv/insn32.decode | 4 +-- target/riscv/insn_trans/trans_rvv.c.inc | 39 +++++++++++++------------ target/riscv/internals.h | 5 ---- 3 files changed, 22 insertions(+), 26 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index f26723a4d27..8516a12b126 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -612,8 +612,8 @@ vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2 vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r -vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd -vfmv_s_f 001101 1 00000 ..... 101 ..... 1010111 @r2 +vfmv_f_s 010000 1 ..... 00000 001 ..... 1010111 @r2rd +vfmv_s_f 010000 1 00000 ..... 101 ..... 1010111 @r2 vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm vslideup_vi 001110 . ..... ..... 011 ..... 1010111 @r_vm vslide1up_vx 001110 . ..... ..... 110 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 7ac7d6a2b92..63e31299b3b 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3282,14 +3282,20 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a) /* Floating-Point Scalar Move Instructions */ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a) { - if (!s->vill && has_ext(s, RVF) && - (s->mstatus_fs != 0) && (s->sew != 0)) { - unsigned int len = 8 << s->sew; + if (require_rvv(s) && + require_rvf(s) && + vext_check_isa_ill(s)) { + unsigned int ofs = (8 << s->sew); + unsigned int len = 64 - ofs; + TCGv_i64 t_nan; vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0, false); - if (len < 64) { - tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], - MAKE_64BIT_MASK(len, 64 - len)); + /* NaN-box f[rd] as necessary for SEW */ + if (len) { + t_nan = tcg_const_i64(UINT64_MAX); + tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], + t_nan, ofs, len); + tcg_temp_free_i64(t_nan); } mark_fs_dirty(s); @@ -3301,25 +3307,20 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a) /* vfmv.s.f vd, rs1 # vd[0] = rs1 (vs2=0) */ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a) { - if (!s->vill && has_ext(s, RVF) && (s->sew != 0)) { - TCGv_i64 t1; + if (require_rvv(s) && + require_rvf(s) && + vext_check_isa_ill(s)) { /* The instructions ignore LMUL and vector register group. */ - uint32_t vlmax = s->vlen >> 3; + TCGv_i64 t1; + TCGLabel *over = gen_new_label(); /* if vl == 0, skip vector register write back */ - TCGLabel *over = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - /* zeroed all elements */ - tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), vlmax, vlmax, 0); - - /* NaN-box f[rs1] as necessary for SEW */ + /* NaN-box f[rs1] */ t1 = tcg_temp_new_i64(); - if (s->sew == MO_64 && !has_ext(s, RVD)) { - tcg_gen_ori_i64(t1, cpu_fpr[a->rs1], MAKE_64BIT_MASK(32, 32)); - } else { - tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); - } + do_nanbox(s, t1, cpu_fpr[a->rs1]); + vec_element_storei(s, a->rd, 0, t1); tcg_temp_free_i64(t1); mark_vs_dirty(s); diff --git a/target/riscv/internals.h b/target/riscv/internals.h index c3bbeea9a94..959b81b3016 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -32,11 +32,6 @@ target_ulong fclass_h(uint64_t frs1); target_ulong fclass_s(uint64_t frs1); target_ulong fclass_d(uint64_t frs1); -#define SEW8 0 -#define SEW16 1 -#define SEW32 2 -#define SEW64 3 - #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_riscv_cpu; #endif -- 2.17.1
next prev parent reply other threads:[~2021-01-12 10:14 UTC|newest] Thread overview: 213+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-01-12 9:38 [PATCH v6 00/72] support vector extension v1.0 frank.chang 2021-01-12 9:38 ` [PATCH v6 01/72] target/riscv: drop vector 0.7.1 and add 1.0 support frank.chang 2021-01-12 9:38 ` frank.chang 2021-01-12 9:38 ` [PATCH v6 02/72] target/riscv: Use FIELD_EX32() to extract wd field frank.chang 2021-01-12 9:38 ` frank.chang 2021-01-19 16:34 ` Alistair Francis 2021-01-19 16:34 ` Alistair Francis 2021-01-12 9:38 ` [PATCH v6 03/72] target/riscv: rvv-1.0: add mstatus VS field frank.chang 2021-01-12 9:38 ` frank.chang 2021-01-19 16:36 ` Alistair Francis 2021-01-19 16:36 ` Alistair Francis 2021-01-12 9:38 ` [PATCH v6 04/72] target/riscv: rvv-1.0: add sstatus " frank.chang 2021-01-12 9:38 ` frank.chang 2021-01-19 16:36 ` Alistair Francis 2021-01-19 16:36 ` Alistair Francis 2021-01-12 9:38 ` [PATCH v6 05/72] target/riscv: rvv-1.0: introduce writable misa.v field frank.chang 2021-01-12 9:38 ` frank.chang 2021-01-19 16:37 ` Alistair Francis 2021-01-19 16:37 ` Alistair Francis 2021-01-12 9:38 ` [PATCH v6 06/72] target/riscv: rvv-1.0: add translation-time vector context status frank.chang 2021-01-12 9:38 ` frank.chang 2021-01-19 18:47 ` Alistair Francis 2021-01-19 18:47 ` Alistair Francis 2021-01-12 9:38 ` [PATCH v6 07/72] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers frank.chang 2021-01-12 9:38 ` frank.chang 2021-01-19 16:47 ` Alistair Francis 2021-01-19 16:47 ` Alistair Francis 2021-01-12 9:38 ` [PATCH v6 08/72] target/riscv: rvv-1.0: add vcsr register frank.chang 2021-01-12 9:38 ` frank.chang 2021-01-19 17:38 ` Alistair Francis 2021-01-19 17:38 ` Alistair Francis 2021-01-12 9:38 ` [PATCH v6 09/72] target/riscv: rvv-1.0: add vlenb register frank.chang 2021-01-12 9:38 ` frank.chang 2021-01-19 17:39 ` Alistair Francis 2021-01-19 17:39 ` Alistair Francis 2021-01-12 9:38 ` [PATCH v6 10/72] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers frank.chang 2021-01-12 9:38 ` frank.chang 2021-01-19 17:40 ` Alistair Francis 2021-01-19 17:40 ` Alistair Francis 2021-01-12 9:38 ` [PATCH v6 11/72] target/riscv: rvv-1.0: remove MLEN calculations frank.chang 2021-01-12 9:38 ` frank.chang 2021-01-19 17:41 ` Alistair Francis 2021-01-19 17:41 ` Alistair Francis 2021-01-12 9:38 ` [PATCH v6 12/72] target/riscv: rvv-1.0: add fractional LMUL frank.chang 2021-01-12 9:38 ` frank.chang 2021-01-19 18:43 ` Alistair Francis 2021-01-19 18:43 ` Alistair Francis 2021-01-12 9:38 ` [PATCH v6 13/72] target/riscv: rvv-1.0: add VMA and VTA frank.chang 2021-01-12 9:38 ` frank.chang 2021-01-19 18:51 ` Alistair Francis 2021-01-19 18:51 ` Alistair Francis 2021-01-12 9:38 ` [PATCH v6 14/72] target/riscv: rvv-1.0: update check functions frank.chang 2021-01-12 9:38 ` frank.chang 2021-01-28 21:15 ` Alistair Francis 2021-01-28 21:15 ` Alistair Francis 2021-01-12 9:38 ` [PATCH v6 15/72] target/riscv: introduce more imm value modes in translator functions frank.chang 2021-01-12 9:38 ` frank.chang 2021-01-19 18:55 ` Alistair Francis 2021-01-19 18:55 ` Alistair Francis 2021-01-12 9:38 ` [PATCH v6 16/72] target/riscv: rvv:1.0: add translation-time nan-box helper function frank.chang 2021-01-12 9:38 ` frank.chang 2021-01-19 18:58 ` Alistair Francis 2021-01-19 18:58 ` Alistair Francis 2021-01-12 9:38 ` [PATCH v6 17/72] target/riscv: rvv-1.0: configure instructions frank.chang 2021-01-12 9:38 ` frank.chang 2021-01-19 18:59 ` Alistair Francis 2021-01-19 18:59 ` Alistair Francis 2021-01-12 9:38 ` [PATCH v6 18/72] target/riscv: rvv-1.0: stride load and store instructions frank.chang 2021-01-12 9:38 ` frank.chang 2021-01-19 19:03 ` Alistair Francis 2021-01-19 19:03 ` Alistair Francis 2021-01-12 9:38 ` [PATCH v6 19/72] target/riscv: rvv-1.0: index " frank.chang 2021-01-12 9:38 ` frank.chang 2021-01-19 19:09 ` Alistair Francis 2021-01-19 19:09 ` Alistair Francis 2021-01-12 9:38 ` [PATCH v6 20/72] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns frank.chang 2021-01-12 9:38 ` frank.chang 2021-01-19 19:22 ` Alistair Francis 2021-01-19 19:22 ` Alistair Francis 2021-01-12 9:38 ` [PATCH v6 21/72] target/riscv: rvv-1.0: fault-only-first unit stride load frank.chang 2021-01-12 9:38 ` frank.chang 2021-01-19 19:19 ` Alistair Francis 2021-01-19 19:19 ` Alistair Francis 2021-01-12 9:38 ` [PATCH v6 22/72] target/riscv: rvv-1.0: amo operations frank.chang 2021-01-12 9:38 ` frank.chang 2021-01-25 23:19 ` Alistair Francis 2021-01-25 23:19 ` Alistair Francis 2021-01-12 9:38 ` [PATCH v6 23/72] target/riscv: rvv-1.0: load/store whole register instructions frank.chang 2021-01-12 9:38 ` frank.chang 2021-01-25 23:24 ` Alistair Francis 2021-01-25 23:24 ` Alistair Francis 2021-01-12 9:38 ` [PATCH v6 24/72] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns frank.chang 2021-01-12 9:38 ` frank.chang 2021-01-25 23:33 ` Alistair Francis 2021-01-25 23:33 ` Alistair Francis 2021-01-12 9:38 ` [PATCH v6 25/72] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation frank.chang 2021-01-12 9:38 ` frank.chang 2021-01-25 23:42 ` Alistair Francis 2021-01-25 23:42 ` Alistair Francis 2021-01-12 9:39 ` [PATCH v6 26/72] target/riscv: rvv-1.0: floating-point square-root instruction frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-25 23:49 ` Alistair Francis 2021-01-25 23:49 ` Alistair Francis 2021-01-12 9:39 ` [PATCH v6 27/72] target/riscv: rvv-1.0: floating-point classify instructions frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-25 23:50 ` Alistair Francis 2021-01-25 23:50 ` Alistair Francis 2021-01-12 9:39 ` [PATCH v6 28/72] target/riscv: rvv-1.0: mask population count instruction frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 29/72] target/riscv: rvv-1.0: find-first-set mask bit instruction frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 30/72] target/riscv: rvv-1.0: set-X-first mask bit instructions frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 31/72] target/riscv: rvv-1.0: iota instruction frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 32/72] target/riscv: rvv-1.0: element index instruction frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 33/72] target/riscv: rvv-1.0: allow load element with sign-extended frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 34/72] target/riscv: rvv-1.0: register gather instructions frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-28 21:18 ` Alistair Francis 2021-01-28 21:18 ` Alistair Francis 2021-01-12 9:39 ` [PATCH v6 35/72] target/riscv: rvv-1.0: integer scalar move instructions frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 36/72] target/riscv: rvv-1.0: floating-point move instruction frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-28 21:20 ` Alistair Francis 2021-01-28 21:20 ` Alistair Francis 2021-01-12 9:39 ` frank.chang [this message] 2021-01-12 9:39 ` [PATCH v6 37/72] target/riscv: rvv-1.0: floating-point scalar move instructions frank.chang 2021-01-12 9:39 ` [PATCH v6 38/72] target/riscv: rvv-1.0: whole register " frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 39/72] target/riscv: rvv-1.0: integer extension instructions frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 40/72] target/riscv: rvv-1.0: single-width averaging add and subtract instructions frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 41/72] target/riscv: rvv-1.0: single-width bit shift instructions frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 42/72] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 43/72] target/riscv: rvv-1.0: narrowing integer right shift instructions frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 44/72] target/riscv: rvv-1.0: widening integer multiply-add instructions frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 45/72] target/riscv: rvv-1.0: single-width saturating add and subtract instructions frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 46/72] target/riscv: rvv-1.0: integer comparison instructions frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 47/72] target/riscv: rvv-1.0: floating-point compare instructions frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 48/72] target/riscv: rvv-1.0: mask-register logical instructions frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 49/72] target/riscv: rvv-1.0: slide instructions frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 50/72] target/riscv: rvv-1.0: floating-point " frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 51/72] target/riscv: rvv-1.0: narrowing fixed-point clip instructions frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 52/72] target/riscv: rvv-1.0: single-width floating-point reduction frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 53/72] target/riscv: rvv-1.0: widening floating-point reduction instructions frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 54/72] target/riscv: rvv-1.0: single-width scaling shift instructions frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 55/72] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 56/72] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 57/72] target/riscv: rvv-1.0: remove integer extract instruction frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 58/72] target/riscv: rvv-1.0: floating-point min/max instructions frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 59/72] target/riscv: introduce floating-point rounding mode enum frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 60/72] target/riscv: rvv-1.0: floating-point/integer type-convert instructions frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 61/72] target/riscv: rvv-1.0: widening floating-point/integer type-convert frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 62/72] target/riscv: add "set round to odd" rounding mode helper function frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 63/72] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 64/72] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 65/72] target/riscv: rvv-1.0: implement vstart CSR frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 66/72] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 67/72] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-28 21:27 ` Alistair Francis 2021-01-28 21:27 ` Alistair Francis 2021-01-12 9:39 ` [PATCH v6 68/72] target/riscv: gdb: modify gdb csr xml file to align with csr register map frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-25 23:53 ` Alistair Francis 2021-01-25 23:53 ` Alistair Francis 2021-01-26 7:43 ` Frank Chang 2021-01-26 7:43 ` Frank Chang 2021-01-12 9:39 ` [PATCH v6 69/72] target/riscv: gdb: support vector registers for rv64 & rv32 frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 70/72] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 71/72] target/riscv: rvv-1.0: floating-point reciprocal " frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 9:39 ` [PATCH v6 72/72] target/riscv: set mstatus.SD bit when writing fp CSRs frank.chang 2021-01-12 9:39 ` frank.chang 2021-01-12 11:10 ` [PATCH v6 00/72] support vector extension v1.0 no-reply 2021-01-12 11:10 ` no-reply 2021-01-19 19:11 ` Alistair Francis 2021-01-19 19:11 ` Alistair Francis 2021-01-26 6:14 ` Frank Chang 2021-01-26 6:14 ` Frank Chang
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