[igt-dev] [PATCH 1/3] lib: Add stride and size calculation for amdgpu + tiling

[igt-dev] [PATCH 1/3] lib: Add stride and size calculation for amdgpu + tiling

[Sung Joon Kim]

For amdgpu, we need to calculate the stride and size of framebuffer correctly during non-linear tiling mode

v2: add call to amdgpu tiling/swizzle addressing
Signed-off-by: Sung Joon Kim <sungkim@amd.com>
---
 lib/igt_fb.c | 24 +++++++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 4b9be47e..6eebe048 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -671,6 +671,11 @@ static uint32_t calc_plane_stride(struct igt_fb *fb, int plane)
 		 * so the easiest way is to align the luma stride to 256.
 		 */
 		return ALIGN(min_stride, 256);
+	}else if (fb->modifier != LOCAL_DRM_FORMAT_MOD_NONE && is_amdgpu_device(fb->fd)) {
+		/*
+		 * For amdgpu device with tiling mode
+		 */
+		return ALIGN(min_stride, 512);
 	} else if (is_gen12_ccs_cc_plane(fb, plane)) {
 		/* clear color always fixed to 64 bytes */
 		return 64;
@@ -711,6 +716,12 @@ static uint64_t calc_plane_size(struct igt_fb *fb, int plane)
 		size = roundup_power_of_two(size);
 
 		return size;
+	} else if (fb->modifier != LOCAL_DRM_FORMAT_MOD_NONE && is_amdgpu_device(fb->fd)) {
+		/*
+		 * For amdgpu device with tiling mode
+		 */
+		return (uint64_t) fb->strides[plane] *
+			ALIGN(fb->plane_height[plane], 512);
 	} else if (is_gen12_ccs_plane(fb, plane)) {
 		/* The AUX CCS surface must be page aligned */
 		return (uint64_t)fb->strides[plane] *
@@ -2352,6 +2363,13 @@ static void free_linear_mapping(struct fb_blit_upload *blit)
 
 		vc4_fb_convert_plane_to_tiled(fb, map, &linear->fb, &linear->map);
 
+		munmap(map, fb->size);
+	} else if (is_amdgpu_device(fd) && fb->modifier != 0) {
+		void *map = igt_amd_mmap_bo(fd, fb->gem_handle, fb->size, PROT_WRITE);
+
+		igt_amd_fb_convert_plane_to_tiled(fb, map, &linear->fb, linear->map);
+
+		munmap(linear->map, fb->size);
 		munmap(map, fb->size);
 	} else {
 		gem_munmap(linear->map, linear->fb.size);
@@ -2419,6 +2437,10 @@ static void setup_linear_mapping(struct fb_blit_upload *blit)
 		vc4_fb_convert_plane_from_tiled(&linear->fb, &linear->map, fb, map);
 
 		munmap(map, fb->size);
+	} else if (is_amdgpu_device(fd) && fb->modifier != 0) {
+		linear->map = igt_amd_mmap_bo(fd, linear->fb.gem_handle,
+					      linear->fb.size,
+					      PROT_READ | PROT_WRITE);
 	} else {
 		/* Copy fb content to linear BO */
 		gem_set_domain(fd, linear->fb.gem_handle,
@@ -3625,7 +3647,7 @@ cairo_surface_t *igt_get_cairo_surface(int fd, struct igt_fb *fb)
 		if (use_convert(fb))
 			create_cairo_surface__convert(fd, fb);
 		else if (use_blitter(fb) || use_enginecopy(fb) ||
-			 igt_vc4_is_tiled(fb->modifier))
+			 igt_vc4_is_tiled(fb->modifier) || (is_amdgpu_device(fd) && fb->modifier != 0))
 			create_cairo_surface__gpu(fd, fb);
 		else
 			create_cairo_surface__gtt(fd, fb);
-- 
2.25.1

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[igt-dev] [PATCH 2/3] kms_rotation_crc:Add HW rotation test case for amdgpu

[Sung Joon Kim]

Added Hw rotation case specifically for amdgpu. Currently, kms_rotation_crc tests intel gpus. Added conditions to bypass all the requirements needed for intel when testing amdgpu.

v2: add crc equal assert since tiling/swizzle is implemented
Signed-off-by: Sung Joon Kim <sungkim@amd.com>
---
 tests/kms_rotation_crc.c | 270 ++++++++++++++++++++++++---------------
 1 file changed, 168 insertions(+), 102 deletions(-)

diff --git a/tests/kms_rotation_crc.c b/tests/kms_rotation_crc.c
index 33a97cca..31c7499c 100644
--- a/tests/kms_rotation_crc.c
+++ b/tests/kms_rotation_crc.c
@@ -197,6 +197,18 @@ static void prepare_crtc(data_t *data, igt_output_t *output, enum pipe pipe,
 	/* create the pipe_crc object for this pipe */
 	igt_pipe_crc_free(data->pipe_crc);
 
+	if (is_amdgpu_device(data->gfx_fd)) {
+		igt_fb_t fb_temp;
+		drmModeModeInfo *mode = igt_output_get_mode(output);
+
+		igt_create_fb(data->gfx_fd, mode->hdisplay, mode->vdisplay,
+				  DRM_FORMAT_XRGB8888, 0, &fb_temp);
+		igt_plane_set_fb(plane, &fb_temp);
+		paint_squares(data, IGT_ROTATION_0, &fb_temp, 1.0);
+
+		if (plane->type != DRM_PLANE_TYPE_CURSOR)
+			igt_plane_set_position(plane, data->pos_x, data->pos_y);
+	}
 	igt_display_commit2(display, COMMIT_ATOMIC);
 	data->pipe_crc = igt_pipe_crc_new(data->gfx_fd, pipe, INTEL_PIPE_CRC_SOURCE_AUTO);
 
@@ -213,6 +225,8 @@ static void prepare_fbs(data_t *data, igt_output_t *output,
 	uint64_t tiling = data->override_tiling ?: LOCAL_DRM_FORMAT_MOD_NONE;
 	uint32_t pixel_format = data->override_fmt ?: DRM_FORMAT_XRGB8888;
 	const float flip_opacity = 0.75;
+	bool amd_gpu = is_amdgpu_device(data->gfx_fd);
+	bool intel_gpu = is_i915_device(data->gfx_fd);
 
 	remove_fbs(data);
 
@@ -220,16 +234,21 @@ static void prepare_fbs(data_t *data, igt_output_t *output,
 
 	mode = igt_output_get_mode(output);
 	if (plane->type != DRM_PLANE_TYPE_CURSOR) {
-		if (data->use_native_resolution) {
+		if (amd_gpu) {
 			w = mode->hdisplay;
 			h = mode->vdisplay;
-		} else {
-			w = min(TEST_MAX_WIDTH, mode->hdisplay);
-			h = min(TEST_MAX_HEIGHT, mode->vdisplay);
-		}
+		} else if (intel_gpu) {
+			if (data->use_native_resolution) {
+				w = mode->hdisplay;
+				h = mode->vdisplay;
+			} else {
+				w = min(TEST_MAX_WIDTH, mode->hdisplay);
+				h = min(TEST_MAX_HEIGHT, mode->vdisplay);
+			}
 
-		min_w = 256;
-		min_h = 256;
+			min_w = 256;
+			min_h = 256;
+		}
 	} else {
 		pixel_format = data->override_fmt ?: DRM_FORMAT_ARGB8888;
 
@@ -261,7 +280,8 @@ static void prepare_fbs(data_t *data, igt_output_t *output,
 	 * frame can fit in
 	 */
 	if (data->rotation & (IGT_ROTATION_90 | IGT_ROTATION_270)) {
-		tiling = data->override_tiling ?: LOCAL_I915_FORMAT_MOD_Y_TILED;
+		if (intel_gpu)
+			tiling = data->override_tiling ?: LOCAL_I915_FORMAT_MOD_Y_TILED;
 
 		igt_swap(w, h);
 	}
@@ -272,45 +292,62 @@ static void prepare_fbs(data_t *data, igt_output_t *output,
 	 */
 	igt_require(igt_display_has_format_mod(display, pixel_format, tiling));
 
-	if (!data->crc_rect[rect].valid) {
-		/*
-		* Create a reference software rotated flip framebuffer.
-		*/
-		igt_create_fb(data->gfx_fd, ref_w, ref_h, pixel_format, tiling,
-			&data->fb_flip);
-		paint_squares(data, data->rotation, &data->fb_flip,
-			flip_opacity);
-		igt_plane_set_fb(plane, &data->fb_flip);
-		if (plane->type != DRM_PLANE_TYPE_CURSOR)
-			igt_plane_set_position(plane, data->pos_x, data->pos_y);
-		igt_display_commit2(display, COMMIT_ATOMIC);
-
-		igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &data->crc_rect[rect].flip_crc);
-		igt_remove_fb(data->gfx_fd, &data->fb_flip);
+	if (intel_gpu) {
+		if (!data->crc_rect[rect].valid) {
+			/*
+			* Create a reference software rotated flip framebuffer.
+			*/
+			igt_create_fb(data->gfx_fd, ref_w, ref_h, pixel_format, tiling,
+				&data->fb_flip);
+			paint_squares(data, data->rotation, &data->fb_flip,
+				flip_opacity);
+			igt_plane_set_fb(plane, &data->fb_flip);
+			if (plane->type != DRM_PLANE_TYPE_CURSOR)
+				igt_plane_set_position(plane, data->pos_x, data->pos_y);
+			igt_display_commit2(display, COMMIT_ATOMIC);
+
+			igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &data->crc_rect[rect].flip_crc);
+			igt_remove_fb(data->gfx_fd, &data->fb_flip);
+
+			/*
+			* Create a reference CRC for a software-rotated fb.
+			*/
+			igt_create_fb(data->gfx_fd, ref_w, ref_h, pixel_format,
+				data->override_tiling ?: LOCAL_DRM_FORMAT_MOD_NONE, &data->fb_reference);
+			paint_squares(data, data->rotation, &data->fb_reference, 1.0);
+
+			igt_plane_set_fb(plane, &data->fb_reference);
+			if (plane->type != DRM_PLANE_TYPE_CURSOR)
+				igt_plane_set_position(plane, data->pos_x, data->pos_y);
+			igt_display_commit2(display, COMMIT_ATOMIC);
+
+			igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &data->crc_rect[rect].ref_crc);
+			data->crc_rect[rect].valid = true;
+		}
 
 		/*
-		* Create a reference CRC for a software-rotated fb.
-		*/
+		  * Prepare the non-rotated flip fb.
+		  */
+		igt_create_fb(data->gfx_fd, w, h, pixel_format, tiling,
+			      &data->fb_flip);
+		paint_squares(data, IGT_ROTATION_0, &data->fb_flip,
+			      flip_opacity);
+	} else if (amd_gpu) {
+		tiling = 0x900;
 		igt_create_fb(data->gfx_fd, ref_w, ref_h, pixel_format,
-			data->override_tiling ?: LOCAL_DRM_FORMAT_MOD_NONE, &data->fb_reference);
+				  LOCAL_DRM_FORMAT_MOD_NONE, &data->fb_reference);
 		paint_squares(data, data->rotation, &data->fb_reference, 1.0);
 
 		igt_plane_set_fb(plane, &data->fb_reference);
 		if (plane->type != DRM_PLANE_TYPE_CURSOR)
 			igt_plane_set_position(plane, data->pos_x, data->pos_y);
-		igt_display_commit2(display, COMMIT_ATOMIC);
 
-		igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &data->crc_rect[rect].ref_crc);
-		data->crc_rect[rect].valid = true;
-	}
+		if (data->rotation & (IGT_ROTATION_90 | IGT_ROTATION_270))
+			igt_plane_set_size(plane, ref_w, ref_h);
 
-	/*
-	  * Prepare the non-rotated flip fb.
-	  */
-	igt_create_fb(data->gfx_fd, w, h, pixel_format, tiling,
-		      &data->fb_flip);
-	paint_squares(data, IGT_ROTATION_0, &data->fb_flip,
-		      flip_opacity);
+		igt_display_commit2(display, COMMIT_ATOMIC);
+		igt_pipe_crc_collect_crc(data->pipe_crc, &data->ref_crc);
+	}
 
 	/*
 	 * Prepare the plane with an non-rotated fb let the hw rotate it.
@@ -349,32 +386,37 @@ static void test_single_case(data_t *data, enum pipe pipe,
 	/* Verify commit was ok. */
 	igt_assert_eq(ret, 0);
 
-	/* Check CRC */
-	igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &crc_output);
-	igt_assert_crc_equal(&data->crc_rect[rect].ref_crc, &crc_output);
+	if (is_i915_device(data->gfx_fd)) {
+		/* Check CRC */
+		igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &crc_output);
+		igt_assert_crc_equal(&data->crc_rect[rect].ref_crc, &crc_output);
 
-	/*
-	 * If flips are requested flip to a different fb and
-	 * check CRC against that one as well.
-	 */
-	if (data->fb_flip.fb_id) {
-		igt_plane_set_fb(plane, &data->fb_flip);
-		if (data->rotation == IGT_ROTATION_90 || data->rotation == IGT_ROTATION_270)
-			igt_plane_set_size(plane, data->fb.height, data->fb.width);
-
-		if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
-			igt_display_commit_atomic(display, DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_ATOMIC_NONBLOCK, NULL);
-		} else {
-			ret = drmModePageFlip(data->gfx_fd,
-					output->config.crtc->crtc_id,
-					data->fb_flip.fb_id,
-					DRM_MODE_PAGE_FLIP_EVENT,
-					NULL);
-			igt_assert_eq(ret, 0);
+		/*
+		 * If flips are requested flip to a different fb and
+		 * check CRC against that one as well.
+		 */
+		if (data->fb_flip.fb_id) {
+			igt_plane_set_fb(plane, &data->fb_flip);
+			if (data->rotation == IGT_ROTATION_90 || data->rotation == IGT_ROTATION_270)
+				igt_plane_set_size(plane, data->fb.height, data->fb.width);
+
+			if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
+				igt_display_commit_atomic(display, DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_ATOMIC_NONBLOCK, NULL);
+			} else {
+				ret = drmModePageFlip(data->gfx_fd,
+						output->config.crtc->crtc_id,
+						data->fb_flip.fb_id,
+						DRM_MODE_PAGE_FLIP_EVENT,
+						NULL);
+				igt_assert_eq(ret, 0);
+			}
+			kmstest_wait_for_pageflip(data->gfx_fd);
+			igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &crc_output);
+			igt_assert_crc_equal(&data->crc_rect[rect].flip_crc, &crc_output);
 		}
-		kmstest_wait_for_pageflip(data->gfx_fd);
-		igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &crc_output);
-		igt_assert_crc_equal(&data->crc_rect[rect].flip_crc, &crc_output);
+	} else if (is_amdgpu_device(data->gfx_fd)) {
+		igt_pipe_crc_collect_crc(data->pipe_crc, &crc_output);
+		igt_assert_crc_equal(&data->ref_crc, &crc_output);
 	}
 }
 
@@ -415,57 +457,77 @@ static void test_plane_rotation(data_t *data, int plane_type, bool test_bad_form
 		igt_plane_t *plane;
 		int i, j, c;
 
-		for (c = 0; c < num_rectangle_types; c++)
-			data->crc_rect[c].valid = false;
-
-		if (IS_CHERRYVIEW(data->devid) && pipe != PIPE_B)
-			continue;
+		if (is_i915_device(data->gfx_fd)) {
+			for (c = 0; c < num_rectangle_types; c++)
+				data->crc_rect[c].valid = false;
 
-		igt_output_set_pipe(output, pipe);
+			if (IS_CHERRYVIEW(data->devid) && pipe != PIPE_B)
+				continue;
 
-		plane = igt_output_get_plane_type(output, plane_type);
-		igt_require(igt_plane_has_prop(plane, IGT_PLANE_ROTATION));
+			igt_output_set_pipe(output, pipe);
 
-		prepare_crtc(data, output, pipe, plane, true);
+			plane = igt_output_get_plane_type(output, plane_type);
+			igt_require(igt_plane_has_prop(plane, IGT_PLANE_ROTATION));
 
-		for (i = 0; i < num_rectangle_types; i++) {
-			/* Unsupported on i915 */
-			if (plane_type == DRM_PLANE_TYPE_CURSOR &&
-			    i != square)
-				continue;
+			prepare_crtc(data, output, pipe, plane, true);
 
-			/* Only support partial covering primary plane on gen9+ */
-			if (plane_type == DRM_PLANE_TYPE_PRIMARY &&
-			    intel_gen(intel_get_drm_devid(data->gfx_fd)) < 9) {
-				if (i != rectangle)
+			for (i = 0; i < num_rectangle_types; i++) {
+				/* Unsupported on i915 */
+				if (plane_type == DRM_PLANE_TYPE_CURSOR &&
+				    i != square)
 					continue;
-				else
-					data->use_native_resolution = true;
-			} else {
-				data->use_native_resolution = false;
-			}
 
-			if (!data->override_fmt) {
-				struct igt_vec tested_formats;
+				/* Only support partial covering primary plane on gen9+ */
+				if (plane_type == DRM_PLANE_TYPE_PRIMARY &&
+				    intel_gen(intel_get_drm_devid(data->gfx_fd)) < 9) {
+					if (i != rectangle)
+						continue;
+					else
+						data->use_native_resolution = true;
+				} else {
+					data->use_native_resolution = false;
+				}
 
-				igt_vec_init(&tested_formats, sizeof(uint32_t));
+				if (!data->override_fmt) {
+					struct igt_vec tested_formats;
 
-				for (j = 0; j < plane->drm_plane->count_formats; j++) {
-					uint32_t format = plane->drm_plane->formats[j];
+					igt_vec_init(&tested_formats, sizeof(uint32_t));
 
-					if (!test_format(data, &tested_formats, format))
-						continue;
+					for (j = 0; j < plane->drm_plane->count_formats; j++) {
+						uint32_t format = plane->drm_plane->formats[j];
 
+						if (!test_format(data, &tested_formats, format))
+							continue;
+
+						test_single_case(data, pipe, output, plane, i,
+								 format, test_bad_format);
+					}
+
+					igt_vec_fini(&tested_formats);
+				} else {
 					test_single_case(data, pipe, output, plane, i,
-							 format, test_bad_format);
+							 data->override_fmt, test_bad_format);
 				}
+			}
+		} else if (is_amdgpu_device(data->gfx_fd)) {
+			uint32_t format = DRM_FORMAT_XRGB8888;
 
-				igt_vec_fini(&tested_formats);
-			} else {
-				test_single_case(data, pipe, output, plane, i,
-						 data->override_fmt, test_bad_format);
+			igt_output_set_pipe(output, pipe);
+
+			plane = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
+			igt_require(igt_plane_has_prop(plane, IGT_PLANE_ROTATION));
+
+			prepare_crtc(data, output, pipe, plane, false);
+
+			if (plane_type != DRM_PLANE_TYPE_PRIMARY) {
+				plane = igt_output_get_plane_type(output, plane_type);
+				igt_require(igt_plane_has_prop(plane, IGT_PLANE_ROTATION));
 			}
+
+			test_single_case(data, pipe, output, plane,
+					 rectangle, format, test_bad_format);
 		}
+
 		igt_pipe_crc_stop(data->pipe_crc);
 	}
 }
@@ -844,9 +906,11 @@ igt_main_args("", long_opts, help_str, opt_handler, &data)
 	int gen = 0;
 
 	igt_fixture {
-		data.gfx_fd = drm_open_driver_master(DRIVER_INTEL);
-		data.devid = intel_get_drm_devid(data.gfx_fd);
-		gen = intel_gen(data.devid);
+		data.gfx_fd = drm_open_driver_master(DRIVER_INTEL | DRIVER_AMDGPU);
+		if (is_i915_device(data.gfx_fd)) {
+			data.devid = intel_get_drm_devid(data.gfx_fd);
+			gen = intel_gen(data.devid);
+		}
 
 		kmstest_set_vt_graphics_mode();
 
@@ -860,9 +924,11 @@ igt_main_args("", long_opts, help_str, opt_handler, &data)
 		igt_subtest_f("%s-rotation-%s",
 			      plane_test_str(subtest->plane),
 			      rot_test_str(subtest->rot)) {
-			igt_require(!(subtest->rot &
-				    (IGT_ROTATION_90 | IGT_ROTATION_270)) ||
-				    gen >= 9);
+			if (is_i915_device(data.gfx_fd)) {
+				igt_require(!(subtest->rot &
+					    (IGT_ROTATION_90 | IGT_ROTATION_270)) ||
+					    gen >= 9);
+			}
 			data.rotation = subtest->rot;
 			test_plane_rotation(&data, subtest->plane, false);
 		}
-- 
2.25.1

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Re: [igt-dev] [PATCH 2/3] kms_rotation_crc:Add HW rotation test case for amdgpu

[Cornij, Nikola]

[AMD Public Use]

Reviewed by: Nikola Cornij < nikola.cornij@amd.com>

-----Original Message-----
From: Kim, Sung joon <Sungjoon.Kim@amd.com> 
Sent: Tuesday, January 12, 2021 5:54 PM
To: igt-dev@lists.freedesktop.org
Cc: Kazlauskas, Nicholas <Nicholas.Kazlauskas@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>; Cornij, Nikola <Nikola.Cornij@amd.com>; Kim, Sung joon <Sungjoon.Kim@amd.com>
Subject: [PATCH 2/3] kms_rotation_crc:Add HW rotation test case for amdgpu

Added Hw rotation case specifically for amdgpu. Currently, kms_rotation_crc tests intel gpus. Added conditions to bypass all the requirements needed for intel when testing amdgpu.

v2: add crc equal assert since tiling/swizzle is implemented
Signed-off-by: Sung Joon Kim <sungkim@amd.com>
---
 tests/kms_rotation_crc.c | 270 ++++++++++++++++++++++++---------------
 1 file changed, 168 insertions(+), 102 deletions(-)

diff --git a/tests/kms_rotation_crc.c b/tests/kms_rotation_crc.c index 33a97cca..31c7499c 100644
--- a/tests/kms_rotation_crc.c
+++ b/tests/kms_rotation_crc.c
@@ -197,6 +197,18 @@ static void prepare_crtc(data_t *data, igt_output_t *output, enum pipe pipe,
 	/* create the pipe_crc object for this pipe */
 	igt_pipe_crc_free(data->pipe_crc);
 
+	if (is_amdgpu_device(data->gfx_fd)) {
+		igt_fb_t fb_temp;
+		drmModeModeInfo *mode = igt_output_get_mode(output);
+
+		igt_create_fb(data->gfx_fd, mode->hdisplay, mode->vdisplay,
+				  DRM_FORMAT_XRGB8888, 0, &fb_temp);
+		igt_plane_set_fb(plane, &fb_temp);
+		paint_squares(data, IGT_ROTATION_0, &fb_temp, 1.0);
+
+		if (plane->type != DRM_PLANE_TYPE_CURSOR)
+			igt_plane_set_position(plane, data->pos_x, data->pos_y);
+	}
 	igt_display_commit2(display, COMMIT_ATOMIC);
 	data->pipe_crc = igt_pipe_crc_new(data->gfx_fd, pipe, INTEL_PIPE_CRC_SOURCE_AUTO);
 
@@ -213,6 +225,8 @@ static void prepare_fbs(data_t *data, igt_output_t *output,
 	uint64_t tiling = data->override_tiling ?: LOCAL_DRM_FORMAT_MOD_NONE;
 	uint32_t pixel_format = data->override_fmt ?: DRM_FORMAT_XRGB8888;
 	const float flip_opacity = 0.75;
+	bool amd_gpu = is_amdgpu_device(data->gfx_fd);
+	bool intel_gpu = is_i915_device(data->gfx_fd);
 
 	remove_fbs(data);
 
@@ -220,16 +234,21 @@ static void prepare_fbs(data_t *data, igt_output_t *output,
 
 	mode = igt_output_get_mode(output);
 	if (plane->type != DRM_PLANE_TYPE_CURSOR) {
-		if (data->use_native_resolution) {
+		if (amd_gpu) {
 			w = mode->hdisplay;
 			h = mode->vdisplay;
-		} else {
-			w = min(TEST_MAX_WIDTH, mode->hdisplay);
-			h = min(TEST_MAX_HEIGHT, mode->vdisplay);
-		}
+		} else if (intel_gpu) {
+			if (data->use_native_resolution) {
+				w = mode->hdisplay;
+				h = mode->vdisplay;
+			} else {
+				w = min(TEST_MAX_WIDTH, mode->hdisplay);
+				h = min(TEST_MAX_HEIGHT, mode->vdisplay);
+			}
 
-		min_w = 256;
-		min_h = 256;
+			min_w = 256;
+			min_h = 256;
+		}
 	} else {
 		pixel_format = data->override_fmt ?: DRM_FORMAT_ARGB8888;
 
@@ -261,7 +280,8 @@ static void prepare_fbs(data_t *data, igt_output_t *output,
 	 * frame can fit in
 	 */
 	if (data->rotation & (IGT_ROTATION_90 | IGT_ROTATION_270)) {
-		tiling = data->override_tiling ?: LOCAL_I915_FORMAT_MOD_Y_TILED;
+		if (intel_gpu)
+			tiling = data->override_tiling ?: LOCAL_I915_FORMAT_MOD_Y_TILED;
 
 		igt_swap(w, h);
 	}
@@ -272,45 +292,62 @@ static void prepare_fbs(data_t *data, igt_output_t *output,
 	 */
 	igt_require(igt_display_has_format_mod(display, pixel_format, tiling));
 
-	if (!data->crc_rect[rect].valid) {
-		/*
-		* Create a reference software rotated flip framebuffer.
-		*/
-		igt_create_fb(data->gfx_fd, ref_w, ref_h, pixel_format, tiling,
-			&data->fb_flip);
-		paint_squares(data, data->rotation, &data->fb_flip,
-			flip_opacity);
-		igt_plane_set_fb(plane, &data->fb_flip);
-		if (plane->type != DRM_PLANE_TYPE_CURSOR)
-			igt_plane_set_position(plane, data->pos_x, data->pos_y);
-		igt_display_commit2(display, COMMIT_ATOMIC);
-
-		igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &data->crc_rect[rect].flip_crc);
-		igt_remove_fb(data->gfx_fd, &data->fb_flip);
+	if (intel_gpu) {
+		if (!data->crc_rect[rect].valid) {
+			/*
+			* Create a reference software rotated flip framebuffer.
+			*/
+			igt_create_fb(data->gfx_fd, ref_w, ref_h, pixel_format, tiling,
+				&data->fb_flip);
+			paint_squares(data, data->rotation, &data->fb_flip,
+				flip_opacity);
+			igt_plane_set_fb(plane, &data->fb_flip);
+			if (plane->type != DRM_PLANE_TYPE_CURSOR)
+				igt_plane_set_position(plane, data->pos_x, data->pos_y);
+			igt_display_commit2(display, COMMIT_ATOMIC);
+
+			igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &data->crc_rect[rect].flip_crc);
+			igt_remove_fb(data->gfx_fd, &data->fb_flip);
+
+			/*
+			* Create a reference CRC for a software-rotated fb.
+			*/
+			igt_create_fb(data->gfx_fd, ref_w, ref_h, pixel_format,
+				data->override_tiling ?: LOCAL_DRM_FORMAT_MOD_NONE, &data->fb_reference);
+			paint_squares(data, data->rotation, &data->fb_reference, 1.0);
+
+			igt_plane_set_fb(plane, &data->fb_reference);
+			if (plane->type != DRM_PLANE_TYPE_CURSOR)
+				igt_plane_set_position(plane, data->pos_x, data->pos_y);
+			igt_display_commit2(display, COMMIT_ATOMIC);
+
+			igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &data->crc_rect[rect].ref_crc);
+			data->crc_rect[rect].valid = true;
+		}
 
 		/*
-		* Create a reference CRC for a software-rotated fb.
-		*/
+		  * Prepare the non-rotated flip fb.
+		  */
+		igt_create_fb(data->gfx_fd, w, h, pixel_format, tiling,
+			      &data->fb_flip);
+		paint_squares(data, IGT_ROTATION_0, &data->fb_flip,
+			      flip_opacity);
+	} else if (amd_gpu) {
+		tiling = 0x900;
 		igt_create_fb(data->gfx_fd, ref_w, ref_h, pixel_format,
-			data->override_tiling ?: LOCAL_DRM_FORMAT_MOD_NONE, &data->fb_reference);
+				  LOCAL_DRM_FORMAT_MOD_NONE, &data->fb_reference);
 		paint_squares(data, data->rotation, &data->fb_reference, 1.0);
 
 		igt_plane_set_fb(plane, &data->fb_reference);
 		if (plane->type != DRM_PLANE_TYPE_CURSOR)
 			igt_plane_set_position(plane, data->pos_x, data->pos_y);
-		igt_display_commit2(display, COMMIT_ATOMIC);
 
-		igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &data->crc_rect[rect].ref_crc);
-		data->crc_rect[rect].valid = true;
-	}
+		if (data->rotation & (IGT_ROTATION_90 | IGT_ROTATION_270))
+			igt_plane_set_size(plane, ref_w, ref_h);
 
-	/*
-	  * Prepare the non-rotated flip fb.
-	  */
-	igt_create_fb(data->gfx_fd, w, h, pixel_format, tiling,
-		      &data->fb_flip);
-	paint_squares(data, IGT_ROTATION_0, &data->fb_flip,
-		      flip_opacity);
+		igt_display_commit2(display, COMMIT_ATOMIC);
+		igt_pipe_crc_collect_crc(data->pipe_crc, &data->ref_crc);
+	}
 
 	/*
 	 * Prepare the plane with an non-rotated fb let the hw rotate it.
@@ -349,32 +386,37 @@ static void test_single_case(data_t *data, enum pipe pipe,
 	/* Verify commit was ok. */
 	igt_assert_eq(ret, 0);
 
-	/* Check CRC */
-	igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &crc_output);
-	igt_assert_crc_equal(&data->crc_rect[rect].ref_crc, &crc_output);
+	if (is_i915_device(data->gfx_fd)) {
+		/* Check CRC */
+		igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &crc_output);
+		igt_assert_crc_equal(&data->crc_rect[rect].ref_crc, &crc_output);
 
-	/*
-	 * If flips are requested flip to a different fb and
-	 * check CRC against that one as well.
-	 */
-	if (data->fb_flip.fb_id) {
-		igt_plane_set_fb(plane, &data->fb_flip);
-		if (data->rotation == IGT_ROTATION_90 || data->rotation == IGT_ROTATION_270)
-			igt_plane_set_size(plane, data->fb.height, data->fb.width);
-
-		if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
-			igt_display_commit_atomic(display, DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_ATOMIC_NONBLOCK, NULL);
-		} else {
-			ret = drmModePageFlip(data->gfx_fd,
-					output->config.crtc->crtc_id,
-					data->fb_flip.fb_id,
-					DRM_MODE_PAGE_FLIP_EVENT,
-					NULL);
-			igt_assert_eq(ret, 0);
+		/*
+		 * If flips are requested flip to a different fb and
+		 * check CRC against that one as well.
+		 */
+		if (data->fb_flip.fb_id) {
+			igt_plane_set_fb(plane, &data->fb_flip);
+			if (data->rotation == IGT_ROTATION_90 || data->rotation == IGT_ROTATION_270)
+				igt_plane_set_size(plane, data->fb.height, data->fb.width);
+
+			if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
+				igt_display_commit_atomic(display, DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_ATOMIC_NONBLOCK, NULL);
+			} else {
+				ret = drmModePageFlip(data->gfx_fd,
+						output->config.crtc->crtc_id,
+						data->fb_flip.fb_id,
+						DRM_MODE_PAGE_FLIP_EVENT,
+						NULL);
+				igt_assert_eq(ret, 0);
+			}
+			kmstest_wait_for_pageflip(data->gfx_fd);
+			igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &crc_output);
+			igt_assert_crc_equal(&data->crc_rect[rect].flip_crc, &crc_output);
 		}
-		kmstest_wait_for_pageflip(data->gfx_fd);
-		igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &crc_output);
-		igt_assert_crc_equal(&data->crc_rect[rect].flip_crc, &crc_output);
+	} else if (is_amdgpu_device(data->gfx_fd)) {
+		igt_pipe_crc_collect_crc(data->pipe_crc, &crc_output);
+		igt_assert_crc_equal(&data->ref_crc, &crc_output);
 	}
 }
 
@@ -415,57 +457,77 @@ static void test_plane_rotation(data_t *data, int plane_type, bool test_bad_form
 		igt_plane_t *plane;
 		int i, j, c;
 
-		for (c = 0; c < num_rectangle_types; c++)
-			data->crc_rect[c].valid = false;
-
-		if (IS_CHERRYVIEW(data->devid) && pipe != PIPE_B)
-			continue;
+		if (is_i915_device(data->gfx_fd)) {
+			for (c = 0; c < num_rectangle_types; c++)
+				data->crc_rect[c].valid = false;
 
-		igt_output_set_pipe(output, pipe);
+			if (IS_CHERRYVIEW(data->devid) && pipe != PIPE_B)
+				continue;
 
-		plane = igt_output_get_plane_type(output, plane_type);
-		igt_require(igt_plane_has_prop(plane, IGT_PLANE_ROTATION));
+			igt_output_set_pipe(output, pipe);
 
-		prepare_crtc(data, output, pipe, plane, true);
+			plane = igt_output_get_plane_type(output, plane_type);
+			igt_require(igt_plane_has_prop(plane, IGT_PLANE_ROTATION));
 
-		for (i = 0; i < num_rectangle_types; i++) {
-			/* Unsupported on i915 */
-			if (plane_type == DRM_PLANE_TYPE_CURSOR &&
-			    i != square)
-				continue;
+			prepare_crtc(data, output, pipe, plane, true);
 
-			/* Only support partial covering primary plane on gen9+ */
-			if (plane_type == DRM_PLANE_TYPE_PRIMARY &&
-			    intel_gen(intel_get_drm_devid(data->gfx_fd)) < 9) {
-				if (i != rectangle)
+			for (i = 0; i < num_rectangle_types; i++) {
+				/* Unsupported on i915 */
+				if (plane_type == DRM_PLANE_TYPE_CURSOR &&
+				    i != square)
 					continue;
-				else
-					data->use_native_resolution = true;
-			} else {
-				data->use_native_resolution = false;
-			}
 
-			if (!data->override_fmt) {
-				struct igt_vec tested_formats;
+				/* Only support partial covering primary plane on gen9+ */
+				if (plane_type == DRM_PLANE_TYPE_PRIMARY &&
+				    intel_gen(intel_get_drm_devid(data->gfx_fd)) < 9) {
+					if (i != rectangle)
+						continue;
+					else
+						data->use_native_resolution = true;
+				} else {
+					data->use_native_resolution = false;
+				}
 
-				igt_vec_init(&tested_formats, sizeof(uint32_t));
+				if (!data->override_fmt) {
+					struct igt_vec tested_formats;
 
-				for (j = 0; j < plane->drm_plane->count_formats; j++) {
-					uint32_t format = plane->drm_plane->formats[j];
+					igt_vec_init(&tested_formats, sizeof(uint32_t));
 
-					if (!test_format(data, &tested_formats, format))
-						continue;
+					for (j = 0; j < plane->drm_plane->count_formats; j++) {
+						uint32_t format = plane->drm_plane->formats[j];
 
+						if (!test_format(data, &tested_formats, format))
+							continue;
+
+						test_single_case(data, pipe, output, plane, i,
+								 format, test_bad_format);
+					}
+
+					igt_vec_fini(&tested_formats);
+				} else {
 					test_single_case(data, pipe, output, plane, i,
-							 format, test_bad_format);
+							 data->override_fmt, test_bad_format);
 				}
+			}
+		} else if (is_amdgpu_device(data->gfx_fd)) {
+			uint32_t format = DRM_FORMAT_XRGB8888;
 
-				igt_vec_fini(&tested_formats);
-			} else {
-				test_single_case(data, pipe, output, plane, i,
-						 data->override_fmt, test_bad_format);
+			igt_output_set_pipe(output, pipe);
+
+			plane = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
+			igt_require(igt_plane_has_prop(plane, IGT_PLANE_ROTATION));
+
+			prepare_crtc(data, output, pipe, plane, false);
+
+			if (plane_type != DRM_PLANE_TYPE_PRIMARY) {
+				plane = igt_output_get_plane_type(output, plane_type);
+				igt_require(igt_plane_has_prop(plane, IGT_PLANE_ROTATION));
 			}
+
+			test_single_case(data, pipe, output, plane,
+					 rectangle, format, test_bad_format);
 		}
+
 		igt_pipe_crc_stop(data->pipe_crc);
 	}
 }
@@ -844,9 +906,11 @@ igt_main_args("", long_opts, help_str, opt_handler, &data)
 	int gen = 0;
 
 	igt_fixture {
-		data.gfx_fd = drm_open_driver_master(DRIVER_INTEL);
-		data.devid = intel_get_drm_devid(data.gfx_fd);
-		gen = intel_gen(data.devid);
+		data.gfx_fd = drm_open_driver_master(DRIVER_INTEL | DRIVER_AMDGPU);
+		if (is_i915_device(data.gfx_fd)) {
+			data.devid = intel_get_drm_devid(data.gfx_fd);
+			gen = intel_gen(data.devid);
+		}
 
 		kmstest_set_vt_graphics_mode();
 
@@ -860,9 +924,11 @@ igt_main_args("", long_opts, help_str, opt_handler, &data)
 		igt_subtest_f("%s-rotation-%s",
 			      plane_test_str(subtest->plane),
 			      rot_test_str(subtest->rot)) {
-			igt_require(!(subtest->rot &
-				    (IGT_ROTATION_90 | IGT_ROTATION_270)) ||
-				    gen >= 9);
+			if (is_i915_device(data.gfx_fd)) {
+				igt_require(!(subtest->rot &
+					    (IGT_ROTATION_90 | IGT_ROTATION_270)) ||
+					    gen >= 9);
+			}
 			data.rotation = subtest->rot;
 			test_plane_rotation(&data, subtest->plane, false);
 		}
--
2.25.1
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Re: [igt-dev] [PATCH 2/3] kms_rotation_crc:Add HW rotation test case for amdgpu

[Cornij, Nikola]

-----Original Message-----
From: Kim, Sung joon <Sungjoon.Kim@amd.com> 
Sent: Tuesday, January 12, 2021 5:54 PM
To: igt-dev@lists.freedesktop.org
Cc: Kazlauskas, Nicholas <Nicholas.Kazlauskas@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>; Cornij, Nikola <Nikola.Cornij@amd.com>; Kim, Sung joon <Sungjoon.Kim@amd.com>
Subject: [PATCH 2/3] kms_rotation_crc:Add HW rotation test case for amdgpu

Added Hw rotation case specifically for amdgpu. Currently, kms_rotation_crc tests intel gpus. Added conditions to bypass all the requirements needed for intel when testing amdgpu.

v2: add crc equal assert since tiling/swizzle is implemented
Signed-off-by: Sung Joon Kim <sungkim@amd.com>
Reviewed by: Nikola Cornij <nikola.cornij@amd.com>
---
 tests/kms_rotation_crc.c | 270 ++++++++++++++++++++++++---------------
 1 file changed, 168 insertions(+), 102 deletions(-)

diff --git a/tests/kms_rotation_crc.c b/tests/kms_rotation_crc.c index 33a97cca..31c7499c 100644
--- a/tests/kms_rotation_crc.c
+++ b/tests/kms_rotation_crc.c
@@ -197,6 +197,18 @@ static void prepare_crtc(data_t *data, igt_output_t *output, enum pipe pipe,
 	/* create the pipe_crc object for this pipe */
 	igt_pipe_crc_free(data->pipe_crc);
 
+	if (is_amdgpu_device(data->gfx_fd)) {
+		igt_fb_t fb_temp;
+		drmModeModeInfo *mode = igt_output_get_mode(output);
+
+		igt_create_fb(data->gfx_fd, mode->hdisplay, mode->vdisplay,
+				  DRM_FORMAT_XRGB8888, 0, &fb_temp);
+		igt_plane_set_fb(plane, &fb_temp);
+		paint_squares(data, IGT_ROTATION_0, &fb_temp, 1.0);
+
+		if (plane->type != DRM_PLANE_TYPE_CURSOR)
+			igt_plane_set_position(plane, data->pos_x, data->pos_y);
+	}
 	igt_display_commit2(display, COMMIT_ATOMIC);
 	data->pipe_crc = igt_pipe_crc_new(data->gfx_fd, pipe, INTEL_PIPE_CRC_SOURCE_AUTO);
 
@@ -213,6 +225,8 @@ static void prepare_fbs(data_t *data, igt_output_t *output,
 	uint64_t tiling = data->override_tiling ?: LOCAL_DRM_FORMAT_MOD_NONE;
 	uint32_t pixel_format = data->override_fmt ?: DRM_FORMAT_XRGB8888;
 	const float flip_opacity = 0.75;
+	bool amd_gpu = is_amdgpu_device(data->gfx_fd);
+	bool intel_gpu = is_i915_device(data->gfx_fd);
 
 	remove_fbs(data);
 
@@ -220,16 +234,21 @@ static void prepare_fbs(data_t *data, igt_output_t *output,
 
 	mode = igt_output_get_mode(output);
 	if (plane->type != DRM_PLANE_TYPE_CURSOR) {
-		if (data->use_native_resolution) {
+		if (amd_gpu) {
 			w = mode->hdisplay;
 			h = mode->vdisplay;
-		} else {
-			w = min(TEST_MAX_WIDTH, mode->hdisplay);
-			h = min(TEST_MAX_HEIGHT, mode->vdisplay);
-		}
+		} else if (intel_gpu) {
+			if (data->use_native_resolution) {
+				w = mode->hdisplay;
+				h = mode->vdisplay;
+			} else {
+				w = min(TEST_MAX_WIDTH, mode->hdisplay);
+				h = min(TEST_MAX_HEIGHT, mode->vdisplay);
+			}
 
-		min_w = 256;
-		min_h = 256;
+			min_w = 256;
+			min_h = 256;
+		}
 	} else {
 		pixel_format = data->override_fmt ?: DRM_FORMAT_ARGB8888;
 
@@ -261,7 +280,8 @@ static void prepare_fbs(data_t *data, igt_output_t *output,
 	 * frame can fit in
 	 */
 	if (data->rotation & (IGT_ROTATION_90 | IGT_ROTATION_270)) {
-		tiling = data->override_tiling ?: LOCAL_I915_FORMAT_MOD_Y_TILED;
+		if (intel_gpu)
+			tiling = data->override_tiling ?: LOCAL_I915_FORMAT_MOD_Y_TILED;
 
 		igt_swap(w, h);
 	}
@@ -272,45 +292,62 @@ static void prepare_fbs(data_t *data, igt_output_t *output,
 	 */
 	igt_require(igt_display_has_format_mod(display, pixel_format, tiling));
 
-	if (!data->crc_rect[rect].valid) {
-		/*
-		* Create a reference software rotated flip framebuffer.
-		*/
-		igt_create_fb(data->gfx_fd, ref_w, ref_h, pixel_format, tiling,
-			&data->fb_flip);
-		paint_squares(data, data->rotation, &data->fb_flip,
-			flip_opacity);
-		igt_plane_set_fb(plane, &data->fb_flip);
-		if (plane->type != DRM_PLANE_TYPE_CURSOR)
-			igt_plane_set_position(plane, data->pos_x, data->pos_y);
-		igt_display_commit2(display, COMMIT_ATOMIC);
-
-		igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &data->crc_rect[rect].flip_crc);
-		igt_remove_fb(data->gfx_fd, &data->fb_flip);
+	if (intel_gpu) {
+		if (!data->crc_rect[rect].valid) {
+			/*
+			* Create a reference software rotated flip framebuffer.
+			*/
+			igt_create_fb(data->gfx_fd, ref_w, ref_h, pixel_format, tiling,
+				&data->fb_flip);
+			paint_squares(data, data->rotation, &data->fb_flip,
+				flip_opacity);
+			igt_plane_set_fb(plane, &data->fb_flip);
+			if (plane->type != DRM_PLANE_TYPE_CURSOR)
+				igt_plane_set_position(plane, data->pos_x, data->pos_y);
+			igt_display_commit2(display, COMMIT_ATOMIC);
+
+			igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &data->crc_rect[rect].flip_crc);
+			igt_remove_fb(data->gfx_fd, &data->fb_flip);
+
+			/*
+			* Create a reference CRC for a software-rotated fb.
+			*/
+			igt_create_fb(data->gfx_fd, ref_w, ref_h, pixel_format,
+				data->override_tiling ?: LOCAL_DRM_FORMAT_MOD_NONE, &data->fb_reference);
+			paint_squares(data, data->rotation, &data->fb_reference, 1.0);
+
+			igt_plane_set_fb(plane, &data->fb_reference);
+			if (plane->type != DRM_PLANE_TYPE_CURSOR)
+				igt_plane_set_position(plane, data->pos_x, data->pos_y);
+			igt_display_commit2(display, COMMIT_ATOMIC);
+
+			igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &data->crc_rect[rect].ref_crc);
+			data->crc_rect[rect].valid = true;
+		}
 
 		/*
-		* Create a reference CRC for a software-rotated fb.
-		*/
+		  * Prepare the non-rotated flip fb.
+		  */
+		igt_create_fb(data->gfx_fd, w, h, pixel_format, tiling,
+			      &data->fb_flip);
+		paint_squares(data, IGT_ROTATION_0, &data->fb_flip,
+			      flip_opacity);
+	} else if (amd_gpu) {
+		tiling = 0x900;
 		igt_create_fb(data->gfx_fd, ref_w, ref_h, pixel_format,
-			data->override_tiling ?: LOCAL_DRM_FORMAT_MOD_NONE, &data->fb_reference);
+				  LOCAL_DRM_FORMAT_MOD_NONE, &data->fb_reference);
 		paint_squares(data, data->rotation, &data->fb_reference, 1.0);
 
 		igt_plane_set_fb(plane, &data->fb_reference);
 		if (plane->type != DRM_PLANE_TYPE_CURSOR)
 			igt_plane_set_position(plane, data->pos_x, data->pos_y);
-		igt_display_commit2(display, COMMIT_ATOMIC);
 
-		igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &data->crc_rect[rect].ref_crc);
-		data->crc_rect[rect].valid = true;
-	}
+		if (data->rotation & (IGT_ROTATION_90 | IGT_ROTATION_270))
+			igt_plane_set_size(plane, ref_w, ref_h);
 
-	/*
-	  * Prepare the non-rotated flip fb.
-	  */
-	igt_create_fb(data->gfx_fd, w, h, pixel_format, tiling,
-		      &data->fb_flip);
-	paint_squares(data, IGT_ROTATION_0, &data->fb_flip,
-		      flip_opacity);
+		igt_display_commit2(display, COMMIT_ATOMIC);
+		igt_pipe_crc_collect_crc(data->pipe_crc, &data->ref_crc);
+	}
 
 	/*
 	 * Prepare the plane with an non-rotated fb let the hw rotate it.
@@ -349,32 +386,37 @@ static void test_single_case(data_t *data, enum pipe pipe,
 	/* Verify commit was ok. */
 	igt_assert_eq(ret, 0);
 
-	/* Check CRC */
-	igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &crc_output);
-	igt_assert_crc_equal(&data->crc_rect[rect].ref_crc, &crc_output);
+	if (is_i915_device(data->gfx_fd)) {
+		/* Check CRC */
+		igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &crc_output);
+		igt_assert_crc_equal(&data->crc_rect[rect].ref_crc, &crc_output);
 
-	/*
-	 * If flips are requested flip to a different fb and
-	 * check CRC against that one as well.
-	 */
-	if (data->fb_flip.fb_id) {
-		igt_plane_set_fb(plane, &data->fb_flip);
-		if (data->rotation == IGT_ROTATION_90 || data->rotation == IGT_ROTATION_270)
-			igt_plane_set_size(plane, data->fb.height, data->fb.width);
-
-		if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
-			igt_display_commit_atomic(display, DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_ATOMIC_NONBLOCK, NULL);
-		} else {
-			ret = drmModePageFlip(data->gfx_fd,
-					output->config.crtc->crtc_id,
-					data->fb_flip.fb_id,
-					DRM_MODE_PAGE_FLIP_EVENT,
-					NULL);
-			igt_assert_eq(ret, 0);
+		/*
+		 * If flips are requested flip to a different fb and
+		 * check CRC against that one as well.
+		 */
+		if (data->fb_flip.fb_id) {
+			igt_plane_set_fb(plane, &data->fb_flip);
+			if (data->rotation == IGT_ROTATION_90 || data->rotation == IGT_ROTATION_270)
+				igt_plane_set_size(plane, data->fb.height, data->fb.width);
+
+			if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
+				igt_display_commit_atomic(display, DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_ATOMIC_NONBLOCK, NULL);
+			} else {
+				ret = drmModePageFlip(data->gfx_fd,
+						output->config.crtc->crtc_id,
+						data->fb_flip.fb_id,
+						DRM_MODE_PAGE_FLIP_EVENT,
+						NULL);
+				igt_assert_eq(ret, 0);
+			}
+			kmstest_wait_for_pageflip(data->gfx_fd);
+			igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &crc_output);
+			igt_assert_crc_equal(&data->crc_rect[rect].flip_crc, &crc_output);
 		}
-		kmstest_wait_for_pageflip(data->gfx_fd);
-		igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &crc_output);
-		igt_assert_crc_equal(&data->crc_rect[rect].flip_crc, &crc_output);
+	} else if (is_amdgpu_device(data->gfx_fd)) {
+		igt_pipe_crc_collect_crc(data->pipe_crc, &crc_output);
+		igt_assert_crc_equal(&data->ref_crc, &crc_output);
 	}
 }
 
@@ -415,57 +457,77 @@ static void test_plane_rotation(data_t *data, int plane_type, bool test_bad_form
 		igt_plane_t *plane;
 		int i, j, c;
 
-		for (c = 0; c < num_rectangle_types; c++)
-			data->crc_rect[c].valid = false;
-
-		if (IS_CHERRYVIEW(data->devid) && pipe != PIPE_B)
-			continue;
+		if (is_i915_device(data->gfx_fd)) {
+			for (c = 0; c < num_rectangle_types; c++)
+				data->crc_rect[c].valid = false;
 
-		igt_output_set_pipe(output, pipe);
+			if (IS_CHERRYVIEW(data->devid) && pipe != PIPE_B)
+				continue;
 
-		plane = igt_output_get_plane_type(output, plane_type);
-		igt_require(igt_plane_has_prop(plane, IGT_PLANE_ROTATION));
+			igt_output_set_pipe(output, pipe);
 
-		prepare_crtc(data, output, pipe, plane, true);
+			plane = igt_output_get_plane_type(output, plane_type);
+			igt_require(igt_plane_has_prop(plane, IGT_PLANE_ROTATION));
 
-		for (i = 0; i < num_rectangle_types; i++) {
-			/* Unsupported on i915 */
-			if (plane_type == DRM_PLANE_TYPE_CURSOR &&
-			    i != square)
-				continue;
+			prepare_crtc(data, output, pipe, plane, true);
 
-			/* Only support partial covering primary plane on gen9+ */
-			if (plane_type == DRM_PLANE_TYPE_PRIMARY &&
-			    intel_gen(intel_get_drm_devid(data->gfx_fd)) < 9) {
-				if (i != rectangle)
+			for (i = 0; i < num_rectangle_types; i++) {
+				/* Unsupported on i915 */
+				if (plane_type == DRM_PLANE_TYPE_CURSOR &&
+				    i != square)
 					continue;
-				else
-					data->use_native_resolution = true;
-			} else {
-				data->use_native_resolution = false;
-			}
 
-			if (!data->override_fmt) {
-				struct igt_vec tested_formats;
+				/* Only support partial covering primary plane on gen9+ */
+				if (plane_type == DRM_PLANE_TYPE_PRIMARY &&
+				    intel_gen(intel_get_drm_devid(data->gfx_fd)) < 9) {
+					if (i != rectangle)
+						continue;
+					else
+						data->use_native_resolution = true;
+				} else {
+					data->use_native_resolution = false;
+				}
 
-				igt_vec_init(&tested_formats, sizeof(uint32_t));
+				if (!data->override_fmt) {
+					struct igt_vec tested_formats;
 
-				for (j = 0; j < plane->drm_plane->count_formats; j++) {
-					uint32_t format = plane->drm_plane->formats[j];
+					igt_vec_init(&tested_formats, sizeof(uint32_t));
 
-					if (!test_format(data, &tested_formats, format))
-						continue;
+					for (j = 0; j < plane->drm_plane->count_formats; j++) {
+						uint32_t format = plane->drm_plane->formats[j];
 
+						if (!test_format(data, &tested_formats, format))
+							continue;
+
+						test_single_case(data, pipe, output, plane, i,
+								 format, test_bad_format);
+					}
+
+					igt_vec_fini(&tested_formats);
+				} else {
 					test_single_case(data, pipe, output, plane, i,
-							 format, test_bad_format);
+							 data->override_fmt, test_bad_format);
 				}
+			}
+		} else if (is_amdgpu_device(data->gfx_fd)) {
+			uint32_t format = DRM_FORMAT_XRGB8888;
 
-				igt_vec_fini(&tested_formats);
-			} else {
-				test_single_case(data, pipe, output, plane, i,
-						 data->override_fmt, test_bad_format);
+			igt_output_set_pipe(output, pipe);
+
+			plane = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
+			igt_require(igt_plane_has_prop(plane, IGT_PLANE_ROTATION));
+
+			prepare_crtc(data, output, pipe, plane, false);
+
+			if (plane_type != DRM_PLANE_TYPE_PRIMARY) {
+				plane = igt_output_get_plane_type(output, plane_type);
+				igt_require(igt_plane_has_prop(plane, IGT_PLANE_ROTATION));
 			}
+
+			test_single_case(data, pipe, output, plane,
+					 rectangle, format, test_bad_format);
 		}
+
 		igt_pipe_crc_stop(data->pipe_crc);
 	}
 }
@@ -844,9 +906,11 @@ igt_main_args("", long_opts, help_str, opt_handler, &data)
 	int gen = 0;
 
 	igt_fixture {
-		data.gfx_fd = drm_open_driver_master(DRIVER_INTEL);
-		data.devid = intel_get_drm_devid(data.gfx_fd);
-		gen = intel_gen(data.devid);
+		data.gfx_fd = drm_open_driver_master(DRIVER_INTEL | DRIVER_AMDGPU);
+		if (is_i915_device(data.gfx_fd)) {
+			data.devid = intel_get_drm_devid(data.gfx_fd);
+			gen = intel_gen(data.devid);
+		}
 
 		kmstest_set_vt_graphics_mode();
 
@@ -860,9 +924,11 @@ igt_main_args("", long_opts, help_str, opt_handler, &data)
 		igt_subtest_f("%s-rotation-%s",
 			      plane_test_str(subtest->plane),
 			      rot_test_str(subtest->rot)) {
-			igt_require(!(subtest->rot &
-				    (IGT_ROTATION_90 | IGT_ROTATION_270)) ||
-				    gen >= 9);
+			if (is_i915_device(data.gfx_fd)) {
+				igt_require(!(subtest->rot &
+					    (IGT_ROTATION_90 | IGT_ROTATION_270)) ||
+					    gen >= 9);
+			}
 			data.rotation = subtest->rot;
 			test_plane_rotation(&data, subtest->plane, false);
 		}
--
2.25.1

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Re: [igt-dev] [PATCH 2/3] kms_rotation_crc:Add HW rotation test case for amdgpu

[Kazlauskas, Nicholas]

On 2021-01-12 5:53 p.m., Sung Joon Kim wrote:
> Added Hw rotation case specifically for amdgpu. Currently, kms_rotation_crc tests intel gpus. Added conditions to bypass all the requirements needed for intel when testing amdgpu.
> 
> v2: add crc equal assert since tiling/swizzle is implemented
> Signed-off-by: Sung Joon Kim <sungkim@amd.com>

I think you missed the feedback I left from the previous patch series, 
but this patch is a NAK from me until that's addressed or I understand 
the intent of what it was trying to do.

Regards,
Nicholas Kazlauskas

> ---
>   tests/kms_rotation_crc.c | 270 ++++++++++++++++++++++++---------------
>   1 file changed, 168 insertions(+), 102 deletions(-)
> 
> diff --git a/tests/kms_rotation_crc.c b/tests/kms_rotation_crc.c
> index 33a97cca..31c7499c 100644
> --- a/tests/kms_rotation_crc.c
> +++ b/tests/kms_rotation_crc.c
> @@ -197,6 +197,18 @@ static void prepare_crtc(data_t *data, igt_output_t *output, enum pipe pipe,
>   	/* create the pipe_crc object for this pipe */
>   	igt_pipe_crc_free(data->pipe_crc);
>   
> +	if (is_amdgpu_device(data->gfx_fd)) {
> +		igt_fb_t fb_temp;
> +		drmModeModeInfo *mode = igt_output_get_mode(output);
> +
> +		igt_create_fb(data->gfx_fd, mode->hdisplay, mode->vdisplay,
> +				  DRM_FORMAT_XRGB8888, 0, &fb_temp);
> +		igt_plane_set_fb(plane, &fb_temp);
> +		paint_squares(data, IGT_ROTATION_0, &fb_temp, 1.0);
> +
> +		if (plane->type != DRM_PLANE_TYPE_CURSOR)
> +			igt_plane_set_position(plane, data->pos_x, data->pos_y);
> +	}
>   	igt_display_commit2(display, COMMIT_ATOMIC);
>   	data->pipe_crc = igt_pipe_crc_new(data->gfx_fd, pipe, INTEL_PIPE_CRC_SOURCE_AUTO);
>   
> @@ -213,6 +225,8 @@ static void prepare_fbs(data_t *data, igt_output_t *output,
>   	uint64_t tiling = data->override_tiling ?: LOCAL_DRM_FORMAT_MOD_NONE;
>   	uint32_t pixel_format = data->override_fmt ?: DRM_FORMAT_XRGB8888;
>   	const float flip_opacity = 0.75;
> +	bool amd_gpu = is_amdgpu_device(data->gfx_fd);
> +	bool intel_gpu = is_i915_device(data->gfx_fd);
>   
>   	remove_fbs(data);
>   
> @@ -220,16 +234,21 @@ static void prepare_fbs(data_t *data, igt_output_t *output,
>   
>   	mode = igt_output_get_mode(output);
>   	if (plane->type != DRM_PLANE_TYPE_CURSOR) {
> -		if (data->use_native_resolution) {
> +		if (amd_gpu) {
>   			w = mode->hdisplay;
>   			h = mode->vdisplay;
> -		} else {
> -			w = min(TEST_MAX_WIDTH, mode->hdisplay);
> -			h = min(TEST_MAX_HEIGHT, mode->vdisplay);
> -		}
> +		} else if (intel_gpu) {
> +			if (data->use_native_resolution) {
> +				w = mode->hdisplay;
> +				h = mode->vdisplay;
> +			} else {
> +				w = min(TEST_MAX_WIDTH, mode->hdisplay);
> +				h = min(TEST_MAX_HEIGHT, mode->vdisplay);
> +			}
>   
> -		min_w = 256;
> -		min_h = 256;
> +			min_w = 256;
> +			min_h = 256;
> +		}
>   	} else {
>   		pixel_format = data->override_fmt ?: DRM_FORMAT_ARGB8888;
>   
> @@ -261,7 +280,8 @@ static void prepare_fbs(data_t *data, igt_output_t *output,
>   	 * frame can fit in
>   	 */
>   	if (data->rotation & (IGT_ROTATION_90 | IGT_ROTATION_270)) {
> -		tiling = data->override_tiling ?: LOCAL_I915_FORMAT_MOD_Y_TILED;
> +		if (intel_gpu)
> +			tiling = data->override_tiling ?: LOCAL_I915_FORMAT_MOD_Y_TILED;
>   
>   		igt_swap(w, h);
>   	}
> @@ -272,45 +292,62 @@ static void prepare_fbs(data_t *data, igt_output_t *output,
>   	 */
>   	igt_require(igt_display_has_format_mod(display, pixel_format, tiling));
>   
> -	if (!data->crc_rect[rect].valid) {
> -		/*
> -		* Create a reference software rotated flip framebuffer.
> -		*/
> -		igt_create_fb(data->gfx_fd, ref_w, ref_h, pixel_format, tiling,
> -			&data->fb_flip);
> -		paint_squares(data, data->rotation, &data->fb_flip,
> -			flip_opacity);
> -		igt_plane_set_fb(plane, &data->fb_flip);
> -		if (plane->type != DRM_PLANE_TYPE_CURSOR)
> -			igt_plane_set_position(plane, data->pos_x, data->pos_y);
> -		igt_display_commit2(display, COMMIT_ATOMIC);
> -
> -		igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &data->crc_rect[rect].flip_crc);
> -		igt_remove_fb(data->gfx_fd, &data->fb_flip);
> +	if (intel_gpu) {
> +		if (!data->crc_rect[rect].valid) {
> +			/*
> +			* Create a reference software rotated flip framebuffer.
> +			*/
> +			igt_create_fb(data->gfx_fd, ref_w, ref_h, pixel_format, tiling,
> +				&data->fb_flip);
> +			paint_squares(data, data->rotation, &data->fb_flip,
> +				flip_opacity);
> +			igt_plane_set_fb(plane, &data->fb_flip);
> +			if (plane->type != DRM_PLANE_TYPE_CURSOR)
> +				igt_plane_set_position(plane, data->pos_x, data->pos_y);
> +			igt_display_commit2(display, COMMIT_ATOMIC);
> +
> +			igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &data->crc_rect[rect].flip_crc);
> +			igt_remove_fb(data->gfx_fd, &data->fb_flip);
> +
> +			/*
> +			* Create a reference CRC for a software-rotated fb.
> +			*/
> +			igt_create_fb(data->gfx_fd, ref_w, ref_h, pixel_format,
> +				data->override_tiling ?: LOCAL_DRM_FORMAT_MOD_NONE, &data->fb_reference);
> +			paint_squares(data, data->rotation, &data->fb_reference, 1.0);
> +
> +			igt_plane_set_fb(plane, &data->fb_reference);
> +			if (plane->type != DRM_PLANE_TYPE_CURSOR)
> +				igt_plane_set_position(plane, data->pos_x, data->pos_y);
> +			igt_display_commit2(display, COMMIT_ATOMIC);
> +
> +			igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &data->crc_rect[rect].ref_crc);
> +			data->crc_rect[rect].valid = true;
> +		}

This part as well. I don't quite understand why this is i915 specific 
still, could you please clarify what the intent is?

>   
>   		/*
> -		* Create a reference CRC for a software-rotated fb.
> -		*/
> +		  * Prepare the non-rotated flip fb.
> +		  */
> +		igt_create_fb(data->gfx_fd, w, h, pixel_format, tiling,
> +			      &data->fb_flip);
> +		paint_squares(data, IGT_ROTATION_0, &data->fb_flip,
> +			      flip_opacity);
> +	} else if (amd_gpu) {
> +		tiling = 0x900;
>   		igt_create_fb(data->gfx_fd, ref_w, ref_h, pixel_format,
> -			data->override_tiling ?: LOCAL_DRM_FORMAT_MOD_NONE, &data->fb_reference);
> +				  LOCAL_DRM_FORMAT_MOD_NONE, &data->fb_reference);
>   		paint_squares(data, data->rotation, &data->fb_reference, 1.0);
>   
>   		igt_plane_set_fb(plane, &data->fb_reference);
>   		if (plane->type != DRM_PLANE_TYPE_CURSOR)
>   			igt_plane_set_position(plane, data->pos_x, data->pos_y);
> -		igt_display_commit2(display, COMMIT_ATOMIC);
>   
> -		igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &data->crc_rect[rect].ref_crc);
> -		data->crc_rect[rect].valid = true;
> -	}
> +		if (data->rotation & (IGT_ROTATION_90 | IGT_ROTATION_270))
> +			igt_plane_set_size(plane, ref_w, ref_h);
>   
> -	/*
> -	  * Prepare the non-rotated flip fb.
> -	  */
> -	igt_create_fb(data->gfx_fd, w, h, pixel_format, tiling,
> -		      &data->fb_flip);
> -	paint_squares(data, IGT_ROTATION_0, &data->fb_flip,
> -		      flip_opacity);
> +		igt_display_commit2(display, COMMIT_ATOMIC);
> +		igt_pipe_crc_collect_crc(data->pipe_crc, &data->ref_crc);
> +	}
>   
>   	/*
>   	 * Prepare the plane with an non-rotated fb let the hw rotate it.
> @@ -349,32 +386,37 @@ static void test_single_case(data_t *data, enum pipe pipe,
>   	/* Verify commit was ok. */
>   	igt_assert_eq(ret, 0);
>   
> -	/* Check CRC */
> -	igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &crc_output);
> -	igt_assert_crc_equal(&data->crc_rect[rect].ref_crc, &crc_output);
> +	if (is_i915_device(data->gfx_fd)) {
> +		/* Check CRC */
> +		igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &crc_output);
> +		igt_assert_crc_equal(&data->crc_rect[rect].ref_crc, &crc_output);
>   
> -	/*
> -	 * If flips are requested flip to a different fb and
> -	 * check CRC against that one as well.
> -	 */
> -	if (data->fb_flip.fb_id) {
> -		igt_plane_set_fb(plane, &data->fb_flip);
> -		if (data->rotation == IGT_ROTATION_90 || data->rotation == IGT_ROTATION_270)
> -			igt_plane_set_size(plane, data->fb.height, data->fb.width);
> -
> -		if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
> -			igt_display_commit_atomic(display, DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_ATOMIC_NONBLOCK, NULL);
> -		} else {
> -			ret = drmModePageFlip(data->gfx_fd,
> -					output->config.crtc->crtc_id,
> -					data->fb_flip.fb_id,
> -					DRM_MODE_PAGE_FLIP_EVENT,
> -					NULL);
> -			igt_assert_eq(ret, 0);
> +		/*
> +		 * If flips are requested flip to a different fb and
> +		 * check CRC against that one as well.
> +		 */
> +		if (data->fb_flip.fb_id) {
> +			igt_plane_set_fb(plane, &data->fb_flip);
> +			if (data->rotation == IGT_ROTATION_90 || data->rotation == IGT_ROTATION_270)
> +				igt_plane_set_size(plane, data->fb.height, data->fb.width);
> +
> +			if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
> +				igt_display_commit_atomic(display, DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_ATOMIC_NONBLOCK, NULL);
> +			} else {
> +				ret = drmModePageFlip(data->gfx_fd,
> +						output->config.crtc->crtc_id,
> +						data->fb_flip.fb_id,
> +						DRM_MODE_PAGE_FLIP_EVENT,
> +						NULL);
> +				igt_assert_eq(ret, 0);
> +			}
> +			kmstest_wait_for_pageflip(data->gfx_fd);
> +			igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &crc_output);
> +			igt_assert_crc_equal(&data->crc_rect[rect].flip_crc, &crc_output);
>   		}
> -		kmstest_wait_for_pageflip(data->gfx_fd);
> -		igt_pipe_crc_get_current(display->drm_fd, data->pipe_crc, &crc_output);
> -		igt_assert_crc_equal(&data->crc_rect[rect].flip_crc, &crc_output);
> +	} else if (is_amdgpu_device(data->gfx_fd)) {
> +		igt_pipe_crc_collect_crc(data->pipe_crc, &crc_output);
> +		igt_assert_crc_equal(&data->ref_crc, &crc_output);
>   	}
>   }
>   
> @@ -415,57 +457,77 @@ static void test_plane_rotation(data_t *data, int plane_type, bool test_bad_form
>   		igt_plane_t *plane;
>   		int i, j, c;
>   
> -		for (c = 0; c < num_rectangle_types; c++)
> -			data->crc_rect[c].valid = false;
> -
> -		if (IS_CHERRYVIEW(data->devid) && pipe != PIPE_B)
> -			continue;
> +		if (is_i915_device(data->gfx_fd)) {
> +			for (c = 0; c < num_rectangle_types; c++)
> +				data->crc_rect[c].valid = false;
>   
> -		igt_output_set_pipe(output, pipe);
> +			if (IS_CHERRYVIEW(data->devid) && pipe != PIPE_B)
> +				continue;
>   
> -		plane = igt_output_get_plane_type(output, plane_type);
> -		igt_require(igt_plane_has_prop(plane, IGT_PLANE_ROTATION));
> +			igt_output_set_pipe(output, pipe);
>   
> -		prepare_crtc(data, output, pipe, plane, true);
> +			plane = igt_output_get_plane_type(output, plane_type);
> +			igt_require(igt_plane_has_prop(plane, IGT_PLANE_ROTATION));
>   
> -		for (i = 0; i < num_rectangle_types; i++) {
> -			/* Unsupported on i915 */
> -			if (plane_type == DRM_PLANE_TYPE_CURSOR &&
> -			    i != square)
> -				continue;
> +			prepare_crtc(data, output, pipe, plane, true);
>   
> -			/* Only support partial covering primary plane on gen9+ */
> -			if (plane_type == DRM_PLANE_TYPE_PRIMARY &&
> -			    intel_gen(intel_get_drm_devid(data->gfx_fd)) < 9) {
> -				if (i != rectangle)
> +			for (i = 0; i < num_rectangle_types; i++) {
> +				/* Unsupported on i915 */
> +				if (plane_type == DRM_PLANE_TYPE_CURSOR &&
> +				    i != square)
>   					continue;
> -				else
> -					data->use_native_resolution = true;
> -			} else {
> -				data->use_native_resolution = false;
> -			}
>   
> -			if (!data->override_fmt) {
> -				struct igt_vec tested_formats;
> +				/* Only support partial covering primary plane on gen9+ */
> +				if (plane_type == DRM_PLANE_TYPE_PRIMARY &&
> +				    intel_gen(intel_get_drm_devid(data->gfx_fd)) < 9) {
> +					if (i != rectangle)
> +						continue;
> +					else
> +						data->use_native_resolution = true;
> +				} else {
> +					data->use_native_resolution = false;
> +				}
>   
> -				igt_vec_init(&tested_formats, sizeof(uint32_t));
> +				if (!data->override_fmt) {
> +					struct igt_vec tested_formats;
>   
> -				for (j = 0; j < plane->drm_plane->count_formats; j++) {
> -					uint32_t format = plane->drm_plane->formats[j];
> +					igt_vec_init(&tested_formats, sizeof(uint32_t));
>   
> -					if (!test_format(data, &tested_formats, format))
> -						continue;
> +					for (j = 0; j < plane->drm_plane->count_formats; j++) {
> +						uint32_t format = plane->drm_plane->formats[j];
>   
> +						if (!test_format(data, &tested_formats, format))
> +							continue;
> +
> +						test_single_case(data, pipe, output, plane, i,
> +								 format, test_bad_format);
> +					}
> +
> +					igt_vec_fini(&tested_formats);
> +				} else {
>   					test_single_case(data, pipe, output, plane, i,
> -							 format, test_bad_format);
> +							 data->override_fmt, test_bad_format);
>   				}
> +			}
> +		} else if (is_amdgpu_device(data->gfx_fd)) {
> +			uint32_t format = DRM_FORMAT_XRGB8888;
>   
> -				igt_vec_fini(&tested_formats);
> -			} else {
> -				test_single_case(data, pipe, output, plane, i,
> -						 data->override_fmt, test_bad_format);
> +			igt_output_set_pipe(output, pipe);
> +
> +			plane = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
> +			igt_require(igt_plane_has_prop(plane, IGT_PLANE_ROTATION));
> +
> +			prepare_crtc(data, output, pipe, plane, false);
> +
> +			if (plane_type != DRM_PLANE_TYPE_PRIMARY) {
> +				plane = igt_output_get_plane_type(output, plane_type);
> +				igt_require(igt_plane_has_prop(plane, IGT_PLANE_ROTATION));
>   			}
> +
> +			test_single_case(data, pipe, output, plane,
> +					 rectangle, format, test_bad_format);
>   		}
> +
>   		igt_pipe_crc_stop(data->pipe_crc);
>   	}
>   }
> @@ -844,9 +906,11 @@ igt_main_args("", long_opts, help_str, opt_handler, &data)
>   	int gen = 0;
>   
>   	igt_fixture {
> -		data.gfx_fd = drm_open_driver_master(DRIVER_INTEL);
> -		data.devid = intel_get_drm_devid(data.gfx_fd);
> -		gen = intel_gen(data.devid);
> +		data.gfx_fd = drm_open_driver_master(DRIVER_INTEL | DRIVER_AMDGPU);
> +		if (is_i915_device(data.gfx_fd)) {
> +			data.devid = intel_get_drm_devid(data.gfx_fd);
> +			gen = intel_gen(data.devid);
> +		}
>   
>   		kmstest_set_vt_graphics_mode();
>   
> @@ -860,9 +924,11 @@ igt_main_args("", long_opts, help_str, opt_handler, &data)
>   		igt_subtest_f("%s-rotation-%s",
>   			      plane_test_str(subtest->plane),
>   			      rot_test_str(subtest->rot)) {
> -			igt_require(!(subtest->rot &
> -				    (IGT_ROTATION_90 | IGT_ROTATION_270)) ||
> -				    gen >= 9);
> +			if (is_i915_device(data.gfx_fd)) {
> +				igt_require(!(subtest->rot &
> +					    (IGT_ROTATION_90 | IGT_ROTATION_270)) ||
> +					    gen >= 9);
> +			}
>   			data.rotation = subtest->rot;
>   			test_plane_rotation(&data, subtest->plane, false);
>   		}
> 

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[igt-dev] [PATCH 3/3] lib: Implement tiling/swizzle addressing for amdgpu

[Sung Joon Kim]

The swizzle mode is 64kb withe standard pattern.

Signed-off-by: Sung Joon Kim <sungkim@amd.com>
---
 lib/igt_amd.c | 132 ++++++++++++++++++++++++++++++++++++++++++++++++++
 lib/igt_amd.h |  31 ++++++++++++
 2 files changed, 163 insertions(+)

diff --git a/lib/igt_amd.c b/lib/igt_amd.c
index abd3ad96..737e5670 100644
--- a/lib/igt_amd.c
+++ b/lib/igt_amd.c
@@ -54,3 +54,135 @@ void *igt_amd_mmap_bo(int fd, uint32_t handle, uint64_t size, int prot)
 	ptr = mmap(0, size, prot, MAP_SHARED, fd, map.out.addr_ptr);
 	return ptr == MAP_FAILED ? NULL : ptr;
 }
+
+unsigned int igt_amd_compute_offset(unsigned int* swizzle_pattern, unsigned int x, unsigned int y)
+{
+    unsigned int offset = 0, index = 0, blk_size_table_index = 0, interleave = 0;
+    unsigned int channel[16] = {0, 0, 1, 1, 2, 2, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1};
+    unsigned int i, v;
+
+    for (i = 0; i < 16; i++)
+    {
+        v = 0;
+        if (channel[i] == 1)
+        {
+            blk_size_table_index = 0;
+            interleave = swizzle_pattern[i];
+
+            while (interleave > 1) {
+				blk_size_table_index++;
+				interleave = (interleave + 1) >> 1;
+			}
+
+            index = blk_size_table_index + 2;
+            v ^= (x >> index) & 1;
+        }
+        else if (channel[i] == 2)
+        {
+            blk_size_table_index = 0;
+            interleave = swizzle_pattern[i];
+
+            while (interleave > 1) {
+				blk_size_table_index++;
+				interleave = (interleave + 1) >> 1;
+			}
+
+            index = blk_size_table_index;
+            v ^= (y >> index) & 1;
+        }
+
+        offset |= (v << i);
+    }
+
+	return offset;
+}
+
+uint32_t igt_amd_fb_tiled_offset(unsigned int bpp, unsigned int x_input, unsigned int y_input,
+				       unsigned int width_input)
+{
+	unsigned int blk_size_table_index, blk_size_log2, blk_size_log2_256B;
+	unsigned int element_bytes, width_amp, height_amp, width, height, pitch;
+	unsigned int pb, yb, xb, blk_idx, blk_offset, addr;
+	unsigned int* swizzle_pattern;
+	unsigned int block256_2d[][2] = {{16, 16}, {16, 8}, {8, 8}, {8, 4}, {4, 4}};
+	unsigned int sw_64k_s[][16]=
+	{
+	    {X0, X1, X2, X3, Y0, Y1, Y2, Y3, Y4, X4, Y5, X5, Y6, X6, Y7, X7},
+	    {0,  X0, X1, X2, Y0, Y1, Y2, X3, Y3, X4, Y4, X5, Y5, X6, Y6, X7},
+	    {0,  0,  X0, X1, Y0, Y1, Y2, X2, Y3, X3, Y4, X4, Y5, X5, Y6, X6},
+	    {0,  0,  0,  X0, Y0, Y1, X1, X2, Y2, X3, Y3, X4, Y4, X5, Y5, X6},
+	    {0,  0,  0,  0,  Y0, Y1, X0, X1, Y2, X2, Y3, X3, Y4, X4, Y5, X5},
+	};
+
+	element_bytes = bpp >> 3;
+	blk_size_table_index = 0;
+
+	while (element_bytes > 1) {
+		blk_size_table_index++;
+		element_bytes = (element_bytes + 1) >> 1;
+	}
+
+	blk_size_log2 = 16;
+	blk_size_log2_256B = blk_size_log2 - 8;
+
+	width_amp = blk_size_log2_256B / 2;
+	height_amp = blk_size_log2_256B - width_amp;
+
+	width  = (block256_2d[blk_size_table_index][0] << width_amp);
+	height = (block256_2d[blk_size_table_index][1] << height_amp);
+
+	pitch = (width_input + (width - 1)) & (~(width - 1));
+
+	swizzle_pattern = sw_64k_s[blk_size_table_index];
+
+	pb = pitch / width;
+	yb = y_input / height;
+	xb = x_input / width;
+	blk_idx = yb * pb + xb;
+	blk_offset = igt_amd_compute_offset(swizzle_pattern,
+					x_input << blk_size_table_index, y_input);
+	addr = (blk_idx << blk_size_log2) + blk_offset;
+
+    return (uint32_t)addr;
+}
+
+void igt_amd_fb_to_tiled(struct igt_fb *dst, void *dst_buf, struct igt_fb *src,
+				       void *src_buf, unsigned int plane)
+{
+	uint32_t src_offset, dst_offset;
+	unsigned int bpp = src->plane_bpp[plane];
+	unsigned int width = dst->plane_width[plane];
+	unsigned int height = dst->plane_height[plane];
+	unsigned int x, y;
+
+	for (y = 0; y < height; y++) {
+		for (x = 0; x < width; x++) {
+			src_offset = src->offsets[plane];
+			dst_offset = dst->offsets[plane];
+
+			src_offset += src->strides[plane] * y + x * bpp / 8;
+			dst_offset += igt_amd_fb_tiled_offset(bpp, x, y, width);
+
+			switch (bpp) {
+			case 16:
+				*(uint16_t *)(dst_buf + dst_offset) =
+					*(uint16_t *)(src_buf + src_offset);
+				break;
+			case 32:
+				*(uint32_t *)(dst_buf + dst_offset) =
+					*(uint32_t *)(src_buf + src_offset);
+				break;
+			}
+		}
+	}
+}
+
+void igt_amd_fb_convert_plane_to_tiled(struct igt_fb *dst, void *dst_buf,
+				       struct igt_fb *src, void *src_buf)
+{
+	unsigned int plane;
+
+	for (plane = 0; plane < src->num_planes; plane++) {
+		igt_amd_fb_to_tiled(dst, dst_buf, src, src_buf, plane);
+	}
+}
diff --git a/lib/igt_amd.h b/lib/igt_amd.h
index f63d26f4..d5b421b4 100644
--- a/lib/igt_amd.h
+++ b/lib/igt_amd.h
@@ -24,8 +24,39 @@
 #define IGT_AMD_H
 
 #include <stdint.h>
+#include "igt_fb.h"
 
 uint32_t igt_amd_create_bo(int fd, uint64_t size);
 void *igt_amd_mmap_bo(int fd, uint32_t handle, uint64_t size, int prot);
+unsigned int igt_amd_compute_offset(unsigned int* SwizzlePattern, unsigned int x, unsigned int y);
+uint32_t igt_amd_fb_tiled_offset(unsigned int bpp, unsigned int x_input, unsigned int y_input,
+				       unsigned int width_input);
+void igt_amd_fb_to_tiled(struct igt_fb *dst, void *dst_buf, struct igt_fb *src,
+				       void *src_buf, unsigned int plane);
+void igt_amd_fb_convert_plane_to_tiled(struct igt_fb *dst, void *dst_buf,
+				       struct igt_fb *src, void *src_buf);
+
+#define X0 1
+#define X1 2
+#define X2 4
+#define X3 8
+#define X4 16
+#define X5 32
+#define X6 64
+#define X7 128
+#define Y0 1
+#define Y1 2
+#define Y2 4
+#define Y3 8
+#define Y4 16
+#define Y5 32
+#define Y6 64
+#define Y7 128
+
+struct Dim2d
+{
+    int w;
+    int h;
+};
 
 #endif /* IGT_AMD_H */
-- 
2.25.1

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Re: [igt-dev] [PATCH 3/3] lib: Implement tiling/swizzle addressing for amdgpu

[Cornij, Nikola]

[AMD Public Use]

Reviewed by: Nikola Cornij < nikola.cornij@amd.com>

-----Original Message-----
From: Kim, Sung joon <Sungjoon.Kim@amd.com> 
Sent: Tuesday, January 12, 2021 5:54 PM
To: igt-dev@lists.freedesktop.org
Cc: Kazlauskas, Nicholas <Nicholas.Kazlauskas@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>; Cornij, Nikola <Nikola.Cornij@amd.com>; Kim, Sung joon <Sungjoon.Kim@amd.com>
Subject: [PATCH 3/3] lib: Implement tiling/swizzle addressing for amdgpu

The swizzle mode is 64kb withe standard pattern.

Signed-off-by: Sung Joon Kim <sungkim@amd.com>
---
 lib/igt_amd.c | 132 ++++++++++++++++++++++++++++++++++++++++++++++++++
 lib/igt_amd.h |  31 ++++++++++++
 2 files changed, 163 insertions(+)

diff --git a/lib/igt_amd.c b/lib/igt_amd.c index abd3ad96..737e5670 100644
--- a/lib/igt_amd.c
+++ b/lib/igt_amd.c
@@ -54,3 +54,135 @@ void *igt_amd_mmap_bo(int fd, uint32_t handle, uint64_t size, int prot)
 	ptr = mmap(0, size, prot, MAP_SHARED, fd, map.out.addr_ptr);
 	return ptr == MAP_FAILED ? NULL : ptr;  }
+
+unsigned int igt_amd_compute_offset(unsigned int* swizzle_pattern, 
+unsigned int x, unsigned int y) {
+    unsigned int offset = 0, index = 0, blk_size_table_index = 0, interleave = 0;
+    unsigned int channel[16] = {0, 0, 1, 1, 2, 2, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1};
+    unsigned int i, v;
+
+    for (i = 0; i < 16; i++)
+    {
+        v = 0;
+        if (channel[i] == 1)
+        {
+            blk_size_table_index = 0;
+            interleave = swizzle_pattern[i];
+
+            while (interleave > 1) {
+				blk_size_table_index++;
+				interleave = (interleave + 1) >> 1;
+			}
+
+            index = blk_size_table_index + 2;
+            v ^= (x >> index) & 1;
+        }
+        else if (channel[i] == 2)
+        {
+            blk_size_table_index = 0;
+            interleave = swizzle_pattern[i];
+
+            while (interleave > 1) {
+				blk_size_table_index++;
+				interleave = (interleave + 1) >> 1;
+			}
+
+            index = blk_size_table_index;
+            v ^= (y >> index) & 1;
+        }
+
+        offset |= (v << i);
+    }
+
+	return offset;
+}
+
+uint32_t igt_amd_fb_tiled_offset(unsigned int bpp, unsigned int x_input, unsigned int y_input,
+				       unsigned int width_input)
+{
+	unsigned int blk_size_table_index, blk_size_log2, blk_size_log2_256B;
+	unsigned int element_bytes, width_amp, height_amp, width, height, pitch;
+	unsigned int pb, yb, xb, blk_idx, blk_offset, addr;
+	unsigned int* swizzle_pattern;
+	unsigned int block256_2d[][2] = {{16, 16}, {16, 8}, {8, 8}, {8, 4}, {4, 4}};
+	unsigned int sw_64k_s[][16]=
+	{
+	    {X0, X1, X2, X3, Y0, Y1, Y2, Y3, Y4, X4, Y5, X5, Y6, X6, Y7, X7},
+	    {0,  X0, X1, X2, Y0, Y1, Y2, X3, Y3, X4, Y4, X5, Y5, X6, Y6, X7},
+	    {0,  0,  X0, X1, Y0, Y1, Y2, X2, Y3, X3, Y4, X4, Y5, X5, Y6, X6},
+	    {0,  0,  0,  X0, Y0, Y1, X1, X2, Y2, X3, Y3, X4, Y4, X5, Y5, X6},
+	    {0,  0,  0,  0,  Y0, Y1, X0, X1, Y2, X2, Y3, X3, Y4, X4, Y5, X5},
+	};
+
+	element_bytes = bpp >> 3;
+	blk_size_table_index = 0;
+
+	while (element_bytes > 1) {
+		blk_size_table_index++;
+		element_bytes = (element_bytes + 1) >> 1;
+	}
+
+	blk_size_log2 = 16;
+	blk_size_log2_256B = blk_size_log2 - 8;
+
+	width_amp = blk_size_log2_256B / 2;
+	height_amp = blk_size_log2_256B - width_amp;
+
+	width  = (block256_2d[blk_size_table_index][0] << width_amp);
+	height = (block256_2d[blk_size_table_index][1] << height_amp);
+
+	pitch = (width_input + (width - 1)) & (~(width - 1));
+
+	swizzle_pattern = sw_64k_s[blk_size_table_index];
+
+	pb = pitch / width;
+	yb = y_input / height;
+	xb = x_input / width;
+	blk_idx = yb * pb + xb;
+	blk_offset = igt_amd_compute_offset(swizzle_pattern,
+					x_input << blk_size_table_index, y_input);
+	addr = (blk_idx << blk_size_log2) + blk_offset;
+
+    return (uint32_t)addr;
+}
+
+void igt_amd_fb_to_tiled(struct igt_fb *dst, void *dst_buf, struct igt_fb *src,
+				       void *src_buf, unsigned int plane) {
+	uint32_t src_offset, dst_offset;
+	unsigned int bpp = src->plane_bpp[plane];
+	unsigned int width = dst->plane_width[plane];
+	unsigned int height = dst->plane_height[plane];
+	unsigned int x, y;
+
+	for (y = 0; y < height; y++) {
+		for (x = 0; x < width; x++) {
+			src_offset = src->offsets[plane];
+			dst_offset = dst->offsets[plane];
+
+			src_offset += src->strides[plane] * y + x * bpp / 8;
+			dst_offset += igt_amd_fb_tiled_offset(bpp, x, y, width);
+
+			switch (bpp) {
+			case 16:
+				*(uint16_t *)(dst_buf + dst_offset) =
+					*(uint16_t *)(src_buf + src_offset);
+				break;
+			case 32:
+				*(uint32_t *)(dst_buf + dst_offset) =
+					*(uint32_t *)(src_buf + src_offset);
+				break;
+			}
+		}
+	}
+}
+
+void igt_amd_fb_convert_plane_to_tiled(struct igt_fb *dst, void *dst_buf,
+				       struct igt_fb *src, void *src_buf) {
+	unsigned int plane;
+
+	for (plane = 0; plane < src->num_planes; plane++) {
+		igt_amd_fb_to_tiled(dst, dst_buf, src, src_buf, plane);
+	}
+}
diff --git a/lib/igt_amd.h b/lib/igt_amd.h index f63d26f4..d5b421b4 100644
--- a/lib/igt_amd.h
+++ b/lib/igt_amd.h
@@ -24,8 +24,39 @@
 #define IGT_AMD_H
 
 #include <stdint.h>
+#include "igt_fb.h"
 
 uint32_t igt_amd_create_bo(int fd, uint64_t size);  void *igt_amd_mmap_bo(int fd, uint32_t handle, uint64_t size, int prot);
+unsigned int igt_amd_compute_offset(unsigned int* SwizzlePattern, 
+unsigned int x, unsigned int y); uint32_t igt_amd_fb_tiled_offset(unsigned int bpp, unsigned int x_input, unsigned int y_input,
+				       unsigned int width_input);
+void igt_amd_fb_to_tiled(struct igt_fb *dst, void *dst_buf, struct igt_fb *src,
+				       void *src_buf, unsigned int plane); void 
+igt_amd_fb_convert_plane_to_tiled(struct igt_fb *dst, void *dst_buf,
+				       struct igt_fb *src, void *src_buf);
+
+#define X0 1
+#define X1 2
+#define X2 4
+#define X3 8
+#define X4 16
+#define X5 32
+#define X6 64
+#define X7 128
+#define Y0 1
+#define Y1 2
+#define Y2 4
+#define Y3 8
+#define Y4 16
+#define Y5 32
+#define Y6 64
+#define Y7 128
+
+struct Dim2d
+{
+    int w;
+    int h;
+};
 
 #endif /* IGT_AMD_H */
--
2.25.1
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Re: [igt-dev] [PATCH 3/3] lib: Implement tiling/swizzle addressing for amdgpu

[Cornij, Nikola]

-----Original Message-----
From: Kim, Sung joon <Sungjoon.Kim@amd.com> 
Sent: Tuesday, January 12, 2021 5:54 PM
To: igt-dev@lists.freedesktop.org
Cc: Kazlauskas, Nicholas <Nicholas.Kazlauskas@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>; Cornij, Nikola <Nikola.Cornij@amd.com>; Kim, Sung joon <Sungjoon.Kim@amd.com>
Subject: [PATCH 3/3] lib: Implement tiling/swizzle addressing for amdgpu

The swizzle mode is 64kb withe standard pattern.

Signed-off-by: Sung Joon Kim <sungkim@amd.com>
Reviewed by: Nikola Cornij <nikola.cornij@amd.com>
---
 lib/igt_amd.c | 132 ++++++++++++++++++++++++++++++++++++++++++++++++++
 lib/igt_amd.h |  31 ++++++++++++
 2 files changed, 163 insertions(+)

diff --git a/lib/igt_amd.c b/lib/igt_amd.c index abd3ad96..737e5670 100644
--- a/lib/igt_amd.c
+++ b/lib/igt_amd.c
@@ -54,3 +54,135 @@ void *igt_amd_mmap_bo(int fd, uint32_t handle, uint64_t size, int prot)
 	ptr = mmap(0, size, prot, MAP_SHARED, fd, map.out.addr_ptr);
 	return ptr == MAP_FAILED ? NULL : ptr;  }
+
+unsigned int igt_amd_compute_offset(unsigned int* swizzle_pattern, 
+unsigned int x, unsigned int y) {
+    unsigned int offset = 0, index = 0, blk_size_table_index = 0, interleave = 0;
+    unsigned int channel[16] = {0, 0, 1, 1, 2, 2, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1};
+    unsigned int i, v;
+
+    for (i = 0; i < 16; i++)
+    {
+        v = 0;
+        if (channel[i] == 1)
+        {
+            blk_size_table_index = 0;
+            interleave = swizzle_pattern[i];
+
+            while (interleave > 1) {
+				blk_size_table_index++;
+				interleave = (interleave + 1) >> 1;
+			}
+
+            index = blk_size_table_index + 2;
+            v ^= (x >> index) & 1;
+        }
+        else if (channel[i] == 2)
+        {
+            blk_size_table_index = 0;
+            interleave = swizzle_pattern[i];
+
+            while (interleave > 1) {
+				blk_size_table_index++;
+				interleave = (interleave + 1) >> 1;
+			}
+
+            index = blk_size_table_index;
+            v ^= (y >> index) & 1;
+        }
+
+        offset |= (v << i);
+    }
+
+	return offset;
+}
+
+uint32_t igt_amd_fb_tiled_offset(unsigned int bpp, unsigned int x_input, unsigned int y_input,
+				       unsigned int width_input)
+{
+	unsigned int blk_size_table_index, blk_size_log2, blk_size_log2_256B;
+	unsigned int element_bytes, width_amp, height_amp, width, height, pitch;
+	unsigned int pb, yb, xb, blk_idx, blk_offset, addr;
+	unsigned int* swizzle_pattern;
+	unsigned int block256_2d[][2] = {{16, 16}, {16, 8}, {8, 8}, {8, 4}, {4, 4}};
+	unsigned int sw_64k_s[][16]=
+	{
+	    {X0, X1, X2, X3, Y0, Y1, Y2, Y3, Y4, X4, Y5, X5, Y6, X6, Y7, X7},
+	    {0,  X0, X1, X2, Y0, Y1, Y2, X3, Y3, X4, Y4, X5, Y5, X6, Y6, X7},
+	    {0,  0,  X0, X1, Y0, Y1, Y2, X2, Y3, X3, Y4, X4, Y5, X5, Y6, X6},
+	    {0,  0,  0,  X0, Y0, Y1, X1, X2, Y2, X3, Y3, X4, Y4, X5, Y5, X6},
+	    {0,  0,  0,  0,  Y0, Y1, X0, X1, Y2, X2, Y3, X3, Y4, X4, Y5, X5},
+	};
+
+	element_bytes = bpp >> 3;
+	blk_size_table_index = 0;
+
+	while (element_bytes > 1) {
+		blk_size_table_index++;
+		element_bytes = (element_bytes + 1) >> 1;
+	}
+
+	blk_size_log2 = 16;
+	blk_size_log2_256B = blk_size_log2 - 8;
+
+	width_amp = blk_size_log2_256B / 2;
+	height_amp = blk_size_log2_256B - width_amp;
+
+	width  = (block256_2d[blk_size_table_index][0] << width_amp);
+	height = (block256_2d[blk_size_table_index][1] << height_amp);
+
+	pitch = (width_input + (width - 1)) & (~(width - 1));
+
+	swizzle_pattern = sw_64k_s[blk_size_table_index];
+
+	pb = pitch / width;
+	yb = y_input / height;
+	xb = x_input / width;
+	blk_idx = yb * pb + xb;
+	blk_offset = igt_amd_compute_offset(swizzle_pattern,
+					x_input << blk_size_table_index, y_input);
+	addr = (blk_idx << blk_size_log2) + blk_offset;
+
+    return (uint32_t)addr;
+}
+
+void igt_amd_fb_to_tiled(struct igt_fb *dst, void *dst_buf, struct igt_fb *src,
+				       void *src_buf, unsigned int plane) {
+	uint32_t src_offset, dst_offset;
+	unsigned int bpp = src->plane_bpp[plane];
+	unsigned int width = dst->plane_width[plane];
+	unsigned int height = dst->plane_height[plane];
+	unsigned int x, y;
+
+	for (y = 0; y < height; y++) {
+		for (x = 0; x < width; x++) {
+			src_offset = src->offsets[plane];
+			dst_offset = dst->offsets[plane];
+
+			src_offset += src->strides[plane] * y + x * bpp / 8;
+			dst_offset += igt_amd_fb_tiled_offset(bpp, x, y, width);
+
+			switch (bpp) {
+			case 16:
+				*(uint16_t *)(dst_buf + dst_offset) =
+					*(uint16_t *)(src_buf + src_offset);
+				break;
+			case 32:
+				*(uint32_t *)(dst_buf + dst_offset) =
+					*(uint32_t *)(src_buf + src_offset);
+				break;
+			}
+		}
+	}
+}
+
+void igt_amd_fb_convert_plane_to_tiled(struct igt_fb *dst, void *dst_buf,
+				       struct igt_fb *src, void *src_buf) {
+	unsigned int plane;
+
+	for (plane = 0; plane < src->num_planes; plane++) {
+		igt_amd_fb_to_tiled(dst, dst_buf, src, src_buf, plane);
+	}
+}
diff --git a/lib/igt_amd.h b/lib/igt_amd.h index f63d26f4..d5b421b4 100644
--- a/lib/igt_amd.h
+++ b/lib/igt_amd.h
@@ -24,8 +24,39 @@
 #define IGT_AMD_H
 
 #include <stdint.h>
+#include "igt_fb.h"
 
 uint32_t igt_amd_create_bo(int fd, uint64_t size);  void *igt_amd_mmap_bo(int fd, uint32_t handle, uint64_t size, int prot);
+unsigned int igt_amd_compute_offset(unsigned int* SwizzlePattern, 
+unsigned int x, unsigned int y); uint32_t igt_amd_fb_tiled_offset(unsigned int bpp, unsigned int x_input, unsigned int y_input,
+				       unsigned int width_input);
+void igt_amd_fb_to_tiled(struct igt_fb *dst, void *dst_buf, struct igt_fb *src,
+				       void *src_buf, unsigned int plane); void 
+igt_amd_fb_convert_plane_to_tiled(struct igt_fb *dst, void *dst_buf,
+				       struct igt_fb *src, void *src_buf);
+
+#define X0 1
+#define X1 2
+#define X2 4
+#define X3 8
+#define X4 16
+#define X5 32
+#define X6 64
+#define X7 128
+#define Y0 1
+#define Y1 2
+#define Y2 4
+#define Y3 8
+#define Y4 16
+#define Y5 32
+#define Y6 64
+#define Y7 128
+
+struct Dim2d
+{
+    int w;
+    int h;
+};
 
 #endif /* IGT_AMD_H */
--
2.25.1

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Re: [igt-dev] [PATCH 3/3] lib: Implement tiling/swizzle addressing for amdgpu

[Kazlauskas, Nicholas]

On 2021-01-12 5:54 p.m., Sung Joon Kim wrote:
> The swizzle mode is 64kb withe standard pattern.
> 
> Signed-off-by: Sung Joon Kim <sungkim@amd.com>

Mentioned in patch 1, but let's merge this with patch 1.

> ---
>   lib/igt_amd.c | 132 ++++++++++++++++++++++++++++++++++++++++++++++++++
>   lib/igt_amd.h |  31 ++++++++++++
>   2 files changed, 163 insertions(+)
> 
> diff --git a/lib/igt_amd.c b/lib/igt_amd.c
> index abd3ad96..737e5670 100644
> --- a/lib/igt_amd.c
> +++ b/lib/igt_amd.c
> @@ -54,3 +54,135 @@ void *igt_amd_mmap_bo(int fd, uint32_t handle, uint64_t size, int prot)
>   	ptr = mmap(0, size, prot, MAP_SHARED, fd, map.out.addr_ptr);
>   	return ptr == MAP_FAILED ? NULL : ptr;
>   }
> +
> +unsigned int igt_amd_compute_offset(unsigned int* swizzle_pattern, unsigned int x, unsigned int y)
> +{
> +    unsigned int offset = 0, index = 0, blk_size_table_index = 0, interleave = 0;
> +    unsigned int channel[16] = {0, 0, 1, 1, 2, 2, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1};
> +    unsigned int i, v;
> +
> +    for (i = 0; i < 16; i++)
> +    {
> +        v = 0;
> +        if (channel[i] == 1)
> +        {
> +            blk_size_table_index = 0;
> +            interleave = swizzle_pattern[i];
> +
> +            while (interleave > 1) {
> +				blk_size_table_index++;
> +				interleave = (interleave + 1) >> 1;
> +			}
> +
> +            index = blk_size_table_index + 2;
> +            v ^= (x >> index) & 1;
> +        }
> +        else if (channel[i] == 2)
> +        {
> +            blk_size_table_index = 0;
> +            interleave = swizzle_pattern[i];
> +
> +            while (interleave > 1) {
> +				blk_size_table_index++;
> +				interleave = (interleave + 1) >> 1;
> +			}
> +
> +            index = blk_size_table_index;
> +            v ^= (y >> index) & 1;
> +        }
> +
> +        offset |= (v << i);
> +    }
> +
> +	return offset;
> +}
> +
> +uint32_t igt_amd_fb_tiled_offset(unsigned int bpp, unsigned int x_input, unsigned int y_input,
> +				       unsigned int width_input)
> +{
> +	unsigned int blk_size_table_index, blk_size_log2, blk_size_log2_256B;
> +	unsigned int element_bytes, width_amp, height_amp, width, height, pitch;
> +	unsigned int pb, yb, xb, blk_idx, blk_offset, addr;
> +	unsigned int* swizzle_pattern;
> +	unsigned int block256_2d[][2] = {{16, 16}, {16, 8}, {8, 8}, {8, 4}, {4, 4}};
> +	unsigned int sw_64k_s[][16]=
> +	{
> +	    {X0, X1, X2, X3, Y0, Y1, Y2, Y3, Y4, X4, Y5, X5, Y6, X6, Y7, X7},
> +	    {0,  X0, X1, X2, Y0, Y1, Y2, X3, Y3, X4, Y4, X5, Y5, X6, Y6, X7},
> +	    {0,  0,  X0, X1, Y0, Y1, Y2, X2, Y3, X3, Y4, X4, Y5, X5, Y6, X6},
> +	    {0,  0,  0,  X0, Y0, Y1, X1, X2, Y2, X3, Y3, X4, Y4, X5, Y5, X6},
> +	    {0,  0,  0,  0,  Y0, Y1, X0, X1, Y2, X2, Y3, X3, Y4, X4, Y5, X5},
> +	};
> +
> +	element_bytes = bpp >> 3;
> +	blk_size_table_index = 0;
> +
> +	while (element_bytes > 1) {
> +		blk_size_table_index++;
> +		element_bytes = (element_bytes + 1) >> 1;
> +	}
> +
> +	blk_size_log2 = 16;
> +	blk_size_log2_256B = blk_size_log2 - 8;
> +
> +	width_amp = blk_size_log2_256B / 2;
> +	height_amp = blk_size_log2_256B - width_amp;
> +
> +	width  = (block256_2d[blk_size_table_index][0] << width_amp);
> +	height = (block256_2d[blk_size_table_index][1] << height_amp);
> +
> +	pitch = (width_input + (width - 1)) & (~(width - 1));
> +
> +	swizzle_pattern = sw_64k_s[blk_size_table_index];
> +
> +	pb = pitch / width;
> +	yb = y_input / height;
> +	xb = x_input / width;
> +	blk_idx = yb * pb + xb;
> +	blk_offset = igt_amd_compute_offset(swizzle_pattern,
> +					x_input << blk_size_table_index, y_input);
> +	addr = (blk_idx << blk_size_log2) + blk_offset;
> +
> +    return (uint32_t)addr;
> +}
> +
> +void igt_amd_fb_to_tiled(struct igt_fb *dst, void *dst_buf, struct igt_fb *src,
> +				       void *src_buf, unsigned int plane)
> +{
> +	uint32_t src_offset, dst_offset;
> +	unsigned int bpp = src->plane_bpp[plane];
> +	unsigned int width = dst->plane_width[plane];
> +	unsigned int height = dst->plane_height[plane];
> +	unsigned int x, y;
> +
> +	for (y = 0; y < height; y++) {
> +		for (x = 0; x < width; x++) {
> +			src_offset = src->offsets[plane];
> +			dst_offset = dst->offsets[plane];
> +
> +			src_offset += src->strides[plane] * y + x * bpp / 8;
> +			dst_offset += igt_amd_fb_tiled_offset(bpp, x, y, width);
> +
> +			switch (bpp) {
> +			case 16:
> +				*(uint16_t *)(dst_buf + dst_offset) =
> +					*(uint16_t *)(src_buf + src_offset);
> +				break;
> +			case 32:
> +				*(uint32_t *)(dst_buf + dst_offset) =
> +					*(uint32_t *)(src_buf + src_offset);
> +				break;
> +			}
> +		}
> +	}
> +}
> +
> +void igt_amd_fb_convert_plane_to_tiled(struct igt_fb *dst, void *dst_buf,
> +				       struct igt_fb *src, void *src_buf)
> +{
> +	unsigned int plane;
> +
Shouldn't the tiling format be checked here? This is only implementing 
one type of tiling, other types should fail.

> +	for (plane = 0; plane < src->num_planes; plane++) {
> +		igt_amd_fb_to_tiled(dst, dst_buf, src, src_buf, plane);
> +	}
> +}
> diff --git a/lib/igt_amd.h b/lib/igt_amd.h
> index f63d26f4..d5b421b4 100644
> --- a/lib/igt_amd.h
> +++ b/lib/igt_amd.h
> @@ -24,8 +24,39 @@
>   #define IGT_AMD_H
>   
>   #include <stdint.h>
> +#include "igt_fb.h"
>   
>   uint32_t igt_amd_create_bo(int fd, uint64_t size);
>   void *igt_amd_mmap_bo(int fd, uint32_t handle, uint64_t size, int prot);
> +unsigned int igt_amd_compute_offset(unsigned int* SwizzlePattern, unsigned int x, unsigned int y);
> +uint32_t igt_amd_fb_tiled_offset(unsigned int bpp, unsigned int x_input, unsigned int y_input,
> +				       unsigned int width_input);
> +void igt_amd_fb_to_tiled(struct igt_fb *dst, void *dst_buf, struct igt_fb *src,
> +				       void *src_buf, unsigned int plane);
> +void igt_amd_fb_convert_plane_to_tiled(struct igt_fb *dst, void *dst_buf,
> +				       struct igt_fb *src, void *src_buf);

Do we need conversion helpers for tiled -> linear?

Regards,
Nicholas Kazlauskas

> +
> +#define X0 1
> +#define X1 2
> +#define X2 4
> +#define X3 8
> +#define X4 16
> +#define X5 32
> +#define X6 64
> +#define X7 128
> +#define Y0 1
> +#define Y1 2
> +#define Y2 4
> +#define Y3 8
> +#define Y4 16
> +#define Y5 32
> +#define Y6 64
> +#define Y7 128

Can we move these constants into the igt_amd.c file itself so it doesn't 
pollute the namespace?

> +
> +struct Dim2d

nitpick: naming should be lowercase, ie. dim2d.

Can also include this structure in igt_amd.c since we're not using it 
anywhere else.

Regards,
Nicholas Kazlauskas

> +{
> +    int w;
> +    int h;
> +};
>   
>   #endif /* IGT_AMD_H */
> 

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[igt-dev] ✓ Fi.CI.BAT: success for series starting with [1/3] lib: Add stride and size calculation for amdgpu + tiling

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 3081 bytes --]

== Series Details ==

Series: series starting with [1/3] lib: Add stride and size calculation for amdgpu + tiling
URL   : https://patchwork.freedesktop.org/series/85772/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9596 -> IGTPW_5388
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/index.html

Known issues
------------

  Here are the changes found in IGTPW_5388 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - fi-snb-2600:        NOTRUN -> [SKIP][1] ([fdo#109271]) +30 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/fi-snb-2600/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_chamelium@hdmi-crc-fast:
    - fi-snb-2600:        NOTRUN -> [SKIP][2] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/fi-snb-2600/igt@kms_chamelium@hdmi-crc-fast.html

  * igt@prime_vgem@basic-write:
    - fi-tgl-y:           [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/fi-tgl-y/igt@prime_vgem@basic-write.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/fi-tgl-y/igt@prime_vgem@basic-write.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-snb-2600:        [DMESG-WARN][5] ([i915#2772]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/fi-snb-2600/igt@gem_exec_suspend@basic-s3.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/fi-snb-2600/igt@gem_exec_suspend@basic-s3.html

  * igt@prime_self_import@basic-with_one_bo_two_files:
    - fi-tgl-y:           [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2772]: https://gitlab.freedesktop.org/drm/intel/issues/2772
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (44 -> 38)
------------------------------

  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-dg1-1 fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5957 -> IGTPW_5388

  CI-20190529: 20190529
  CI_DRM_9596: 6acb53490b1d09467acf0862c33880a92a3e596e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_5388: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/index.html
  IGT_5957: 2a2b3418f7458dfa1fac255cc5c71603f617690a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/index.html

[-- Attachment #1.2: Type: text/html, Size: 3924 bytes --]

[-- Attachment #2: Type: text/plain, Size: 154 bytes --]

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[igt-dev] ✓ Fi.CI.IGT: success for series starting with [1/3] lib: Add stride and size calculation for amdgpu + tiling

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 30301 bytes --]

== Series Details ==

Series: series starting with [1/3] lib: Add stride and size calculation for amdgpu + tiling
URL   : https://patchwork.freedesktop.org/series/85772/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9596_full -> IGTPW_5388_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/index.html

Known issues
------------

  Here are the changes found in IGTPW_5388_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_persistence@legacy-engines-mixed-process:
    - shard-hsw:          NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) +7 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-hsw4/igt@gem_ctx_persistence@legacy-engines-mixed-process.html

  * igt@gem_exec_params@secure-non-root:
    - shard-iclb:         NOTRUN -> [SKIP][2] ([fdo#112283])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-iclb2/igt@gem_exec_params@secure-non-root.html

  * igt@gem_exec_reloc@basic-wide-active@bcs0:
    - shard-hsw:          NOTRUN -> [FAIL][3] ([i915#2389]) +3 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-hsw4/igt@gem_exec_reloc@basic-wide-active@bcs0.html

  * igt@gem_exec_reloc@basic-wide-active@vcs1:
    - shard-iclb:         NOTRUN -> [FAIL][4] ([i915#2389])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-iclb1/igt@gem_exec_reloc@basic-wide-active@vcs1.html

  * igt@gem_media_vme:
    - shard-tglb:         NOTRUN -> [SKIP][5] ([i915#284])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-tglb7/igt@gem_media_vme.html

  * igt@gem_pread@exhaustion:
    - shard-tglb:         NOTRUN -> [WARN][6] ([i915#2658])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-tglb3/igt@gem_pread@exhaustion.html
    - shard-glk:          NOTRUN -> [WARN][7] ([i915#2658])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-glk7/igt@gem_pread@exhaustion.html
    - shard-apl:          NOTRUN -> [WARN][8] ([i915#2658])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-apl8/igt@gem_pread@exhaustion.html
    - shard-iclb:         NOTRUN -> [WARN][9] ([i915#2658])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-iclb1/igt@gem_pread@exhaustion.html
    - shard-kbl:          NOTRUN -> [WARN][10] ([i915#2658])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-kbl1/igt@gem_pread@exhaustion.html

  * igt@gem_userptr_blits@process-exit-mmap-busy@uc:
    - shard-kbl:          NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#1699]) +3 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-kbl7/igt@gem_userptr_blits@process-exit-mmap-busy@uc.html

  * igt@gem_userptr_blits@readonly-mmap-unsync@wb:
    - shard-tglb:         NOTRUN -> [SKIP][12] ([i915#1704]) +3 similar issues
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-tglb5/igt@gem_userptr_blits@readonly-mmap-unsync@wb.html
    - shard-iclb:         NOTRUN -> [SKIP][13] ([i915#1704]) +3 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-iclb4/igt@gem_userptr_blits@readonly-mmap-unsync@wb.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-glk:          [PASS][14] -> [DMESG-WARN][15] ([i915#1436] / [i915#716])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-glk2/igt@gen9_exec_parse@allowed-all.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-glk6/igt@gen9_exec_parse@allowed-all.html

  * igt@gen9_exec_parse@bb-large:
    - shard-tglb:         NOTRUN -> [SKIP][16] ([i915#2527])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-tglb8/igt@gen9_exec_parse@bb-large.html
    - shard-iclb:         NOTRUN -> [SKIP][17] ([i915#2527])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-iclb8/igt@gen9_exec_parse@bb-large.html

  * igt@gen9_exec_parse@bb-start-far:
    - shard-iclb:         NOTRUN -> [SKIP][18] ([fdo#112306])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-iclb6/igt@gen9_exec_parse@bb-start-far.html
    - shard-tglb:         NOTRUN -> [SKIP][19] ([fdo#112306])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-tglb3/igt@gen9_exec_parse@bb-start-far.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-snb:          [PASS][20] -> [INCOMPLETE][21] ([i915#2880])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-snb7/igt@i915_module_load@reload-with-fault-injection.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-snb4/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-kbl:          NOTRUN -> [SKIP][22] ([fdo#109271]) +36 similar issues
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-kbl2/igt@i915_pm_dc@dc6-psr.html
    - shard-tglb:         NOTRUN -> [FAIL][23] ([i915#454])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-tglb5/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-iclb:         NOTRUN -> [SKIP][24] ([fdo#110892])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-iclb3/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@i915_pm_rpm@pm-tiling:
    - shard-apl:          [PASS][25] -> [SKIP][26] ([fdo#109271])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-apl1/igt@i915_pm_rpm@pm-tiling.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-apl8/igt@i915_pm_rpm@pm-tiling.html
    - shard-tglb:         [PASS][27] -> [SKIP][28] ([i915#579])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-tglb6/igt@i915_pm_rpm@pm-tiling.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-tglb3/igt@i915_pm_rpm@pm-tiling.html
    - shard-iclb:         [PASS][29] -> [SKIP][30] ([i915#579])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-iclb7/igt@i915_pm_rpm@pm-tiling.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-iclb6/igt@i915_pm_rpm@pm-tiling.html

  * igt@i915_selftest@live@gt_heartbeat:
    - shard-glk:          [PASS][31] -> [DMESG-FAIL][32] ([i915#2291])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-glk4/igt@i915_selftest@live@gt_heartbeat.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-glk5/igt@i915_selftest@live@gt_heartbeat.html

  * igt@kms_big_fb@linear-64bpp-rotate-0:
    - shard-glk:          [PASS][33] -> [FAIL][34] ([i915#1119])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-glk7/igt@kms_big_fb@linear-64bpp-rotate-0.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-glk4/igt@kms_big_fb@linear-64bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-90:
    - shard-iclb:         NOTRUN -> [SKIP][35] ([fdo#110723])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-iclb4/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-addfb:
    - shard-tglb:         NOTRUN -> [SKIP][36] ([fdo#111615]) +1 similar issue
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-tglb2/igt@kms_big_fb@yf-tiled-addfb.html

  * igt@kms_ccs@pipe-c-ccs-on-another-bo:
    - shard-glk:          NOTRUN -> [SKIP][37] ([fdo#109271]) +58 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-glk2/igt@kms_ccs@pipe-c-ccs-on-another-bo.html

  * igt@kms_color@pipe-b-degamma:
    - shard-iclb:         NOTRUN -> [FAIL][38] ([i915#1149])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-iclb7/igt@kms_color@pipe-b-degamma.html

  * igt@kms_color@pipe-d-legacy-gamma:
    - shard-apl:          NOTRUN -> [SKIP][39] ([fdo#109271]) +26 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-apl3/igt@kms_color@pipe-d-legacy-gamma.html

  * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
    - shard-hsw:          NOTRUN -> [SKIP][40] ([fdo#109271] / [fdo#111827]) +25 similar issues
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-hsw4/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html

  * igt@kms_color_chamelium@pipe-a-ctm-green-to-red:
    - shard-glk:          NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-glk4/igt@kms_color_chamelium@pipe-a-ctm-green-to-red.html

  * igt@kms_color_chamelium@pipe-c-ctm-max:
    - shard-apl:          NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-apl3/igt@kms_color_chamelium@pipe-c-ctm-max.html
    - shard-kbl:          NOTRUN -> [SKIP][43] ([fdo#109271] / [fdo#111827]) +1 similar issue
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-kbl6/igt@kms_color_chamelium@pipe-c-ctm-max.html
    - shard-iclb:         NOTRUN -> [SKIP][44] ([fdo#109284] / [fdo#111827]) +2 similar issues
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-iclb7/igt@kms_color_chamelium@pipe-c-ctm-max.html
    - shard-tglb:         NOTRUN -> [SKIP][45] ([fdo#109284] / [fdo#111827])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-tglb8/igt@kms_color_chamelium@pipe-c-ctm-max.html

  * igt@kms_concurrent@pipe-c:
    - shard-kbl:          [PASS][46] -> [DMESG-WARN][47] ([i915#180] / [i915#78])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-kbl3/igt@kms_concurrent@pipe-c.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-kbl2/igt@kms_concurrent@pipe-c.html

  * igt@kms_cursor_crc@pipe-c-cursor-512x512-rapid-movement:
    - shard-iclb:         NOTRUN -> [SKIP][48] ([fdo#109278] / [fdo#109279]) +1 similar issue
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-iclb3/igt@kms_cursor_crc@pipe-c-cursor-512x512-rapid-movement.html

  * igt@kms_cursor_crc@pipe-c-cursor-64x21-onscreen:
    - shard-apl:          [PASS][49] -> [FAIL][50] ([i915#54]) +1 similar issue
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-apl8/igt@kms_cursor_crc@pipe-c-cursor-64x21-onscreen.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-apl4/igt@kms_cursor_crc@pipe-c-cursor-64x21-onscreen.html
    - shard-glk:          [PASS][51] -> [FAIL][52] ([i915#54]) +1 similar issue
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-glk8/igt@kms_cursor_crc@pipe-c-cursor-64x21-onscreen.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-glk1/igt@kms_cursor_crc@pipe-c-cursor-64x21-onscreen.html
    - shard-kbl:          [PASS][53] -> [FAIL][54] ([i915#54]) +1 similar issue
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-64x21-onscreen.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-64x21-onscreen.html

  * igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding:
    - shard-tglb:         NOTRUN -> [SKIP][55] ([fdo#109279]) +1 similar issue
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-tglb6/igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding.html

  * igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic:
    - shard-iclb:         NOTRUN -> [SKIP][56] ([fdo#109274] / [fdo#109278]) +2 similar issues
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-iclb3/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
    - shard-tglb:         [PASS][57] -> [FAIL][58] ([i915#2346])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-tglb1/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-tglb5/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-cpu:
    - shard-tglb:         NOTRUN -> [SKIP][59] ([fdo#111825]) +7 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-gtt:
    - shard-iclb:         NOTRUN -> [SKIP][60] ([fdo#109280]) +9 similar issues
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-iclb:         [PASS][61] -> [DMESG-WARN][62] ([i915#1602])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-iclb4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-iclb7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
    - shard-apl:          [PASS][63] -> [DMESG-WARN][64] ([i915#1602] / [i915#2635])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
    - shard-glk:          [PASS][65] -> [DMESG-WARN][66] ([i915#1602] / [i915#2635])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-glk7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-glk4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
    - shard-hsw:          [PASS][67] -> [DMESG-WARN][68] ([i915#2637])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-hsw6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-hsw4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
    - shard-tglb:         [PASS][69] -> [INCOMPLETE][70] ([i915#1436] / [i915#1798] / [i915#1982] / [i915#456])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-tglb2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-tglb8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
    - shard-kbl:          [PASS][71] -> [DMESG-WARN][72] ([i915#1602])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-kbl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
    - shard-glk:          NOTRUN -> [FAIL][73] ([fdo#108145] / [i915#265])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-glk8/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
    - shard-apl:          NOTRUN -> [FAIL][74] ([fdo#108145] / [i915#265])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-apl6/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
    - shard-kbl:          NOTRUN -> [FAIL][75] ([fdo#108145] / [i915#265])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-kbl3/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html

  * igt@kms_plane_alpha_blend@pipe-d-alpha-transparent-fb:
    - shard-iclb:         NOTRUN -> [SKIP][76] ([fdo#109278]) +6 similar issues
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-iclb5/igt@kms_plane_alpha_blend@pipe-d-alpha-transparent-fb.html

  * igt@kms_plane_lowres@pipe-b-tiling-yf:
    - shard-hsw:          NOTRUN -> [SKIP][77] ([fdo#109271]) +332 similar issues
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-hsw6/igt@kms_plane_lowres@pipe-b-tiling-yf.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [PASS][78] -> [SKIP][79] ([fdo#109441]) +1 similar issue
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-iclb1/igt@kms_psr@psr2_cursor_render.html

  * igt@kms_writeback@writeback-fb-id:
    - shard-glk:          NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#2437])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-glk1/igt@kms_writeback@writeback-fb-id.html

  * igt@prime_nv_api@i915_self_import:
    - shard-tglb:         NOTRUN -> [SKIP][81] ([fdo#109291])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-tglb2/igt@prime_nv_api@i915_self_import.html

  * igt@prime_nv_api@nv_i915_reimport_twice_check_flink_name:
    - shard-iclb:         NOTRUN -> [SKIP][82] ([fdo#109291]) +2 similar issues
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-iclb3/igt@prime_nv_api@nv_i915_reimport_twice_check_flink_name.html

  * igt@runner@aborted:
    - shard-snb:          NOTRUN -> [FAIL][83] ([i915#2292] / [i915#2722])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-snb4/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@gem_ctx_persistence@close-replace-race:
    - shard-kbl:          [TIMEOUT][84] -> [PASS][85]
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-kbl2/igt@gem_ctx_persistence@close-replace-race.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-kbl3/igt@gem_ctx_persistence@close-replace-race.html

  * {igt@gem_exec_fair@basic-deadline}:
    - shard-kbl:          [FAIL][86] ([i915#2846]) -> [PASS][87]
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-kbl6/igt@gem_exec_fair@basic-deadline.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-kbl6/igt@gem_exec_fair@basic-deadline.html
    - shard-glk:          [FAIL][88] ([i915#2846]) -> [PASS][89]
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-glk7/igt@gem_exec_fair@basic-deadline.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-glk2/igt@gem_exec_fair@basic-deadline.html

  * {igt@gem_exec_fair@basic-none@vcs0}:
    - shard-kbl:          [FAIL][90] ([i915#2842]) -> [PASS][91] +2 similar issues
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-kbl3/igt@gem_exec_fair@basic-none@vcs0.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-kbl4/igt@gem_exec_fair@basic-none@vcs0.html

  * {igt@gem_exec_schedule@u-fairslice@vcs0}:
    - shard-iclb:         [DMESG-WARN][92] ([i915#2803]) -> [PASS][93]
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-iclb8/igt@gem_exec_schedule@u-fairslice@vcs0.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-iclb5/igt@gem_exec_schedule@u-fairslice@vcs0.html

  * igt@gem_exec_whisper@basic-queues-forked:
    - shard-glk:          [DMESG-WARN][94] ([i915#118] / [i915#95]) -> [PASS][95]
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-glk2/igt@gem_exec_whisper@basic-queues-forked.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-glk1/igt@gem_exec_whisper@basic-queues-forked.html

  * igt@i915_pm_dc@dc5-psr:
    - shard-iclb:         [FAIL][96] ([i915#2745]) -> [PASS][97]
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-iclb2/igt@i915_pm_dc@dc5-psr.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-iclb7/igt@i915_pm_dc@dc5-psr.html
    - shard-tglb:         [FAIL][98] ([i915#2745]) -> [PASS][99]
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-tglb6/igt@i915_pm_dc@dc5-psr.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-tglb7/igt@i915_pm_dc@dc5-psr.html

  * igt@i915_pm_rpm@drm-resources-equal:
    - shard-kbl:          [SKIP][100] ([fdo#109271]) -> [PASS][101]
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-kbl3/igt@i915_pm_rpm@drm-resources-equal.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-kbl1/igt@i915_pm_rpm@drm-resources-equal.html
    - shard-iclb:         [SKIP][102] ([i915#579]) -> [PASS][103] +1 similar issue
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-iclb2/igt@i915_pm_rpm@drm-resources-equal.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-iclb1/igt@i915_pm_rpm@drm-resources-equal.html
    - shard-apl:          [SKIP][104] ([fdo#109271]) -> [PASS][105]
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-apl1/igt@i915_pm_rpm@drm-resources-equal.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-apl8/igt@i915_pm_rpm@drm-resources-equal.html
    - shard-tglb:         [SKIP][106] ([i915#579]) -> [PASS][107]
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-tglb6/igt@i915_pm_rpm@drm-resources-equal.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-tglb3/igt@i915_pm_rpm@drm-resources-equal.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing@dp-1-pipe-c:
    - shard-kbl:          [DMESG-WARN][108] ([i915#165] / [i915#180] / [i915#78]) -> [PASS][109]
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-kbl2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@dp-1-pipe-c.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-kbl2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@dp-1-pipe-c.html

  * igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque:
    - shard-kbl:          [FAIL][110] ([i915#54]) -> [PASS][111]
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html
    - shard-apl:          [FAIL][112] ([i915#54]) -> [PASS][113]
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-apl4/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-apl3/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html
    - shard-glk:          [FAIL][114] ([i915#54]) -> [PASS][115]
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-glk2/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-glk2/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html

  * igt@kms_cursor_edge_walk@pipe-c-256x256-right-edge:
    - shard-kbl:          [DMESG-WARN][116] ([i915#180] / [i915#78]) -> [PASS][117]
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-kbl2/igt@kms_cursor_edge_walk@pipe-c-256x256-right-edge.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-kbl1/igt@kms_cursor_edge_walk@pipe-c-256x256-right-edge.html

  * igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2:
    - shard-glk:          [DMESG-WARN][118] ([i915#2635]) -> [PASS][119]
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-glk9/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-glk1/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@2x-flip-vs-suspend@ac-hdmi-a1-hdmi-a2:
    - shard-glk:          [DMESG-WARN][120] -> [PASS][121] +1 similar issue
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-glk9/igt@kms_flip@2x-flip-vs-suspend@ac-hdmi-a1-hdmi-a2.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-glk1/igt@kms_flip@2x-flip-vs-suspend@ac-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
    - shard-tglb:         [FAIL][122] ([i915#2598]) -> [PASS][123]
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-tglb1/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-tglb8/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
    - shard-kbl:          [DMESG-WARN][124] ([i915#180]) -> [PASS][125]
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a1:
    - shard-hsw:          [INCOMPLETE][126] ([i915#2295]) -> [PASS][127]
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-hsw4/igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a1.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-hsw6/igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a1.html

  * igt@kms_plane_lowres@pipe-a-tiling-y:
    - shard-kbl:          [DMESG-WARN][128] ([i915#165] / [i915#180] / [i915#2621] / [i915#78]) -> [PASS][129]
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-kbl2/igt@kms_plane_lowres@pipe-a-tiling-y.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-kbl4/igt@kms_plane_lowres@pipe-a-tiling-y.html

  * igt@kms_psr@psr2_cursor_blt:
    - shard-iclb:         [SKIP][130] ([fdo#109441]) -> [PASS][131]
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-iclb4/igt@kms_psr@psr2_cursor_blt.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html

  * igt@syncobj_wait@wait-for-submit-snapshot:
    - shard-kbl:          [DMESG-WARN][132] ([i915#165]) -> [PASS][133]
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-kbl2/igt@syncobj_wait@wait-for-submit-snapshot.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-kbl4/igt@syncobj_wait@wait-for-submit-snapshot.html

  
#### Warnings ####

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-iclb:         [WARN][134] ([i915#2681] / [i915#2684]) -> [WARN][135] ([i915#1804] / [i915#2684])
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-iclb8/igt@i915_pm_rc6_residency@rc6-fence.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-iclb3/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-iclb:         [WARN][136] ([i915#2681] / [i915#2684]) -> [WARN][137] ([i915#2684])
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-iclb1/igt@i915_pm_rc6_residency@rc6-idle.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-iclb5/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@runner@aborted:
    - shard-kbl:          ([FAIL][138], [FAIL][139]) ([i915#2295]) -> ([FAIL][140], [FAIL][141]) ([i915#1814] / [i915#2295] / [i915#2505])
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-kbl4/igt@runner@aborted.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-kbl7/igt@runner@aborted.html
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-kbl6/igt@runner@aborted.html
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-kbl7/igt@runner@aborted.html
    - shard-iclb:         ([FAIL][142], [FAIL][143]) ([i915#2295] / [i915#2426] / [i915#2724]) -> ([FAIL][144], [FAIL][145]) ([i915#1814] / [i915#2295] / [i915#2724])
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-iclb3/igt@runner@aborted.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-iclb8/igt@runner@aborted.html
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-iclb7/igt@runner@aborted.html
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-iclb2/igt@runner@aborted.html
    - shard-apl:          [FAIL][146] ([i915#2295]) -> ([FAIL][147], [FAIL][148]) ([i915#1814] / [i915#2295])
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-apl6/igt@runner@aborted.html
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-apl2/igt@runner@aborted.html
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-apl4/igt@runner@aborted.html
    - shard-glk:          ([FAIL][149], [FAIL][150]) ([i915#2295] / [k.org#202321]) -> ([FAIL][151], [FAIL][152], [FAIL][153]) ([i915#1814] / [i915#2295] / [k.org#202321])
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-glk9/igt@runner@aborted.html
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-glk6/igt@runner@aborted.html
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-glk4/igt@runner@aborted.html
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-glk4/igt@runner@aborted.html
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-glk6/igt@runner@aborted.html
    - shard-tglb:         [FAIL][154] ([i915#2295] / [i915#2667]) -> ([FAIL][155], [FAIL][156], [FAIL][157]) ([i915#1814] / [i915#2295] / [i915#2426] / [i915#2667] / [i915#2803])
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9596/shard-tglb3/igt@runner@aborted.html
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-tglb5/igt@runner@aborted.html
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-tglb8/igt@runner@aborted.html
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/shard-tglb6/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5388/index.html

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Re: [igt-dev] [PATCH 1/3] lib: Add stride and size calculation for amdgpu + tiling

[Cornij, Nikola]

[AMD Public Use]

Reviewed by: Nikola Cornij < nikola.cornij@amd.com>

-----Original Message-----
From: Kim, Sung joon <Sungjoon.Kim@amd.com> 
Sent: Tuesday, January 12, 2021 5:54 PM
To: igt-dev@lists.freedesktop.org
Cc: Kazlauskas, Nicholas <Nicholas.Kazlauskas@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>; Cornij, Nikola <Nikola.Cornij@amd.com>; Kim, Sung joon <Sungjoon.Kim@amd.com>
Subject: [PATCH 1/3] lib: Add stride and size calculation for amdgpu + tiling

For amdgpu, we need to calculate the stride and size of framebuffer correctly during non-linear tiling mode

v2: add call to amdgpu tiling/swizzle addressing
Signed-off-by: Sung Joon Kim <sungkim@amd.com>
---
 lib/igt_fb.c | 24 +++++++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/lib/igt_fb.c b/lib/igt_fb.c index 4b9be47e..6eebe048 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -671,6 +671,11 @@ static uint32_t calc_plane_stride(struct igt_fb *fb, int plane)
 		 * so the easiest way is to align the luma stride to 256.
 		 */
 		return ALIGN(min_stride, 256);
+	}else if (fb->modifier != LOCAL_DRM_FORMAT_MOD_NONE && is_amdgpu_device(fb->fd)) {
+		/*
+		 * For amdgpu device with tiling mode
+		 */
+		return ALIGN(min_stride, 512);
 	} else if (is_gen12_ccs_cc_plane(fb, plane)) {
 		/* clear color always fixed to 64 bytes */
 		return 64;
@@ -711,6 +716,12 @@ static uint64_t calc_plane_size(struct igt_fb *fb, int plane)
 		size = roundup_power_of_two(size);
 
 		return size;
+	} else if (fb->modifier != LOCAL_DRM_FORMAT_MOD_NONE && is_amdgpu_device(fb->fd)) {
+		/*
+		 * For amdgpu device with tiling mode
+		 */
+		return (uint64_t) fb->strides[plane] *
+			ALIGN(fb->plane_height[plane], 512);
 	} else if (is_gen12_ccs_plane(fb, plane)) {
 		/* The AUX CCS surface must be page aligned */
 		return (uint64_t)fb->strides[plane] * @@ -2352,6 +2363,13 @@ static void free_linear_mapping(struct fb_blit_upload *blit)
 
 		vc4_fb_convert_plane_to_tiled(fb, map, &linear->fb, &linear->map);
 
+		munmap(map, fb->size);
+	} else if (is_amdgpu_device(fd) && fb->modifier != 0) {
+		void *map = igt_amd_mmap_bo(fd, fb->gem_handle, fb->size, 
+PROT_WRITE);
+
+		igt_amd_fb_convert_plane_to_tiled(fb, map, &linear->fb, linear->map);
+
+		munmap(linear->map, fb->size);
 		munmap(map, fb->size);
 	} else {
 		gem_munmap(linear->map, linear->fb.size); @@ -2419,6 +2437,10 @@ static void setup_linear_mapping(struct fb_blit_upload *blit)
 		vc4_fb_convert_plane_from_tiled(&linear->fb, &linear->map, fb, map);
 
 		munmap(map, fb->size);
+	} else if (is_amdgpu_device(fd) && fb->modifier != 0) {
+		linear->map = igt_amd_mmap_bo(fd, linear->fb.gem_handle,
+					      linear->fb.size,
+					      PROT_READ | PROT_WRITE);
 	} else {
 		/* Copy fb content to linear BO */
 		gem_set_domain(fd, linear->fb.gem_handle, @@ -3625,7 +3647,7 @@ cairo_surface_t *igt_get_cairo_surface(int fd, struct igt_fb *fb)
 		if (use_convert(fb))
 			create_cairo_surface__convert(fd, fb);
 		else if (use_blitter(fb) || use_enginecopy(fb) ||
-			 igt_vc4_is_tiled(fb->modifier))
+			 igt_vc4_is_tiled(fb->modifier) || (is_amdgpu_device(fd) && 
+fb->modifier != 0))
 			create_cairo_surface__gpu(fd, fb);
 		else
 			create_cairo_surface__gtt(fd, fb);
--
2.25.1
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[igt-dev] ✗ Fi.CI.BUILD: failure for series starting with [1/3] lib: Add stride and size calculation for amdgpu + tiling (rev4)

[Patchwork]

== Series Details ==

Series: series starting with [1/3] lib: Add stride and size calculation for amdgpu + tiling (rev4)
URL   : https://patchwork.freedesktop.org/series/85772/
State : failure

== Summary ==

Applying: lib: Add stride and size calculation for amdgpu + tiling
Patch failed at 0001 lib: Add stride and size calculation for amdgpu + tiling
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".


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Re: [igt-dev] [PATCH 1/3] lib: Add stride and size calculation for amdgpu + tiling

[Petri Latvala]

On Tue, Jan 12, 2021 at 05:53:58PM -0500, Sung Joon Kim wrote:
> For amdgpu, we need to calculate the stride and size of framebuffer correctly during non-linear tiling mode
> 
> v2: add call to amdgpu tiling/swizzle addressing
> Signed-off-by: Sung Joon Kim <sungkim@amd.com>
> ---
>  lib/igt_fb.c | 24 +++++++++++++++++++++++-
>  1 file changed, 23 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/igt_fb.c b/lib/igt_fb.c
> index 4b9be47e..6eebe048 100644
> --- a/lib/igt_fb.c
> +++ b/lib/igt_fb.c
> @@ -671,6 +671,11 @@ static uint32_t calc_plane_stride(struct igt_fb *fb, int plane)
>  		 * so the easiest way is to align the luma stride to 256.
>  		 */
>  		return ALIGN(min_stride, 256);
> +	}else if (fb->modifier != LOCAL_DRM_FORMAT_MOD_NONE && is_amdgpu_device(fb->fd)) {
> +		/*
> +		 * For amdgpu device with tiling mode
> +		 */
> +		return ALIGN(min_stride, 512);
>  	} else if (is_gen12_ccs_cc_plane(fb, plane)) {
>  		/* clear color always fixed to 64 bytes */
>  		return 64;
> @@ -711,6 +716,12 @@ static uint64_t calc_plane_size(struct igt_fb *fb, int plane)
>  		size = roundup_power_of_two(size);
>  
>  		return size;
> +	} else if (fb->modifier != LOCAL_DRM_FORMAT_MOD_NONE && is_amdgpu_device(fb->fd)) {
> +		/*
> +		 * For amdgpu device with tiling mode
> +		 */
> +		return (uint64_t) fb->strides[plane] *
> +			ALIGN(fb->plane_height[plane], 512);
>  	} else if (is_gen12_ccs_plane(fb, plane)) {
>  		/* The AUX CCS surface must be page aligned */
>  		return (uint64_t)fb->strides[plane] *
> @@ -2352,6 +2363,13 @@ static void free_linear_mapping(struct fb_blit_upload *blit)
>  
>  		vc4_fb_convert_plane_to_tiled(fb, map, &linear->fb, &linear->map);
>  
> +		munmap(map, fb->size);
> +	} else if (is_amdgpu_device(fd) && fb->modifier != 0) {
> +		void *map = igt_amd_mmap_bo(fd, fb->gem_handle, fb->size, PROT_WRITE);
> +
> +		igt_amd_fb_convert_plane_to_tiled(fb, map, &linear->fb, linear->map);
> +
> +		munmap(linear->map, fb->size);
>  		munmap(map, fb->size);
>  	} else {
>  		gem_munmap(linear->map, linear->fb.size);
> @@ -2419,6 +2437,10 @@ static void setup_linear_mapping(struct fb_blit_upload *blit)
>  		vc4_fb_convert_plane_from_tiled(&linear->fb, &linear->map, fb, map);
>  
>  		munmap(map, fb->size);
> +	} else if (is_amdgpu_device(fd) && fb->modifier != 0) {
> +		linear->map = igt_amd_mmap_bo(fd, linear->fb.gem_handle,
> +					      linear->fb.size,
> +					      PROT_READ | PROT_WRITE);
>  	} else {
>  		/* Copy fb content to linear BO */
>  		gem_set_domain(fd, linear->fb.gem_handle,
> @@ -3625,7 +3647,7 @@ cairo_surface_t *igt_get_cairo_surface(int fd, struct igt_fb *fb)
>  		if (use_convert(fb))
>  			create_cairo_surface__convert(fd, fb);
>  		else if (use_blitter(fb) || use_enginecopy(fb) ||
> -			 igt_vc4_is_tiled(fb->modifier))
> +			 igt_vc4_is_tiled(fb->modifier) || (is_amdgpu_device(fd) && fb->modifier != 0))

This line grows a bit long, add newline after the ||



-- 
Petri Latvala
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Re: [igt-dev] [PATCH 1/3] lib: Add stride and size calculation for amdgpu + tiling

[Cornij, Nikola]

-----Original Message-----
From: Kim, Sung joon <Sungjoon.Kim@amd.com> 
Sent: Tuesday, January 12, 2021 5:54 PM
To: igt-dev@lists.freedesktop.org
Cc: Kazlauskas, Nicholas <Nicholas.Kazlauskas@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>; Cornij, Nikola <Nikola.Cornij@amd.com>; Kim, Sung joon <Sungjoon.Kim@amd.com>
Subject: [PATCH 1/3] lib: Add stride and size calculation for amdgpu + tiling

For amdgpu, we need to calculate the stride and size of framebuffer correctly during non-linear tiling mode

v2: add call to amdgpu tiling/swizzle addressing
Signed-off-by: Sung Joon Kim <sungkim@amd.com>
Reviewed by: Nikola Cornij < nikola.cornij@amd.com>
---
 lib/igt_fb.c | 24 +++++++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/lib/igt_fb.c b/lib/igt_fb.c index 4b9be47e..6eebe048 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -671,6 +671,11 @@ static uint32_t calc_plane_stride(struct igt_fb *fb, int plane)
 		 * so the easiest way is to align the luma stride to 256.
 		 */
 		return ALIGN(min_stride, 256);
+	}else if (fb->modifier != LOCAL_DRM_FORMAT_MOD_NONE && is_amdgpu_device(fb->fd)) {
+		/*
+		 * For amdgpu device with tiling mode
+		 */
+		return ALIGN(min_stride, 512);
 	} else if (is_gen12_ccs_cc_plane(fb, plane)) {
 		/* clear color always fixed to 64 bytes */
 		return 64;
@@ -711,6 +716,12 @@ static uint64_t calc_plane_size(struct igt_fb *fb, int plane)
 		size = roundup_power_of_two(size);
 
 		return size;
+	} else if (fb->modifier != LOCAL_DRM_FORMAT_MOD_NONE && is_amdgpu_device(fb->fd)) {
+		/*
+		 * For amdgpu device with tiling mode
+		 */
+		return (uint64_t) fb->strides[plane] *
+			ALIGN(fb->plane_height[plane], 512);
 	} else if (is_gen12_ccs_plane(fb, plane)) {
 		/* The AUX CCS surface must be page aligned */
 		return (uint64_t)fb->strides[plane] * @@ -2352,6 +2363,13 @@ static void free_linear_mapping(struct fb_blit_upload *blit)
 
 		vc4_fb_convert_plane_to_tiled(fb, map, &linear->fb, &linear->map);
 
+		munmap(map, fb->size);
+	} else if (is_amdgpu_device(fd) && fb->modifier != 0) {
+		void *map = igt_amd_mmap_bo(fd, fb->gem_handle, fb->size, 
+PROT_WRITE);
+
+		igt_amd_fb_convert_plane_to_tiled(fb, map, &linear->fb, linear->map);
+
+		munmap(linear->map, fb->size);
 		munmap(map, fb->size);
 	} else {
 		gem_munmap(linear->map, linear->fb.size); @@ -2419,6 +2437,10 @@ static void setup_linear_mapping(struct fb_blit_upload *blit)
 		vc4_fb_convert_plane_from_tiled(&linear->fb, &linear->map, fb, map);
 
 		munmap(map, fb->size);
+	} else if (is_amdgpu_device(fd) && fb->modifier != 0) {
+		linear->map = igt_amd_mmap_bo(fd, linear->fb.gem_handle,
+					      linear->fb.size,
+					      PROT_READ | PROT_WRITE);
 	} else {
 		/* Copy fb content to linear BO */
 		gem_set_domain(fd, linear->fb.gem_handle, @@ -3625,7 +3647,7 @@ cairo_surface_t *igt_get_cairo_surface(int fd, struct igt_fb *fb)
 		if (use_convert(fb))
 			create_cairo_surface__convert(fd, fb);
 		else if (use_blitter(fb) || use_enginecopy(fb) ||
-			 igt_vc4_is_tiled(fb->modifier))
+			 igt_vc4_is_tiled(fb->modifier) || (is_amdgpu_device(fd) && 
+fb->modifier != 0))
 			create_cairo_surface__gpu(fd, fb);
 		else
 			create_cairo_surface__gtt(fd, fb);
--
2.25.1

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Re: [igt-dev] [PATCH 1/3] lib: Add stride and size calculation for amdgpu + tiling

[Kazlauskas, Nicholas]

On 2021-01-12 5:53 p.m., Sung Joon Kim wrote:
> For amdgpu, we need to calculate the stride and size of framebuffer correctly during non-linear tiling mode
> 
> v2: add call to amdgpu tiling/swizzle addressing
> Signed-off-by: Sung Joon Kim <sungkim@amd.com>
> ---
>   lib/igt_fb.c | 24 +++++++++++++++++++++++-
>   1 file changed, 23 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/igt_fb.c b/lib/igt_fb.c
> index 4b9be47e..6eebe048 100644
> --- a/lib/igt_fb.c
> +++ b/lib/igt_fb.c
> @@ -671,6 +671,11 @@ static uint32_t calc_plane_stride(struct igt_fb *fb, int plane)
>   		 * so the easiest way is to align the luma stride to 256.
>   		 */
>   		return ALIGN(min_stride, 256);
> +	}else if (fb->modifier != LOCAL_DRM_FORMAT_MOD_NONE && is_amdgpu_device(fb->fd)) {
> +		/*
> +		 * For amdgpu device with tiling mode
> +		 */
> +		return ALIGN(min_stride, 512);
>   	} else if (is_gen12_ccs_cc_plane(fb, plane)) {
>   		/* clear color always fixed to 64 bytes */
>   		return 64;
> @@ -711,6 +716,12 @@ static uint64_t calc_plane_size(struct igt_fb *fb, int plane)
>   		size = roundup_power_of_two(size);
>   
>   		return size;
> +	} else if (fb->modifier != LOCAL_DRM_FORMAT_MOD_NONE && is_amdgpu_device(fb->fd)) {
> +		/*
> +		 * For amdgpu device with tiling mode
> +		 */
> +		return (uint64_t) fb->strides[plane] *
> +			ALIGN(fb->plane_height[plane], 512);
>   	} else if (is_gen12_ccs_plane(fb, plane)) {
>   		/* The AUX CCS surface must be page aligned */
>   		return (uint64_t)fb->strides[plane] *
> @@ -2352,6 +2363,13 @@ static void free_linear_mapping(struct fb_blit_upload *blit)
>   
>   		vc4_fb_convert_plane_to_tiled(fb, map, &linear->fb, &linear->map);
>   
> +		munmap(map, fb->size);
> +	} else if (is_amdgpu_device(fd) && fb->modifier != 0) {
> +		void *map = igt_amd_mmap_bo(fd, fb->gem_handle, fb->size, PROT_WRITE);
> +
> +		igt_amd_fb_convert_plane_to_tiled(fb, map, &linear->fb, linear->map);

Are you missing a patch in the series?

I don't see the definition for igt_amd_fb_convert_plane_to_tiled() anywhere.

Regards,
Nicholas Kazlauskas

> +
> +		munmap(linear->map, fb->size);
>   		munmap(map, fb->size);
>   	} else {
>   		gem_munmap(linear->map, linear->fb.size);
> @@ -2419,6 +2437,10 @@ static void setup_linear_mapping(struct fb_blit_upload *blit)
>   		vc4_fb_convert_plane_from_tiled(&linear->fb, &linear->map, fb, map);
>   
>   		munmap(map, fb->size);
> +	} else if (is_amdgpu_device(fd) && fb->modifier != 0) {
> +		linear->map = igt_amd_mmap_bo(fd, linear->fb.gem_handle,
> +					      linear->fb.size,
> +					      PROT_READ | PROT_WRITE);
>   	} else {
>   		/* Copy fb content to linear BO */
>   		gem_set_domain(fd, linear->fb.gem_handle,
> @@ -3625,7 +3647,7 @@ cairo_surface_t *igt_get_cairo_surface(int fd, struct igt_fb *fb)
>   		if (use_convert(fb))
>   			create_cairo_surface__convert(fd, fb);
>   		else if (use_blitter(fb) || use_enginecopy(fb) ||
> -			 igt_vc4_is_tiled(fb->modifier))
> +			 igt_vc4_is_tiled(fb->modifier) || (is_amdgpu_device(fd) && fb->modifier != 0))
>   			create_cairo_surface__gpu(fd, fb);
>   		else
>   			create_cairo_surface__gtt(fd, fb);
> 

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Re: [igt-dev] [PATCH 1/3] lib: Add stride and size calculation for amdgpu + tiling

[Kim, Sung joon]

[AMD Official Use Only - Internal Distribution Only]

On 2021-01-12 5:53 p.m., Sung Joon Kim wrote:
> For amdgpu, we need to calculate the stride and size of framebuffer 
> correctly during non-linear tiling mode
> 
> v2: add call to amdgpu tiling/swizzle addressing
> Signed-off-by: Sung Joon Kim <sungkim@amd.com>
> ---
>   lib/igt_fb.c | 24 +++++++++++++++++++++++-
>   1 file changed, 23 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/igt_fb.c b/lib/igt_fb.c index 4b9be47e..6eebe048 
> 100644
> --- a/lib/igt_fb.c
> +++ b/lib/igt_fb.c
> @@ -671,6 +671,11 @@ static uint32_t calc_plane_stride(struct igt_fb *fb, int plane)
>   		 * so the easiest way is to align the luma stride to 256.
>   		 */
>   		return ALIGN(min_stride, 256);
> +	}else if (fb->modifier != LOCAL_DRM_FORMAT_MOD_NONE && is_amdgpu_device(fb->fd)) {
> +		/*
> +		 * For amdgpu device with tiling mode
> +		 */
> +		return ALIGN(min_stride, 512);
>   	} else if (is_gen12_ccs_cc_plane(fb, plane)) {
>   		/* clear color always fixed to 64 bytes */
>   		return 64;
> @@ -711,6 +716,12 @@ static uint64_t calc_plane_size(struct igt_fb *fb, int plane)
>   		size = roundup_power_of_two(size);
>   
>   		return size;
> +	} else if (fb->modifier != LOCAL_DRM_FORMAT_MOD_NONE && is_amdgpu_device(fb->fd)) {
> +		/*
> +		 * For amdgpu device with tiling mode
> +		 */
> +		return (uint64_t) fb->strides[plane] *
> +			ALIGN(fb->plane_height[plane], 512);
>   	} else if (is_gen12_ccs_plane(fb, plane)) {
>   		/* The AUX CCS surface must be page aligned */
>   		return (uint64_t)fb->strides[plane] * @@ -2352,6 +2363,13 @@ 
> static void free_linear_mapping(struct fb_blit_upload *blit)
>   
>   		vc4_fb_convert_plane_to_tiled(fb, map, &linear->fb, &linear->map);
>   
> +		munmap(map, fb->size);
> +	} else if (is_amdgpu_device(fd) && fb->modifier != 0) {
> +		void *map = igt_amd_mmap_bo(fd, fb->gem_handle, fb->size, 
> +PROT_WRITE);
> +
> +		igt_amd_fb_convert_plane_to_tiled(fb, map, &linear->fb, 
> +linear->map);

Hi Nicholas,

The definition of that function should be in igt_amd.c which is shown in [PATCH 3/3].

Thanks,
Joon

Are you missing a patch in the series?

I don't see the definition for igt_amd_fb_convert_plane_to_tiled() anywhere.

Regards,
Nicholas Kazlauskas

> +
> +		munmap(linear->map, fb->size);
>   		munmap(map, fb->size);
>   	} else {
>   		gem_munmap(linear->map, linear->fb.size); @@ -2419,6 +2437,10 @@ 
> static void setup_linear_mapping(struct fb_blit_upload *blit)
>   		vc4_fb_convert_plane_from_tiled(&linear->fb, &linear->map, fb, 
> map);
>   
>   		munmap(map, fb->size);
> +	} else if (is_amdgpu_device(fd) && fb->modifier != 0) {
> +		linear->map = igt_amd_mmap_bo(fd, linear->fb.gem_handle,
> +					      linear->fb.size,
> +					      PROT_READ | PROT_WRITE);
>   	} else {
>   		/* Copy fb content to linear BO */
>   		gem_set_domain(fd, linear->fb.gem_handle, @@ -3625,7 +3647,7 @@ 
> cairo_surface_t *igt_get_cairo_surface(int fd, struct igt_fb *fb)
>   		if (use_convert(fb))
>   			create_cairo_surface__convert(fd, fb);
>   		else if (use_blitter(fb) || use_enginecopy(fb) ||
> -			 igt_vc4_is_tiled(fb->modifier))
> +			 igt_vc4_is_tiled(fb->modifier) || (is_amdgpu_device(fd) && 
> +fb->modifier != 0))
>   			create_cairo_surface__gpu(fd, fb);
>   		else
>   			create_cairo_surface__gtt(fd, fb);
> 
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Re: [igt-dev] [PATCH 1/3] lib: Add stride and size calculation for amdgpu + tiling

[Kazlauskas, Nicholas]

On 2021-01-14 11:43 a.m., Kim, Sung joon wrote:
> [AMD Official Use Only - Internal Distribution Only]
> 
> On 2021-01-12 5:53 p.m., Sung Joon Kim wrote:
>> For amdgpu, we need to calculate the stride and size of framebuffer
>> correctly during non-linear tiling mode
>>
>> v2: add call to amdgpu tiling/swizzle addressing
>> Signed-off-by: Sung Joon Kim <sungkim@amd.com>
>> ---
>>    lib/igt_fb.c | 24 +++++++++++++++++++++++-
>>    1 file changed, 23 insertions(+), 1 deletion(-)
>>
>> diff --git a/lib/igt_fb.c b/lib/igt_fb.c index 4b9be47e..6eebe048
>> 100644
>> --- a/lib/igt_fb.c
>> +++ b/lib/igt_fb.c
>> @@ -671,6 +671,11 @@ static uint32_t calc_plane_stride(struct igt_fb *fb, int plane)
>>    		 * so the easiest way is to align the luma stride to 256.
>>    		 */
>>    		return ALIGN(min_stride, 256);
>> +	}else if (fb->modifier != LOCAL_DRM_FORMAT_MOD_NONE && is_amdgpu_device(fb->fd)) {
>> +		/*
>> +		 * For amdgpu device with tiling mode
>> +		 */
>> +		return ALIGN(min_stride, 512);
>>    	} else if (is_gen12_ccs_cc_plane(fb, plane)) {
>>    		/* clear color always fixed to 64 bytes */
>>    		return 64;
>> @@ -711,6 +716,12 @@ static uint64_t calc_plane_size(struct igt_fb *fb, int plane)
>>    		size = roundup_power_of_two(size);
>>    
>>    		return size;
>> +	} else if (fb->modifier != LOCAL_DRM_FORMAT_MOD_NONE && is_amdgpu_device(fb->fd)) {
>> +		/*
>> +		 * For amdgpu device with tiling mode
>> +		 */
>> +		return (uint64_t) fb->strides[plane] *
>> +			ALIGN(fb->plane_height[plane], 512);
>>    	} else if (is_gen12_ccs_plane(fb, plane)) {
>>    		/* The AUX CCS surface must be page aligned */
>>    		return (uint64_t)fb->strides[plane] * @@ -2352,6 +2363,13 @@
>> static void free_linear_mapping(struct fb_blit_upload *blit)
>>    
>>    		vc4_fb_convert_plane_to_tiled(fb, map, &linear->fb, &linear->map);
>>    
>> +		munmap(map, fb->size);
>> +	} else if (is_amdgpu_device(fd) && fb->modifier != 0) {
>> +		void *map = igt_amd_mmap_bo(fd, fb->gem_handle, fb->size,
>> +PROT_WRITE);
>> +
>> +		igt_amd_fb_convert_plane_to_tiled(fb, map, &linear->fb,
>> +linear->map);
> 
> Hi Nicholas,
> 
> The definition of that function should be in igt_amd.c which is shown in [PATCH 3/3].
> 
> Thanks,
> Joon

Can you move that definition into patch #1 so each patch will correctly 
compile?

Regards,
Nicholas Kazlauskas

> 
> Are you missing a patch in the series?
> 
> I don't see the definition for igt_amd_fb_convert_plane_to_tiled() anywhere.
> 
> Regards,
> Nicholas Kazlauskas
> 
>> +
>> +		munmap(linear->map, fb->size);
>>    		munmap(map, fb->size);
>>    	} else {
>>    		gem_munmap(linear->map, linear->fb.size); @@ -2419,6 +2437,10 @@
>> static void setup_linear_mapping(struct fb_blit_upload *blit)
>>    		vc4_fb_convert_plane_from_tiled(&linear->fb, &linear->map, fb,
>> map);
>>    
>>    		munmap(map, fb->size);
>> +	} else if (is_amdgpu_device(fd) && fb->modifier != 0) {
>> +		linear->map = igt_amd_mmap_bo(fd, linear->fb.gem_handle,
>> +					      linear->fb.size,
>> +					      PROT_READ | PROT_WRITE);
>>    	} else {
>>    		/* Copy fb content to linear BO */
>>    		gem_set_domain(fd, linear->fb.gem_handle, @@ -3625,7 +3647,7 @@
>> cairo_surface_t *igt_get_cairo_surface(int fd, struct igt_fb *fb)
>>    		if (use_convert(fb))
>>    			create_cairo_surface__convert(fd, fb);
>>    		else if (use_blitter(fb) || use_enginecopy(fb) ||
>> -			 igt_vc4_is_tiled(fb->modifier))
>> +			 igt_vc4_is_tiled(fb->modifier) || (is_amdgpu_device(fd) &&
>> +fb->modifier != 0))
>>    			create_cairo_surface__gpu(fd, fb);
>>    		else
>>    			create_cairo_surface__gtt(fd, fb);
>>

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[igt-dev] ✗ Fi.CI.BUILD: failure for series starting with [1/3] lib: Add stride and size calculation for amdgpu + tiling (rev7)

[Patchwork]

== Series Details ==

Series: series starting with [1/3] lib: Add stride and size calculation for amdgpu + tiling (rev7)
URL   : https://patchwork.freedesktop.org/series/85772/
State : failure

== Summary ==

Applying: lib: Add stride and size calculation for amdgpu + tiling
Patch failed at 0001 lib: Add stride and size calculation for amdgpu + tiling
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".


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[igt-dev] [PATCH 1/3] lib: Add stride and size calculation for amdgpu + tiling

[Sung Joon Kim]

For amdgpu, we need to calculate the stride and size of framebuffer correctly during non-linear tiling mode

v2: add call to amdgpu tiling/swizzle addressing
Signed-off-by: Sung Joon Kim <sungkim@amd.com>
---
 lib/igt_fb.c | 24 +++++++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 4b9be47e..6eebe048 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -671,6 +671,11 @@ static uint32_t calc_plane_stride(struct igt_fb *fb, int plane)
 		 * so the easiest way is to align the luma stride to 256.
 		 */
 		return ALIGN(min_stride, 256);
+	}else if (fb->modifier != LOCAL_DRM_FORMAT_MOD_NONE && is_amdgpu_device(fb->fd)) {
+		/*
+		 * For amdgpu device with tiling mode
+		 */
+		return ALIGN(min_stride, 512);
 	} else if (is_gen12_ccs_cc_plane(fb, plane)) {
 		/* clear color always fixed to 64 bytes */
 		return 64;
@@ -711,6 +716,12 @@ static uint64_t calc_plane_size(struct igt_fb *fb, int plane)
 		size = roundup_power_of_two(size);
 
 		return size;
+	} else if (fb->modifier != LOCAL_DRM_FORMAT_MOD_NONE && is_amdgpu_device(fb->fd)) {
+		/*
+		 * For amdgpu device with tiling mode
+		 */
+		return (uint64_t) fb->strides[plane] *
+			ALIGN(fb->plane_height[plane], 512);
 	} else if (is_gen12_ccs_plane(fb, plane)) {
 		/* The AUX CCS surface must be page aligned */
 		return (uint64_t)fb->strides[plane] *
@@ -2352,6 +2363,13 @@ static void free_linear_mapping(struct fb_blit_upload *blit)
 
 		vc4_fb_convert_plane_to_tiled(fb, map, &linear->fb, &linear->map);
 
+		munmap(map, fb->size);
+	} else if (is_amdgpu_device(fd) && fb->modifier != 0) {
+		void *map = igt_amd_mmap_bo(fd, fb->gem_handle, fb->size, PROT_WRITE);
+
+		igt_amd_fb_convert_plane_to_tiled(fb, map, &linear->fb, linear->map);
+
+		munmap(linear->map, fb->size);
 		munmap(map, fb->size);
 	} else {
 		gem_munmap(linear->map, linear->fb.size);
@@ -2419,6 +2437,10 @@ static void setup_linear_mapping(struct fb_blit_upload *blit)
 		vc4_fb_convert_plane_from_tiled(&linear->fb, &linear->map, fb, map);
 
 		munmap(map, fb->size);
+	} else if (is_amdgpu_device(fd) && fb->modifier != 0) {
+		linear->map = igt_amd_mmap_bo(fd, linear->fb.gem_handle,
+					      linear->fb.size,
+					      PROT_READ | PROT_WRITE);
 	} else {
 		/* Copy fb content to linear BO */
 		gem_set_domain(fd, linear->fb.gem_handle,
@@ -3625,7 +3647,7 @@ cairo_surface_t *igt_get_cairo_surface(int fd, struct igt_fb *fb)
 		if (use_convert(fb))
 			create_cairo_surface__convert(fd, fb);
 		else if (use_blitter(fb) || use_enginecopy(fb) ||
-			 igt_vc4_is_tiled(fb->modifier))
+			 igt_vc4_is_tiled(fb->modifier) || (is_amdgpu_device(fd) && fb->modifier != 0))
 			create_cairo_surface__gpu(fd, fb);
 		else
 			create_cairo_surface__gtt(fd, fb);
-- 
2.25.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] [PATCH 3/3] lib: Implement tiling/swizzle addressing for amdgpu

[Sung Joon Kim]

The swizzle mode is 64kb withe standard pattern.

Signed-off-by: Sung Joon Kim <sungkim@amd.com>
---
 lib/igt_amd.c | 132 ++++++++++++++++++++++++++++++++++++++++++++++++++
 lib/igt_amd.h |  31 ++++++++++++
 2 files changed, 163 insertions(+)

diff --git a/lib/igt_amd.c b/lib/igt_amd.c
index abd3ad96..737e5670 100644
--- a/lib/igt_amd.c
+++ b/lib/igt_amd.c
@@ -54,3 +54,135 @@ void *igt_amd_mmap_bo(int fd, uint32_t handle, uint64_t size, int prot)
 	ptr = mmap(0, size, prot, MAP_SHARED, fd, map.out.addr_ptr);
 	return ptr == MAP_FAILED ? NULL : ptr;
 }
+
+unsigned int igt_amd_compute_offset(unsigned int* swizzle_pattern, unsigned int x, unsigned int y)
+{
+    unsigned int offset = 0, index = 0, blk_size_table_index = 0, interleave = 0;
+    unsigned int channel[16] = {0, 0, 1, 1, 2, 2, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1};
+    unsigned int i, v;
+
+    for (i = 0; i < 16; i++)
+    {
+        v = 0;
+        if (channel[i] == 1)
+        {
+            blk_size_table_index = 0;
+            interleave = swizzle_pattern[i];
+
+            while (interleave > 1) {
+				blk_size_table_index++;
+				interleave = (interleave + 1) >> 1;
+			}
+
+            index = blk_size_table_index + 2;
+            v ^= (x >> index) & 1;
+        }
+        else if (channel[i] == 2)
+        {
+            blk_size_table_index = 0;
+            interleave = swizzle_pattern[i];
+
+            while (interleave > 1) {
+				blk_size_table_index++;
+				interleave = (interleave + 1) >> 1;
+			}
+
+            index = blk_size_table_index;
+            v ^= (y >> index) & 1;
+        }
+
+        offset |= (v << i);
+    }
+
+	return offset;
+}
+
+uint32_t igt_amd_fb_tiled_offset(unsigned int bpp, unsigned int x_input, unsigned int y_input,
+				       unsigned int width_input)
+{
+	unsigned int blk_size_table_index, blk_size_log2, blk_size_log2_256B;
+	unsigned int element_bytes, width_amp, height_amp, width, height, pitch;
+	unsigned int pb, yb, xb, blk_idx, blk_offset, addr;
+	unsigned int* swizzle_pattern;
+	unsigned int block256_2d[][2] = {{16, 16}, {16, 8}, {8, 8}, {8, 4}, {4, 4}};
+	unsigned int sw_64k_s[][16]=
+	{
+	    {X0, X1, X2, X3, Y0, Y1, Y2, Y3, Y4, X4, Y5, X5, Y6, X6, Y7, X7},
+	    {0,  X0, X1, X2, Y0, Y1, Y2, X3, Y3, X4, Y4, X5, Y5, X6, Y6, X7},
+	    {0,  0,  X0, X1, Y0, Y1, Y2, X2, Y3, X3, Y4, X4, Y5, X5, Y6, X6},
+	    {0,  0,  0,  X0, Y0, Y1, X1, X2, Y2, X3, Y3, X4, Y4, X5, Y5, X6},
+	    {0,  0,  0,  0,  Y0, Y1, X0, X1, Y2, X2, Y3, X3, Y4, X4, Y5, X5},
+	};
+
+	element_bytes = bpp >> 3;
+	blk_size_table_index = 0;
+
+	while (element_bytes > 1) {
+		blk_size_table_index++;
+		element_bytes = (element_bytes + 1) >> 1;
+	}
+
+	blk_size_log2 = 16;
+	blk_size_log2_256B = blk_size_log2 - 8;
+
+	width_amp = blk_size_log2_256B / 2;
+	height_amp = blk_size_log2_256B - width_amp;
+
+	width  = (block256_2d[blk_size_table_index][0] << width_amp);
+	height = (block256_2d[blk_size_table_index][1] << height_amp);
+
+	pitch = (width_input + (width - 1)) & (~(width - 1));
+
+	swizzle_pattern = sw_64k_s[blk_size_table_index];
+
+	pb = pitch / width;
+	yb = y_input / height;
+	xb = x_input / width;
+	blk_idx = yb * pb + xb;
+	blk_offset = igt_amd_compute_offset(swizzle_pattern,
+					x_input << blk_size_table_index, y_input);
+	addr = (blk_idx << blk_size_log2) + blk_offset;
+
+    return (uint32_t)addr;
+}
+
+void igt_amd_fb_to_tiled(struct igt_fb *dst, void *dst_buf, struct igt_fb *src,
+				       void *src_buf, unsigned int plane)
+{
+	uint32_t src_offset, dst_offset;
+	unsigned int bpp = src->plane_bpp[plane];
+	unsigned int width = dst->plane_width[plane];
+	unsigned int height = dst->plane_height[plane];
+	unsigned int x, y;
+
+	for (y = 0; y < height; y++) {
+		for (x = 0; x < width; x++) {
+			src_offset = src->offsets[plane];
+			dst_offset = dst->offsets[plane];
+
+			src_offset += src->strides[plane] * y + x * bpp / 8;
+			dst_offset += igt_amd_fb_tiled_offset(bpp, x, y, width);
+
+			switch (bpp) {
+			case 16:
+				*(uint16_t *)(dst_buf + dst_offset) =
+					*(uint16_t *)(src_buf + src_offset);
+				break;
+			case 32:
+				*(uint32_t *)(dst_buf + dst_offset) =
+					*(uint32_t *)(src_buf + src_offset);
+				break;
+			}
+		}
+	}
+}
+
+void igt_amd_fb_convert_plane_to_tiled(struct igt_fb *dst, void *dst_buf,
+				       struct igt_fb *src, void *src_buf)
+{
+	unsigned int plane;
+
+	for (plane = 0; plane < src->num_planes; plane++) {
+		igt_amd_fb_to_tiled(dst, dst_buf, src, src_buf, plane);
+	}
+}
diff --git a/lib/igt_amd.h b/lib/igt_amd.h
index f63d26f4..d5b421b4 100644
--- a/lib/igt_amd.h
+++ b/lib/igt_amd.h
@@ -24,8 +24,39 @@
 #define IGT_AMD_H
 
 #include <stdint.h>
+#include "igt_fb.h"
 
 uint32_t igt_amd_create_bo(int fd, uint64_t size);
 void *igt_amd_mmap_bo(int fd, uint32_t handle, uint64_t size, int prot);
+unsigned int igt_amd_compute_offset(unsigned int* SwizzlePattern, unsigned int x, unsigned int y);
+uint32_t igt_amd_fb_tiled_offset(unsigned int bpp, unsigned int x_input, unsigned int y_input,
+				       unsigned int width_input);
+void igt_amd_fb_to_tiled(struct igt_fb *dst, void *dst_buf, struct igt_fb *src,
+				       void *src_buf, unsigned int plane);
+void igt_amd_fb_convert_plane_to_tiled(struct igt_fb *dst, void *dst_buf,
+				       struct igt_fb *src, void *src_buf);
+
+#define X0 1
+#define X1 2
+#define X2 4
+#define X3 8
+#define X4 16
+#define X5 32
+#define X6 64
+#define X7 128
+#define Y0 1
+#define Y1 2
+#define Y2 4
+#define Y3 8
+#define Y4 16
+#define Y5 32
+#define Y6 64
+#define Y7 128
+
+struct Dim2d
+{
+    int w;
+    int h;
+};
 
 #endif /* IGT_AMD_H */
-- 
2.25.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] [PATCH 1/3] lib: Add stride and size calculation for amdgpu + tiling

[Sung Joon Kim]

For amdgpu, we need to calculate the stride and size of framebuffer correctly during non-linear tiling mode

v2: add call to amdgpu tiling/swizzle addressing
Signed-off-by: Sung Joon Kim <sungkim@amd.com>
---
 lib/igt_fb.c | 24 +++++++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 4b9be47e..6eebe048 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -671,6 +671,11 @@ static uint32_t calc_plane_stride(struct igt_fb *fb, int plane)
 		 * so the easiest way is to align the luma stride to 256.
 		 */
 		return ALIGN(min_stride, 256);
+	}else if (fb->modifier != LOCAL_DRM_FORMAT_MOD_NONE && is_amdgpu_device(fb->fd)) {
+		/*
+		 * For amdgpu device with tiling mode
+		 */
+		return ALIGN(min_stride, 512);
 	} else if (is_gen12_ccs_cc_plane(fb, plane)) {
 		/* clear color always fixed to 64 bytes */
 		return 64;
@@ -711,6 +716,12 @@ static uint64_t calc_plane_size(struct igt_fb *fb, int plane)
 		size = roundup_power_of_two(size);
 
 		return size;
+	} else if (fb->modifier != LOCAL_DRM_FORMAT_MOD_NONE && is_amdgpu_device(fb->fd)) {
+		/*
+		 * For amdgpu device with tiling mode
+		 */
+		return (uint64_t) fb->strides[plane] *
+			ALIGN(fb->plane_height[plane], 512);
 	} else if (is_gen12_ccs_plane(fb, plane)) {
 		/* The AUX CCS surface must be page aligned */
 		return (uint64_t)fb->strides[plane] *
@@ -2352,6 +2363,13 @@ static void free_linear_mapping(struct fb_blit_upload *blit)
 
 		vc4_fb_convert_plane_to_tiled(fb, map, &linear->fb, &linear->map);
 
+		munmap(map, fb->size);
+	} else if (is_amdgpu_device(fd) && fb->modifier != 0) {
+		void *map = igt_amd_mmap_bo(fd, fb->gem_handle, fb->size, PROT_WRITE);
+
+		igt_amd_fb_convert_plane_to_tiled(fb, map, &linear->fb, linear->map);
+
+		munmap(linear->map, fb->size);
 		munmap(map, fb->size);
 	} else {
 		gem_munmap(linear->map, linear->fb.size);
@@ -2419,6 +2437,10 @@ static void setup_linear_mapping(struct fb_blit_upload *blit)
 		vc4_fb_convert_plane_from_tiled(&linear->fb, &linear->map, fb, map);
 
 		munmap(map, fb->size);
+	} else if (is_amdgpu_device(fd) && fb->modifier != 0) {
+		linear->map = igt_amd_mmap_bo(fd, linear->fb.gem_handle,
+					      linear->fb.size,
+					      PROT_READ | PROT_WRITE);
 	} else {
 		/* Copy fb content to linear BO */
 		gem_set_domain(fd, linear->fb.gem_handle,
@@ -3625,7 +3647,7 @@ cairo_surface_t *igt_get_cairo_surface(int fd, struct igt_fb *fb)
 		if (use_convert(fb))
 			create_cairo_surface__convert(fd, fb);
 		else if (use_blitter(fb) || use_enginecopy(fb) ||
-			 igt_vc4_is_tiled(fb->modifier))
+			 igt_vc4_is_tiled(fb->modifier) || (is_amdgpu_device(fd) && fb->modifier != 0))
 			create_cairo_surface__gpu(fd, fb);
 		else
 			create_cairo_surface__gtt(fd, fb);
-- 
2.25.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] [PATCH 3/3] lib: Implement tiling/swizzle addressing for amdgpu

[Sung Joon Kim]

The swizzle mode is 64kb withe standard pattern.

Signed-off-by: Sung Joon Kim <sungkim@amd.com>
---
 lib/igt_amd.c | 132 ++++++++++++++++++++++++++++++++++++++++++++++++++
 lib/igt_amd.h |  31 ++++++++++++
 2 files changed, 163 insertions(+)

diff --git a/lib/igt_amd.c b/lib/igt_amd.c
index abd3ad96..737e5670 100644
--- a/lib/igt_amd.c
+++ b/lib/igt_amd.c
@@ -54,3 +54,135 @@ void *igt_amd_mmap_bo(int fd, uint32_t handle, uint64_t size, int prot)
 	ptr = mmap(0, size, prot, MAP_SHARED, fd, map.out.addr_ptr);
 	return ptr == MAP_FAILED ? NULL : ptr;
 }
+
+unsigned int igt_amd_compute_offset(unsigned int* swizzle_pattern, unsigned int x, unsigned int y)
+{
+    unsigned int offset = 0, index = 0, blk_size_table_index = 0, interleave = 0;
+    unsigned int channel[16] = {0, 0, 1, 1, 2, 2, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1};
+    unsigned int i, v;
+
+    for (i = 0; i < 16; i++)
+    {
+        v = 0;
+        if (channel[i] == 1)
+        {
+            blk_size_table_index = 0;
+            interleave = swizzle_pattern[i];
+
+            while (interleave > 1) {
+				blk_size_table_index++;
+				interleave = (interleave + 1) >> 1;
+			}
+
+            index = blk_size_table_index + 2;
+            v ^= (x >> index) & 1;
+        }
+        else if (channel[i] == 2)
+        {
+            blk_size_table_index = 0;
+            interleave = swizzle_pattern[i];
+
+            while (interleave > 1) {
+				blk_size_table_index++;
+				interleave = (interleave + 1) >> 1;
+			}
+
+            index = blk_size_table_index;
+            v ^= (y >> index) & 1;
+        }
+
+        offset |= (v << i);
+    }
+
+	return offset;
+}
+
+uint32_t igt_amd_fb_tiled_offset(unsigned int bpp, unsigned int x_input, unsigned int y_input,
+				       unsigned int width_input)
+{
+	unsigned int blk_size_table_index, blk_size_log2, blk_size_log2_256B;
+	unsigned int element_bytes, width_amp, height_amp, width, height, pitch;
+	unsigned int pb, yb, xb, blk_idx, blk_offset, addr;
+	unsigned int* swizzle_pattern;
+	unsigned int block256_2d[][2] = {{16, 16}, {16, 8}, {8, 8}, {8, 4}, {4, 4}};
+	unsigned int sw_64k_s[][16]=
+	{
+	    {X0, X1, X2, X3, Y0, Y1, Y2, Y3, Y4, X4, Y5, X5, Y6, X6, Y7, X7},
+	    {0,  X0, X1, X2, Y0, Y1, Y2, X3, Y3, X4, Y4, X5, Y5, X6, Y6, X7},
+	    {0,  0,  X0, X1, Y0, Y1, Y2, X2, Y3, X3, Y4, X4, Y5, X5, Y6, X6},
+	    {0,  0,  0,  X0, Y0, Y1, X1, X2, Y2, X3, Y3, X4, Y4, X5, Y5, X6},
+	    {0,  0,  0,  0,  Y0, Y1, X0, X1, Y2, X2, Y3, X3, Y4, X4, Y5, X5},
+	};
+
+	element_bytes = bpp >> 3;
+	blk_size_table_index = 0;
+
+	while (element_bytes > 1) {
+		blk_size_table_index++;
+		element_bytes = (element_bytes + 1) >> 1;
+	}
+
+	blk_size_log2 = 16;
+	blk_size_log2_256B = blk_size_log2 - 8;
+
+	width_amp = blk_size_log2_256B / 2;
+	height_amp = blk_size_log2_256B - width_amp;
+
+	width  = (block256_2d[blk_size_table_index][0] << width_amp);
+	height = (block256_2d[blk_size_table_index][1] << height_amp);
+
+	pitch = (width_input + (width - 1)) & (~(width - 1));
+
+	swizzle_pattern = sw_64k_s[blk_size_table_index];
+
+	pb = pitch / width;
+	yb = y_input / height;
+	xb = x_input / width;
+	blk_idx = yb * pb + xb;
+	blk_offset = igt_amd_compute_offset(swizzle_pattern,
+					x_input << blk_size_table_index, y_input);
+	addr = (blk_idx << blk_size_log2) + blk_offset;
+
+    return (uint32_t)addr;
+}
+
+void igt_amd_fb_to_tiled(struct igt_fb *dst, void *dst_buf, struct igt_fb *src,
+				       void *src_buf, unsigned int plane)
+{
+	uint32_t src_offset, dst_offset;
+	unsigned int bpp = src->plane_bpp[plane];
+	unsigned int width = dst->plane_width[plane];
+	unsigned int height = dst->plane_height[plane];
+	unsigned int x, y;
+
+	for (y = 0; y < height; y++) {
+		for (x = 0; x < width; x++) {
+			src_offset = src->offsets[plane];
+			dst_offset = dst->offsets[plane];
+
+			src_offset += src->strides[plane] * y + x * bpp / 8;
+			dst_offset += igt_amd_fb_tiled_offset(bpp, x, y, width);
+
+			switch (bpp) {
+			case 16:
+				*(uint16_t *)(dst_buf + dst_offset) =
+					*(uint16_t *)(src_buf + src_offset);
+				break;
+			case 32:
+				*(uint32_t *)(dst_buf + dst_offset) =
+					*(uint32_t *)(src_buf + src_offset);
+				break;
+			}
+		}
+	}
+}
+
+void igt_amd_fb_convert_plane_to_tiled(struct igt_fb *dst, void *dst_buf,
+				       struct igt_fb *src, void *src_buf)
+{
+	unsigned int plane;
+
+	for (plane = 0; plane < src->num_planes; plane++) {
+		igt_amd_fb_to_tiled(dst, dst_buf, src, src_buf, plane);
+	}
+}
diff --git a/lib/igt_amd.h b/lib/igt_amd.h
index f63d26f4..d5b421b4 100644
--- a/lib/igt_amd.h
+++ b/lib/igt_amd.h
@@ -24,8 +24,39 @@
 #define IGT_AMD_H
 
 #include <stdint.h>
+#include "igt_fb.h"
 
 uint32_t igt_amd_create_bo(int fd, uint64_t size);
 void *igt_amd_mmap_bo(int fd, uint32_t handle, uint64_t size, int prot);
+unsigned int igt_amd_compute_offset(unsigned int* SwizzlePattern, unsigned int x, unsigned int y);
+uint32_t igt_amd_fb_tiled_offset(unsigned int bpp, unsigned int x_input, unsigned int y_input,
+				       unsigned int width_input);
+void igt_amd_fb_to_tiled(struct igt_fb *dst, void *dst_buf, struct igt_fb *src,
+				       void *src_buf, unsigned int plane);
+void igt_amd_fb_convert_plane_to_tiled(struct igt_fb *dst, void *dst_buf,
+				       struct igt_fb *src, void *src_buf);
+
+#define X0 1
+#define X1 2
+#define X2 4
+#define X3 8
+#define X4 16
+#define X5 32
+#define X6 64
+#define X7 128
+#define Y0 1
+#define Y1 2
+#define Y2 4
+#define Y3 8
+#define Y4 16
+#define Y5 32
+#define Y6 64
+#define Y7 128
+
+struct Dim2d
+{
+    int w;
+    int h;
+};
 
 #endif /* IGT_AMD_H */
-- 
2.25.1

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[igt-dev] [PATCH 1/3] lib: Add stride and size calculation for amdgpu + tiling

[Sung Joon Kim]

For amdgpu, we need to calculate the stride and size of framebuffer correctly during non-linear tiling mode

v2: add call to amdgpu tiling/swizzle addressing
Signed-off-by: Sung Joon Kim <sungkim@amd.com>
---
 lib/igt_fb.c | 24 +++++++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 422a9e06..143d6785 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -670,6 +670,11 @@ static uint32_t calc_plane_stride(struct igt_fb *fb, int plane)
 		 * so the easiest way is to align the luma stride to 256.
 		 */
 		return ALIGN(min_stride, 256);
+	} else if (fb->modifier != LOCAL_DRM_FORMAT_MOD_NONE && is_amdgpu_device(fb->fd)) {
+		/*
+		 * For amdgpu device with tiling mode
+		 */
+		return ALIGN(min_stride, 512);
 	} else if (is_gen12_ccs_cc_plane(fb, plane)) {
 		/* clear color always fixed to 64 bytes */
 		return 64;
@@ -710,6 +715,12 @@ static uint64_t calc_plane_size(struct igt_fb *fb, int plane)
 		size = roundup_power_of_two(size);
 
 		return size;
+	} else if (fb->modifier != LOCAL_DRM_FORMAT_MOD_NONE && is_amdgpu_device(fb->fd)) {
+		/*
+		 * For amdgpu device with tiling mode
+		 */
+		return (uint64_t) fb->strides[plane] *
+			ALIGN(fb->plane_height[plane], 512);
 	} else if (is_gen12_ccs_plane(fb, plane)) {
 		/* The AUX CCS surface must be page aligned */
 		return (uint64_t)fb->strides[plane] *
@@ -2351,6 +2362,13 @@ static void free_linear_mapping(struct fb_blit_upload *blit)
 
 		vc4_fb_convert_plane_to_tiled(fb, map, &linear->fb, &linear->map);
 
+		munmap(map, fb->size);
+	} else if (is_amdgpu_device(fd) && fb->modifier != 0) {
+		void *map = igt_amd_mmap_bo(fd, fb->gem_handle, fb->size, PROT_WRITE);
+
+		igt_amd_fb_convert_plane_to_tiled(fb, map, &linear->fb, linear->map);
+
+		munmap(linear->map, fb->size);
 		munmap(map, fb->size);
 	} else {
 		gem_munmap(linear->map, linear->fb.size);
@@ -2418,6 +2436,10 @@ static void setup_linear_mapping(struct fb_blit_upload *blit)
 		vc4_fb_convert_plane_from_tiled(&linear->fb, &linear->map, fb, map);
 
 		munmap(map, fb->size);
+	} else if (is_amdgpu_device(fd) && fb->modifier != 0) {
+		linear->map = igt_amd_mmap_bo(fd, linear->fb.gem_handle,
+					      linear->fb.size,
+					      PROT_READ | PROT_WRITE);
 	} else {
 		/* Copy fb content to linear BO */
 		gem_set_domain(fd, linear->fb.gem_handle,
@@ -3624,7 +3646,7 @@ cairo_surface_t *igt_get_cairo_surface(int fd, struct igt_fb *fb)
 		if (use_convert(fb))
 			create_cairo_surface__convert(fd, fb);
 		else if (use_blitter(fb) || use_enginecopy(fb) ||
-			 igt_vc4_is_tiled(fb->modifier))
+			 igt_vc4_is_tiled(fb->modifier) || (is_amdgpu_device(fd) && fb->modifier != 0))
 			create_cairo_surface__gpu(fd, fb);
 		else
 			create_cairo_surface__gtt(fd, fb);
-- 
2.25.1

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[igt-dev] [PATCH 3/3] lib: Implement tiling/swizzle addressing for amdgpu

[Sung Joon Kim]

The swizzle mode is 64kb withe standard pattern.

Signed-off-by: Sung Joon Kim <sungkim@amd.com>
---
 lib/igt_amd.c | 132 ++++++++++++++++++++++++++++++++++++++++++++++++++
 lib/igt_amd.h |  31 ++++++++++++
 2 files changed, 163 insertions(+)

diff --git a/lib/igt_amd.c b/lib/igt_amd.c
index abd3ad96..737e5670 100644
--- a/lib/igt_amd.c
+++ b/lib/igt_amd.c
@@ -54,3 +54,135 @@ void *igt_amd_mmap_bo(int fd, uint32_t handle, uint64_t size, int prot)
 	ptr = mmap(0, size, prot, MAP_SHARED, fd, map.out.addr_ptr);
 	return ptr == MAP_FAILED ? NULL : ptr;
 }
+
+unsigned int igt_amd_compute_offset(unsigned int* swizzle_pattern, unsigned int x, unsigned int y)
+{
+    unsigned int offset = 0, index = 0, blk_size_table_index = 0, interleave = 0;
+    unsigned int channel[16] = {0, 0, 1, 1, 2, 2, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1};
+    unsigned int i, v;
+
+    for (i = 0; i < 16; i++)
+    {
+        v = 0;
+        if (channel[i] == 1)
+        {
+            blk_size_table_index = 0;
+            interleave = swizzle_pattern[i];
+
+            while (interleave > 1) {
+				blk_size_table_index++;
+				interleave = (interleave + 1) >> 1;
+			}
+
+            index = blk_size_table_index + 2;
+            v ^= (x >> index) & 1;
+        }
+        else if (channel[i] == 2)
+        {
+            blk_size_table_index = 0;
+            interleave = swizzle_pattern[i];
+
+            while (interleave > 1) {
+				blk_size_table_index++;
+				interleave = (interleave + 1) >> 1;
+			}
+
+            index = blk_size_table_index;
+            v ^= (y >> index) & 1;
+        }
+
+        offset |= (v << i);
+    }
+
+	return offset;
+}
+
+uint32_t igt_amd_fb_tiled_offset(unsigned int bpp, unsigned int x_input, unsigned int y_input,
+				       unsigned int width_input)
+{
+	unsigned int blk_size_table_index, blk_size_log2, blk_size_log2_256B;
+	unsigned int element_bytes, width_amp, height_amp, width, height, pitch;
+	unsigned int pb, yb, xb, blk_idx, blk_offset, addr;
+	unsigned int* swizzle_pattern;
+	unsigned int block256_2d[][2] = {{16, 16}, {16, 8}, {8, 8}, {8, 4}, {4, 4}};
+	unsigned int sw_64k_s[][16]=
+	{
+	    {X0, X1, X2, X3, Y0, Y1, Y2, Y3, Y4, X4, Y5, X5, Y6, X6, Y7, X7},
+	    {0,  X0, X1, X2, Y0, Y1, Y2, X3, Y3, X4, Y4, X5, Y5, X6, Y6, X7},
+	    {0,  0,  X0, X1, Y0, Y1, Y2, X2, Y3, X3, Y4, X4, Y5, X5, Y6, X6},
+	    {0,  0,  0,  X0, Y0, Y1, X1, X2, Y2, X3, Y3, X4, Y4, X5, Y5, X6},
+	    {0,  0,  0,  0,  Y0, Y1, X0, X1, Y2, X2, Y3, X3, Y4, X4, Y5, X5},
+	};
+
+	element_bytes = bpp >> 3;
+	blk_size_table_index = 0;
+
+	while (element_bytes > 1) {
+		blk_size_table_index++;
+		element_bytes = (element_bytes + 1) >> 1;
+	}
+
+	blk_size_log2 = 16;
+	blk_size_log2_256B = blk_size_log2 - 8;
+
+	width_amp = blk_size_log2_256B / 2;
+	height_amp = blk_size_log2_256B - width_amp;
+
+	width  = (block256_2d[blk_size_table_index][0] << width_amp);
+	height = (block256_2d[blk_size_table_index][1] << height_amp);
+
+	pitch = (width_input + (width - 1)) & (~(width - 1));
+
+	swizzle_pattern = sw_64k_s[blk_size_table_index];
+
+	pb = pitch / width;
+	yb = y_input / height;
+	xb = x_input / width;
+	blk_idx = yb * pb + xb;
+	blk_offset = igt_amd_compute_offset(swizzle_pattern,
+					x_input << blk_size_table_index, y_input);
+	addr = (blk_idx << blk_size_log2) + blk_offset;
+
+    return (uint32_t)addr;
+}
+
+void igt_amd_fb_to_tiled(struct igt_fb *dst, void *dst_buf, struct igt_fb *src,
+				       void *src_buf, unsigned int plane)
+{
+	uint32_t src_offset, dst_offset;
+	unsigned int bpp = src->plane_bpp[plane];
+	unsigned int width = dst->plane_width[plane];
+	unsigned int height = dst->plane_height[plane];
+	unsigned int x, y;
+
+	for (y = 0; y < height; y++) {
+		for (x = 0; x < width; x++) {
+			src_offset = src->offsets[plane];
+			dst_offset = dst->offsets[plane];
+
+			src_offset += src->strides[plane] * y + x * bpp / 8;
+			dst_offset += igt_amd_fb_tiled_offset(bpp, x, y, width);
+
+			switch (bpp) {
+			case 16:
+				*(uint16_t *)(dst_buf + dst_offset) =
+					*(uint16_t *)(src_buf + src_offset);
+				break;
+			case 32:
+				*(uint32_t *)(dst_buf + dst_offset) =
+					*(uint32_t *)(src_buf + src_offset);
+				break;
+			}
+		}
+	}
+}
+
+void igt_amd_fb_convert_plane_to_tiled(struct igt_fb *dst, void *dst_buf,
+				       struct igt_fb *src, void *src_buf)
+{
+	unsigned int plane;
+
+	for (plane = 0; plane < src->num_planes; plane++) {
+		igt_amd_fb_to_tiled(dst, dst_buf, src, src_buf, plane);
+	}
+}
diff --git a/lib/igt_amd.h b/lib/igt_amd.h
index f63d26f4..d5b421b4 100644
--- a/lib/igt_amd.h
+++ b/lib/igt_amd.h
@@ -24,8 +24,39 @@
 #define IGT_AMD_H
 
 #include <stdint.h>
+#include "igt_fb.h"
 
 uint32_t igt_amd_create_bo(int fd, uint64_t size);
 void *igt_amd_mmap_bo(int fd, uint32_t handle, uint64_t size, int prot);
+unsigned int igt_amd_compute_offset(unsigned int* SwizzlePattern, unsigned int x, unsigned int y);
+uint32_t igt_amd_fb_tiled_offset(unsigned int bpp, unsigned int x_input, unsigned int y_input,
+				       unsigned int width_input);
+void igt_amd_fb_to_tiled(struct igt_fb *dst, void *dst_buf, struct igt_fb *src,
+				       void *src_buf, unsigned int plane);
+void igt_amd_fb_convert_plane_to_tiled(struct igt_fb *dst, void *dst_buf,
+				       struct igt_fb *src, void *src_buf);
+
+#define X0 1
+#define X1 2
+#define X2 4
+#define X3 8
+#define X4 16
+#define X5 32
+#define X6 64
+#define X7 128
+#define Y0 1
+#define Y1 2
+#define Y2 4
+#define Y3 8
+#define Y4 16
+#define Y5 32
+#define Y6 64
+#define Y7 128
+
+struct Dim2d
+{
+    int w;
+    int h;
+};
 
 #endif /* IGT_AMD_H */
-- 
2.25.1

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