From: Michael Tretter <m.tretter@pengutronix.de> To: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Cc: m.mtretter@pengutronix.de, michals@xilinx.com, kernel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org Subject: [PATCH v3 00/15] soc: xilinx: vcu: Convert driver to clock provider Date: Thu, 21 Jan 2021 08:16:44 +0100 [thread overview] Message-ID: <20210121071659.1226489-1-m.tretter@pengutronix.de> (raw) Hello, This is v3 of the series to transform the xlnx_vcu driver into a proper clock provider driver. The driver implements a clock provider of a PLL and four output clocks created from the PLL via dividers that are used by the Xilinx Video Codec Unit. Compared to v2, I added a missing kernel-doc, collected Acked-By: tags, and rebased it on clk-next. Michael Changelog: v3: - Add missing kernel-doc v2: - Remove dummy clock and explicit re-parenting of mux clocks - Add patches to fix checkpatch warnings - Move driver from drivers/soc to drivers/clk - Use clk_parent_data instead of parent_names - Add missing decoder clocks - Fix smatch warnings - Fix kernel-doc Michael Tretter (15): ARM: dts: vcu: define indexes for output clocks clk: divider: fix initialization with parent_hw soc: xilinx: vcu: drop coreclk from struct xlnx_vcu soc: xilinx: vcu: add helper to wait for PLL locked soc: xilinx: vcu: add helpers for configuring PLL soc: xilinx: vcu: implement PLL disable soc: xilinx: vcu: register PLL as fixed rate clock soc: xilinx: vcu: implement clock provider for output clocks soc: xilinx: vcu: make pll post divider explicit soc: xilinx: vcu: make the PLL configurable soc: xilinx: vcu: remove calculation of PLL configuration soc: xilinx: vcu: use bitfields for register definition soc: xilinx: vcu: fix repeated word the in comment soc: xilinx: vcu: fix alignment to open parenthesis clk: xilinx: move xlnx_vcu clock driver from soc drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/clk-divider.c | 9 +- drivers/clk/xilinx/Kconfig | 19 + drivers/clk/xilinx/Makefile | 2 + drivers/clk/xilinx/xlnx_vcu.c | 743 +++++++++++++++++++++++++++ drivers/soc/xilinx/Kconfig | 17 - drivers/soc/xilinx/Makefile | 1 - drivers/soc/xilinx/xlnx_vcu.c | 628 ---------------------- include/dt-bindings/clock/xlnx-vcu.h | 15 + 10 files changed, 788 insertions(+), 648 deletions(-) create mode 100644 drivers/clk/xilinx/Kconfig create mode 100644 drivers/clk/xilinx/Makefile create mode 100644 drivers/clk/xilinx/xlnx_vcu.c delete mode 100644 drivers/soc/xilinx/xlnx_vcu.c create mode 100644 include/dt-bindings/clock/xlnx-vcu.h -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Michael Tretter <m.tretter@pengutronix.de> To: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Cc: sboyd@kernel.org, mturquette@baylibre.com, m.mtretter@pengutronix.de, michals@xilinx.com, kernel@pengutronix.de Subject: [PATCH v3 00/15] soc: xilinx: vcu: Convert driver to clock provider Date: Thu, 21 Jan 2021 08:16:44 +0100 [thread overview] Message-ID: <20210121071659.1226489-1-m.tretter@pengutronix.de> (raw) Hello, This is v3 of the series to transform the xlnx_vcu driver into a proper clock provider driver. The driver implements a clock provider of a PLL and four output clocks created from the PLL via dividers that are used by the Xilinx Video Codec Unit. Compared to v2, I added a missing kernel-doc, collected Acked-By: tags, and rebased it on clk-next. Michael Changelog: v3: - Add missing kernel-doc v2: - Remove dummy clock and explicit re-parenting of mux clocks - Add patches to fix checkpatch warnings - Move driver from drivers/soc to drivers/clk - Use clk_parent_data instead of parent_names - Add missing decoder clocks - Fix smatch warnings - Fix kernel-doc Michael Tretter (15): ARM: dts: vcu: define indexes for output clocks clk: divider: fix initialization with parent_hw soc: xilinx: vcu: drop coreclk from struct xlnx_vcu soc: xilinx: vcu: add helper to wait for PLL locked soc: xilinx: vcu: add helpers for configuring PLL soc: xilinx: vcu: implement PLL disable soc: xilinx: vcu: register PLL as fixed rate clock soc: xilinx: vcu: implement clock provider for output clocks soc: xilinx: vcu: make pll post divider explicit soc: xilinx: vcu: make the PLL configurable soc: xilinx: vcu: remove calculation of PLL configuration soc: xilinx: vcu: use bitfields for register definition soc: xilinx: vcu: fix repeated word the in comment soc: xilinx: vcu: fix alignment to open parenthesis clk: xilinx: move xlnx_vcu clock driver from soc drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/clk-divider.c | 9 +- drivers/clk/xilinx/Kconfig | 19 + drivers/clk/xilinx/Makefile | 2 + drivers/clk/xilinx/xlnx_vcu.c | 743 +++++++++++++++++++++++++++ drivers/soc/xilinx/Kconfig | 17 - drivers/soc/xilinx/Makefile | 1 - drivers/soc/xilinx/xlnx_vcu.c | 628 ---------------------- include/dt-bindings/clock/xlnx-vcu.h | 15 + 10 files changed, 788 insertions(+), 648 deletions(-) create mode 100644 drivers/clk/xilinx/Kconfig create mode 100644 drivers/clk/xilinx/Makefile create mode 100644 drivers/clk/xilinx/xlnx_vcu.c delete mode 100644 drivers/soc/xilinx/xlnx_vcu.c create mode 100644 include/dt-bindings/clock/xlnx-vcu.h -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next reply other threads:[~2021-01-21 7:18 UTC|newest] Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-01-21 7:16 Michael Tretter [this message] 2021-01-21 7:16 ` [PATCH v3 00/15] soc: xilinx: vcu: Convert driver to clock provider Michael Tretter 2021-01-21 7:16 ` [PATCH v3 01/15] ARM: dts: vcu: define indexes for output clocks Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:32 ` Stephen Boyd 2021-02-09 2:32 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 02/15] clk: divider: fix initialization with parent_hw Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:32 ` Stephen Boyd 2021-02-09 2:32 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 03/15] soc: xilinx: vcu: drop coreclk from struct xlnx_vcu Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:32 ` Stephen Boyd 2021-02-09 2:32 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 04/15] soc: xilinx: vcu: add helper to wait for PLL locked Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:32 ` Stephen Boyd 2021-02-09 2:32 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 05/15] soc: xilinx: vcu: add helpers for configuring PLL Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:32 ` Stephen Boyd 2021-02-09 2:32 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 06/15] soc: xilinx: vcu: implement PLL disable Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:32 ` Stephen Boyd 2021-02-09 2:32 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 07/15] soc: xilinx: vcu: register PLL as fixed rate clock Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:32 ` Stephen Boyd 2021-02-09 2:32 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 08/15] soc: xilinx: vcu: implement clock provider for output clocks Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:35 ` Stephen Boyd 2021-02-09 2:35 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 09/15] soc: xilinx: vcu: make pll post divider explicit Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:35 ` Stephen Boyd 2021-02-09 2:35 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 10/15] soc: xilinx: vcu: make the PLL configurable Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:35 ` Stephen Boyd 2021-02-09 2:35 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 11/15] soc: xilinx: vcu: remove calculation of PLL configuration Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:35 ` Stephen Boyd 2021-02-09 2:35 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 12/15] soc: xilinx: vcu: use bitfields for register definition Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:35 ` Stephen Boyd 2021-02-09 2:35 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 13/15] soc: xilinx: vcu: fix repeated word the in comment Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:35 ` Stephen Boyd 2021-02-09 2:35 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 14/15] soc: xilinx: vcu: fix alignment to open parenthesis Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:35 ` Stephen Boyd 2021-02-09 2:35 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 15/15] clk: xilinx: move xlnx_vcu clock driver from soc Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:35 ` Stephen Boyd 2021-02-09 2:35 ` Stephen Boyd
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