From: Michael Tretter <m.tretter@pengutronix.de> To: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Cc: m.mtretter@pengutronix.de, michals@xilinx.com, kernel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org Subject: [PATCH v3 15/15] clk: xilinx: move xlnx_vcu clock driver from soc Date: Thu, 21 Jan 2021 08:16:59 +0100 [thread overview] Message-ID: <20210121071659.1226489-16-m.tretter@pengutronix.de> (raw) In-Reply-To: <20210121071659.1226489-1-m.tretter@pengutronix.de> The xlnx_vcu driver is actually a clock controller driver which provides clocks that can be used by a driver for the encoder/decoder units. There is no reason to keep this driver in soc. Move the driver to clk. NOTE: The register mapping actually contains registers for AXI performance monitoring, but these are not used by the driver. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Acked-by: Michal Simek <michal.simek@xilinx.com> --- Changelog: v3: none v2: - New patch --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/xilinx/Kconfig | 19 +++++++++++++++++++ drivers/clk/xilinx/Makefile | 2 ++ drivers/{soc => clk}/xilinx/xlnx_vcu.c | 0 drivers/soc/xilinx/Kconfig | 17 ----------------- drivers/soc/xilinx/Makefile | 1 - 7 files changed, 23 insertions(+), 18 deletions(-) create mode 100644 drivers/clk/xilinx/Kconfig create mode 100644 drivers/clk/xilinx/Makefile rename drivers/{soc => clk}/xilinx/xlnx_vcu.c (100%) diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 85856cff506c..7e066c25c698 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -392,6 +392,7 @@ source "drivers/clk/tegra/Kconfig" source "drivers/clk/ti/Kconfig" source "drivers/clk/uniphier/Kconfig" source "drivers/clk/x86/Kconfig" +source "drivers/clk/xilinx/Kconfig" source "drivers/clk/zynqmp/Kconfig" endif diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index dbdc590e7de3..074e2233f445 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -122,6 +122,7 @@ obj-y += versatile/ ifeq ($(CONFIG_COMMON_CLK), y) obj-$(CONFIG_X86) += x86/ endif +obj-y += xilinx/ obj-$(CONFIG_ARCH_ZX) += zte/ obj-$(CONFIG_ARCH_ZYNQ) += zynq/ obj-$(CONFIG_COMMON_CLK_ZYNQMP) += zynqmp/ diff --git a/drivers/clk/xilinx/Kconfig b/drivers/clk/xilinx/Kconfig new file mode 100644 index 000000000000..5224114176ed --- /dev/null +++ b/drivers/clk/xilinx/Kconfig @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0 + +config XILINX_VCU + tristate "Xilinx VCU logicoreIP Init" + depends on HAS_IOMEM && COMMON_CLK + select REGMAP_MMIO + help + Provides the driver to enable and disable the isolation between the + processing system and programmable logic part by using the logicoreIP + register set. This driver also configures the frequency based on the + clock information from the logicoreIP register set. + + If you say yes here you get support for the logicoreIP. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called xlnx_vcu. + diff --git a/drivers/clk/xilinx/Makefile b/drivers/clk/xilinx/Makefile new file mode 100644 index 000000000000..dee8fd51e303 --- /dev/null +++ b/drivers/clk/xilinx/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_XILINX_VCU) += xlnx_vcu.o diff --git a/drivers/soc/xilinx/xlnx_vcu.c b/drivers/clk/xilinx/xlnx_vcu.c similarity index 100% rename from drivers/soc/xilinx/xlnx_vcu.c rename to drivers/clk/xilinx/xlnx_vcu.c diff --git a/drivers/soc/xilinx/Kconfig b/drivers/soc/xilinx/Kconfig index 9fe703772e5a..53af9115dc31 100644 --- a/drivers/soc/xilinx/Kconfig +++ b/drivers/soc/xilinx/Kconfig @@ -1,23 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 menu "Xilinx SoC drivers" -config XILINX_VCU - tristate "Xilinx VCU logicoreIP Init" - depends on HAS_IOMEM && COMMON_CLK - select REGMAP_MMIO - help - Provides the driver to enable and disable the isolation between the - processing system and programmable logic part by using the logicoreIP - register set. This driver also configures the frequency based on the - clock information from the logicoreIP register set. - - If you say yes here you get support for the logicoreIP. - - If unsure, say N. - - To compile this driver as a module, choose M here: the - module will be called xlnx_vcu. - config ZYNQMP_POWER bool "Enable Xilinx Zynq MPSoC Power Management driver" depends on PM && ZYNQMP_FIRMWARE diff --git a/drivers/soc/xilinx/Makefile b/drivers/soc/xilinx/Makefile index f66bfea5de17..9854e6f6086b 100644 --- a/drivers/soc/xilinx/Makefile +++ b/drivers/soc/xilinx/Makefile @@ -1,4 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_XILINX_VCU) += xlnx_vcu.o obj-$(CONFIG_ZYNQMP_POWER) += zynqmp_power.o obj-$(CONFIG_ZYNQMP_PM_DOMAINS) += zynqmp_pm_domains.o -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Michael Tretter <m.tretter@pengutronix.de> To: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Cc: sboyd@kernel.org, mturquette@baylibre.com, m.mtretter@pengutronix.de, michals@xilinx.com, kernel@pengutronix.de Subject: [PATCH v3 15/15] clk: xilinx: move xlnx_vcu clock driver from soc Date: Thu, 21 Jan 2021 08:16:59 +0100 [thread overview] Message-ID: <20210121071659.1226489-16-m.tretter@pengutronix.de> (raw) In-Reply-To: <20210121071659.1226489-1-m.tretter@pengutronix.de> The xlnx_vcu driver is actually a clock controller driver which provides clocks that can be used by a driver for the encoder/decoder units. There is no reason to keep this driver in soc. Move the driver to clk. NOTE: The register mapping actually contains registers for AXI performance monitoring, but these are not used by the driver. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Acked-by: Michal Simek <michal.simek@xilinx.com> --- Changelog: v3: none v2: - New patch --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/xilinx/Kconfig | 19 +++++++++++++++++++ drivers/clk/xilinx/Makefile | 2 ++ drivers/{soc => clk}/xilinx/xlnx_vcu.c | 0 drivers/soc/xilinx/Kconfig | 17 ----------------- drivers/soc/xilinx/Makefile | 1 - 7 files changed, 23 insertions(+), 18 deletions(-) create mode 100644 drivers/clk/xilinx/Kconfig create mode 100644 drivers/clk/xilinx/Makefile rename drivers/{soc => clk}/xilinx/xlnx_vcu.c (100%) diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 85856cff506c..7e066c25c698 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -392,6 +392,7 @@ source "drivers/clk/tegra/Kconfig" source "drivers/clk/ti/Kconfig" source "drivers/clk/uniphier/Kconfig" source "drivers/clk/x86/Kconfig" +source "drivers/clk/xilinx/Kconfig" source "drivers/clk/zynqmp/Kconfig" endif diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index dbdc590e7de3..074e2233f445 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -122,6 +122,7 @@ obj-y += versatile/ ifeq ($(CONFIG_COMMON_CLK), y) obj-$(CONFIG_X86) += x86/ endif +obj-y += xilinx/ obj-$(CONFIG_ARCH_ZX) += zte/ obj-$(CONFIG_ARCH_ZYNQ) += zynq/ obj-$(CONFIG_COMMON_CLK_ZYNQMP) += zynqmp/ diff --git a/drivers/clk/xilinx/Kconfig b/drivers/clk/xilinx/Kconfig new file mode 100644 index 000000000000..5224114176ed --- /dev/null +++ b/drivers/clk/xilinx/Kconfig @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0 + +config XILINX_VCU + tristate "Xilinx VCU logicoreIP Init" + depends on HAS_IOMEM && COMMON_CLK + select REGMAP_MMIO + help + Provides the driver to enable and disable the isolation between the + processing system and programmable logic part by using the logicoreIP + register set. This driver also configures the frequency based on the + clock information from the logicoreIP register set. + + If you say yes here you get support for the logicoreIP. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called xlnx_vcu. + diff --git a/drivers/clk/xilinx/Makefile b/drivers/clk/xilinx/Makefile new file mode 100644 index 000000000000..dee8fd51e303 --- /dev/null +++ b/drivers/clk/xilinx/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_XILINX_VCU) += xlnx_vcu.o diff --git a/drivers/soc/xilinx/xlnx_vcu.c b/drivers/clk/xilinx/xlnx_vcu.c similarity index 100% rename from drivers/soc/xilinx/xlnx_vcu.c rename to drivers/clk/xilinx/xlnx_vcu.c diff --git a/drivers/soc/xilinx/Kconfig b/drivers/soc/xilinx/Kconfig index 9fe703772e5a..53af9115dc31 100644 --- a/drivers/soc/xilinx/Kconfig +++ b/drivers/soc/xilinx/Kconfig @@ -1,23 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 menu "Xilinx SoC drivers" -config XILINX_VCU - tristate "Xilinx VCU logicoreIP Init" - depends on HAS_IOMEM && COMMON_CLK - select REGMAP_MMIO - help - Provides the driver to enable and disable the isolation between the - processing system and programmable logic part by using the logicoreIP - register set. This driver also configures the frequency based on the - clock information from the logicoreIP register set. - - If you say yes here you get support for the logicoreIP. - - If unsure, say N. - - To compile this driver as a module, choose M here: the - module will be called xlnx_vcu. - config ZYNQMP_POWER bool "Enable Xilinx Zynq MPSoC Power Management driver" depends on PM && ZYNQMP_FIRMWARE diff --git a/drivers/soc/xilinx/Makefile b/drivers/soc/xilinx/Makefile index f66bfea5de17..9854e6f6086b 100644 --- a/drivers/soc/xilinx/Makefile +++ b/drivers/soc/xilinx/Makefile @@ -1,4 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_XILINX_VCU) += xlnx_vcu.o obj-$(CONFIG_ZYNQMP_POWER) += zynqmp_power.o obj-$(CONFIG_ZYNQMP_PM_DOMAINS) += zynqmp_pm_domains.o -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-01-21 7:18 UTC|newest] Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-01-21 7:16 [PATCH v3 00/15] soc: xilinx: vcu: Convert driver to clock provider Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-01-21 7:16 ` [PATCH v3 01/15] ARM: dts: vcu: define indexes for output clocks Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:32 ` Stephen Boyd 2021-02-09 2:32 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 02/15] clk: divider: fix initialization with parent_hw Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:32 ` Stephen Boyd 2021-02-09 2:32 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 03/15] soc: xilinx: vcu: drop coreclk from struct xlnx_vcu Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:32 ` Stephen Boyd 2021-02-09 2:32 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 04/15] soc: xilinx: vcu: add helper to wait for PLL locked Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:32 ` Stephen Boyd 2021-02-09 2:32 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 05/15] soc: xilinx: vcu: add helpers for configuring PLL Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:32 ` Stephen Boyd 2021-02-09 2:32 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 06/15] soc: xilinx: vcu: implement PLL disable Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:32 ` Stephen Boyd 2021-02-09 2:32 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 07/15] soc: xilinx: vcu: register PLL as fixed rate clock Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:32 ` Stephen Boyd 2021-02-09 2:32 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 08/15] soc: xilinx: vcu: implement clock provider for output clocks Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:35 ` Stephen Boyd 2021-02-09 2:35 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 09/15] soc: xilinx: vcu: make pll post divider explicit Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:35 ` Stephen Boyd 2021-02-09 2:35 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 10/15] soc: xilinx: vcu: make the PLL configurable Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:35 ` Stephen Boyd 2021-02-09 2:35 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 11/15] soc: xilinx: vcu: remove calculation of PLL configuration Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:35 ` Stephen Boyd 2021-02-09 2:35 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 12/15] soc: xilinx: vcu: use bitfields for register definition Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:35 ` Stephen Boyd 2021-02-09 2:35 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 13/15] soc: xilinx: vcu: fix repeated word the in comment Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:35 ` Stephen Boyd 2021-02-09 2:35 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 14/15] soc: xilinx: vcu: fix alignment to open parenthesis Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:35 ` Stephen Boyd 2021-02-09 2:35 ` Stephen Boyd 2021-01-21 7:16 ` Michael Tretter [this message] 2021-01-21 7:16 ` [PATCH v3 15/15] clk: xilinx: move xlnx_vcu clock driver from soc Michael Tretter 2021-02-09 2:35 ` Stephen Boyd 2021-02-09 2:35 ` Stephen Boyd
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