* [PATCH v2 0/4] Promote Hikey 970 USB phy out of staging @ 2021-01-14 17:35 ` Mauro Carvalho Chehab 0 siblings, 0 replies; 25+ messages in thread From: Mauro Carvalho Chehab @ 2021-01-14 17:35 UTC (permalink / raw) To: Vinod Koul Cc: Mauro Carvalho Chehab, Alex Dewar, Greg Kroah-Hartman, Kishon Vijay Abraham I, Rob Herring, Yu Chen, devel, devicetree, linux-kernel Hi Vinod, This series contain just the PHY patch I sent in Nov, 30 from this series: Move Hikey 970 USB support out of staging and add DT The 3 initial patches address the issues you pointed during your review: patch 1 change the logic to use GENMASK and FIELD_GET/FIELD_PREP macros. It also places all hexadecimal values in lowercase; patch 2 add a delay inside the retry logic; patch 3 changes a function to return a boolean. The 4th patch is actually identical to the patch I sent previously: it just moves the driver to drivers/phy: rename {drivers/staging/hikey9xx => Documentation/devicetree/bindings/phy}/phy-hi3670-usb3.yaml (100%) rename drivers/{staging/hikey9xx => phy/hisilicon}/phy-hi3670-usb3.c (100%) Yet, in order to make this series easier to review, I'm submitting it with --no-merges. This way, you can check the driver as a hole while reviewing the last patch. Mauro Carvalho Chehab (4): staging: hikey9xx: phy-hi3670-usb3.c: use bitfield macros staging: hikey9xx: phy-hi3670-usb3.c: adjust retry logic staging: hikey9xx: phy-hi3670-usb3.c: hi3670_is_abbclk_seleted() returns bool phy: phy-hi3670-usb3: move driver from staging into phy .../bindings/phy/phy-hi3670-usb3.yaml | 72 ++ MAINTAINERS | 9 +- drivers/phy/hisilicon/Kconfig | 10 + drivers/phy/hisilicon/Makefile | 1 + drivers/phy/hisilicon/phy-hi3670-usb3.c | 668 +++++++++++++++++ drivers/staging/hikey9xx/Kconfig | 11 - drivers/staging/hikey9xx/Makefile | 2 - drivers/staging/hikey9xx/phy-hi3670-usb3.c | 671 ------------------ drivers/staging/hikey9xx/phy-hi3670-usb3.yaml | 72 -- 9 files changed, 759 insertions(+), 757 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml create mode 100644 drivers/phy/hisilicon/phy-hi3670-usb3.c delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.c delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.yaml -- 2.29.2 ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 0/4] Promote Hikey 970 USB phy out of staging @ 2021-01-14 17:35 ` Mauro Carvalho Chehab 0 siblings, 0 replies; 25+ messages in thread From: Mauro Carvalho Chehab @ 2021-01-14 17:35 UTC (permalink / raw) To: Vinod Koul Cc: devel, devicetree, Mauro Carvalho Chehab, Greg Kroah-Hartman, Yu Chen, linux-kernel, Kishon Vijay Abraham I, Rob Herring, Alex Dewar Hi Vinod, This series contain just the PHY patch I sent in Nov, 30 from this series: Move Hikey 970 USB support out of staging and add DT The 3 initial patches address the issues you pointed during your review: patch 1 change the logic to use GENMASK and FIELD_GET/FIELD_PREP macros. It also places all hexadecimal values in lowercase; patch 2 add a delay inside the retry logic; patch 3 changes a function to return a boolean. The 4th patch is actually identical to the patch I sent previously: it just moves the driver to drivers/phy: rename {drivers/staging/hikey9xx => Documentation/devicetree/bindings/phy}/phy-hi3670-usb3.yaml (100%) rename drivers/{staging/hikey9xx => phy/hisilicon}/phy-hi3670-usb3.c (100%) Yet, in order to make this series easier to review, I'm submitting it with --no-merges. This way, you can check the driver as a hole while reviewing the last patch. Mauro Carvalho Chehab (4): staging: hikey9xx: phy-hi3670-usb3.c: use bitfield macros staging: hikey9xx: phy-hi3670-usb3.c: adjust retry logic staging: hikey9xx: phy-hi3670-usb3.c: hi3670_is_abbclk_seleted() returns bool phy: phy-hi3670-usb3: move driver from staging into phy .../bindings/phy/phy-hi3670-usb3.yaml | 72 ++ MAINTAINERS | 9 +- drivers/phy/hisilicon/Kconfig | 10 + drivers/phy/hisilicon/Makefile | 1 + drivers/phy/hisilicon/phy-hi3670-usb3.c | 668 +++++++++++++++++ drivers/staging/hikey9xx/Kconfig | 11 - drivers/staging/hikey9xx/Makefile | 2 - drivers/staging/hikey9xx/phy-hi3670-usb3.c | 671 ------------------ drivers/staging/hikey9xx/phy-hi3670-usb3.yaml | 72 -- 9 files changed, 759 insertions(+), 757 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml create mode 100644 drivers/phy/hisilicon/phy-hi3670-usb3.c delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.c delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.yaml -- 2.29.2 _______________________________________________ devel mailing list devel@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 1/4] staging: hikey9xx: phy-hi3670-usb3.c: use bitfield macros 2021-01-14 17:35 ` Mauro Carvalho Chehab @ 2021-01-14 17:35 ` Mauro Carvalho Chehab -1 siblings, 0 replies; 25+ messages in thread From: Mauro Carvalho Chehab @ 2021-01-14 17:35 UTC (permalink / raw) To: Vinod Koul Cc: Mauro Carvalho Chehab, Alex Dewar, Greg Kroah-Hartman, Yu Chen, devel, linux-kernel Cleanup the bitfield macros by using FIELD_PREP() and GENMASK(). While here, place all hexadecimal values in lowercase. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> --- drivers/staging/hikey9xx/phy-hi3670-usb3.c | 61 ++++++++++------------ 1 file changed, 28 insertions(+), 33 deletions(-) diff --git a/drivers/staging/hikey9xx/phy-hi3670-usb3.c b/drivers/staging/hikey9xx/phy-hi3670-usb3.c index 4fc013911a78..722cabaa9bd9 100644 --- a/drivers/staging/hikey9xx/phy-hi3670-usb3.c +++ b/drivers/staging/hikey9xx/phy-hi3670-usb3.c @@ -8,6 +8,7 @@ * Authors: Yu Chen <chenyu56@huawei.com> */ +#include <linux/bitfield.h> #include <linux/clk.h> #include <linux/kernel.h> #include <linux/mfd/syscon.h> @@ -41,15 +42,15 @@ #define SC_CLK_USB3PHY_3MUX1_SEL BIT(25) #define USB3OTG_CTRL0 (0x00) -#define USB3OTG_CTRL3 (0x0C) +#define USB3OTG_CTRL3 (0x0c) #define USB3OTG_CTRL4 (0x10) #define USB3OTG_CTRL5 (0x14) -#define USB3OTG_CTRL7 (0x1C) +#define USB3OTG_CTRL7 (0x1c) #define USB_MISC_CFG50 (0x50) #define USB_MISC_CFG54 (0x54) #define USB_MISC_CFG58 (0x58) -#define USB_MISC_CFG5C (0x5C) -#define USB_MISC_CFGA0 (0xA0) +#define USB_MISC_CFG5C (0x5c) +#define USB_MISC_CFGA0 (0xa0) #define TCA_CLK_RST (0x200) #define TCA_INTR_EN (0x204) #define TCA_INTR_STS (0x208) @@ -66,14 +67,14 @@ #define CTRL5_USB2_SIDDQ BIT(0) -#define CTRL7_USB2_REFCLKSEL_MASK (3 << 3) -#define CTRL7_USB2_REFCLKSEL_ABB (3 << 3) -#define CTRL7_USB2_REFCLKSEL_PAD (2 << 3) +#define CTRL7_USB2_REFCLKSEL_MASK GENMASK(4, 3) +#define CTRL7_USB2_REFCLKSEL_ABB (BIT(4) | BIT(3)) +#define CTRL7_USB2_REFCLKSEL_PAD BIT(4) #define CFG50_USB3_PHY_TEST_POWERDOWN BIT(23) -#define CFG54_USB31PHY_CR_ADDR_MASK (0xFFFF) -#define CFG54_USB31PHY_CR_ADDR_SHIFT (16) +#define CFG54_USB31PHY_CR_ADDR_MASK GENMASK(31, 16) + #define CFG54_USB3PHY_REF_USE_PAD BIT(12) #define CFG54_PHY0_PMA_PWR_STABLE BIT(11) #define CFG54_PHY0_PCS_PWR_STABLE BIT(9) @@ -84,8 +85,7 @@ #define CFG54_USB31PHY_CR_CLK BIT(2) #define CFG54_USB3_PHY0_ANA_PWR_EN BIT(1) -#define CFG58_USB31PHY_CR_DATA_MASK (0xFFFF) -#define CFG58_USB31PHY_CR_DATA_RD_START (16) +#define CFG58_USB31PHY_CR_DATA_MASK GENMASK(31, 16) #define CFG5C_USB3_PHY0_SS_MPLLA_SSC_EN BIT(1) @@ -102,20 +102,20 @@ #define CLK_RST_SUSPEND_CLK_EN BIT(0) #define GCFG_ROLE_HSTDEV BIT(4) -#define GCFG_OP_MODE (3 << 0) +#define GCFG_OP_MODE GENMASK(1, 0) #define GCFG_OP_MODE_CTRL_SYNC_MODE BIT(0) #define TCPC_VALID BIT(4) #define TCPC_LOW_POWER_EN BIT(3) -#define TCPC_MUX_CONTROL_MASK (3 << 0) +#define TCPC_MUX_CONTROL_MASK GENMASK(1, 0) #define TCPC_MUX_CONTROL_USB31 BIT(0) #define SYSMODE_CFG_TYPEC_DISABLE BIT(3) -#define VBUS_CTRL_POWERPRESENT_OVERRD (3 << 2) -#define VBUS_CTRL_VBUSVALID_OVERRD (3 << 0) +#define VBUS_CTRL_POWERPRESENT_OVERRD GENMASK(3, 2) +#define VBUS_CTRL_VBUSVALID_OVERRD GENMASK(1, 0) -#define KIRIN970_USB_DEFAULT_PHY_PARAM (0xFDFEE4) +#define KIRIN970_USB_DEFAULT_PHY_PARAM (0xfdfee4) #define KIRIN970_USB_DEFAULT_PHY_VBOOST (0x5) #define TX_VBOOST_LVL_REG (0xf) @@ -162,16 +162,14 @@ static int hi3670_phy_cr_set_sel(struct regmap *usb31misc) static int hi3670_phy_cr_start(struct regmap *usb31misc, int direction) { - int ret; + int ret, reg; if (direction) - ret = regmap_update_bits(usb31misc, USB_MISC_CFG54, - CFG54_USB31PHY_CR_WR_EN, - CFG54_USB31PHY_CR_WR_EN); + reg = CFG54_USB31PHY_CR_WR_EN; else - ret = regmap_update_bits(usb31misc, USB_MISC_CFG54, - CFG54_USB31PHY_CR_RD_EN, - CFG54_USB31PHY_CR_RD_EN); + reg = CFG54_USB31PHY_CR_RD_EN; + + ret = regmap_update_bits(usb31misc, USB_MISC_CFG54, reg, reg); if (ret) return ret; @@ -180,10 +178,8 @@ static int hi3670_phy_cr_start(struct regmap *usb31misc, int direction) if (ret) return ret; - ret = regmap_update_bits(usb31misc, USB_MISC_CFG54, - CFG54_USB31PHY_CR_RD_EN | CFG54_USB31PHY_CR_WR_EN, 0); - - return ret; + return regmap_update_bits(usb31misc, USB_MISC_CFG54, + CFG54_USB31PHY_CR_RD_EN | CFG54_USB31PHY_CR_WR_EN, 0); } static int hi3670_phy_cr_wait_ack(struct regmap *usb31misc) @@ -216,9 +212,9 @@ static int hi3670_phy_cr_set_addr(struct regmap *usb31misc, u32 addr) if (ret) return ret; - reg &= ~(CFG54_USB31PHY_CR_ADDR_MASK << CFG54_USB31PHY_CR_ADDR_SHIFT); - reg |= ((addr & CFG54_USB31PHY_CR_ADDR_MASK) << CFG54_USB31PHY_CR_ADDR_SHIFT); - ret = regmap_write(usb31misc, USB_MISC_CFG54, reg); + reg = FIELD_PREP(CFG54_USB31PHY_CR_ADDR_MASK, addr); + ret = regmap_update_bits(usb31misc, USB_MISC_CFG54, + CFG54_USB31PHY_CR_ADDR_MASK, reg); return ret; } @@ -255,8 +251,7 @@ static int hi3670_phy_cr_read(struct regmap *usb31misc, u32 addr, u32 *val) if (ret) return ret; - *val = (reg >> CFG58_USB31PHY_CR_DATA_RD_START) & - CFG58_USB31PHY_CR_DATA_MASK; + *val = FIELD_GET(CFG58_USB31PHY_CR_DATA_MASK, reg); return 0; } @@ -281,7 +276,7 @@ static int hi3670_phy_cr_write(struct regmap *usb31misc, u32 addr, u32 val) return ret; ret = regmap_write(usb31misc, USB_MISC_CFG58, - val & CFG58_USB31PHY_CR_DATA_MASK); + FIELD_PREP(CFG58_USB31PHY_CR_DATA_MASK, val)); if (ret) return ret; -- 2.29.2 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v2 1/4] staging: hikey9xx: phy-hi3670-usb3.c: use bitfield macros @ 2021-01-14 17:35 ` Mauro Carvalho Chehab 0 siblings, 0 replies; 25+ messages in thread From: Mauro Carvalho Chehab @ 2021-01-14 17:35 UTC (permalink / raw) To: Vinod Koul Cc: devel, Mauro Carvalho Chehab, Greg Kroah-Hartman, Yu Chen, linux-kernel, Alex Dewar Cleanup the bitfield macros by using FIELD_PREP() and GENMASK(). While here, place all hexadecimal values in lowercase. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> --- drivers/staging/hikey9xx/phy-hi3670-usb3.c | 61 ++++++++++------------ 1 file changed, 28 insertions(+), 33 deletions(-) diff --git a/drivers/staging/hikey9xx/phy-hi3670-usb3.c b/drivers/staging/hikey9xx/phy-hi3670-usb3.c index 4fc013911a78..722cabaa9bd9 100644 --- a/drivers/staging/hikey9xx/phy-hi3670-usb3.c +++ b/drivers/staging/hikey9xx/phy-hi3670-usb3.c @@ -8,6 +8,7 @@ * Authors: Yu Chen <chenyu56@huawei.com> */ +#include <linux/bitfield.h> #include <linux/clk.h> #include <linux/kernel.h> #include <linux/mfd/syscon.h> @@ -41,15 +42,15 @@ #define SC_CLK_USB3PHY_3MUX1_SEL BIT(25) #define USB3OTG_CTRL0 (0x00) -#define USB3OTG_CTRL3 (0x0C) +#define USB3OTG_CTRL3 (0x0c) #define USB3OTG_CTRL4 (0x10) #define USB3OTG_CTRL5 (0x14) -#define USB3OTG_CTRL7 (0x1C) +#define USB3OTG_CTRL7 (0x1c) #define USB_MISC_CFG50 (0x50) #define USB_MISC_CFG54 (0x54) #define USB_MISC_CFG58 (0x58) -#define USB_MISC_CFG5C (0x5C) -#define USB_MISC_CFGA0 (0xA0) +#define USB_MISC_CFG5C (0x5c) +#define USB_MISC_CFGA0 (0xa0) #define TCA_CLK_RST (0x200) #define TCA_INTR_EN (0x204) #define TCA_INTR_STS (0x208) @@ -66,14 +67,14 @@ #define CTRL5_USB2_SIDDQ BIT(0) -#define CTRL7_USB2_REFCLKSEL_MASK (3 << 3) -#define CTRL7_USB2_REFCLKSEL_ABB (3 << 3) -#define CTRL7_USB2_REFCLKSEL_PAD (2 << 3) +#define CTRL7_USB2_REFCLKSEL_MASK GENMASK(4, 3) +#define CTRL7_USB2_REFCLKSEL_ABB (BIT(4) | BIT(3)) +#define CTRL7_USB2_REFCLKSEL_PAD BIT(4) #define CFG50_USB3_PHY_TEST_POWERDOWN BIT(23) -#define CFG54_USB31PHY_CR_ADDR_MASK (0xFFFF) -#define CFG54_USB31PHY_CR_ADDR_SHIFT (16) +#define CFG54_USB31PHY_CR_ADDR_MASK GENMASK(31, 16) + #define CFG54_USB3PHY_REF_USE_PAD BIT(12) #define CFG54_PHY0_PMA_PWR_STABLE BIT(11) #define CFG54_PHY0_PCS_PWR_STABLE BIT(9) @@ -84,8 +85,7 @@ #define CFG54_USB31PHY_CR_CLK BIT(2) #define CFG54_USB3_PHY0_ANA_PWR_EN BIT(1) -#define CFG58_USB31PHY_CR_DATA_MASK (0xFFFF) -#define CFG58_USB31PHY_CR_DATA_RD_START (16) +#define CFG58_USB31PHY_CR_DATA_MASK GENMASK(31, 16) #define CFG5C_USB3_PHY0_SS_MPLLA_SSC_EN BIT(1) @@ -102,20 +102,20 @@ #define CLK_RST_SUSPEND_CLK_EN BIT(0) #define GCFG_ROLE_HSTDEV BIT(4) -#define GCFG_OP_MODE (3 << 0) +#define GCFG_OP_MODE GENMASK(1, 0) #define GCFG_OP_MODE_CTRL_SYNC_MODE BIT(0) #define TCPC_VALID BIT(4) #define TCPC_LOW_POWER_EN BIT(3) -#define TCPC_MUX_CONTROL_MASK (3 << 0) +#define TCPC_MUX_CONTROL_MASK GENMASK(1, 0) #define TCPC_MUX_CONTROL_USB31 BIT(0) #define SYSMODE_CFG_TYPEC_DISABLE BIT(3) -#define VBUS_CTRL_POWERPRESENT_OVERRD (3 << 2) -#define VBUS_CTRL_VBUSVALID_OVERRD (3 << 0) +#define VBUS_CTRL_POWERPRESENT_OVERRD GENMASK(3, 2) +#define VBUS_CTRL_VBUSVALID_OVERRD GENMASK(1, 0) -#define KIRIN970_USB_DEFAULT_PHY_PARAM (0xFDFEE4) +#define KIRIN970_USB_DEFAULT_PHY_PARAM (0xfdfee4) #define KIRIN970_USB_DEFAULT_PHY_VBOOST (0x5) #define TX_VBOOST_LVL_REG (0xf) @@ -162,16 +162,14 @@ static int hi3670_phy_cr_set_sel(struct regmap *usb31misc) static int hi3670_phy_cr_start(struct regmap *usb31misc, int direction) { - int ret; + int ret, reg; if (direction) - ret = regmap_update_bits(usb31misc, USB_MISC_CFG54, - CFG54_USB31PHY_CR_WR_EN, - CFG54_USB31PHY_CR_WR_EN); + reg = CFG54_USB31PHY_CR_WR_EN; else - ret = regmap_update_bits(usb31misc, USB_MISC_CFG54, - CFG54_USB31PHY_CR_RD_EN, - CFG54_USB31PHY_CR_RD_EN); + reg = CFG54_USB31PHY_CR_RD_EN; + + ret = regmap_update_bits(usb31misc, USB_MISC_CFG54, reg, reg); if (ret) return ret; @@ -180,10 +178,8 @@ static int hi3670_phy_cr_start(struct regmap *usb31misc, int direction) if (ret) return ret; - ret = regmap_update_bits(usb31misc, USB_MISC_CFG54, - CFG54_USB31PHY_CR_RD_EN | CFG54_USB31PHY_CR_WR_EN, 0); - - return ret; + return regmap_update_bits(usb31misc, USB_MISC_CFG54, + CFG54_USB31PHY_CR_RD_EN | CFG54_USB31PHY_CR_WR_EN, 0); } static int hi3670_phy_cr_wait_ack(struct regmap *usb31misc) @@ -216,9 +212,9 @@ static int hi3670_phy_cr_set_addr(struct regmap *usb31misc, u32 addr) if (ret) return ret; - reg &= ~(CFG54_USB31PHY_CR_ADDR_MASK << CFG54_USB31PHY_CR_ADDR_SHIFT); - reg |= ((addr & CFG54_USB31PHY_CR_ADDR_MASK) << CFG54_USB31PHY_CR_ADDR_SHIFT); - ret = regmap_write(usb31misc, USB_MISC_CFG54, reg); + reg = FIELD_PREP(CFG54_USB31PHY_CR_ADDR_MASK, addr); + ret = regmap_update_bits(usb31misc, USB_MISC_CFG54, + CFG54_USB31PHY_CR_ADDR_MASK, reg); return ret; } @@ -255,8 +251,7 @@ static int hi3670_phy_cr_read(struct regmap *usb31misc, u32 addr, u32 *val) if (ret) return ret; - *val = (reg >> CFG58_USB31PHY_CR_DATA_RD_START) & - CFG58_USB31PHY_CR_DATA_MASK; + *val = FIELD_GET(CFG58_USB31PHY_CR_DATA_MASK, reg); return 0; } @@ -281,7 +276,7 @@ static int hi3670_phy_cr_write(struct regmap *usb31misc, u32 addr, u32 val) return ret; ret = regmap_write(usb31misc, USB_MISC_CFG58, - val & CFG58_USB31PHY_CR_DATA_MASK); + FIELD_PREP(CFG58_USB31PHY_CR_DATA_MASK, val)); if (ret) return ret; -- 2.29.2 _______________________________________________ devel mailing list devel@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v2 2/4] staging: hikey9xx: phy-hi3670-usb3.c: adjust retry logic 2021-01-14 17:35 ` Mauro Carvalho Chehab @ 2021-01-14 17:35 ` Mauro Carvalho Chehab -1 siblings, 0 replies; 25+ messages in thread From: Mauro Carvalho Chehab @ 2021-01-14 17:35 UTC (permalink / raw) To: Vinod Koul Cc: Mauro Carvalho Chehab, Alex Dewar, Greg Kroah-Hartman, Yu Chen, devel, linux-kernel Instead of running a loop up to 100k times, add a small delay inside it, running it up to 10 times, waiting up to 100-200 us. It should be noticed that I don't have the datasheet for this PHY. So, not sure if this time will cover all situations. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> --- drivers/staging/hikey9xx/phy-hi3670-usb3.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/staging/hikey9xx/phy-hi3670-usb3.c b/drivers/staging/hikey9xx/phy-hi3670-usb3.c index 722cabaa9bd9..cffe6c58dfd7 100644 --- a/drivers/staging/hikey9xx/phy-hi3670-usb3.c +++ b/drivers/staging/hikey9xx/phy-hi3670-usb3.c @@ -185,7 +185,7 @@ static int hi3670_phy_cr_start(struct regmap *usb31misc, int direction) static int hi3670_phy_cr_wait_ack(struct regmap *usb31misc) { u32 reg; - int retry = 100000; + int retry = 10; int ret; while (retry-- > 0) { @@ -198,6 +198,8 @@ static int hi3670_phy_cr_wait_ack(struct regmap *usb31misc) ret = hi3670_phy_cr_clk(usb31misc); if (ret) return ret; + + usleep_range(10, 20); } return -ETIMEDOUT; -- 2.29.2 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v2 2/4] staging: hikey9xx: phy-hi3670-usb3.c: adjust retry logic @ 2021-01-14 17:35 ` Mauro Carvalho Chehab 0 siblings, 0 replies; 25+ messages in thread From: Mauro Carvalho Chehab @ 2021-01-14 17:35 UTC (permalink / raw) To: Vinod Koul Cc: devel, Mauro Carvalho Chehab, Greg Kroah-Hartman, Yu Chen, linux-kernel, Alex Dewar Instead of running a loop up to 100k times, add a small delay inside it, running it up to 10 times, waiting up to 100-200 us. It should be noticed that I don't have the datasheet for this PHY. So, not sure if this time will cover all situations. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> --- drivers/staging/hikey9xx/phy-hi3670-usb3.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/staging/hikey9xx/phy-hi3670-usb3.c b/drivers/staging/hikey9xx/phy-hi3670-usb3.c index 722cabaa9bd9..cffe6c58dfd7 100644 --- a/drivers/staging/hikey9xx/phy-hi3670-usb3.c +++ b/drivers/staging/hikey9xx/phy-hi3670-usb3.c @@ -185,7 +185,7 @@ static int hi3670_phy_cr_start(struct regmap *usb31misc, int direction) static int hi3670_phy_cr_wait_ack(struct regmap *usb31misc) { u32 reg; - int retry = 100000; + int retry = 10; int ret; while (retry-- > 0) { @@ -198,6 +198,8 @@ static int hi3670_phy_cr_wait_ack(struct regmap *usb31misc) ret = hi3670_phy_cr_clk(usb31misc); if (ret) return ret; + + usleep_range(10, 20); } return -ETIMEDOUT; -- 2.29.2 _______________________________________________ devel mailing list devel@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v2 3/4] staging: hikey9xx: phy-hi3670-usb3.c: hi3670_is_abbclk_seleted() returns bool 2021-01-14 17:35 ` Mauro Carvalho Chehab @ 2021-01-14 17:35 ` Mauro Carvalho Chehab -1 siblings, 0 replies; 25+ messages in thread From: Mauro Carvalho Chehab @ 2021-01-14 17:35 UTC (permalink / raw) To: Vinod Koul Cc: Mauro Carvalho Chehab, Alex Dewar, Greg Kroah-Hartman, Yu Chen, devel, linux-kernel Instead of using 1/0 for true/false, change the type to boolean and change the returned value. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> --- drivers/staging/hikey9xx/phy-hi3670-usb3.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/staging/hikey9xx/phy-hi3670-usb3.c b/drivers/staging/hikey9xx/phy-hi3670-usb3.c index cffe6c58dfd7..b5fed306fcbf 100644 --- a/drivers/staging/hikey9xx/phy-hi3670-usb3.c +++ b/drivers/staging/hikey9xx/phy-hi3670-usb3.c @@ -326,24 +326,24 @@ static int hi3670_phy_set_params(struct hi3670_priv *priv) return ret; } -static int hi3670_is_abbclk_seleted(struct hi3670_priv *priv) +static bool hi3670_is_abbclk_seleted(struct hi3670_priv *priv) { u32 reg; if (!priv->sctrl) { dev_err(priv->dev, "priv->sctrl is null!\n"); - return 1; + return true; } if (regmap_read(priv->sctrl, SCTRL_SCDEEPSLEEPED, ®)) { dev_err(priv->dev, "SCTRL_SCDEEPSLEEPED read failed!\n"); - return 1; + return true; } if ((reg & USB_CLK_SELECTED) == 0) - return 1; + return true; - return 0; + return false; } static int hi3670_config_phy_clock(struct hi3670_priv *priv) -- 2.29.2 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v2 3/4] staging: hikey9xx: phy-hi3670-usb3.c: hi3670_is_abbclk_seleted() returns bool @ 2021-01-14 17:35 ` Mauro Carvalho Chehab 0 siblings, 0 replies; 25+ messages in thread From: Mauro Carvalho Chehab @ 2021-01-14 17:35 UTC (permalink / raw) To: Vinod Koul Cc: devel, Mauro Carvalho Chehab, Greg Kroah-Hartman, Yu Chen, linux-kernel, Alex Dewar Instead of using 1/0 for true/false, change the type to boolean and change the returned value. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> --- drivers/staging/hikey9xx/phy-hi3670-usb3.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/staging/hikey9xx/phy-hi3670-usb3.c b/drivers/staging/hikey9xx/phy-hi3670-usb3.c index cffe6c58dfd7..b5fed306fcbf 100644 --- a/drivers/staging/hikey9xx/phy-hi3670-usb3.c +++ b/drivers/staging/hikey9xx/phy-hi3670-usb3.c @@ -326,24 +326,24 @@ static int hi3670_phy_set_params(struct hi3670_priv *priv) return ret; } -static int hi3670_is_abbclk_seleted(struct hi3670_priv *priv) +static bool hi3670_is_abbclk_seleted(struct hi3670_priv *priv) { u32 reg; if (!priv->sctrl) { dev_err(priv->dev, "priv->sctrl is null!\n"); - return 1; + return true; } if (regmap_read(priv->sctrl, SCTRL_SCDEEPSLEEPED, ®)) { dev_err(priv->dev, "SCTRL_SCDEEPSLEEPED read failed!\n"); - return 1; + return true; } if ((reg & USB_CLK_SELECTED) == 0) - return 1; + return true; - return 0; + return false; } static int hi3670_config_phy_clock(struct hi3670_priv *priv) -- 2.29.2 _______________________________________________ devel mailing list devel@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v2 3/4] staging: hikey9xx: phy-hi3670-usb3.c: hi3670_is_abbclk_seleted() returns bool 2021-01-14 17:35 ` Mauro Carvalho Chehab @ 2021-01-14 17:56 ` Joe Perches -1 siblings, 0 replies; 25+ messages in thread From: Joe Perches @ 2021-01-14 17:56 UTC (permalink / raw) To: Mauro Carvalho Chehab, Vinod Koul Cc: Alex Dewar, Greg Kroah-Hartman, Yu Chen, devel, linux-kernel On Thu, 2021-01-14 at 18:35 +0100, Mauro Carvalho Chehab wrote: > Instead of using 1/0 for true/false, change the type to boolean > and change the returned value. [] > diff --git a/drivers/staging/hikey9xx/phy-hi3670-usb3.c b/drivers/staging/hikey9xx/phy-hi3670-usb3.c [] > @@ -326,24 +326,24 @@ static int hi3670_phy_set_params(struct hi3670_priv *priv) > return ret; > } > > -static int hi3670_is_abbclk_seleted(struct hi3670_priv *priv) > +static bool hi3670_is_abbclk_seleted(struct hi3670_priv *priv) Presumably this should be "selected" not "seleted" > { > u32 reg; > > if (!priv->sctrl) { > dev_err(priv->dev, "priv->sctrl is null!\n"); > - return 1; > + return true; > } > > if (regmap_read(priv->sctrl, SCTRL_SCDEEPSLEEPED, ®)) { > dev_err(priv->dev, "SCTRL_SCDEEPSLEEPED read failed!\n"); > - return 1; > + return true; > } > > if ((reg & USB_CLK_SELECTED) == 0) > - return 1; > + return true; > > - return 0; > + return false; > } if (foo) return true; return false; should generally be consolidated into a single test. So this is perhaps better as: return (!(reg & USB_CLK_SELECTED)); But the return value seems backwards. ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 3/4] staging: hikey9xx: phy-hi3670-usb3.c: hi3670_is_abbclk_seleted() returns bool @ 2021-01-14 17:56 ` Joe Perches 0 siblings, 0 replies; 25+ messages in thread From: Joe Perches @ 2021-01-14 17:56 UTC (permalink / raw) To: Mauro Carvalho Chehab, Vinod Koul Cc: devel, Greg Kroah-Hartman, Yu Chen, Alex Dewar, linux-kernel On Thu, 2021-01-14 at 18:35 +0100, Mauro Carvalho Chehab wrote: > Instead of using 1/0 for true/false, change the type to boolean > and change the returned value. [] > diff --git a/drivers/staging/hikey9xx/phy-hi3670-usb3.c b/drivers/staging/hikey9xx/phy-hi3670-usb3.c [] > @@ -326,24 +326,24 @@ static int hi3670_phy_set_params(struct hi3670_priv *priv) > return ret; > } > > -static int hi3670_is_abbclk_seleted(struct hi3670_priv *priv) > +static bool hi3670_is_abbclk_seleted(struct hi3670_priv *priv) Presumably this should be "selected" not "seleted" > { > u32 reg; > > if (!priv->sctrl) { > dev_err(priv->dev, "priv->sctrl is null!\n"); > - return 1; > + return true; > } > > if (regmap_read(priv->sctrl, SCTRL_SCDEEPSLEEPED, ®)) { > dev_err(priv->dev, "SCTRL_SCDEEPSLEEPED read failed!\n"); > - return 1; > + return true; > } > > if ((reg & USB_CLK_SELECTED) == 0) > - return 1; > + return true; > > - return 0; > + return false; > } if (foo) return true; return false; should generally be consolidated into a single test. So this is perhaps better as: return (!(reg & USB_CLK_SELECTED)); But the return value seems backwards. _______________________________________________ devel mailing list devel@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 3/4] staging: hikey9xx: phy-hi3670-usb3.c: hi3670_is_abbclk_seleted() returns bool 2021-01-14 17:56 ` Joe Perches @ 2021-01-19 6:56 ` Dan Carpenter -1 siblings, 0 replies; 25+ messages in thread From: Dan Carpenter @ 2021-01-19 6:56 UTC (permalink / raw) To: Joe Perches Cc: Mauro Carvalho Chehab, Vinod Koul, devel, Greg Kroah-Hartman, Yu Chen, Alex Dewar, linux-kernel On Thu, Jan 14, 2021 at 09:56:41AM -0800, Joe Perches wrote: > On Thu, 2021-01-14 at 18:35 +0100, Mauro Carvalho Chehab wrote: > > Instead of using 1/0 for true/false, change the type to boolean > > and change the returned value. > [] > > diff --git a/drivers/staging/hikey9xx/phy-hi3670-usb3.c b/drivers/staging/hikey9xx/phy-hi3670-usb3.c > [] > > @@ -326,24 +326,24 @@ static int hi3670_phy_set_params(struct hi3670_priv *priv) > > return ret; > > } > > > > -static int hi3670_is_abbclk_seleted(struct hi3670_priv *priv) > > +static bool hi3670_is_abbclk_seleted(struct hi3670_priv *priv) > > Presumably this should be "selected" not "seleted" > > > { > > u32 reg; > > > > if (!priv->sctrl) { > > dev_err(priv->dev, "priv->sctrl is null!\n"); > > - return 1; > > + return true; > > } > > > > if (regmap_read(priv->sctrl, SCTRL_SCDEEPSLEEPED, ®)) { > > dev_err(priv->dev, "SCTRL_SCDEEPSLEEPED read failed!\n"); > > - return 1; > > + return true; > > } > > > > if ((reg & USB_CLK_SELECTED) == 0) > > - return 1; > > + return true; > > > > - return 0; > > + return false; > > } > > if (foo) > return true; > return false; > > should generally be consolidated into a single test. I quite prefer the original format, but you're right about the return looking reversed. Using "return !!(reg & USB_CLK_SELECTED);" is especially problematic. I like !! but Linus has commented a couple times that he doesn't like !!. regards, dan carpenter ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 3/4] staging: hikey9xx: phy-hi3670-usb3.c: hi3670_is_abbclk_seleted() returns bool @ 2021-01-19 6:56 ` Dan Carpenter 0 siblings, 0 replies; 25+ messages in thread From: Dan Carpenter @ 2021-01-19 6:56 UTC (permalink / raw) To: Joe Perches Cc: devel, Mauro Carvalho Chehab, Greg Kroah-Hartman, Yu Chen, linux-kernel, Vinod Koul, Alex Dewar On Thu, Jan 14, 2021 at 09:56:41AM -0800, Joe Perches wrote: > On Thu, 2021-01-14 at 18:35 +0100, Mauro Carvalho Chehab wrote: > > Instead of using 1/0 for true/false, change the type to boolean > > and change the returned value. > [] > > diff --git a/drivers/staging/hikey9xx/phy-hi3670-usb3.c b/drivers/staging/hikey9xx/phy-hi3670-usb3.c > [] > > @@ -326,24 +326,24 @@ static int hi3670_phy_set_params(struct hi3670_priv *priv) > > return ret; > > } > > > > -static int hi3670_is_abbclk_seleted(struct hi3670_priv *priv) > > +static bool hi3670_is_abbclk_seleted(struct hi3670_priv *priv) > > Presumably this should be "selected" not "seleted" > > > { > > u32 reg; > > > > if (!priv->sctrl) { > > dev_err(priv->dev, "priv->sctrl is null!\n"); > > - return 1; > > + return true; > > } > > > > if (regmap_read(priv->sctrl, SCTRL_SCDEEPSLEEPED, ®)) { > > dev_err(priv->dev, "SCTRL_SCDEEPSLEEPED read failed!\n"); > > - return 1; > > + return true; > > } > > > > if ((reg & USB_CLK_SELECTED) == 0) > > - return 1; > > + return true; > > > > - return 0; > > + return false; > > } > > if (foo) > return true; > return false; > > should generally be consolidated into a single test. I quite prefer the original format, but you're right about the return looking reversed. Using "return !!(reg & USB_CLK_SELECTED);" is especially problematic. I like !! but Linus has commented a couple times that he doesn't like !!. regards, dan carpenter _______________________________________________ devel mailing list devel@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 3/4] staging: hikey9xx: phy-hi3670-usb3.c: hi3670_is_abbclk_seleted() returns bool 2021-01-19 6:56 ` Dan Carpenter (?) @ 2021-01-19 10:24 ` Mauro Carvalho Chehab -1 siblings, 0 replies; 25+ messages in thread From: Mauro Carvalho Chehab @ 2021-01-19 10:24 UTC (permalink / raw) To: Dan Carpenter Cc: devel, Greg Kroah-Hartman, Yu Chen, Vinod Koul, Joe Perches, Alex Dewar Em Tue, 19 Jan 2021 09:56:31 +0300 Dan Carpenter <dan.carpenter@oracle.com> escreveu: > On Thu, Jan 14, 2021 at 09:56:41AM -0800, Joe Perches wrote: > > On Thu, 2021-01-14 at 18:35 +0100, Mauro Carvalho Chehab wrote: > > > Instead of using 1/0 for true/false, change the type to boolean > > > and change the returned value. > > [] > > > diff --git a/drivers/staging/hikey9xx/phy-hi3670-usb3.c b/drivers/staging/hikey9xx/phy-hi3670-usb3.c > > [] > > > @@ -326,24 +326,24 @@ static int hi3670_phy_set_params(struct hi3670_priv *priv) > > > return ret; > > > } > > > > > > -static int hi3670_is_abbclk_seleted(struct hi3670_priv *priv) > > > +static bool hi3670_is_abbclk_seleted(struct hi3670_priv *priv) > > > > Presumably this should be "selected" not "seleted" True. I'll fix it. > > > > > { > > > u32 reg; > > > > > > if (!priv->sctrl) { > > > dev_err(priv->dev, "priv->sctrl is null!\n"); > > > - return 1; > > > + return true; > > > } > > > > > > if (regmap_read(priv->sctrl, SCTRL_SCDEEPSLEEPED, ®)) { > > > dev_err(priv->dev, "SCTRL_SCDEEPSLEEPED read failed!\n"); > > > - return 1; > > > + return true; > > > } > > > > > > if ((reg & USB_CLK_SELECTED) == 0) > > > - return 1; > > > + return true; > > > > > > - return 0; > > > + return false; > > > } > > > > if (foo) > > return true; > > return false; > > > > should generally be consolidated into a single test. > > I quite prefer the original format, but you're right about the return > looking reversed. Using "return !!(reg & USB_CLK_SELECTED);" is > especially problematic. I like !! but Linus has commented a couple > times that he doesn't like !!. Me to. "return !!(reg & USB_CLK_SELECTED)" just obfuscates the source code, imho for no good reason. It sounds a lot easier to read something like: if (cond1) return true; if (cond2) return true; if (cond3) return true; return false; Yet, I agree that the logic here seems to be inverted. > > regards, > dan carpenter > > Thanks, Mauro _______________________________________________ devel mailing list devel@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 4/4] phy: phy-hi3670-usb3: move driver from staging into phy 2021-01-14 17:35 ` Mauro Carvalho Chehab @ 2021-01-14 17:35 ` Mauro Carvalho Chehab -1 siblings, 0 replies; 25+ messages in thread From: Mauro Carvalho Chehab @ 2021-01-14 17:35 UTC (permalink / raw) To: Vinod Koul Cc: Mauro Carvalho Chehab, Alex Dewar, Greg Kroah-Hartman, Kishon Vijay Abraham I, Rob Herring, Yu Chen, devel, devicetree, linux-kernel The phy USB3 driver for Hisilicon 970 (hi3670) is ready for mainstream. Mode it from staging into the main driver's phy/ directory. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> --- .../bindings/phy/phy-hi3670-usb3.yaml | 72 ++ MAINTAINERS | 9 +- drivers/phy/hisilicon/Kconfig | 10 + drivers/phy/hisilicon/Makefile | 1 + drivers/phy/hisilicon/phy-hi3670-usb3.c | 668 ++++++++++++++++++ drivers/staging/hikey9xx/Kconfig | 11 - drivers/staging/hikey9xx/Makefile | 2 - drivers/staging/hikey9xx/phy-hi3670-usb3.c | 668 ------------------ drivers/staging/hikey9xx/phy-hi3670-usb3.yaml | 72 -- 9 files changed, 759 insertions(+), 754 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml create mode 100644 drivers/phy/hisilicon/phy-hi3670-usb3.c delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.c delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.yaml diff --git a/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml b/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml new file mode 100644 index 000000000000..125a5d6546ae --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/hisilicon,hi3670-usb3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Kirin970 USB PHY + +maintainers: + - Mauro Carvalho Chehab <mchehab+huawei@kernel.org> +description: |+ + Bindings for USB3 PHY on HiSilicon Kirin 970. + +properties: + compatible: + const: hisilicon,hi3670-usb-phy + + "#phy-cells": + const: 0 + + hisilicon,pericrg-syscon: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: phandle of syscon used to control iso refclk. + + hisilicon,pctrl-syscon: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: phandle of syscon used to control usb tcxo. + + hisilicon,sctrl-syscon: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: phandle of syscon used to control phy deep sleep. + + hisilicon,eye-diagram-param: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Eye diagram for phy. + + hisilicon,tx-vboost-lvl: + $ref: /schemas/types.yaml#/definitions/uint32 + description: TX level vboost for phy. + +required: + - compatible + - hisilicon,pericrg-syscon + - hisilicon,pctrl-syscon + - hisilicon,sctrl-syscon + - hisilicon,eye-diagram-param + - hisilicon,tx-vboost-lvl + - "#phy-cells" + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + usb3_otg_bc: usb3_otg_bc@ff200000 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0xff200000 0x0 0x1000>; + + usb_phy { + compatible = "hisilicon,hi3670-usb-phy"; + #phy-cells = <0>; + hisilicon,pericrg-syscon = <&crg_ctrl>; + hisilicon,pctrl-syscon = <&pctrl>; + hisilicon,sctrl-syscon = <&sctrl>; + hisilicon,eye-diagram-param = <0xfdfee4>; + hisilicon,tx-vboost-lvl = <0x5>; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 281de213ef47..8d858e8d5a52 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18088,7 +18088,7 @@ L: linux-usb@vger.kernel.org S: Maintained F: drivers/usb/roles/intel-xhci-usb-role-switch.c -USB IP DRIVER FOR HISILICON KIRIN +USB IP DRIVER FOR HISILICON KIRIN 960 M: Yu Chen <chenyu56@huawei.com> M: Binghui Wang <wangbinghui@hisilicon.com> L: linux-usb@vger.kernel.org @@ -18096,6 +18096,13 @@ S: Maintained F: Documentation/devicetree/bindings/phy/hisilicon,hi3660-usb3.yaml F: drivers/phy/hisilicon/phy-hi3660-usb3.c +USB IP DRIVER FOR HISILICON KIRIN 970 +M: Mauro Carvalho Chehab <mchehab@kernel.org> +L: linux-usb@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/phy/hisilicon,kirin970-usb3.yaml +F: drivers/phy/hisilicon/phy-kirin970-usb3.c + USB ISP116X DRIVER M: Olav Kongas <ok@artecdesign.ee> L: linux-usb@vger.kernel.org diff --git a/drivers/phy/hisilicon/Kconfig b/drivers/phy/hisilicon/Kconfig index 1c73053bcc98..4d008cfc279c 100644 --- a/drivers/phy/hisilicon/Kconfig +++ b/drivers/phy/hisilicon/Kconfig @@ -23,6 +23,16 @@ config PHY_HI3660_USB To compile this driver as a module, choose M here. +config PHY_HI3670_USB + tristate "hi3670 USB PHY support" + depends on (ARCH_HISI && ARM64) || COMPILE_TEST + select GENERIC_PHY + select MFD_SYSCON + help + Enable this to support the HISILICON HI3670 USB PHY. + + To compile this driver as a module, choose M here. + config PHY_HISTB_COMBPHY tristate "HiSilicon STB SoCs COMBPHY support" depends on (ARCH_HISI && ARM64) || COMPILE_TEST diff --git a/drivers/phy/hisilicon/Makefile b/drivers/phy/hisilicon/Makefile index 92e874ae9c74..51729868145b 100644 --- a/drivers/phy/hisilicon/Makefile +++ b/drivers/phy/hisilicon/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_PHY_HI6220_USB) += phy-hi6220-usb.o obj-$(CONFIG_PHY_HI3660_USB) += phy-hi3660-usb3.o +obj-$(CONFIG_PHY_HI3670_USB) += phy-hi3670-usb3.o obj-$(CONFIG_PHY_HISTB_COMBPHY) += phy-histb-combphy.o obj-$(CONFIG_PHY_HISI_INNO_USB2) += phy-hisi-inno-usb2.o obj-$(CONFIG_PHY_HIX5HD2_SATA) += phy-hix5hd2-sata.o diff --git a/drivers/phy/hisilicon/phy-hi3670-usb3.c b/drivers/phy/hisilicon/phy-hi3670-usb3.c new file mode 100644 index 000000000000..b5fed306fcbf --- /dev/null +++ b/drivers/phy/hisilicon/phy-hi3670-usb3.c @@ -0,0 +1,668 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Phy provider for USB 3.1 controller on HiSilicon Kirin970 platform + * + * Copyright (C) 2017-2020 Hilisicon Electronics Co., Ltd. + * http://www.huawei.com + * + * Authors: Yu Chen <chenyu56@huawei.com> + */ + +#include <linux/bitfield.h> +#include <linux/clk.h> +#include <linux/kernel.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/phy/phy.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#define SCTRL_SCDEEPSLEEPED (0x0) +#define USB_CLK_SELECTED BIT(20) + +#define PERI_CRG_PEREN0 (0x00) +#define PERI_CRG_PERDIS0 (0x04) +#define PERI_CRG_PEREN4 (0x40) +#define PERI_CRG_PERDIS4 (0x44) +#define PERI_CRG_PERRSTEN4 (0x90) +#define PERI_CRG_PERRSTDIS4 (0x94) +#define PERI_CRG_ISODIS (0x148) +#define PERI_CRG_PEREN6 (0x410) +#define PERI_CRG_PERDIS6 (0x414) + +#define USB_REFCLK_ISO_EN BIT(25) + +#define GT_CLK_USB2PHY_REF BIT(19) + +#define PCTRL_PERI_CTRL3 (0x10) +#define PCTRL_PERI_CTRL3_MSK_START (16) +#define USB_TCXO_EN BIT(1) + +#define PCTRL_PERI_CTRL24 (0x64) +#define SC_CLK_USB3PHY_3MUX1_SEL BIT(25) + +#define USB3OTG_CTRL0 (0x00) +#define USB3OTG_CTRL3 (0x0c) +#define USB3OTG_CTRL4 (0x10) +#define USB3OTG_CTRL5 (0x14) +#define USB3OTG_CTRL7 (0x1c) +#define USB_MISC_CFG50 (0x50) +#define USB_MISC_CFG54 (0x54) +#define USB_MISC_CFG58 (0x58) +#define USB_MISC_CFG5C (0x5c) +#define USB_MISC_CFGA0 (0xa0) +#define TCA_CLK_RST (0x200) +#define TCA_INTR_EN (0x204) +#define TCA_INTR_STS (0x208) +#define TCA_GCFG (0x210) +#define TCA_TCPC (0x214) +#define TCA_SYSMODE_CFG (0x218) +#define TCA_VBUS_CTRL (0x240) + +#define CTRL0_USB3_VBUSVLD BIT(7) +#define CTRL0_USB3_VBUSVLD_SEL BIT(6) + +#define CTRL3_USB2_VBUSVLDEXT0 BIT(6) +#define CTRL3_USB2_VBUSVLDEXTSEL0 BIT(5) + +#define CTRL5_USB2_SIDDQ BIT(0) + +#define CTRL7_USB2_REFCLKSEL_MASK GENMASK(4, 3) +#define CTRL7_USB2_REFCLKSEL_ABB (BIT(4) | BIT(3)) +#define CTRL7_USB2_REFCLKSEL_PAD BIT(4) + +#define CFG50_USB3_PHY_TEST_POWERDOWN BIT(23) + +#define CFG54_USB31PHY_CR_ADDR_MASK GENMASK(31, 16) + +#define CFG54_USB3PHY_REF_USE_PAD BIT(12) +#define CFG54_PHY0_PMA_PWR_STABLE BIT(11) +#define CFG54_PHY0_PCS_PWR_STABLE BIT(9) +#define CFG54_USB31PHY_CR_ACK BIT(7) +#define CFG54_USB31PHY_CR_WR_EN BIT(5) +#define CFG54_USB31PHY_CR_SEL BIT(4) +#define CFG54_USB31PHY_CR_RD_EN BIT(3) +#define CFG54_USB31PHY_CR_CLK BIT(2) +#define CFG54_USB3_PHY0_ANA_PWR_EN BIT(1) + +#define CFG58_USB31PHY_CR_DATA_MASK GENMASK(31, 16) + +#define CFG5C_USB3_PHY0_SS_MPLLA_SSC_EN BIT(1) + +#define CFGA0_VAUX_RESET BIT(9) +#define CFGA0_USB31C_RESET BIT(8) +#define CFGA0_USB2PHY_REFCLK_SELECT BIT(4) +#define CFGA0_USB3PHY_RESET BIT(1) +#define CFGA0_USB2PHY_POR BIT(0) + +#define INTR_EN_XA_TIMEOUT_EVT_EN BIT(1) +#define INTR_EN_XA_ACK_EVT_EN BIT(0) + +#define CLK_RST_TCA_REF_CLK_EN BIT(1) +#define CLK_RST_SUSPEND_CLK_EN BIT(0) + +#define GCFG_ROLE_HSTDEV BIT(4) +#define GCFG_OP_MODE GENMASK(1, 0) +#define GCFG_OP_MODE_CTRL_SYNC_MODE BIT(0) + +#define TCPC_VALID BIT(4) +#define TCPC_LOW_POWER_EN BIT(3) +#define TCPC_MUX_CONTROL_MASK GENMASK(1, 0) +#define TCPC_MUX_CONTROL_USB31 BIT(0) + +#define SYSMODE_CFG_TYPEC_DISABLE BIT(3) + +#define VBUS_CTRL_POWERPRESENT_OVERRD GENMASK(3, 2) +#define VBUS_CTRL_VBUSVALID_OVERRD GENMASK(1, 0) + +#define KIRIN970_USB_DEFAULT_PHY_PARAM (0xfdfee4) +#define KIRIN970_USB_DEFAULT_PHY_VBOOST (0x5) + +#define TX_VBOOST_LVL_REG (0xf) +#define TX_VBOOST_LVL_START (6) +#define TX_VBOOST_LVL_ENABLE BIT(9) + +struct hi3670_priv { + struct device *dev; + struct regmap *peri_crg; + struct regmap *pctrl; + struct regmap *sctrl; + struct regmap *usb31misc; + + u32 eye_diagram_param; + u32 tx_vboost_lvl; + + u32 peri_crg_offset; + u32 pctrl_offset; + u32 usb31misc_offset; +}; + +static int hi3670_phy_cr_clk(struct regmap *usb31misc) +{ + int ret; + + /* Clock up */ + ret = regmap_update_bits(usb31misc, USB_MISC_CFG54, + CFG54_USB31PHY_CR_CLK, CFG54_USB31PHY_CR_CLK); + if (ret) + return ret; + + /* Clock down */ + ret = regmap_update_bits(usb31misc, USB_MISC_CFG54, + CFG54_USB31PHY_CR_CLK, 0); + + return ret; +} + +static int hi3670_phy_cr_set_sel(struct regmap *usb31misc) +{ + return regmap_update_bits(usb31misc, USB_MISC_CFG54, + CFG54_USB31PHY_CR_SEL, CFG54_USB31PHY_CR_SEL); +} + +static int hi3670_phy_cr_start(struct regmap *usb31misc, int direction) +{ + int ret, reg; + + if (direction) + reg = CFG54_USB31PHY_CR_WR_EN; + else + reg = CFG54_USB31PHY_CR_RD_EN; + + ret = regmap_update_bits(usb31misc, USB_MISC_CFG54, reg, reg); + + if (ret) + return ret; + + ret = hi3670_phy_cr_clk(usb31misc); + if (ret) + return ret; + + return regmap_update_bits(usb31misc, USB_MISC_CFG54, + CFG54_USB31PHY_CR_RD_EN | CFG54_USB31PHY_CR_WR_EN, 0); +} + +static int hi3670_phy_cr_wait_ack(struct regmap *usb31misc) +{ + u32 reg; + int retry = 10; + int ret; + + while (retry-- > 0) { + ret = regmap_read(usb31misc, USB_MISC_CFG54, ®); + if (ret) + return ret; + if ((reg & CFG54_USB31PHY_CR_ACK) == CFG54_USB31PHY_CR_ACK) + return 0; + + ret = hi3670_phy_cr_clk(usb31misc); + if (ret) + return ret; + + usleep_range(10, 20); + } + + return -ETIMEDOUT; +} + +static int hi3670_phy_cr_set_addr(struct regmap *usb31misc, u32 addr) +{ + u32 reg; + int ret; + + ret = regmap_read(usb31misc, USB_MISC_CFG54, ®); + if (ret) + return ret; + + reg = FIELD_PREP(CFG54_USB31PHY_CR_ADDR_MASK, addr); + ret = regmap_update_bits(usb31misc, USB_MISC_CFG54, + CFG54_USB31PHY_CR_ADDR_MASK, reg); + + return ret; +} + +static int hi3670_phy_cr_read(struct regmap *usb31misc, u32 addr, u32 *val) +{ + int reg; + int i; + int ret; + + for (i = 0; i < 100; i++) { + ret = hi3670_phy_cr_clk(usb31misc); + if (ret) + return ret; + } + + ret = hi3670_phy_cr_set_sel(usb31misc); + if (ret) + return ret; + + ret = hi3670_phy_cr_set_addr(usb31misc, addr); + if (ret) + return ret; + + ret = hi3670_phy_cr_start(usb31misc, 0); + if (ret) + return ret; + + ret = hi3670_phy_cr_wait_ack(usb31misc); + if (ret) + return ret; + + ret = regmap_read(usb31misc, USB_MISC_CFG58, ®); + if (ret) + return ret; + + *val = FIELD_GET(CFG58_USB31PHY_CR_DATA_MASK, reg); + + return 0; +} + +static int hi3670_phy_cr_write(struct regmap *usb31misc, u32 addr, u32 val) +{ + int i; + int ret; + + for (i = 0; i < 100; i++) { + ret = hi3670_phy_cr_clk(usb31misc); + if (ret) + return ret; + } + + ret = hi3670_phy_cr_set_sel(usb31misc); + if (ret) + return ret; + + ret = hi3670_phy_cr_set_addr(usb31misc, addr); + if (ret) + return ret; + + ret = regmap_write(usb31misc, USB_MISC_CFG58, + FIELD_PREP(CFG58_USB31PHY_CR_DATA_MASK, val)); + if (ret) + return ret; + + ret = hi3670_phy_cr_start(usb31misc, 1); + if (ret) + return ret; + + ret = hi3670_phy_cr_wait_ack(usb31misc); + + return ret; +} + +static int hi3670_phy_set_params(struct hi3670_priv *priv) +{ + u32 reg; + int ret; + int retry = 3; + + ret = regmap_write(priv->usb31misc, USB3OTG_CTRL4, + priv->eye_diagram_param); + if (ret) { + dev_err(priv->dev, "set USB3OTG_CTRL4 failed\n"); + return ret; + } + + while (retry-- > 0) { + ret = hi3670_phy_cr_read(priv->usb31misc, + TX_VBOOST_LVL_REG, ®); + if (!ret) + break; + + if (ret != -ETIMEDOUT) { + dev_err(priv->dev, "read TX_VBOOST_LVL_REG failed\n"); + return ret; + } + } + if (ret) + return ret; + + reg |= (TX_VBOOST_LVL_ENABLE | (priv->tx_vboost_lvl << TX_VBOOST_LVL_START)); + ret = hi3670_phy_cr_write(priv->usb31misc, TX_VBOOST_LVL_REG, reg); + if (ret) + dev_err(priv->dev, "write TX_VBOOST_LVL_REG failed\n"); + + return ret; +} + +static bool hi3670_is_abbclk_seleted(struct hi3670_priv *priv) +{ + u32 reg; + + if (!priv->sctrl) { + dev_err(priv->dev, "priv->sctrl is null!\n"); + return true; + } + + if (regmap_read(priv->sctrl, SCTRL_SCDEEPSLEEPED, ®)) { + dev_err(priv->dev, "SCTRL_SCDEEPSLEEPED read failed!\n"); + return true; + } + + if ((reg & USB_CLK_SELECTED) == 0) + return true; + + return false; +} + +static int hi3670_config_phy_clock(struct hi3670_priv *priv) +{ + u32 val, mask; + int ret; + + if (hi3670_is_abbclk_seleted(priv)) { + /* usb refclk iso disable */ + ret = regmap_write(priv->peri_crg, PERI_CRG_ISODIS, + USB_REFCLK_ISO_EN); + if (ret) + goto out; + + /* enable usb_tcxo_en */ + ret = regmap_write(priv->pctrl, PCTRL_PERI_CTRL3, + USB_TCXO_EN | + (USB_TCXO_EN << PCTRL_PERI_CTRL3_MSK_START)); + + /* select usbphy clk from abb */ + mask = SC_CLK_USB3PHY_3MUX1_SEL; + ret = regmap_update_bits(priv->pctrl, + PCTRL_PERI_CTRL24, mask, 0); + if (ret) + goto out; + + ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, + CFGA0_USB2PHY_REFCLK_SELECT, 0); + if (ret) + goto out; + + ret = regmap_read(priv->usb31misc, USB3OTG_CTRL7, &val); + if (ret) + goto out; + val &= ~CTRL7_USB2_REFCLKSEL_MASK; + val |= CTRL7_USB2_REFCLKSEL_ABB; + ret = regmap_write(priv->usb31misc, USB3OTG_CTRL7, val); + if (ret) + goto out; + + return 0; + } + + ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFG54, + CFG54_USB3PHY_REF_USE_PAD, + CFG54_USB3PHY_REF_USE_PAD); + if (ret) + goto out; + + ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, + CFGA0_USB2PHY_REFCLK_SELECT, + CFGA0_USB2PHY_REFCLK_SELECT); + if (ret) + goto out; + + ret = regmap_read(priv->usb31misc, USB3OTG_CTRL7, &val); + if (ret) + goto out; + val &= ~CTRL7_USB2_REFCLKSEL_MASK; + val |= CTRL7_USB2_REFCLKSEL_PAD; + ret = regmap_write(priv->usb31misc, USB3OTG_CTRL7, val); + if (ret) + goto out; + + ret = regmap_write(priv->peri_crg, + PERI_CRG_PEREN6, GT_CLK_USB2PHY_REF); + if (ret) + goto out; + + return 0; +out: + dev_err(priv->dev, "failed to config phy clock ret: %d\n", ret); + return ret; +} + +static int hi3670_config_tca(struct hi3670_priv *priv) +{ + u32 val, mask; + int ret; + + ret = regmap_write(priv->usb31misc, TCA_INTR_STS, 0xffff); + if (ret) + goto out; + + ret = regmap_write(priv->usb31misc, TCA_INTR_EN, + INTR_EN_XA_TIMEOUT_EVT_EN | INTR_EN_XA_ACK_EVT_EN); + if (ret) + goto out; + + mask = CLK_RST_TCA_REF_CLK_EN | CLK_RST_SUSPEND_CLK_EN; + ret = regmap_update_bits(priv->usb31misc, TCA_CLK_RST, mask, 0); + if (ret) + goto out; + + ret = regmap_update_bits(priv->usb31misc, TCA_GCFG, + GCFG_ROLE_HSTDEV | GCFG_OP_MODE, + GCFG_ROLE_HSTDEV | GCFG_OP_MODE_CTRL_SYNC_MODE); + if (ret) + goto out; + + ret = regmap_update_bits(priv->usb31misc, TCA_SYSMODE_CFG, + SYSMODE_CFG_TYPEC_DISABLE, 0); + if (ret) + goto out; + + ret = regmap_read(priv->usb31misc, TCA_TCPC, &val); + if (ret) + goto out; + val &= ~(TCPC_VALID | TCPC_LOW_POWER_EN | TCPC_MUX_CONTROL_MASK); + val |= (TCPC_VALID | TCPC_MUX_CONTROL_USB31); + ret = regmap_write(priv->usb31misc, TCA_TCPC, val); + if (ret) + goto out; + + ret = regmap_write(priv->usb31misc, TCA_VBUS_CTRL, + VBUS_CTRL_POWERPRESENT_OVERRD | VBUS_CTRL_VBUSVALID_OVERRD); + if (ret) + goto out; + + return 0; +out: + dev_err(priv->dev, "failed to config phy clock ret: %d\n", ret); + return ret; +} + +static int hi3670_phy_init(struct phy *phy) +{ + struct hi3670_priv *priv = phy_get_drvdata(phy); + u32 val; + int ret; + + /* assert controller */ + val = CFGA0_VAUX_RESET | CFGA0_USB31C_RESET | + CFGA0_USB3PHY_RESET | CFGA0_USB2PHY_POR; + ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, val, 0); + if (ret) + goto out; + + ret = hi3670_config_phy_clock(priv); + if (ret) + goto out; + + /* Exit from IDDQ mode */ + ret = regmap_update_bits(priv->usb31misc, USB3OTG_CTRL5, + CTRL5_USB2_SIDDQ, 0); + if (ret) + goto out; + + /* Release USB31 PHY out of TestPowerDown mode */ + ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFG50, + CFG50_USB3_PHY_TEST_POWERDOWN, 0); + if (ret) + goto out; + + /* Deassert phy */ + val = CFGA0_USB3PHY_RESET | CFGA0_USB2PHY_POR; + ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, val, val); + if (ret) + goto out; + + usleep_range(100, 120); + + /* Tell the PHY power is stable */ + val = CFG54_USB3_PHY0_ANA_PWR_EN | CFG54_PHY0_PCS_PWR_STABLE | + CFG54_PHY0_PMA_PWR_STABLE; + ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFG54, + val, val); + if (ret) + goto out; + + ret = hi3670_config_tca(priv); + if (ret) + goto out; + + /* Enable SSC */ + ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFG5C, + CFG5C_USB3_PHY0_SS_MPLLA_SSC_EN, + CFG5C_USB3_PHY0_SS_MPLLA_SSC_EN); + if (ret) + goto out; + + /* Deassert controller */ + val = CFGA0_VAUX_RESET | CFGA0_USB31C_RESET; + ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, val, val); + if (ret) + goto out; + + usleep_range(100, 120); + + /* Set fake vbus valid signal */ + val = CTRL0_USB3_VBUSVLD | CTRL0_USB3_VBUSVLD_SEL; + ret = regmap_update_bits(priv->usb31misc, USB3OTG_CTRL0, val, val); + if (ret) + goto out; + + val = CTRL3_USB2_VBUSVLDEXT0 | CTRL3_USB2_VBUSVLDEXTSEL0; + ret = regmap_update_bits(priv->usb31misc, USB3OTG_CTRL3, val, val); + if (ret) + goto out; + + usleep_range(100, 120); + + ret = hi3670_phy_set_params(priv); + if (ret) + goto out; + + return 0; +out: + dev_err(priv->dev, "failed to init phy ret: %d\n", ret); + return ret; +} + +static int hi3670_phy_exit(struct phy *phy) +{ + struct hi3670_priv *priv = phy_get_drvdata(phy); + u32 mask; + int ret; + + /* Assert phy */ + mask = CFGA0_USB3PHY_RESET | CFGA0_USB2PHY_POR; + ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, mask, 0); + if (ret) + goto out; + + if (hi3670_is_abbclk_seleted(priv)) { + /* disable usb_tcxo_en */ + ret = regmap_write(priv->pctrl, PCTRL_PERI_CTRL3, + USB_TCXO_EN << PCTRL_PERI_CTRL3_MSK_START); + } else { + ret = regmap_write(priv->peri_crg, PERI_CRG_PERDIS6, + GT_CLK_USB2PHY_REF); + if (ret) + goto out; + } + + return 0; +out: + dev_err(priv->dev, "failed to exit phy ret: %d\n", ret); + return ret; +} + +static struct phy_ops hi3670_phy_ops = { + .init = hi3670_phy_init, + .exit = hi3670_phy_exit, + .owner = THIS_MODULE, +}; + +static int hi3670_phy_probe(struct platform_device *pdev) +{ + struct phy_provider *phy_provider; + struct device *dev = &pdev->dev; + struct phy *phy; + struct hi3670_priv *priv; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + priv->peri_crg = syscon_regmap_lookup_by_phandle(dev->of_node, + "hisilicon,pericrg-syscon"); + if (IS_ERR(priv->peri_crg)) { + dev_err(dev, "no hisilicon,pericrg-syscon\n"); + return PTR_ERR(priv->peri_crg); + } + + priv->pctrl = syscon_regmap_lookup_by_phandle(dev->of_node, + "hisilicon,pctrl-syscon"); + if (IS_ERR(priv->pctrl)) { + dev_err(dev, "no hisilicon,pctrl-syscon\n"); + return PTR_ERR(priv->pctrl); + } + + priv->sctrl = syscon_regmap_lookup_by_phandle(dev->of_node, + "hisilicon,sctrl-syscon"); + if (IS_ERR(priv->sctrl)) { + dev_err(dev, "no hisilicon,sctrl-syscon\n"); + return PTR_ERR(priv->sctrl); + } + + /* node of hi3670 phy is a sub-node of usb3_otg_bc */ + priv->usb31misc = syscon_node_to_regmap(dev->parent->of_node); + if (IS_ERR(priv->usb31misc)) { + dev_err(dev, "no hisilicon,usb3-otg-bc-syscon\n"); + return PTR_ERR(priv->usb31misc); + } + + if (of_property_read_u32(dev->of_node, "hisilicon,eye-diagram-param", + &priv->eye_diagram_param)) + priv->eye_diagram_param = KIRIN970_USB_DEFAULT_PHY_PARAM; + + if (of_property_read_u32(dev->of_node, "hisilicon,tx-vboost-lvl", + &priv->tx_vboost_lvl)) + priv->tx_vboost_lvl = KIRIN970_USB_DEFAULT_PHY_VBOOST; + + phy = devm_phy_create(dev, NULL, &hi3670_phy_ops); + if (IS_ERR(phy)) + return PTR_ERR(phy); + + phy_set_drvdata(phy, priv); + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id hi3670_phy_of_match[] = { + { .compatible = "hisilicon,hi3670-usb-phy" }, + { }, +}; +MODULE_DEVICE_TABLE(of, hi3670_phy_of_match); + +static struct platform_driver hi3670_phy_driver = { + .probe = hi3670_phy_probe, + .driver = { + .name = "hi3670-usb-phy", + .of_match_table = hi3670_phy_of_match, + } +}; +module_platform_driver(hi3670_phy_driver); + +MODULE_AUTHOR("Yu Chen <chenyu56@huawei.com>"); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Hilisicon Kirin970 USB31 PHY Driver"); diff --git a/drivers/staging/hikey9xx/Kconfig b/drivers/staging/hikey9xx/Kconfig index b29f5d5df134..0e97b5b9a56a 100644 --- a/drivers/staging/hikey9xx/Kconfig +++ b/drivers/staging/hikey9xx/Kconfig @@ -1,16 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -# to be placed at drivers/phy -config PHY_HI3670_USB - tristate "hi3670 USB PHY support" - depends on (ARCH_HISI && ARM64) || COMPILE_TEST - select GENERIC_PHY - select MFD_SYSCON - help - Enable this to support the HISILICON HI3670 USB PHY. - - To compile this driver as a module, choose M here. - # to be placed at drivers/spmi config SPMI_HISI3670 tristate "Hisilicon 3670 SPMI Controller" diff --git a/drivers/staging/hikey9xx/Makefile b/drivers/staging/hikey9xx/Makefile index 1924fadac952..9371dcc3d35b 100644 --- a/drivers/staging/hikey9xx/Makefile +++ b/drivers/staging/hikey9xx/Makefile @@ -1,7 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_PHY_HI3670_USB) += phy-hi3670-usb3.o - obj-$(CONFIG_SPMI_HISI3670) += hisi-spmi-controller.o obj-$(CONFIG_MFD_HI6421_SPMI) += hi6421-spmi-pmic.o obj-$(CONFIG_REGULATOR_HI6421V600) += hi6421v600-regulator.o diff --git a/drivers/staging/hikey9xx/phy-hi3670-usb3.c b/drivers/staging/hikey9xx/phy-hi3670-usb3.c deleted file mode 100644 index b5fed306fcbf..000000000000 --- a/drivers/staging/hikey9xx/phy-hi3670-usb3.c +++ /dev/null @@ -1,668 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Phy provider for USB 3.1 controller on HiSilicon Kirin970 platform - * - * Copyright (C) 2017-2020 Hilisicon Electronics Co., Ltd. - * http://www.huawei.com - * - * Authors: Yu Chen <chenyu56@huawei.com> - */ - -#include <linux/bitfield.h> -#include <linux/clk.h> -#include <linux/kernel.h> -#include <linux/mfd/syscon.h> -#include <linux/module.h> -#include <linux/phy/phy.h> -#include <linux/platform_device.h> -#include <linux/regmap.h> - -#define SCTRL_SCDEEPSLEEPED (0x0) -#define USB_CLK_SELECTED BIT(20) - -#define PERI_CRG_PEREN0 (0x00) -#define PERI_CRG_PERDIS0 (0x04) -#define PERI_CRG_PEREN4 (0x40) -#define PERI_CRG_PERDIS4 (0x44) -#define PERI_CRG_PERRSTEN4 (0x90) -#define PERI_CRG_PERRSTDIS4 (0x94) -#define PERI_CRG_ISODIS (0x148) -#define PERI_CRG_PEREN6 (0x410) -#define PERI_CRG_PERDIS6 (0x414) - -#define USB_REFCLK_ISO_EN BIT(25) - -#define GT_CLK_USB2PHY_REF BIT(19) - -#define PCTRL_PERI_CTRL3 (0x10) -#define PCTRL_PERI_CTRL3_MSK_START (16) -#define USB_TCXO_EN BIT(1) - -#define PCTRL_PERI_CTRL24 (0x64) -#define SC_CLK_USB3PHY_3MUX1_SEL BIT(25) - -#define USB3OTG_CTRL0 (0x00) -#define USB3OTG_CTRL3 (0x0c) -#define USB3OTG_CTRL4 (0x10) -#define USB3OTG_CTRL5 (0x14) -#define USB3OTG_CTRL7 (0x1c) -#define USB_MISC_CFG50 (0x50) -#define USB_MISC_CFG54 (0x54) -#define USB_MISC_CFG58 (0x58) -#define USB_MISC_CFG5C (0x5c) -#define USB_MISC_CFGA0 (0xa0) -#define TCA_CLK_RST (0x200) -#define TCA_INTR_EN (0x204) -#define TCA_INTR_STS (0x208) -#define TCA_GCFG (0x210) -#define TCA_TCPC (0x214) -#define TCA_SYSMODE_CFG (0x218) -#define TCA_VBUS_CTRL (0x240) - -#define CTRL0_USB3_VBUSVLD BIT(7) -#define CTRL0_USB3_VBUSVLD_SEL BIT(6) - -#define CTRL3_USB2_VBUSVLDEXT0 BIT(6) -#define CTRL3_USB2_VBUSVLDEXTSEL0 BIT(5) - -#define CTRL5_USB2_SIDDQ BIT(0) - -#define CTRL7_USB2_REFCLKSEL_MASK GENMASK(4, 3) -#define CTRL7_USB2_REFCLKSEL_ABB (BIT(4) | BIT(3)) -#define CTRL7_USB2_REFCLKSEL_PAD BIT(4) - -#define CFG50_USB3_PHY_TEST_POWERDOWN BIT(23) - -#define CFG54_USB31PHY_CR_ADDR_MASK GENMASK(31, 16) - -#define CFG54_USB3PHY_REF_USE_PAD BIT(12) -#define CFG54_PHY0_PMA_PWR_STABLE BIT(11) -#define CFG54_PHY0_PCS_PWR_STABLE BIT(9) -#define CFG54_USB31PHY_CR_ACK BIT(7) -#define CFG54_USB31PHY_CR_WR_EN BIT(5) -#define CFG54_USB31PHY_CR_SEL BIT(4) -#define CFG54_USB31PHY_CR_RD_EN BIT(3) -#define CFG54_USB31PHY_CR_CLK BIT(2) -#define CFG54_USB3_PHY0_ANA_PWR_EN BIT(1) - -#define CFG58_USB31PHY_CR_DATA_MASK GENMASK(31, 16) - -#define CFG5C_USB3_PHY0_SS_MPLLA_SSC_EN BIT(1) - -#define CFGA0_VAUX_RESET BIT(9) -#define CFGA0_USB31C_RESET BIT(8) -#define CFGA0_USB2PHY_REFCLK_SELECT BIT(4) -#define CFGA0_USB3PHY_RESET BIT(1) -#define CFGA0_USB2PHY_POR BIT(0) - -#define INTR_EN_XA_TIMEOUT_EVT_EN BIT(1) -#define INTR_EN_XA_ACK_EVT_EN BIT(0) - -#define CLK_RST_TCA_REF_CLK_EN BIT(1) -#define CLK_RST_SUSPEND_CLK_EN BIT(0) - -#define GCFG_ROLE_HSTDEV BIT(4) -#define GCFG_OP_MODE GENMASK(1, 0) -#define GCFG_OP_MODE_CTRL_SYNC_MODE BIT(0) - -#define TCPC_VALID BIT(4) -#define TCPC_LOW_POWER_EN BIT(3) -#define TCPC_MUX_CONTROL_MASK GENMASK(1, 0) -#define TCPC_MUX_CONTROL_USB31 BIT(0) - -#define SYSMODE_CFG_TYPEC_DISABLE BIT(3) - -#define VBUS_CTRL_POWERPRESENT_OVERRD GENMASK(3, 2) -#define VBUS_CTRL_VBUSVALID_OVERRD GENMASK(1, 0) - -#define KIRIN970_USB_DEFAULT_PHY_PARAM (0xfdfee4) -#define KIRIN970_USB_DEFAULT_PHY_VBOOST (0x5) - -#define TX_VBOOST_LVL_REG (0xf) -#define TX_VBOOST_LVL_START (6) -#define TX_VBOOST_LVL_ENABLE BIT(9) - -struct hi3670_priv { - struct device *dev; - struct regmap *peri_crg; - struct regmap *pctrl; - struct regmap *sctrl; - struct regmap *usb31misc; - - u32 eye_diagram_param; - u32 tx_vboost_lvl; - - u32 peri_crg_offset; - u32 pctrl_offset; - u32 usb31misc_offset; -}; - -static int hi3670_phy_cr_clk(struct regmap *usb31misc) -{ - int ret; - - /* Clock up */ - ret = regmap_update_bits(usb31misc, USB_MISC_CFG54, - CFG54_USB31PHY_CR_CLK, CFG54_USB31PHY_CR_CLK); - if (ret) - return ret; - - /* Clock down */ - ret = regmap_update_bits(usb31misc, USB_MISC_CFG54, - CFG54_USB31PHY_CR_CLK, 0); - - return ret; -} - -static int hi3670_phy_cr_set_sel(struct regmap *usb31misc) -{ - return regmap_update_bits(usb31misc, USB_MISC_CFG54, - CFG54_USB31PHY_CR_SEL, CFG54_USB31PHY_CR_SEL); -} - -static int hi3670_phy_cr_start(struct regmap *usb31misc, int direction) -{ - int ret, reg; - - if (direction) - reg = CFG54_USB31PHY_CR_WR_EN; - else - reg = CFG54_USB31PHY_CR_RD_EN; - - ret = regmap_update_bits(usb31misc, USB_MISC_CFG54, reg, reg); - - if (ret) - return ret; - - ret = hi3670_phy_cr_clk(usb31misc); - if (ret) - return ret; - - return regmap_update_bits(usb31misc, USB_MISC_CFG54, - CFG54_USB31PHY_CR_RD_EN | CFG54_USB31PHY_CR_WR_EN, 0); -} - -static int hi3670_phy_cr_wait_ack(struct regmap *usb31misc) -{ - u32 reg; - int retry = 10; - int ret; - - while (retry-- > 0) { - ret = regmap_read(usb31misc, USB_MISC_CFG54, ®); - if (ret) - return ret; - if ((reg & CFG54_USB31PHY_CR_ACK) == CFG54_USB31PHY_CR_ACK) - return 0; - - ret = hi3670_phy_cr_clk(usb31misc); - if (ret) - return ret; - - usleep_range(10, 20); - } - - return -ETIMEDOUT; -} - -static int hi3670_phy_cr_set_addr(struct regmap *usb31misc, u32 addr) -{ - u32 reg; - int ret; - - ret = regmap_read(usb31misc, USB_MISC_CFG54, ®); - if (ret) - return ret; - - reg = FIELD_PREP(CFG54_USB31PHY_CR_ADDR_MASK, addr); - ret = regmap_update_bits(usb31misc, USB_MISC_CFG54, - CFG54_USB31PHY_CR_ADDR_MASK, reg); - - return ret; -} - -static int hi3670_phy_cr_read(struct regmap *usb31misc, u32 addr, u32 *val) -{ - int reg; - int i; - int ret; - - for (i = 0; i < 100; i++) { - ret = hi3670_phy_cr_clk(usb31misc); - if (ret) - return ret; - } - - ret = hi3670_phy_cr_set_sel(usb31misc); - if (ret) - return ret; - - ret = hi3670_phy_cr_set_addr(usb31misc, addr); - if (ret) - return ret; - - ret = hi3670_phy_cr_start(usb31misc, 0); - if (ret) - return ret; - - ret = hi3670_phy_cr_wait_ack(usb31misc); - if (ret) - return ret; - - ret = regmap_read(usb31misc, USB_MISC_CFG58, ®); - if (ret) - return ret; - - *val = FIELD_GET(CFG58_USB31PHY_CR_DATA_MASK, reg); - - return 0; -} - -static int hi3670_phy_cr_write(struct regmap *usb31misc, u32 addr, u32 val) -{ - int i; - int ret; - - for (i = 0; i < 100; i++) { - ret = hi3670_phy_cr_clk(usb31misc); - if (ret) - return ret; - } - - ret = hi3670_phy_cr_set_sel(usb31misc); - if (ret) - return ret; - - ret = hi3670_phy_cr_set_addr(usb31misc, addr); - if (ret) - return ret; - - ret = regmap_write(usb31misc, USB_MISC_CFG58, - FIELD_PREP(CFG58_USB31PHY_CR_DATA_MASK, val)); - if (ret) - return ret; - - ret = hi3670_phy_cr_start(usb31misc, 1); - if (ret) - return ret; - - ret = hi3670_phy_cr_wait_ack(usb31misc); - - return ret; -} - -static int hi3670_phy_set_params(struct hi3670_priv *priv) -{ - u32 reg; - int ret; - int retry = 3; - - ret = regmap_write(priv->usb31misc, USB3OTG_CTRL4, - priv->eye_diagram_param); - if (ret) { - dev_err(priv->dev, "set USB3OTG_CTRL4 failed\n"); - return ret; - } - - while (retry-- > 0) { - ret = hi3670_phy_cr_read(priv->usb31misc, - TX_VBOOST_LVL_REG, ®); - if (!ret) - break; - - if (ret != -ETIMEDOUT) { - dev_err(priv->dev, "read TX_VBOOST_LVL_REG failed\n"); - return ret; - } - } - if (ret) - return ret; - - reg |= (TX_VBOOST_LVL_ENABLE | (priv->tx_vboost_lvl << TX_VBOOST_LVL_START)); - ret = hi3670_phy_cr_write(priv->usb31misc, TX_VBOOST_LVL_REG, reg); - if (ret) - dev_err(priv->dev, "write TX_VBOOST_LVL_REG failed\n"); - - return ret; -} - -static bool hi3670_is_abbclk_seleted(struct hi3670_priv *priv) -{ - u32 reg; - - if (!priv->sctrl) { - dev_err(priv->dev, "priv->sctrl is null!\n"); - return true; - } - - if (regmap_read(priv->sctrl, SCTRL_SCDEEPSLEEPED, ®)) { - dev_err(priv->dev, "SCTRL_SCDEEPSLEEPED read failed!\n"); - return true; - } - - if ((reg & USB_CLK_SELECTED) == 0) - return true; - - return false; -} - -static int hi3670_config_phy_clock(struct hi3670_priv *priv) -{ - u32 val, mask; - int ret; - - if (hi3670_is_abbclk_seleted(priv)) { - /* usb refclk iso disable */ - ret = regmap_write(priv->peri_crg, PERI_CRG_ISODIS, - USB_REFCLK_ISO_EN); - if (ret) - goto out; - - /* enable usb_tcxo_en */ - ret = regmap_write(priv->pctrl, PCTRL_PERI_CTRL3, - USB_TCXO_EN | - (USB_TCXO_EN << PCTRL_PERI_CTRL3_MSK_START)); - - /* select usbphy clk from abb */ - mask = SC_CLK_USB3PHY_3MUX1_SEL; - ret = regmap_update_bits(priv->pctrl, - PCTRL_PERI_CTRL24, mask, 0); - if (ret) - goto out; - - ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, - CFGA0_USB2PHY_REFCLK_SELECT, 0); - if (ret) - goto out; - - ret = regmap_read(priv->usb31misc, USB3OTG_CTRL7, &val); - if (ret) - goto out; - val &= ~CTRL7_USB2_REFCLKSEL_MASK; - val |= CTRL7_USB2_REFCLKSEL_ABB; - ret = regmap_write(priv->usb31misc, USB3OTG_CTRL7, val); - if (ret) - goto out; - - return 0; - } - - ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFG54, - CFG54_USB3PHY_REF_USE_PAD, - CFG54_USB3PHY_REF_USE_PAD); - if (ret) - goto out; - - ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, - CFGA0_USB2PHY_REFCLK_SELECT, - CFGA0_USB2PHY_REFCLK_SELECT); - if (ret) - goto out; - - ret = regmap_read(priv->usb31misc, USB3OTG_CTRL7, &val); - if (ret) - goto out; - val &= ~CTRL7_USB2_REFCLKSEL_MASK; - val |= CTRL7_USB2_REFCLKSEL_PAD; - ret = regmap_write(priv->usb31misc, USB3OTG_CTRL7, val); - if (ret) - goto out; - - ret = regmap_write(priv->peri_crg, - PERI_CRG_PEREN6, GT_CLK_USB2PHY_REF); - if (ret) - goto out; - - return 0; -out: - dev_err(priv->dev, "failed to config phy clock ret: %d\n", ret); - return ret; -} - -static int hi3670_config_tca(struct hi3670_priv *priv) -{ - u32 val, mask; - int ret; - - ret = regmap_write(priv->usb31misc, TCA_INTR_STS, 0xffff); - if (ret) - goto out; - - ret = regmap_write(priv->usb31misc, TCA_INTR_EN, - INTR_EN_XA_TIMEOUT_EVT_EN | INTR_EN_XA_ACK_EVT_EN); - if (ret) - goto out; - - mask = CLK_RST_TCA_REF_CLK_EN | CLK_RST_SUSPEND_CLK_EN; - ret = regmap_update_bits(priv->usb31misc, TCA_CLK_RST, mask, 0); - if (ret) - goto out; - - ret = regmap_update_bits(priv->usb31misc, TCA_GCFG, - GCFG_ROLE_HSTDEV | GCFG_OP_MODE, - GCFG_ROLE_HSTDEV | GCFG_OP_MODE_CTRL_SYNC_MODE); - if (ret) - goto out; - - ret = regmap_update_bits(priv->usb31misc, TCA_SYSMODE_CFG, - SYSMODE_CFG_TYPEC_DISABLE, 0); - if (ret) - goto out; - - ret = regmap_read(priv->usb31misc, TCA_TCPC, &val); - if (ret) - goto out; - val &= ~(TCPC_VALID | TCPC_LOW_POWER_EN | TCPC_MUX_CONTROL_MASK); - val |= (TCPC_VALID | TCPC_MUX_CONTROL_USB31); - ret = regmap_write(priv->usb31misc, TCA_TCPC, val); - if (ret) - goto out; - - ret = regmap_write(priv->usb31misc, TCA_VBUS_CTRL, - VBUS_CTRL_POWERPRESENT_OVERRD | VBUS_CTRL_VBUSVALID_OVERRD); - if (ret) - goto out; - - return 0; -out: - dev_err(priv->dev, "failed to config phy clock ret: %d\n", ret); - return ret; -} - -static int hi3670_phy_init(struct phy *phy) -{ - struct hi3670_priv *priv = phy_get_drvdata(phy); - u32 val; - int ret; - - /* assert controller */ - val = CFGA0_VAUX_RESET | CFGA0_USB31C_RESET | - CFGA0_USB3PHY_RESET | CFGA0_USB2PHY_POR; - ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, val, 0); - if (ret) - goto out; - - ret = hi3670_config_phy_clock(priv); - if (ret) - goto out; - - /* Exit from IDDQ mode */ - ret = regmap_update_bits(priv->usb31misc, USB3OTG_CTRL5, - CTRL5_USB2_SIDDQ, 0); - if (ret) - goto out; - - /* Release USB31 PHY out of TestPowerDown mode */ - ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFG50, - CFG50_USB3_PHY_TEST_POWERDOWN, 0); - if (ret) - goto out; - - /* Deassert phy */ - val = CFGA0_USB3PHY_RESET | CFGA0_USB2PHY_POR; - ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, val, val); - if (ret) - goto out; - - usleep_range(100, 120); - - /* Tell the PHY power is stable */ - val = CFG54_USB3_PHY0_ANA_PWR_EN | CFG54_PHY0_PCS_PWR_STABLE | - CFG54_PHY0_PMA_PWR_STABLE; - ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFG54, - val, val); - if (ret) - goto out; - - ret = hi3670_config_tca(priv); - if (ret) - goto out; - - /* Enable SSC */ - ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFG5C, - CFG5C_USB3_PHY0_SS_MPLLA_SSC_EN, - CFG5C_USB3_PHY0_SS_MPLLA_SSC_EN); - if (ret) - goto out; - - /* Deassert controller */ - val = CFGA0_VAUX_RESET | CFGA0_USB31C_RESET; - ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, val, val); - if (ret) - goto out; - - usleep_range(100, 120); - - /* Set fake vbus valid signal */ - val = CTRL0_USB3_VBUSVLD | CTRL0_USB3_VBUSVLD_SEL; - ret = regmap_update_bits(priv->usb31misc, USB3OTG_CTRL0, val, val); - if (ret) - goto out; - - val = CTRL3_USB2_VBUSVLDEXT0 | CTRL3_USB2_VBUSVLDEXTSEL0; - ret = regmap_update_bits(priv->usb31misc, USB3OTG_CTRL3, val, val); - if (ret) - goto out; - - usleep_range(100, 120); - - ret = hi3670_phy_set_params(priv); - if (ret) - goto out; - - return 0; -out: - dev_err(priv->dev, "failed to init phy ret: %d\n", ret); - return ret; -} - -static int hi3670_phy_exit(struct phy *phy) -{ - struct hi3670_priv *priv = phy_get_drvdata(phy); - u32 mask; - int ret; - - /* Assert phy */ - mask = CFGA0_USB3PHY_RESET | CFGA0_USB2PHY_POR; - ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, mask, 0); - if (ret) - goto out; - - if (hi3670_is_abbclk_seleted(priv)) { - /* disable usb_tcxo_en */ - ret = regmap_write(priv->pctrl, PCTRL_PERI_CTRL3, - USB_TCXO_EN << PCTRL_PERI_CTRL3_MSK_START); - } else { - ret = regmap_write(priv->peri_crg, PERI_CRG_PERDIS6, - GT_CLK_USB2PHY_REF); - if (ret) - goto out; - } - - return 0; -out: - dev_err(priv->dev, "failed to exit phy ret: %d\n", ret); - return ret; -} - -static struct phy_ops hi3670_phy_ops = { - .init = hi3670_phy_init, - .exit = hi3670_phy_exit, - .owner = THIS_MODULE, -}; - -static int hi3670_phy_probe(struct platform_device *pdev) -{ - struct phy_provider *phy_provider; - struct device *dev = &pdev->dev; - struct phy *phy; - struct hi3670_priv *priv; - - priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; - - priv->dev = dev; - priv->peri_crg = syscon_regmap_lookup_by_phandle(dev->of_node, - "hisilicon,pericrg-syscon"); - if (IS_ERR(priv->peri_crg)) { - dev_err(dev, "no hisilicon,pericrg-syscon\n"); - return PTR_ERR(priv->peri_crg); - } - - priv->pctrl = syscon_regmap_lookup_by_phandle(dev->of_node, - "hisilicon,pctrl-syscon"); - if (IS_ERR(priv->pctrl)) { - dev_err(dev, "no hisilicon,pctrl-syscon\n"); - return PTR_ERR(priv->pctrl); - } - - priv->sctrl = syscon_regmap_lookup_by_phandle(dev->of_node, - "hisilicon,sctrl-syscon"); - if (IS_ERR(priv->sctrl)) { - dev_err(dev, "no hisilicon,sctrl-syscon\n"); - return PTR_ERR(priv->sctrl); - } - - /* node of hi3670 phy is a sub-node of usb3_otg_bc */ - priv->usb31misc = syscon_node_to_regmap(dev->parent->of_node); - if (IS_ERR(priv->usb31misc)) { - dev_err(dev, "no hisilicon,usb3-otg-bc-syscon\n"); - return PTR_ERR(priv->usb31misc); - } - - if (of_property_read_u32(dev->of_node, "hisilicon,eye-diagram-param", - &priv->eye_diagram_param)) - priv->eye_diagram_param = KIRIN970_USB_DEFAULT_PHY_PARAM; - - if (of_property_read_u32(dev->of_node, "hisilicon,tx-vboost-lvl", - &priv->tx_vboost_lvl)) - priv->tx_vboost_lvl = KIRIN970_USB_DEFAULT_PHY_VBOOST; - - phy = devm_phy_create(dev, NULL, &hi3670_phy_ops); - if (IS_ERR(phy)) - return PTR_ERR(phy); - - phy_set_drvdata(phy, priv); - phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); - return PTR_ERR_OR_ZERO(phy_provider); -} - -static const struct of_device_id hi3670_phy_of_match[] = { - { .compatible = "hisilicon,hi3670-usb-phy" }, - { }, -}; -MODULE_DEVICE_TABLE(of, hi3670_phy_of_match); - -static struct platform_driver hi3670_phy_driver = { - .probe = hi3670_phy_probe, - .driver = { - .name = "hi3670-usb-phy", - .of_match_table = hi3670_phy_of_match, - } -}; -module_platform_driver(hi3670_phy_driver); - -MODULE_AUTHOR("Yu Chen <chenyu56@huawei.com>"); -MODULE_LICENSE("GPL v2"); -MODULE_DESCRIPTION("Hilisicon Kirin970 USB31 PHY Driver"); diff --git a/drivers/staging/hikey9xx/phy-hi3670-usb3.yaml b/drivers/staging/hikey9xx/phy-hi3670-usb3.yaml deleted file mode 100644 index 125a5d6546ae..000000000000 --- a/drivers/staging/hikey9xx/phy-hi3670-usb3.yaml +++ /dev/null @@ -1,72 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/phy/hisilicon,hi3670-usb3.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Hisilicon Kirin970 USB PHY - -maintainers: - - Mauro Carvalho Chehab <mchehab+huawei@kernel.org> -description: |+ - Bindings for USB3 PHY on HiSilicon Kirin 970. - -properties: - compatible: - const: hisilicon,hi3670-usb-phy - - "#phy-cells": - const: 0 - - hisilicon,pericrg-syscon: - $ref: '/schemas/types.yaml#/definitions/phandle' - description: phandle of syscon used to control iso refclk. - - hisilicon,pctrl-syscon: - $ref: '/schemas/types.yaml#/definitions/phandle' - description: phandle of syscon used to control usb tcxo. - - hisilicon,sctrl-syscon: - $ref: '/schemas/types.yaml#/definitions/phandle' - description: phandle of syscon used to control phy deep sleep. - - hisilicon,eye-diagram-param: - $ref: /schemas/types.yaml#/definitions/uint32 - description: Eye diagram for phy. - - hisilicon,tx-vboost-lvl: - $ref: /schemas/types.yaml#/definitions/uint32 - description: TX level vboost for phy. - -required: - - compatible - - hisilicon,pericrg-syscon - - hisilicon,pctrl-syscon - - hisilicon,sctrl-syscon - - hisilicon,eye-diagram-param - - hisilicon,tx-vboost-lvl - - "#phy-cells" - -additionalProperties: false - -examples: - - | - bus { - #address-cells = <2>; - #size-cells = <2>; - - usb3_otg_bc: usb3_otg_bc@ff200000 { - compatible = "syscon", "simple-mfd"; - reg = <0x0 0xff200000 0x0 0x1000>; - - usb_phy { - compatible = "hisilicon,hi3670-usb-phy"; - #phy-cells = <0>; - hisilicon,pericrg-syscon = <&crg_ctrl>; - hisilicon,pctrl-syscon = <&pctrl>; - hisilicon,sctrl-syscon = <&sctrl>; - hisilicon,eye-diagram-param = <0xfdfee4>; - hisilicon,tx-vboost-lvl = <0x5>; - }; - }; - }; -- 2.29.2 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v2 4/4] phy: phy-hi3670-usb3: move driver from staging into phy @ 2021-01-14 17:35 ` Mauro Carvalho Chehab 0 siblings, 0 replies; 25+ messages in thread From: Mauro Carvalho Chehab @ 2021-01-14 17:35 UTC (permalink / raw) To: Vinod Koul Cc: devel, devicetree, Mauro Carvalho Chehab, Greg Kroah-Hartman, Yu Chen, linux-kernel, Kishon Vijay Abraham I, Rob Herring, Alex Dewar The phy USB3 driver for Hisilicon 970 (hi3670) is ready for mainstream. Mode it from staging into the main driver's phy/ directory. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> --- .../bindings/phy/phy-hi3670-usb3.yaml | 72 ++ MAINTAINERS | 9 +- drivers/phy/hisilicon/Kconfig | 10 + drivers/phy/hisilicon/Makefile | 1 + drivers/phy/hisilicon/phy-hi3670-usb3.c | 668 ++++++++++++++++++ drivers/staging/hikey9xx/Kconfig | 11 - drivers/staging/hikey9xx/Makefile | 2 - drivers/staging/hikey9xx/phy-hi3670-usb3.c | 668 ------------------ drivers/staging/hikey9xx/phy-hi3670-usb3.yaml | 72 -- 9 files changed, 759 insertions(+), 754 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml create mode 100644 drivers/phy/hisilicon/phy-hi3670-usb3.c delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.c delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.yaml diff --git a/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml b/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml new file mode 100644 index 000000000000..125a5d6546ae --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/hisilicon,hi3670-usb3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Kirin970 USB PHY + +maintainers: + - Mauro Carvalho Chehab <mchehab+huawei@kernel.org> +description: |+ + Bindings for USB3 PHY on HiSilicon Kirin 970. + +properties: + compatible: + const: hisilicon,hi3670-usb-phy + + "#phy-cells": + const: 0 + + hisilicon,pericrg-syscon: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: phandle of syscon used to control iso refclk. + + hisilicon,pctrl-syscon: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: phandle of syscon used to control usb tcxo. + + hisilicon,sctrl-syscon: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: phandle of syscon used to control phy deep sleep. + + hisilicon,eye-diagram-param: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Eye diagram for phy. + + hisilicon,tx-vboost-lvl: + $ref: /schemas/types.yaml#/definitions/uint32 + description: TX level vboost for phy. + +required: + - compatible + - hisilicon,pericrg-syscon + - hisilicon,pctrl-syscon + - hisilicon,sctrl-syscon + - hisilicon,eye-diagram-param + - hisilicon,tx-vboost-lvl + - "#phy-cells" + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + usb3_otg_bc: usb3_otg_bc@ff200000 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0xff200000 0x0 0x1000>; + + usb_phy { + compatible = "hisilicon,hi3670-usb-phy"; + #phy-cells = <0>; + hisilicon,pericrg-syscon = <&crg_ctrl>; + hisilicon,pctrl-syscon = <&pctrl>; + hisilicon,sctrl-syscon = <&sctrl>; + hisilicon,eye-diagram-param = <0xfdfee4>; + hisilicon,tx-vboost-lvl = <0x5>; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 281de213ef47..8d858e8d5a52 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18088,7 +18088,7 @@ L: linux-usb@vger.kernel.org S: Maintained F: drivers/usb/roles/intel-xhci-usb-role-switch.c -USB IP DRIVER FOR HISILICON KIRIN +USB IP DRIVER FOR HISILICON KIRIN 960 M: Yu Chen <chenyu56@huawei.com> M: Binghui Wang <wangbinghui@hisilicon.com> L: linux-usb@vger.kernel.org @@ -18096,6 +18096,13 @@ S: Maintained F: Documentation/devicetree/bindings/phy/hisilicon,hi3660-usb3.yaml F: drivers/phy/hisilicon/phy-hi3660-usb3.c +USB IP DRIVER FOR HISILICON KIRIN 970 +M: Mauro Carvalho Chehab <mchehab@kernel.org> +L: linux-usb@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/phy/hisilicon,kirin970-usb3.yaml +F: drivers/phy/hisilicon/phy-kirin970-usb3.c + USB ISP116X DRIVER M: Olav Kongas <ok@artecdesign.ee> L: linux-usb@vger.kernel.org diff --git a/drivers/phy/hisilicon/Kconfig b/drivers/phy/hisilicon/Kconfig index 1c73053bcc98..4d008cfc279c 100644 --- a/drivers/phy/hisilicon/Kconfig +++ b/drivers/phy/hisilicon/Kconfig @@ -23,6 +23,16 @@ config PHY_HI3660_USB To compile this driver as a module, choose M here. +config PHY_HI3670_USB + tristate "hi3670 USB PHY support" + depends on (ARCH_HISI && ARM64) || COMPILE_TEST + select GENERIC_PHY + select MFD_SYSCON + help + Enable this to support the HISILICON HI3670 USB PHY. + + To compile this driver as a module, choose M here. + config PHY_HISTB_COMBPHY tristate "HiSilicon STB SoCs COMBPHY support" depends on (ARCH_HISI && ARM64) || COMPILE_TEST diff --git a/drivers/phy/hisilicon/Makefile b/drivers/phy/hisilicon/Makefile index 92e874ae9c74..51729868145b 100644 --- a/drivers/phy/hisilicon/Makefile +++ b/drivers/phy/hisilicon/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_PHY_HI6220_USB) += phy-hi6220-usb.o obj-$(CONFIG_PHY_HI3660_USB) += phy-hi3660-usb3.o +obj-$(CONFIG_PHY_HI3670_USB) += phy-hi3670-usb3.o obj-$(CONFIG_PHY_HISTB_COMBPHY) += phy-histb-combphy.o obj-$(CONFIG_PHY_HISI_INNO_USB2) += phy-hisi-inno-usb2.o obj-$(CONFIG_PHY_HIX5HD2_SATA) += phy-hix5hd2-sata.o diff --git a/drivers/phy/hisilicon/phy-hi3670-usb3.c b/drivers/phy/hisilicon/phy-hi3670-usb3.c new file mode 100644 index 000000000000..b5fed306fcbf --- /dev/null +++ b/drivers/phy/hisilicon/phy-hi3670-usb3.c @@ -0,0 +1,668 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Phy provider for USB 3.1 controller on HiSilicon Kirin970 platform + * + * Copyright (C) 2017-2020 Hilisicon Electronics Co., Ltd. + * http://www.huawei.com + * + * Authors: Yu Chen <chenyu56@huawei.com> + */ + +#include <linux/bitfield.h> +#include <linux/clk.h> +#include <linux/kernel.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/phy/phy.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#define SCTRL_SCDEEPSLEEPED (0x0) +#define USB_CLK_SELECTED BIT(20) + +#define PERI_CRG_PEREN0 (0x00) +#define PERI_CRG_PERDIS0 (0x04) +#define PERI_CRG_PEREN4 (0x40) +#define PERI_CRG_PERDIS4 (0x44) +#define PERI_CRG_PERRSTEN4 (0x90) +#define PERI_CRG_PERRSTDIS4 (0x94) +#define PERI_CRG_ISODIS (0x148) +#define PERI_CRG_PEREN6 (0x410) +#define PERI_CRG_PERDIS6 (0x414) + +#define USB_REFCLK_ISO_EN BIT(25) + +#define GT_CLK_USB2PHY_REF BIT(19) + +#define PCTRL_PERI_CTRL3 (0x10) +#define PCTRL_PERI_CTRL3_MSK_START (16) +#define USB_TCXO_EN BIT(1) + +#define PCTRL_PERI_CTRL24 (0x64) +#define SC_CLK_USB3PHY_3MUX1_SEL BIT(25) + +#define USB3OTG_CTRL0 (0x00) +#define USB3OTG_CTRL3 (0x0c) +#define USB3OTG_CTRL4 (0x10) +#define USB3OTG_CTRL5 (0x14) +#define USB3OTG_CTRL7 (0x1c) +#define USB_MISC_CFG50 (0x50) +#define USB_MISC_CFG54 (0x54) +#define USB_MISC_CFG58 (0x58) +#define USB_MISC_CFG5C (0x5c) +#define USB_MISC_CFGA0 (0xa0) +#define TCA_CLK_RST (0x200) +#define TCA_INTR_EN (0x204) +#define TCA_INTR_STS (0x208) +#define TCA_GCFG (0x210) +#define TCA_TCPC (0x214) +#define TCA_SYSMODE_CFG (0x218) +#define TCA_VBUS_CTRL (0x240) + +#define CTRL0_USB3_VBUSVLD BIT(7) +#define CTRL0_USB3_VBUSVLD_SEL BIT(6) + +#define CTRL3_USB2_VBUSVLDEXT0 BIT(6) +#define CTRL3_USB2_VBUSVLDEXTSEL0 BIT(5) + +#define CTRL5_USB2_SIDDQ BIT(0) + +#define CTRL7_USB2_REFCLKSEL_MASK GENMASK(4, 3) +#define CTRL7_USB2_REFCLKSEL_ABB (BIT(4) | BIT(3)) +#define CTRL7_USB2_REFCLKSEL_PAD BIT(4) + +#define CFG50_USB3_PHY_TEST_POWERDOWN BIT(23) + +#define CFG54_USB31PHY_CR_ADDR_MASK GENMASK(31, 16) + +#define CFG54_USB3PHY_REF_USE_PAD BIT(12) +#define CFG54_PHY0_PMA_PWR_STABLE BIT(11) +#define CFG54_PHY0_PCS_PWR_STABLE BIT(9) +#define CFG54_USB31PHY_CR_ACK BIT(7) +#define CFG54_USB31PHY_CR_WR_EN BIT(5) +#define CFG54_USB31PHY_CR_SEL BIT(4) +#define CFG54_USB31PHY_CR_RD_EN BIT(3) +#define CFG54_USB31PHY_CR_CLK BIT(2) +#define CFG54_USB3_PHY0_ANA_PWR_EN BIT(1) + +#define CFG58_USB31PHY_CR_DATA_MASK GENMASK(31, 16) + +#define CFG5C_USB3_PHY0_SS_MPLLA_SSC_EN BIT(1) + +#define CFGA0_VAUX_RESET BIT(9) +#define CFGA0_USB31C_RESET BIT(8) +#define CFGA0_USB2PHY_REFCLK_SELECT BIT(4) +#define CFGA0_USB3PHY_RESET BIT(1) +#define CFGA0_USB2PHY_POR BIT(0) + +#define INTR_EN_XA_TIMEOUT_EVT_EN BIT(1) +#define INTR_EN_XA_ACK_EVT_EN BIT(0) + +#define CLK_RST_TCA_REF_CLK_EN BIT(1) +#define CLK_RST_SUSPEND_CLK_EN BIT(0) + +#define GCFG_ROLE_HSTDEV BIT(4) +#define GCFG_OP_MODE GENMASK(1, 0) +#define GCFG_OP_MODE_CTRL_SYNC_MODE BIT(0) + +#define TCPC_VALID BIT(4) +#define TCPC_LOW_POWER_EN BIT(3) +#define TCPC_MUX_CONTROL_MASK GENMASK(1, 0) +#define TCPC_MUX_CONTROL_USB31 BIT(0) + +#define SYSMODE_CFG_TYPEC_DISABLE BIT(3) + +#define VBUS_CTRL_POWERPRESENT_OVERRD GENMASK(3, 2) +#define VBUS_CTRL_VBUSVALID_OVERRD GENMASK(1, 0) + +#define KIRIN970_USB_DEFAULT_PHY_PARAM (0xfdfee4) +#define KIRIN970_USB_DEFAULT_PHY_VBOOST (0x5) + +#define TX_VBOOST_LVL_REG (0xf) +#define TX_VBOOST_LVL_START (6) +#define TX_VBOOST_LVL_ENABLE BIT(9) + +struct hi3670_priv { + struct device *dev; + struct regmap *peri_crg; + struct regmap *pctrl; + struct regmap *sctrl; + struct regmap *usb31misc; + + u32 eye_diagram_param; + u32 tx_vboost_lvl; + + u32 peri_crg_offset; + u32 pctrl_offset; + u32 usb31misc_offset; +}; + +static int hi3670_phy_cr_clk(struct regmap *usb31misc) +{ + int ret; + + /* Clock up */ + ret = regmap_update_bits(usb31misc, USB_MISC_CFG54, + CFG54_USB31PHY_CR_CLK, CFG54_USB31PHY_CR_CLK); + if (ret) + return ret; + + /* Clock down */ + ret = regmap_update_bits(usb31misc, USB_MISC_CFG54, + CFG54_USB31PHY_CR_CLK, 0); + + return ret; +} + +static int hi3670_phy_cr_set_sel(struct regmap *usb31misc) +{ + return regmap_update_bits(usb31misc, USB_MISC_CFG54, + CFG54_USB31PHY_CR_SEL, CFG54_USB31PHY_CR_SEL); +} + +static int hi3670_phy_cr_start(struct regmap *usb31misc, int direction) +{ + int ret, reg; + + if (direction) + reg = CFG54_USB31PHY_CR_WR_EN; + else + reg = CFG54_USB31PHY_CR_RD_EN; + + ret = regmap_update_bits(usb31misc, USB_MISC_CFG54, reg, reg); + + if (ret) + return ret; + + ret = hi3670_phy_cr_clk(usb31misc); + if (ret) + return ret; + + return regmap_update_bits(usb31misc, USB_MISC_CFG54, + CFG54_USB31PHY_CR_RD_EN | CFG54_USB31PHY_CR_WR_EN, 0); +} + +static int hi3670_phy_cr_wait_ack(struct regmap *usb31misc) +{ + u32 reg; + int retry = 10; + int ret; + + while (retry-- > 0) { + ret = regmap_read(usb31misc, USB_MISC_CFG54, ®); + if (ret) + return ret; + if ((reg & CFG54_USB31PHY_CR_ACK) == CFG54_USB31PHY_CR_ACK) + return 0; + + ret = hi3670_phy_cr_clk(usb31misc); + if (ret) + return ret; + + usleep_range(10, 20); + } + + return -ETIMEDOUT; +} + +static int hi3670_phy_cr_set_addr(struct regmap *usb31misc, u32 addr) +{ + u32 reg; + int ret; + + ret = regmap_read(usb31misc, USB_MISC_CFG54, ®); + if (ret) + return ret; + + reg = FIELD_PREP(CFG54_USB31PHY_CR_ADDR_MASK, addr); + ret = regmap_update_bits(usb31misc, USB_MISC_CFG54, + CFG54_USB31PHY_CR_ADDR_MASK, reg); + + return ret; +} + +static int hi3670_phy_cr_read(struct regmap *usb31misc, u32 addr, u32 *val) +{ + int reg; + int i; + int ret; + + for (i = 0; i < 100; i++) { + ret = hi3670_phy_cr_clk(usb31misc); + if (ret) + return ret; + } + + ret = hi3670_phy_cr_set_sel(usb31misc); + if (ret) + return ret; + + ret = hi3670_phy_cr_set_addr(usb31misc, addr); + if (ret) + return ret; + + ret = hi3670_phy_cr_start(usb31misc, 0); + if (ret) + return ret; + + ret = hi3670_phy_cr_wait_ack(usb31misc); + if (ret) + return ret; + + ret = regmap_read(usb31misc, USB_MISC_CFG58, ®); + if (ret) + return ret; + + *val = FIELD_GET(CFG58_USB31PHY_CR_DATA_MASK, reg); + + return 0; +} + +static int hi3670_phy_cr_write(struct regmap *usb31misc, u32 addr, u32 val) +{ + int i; + int ret; + + for (i = 0; i < 100; i++) { + ret = hi3670_phy_cr_clk(usb31misc); + if (ret) + return ret; + } + + ret = hi3670_phy_cr_set_sel(usb31misc); + if (ret) + return ret; + + ret = hi3670_phy_cr_set_addr(usb31misc, addr); + if (ret) + return ret; + + ret = regmap_write(usb31misc, USB_MISC_CFG58, + FIELD_PREP(CFG58_USB31PHY_CR_DATA_MASK, val)); + if (ret) + return ret; + + ret = hi3670_phy_cr_start(usb31misc, 1); + if (ret) + return ret; + + ret = hi3670_phy_cr_wait_ack(usb31misc); + + return ret; +} + +static int hi3670_phy_set_params(struct hi3670_priv *priv) +{ + u32 reg; + int ret; + int retry = 3; + + ret = regmap_write(priv->usb31misc, USB3OTG_CTRL4, + priv->eye_diagram_param); + if (ret) { + dev_err(priv->dev, "set USB3OTG_CTRL4 failed\n"); + return ret; + } + + while (retry-- > 0) { + ret = hi3670_phy_cr_read(priv->usb31misc, + TX_VBOOST_LVL_REG, ®); + if (!ret) + break; + + if (ret != -ETIMEDOUT) { + dev_err(priv->dev, "read TX_VBOOST_LVL_REG failed\n"); + return ret; + } + } + if (ret) + return ret; + + reg |= (TX_VBOOST_LVL_ENABLE | (priv->tx_vboost_lvl << TX_VBOOST_LVL_START)); + ret = hi3670_phy_cr_write(priv->usb31misc, TX_VBOOST_LVL_REG, reg); + if (ret) + dev_err(priv->dev, "write TX_VBOOST_LVL_REG failed\n"); + + return ret; +} + +static bool hi3670_is_abbclk_seleted(struct hi3670_priv *priv) +{ + u32 reg; + + if (!priv->sctrl) { + dev_err(priv->dev, "priv->sctrl is null!\n"); + return true; + } + + if (regmap_read(priv->sctrl, SCTRL_SCDEEPSLEEPED, ®)) { + dev_err(priv->dev, "SCTRL_SCDEEPSLEEPED read failed!\n"); + return true; + } + + if ((reg & USB_CLK_SELECTED) == 0) + return true; + + return false; +} + +static int hi3670_config_phy_clock(struct hi3670_priv *priv) +{ + u32 val, mask; + int ret; + + if (hi3670_is_abbclk_seleted(priv)) { + /* usb refclk iso disable */ + ret = regmap_write(priv->peri_crg, PERI_CRG_ISODIS, + USB_REFCLK_ISO_EN); + if (ret) + goto out; + + /* enable usb_tcxo_en */ + ret = regmap_write(priv->pctrl, PCTRL_PERI_CTRL3, + USB_TCXO_EN | + (USB_TCXO_EN << PCTRL_PERI_CTRL3_MSK_START)); + + /* select usbphy clk from abb */ + mask = SC_CLK_USB3PHY_3MUX1_SEL; + ret = regmap_update_bits(priv->pctrl, + PCTRL_PERI_CTRL24, mask, 0); + if (ret) + goto out; + + ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, + CFGA0_USB2PHY_REFCLK_SELECT, 0); + if (ret) + goto out; + + ret = regmap_read(priv->usb31misc, USB3OTG_CTRL7, &val); + if (ret) + goto out; + val &= ~CTRL7_USB2_REFCLKSEL_MASK; + val |= CTRL7_USB2_REFCLKSEL_ABB; + ret = regmap_write(priv->usb31misc, USB3OTG_CTRL7, val); + if (ret) + goto out; + + return 0; + } + + ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFG54, + CFG54_USB3PHY_REF_USE_PAD, + CFG54_USB3PHY_REF_USE_PAD); + if (ret) + goto out; + + ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, + CFGA0_USB2PHY_REFCLK_SELECT, + CFGA0_USB2PHY_REFCLK_SELECT); + if (ret) + goto out; + + ret = regmap_read(priv->usb31misc, USB3OTG_CTRL7, &val); + if (ret) + goto out; + val &= ~CTRL7_USB2_REFCLKSEL_MASK; + val |= CTRL7_USB2_REFCLKSEL_PAD; + ret = regmap_write(priv->usb31misc, USB3OTG_CTRL7, val); + if (ret) + goto out; + + ret = regmap_write(priv->peri_crg, + PERI_CRG_PEREN6, GT_CLK_USB2PHY_REF); + if (ret) + goto out; + + return 0; +out: + dev_err(priv->dev, "failed to config phy clock ret: %d\n", ret); + return ret; +} + +static int hi3670_config_tca(struct hi3670_priv *priv) +{ + u32 val, mask; + int ret; + + ret = regmap_write(priv->usb31misc, TCA_INTR_STS, 0xffff); + if (ret) + goto out; + + ret = regmap_write(priv->usb31misc, TCA_INTR_EN, + INTR_EN_XA_TIMEOUT_EVT_EN | INTR_EN_XA_ACK_EVT_EN); + if (ret) + goto out; + + mask = CLK_RST_TCA_REF_CLK_EN | CLK_RST_SUSPEND_CLK_EN; + ret = regmap_update_bits(priv->usb31misc, TCA_CLK_RST, mask, 0); + if (ret) + goto out; + + ret = regmap_update_bits(priv->usb31misc, TCA_GCFG, + GCFG_ROLE_HSTDEV | GCFG_OP_MODE, + GCFG_ROLE_HSTDEV | GCFG_OP_MODE_CTRL_SYNC_MODE); + if (ret) + goto out; + + ret = regmap_update_bits(priv->usb31misc, TCA_SYSMODE_CFG, + SYSMODE_CFG_TYPEC_DISABLE, 0); + if (ret) + goto out; + + ret = regmap_read(priv->usb31misc, TCA_TCPC, &val); + if (ret) + goto out; + val &= ~(TCPC_VALID | TCPC_LOW_POWER_EN | TCPC_MUX_CONTROL_MASK); + val |= (TCPC_VALID | TCPC_MUX_CONTROL_USB31); + ret = regmap_write(priv->usb31misc, TCA_TCPC, val); + if (ret) + goto out; + + ret = regmap_write(priv->usb31misc, TCA_VBUS_CTRL, + VBUS_CTRL_POWERPRESENT_OVERRD | VBUS_CTRL_VBUSVALID_OVERRD); + if (ret) + goto out; + + return 0; +out: + dev_err(priv->dev, "failed to config phy clock ret: %d\n", ret); + return ret; +} + +static int hi3670_phy_init(struct phy *phy) +{ + struct hi3670_priv *priv = phy_get_drvdata(phy); + u32 val; + int ret; + + /* assert controller */ + val = CFGA0_VAUX_RESET | CFGA0_USB31C_RESET | + CFGA0_USB3PHY_RESET | CFGA0_USB2PHY_POR; + ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, val, 0); + if (ret) + goto out; + + ret = hi3670_config_phy_clock(priv); + if (ret) + goto out; + + /* Exit from IDDQ mode */ + ret = regmap_update_bits(priv->usb31misc, USB3OTG_CTRL5, + CTRL5_USB2_SIDDQ, 0); + if (ret) + goto out; + + /* Release USB31 PHY out of TestPowerDown mode */ + ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFG50, + CFG50_USB3_PHY_TEST_POWERDOWN, 0); + if (ret) + goto out; + + /* Deassert phy */ + val = CFGA0_USB3PHY_RESET | CFGA0_USB2PHY_POR; + ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, val, val); + if (ret) + goto out; + + usleep_range(100, 120); + + /* Tell the PHY power is stable */ + val = CFG54_USB3_PHY0_ANA_PWR_EN | CFG54_PHY0_PCS_PWR_STABLE | + CFG54_PHY0_PMA_PWR_STABLE; + ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFG54, + val, val); + if (ret) + goto out; + + ret = hi3670_config_tca(priv); + if (ret) + goto out; + + /* Enable SSC */ + ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFG5C, + CFG5C_USB3_PHY0_SS_MPLLA_SSC_EN, + CFG5C_USB3_PHY0_SS_MPLLA_SSC_EN); + if (ret) + goto out; + + /* Deassert controller */ + val = CFGA0_VAUX_RESET | CFGA0_USB31C_RESET; + ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, val, val); + if (ret) + goto out; + + usleep_range(100, 120); + + /* Set fake vbus valid signal */ + val = CTRL0_USB3_VBUSVLD | CTRL0_USB3_VBUSVLD_SEL; + ret = regmap_update_bits(priv->usb31misc, USB3OTG_CTRL0, val, val); + if (ret) + goto out; + + val = CTRL3_USB2_VBUSVLDEXT0 | CTRL3_USB2_VBUSVLDEXTSEL0; + ret = regmap_update_bits(priv->usb31misc, USB3OTG_CTRL3, val, val); + if (ret) + goto out; + + usleep_range(100, 120); + + ret = hi3670_phy_set_params(priv); + if (ret) + goto out; + + return 0; +out: + dev_err(priv->dev, "failed to init phy ret: %d\n", ret); + return ret; +} + +static int hi3670_phy_exit(struct phy *phy) +{ + struct hi3670_priv *priv = phy_get_drvdata(phy); + u32 mask; + int ret; + + /* Assert phy */ + mask = CFGA0_USB3PHY_RESET | CFGA0_USB2PHY_POR; + ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, mask, 0); + if (ret) + goto out; + + if (hi3670_is_abbclk_seleted(priv)) { + /* disable usb_tcxo_en */ + ret = regmap_write(priv->pctrl, PCTRL_PERI_CTRL3, + USB_TCXO_EN << PCTRL_PERI_CTRL3_MSK_START); + } else { + ret = regmap_write(priv->peri_crg, PERI_CRG_PERDIS6, + GT_CLK_USB2PHY_REF); + if (ret) + goto out; + } + + return 0; +out: + dev_err(priv->dev, "failed to exit phy ret: %d\n", ret); + return ret; +} + +static struct phy_ops hi3670_phy_ops = { + .init = hi3670_phy_init, + .exit = hi3670_phy_exit, + .owner = THIS_MODULE, +}; + +static int hi3670_phy_probe(struct platform_device *pdev) +{ + struct phy_provider *phy_provider; + struct device *dev = &pdev->dev; + struct phy *phy; + struct hi3670_priv *priv; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + priv->peri_crg = syscon_regmap_lookup_by_phandle(dev->of_node, + "hisilicon,pericrg-syscon"); + if (IS_ERR(priv->peri_crg)) { + dev_err(dev, "no hisilicon,pericrg-syscon\n"); + return PTR_ERR(priv->peri_crg); + } + + priv->pctrl = syscon_regmap_lookup_by_phandle(dev->of_node, + "hisilicon,pctrl-syscon"); + if (IS_ERR(priv->pctrl)) { + dev_err(dev, "no hisilicon,pctrl-syscon\n"); + return PTR_ERR(priv->pctrl); + } + + priv->sctrl = syscon_regmap_lookup_by_phandle(dev->of_node, + "hisilicon,sctrl-syscon"); + if (IS_ERR(priv->sctrl)) { + dev_err(dev, "no hisilicon,sctrl-syscon\n"); + return PTR_ERR(priv->sctrl); + } + + /* node of hi3670 phy is a sub-node of usb3_otg_bc */ + priv->usb31misc = syscon_node_to_regmap(dev->parent->of_node); + if (IS_ERR(priv->usb31misc)) { + dev_err(dev, "no hisilicon,usb3-otg-bc-syscon\n"); + return PTR_ERR(priv->usb31misc); + } + + if (of_property_read_u32(dev->of_node, "hisilicon,eye-diagram-param", + &priv->eye_diagram_param)) + priv->eye_diagram_param = KIRIN970_USB_DEFAULT_PHY_PARAM; + + if (of_property_read_u32(dev->of_node, "hisilicon,tx-vboost-lvl", + &priv->tx_vboost_lvl)) + priv->tx_vboost_lvl = KIRIN970_USB_DEFAULT_PHY_VBOOST; + + phy = devm_phy_create(dev, NULL, &hi3670_phy_ops); + if (IS_ERR(phy)) + return PTR_ERR(phy); + + phy_set_drvdata(phy, priv); + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id hi3670_phy_of_match[] = { + { .compatible = "hisilicon,hi3670-usb-phy" }, + { }, +}; +MODULE_DEVICE_TABLE(of, hi3670_phy_of_match); + +static struct platform_driver hi3670_phy_driver = { + .probe = hi3670_phy_probe, + .driver = { + .name = "hi3670-usb-phy", + .of_match_table = hi3670_phy_of_match, + } +}; +module_platform_driver(hi3670_phy_driver); + +MODULE_AUTHOR("Yu Chen <chenyu56@huawei.com>"); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Hilisicon Kirin970 USB31 PHY Driver"); diff --git a/drivers/staging/hikey9xx/Kconfig b/drivers/staging/hikey9xx/Kconfig index b29f5d5df134..0e97b5b9a56a 100644 --- a/drivers/staging/hikey9xx/Kconfig +++ b/drivers/staging/hikey9xx/Kconfig @@ -1,16 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -# to be placed at drivers/phy -config PHY_HI3670_USB - tristate "hi3670 USB PHY support" - depends on (ARCH_HISI && ARM64) || COMPILE_TEST - select GENERIC_PHY - select MFD_SYSCON - help - Enable this to support the HISILICON HI3670 USB PHY. - - To compile this driver as a module, choose M here. - # to be placed at drivers/spmi config SPMI_HISI3670 tristate "Hisilicon 3670 SPMI Controller" diff --git a/drivers/staging/hikey9xx/Makefile b/drivers/staging/hikey9xx/Makefile index 1924fadac952..9371dcc3d35b 100644 --- a/drivers/staging/hikey9xx/Makefile +++ b/drivers/staging/hikey9xx/Makefile @@ -1,7 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_PHY_HI3670_USB) += phy-hi3670-usb3.o - obj-$(CONFIG_SPMI_HISI3670) += hisi-spmi-controller.o obj-$(CONFIG_MFD_HI6421_SPMI) += hi6421-spmi-pmic.o obj-$(CONFIG_REGULATOR_HI6421V600) += hi6421v600-regulator.o diff --git a/drivers/staging/hikey9xx/phy-hi3670-usb3.c b/drivers/staging/hikey9xx/phy-hi3670-usb3.c deleted file mode 100644 index b5fed306fcbf..000000000000 --- a/drivers/staging/hikey9xx/phy-hi3670-usb3.c +++ /dev/null @@ -1,668 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Phy provider for USB 3.1 controller on HiSilicon Kirin970 platform - * - * Copyright (C) 2017-2020 Hilisicon Electronics Co., Ltd. - * http://www.huawei.com - * - * Authors: Yu Chen <chenyu56@huawei.com> - */ - -#include <linux/bitfield.h> -#include <linux/clk.h> -#include <linux/kernel.h> -#include <linux/mfd/syscon.h> -#include <linux/module.h> -#include <linux/phy/phy.h> -#include <linux/platform_device.h> -#include <linux/regmap.h> - -#define SCTRL_SCDEEPSLEEPED (0x0) -#define USB_CLK_SELECTED BIT(20) - -#define PERI_CRG_PEREN0 (0x00) -#define PERI_CRG_PERDIS0 (0x04) -#define PERI_CRG_PEREN4 (0x40) -#define PERI_CRG_PERDIS4 (0x44) -#define PERI_CRG_PERRSTEN4 (0x90) -#define PERI_CRG_PERRSTDIS4 (0x94) -#define PERI_CRG_ISODIS (0x148) -#define PERI_CRG_PEREN6 (0x410) -#define PERI_CRG_PERDIS6 (0x414) - -#define USB_REFCLK_ISO_EN BIT(25) - -#define GT_CLK_USB2PHY_REF BIT(19) - -#define PCTRL_PERI_CTRL3 (0x10) -#define PCTRL_PERI_CTRL3_MSK_START (16) -#define USB_TCXO_EN BIT(1) - -#define PCTRL_PERI_CTRL24 (0x64) -#define SC_CLK_USB3PHY_3MUX1_SEL BIT(25) - -#define USB3OTG_CTRL0 (0x00) -#define USB3OTG_CTRL3 (0x0c) -#define USB3OTG_CTRL4 (0x10) -#define USB3OTG_CTRL5 (0x14) -#define USB3OTG_CTRL7 (0x1c) -#define USB_MISC_CFG50 (0x50) -#define USB_MISC_CFG54 (0x54) -#define USB_MISC_CFG58 (0x58) -#define USB_MISC_CFG5C (0x5c) -#define USB_MISC_CFGA0 (0xa0) -#define TCA_CLK_RST (0x200) -#define TCA_INTR_EN (0x204) -#define TCA_INTR_STS (0x208) -#define TCA_GCFG (0x210) -#define TCA_TCPC (0x214) -#define TCA_SYSMODE_CFG (0x218) -#define TCA_VBUS_CTRL (0x240) - -#define CTRL0_USB3_VBUSVLD BIT(7) -#define CTRL0_USB3_VBUSVLD_SEL BIT(6) - -#define CTRL3_USB2_VBUSVLDEXT0 BIT(6) -#define CTRL3_USB2_VBUSVLDEXTSEL0 BIT(5) - -#define CTRL5_USB2_SIDDQ BIT(0) - -#define CTRL7_USB2_REFCLKSEL_MASK GENMASK(4, 3) -#define CTRL7_USB2_REFCLKSEL_ABB (BIT(4) | BIT(3)) -#define CTRL7_USB2_REFCLKSEL_PAD BIT(4) - -#define CFG50_USB3_PHY_TEST_POWERDOWN BIT(23) - -#define CFG54_USB31PHY_CR_ADDR_MASK GENMASK(31, 16) - -#define CFG54_USB3PHY_REF_USE_PAD BIT(12) -#define CFG54_PHY0_PMA_PWR_STABLE BIT(11) -#define CFG54_PHY0_PCS_PWR_STABLE BIT(9) -#define CFG54_USB31PHY_CR_ACK BIT(7) -#define CFG54_USB31PHY_CR_WR_EN BIT(5) -#define CFG54_USB31PHY_CR_SEL BIT(4) -#define CFG54_USB31PHY_CR_RD_EN BIT(3) -#define CFG54_USB31PHY_CR_CLK BIT(2) -#define CFG54_USB3_PHY0_ANA_PWR_EN BIT(1) - -#define CFG58_USB31PHY_CR_DATA_MASK GENMASK(31, 16) - -#define CFG5C_USB3_PHY0_SS_MPLLA_SSC_EN BIT(1) - -#define CFGA0_VAUX_RESET BIT(9) -#define CFGA0_USB31C_RESET BIT(8) -#define CFGA0_USB2PHY_REFCLK_SELECT BIT(4) -#define CFGA0_USB3PHY_RESET BIT(1) -#define CFGA0_USB2PHY_POR BIT(0) - -#define INTR_EN_XA_TIMEOUT_EVT_EN BIT(1) -#define INTR_EN_XA_ACK_EVT_EN BIT(0) - -#define CLK_RST_TCA_REF_CLK_EN BIT(1) -#define CLK_RST_SUSPEND_CLK_EN BIT(0) - -#define GCFG_ROLE_HSTDEV BIT(4) -#define GCFG_OP_MODE GENMASK(1, 0) -#define GCFG_OP_MODE_CTRL_SYNC_MODE BIT(0) - -#define TCPC_VALID BIT(4) -#define TCPC_LOW_POWER_EN BIT(3) -#define TCPC_MUX_CONTROL_MASK GENMASK(1, 0) -#define TCPC_MUX_CONTROL_USB31 BIT(0) - -#define SYSMODE_CFG_TYPEC_DISABLE BIT(3) - -#define VBUS_CTRL_POWERPRESENT_OVERRD GENMASK(3, 2) -#define VBUS_CTRL_VBUSVALID_OVERRD GENMASK(1, 0) - -#define KIRIN970_USB_DEFAULT_PHY_PARAM (0xfdfee4) -#define KIRIN970_USB_DEFAULT_PHY_VBOOST (0x5) - -#define TX_VBOOST_LVL_REG (0xf) -#define TX_VBOOST_LVL_START (6) -#define TX_VBOOST_LVL_ENABLE BIT(9) - -struct hi3670_priv { - struct device *dev; - struct regmap *peri_crg; - struct regmap *pctrl; - struct regmap *sctrl; - struct regmap *usb31misc; - - u32 eye_diagram_param; - u32 tx_vboost_lvl; - - u32 peri_crg_offset; - u32 pctrl_offset; - u32 usb31misc_offset; -}; - -static int hi3670_phy_cr_clk(struct regmap *usb31misc) -{ - int ret; - - /* Clock up */ - ret = regmap_update_bits(usb31misc, USB_MISC_CFG54, - CFG54_USB31PHY_CR_CLK, CFG54_USB31PHY_CR_CLK); - if (ret) - return ret; - - /* Clock down */ - ret = regmap_update_bits(usb31misc, USB_MISC_CFG54, - CFG54_USB31PHY_CR_CLK, 0); - - return ret; -} - -static int hi3670_phy_cr_set_sel(struct regmap *usb31misc) -{ - return regmap_update_bits(usb31misc, USB_MISC_CFG54, - CFG54_USB31PHY_CR_SEL, CFG54_USB31PHY_CR_SEL); -} - -static int hi3670_phy_cr_start(struct regmap *usb31misc, int direction) -{ - int ret, reg; - - if (direction) - reg = CFG54_USB31PHY_CR_WR_EN; - else - reg = CFG54_USB31PHY_CR_RD_EN; - - ret = regmap_update_bits(usb31misc, USB_MISC_CFG54, reg, reg); - - if (ret) - return ret; - - ret = hi3670_phy_cr_clk(usb31misc); - if (ret) - return ret; - - return regmap_update_bits(usb31misc, USB_MISC_CFG54, - CFG54_USB31PHY_CR_RD_EN | CFG54_USB31PHY_CR_WR_EN, 0); -} - -static int hi3670_phy_cr_wait_ack(struct regmap *usb31misc) -{ - u32 reg; - int retry = 10; - int ret; - - while (retry-- > 0) { - ret = regmap_read(usb31misc, USB_MISC_CFG54, ®); - if (ret) - return ret; - if ((reg & CFG54_USB31PHY_CR_ACK) == CFG54_USB31PHY_CR_ACK) - return 0; - - ret = hi3670_phy_cr_clk(usb31misc); - if (ret) - return ret; - - usleep_range(10, 20); - } - - return -ETIMEDOUT; -} - -static int hi3670_phy_cr_set_addr(struct regmap *usb31misc, u32 addr) -{ - u32 reg; - int ret; - - ret = regmap_read(usb31misc, USB_MISC_CFG54, ®); - if (ret) - return ret; - - reg = FIELD_PREP(CFG54_USB31PHY_CR_ADDR_MASK, addr); - ret = regmap_update_bits(usb31misc, USB_MISC_CFG54, - CFG54_USB31PHY_CR_ADDR_MASK, reg); - - return ret; -} - -static int hi3670_phy_cr_read(struct regmap *usb31misc, u32 addr, u32 *val) -{ - int reg; - int i; - int ret; - - for (i = 0; i < 100; i++) { - ret = hi3670_phy_cr_clk(usb31misc); - if (ret) - return ret; - } - - ret = hi3670_phy_cr_set_sel(usb31misc); - if (ret) - return ret; - - ret = hi3670_phy_cr_set_addr(usb31misc, addr); - if (ret) - return ret; - - ret = hi3670_phy_cr_start(usb31misc, 0); - if (ret) - return ret; - - ret = hi3670_phy_cr_wait_ack(usb31misc); - if (ret) - return ret; - - ret = regmap_read(usb31misc, USB_MISC_CFG58, ®); - if (ret) - return ret; - - *val = FIELD_GET(CFG58_USB31PHY_CR_DATA_MASK, reg); - - return 0; -} - -static int hi3670_phy_cr_write(struct regmap *usb31misc, u32 addr, u32 val) -{ - int i; - int ret; - - for (i = 0; i < 100; i++) { - ret = hi3670_phy_cr_clk(usb31misc); - if (ret) - return ret; - } - - ret = hi3670_phy_cr_set_sel(usb31misc); - if (ret) - return ret; - - ret = hi3670_phy_cr_set_addr(usb31misc, addr); - if (ret) - return ret; - - ret = regmap_write(usb31misc, USB_MISC_CFG58, - FIELD_PREP(CFG58_USB31PHY_CR_DATA_MASK, val)); - if (ret) - return ret; - - ret = hi3670_phy_cr_start(usb31misc, 1); - if (ret) - return ret; - - ret = hi3670_phy_cr_wait_ack(usb31misc); - - return ret; -} - -static int hi3670_phy_set_params(struct hi3670_priv *priv) -{ - u32 reg; - int ret; - int retry = 3; - - ret = regmap_write(priv->usb31misc, USB3OTG_CTRL4, - priv->eye_diagram_param); - if (ret) { - dev_err(priv->dev, "set USB3OTG_CTRL4 failed\n"); - return ret; - } - - while (retry-- > 0) { - ret = hi3670_phy_cr_read(priv->usb31misc, - TX_VBOOST_LVL_REG, ®); - if (!ret) - break; - - if (ret != -ETIMEDOUT) { - dev_err(priv->dev, "read TX_VBOOST_LVL_REG failed\n"); - return ret; - } - } - if (ret) - return ret; - - reg |= (TX_VBOOST_LVL_ENABLE | (priv->tx_vboost_lvl << TX_VBOOST_LVL_START)); - ret = hi3670_phy_cr_write(priv->usb31misc, TX_VBOOST_LVL_REG, reg); - if (ret) - dev_err(priv->dev, "write TX_VBOOST_LVL_REG failed\n"); - - return ret; -} - -static bool hi3670_is_abbclk_seleted(struct hi3670_priv *priv) -{ - u32 reg; - - if (!priv->sctrl) { - dev_err(priv->dev, "priv->sctrl is null!\n"); - return true; - } - - if (regmap_read(priv->sctrl, SCTRL_SCDEEPSLEEPED, ®)) { - dev_err(priv->dev, "SCTRL_SCDEEPSLEEPED read failed!\n"); - return true; - } - - if ((reg & USB_CLK_SELECTED) == 0) - return true; - - return false; -} - -static int hi3670_config_phy_clock(struct hi3670_priv *priv) -{ - u32 val, mask; - int ret; - - if (hi3670_is_abbclk_seleted(priv)) { - /* usb refclk iso disable */ - ret = regmap_write(priv->peri_crg, PERI_CRG_ISODIS, - USB_REFCLK_ISO_EN); - if (ret) - goto out; - - /* enable usb_tcxo_en */ - ret = regmap_write(priv->pctrl, PCTRL_PERI_CTRL3, - USB_TCXO_EN | - (USB_TCXO_EN << PCTRL_PERI_CTRL3_MSK_START)); - - /* select usbphy clk from abb */ - mask = SC_CLK_USB3PHY_3MUX1_SEL; - ret = regmap_update_bits(priv->pctrl, - PCTRL_PERI_CTRL24, mask, 0); - if (ret) - goto out; - - ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, - CFGA0_USB2PHY_REFCLK_SELECT, 0); - if (ret) - goto out; - - ret = regmap_read(priv->usb31misc, USB3OTG_CTRL7, &val); - if (ret) - goto out; - val &= ~CTRL7_USB2_REFCLKSEL_MASK; - val |= CTRL7_USB2_REFCLKSEL_ABB; - ret = regmap_write(priv->usb31misc, USB3OTG_CTRL7, val); - if (ret) - goto out; - - return 0; - } - - ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFG54, - CFG54_USB3PHY_REF_USE_PAD, - CFG54_USB3PHY_REF_USE_PAD); - if (ret) - goto out; - - ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, - CFGA0_USB2PHY_REFCLK_SELECT, - CFGA0_USB2PHY_REFCLK_SELECT); - if (ret) - goto out; - - ret = regmap_read(priv->usb31misc, USB3OTG_CTRL7, &val); - if (ret) - goto out; - val &= ~CTRL7_USB2_REFCLKSEL_MASK; - val |= CTRL7_USB2_REFCLKSEL_PAD; - ret = regmap_write(priv->usb31misc, USB3OTG_CTRL7, val); - if (ret) - goto out; - - ret = regmap_write(priv->peri_crg, - PERI_CRG_PEREN6, GT_CLK_USB2PHY_REF); - if (ret) - goto out; - - return 0; -out: - dev_err(priv->dev, "failed to config phy clock ret: %d\n", ret); - return ret; -} - -static int hi3670_config_tca(struct hi3670_priv *priv) -{ - u32 val, mask; - int ret; - - ret = regmap_write(priv->usb31misc, TCA_INTR_STS, 0xffff); - if (ret) - goto out; - - ret = regmap_write(priv->usb31misc, TCA_INTR_EN, - INTR_EN_XA_TIMEOUT_EVT_EN | INTR_EN_XA_ACK_EVT_EN); - if (ret) - goto out; - - mask = CLK_RST_TCA_REF_CLK_EN | CLK_RST_SUSPEND_CLK_EN; - ret = regmap_update_bits(priv->usb31misc, TCA_CLK_RST, mask, 0); - if (ret) - goto out; - - ret = regmap_update_bits(priv->usb31misc, TCA_GCFG, - GCFG_ROLE_HSTDEV | GCFG_OP_MODE, - GCFG_ROLE_HSTDEV | GCFG_OP_MODE_CTRL_SYNC_MODE); - if (ret) - goto out; - - ret = regmap_update_bits(priv->usb31misc, TCA_SYSMODE_CFG, - SYSMODE_CFG_TYPEC_DISABLE, 0); - if (ret) - goto out; - - ret = regmap_read(priv->usb31misc, TCA_TCPC, &val); - if (ret) - goto out; - val &= ~(TCPC_VALID | TCPC_LOW_POWER_EN | TCPC_MUX_CONTROL_MASK); - val |= (TCPC_VALID | TCPC_MUX_CONTROL_USB31); - ret = regmap_write(priv->usb31misc, TCA_TCPC, val); - if (ret) - goto out; - - ret = regmap_write(priv->usb31misc, TCA_VBUS_CTRL, - VBUS_CTRL_POWERPRESENT_OVERRD | VBUS_CTRL_VBUSVALID_OVERRD); - if (ret) - goto out; - - return 0; -out: - dev_err(priv->dev, "failed to config phy clock ret: %d\n", ret); - return ret; -} - -static int hi3670_phy_init(struct phy *phy) -{ - struct hi3670_priv *priv = phy_get_drvdata(phy); - u32 val; - int ret; - - /* assert controller */ - val = CFGA0_VAUX_RESET | CFGA0_USB31C_RESET | - CFGA0_USB3PHY_RESET | CFGA0_USB2PHY_POR; - ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, val, 0); - if (ret) - goto out; - - ret = hi3670_config_phy_clock(priv); - if (ret) - goto out; - - /* Exit from IDDQ mode */ - ret = regmap_update_bits(priv->usb31misc, USB3OTG_CTRL5, - CTRL5_USB2_SIDDQ, 0); - if (ret) - goto out; - - /* Release USB31 PHY out of TestPowerDown mode */ - ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFG50, - CFG50_USB3_PHY_TEST_POWERDOWN, 0); - if (ret) - goto out; - - /* Deassert phy */ - val = CFGA0_USB3PHY_RESET | CFGA0_USB2PHY_POR; - ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, val, val); - if (ret) - goto out; - - usleep_range(100, 120); - - /* Tell the PHY power is stable */ - val = CFG54_USB3_PHY0_ANA_PWR_EN | CFG54_PHY0_PCS_PWR_STABLE | - CFG54_PHY0_PMA_PWR_STABLE; - ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFG54, - val, val); - if (ret) - goto out; - - ret = hi3670_config_tca(priv); - if (ret) - goto out; - - /* Enable SSC */ - ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFG5C, - CFG5C_USB3_PHY0_SS_MPLLA_SSC_EN, - CFG5C_USB3_PHY0_SS_MPLLA_SSC_EN); - if (ret) - goto out; - - /* Deassert controller */ - val = CFGA0_VAUX_RESET | CFGA0_USB31C_RESET; - ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, val, val); - if (ret) - goto out; - - usleep_range(100, 120); - - /* Set fake vbus valid signal */ - val = CTRL0_USB3_VBUSVLD | CTRL0_USB3_VBUSVLD_SEL; - ret = regmap_update_bits(priv->usb31misc, USB3OTG_CTRL0, val, val); - if (ret) - goto out; - - val = CTRL3_USB2_VBUSVLDEXT0 | CTRL3_USB2_VBUSVLDEXTSEL0; - ret = regmap_update_bits(priv->usb31misc, USB3OTG_CTRL3, val, val); - if (ret) - goto out; - - usleep_range(100, 120); - - ret = hi3670_phy_set_params(priv); - if (ret) - goto out; - - return 0; -out: - dev_err(priv->dev, "failed to init phy ret: %d\n", ret); - return ret; -} - -static int hi3670_phy_exit(struct phy *phy) -{ - struct hi3670_priv *priv = phy_get_drvdata(phy); - u32 mask; - int ret; - - /* Assert phy */ - mask = CFGA0_USB3PHY_RESET | CFGA0_USB2PHY_POR; - ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, mask, 0); - if (ret) - goto out; - - if (hi3670_is_abbclk_seleted(priv)) { - /* disable usb_tcxo_en */ - ret = regmap_write(priv->pctrl, PCTRL_PERI_CTRL3, - USB_TCXO_EN << PCTRL_PERI_CTRL3_MSK_START); - } else { - ret = regmap_write(priv->peri_crg, PERI_CRG_PERDIS6, - GT_CLK_USB2PHY_REF); - if (ret) - goto out; - } - - return 0; -out: - dev_err(priv->dev, "failed to exit phy ret: %d\n", ret); - return ret; -} - -static struct phy_ops hi3670_phy_ops = { - .init = hi3670_phy_init, - .exit = hi3670_phy_exit, - .owner = THIS_MODULE, -}; - -static int hi3670_phy_probe(struct platform_device *pdev) -{ - struct phy_provider *phy_provider; - struct device *dev = &pdev->dev; - struct phy *phy; - struct hi3670_priv *priv; - - priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; - - priv->dev = dev; - priv->peri_crg = syscon_regmap_lookup_by_phandle(dev->of_node, - "hisilicon,pericrg-syscon"); - if (IS_ERR(priv->peri_crg)) { - dev_err(dev, "no hisilicon,pericrg-syscon\n"); - return PTR_ERR(priv->peri_crg); - } - - priv->pctrl = syscon_regmap_lookup_by_phandle(dev->of_node, - "hisilicon,pctrl-syscon"); - if (IS_ERR(priv->pctrl)) { - dev_err(dev, "no hisilicon,pctrl-syscon\n"); - return PTR_ERR(priv->pctrl); - } - - priv->sctrl = syscon_regmap_lookup_by_phandle(dev->of_node, - "hisilicon,sctrl-syscon"); - if (IS_ERR(priv->sctrl)) { - dev_err(dev, "no hisilicon,sctrl-syscon\n"); - return PTR_ERR(priv->sctrl); - } - - /* node of hi3670 phy is a sub-node of usb3_otg_bc */ - priv->usb31misc = syscon_node_to_regmap(dev->parent->of_node); - if (IS_ERR(priv->usb31misc)) { - dev_err(dev, "no hisilicon,usb3-otg-bc-syscon\n"); - return PTR_ERR(priv->usb31misc); - } - - if (of_property_read_u32(dev->of_node, "hisilicon,eye-diagram-param", - &priv->eye_diagram_param)) - priv->eye_diagram_param = KIRIN970_USB_DEFAULT_PHY_PARAM; - - if (of_property_read_u32(dev->of_node, "hisilicon,tx-vboost-lvl", - &priv->tx_vboost_lvl)) - priv->tx_vboost_lvl = KIRIN970_USB_DEFAULT_PHY_VBOOST; - - phy = devm_phy_create(dev, NULL, &hi3670_phy_ops); - if (IS_ERR(phy)) - return PTR_ERR(phy); - - phy_set_drvdata(phy, priv); - phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); - return PTR_ERR_OR_ZERO(phy_provider); -} - -static const struct of_device_id hi3670_phy_of_match[] = { - { .compatible = "hisilicon,hi3670-usb-phy" }, - { }, -}; -MODULE_DEVICE_TABLE(of, hi3670_phy_of_match); - -static struct platform_driver hi3670_phy_driver = { - .probe = hi3670_phy_probe, - .driver = { - .name = "hi3670-usb-phy", - .of_match_table = hi3670_phy_of_match, - } -}; -module_platform_driver(hi3670_phy_driver); - -MODULE_AUTHOR("Yu Chen <chenyu56@huawei.com>"); -MODULE_LICENSE("GPL v2"); -MODULE_DESCRIPTION("Hilisicon Kirin970 USB31 PHY Driver"); diff --git a/drivers/staging/hikey9xx/phy-hi3670-usb3.yaml b/drivers/staging/hikey9xx/phy-hi3670-usb3.yaml deleted file mode 100644 index 125a5d6546ae..000000000000 --- a/drivers/staging/hikey9xx/phy-hi3670-usb3.yaml +++ /dev/null @@ -1,72 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/phy/hisilicon,hi3670-usb3.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Hisilicon Kirin970 USB PHY - -maintainers: - - Mauro Carvalho Chehab <mchehab+huawei@kernel.org> -description: |+ - Bindings for USB3 PHY on HiSilicon Kirin 970. - -properties: - compatible: - const: hisilicon,hi3670-usb-phy - - "#phy-cells": - const: 0 - - hisilicon,pericrg-syscon: - $ref: '/schemas/types.yaml#/definitions/phandle' - description: phandle of syscon used to control iso refclk. - - hisilicon,pctrl-syscon: - $ref: '/schemas/types.yaml#/definitions/phandle' - description: phandle of syscon used to control usb tcxo. - - hisilicon,sctrl-syscon: - $ref: '/schemas/types.yaml#/definitions/phandle' - description: phandle of syscon used to control phy deep sleep. - - hisilicon,eye-diagram-param: - $ref: /schemas/types.yaml#/definitions/uint32 - description: Eye diagram for phy. - - hisilicon,tx-vboost-lvl: - $ref: /schemas/types.yaml#/definitions/uint32 - description: TX level vboost for phy. - -required: - - compatible - - hisilicon,pericrg-syscon - - hisilicon,pctrl-syscon - - hisilicon,sctrl-syscon - - hisilicon,eye-diagram-param - - hisilicon,tx-vboost-lvl - - "#phy-cells" - -additionalProperties: false - -examples: - - | - bus { - #address-cells = <2>; - #size-cells = <2>; - - usb3_otg_bc: usb3_otg_bc@ff200000 { - compatible = "syscon", "simple-mfd"; - reg = <0x0 0xff200000 0x0 0x1000>; - - usb_phy { - compatible = "hisilicon,hi3670-usb-phy"; - #phy-cells = <0>; - hisilicon,pericrg-syscon = <&crg_ctrl>; - hisilicon,pctrl-syscon = <&pctrl>; - hisilicon,sctrl-syscon = <&sctrl>; - hisilicon,eye-diagram-param = <0xfdfee4>; - hisilicon,tx-vboost-lvl = <0x5>; - }; - }; - }; -- 2.29.2 _______________________________________________ devel mailing list devel@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v2 4/4] phy: phy-hi3670-usb3: move driver from staging into phy 2021-01-14 17:35 ` Mauro Carvalho Chehab @ 2021-01-14 22:54 ` Rob Herring -1 siblings, 0 replies; 25+ messages in thread From: Rob Herring @ 2021-01-14 22:54 UTC (permalink / raw) To: Mauro Carvalho Chehab Cc: linux-kernel, Greg Kroah-Hartman, Yu Chen, Kishon Vijay Abraham I, Vinod Koul, devicetree, Alex Dewar, devel, Rob Herring On Thu, 14 Jan 2021 18:35:44 +0100, Mauro Carvalho Chehab wrote: > The phy USB3 driver for Hisilicon 970 (hi3670) is ready > for mainstream. Mode it from staging into the main driver's > phy/ directory. > > Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> > --- > .../bindings/phy/phy-hi3670-usb3.yaml | 72 ++ > MAINTAINERS | 9 +- > drivers/phy/hisilicon/Kconfig | 10 + > drivers/phy/hisilicon/Makefile | 1 + > drivers/phy/hisilicon/phy-hi3670-usb3.c | 668 ++++++++++++++++++ > drivers/staging/hikey9xx/Kconfig | 11 - > drivers/staging/hikey9xx/Makefile | 2 - > drivers/staging/hikey9xx/phy-hi3670-usb3.c | 668 ------------------ > drivers/staging/hikey9xx/phy-hi3670-usb3.yaml | 72 -- > 9 files changed, 759 insertions(+), 754 deletions(-) > create mode 100644 Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml > create mode 100644 drivers/phy/hisilicon/phy-hi3670-usb3.c > delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.c > delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.yaml > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: dtschema/dtc warnings/errors: ./Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml: $id: relative path/filename doesn't match actual path or filename expected: http://devicetree.org/schemas/phy/phy-hi3670-usb3.yaml# See https://patchwork.ozlabs.org/patch/1426545 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit. ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 4/4] phy: phy-hi3670-usb3: move driver from staging into phy @ 2021-01-14 22:54 ` Rob Herring 0 siblings, 0 replies; 25+ messages in thread From: Rob Herring @ 2021-01-14 22:54 UTC (permalink / raw) To: Mauro Carvalho Chehab Cc: devel, devicetree, Greg Kroah-Hartman, Yu Chen, linux-kernel, Kishon Vijay Abraham I, Vinod Koul, Rob Herring, Alex Dewar On Thu, 14 Jan 2021 18:35:44 +0100, Mauro Carvalho Chehab wrote: > The phy USB3 driver for Hisilicon 970 (hi3670) is ready > for mainstream. Mode it from staging into the main driver's > phy/ directory. > > Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> > --- > .../bindings/phy/phy-hi3670-usb3.yaml | 72 ++ > MAINTAINERS | 9 +- > drivers/phy/hisilicon/Kconfig | 10 + > drivers/phy/hisilicon/Makefile | 1 + > drivers/phy/hisilicon/phy-hi3670-usb3.c | 668 ++++++++++++++++++ > drivers/staging/hikey9xx/Kconfig | 11 - > drivers/staging/hikey9xx/Makefile | 2 - > drivers/staging/hikey9xx/phy-hi3670-usb3.c | 668 ------------------ > drivers/staging/hikey9xx/phy-hi3670-usb3.yaml | 72 -- > 9 files changed, 759 insertions(+), 754 deletions(-) > create mode 100644 Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml > create mode 100644 drivers/phy/hisilicon/phy-hi3670-usb3.c > delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.c > delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.yaml > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: dtschema/dtc warnings/errors: ./Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml: $id: relative path/filename doesn't match actual path or filename expected: http://devicetree.org/schemas/phy/phy-hi3670-usb3.yaml# See https://patchwork.ozlabs.org/patch/1426545 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit. _______________________________________________ devel mailing list devel@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 4/4] phy: phy-hi3670-usb3: move driver from staging into phy 2021-01-14 17:35 ` Mauro Carvalho Chehab @ 2021-01-15 1:47 ` Rob Herring -1 siblings, 0 replies; 25+ messages in thread From: Rob Herring @ 2021-01-15 1:47 UTC (permalink / raw) To: Mauro Carvalho Chehab Cc: Vinod Koul, Alex Dewar, Greg Kroah-Hartman, Kishon Vijay Abraham I, Yu Chen, devel, devicetree, linux-kernel On Thu, Jan 14, 2021 at 06:35:44PM +0100, Mauro Carvalho Chehab wrote: > The phy USB3 driver for Hisilicon 970 (hi3670) is ready > for mainstream. Mode it from staging into the main driver's > phy/ directory. > > Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> > --- > .../bindings/phy/phy-hi3670-usb3.yaml | 72 ++ > MAINTAINERS | 9 +- > drivers/phy/hisilicon/Kconfig | 10 + > drivers/phy/hisilicon/Makefile | 1 + > drivers/phy/hisilicon/phy-hi3670-usb3.c | 668 ++++++++++++++++++ > drivers/staging/hikey9xx/Kconfig | 11 - > drivers/staging/hikey9xx/Makefile | 2 - > drivers/staging/hikey9xx/phy-hi3670-usb3.c | 668 ------------------ > drivers/staging/hikey9xx/phy-hi3670-usb3.yaml | 72 -- > 9 files changed, 759 insertions(+), 754 deletions(-) > create mode 100644 Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml > create mode 100644 drivers/phy/hisilicon/phy-hi3670-usb3.c > delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.c > delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.yaml > > diff --git a/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml b/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml > new file mode 100644 > index 000000000000..125a5d6546ae > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml > @@ -0,0 +1,72 @@ > +# SPDX-License-Identifier: GPL-2.0 > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/hisilicon,hi3670-usb3.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Hisilicon Kirin970 USB PHY > + > +maintainers: > + - Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Blank line. > +description: |+ > + Bindings for USB3 PHY on HiSilicon Kirin 970. > + > +properties: > + compatible: > + const: hisilicon,hi3670-usb-phy > + > + "#phy-cells": > + const: 0 > + > + hisilicon,pericrg-syscon: > + $ref: '/schemas/types.yaml#/definitions/phandle' > + description: phandle of syscon used to control iso refclk. > + > + hisilicon,pctrl-syscon: > + $ref: '/schemas/types.yaml#/definitions/phandle' > + description: phandle of syscon used to control usb tcxo. > + > + hisilicon,sctrl-syscon: > + $ref: '/schemas/types.yaml#/definitions/phandle' > + description: phandle of syscon used to control phy deep sleep. > + > + hisilicon,eye-diagram-param: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: Eye diagram for phy. > + > + hisilicon,tx-vboost-lvl: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: TX level vboost for phy. > + > +required: > + - compatible > + - hisilicon,pericrg-syscon > + - hisilicon,pctrl-syscon > + - hisilicon,sctrl-syscon > + - hisilicon,eye-diagram-param > + - hisilicon,tx-vboost-lvl > + - "#phy-cells" > + > +additionalProperties: false > + > +examples: > + - | > + bus { > + #address-cells = <2>; > + #size-cells = <2>; > + > + usb3_otg_bc: usb3_otg_bc@ff200000 { > + compatible = "syscon", "simple-mfd"; > + reg = <0x0 0xff200000 0x0 0x1000>; > + > + usb_phy { Is there a contiguous register region for this sub-block? If so, add 'reg' even though Linux doesn't need it currently. > + compatible = "hisilicon,hi3670-usb-phy"; > + #phy-cells = <0>; > + hisilicon,pericrg-syscon = <&crg_ctrl>; > + hisilicon,pctrl-syscon = <&pctrl>; > + hisilicon,sctrl-syscon = <&sctrl>; > + hisilicon,eye-diagram-param = <0xfdfee4>; > + hisilicon,tx-vboost-lvl = <0x5>; > + }; > + }; > + }; ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 4/4] phy: phy-hi3670-usb3: move driver from staging into phy @ 2021-01-15 1:47 ` Rob Herring 0 siblings, 0 replies; 25+ messages in thread From: Rob Herring @ 2021-01-15 1:47 UTC (permalink / raw) To: Mauro Carvalho Chehab Cc: devel, devicetree, Greg Kroah-Hartman, Yu Chen, linux-kernel, Kishon Vijay Abraham I, Vinod Koul, Alex Dewar On Thu, Jan 14, 2021 at 06:35:44PM +0100, Mauro Carvalho Chehab wrote: > The phy USB3 driver for Hisilicon 970 (hi3670) is ready > for mainstream. Mode it from staging into the main driver's > phy/ directory. > > Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> > --- > .../bindings/phy/phy-hi3670-usb3.yaml | 72 ++ > MAINTAINERS | 9 +- > drivers/phy/hisilicon/Kconfig | 10 + > drivers/phy/hisilicon/Makefile | 1 + > drivers/phy/hisilicon/phy-hi3670-usb3.c | 668 ++++++++++++++++++ > drivers/staging/hikey9xx/Kconfig | 11 - > drivers/staging/hikey9xx/Makefile | 2 - > drivers/staging/hikey9xx/phy-hi3670-usb3.c | 668 ------------------ > drivers/staging/hikey9xx/phy-hi3670-usb3.yaml | 72 -- > 9 files changed, 759 insertions(+), 754 deletions(-) > create mode 100644 Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml > create mode 100644 drivers/phy/hisilicon/phy-hi3670-usb3.c > delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.c > delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.yaml > > diff --git a/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml b/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml > new file mode 100644 > index 000000000000..125a5d6546ae > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml > @@ -0,0 +1,72 @@ > +# SPDX-License-Identifier: GPL-2.0 > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/hisilicon,hi3670-usb3.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Hisilicon Kirin970 USB PHY > + > +maintainers: > + - Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Blank line. > +description: |+ > + Bindings for USB3 PHY on HiSilicon Kirin 970. > + > +properties: > + compatible: > + const: hisilicon,hi3670-usb-phy > + > + "#phy-cells": > + const: 0 > + > + hisilicon,pericrg-syscon: > + $ref: '/schemas/types.yaml#/definitions/phandle' > + description: phandle of syscon used to control iso refclk. > + > + hisilicon,pctrl-syscon: > + $ref: '/schemas/types.yaml#/definitions/phandle' > + description: phandle of syscon used to control usb tcxo. > + > + hisilicon,sctrl-syscon: > + $ref: '/schemas/types.yaml#/definitions/phandle' > + description: phandle of syscon used to control phy deep sleep. > + > + hisilicon,eye-diagram-param: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: Eye diagram for phy. > + > + hisilicon,tx-vboost-lvl: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: TX level vboost for phy. > + > +required: > + - compatible > + - hisilicon,pericrg-syscon > + - hisilicon,pctrl-syscon > + - hisilicon,sctrl-syscon > + - hisilicon,eye-diagram-param > + - hisilicon,tx-vboost-lvl > + - "#phy-cells" > + > +additionalProperties: false > + > +examples: > + - | > + bus { > + #address-cells = <2>; > + #size-cells = <2>; > + > + usb3_otg_bc: usb3_otg_bc@ff200000 { > + compatible = "syscon", "simple-mfd"; > + reg = <0x0 0xff200000 0x0 0x1000>; > + > + usb_phy { Is there a contiguous register region for this sub-block? If so, add 'reg' even though Linux doesn't need it currently. > + compatible = "hisilicon,hi3670-usb-phy"; > + #phy-cells = <0>; > + hisilicon,pericrg-syscon = <&crg_ctrl>; > + hisilicon,pctrl-syscon = <&pctrl>; > + hisilicon,sctrl-syscon = <&sctrl>; > + hisilicon,eye-diagram-param = <0xfdfee4>; > + hisilicon,tx-vboost-lvl = <0x5>; > + }; > + }; > + }; _______________________________________________ devel mailing list devel@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 4/4] phy: phy-hi3670-usb3: move driver from staging into phy 2021-01-15 1:47 ` Rob Herring @ 2021-01-19 10:26 ` Mauro Carvalho Chehab -1 siblings, 0 replies; 25+ messages in thread From: Mauro Carvalho Chehab @ 2021-01-19 10:26 UTC (permalink / raw) To: Rob Herring Cc: Vinod Koul, Alex Dewar, Greg Kroah-Hartman, Kishon Vijay Abraham I, Yu Chen, devel, devicetree, linux-kernel Em Thu, 14 Jan 2021 19:47:31 -0600 Rob Herring <robh@kernel.org> escreveu: > On Thu, Jan 14, 2021 at 06:35:44PM +0100, Mauro Carvalho Chehab wrote: > > The phy USB3 driver for Hisilicon 970 (hi3670) is ready > > for mainstream. Mode it from staging into the main driver's > > phy/ directory. > > > > Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> > > --- > > .../bindings/phy/phy-hi3670-usb3.yaml | 72 ++ > > MAINTAINERS | 9 +- > > drivers/phy/hisilicon/Kconfig | 10 + > > drivers/phy/hisilicon/Makefile | 1 + > > drivers/phy/hisilicon/phy-hi3670-usb3.c | 668 ++++++++++++++++++ > > drivers/staging/hikey9xx/Kconfig | 11 - > > drivers/staging/hikey9xx/Makefile | 2 - > > drivers/staging/hikey9xx/phy-hi3670-usb3.c | 668 ------------------ > > drivers/staging/hikey9xx/phy-hi3670-usb3.yaml | 72 -- > > 9 files changed, 759 insertions(+), 754 deletions(-) > > create mode 100644 Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml > > create mode 100644 drivers/phy/hisilicon/phy-hi3670-usb3.c > > delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.c > > delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.yaml > > > > diff --git a/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml b/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml > > new file mode 100644 > > index 000000000000..125a5d6546ae > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml > > @@ -0,0 +1,72 @@ > > +# SPDX-License-Identifier: GPL-2.0 > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/phy/hisilicon,hi3670-usb3.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Hisilicon Kirin970 USB PHY > > + > > +maintainers: > > + - Mauro Carvalho Chehab <mchehab+huawei@kernel.org> > > Blank line. Ok. > > > +description: |+ > > + Bindings for USB3 PHY on HiSilicon Kirin 970. > > + > > +properties: > > + compatible: > > + const: hisilicon,hi3670-usb-phy > > + > > + "#phy-cells": > > + const: 0 > > + > > + hisilicon,pericrg-syscon: > > + $ref: '/schemas/types.yaml#/definitions/phandle' > > + description: phandle of syscon used to control iso refclk. > > + > > + hisilicon,pctrl-syscon: > > + $ref: '/schemas/types.yaml#/definitions/phandle' > > + description: phandle of syscon used to control usb tcxo. > > + > > + hisilicon,sctrl-syscon: > > + $ref: '/schemas/types.yaml#/definitions/phandle' > > + description: phandle of syscon used to control phy deep sleep. > > + > > + hisilicon,eye-diagram-param: > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + description: Eye diagram for phy. > > + > > + hisilicon,tx-vboost-lvl: > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + description: TX level vboost for phy. > > + > > +required: > > + - compatible > > + - hisilicon,pericrg-syscon > > + - hisilicon,pctrl-syscon > > + - hisilicon,sctrl-syscon > > + - hisilicon,eye-diagram-param > > + - hisilicon,tx-vboost-lvl > > + - "#phy-cells" > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + bus { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + usb3_otg_bc: usb3_otg_bc@ff200000 { > > + compatible = "syscon", "simple-mfd"; > > + reg = <0x0 0xff200000 0x0 0x1000>; > > + > > + usb_phy { > > Is there a contiguous register region for this sub-block? If so, add > 'reg' even though Linux doesn't need it currently. No. The driver uses 4 syscon regions in order to access the needed registers: priv->peri_crg = syscon_regmap_lookup_by_phandle(dev->of_node, "hisilicon,pericrg-syscon"); if (IS_ERR(priv->peri_crg)) { dev_err(dev, "no hisilicon,pericrg-syscon\n"); return PTR_ERR(priv->peri_crg); } priv->pctrl = syscon_regmap_lookup_by_phandle(dev->of_node, "hisilicon,pctrl-syscon"); if (IS_ERR(priv->pctrl)) { dev_err(dev, "no hisilicon,pctrl-syscon\n"); return PTR_ERR(priv->pctrl); } priv->sctrl = syscon_regmap_lookup_by_phandle(dev->of_node, "hisilicon,sctrl-syscon"); if (IS_ERR(priv->sctrl)) { dev_err(dev, "no hisilicon,sctrl-syscon\n"); return PTR_ERR(priv->sctrl); } /* node of hi3670 phy is a sub-node of usb3_otg_bc */ priv->usb31misc = syscon_node_to_regmap(dev->parent->of_node); if (IS_ERR(priv->usb31misc)) { dev_err(dev, "no hisilicon,usb3-otg-bc-syscon\n"); return PTR_ERR(priv->usb31misc); } So, I don't see what an additional reg would help here. > > + compatible = "hisilicon,hi3670-usb-phy"; > > + #phy-cells = <0>; > > + hisilicon,pericrg-syscon = <&crg_ctrl>; > > + hisilicon,pctrl-syscon = <&pctrl>; > > + hisilicon,sctrl-syscon = <&sctrl>; > > + hisilicon,eye-diagram-param = <0xfdfee4>; > > + hisilicon,tx-vboost-lvl = <0x5>; > > + }; > > + }; > > + }; Thanks, Mauro ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 4/4] phy: phy-hi3670-usb3: move driver from staging into phy @ 2021-01-19 10:26 ` Mauro Carvalho Chehab 0 siblings, 0 replies; 25+ messages in thread From: Mauro Carvalho Chehab @ 2021-01-19 10:26 UTC (permalink / raw) To: Rob Herring Cc: devel, devicetree, Greg Kroah-Hartman, Yu Chen, linux-kernel, Kishon Vijay Abraham I, Vinod Koul, Alex Dewar Em Thu, 14 Jan 2021 19:47:31 -0600 Rob Herring <robh@kernel.org> escreveu: > On Thu, Jan 14, 2021 at 06:35:44PM +0100, Mauro Carvalho Chehab wrote: > > The phy USB3 driver for Hisilicon 970 (hi3670) is ready > > for mainstream. Mode it from staging into the main driver's > > phy/ directory. > > > > Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> > > --- > > .../bindings/phy/phy-hi3670-usb3.yaml | 72 ++ > > MAINTAINERS | 9 +- > > drivers/phy/hisilicon/Kconfig | 10 + > > drivers/phy/hisilicon/Makefile | 1 + > > drivers/phy/hisilicon/phy-hi3670-usb3.c | 668 ++++++++++++++++++ > > drivers/staging/hikey9xx/Kconfig | 11 - > > drivers/staging/hikey9xx/Makefile | 2 - > > drivers/staging/hikey9xx/phy-hi3670-usb3.c | 668 ------------------ > > drivers/staging/hikey9xx/phy-hi3670-usb3.yaml | 72 -- > > 9 files changed, 759 insertions(+), 754 deletions(-) > > create mode 100644 Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml > > create mode 100644 drivers/phy/hisilicon/phy-hi3670-usb3.c > > delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.c > > delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.yaml > > > > diff --git a/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml b/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml > > new file mode 100644 > > index 000000000000..125a5d6546ae > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml > > @@ -0,0 +1,72 @@ > > +# SPDX-License-Identifier: GPL-2.0 > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/phy/hisilicon,hi3670-usb3.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Hisilicon Kirin970 USB PHY > > + > > +maintainers: > > + - Mauro Carvalho Chehab <mchehab+huawei@kernel.org> > > Blank line. Ok. > > > +description: |+ > > + Bindings for USB3 PHY on HiSilicon Kirin 970. > > + > > +properties: > > + compatible: > > + const: hisilicon,hi3670-usb-phy > > + > > + "#phy-cells": > > + const: 0 > > + > > + hisilicon,pericrg-syscon: > > + $ref: '/schemas/types.yaml#/definitions/phandle' > > + description: phandle of syscon used to control iso refclk. > > + > > + hisilicon,pctrl-syscon: > > + $ref: '/schemas/types.yaml#/definitions/phandle' > > + description: phandle of syscon used to control usb tcxo. > > + > > + hisilicon,sctrl-syscon: > > + $ref: '/schemas/types.yaml#/definitions/phandle' > > + description: phandle of syscon used to control phy deep sleep. > > + > > + hisilicon,eye-diagram-param: > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + description: Eye diagram for phy. > > + > > + hisilicon,tx-vboost-lvl: > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + description: TX level vboost for phy. > > + > > +required: > > + - compatible > > + - hisilicon,pericrg-syscon > > + - hisilicon,pctrl-syscon > > + - hisilicon,sctrl-syscon > > + - hisilicon,eye-diagram-param > > + - hisilicon,tx-vboost-lvl > > + - "#phy-cells" > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + bus { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + usb3_otg_bc: usb3_otg_bc@ff200000 { > > + compatible = "syscon", "simple-mfd"; > > + reg = <0x0 0xff200000 0x0 0x1000>; > > + > > + usb_phy { > > Is there a contiguous register region for this sub-block? If so, add > 'reg' even though Linux doesn't need it currently. No. The driver uses 4 syscon regions in order to access the needed registers: priv->peri_crg = syscon_regmap_lookup_by_phandle(dev->of_node, "hisilicon,pericrg-syscon"); if (IS_ERR(priv->peri_crg)) { dev_err(dev, "no hisilicon,pericrg-syscon\n"); return PTR_ERR(priv->peri_crg); } priv->pctrl = syscon_regmap_lookup_by_phandle(dev->of_node, "hisilicon,pctrl-syscon"); if (IS_ERR(priv->pctrl)) { dev_err(dev, "no hisilicon,pctrl-syscon\n"); return PTR_ERR(priv->pctrl); } priv->sctrl = syscon_regmap_lookup_by_phandle(dev->of_node, "hisilicon,sctrl-syscon"); if (IS_ERR(priv->sctrl)) { dev_err(dev, "no hisilicon,sctrl-syscon\n"); return PTR_ERR(priv->sctrl); } /* node of hi3670 phy is a sub-node of usb3_otg_bc */ priv->usb31misc = syscon_node_to_regmap(dev->parent->of_node); if (IS_ERR(priv->usb31misc)) { dev_err(dev, "no hisilicon,usb3-otg-bc-syscon\n"); return PTR_ERR(priv->usb31misc); } So, I don't see what an additional reg would help here. > > + compatible = "hisilicon,hi3670-usb-phy"; > > + #phy-cells = <0>; > > + hisilicon,pericrg-syscon = <&crg_ctrl>; > > + hisilicon,pctrl-syscon = <&pctrl>; > > + hisilicon,sctrl-syscon = <&sctrl>; > > + hisilicon,eye-diagram-param = <0xfdfee4>; > > + hisilicon,tx-vboost-lvl = <0x5>; > > + }; > > + }; > > + }; Thanks, Mauro _______________________________________________ devel mailing list devel@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 4/4] phy: phy-hi3670-usb3: move driver from staging into phy 2021-01-19 10:26 ` Mauro Carvalho Chehab @ 2021-01-22 14:51 ` Rob Herring -1 siblings, 0 replies; 25+ messages in thread From: Rob Herring @ 2021-01-22 14:51 UTC (permalink / raw) To: Mauro Carvalho Chehab Cc: Vinod Koul, Alex Dewar, Greg Kroah-Hartman, Kishon Vijay Abraham I, Yu Chen, open list:STAGING SUBSYSTEM, devicetree, linux-kernel On Tue, Jan 19, 2021 at 4:26 AM Mauro Carvalho Chehab <mchehab+huawei@kernel.org> wrote: > > Em Thu, 14 Jan 2021 19:47:31 -0600 > Rob Herring <robh@kernel.org> escreveu: > > > On Thu, Jan 14, 2021 at 06:35:44PM +0100, Mauro Carvalho Chehab wrote: > > > The phy USB3 driver for Hisilicon 970 (hi3670) is ready > > > for mainstream. Mode it from staging into the main driver's > > > phy/ directory. > > > > > > Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> > > > --- > > > .../bindings/phy/phy-hi3670-usb3.yaml | 72 ++ > > > MAINTAINERS | 9 +- > > > drivers/phy/hisilicon/Kconfig | 10 + > > > drivers/phy/hisilicon/Makefile | 1 + > > > drivers/phy/hisilicon/phy-hi3670-usb3.c | 668 ++++++++++++++++++ > > > drivers/staging/hikey9xx/Kconfig | 11 - > > > drivers/staging/hikey9xx/Makefile | 2 - > > > drivers/staging/hikey9xx/phy-hi3670-usb3.c | 668 ------------------ > > > drivers/staging/hikey9xx/phy-hi3670-usb3.yaml | 72 -- > > > 9 files changed, 759 insertions(+), 754 deletions(-) > > > create mode 100644 Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml > > > create mode 100644 drivers/phy/hisilicon/phy-hi3670-usb3.c > > > delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.c > > > delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.yaml > > > > > > diff --git a/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml b/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml > > > new file mode 100644 > > > index 000000000000..125a5d6546ae > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml > > > @@ -0,0 +1,72 @@ > > > +# SPDX-License-Identifier: GPL-2.0 > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/phy/hisilicon,hi3670-usb3.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: Hisilicon Kirin970 USB PHY > > > + > > > +maintainers: > > > + - Mauro Carvalho Chehab <mchehab+huawei@kernel.org> > > > > Blank line. > > Ok. > > > > > > +description: |+ > > > + Bindings for USB3 PHY on HiSilicon Kirin 970. > > > + > > > +properties: > > > + compatible: > > > + const: hisilicon,hi3670-usb-phy > > > + > > > + "#phy-cells": > > > + const: 0 > > > + > > > + hisilicon,pericrg-syscon: > > > + $ref: '/schemas/types.yaml#/definitions/phandle' > > > + description: phandle of syscon used to control iso refclk. > > > + > > > + hisilicon,pctrl-syscon: > > > + $ref: '/schemas/types.yaml#/definitions/phandle' > > > + description: phandle of syscon used to control usb tcxo. > > > + > > > + hisilicon,sctrl-syscon: > > > + $ref: '/schemas/types.yaml#/definitions/phandle' > > > + description: phandle of syscon used to control phy deep sleep. > > > + > > > + hisilicon,eye-diagram-param: > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > + description: Eye diagram for phy. > > > + > > > + hisilicon,tx-vboost-lvl: > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > + description: TX level vboost for phy. > > > + > > > +required: > > > + - compatible > > > + - hisilicon,pericrg-syscon > > > + - hisilicon,pctrl-syscon > > > + - hisilicon,sctrl-syscon > > > + - hisilicon,eye-diagram-param > > > + - hisilicon,tx-vboost-lvl > > > + - "#phy-cells" > > > + > > > +additionalProperties: false > > > + > > > +examples: > > > + - | > > > + bus { > > > + #address-cells = <2>; > > > + #size-cells = <2>; > > > + > > > + usb3_otg_bc: usb3_otg_bc@ff200000 { > > > + compatible = "syscon", "simple-mfd"; > > > + reg = <0x0 0xff200000 0x0 0x1000>; > > > + > > > + usb_phy { > > > > Is there a contiguous register region for this sub-block? If so, add > > 'reg' even though Linux doesn't need it currently. > > No. The driver uses 4 syscon regions in order to access the needed > registers: I meant just for the parent device node. I assume these are the 'main' registers? If not, then maybe it should be a child of one of the other syscons. 'reg' would just be for documentation ATM. However, if the subblock was reused on another chip, but at a different offset then reg would become useful. You could handle that with a fixed offset when 'reg' is missing, but adding it later would be too late. Rob ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 4/4] phy: phy-hi3670-usb3: move driver from staging into phy @ 2021-01-22 14:51 ` Rob Herring 0 siblings, 0 replies; 25+ messages in thread From: Rob Herring @ 2021-01-22 14:51 UTC (permalink / raw) To: Mauro Carvalho Chehab Cc: open list:STAGING SUBSYSTEM, devicetree, Greg Kroah-Hartman, Yu Chen, linux-kernel, Kishon Vijay Abraham I, Vinod Koul, Alex Dewar On Tue, Jan 19, 2021 at 4:26 AM Mauro Carvalho Chehab <mchehab+huawei@kernel.org> wrote: > > Em Thu, 14 Jan 2021 19:47:31 -0600 > Rob Herring <robh@kernel.org> escreveu: > > > On Thu, Jan 14, 2021 at 06:35:44PM +0100, Mauro Carvalho Chehab wrote: > > > The phy USB3 driver for Hisilicon 970 (hi3670) is ready > > > for mainstream. Mode it from staging into the main driver's > > > phy/ directory. > > > > > > Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> > > > --- > > > .../bindings/phy/phy-hi3670-usb3.yaml | 72 ++ > > > MAINTAINERS | 9 +- > > > drivers/phy/hisilicon/Kconfig | 10 + > > > drivers/phy/hisilicon/Makefile | 1 + > > > drivers/phy/hisilicon/phy-hi3670-usb3.c | 668 ++++++++++++++++++ > > > drivers/staging/hikey9xx/Kconfig | 11 - > > > drivers/staging/hikey9xx/Makefile | 2 - > > > drivers/staging/hikey9xx/phy-hi3670-usb3.c | 668 ------------------ > > > drivers/staging/hikey9xx/phy-hi3670-usb3.yaml | 72 -- > > > 9 files changed, 759 insertions(+), 754 deletions(-) > > > create mode 100644 Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml > > > create mode 100644 drivers/phy/hisilicon/phy-hi3670-usb3.c > > > delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.c > > > delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.yaml > > > > > > diff --git a/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml b/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml > > > new file mode 100644 > > > index 000000000000..125a5d6546ae > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml > > > @@ -0,0 +1,72 @@ > > > +# SPDX-License-Identifier: GPL-2.0 > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/phy/hisilicon,hi3670-usb3.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: Hisilicon Kirin970 USB PHY > > > + > > > +maintainers: > > > + - Mauro Carvalho Chehab <mchehab+huawei@kernel.org> > > > > Blank line. > > Ok. > > > > > > +description: |+ > > > + Bindings for USB3 PHY on HiSilicon Kirin 970. > > > + > > > +properties: > > > + compatible: > > > + const: hisilicon,hi3670-usb-phy > > > + > > > + "#phy-cells": > > > + const: 0 > > > + > > > + hisilicon,pericrg-syscon: > > > + $ref: '/schemas/types.yaml#/definitions/phandle' > > > + description: phandle of syscon used to control iso refclk. > > > + > > > + hisilicon,pctrl-syscon: > > > + $ref: '/schemas/types.yaml#/definitions/phandle' > > > + description: phandle of syscon used to control usb tcxo. > > > + > > > + hisilicon,sctrl-syscon: > > > + $ref: '/schemas/types.yaml#/definitions/phandle' > > > + description: phandle of syscon used to control phy deep sleep. > > > + > > > + hisilicon,eye-diagram-param: > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > + description: Eye diagram for phy. > > > + > > > + hisilicon,tx-vboost-lvl: > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > + description: TX level vboost for phy. > > > + > > > +required: > > > + - compatible > > > + - hisilicon,pericrg-syscon > > > + - hisilicon,pctrl-syscon > > > + - hisilicon,sctrl-syscon > > > + - hisilicon,eye-diagram-param > > > + - hisilicon,tx-vboost-lvl > > > + - "#phy-cells" > > > + > > > +additionalProperties: false > > > + > > > +examples: > > > + - | > > > + bus { > > > + #address-cells = <2>; > > > + #size-cells = <2>; > > > + > > > + usb3_otg_bc: usb3_otg_bc@ff200000 { > > > + compatible = "syscon", "simple-mfd"; > > > + reg = <0x0 0xff200000 0x0 0x1000>; > > > + > > > + usb_phy { > > > > Is there a contiguous register region for this sub-block? If so, add > > 'reg' even though Linux doesn't need it currently. > > No. The driver uses 4 syscon regions in order to access the needed > registers: I meant just for the parent device node. I assume these are the 'main' registers? If not, then maybe it should be a child of one of the other syscons. 'reg' would just be for documentation ATM. However, if the subblock was reused on another chip, but at a different offset then reg would become useful. You could handle that with a fixed offset when 'reg' is missing, but adding it later would be too late. Rob _______________________________________________ devel mailing list devel@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 4/4] phy: phy-hi3670-usb3: move driver from staging into phy 2021-01-22 14:51 ` Rob Herring @ 2021-01-22 15:57 ` Mauro Carvalho Chehab -1 siblings, 0 replies; 25+ messages in thread From: Mauro Carvalho Chehab @ 2021-01-22 15:57 UTC (permalink / raw) To: Rob Herring Cc: Vinod Koul, Alex Dewar, Greg Kroah-Hartman, Kishon Vijay Abraham I, Yu Chen, open list:STAGING SUBSYSTEM, devicetree, linux-kernel Em Fri, 22 Jan 2021 08:51:37 -0600 Rob Herring <robh@kernel.org> escreveu: > On Tue, Jan 19, 2021 at 4:26 AM Mauro Carvalho Chehab > <mchehab+huawei@kernel.org> wrote: > > > > Em Thu, 14 Jan 2021 19:47:31 -0600 > > Rob Herring <robh@kernel.org> escreveu: > > > > > On Thu, Jan 14, 2021 at 06:35:44PM +0100, Mauro Carvalho Chehab wrote: > > > > The phy USB3 driver for Hisilicon 970 (hi3670) is ready > > > > for mainstream. Mode it from staging into the main driver's > > > > phy/ directory. > > > > > > > > Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> > > > > --- > > > > .../bindings/phy/phy-hi3670-usb3.yaml | 72 ++ > > > > MAINTAINERS | 9 +- > > > > drivers/phy/hisilicon/Kconfig | 10 + > > > > drivers/phy/hisilicon/Makefile | 1 + > > > > drivers/phy/hisilicon/phy-hi3670-usb3.c | 668 ++++++++++++++++++ > > > > drivers/staging/hikey9xx/Kconfig | 11 - > > > > drivers/staging/hikey9xx/Makefile | 2 - > > > > drivers/staging/hikey9xx/phy-hi3670-usb3.c | 668 ------------------ > > > > drivers/staging/hikey9xx/phy-hi3670-usb3.yaml | 72 -- > > > > 9 files changed, 759 insertions(+), 754 deletions(-) > > > > create mode 100644 Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml > > > > create mode 100644 drivers/phy/hisilicon/phy-hi3670-usb3.c > > > > delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.c > > > > delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.yaml > > > > > > > > diff --git a/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml b/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml > > > > new file mode 100644 > > > > index 000000000000..125a5d6546ae > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml > > > > @@ -0,0 +1,72 @@ > > > > +# SPDX-License-Identifier: GPL-2.0 > > > > +%YAML 1.2 > > > > +--- > > > > +$id: http://devicetree.org/schemas/phy/hisilicon,hi3670-usb3.yaml# > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > > + > > > > +title: Hisilicon Kirin970 USB PHY > > > > + > > > > +maintainers: > > > > + - Mauro Carvalho Chehab <mchehab+huawei@kernel.org> > > > > > > Blank line. > > > > Ok. > > > > > > > > > +description: |+ > > > > + Bindings for USB3 PHY on HiSilicon Kirin 970. > > > > + > > > > +properties: > > > > + compatible: > > > > + const: hisilicon,hi3670-usb-phy > > > > + > > > > + "#phy-cells": > > > > + const: 0 > > > > + > > > > + hisilicon,pericrg-syscon: > > > > + $ref: '/schemas/types.yaml#/definitions/phandle' > > > > + description: phandle of syscon used to control iso refclk. > > > > + > > > > + hisilicon,pctrl-syscon: > > > > + $ref: '/schemas/types.yaml#/definitions/phandle' > > > > + description: phandle of syscon used to control usb tcxo. > > > > + > > > > + hisilicon,sctrl-syscon: > > > > + $ref: '/schemas/types.yaml#/definitions/phandle' > > > > + description: phandle of syscon used to control phy deep sleep. > > > > + > > > > + hisilicon,eye-diagram-param: > > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > > + description: Eye diagram for phy. > > > > + > > > > + hisilicon,tx-vboost-lvl: > > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > > + description: TX level vboost for phy. > > > > + > > > > +required: > > > > + - compatible > > > > + - hisilicon,pericrg-syscon > > > > + - hisilicon,pctrl-syscon > > > > + - hisilicon,sctrl-syscon > > > > + - hisilicon,eye-diagram-param > > > > + - hisilicon,tx-vboost-lvl > > > > + - "#phy-cells" > > > > + > > > > +additionalProperties: false > > > > + > > > > +examples: > > > > + - | > > > > + bus { > > > > + #address-cells = <2>; > > > > + #size-cells = <2>; > > > > + > > > > + usb3_otg_bc: usb3_otg_bc@ff200000 { > > > > + compatible = "syscon", "simple-mfd"; > > > > + reg = <0x0 0xff200000 0x0 0x1000>; > > > > + > > > > + usb_phy { > > > > > > Is there a contiguous register region for this sub-block? If so, add > > > 'reg' even though Linux doesn't need it currently. > > > > No. The driver uses 4 syscon regions in order to access the needed > > registers: > > I meant just for the parent device node. I assume these are the 'main' > registers? If not, then maybe it should be a child of one of the other > syscons. > > 'reg' would just be for documentation ATM. However, if the subblock > was reused on another chip, but at a different offset then reg would > become useful. You could handle that with a fixed offset when 'reg' is > missing, but adding it later would be too late. Hmm... You meaning something like this: examples: - | bus { #address-cells = <2>; #size-cells = <2>; reg = <0>; right? If so, I don't see any problem on doing that, but that fictional "bus" was added there just to be able to set #address-cells and #size-cells, in order to avoid warnings when checking the DT validity, as recommended by a past review from your side. The actual DT for USB is (from hi3670.dtsi): / { compatible = "hisilicon,hi3670"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; soc { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; crg_ctrl: crg_ctrl@fff35000 { compatible = "hisilicon,hi3670-crgctrl", "syscon"; reg = <0x0 0xfff35000 0x0 0x1000>; #clock-cells = <1>; }; ... usb3_otg_bc: usb3_otg_bc@ff200000 { compatible = "syscon", "simple-mfd"; reg = <0x0 0xff200000 0x0 0x1000>; usb_phy: usbphy { compatible = "hisilicon,hi3670-usb-phy"; #phy-cells = <0>; hisilicon,pericrg-syscon = <&crg_ctrl>; hisilicon,pctrl-syscon = <&pctrl>; hisilicon,sctrl-syscon = <&sctrl>; hisilicon,eye-diagram-param = <0xFDFEE4>; hisilicon,tx-vboost-lvl = <0x5>; phy-supply = <&ldo17>; }; }; ... }; }; Thanks, Mauro ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 4/4] phy: phy-hi3670-usb3: move driver from staging into phy @ 2021-01-22 15:57 ` Mauro Carvalho Chehab 0 siblings, 0 replies; 25+ messages in thread From: Mauro Carvalho Chehab @ 2021-01-22 15:57 UTC (permalink / raw) To: Rob Herring Cc: open list:STAGING SUBSYSTEM, devicetree, Greg Kroah-Hartman, Yu Chen, linux-kernel, Kishon Vijay Abraham I, Vinod Koul, Alex Dewar Em Fri, 22 Jan 2021 08:51:37 -0600 Rob Herring <robh@kernel.org> escreveu: > On Tue, Jan 19, 2021 at 4:26 AM Mauro Carvalho Chehab > <mchehab+huawei@kernel.org> wrote: > > > > Em Thu, 14 Jan 2021 19:47:31 -0600 > > Rob Herring <robh@kernel.org> escreveu: > > > > > On Thu, Jan 14, 2021 at 06:35:44PM +0100, Mauro Carvalho Chehab wrote: > > > > The phy USB3 driver for Hisilicon 970 (hi3670) is ready > > > > for mainstream. Mode it from staging into the main driver's > > > > phy/ directory. > > > > > > > > Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> > > > > --- > > > > .../bindings/phy/phy-hi3670-usb3.yaml | 72 ++ > > > > MAINTAINERS | 9 +- > > > > drivers/phy/hisilicon/Kconfig | 10 + > > > > drivers/phy/hisilicon/Makefile | 1 + > > > > drivers/phy/hisilicon/phy-hi3670-usb3.c | 668 ++++++++++++++++++ > > > > drivers/staging/hikey9xx/Kconfig | 11 - > > > > drivers/staging/hikey9xx/Makefile | 2 - > > > > drivers/staging/hikey9xx/phy-hi3670-usb3.c | 668 ------------------ > > > > drivers/staging/hikey9xx/phy-hi3670-usb3.yaml | 72 -- > > > > 9 files changed, 759 insertions(+), 754 deletions(-) > > > > create mode 100644 Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml > > > > create mode 100644 drivers/phy/hisilicon/phy-hi3670-usb3.c > > > > delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.c > > > > delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.yaml > > > > > > > > diff --git a/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml b/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml > > > > new file mode 100644 > > > > index 000000000000..125a5d6546ae > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml > > > > @@ -0,0 +1,72 @@ > > > > +# SPDX-License-Identifier: GPL-2.0 > > > > +%YAML 1.2 > > > > +--- > > > > +$id: http://devicetree.org/schemas/phy/hisilicon,hi3670-usb3.yaml# > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > > + > > > > +title: Hisilicon Kirin970 USB PHY > > > > + > > > > +maintainers: > > > > + - Mauro Carvalho Chehab <mchehab+huawei@kernel.org> > > > > > > Blank line. > > > > Ok. > > > > > > > > > +description: |+ > > > > + Bindings for USB3 PHY on HiSilicon Kirin 970. > > > > + > > > > +properties: > > > > + compatible: > > > > + const: hisilicon,hi3670-usb-phy > > > > + > > > > + "#phy-cells": > > > > + const: 0 > > > > + > > > > + hisilicon,pericrg-syscon: > > > > + $ref: '/schemas/types.yaml#/definitions/phandle' > > > > + description: phandle of syscon used to control iso refclk. > > > > + > > > > + hisilicon,pctrl-syscon: > > > > + $ref: '/schemas/types.yaml#/definitions/phandle' > > > > + description: phandle of syscon used to control usb tcxo. > > > > + > > > > + hisilicon,sctrl-syscon: > > > > + $ref: '/schemas/types.yaml#/definitions/phandle' > > > > + description: phandle of syscon used to control phy deep sleep. > > > > + > > > > + hisilicon,eye-diagram-param: > > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > > + description: Eye diagram for phy. > > > > + > > > > + hisilicon,tx-vboost-lvl: > > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > > + description: TX level vboost for phy. > > > > + > > > > +required: > > > > + - compatible > > > > + - hisilicon,pericrg-syscon > > > > + - hisilicon,pctrl-syscon > > > > + - hisilicon,sctrl-syscon > > > > + - hisilicon,eye-diagram-param > > > > + - hisilicon,tx-vboost-lvl > > > > + - "#phy-cells" > > > > + > > > > +additionalProperties: false > > > > + > > > > +examples: > > > > + - | > > > > + bus { > > > > + #address-cells = <2>; > > > > + #size-cells = <2>; > > > > + > > > > + usb3_otg_bc: usb3_otg_bc@ff200000 { > > > > + compatible = "syscon", "simple-mfd"; > > > > + reg = <0x0 0xff200000 0x0 0x1000>; > > > > + > > > > + usb_phy { > > > > > > Is there a contiguous register region for this sub-block? If so, add > > > 'reg' even though Linux doesn't need it currently. > > > > No. The driver uses 4 syscon regions in order to access the needed > > registers: > > I meant just for the parent device node. I assume these are the 'main' > registers? If not, then maybe it should be a child of one of the other > syscons. > > 'reg' would just be for documentation ATM. However, if the subblock > was reused on another chip, but at a different offset then reg would > become useful. You could handle that with a fixed offset when 'reg' is > missing, but adding it later would be too late. Hmm... You meaning something like this: examples: - | bus { #address-cells = <2>; #size-cells = <2>; reg = <0>; right? If so, I don't see any problem on doing that, but that fictional "bus" was added there just to be able to set #address-cells and #size-cells, in order to avoid warnings when checking the DT validity, as recommended by a past review from your side. The actual DT for USB is (from hi3670.dtsi): / { compatible = "hisilicon,hi3670"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; soc { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; crg_ctrl: crg_ctrl@fff35000 { compatible = "hisilicon,hi3670-crgctrl", "syscon"; reg = <0x0 0xfff35000 0x0 0x1000>; #clock-cells = <1>; }; ... usb3_otg_bc: usb3_otg_bc@ff200000 { compatible = "syscon", "simple-mfd"; reg = <0x0 0xff200000 0x0 0x1000>; usb_phy: usbphy { compatible = "hisilicon,hi3670-usb-phy"; #phy-cells = <0>; hisilicon,pericrg-syscon = <&crg_ctrl>; hisilicon,pctrl-syscon = <&pctrl>; hisilicon,sctrl-syscon = <&sctrl>; hisilicon,eye-diagram-param = <0xFDFEE4>; hisilicon,tx-vboost-lvl = <0x5>; phy-supply = <&ldo17>; }; }; ... }; }; Thanks, Mauro _______________________________________________ devel mailing list devel@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel ^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2021-01-22 17:31 UTC | newest] Thread overview: 25+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-01-14 17:35 [PATCH v2 0/4] Promote Hikey 970 USB phy out of staging Mauro Carvalho Chehab 2021-01-14 17:35 ` Mauro Carvalho Chehab 2021-01-14 17:35 ` [PATCH v2 1/4] staging: hikey9xx: phy-hi3670-usb3.c: use bitfield macros Mauro Carvalho Chehab 2021-01-14 17:35 ` Mauro Carvalho Chehab 2021-01-14 17:35 ` [PATCH v2 2/4] staging: hikey9xx: phy-hi3670-usb3.c: adjust retry logic Mauro Carvalho Chehab 2021-01-14 17:35 ` Mauro Carvalho Chehab 2021-01-14 17:35 ` [PATCH v2 3/4] staging: hikey9xx: phy-hi3670-usb3.c: hi3670_is_abbclk_seleted() returns bool Mauro Carvalho Chehab 2021-01-14 17:35 ` Mauro Carvalho Chehab 2021-01-14 17:56 ` Joe Perches 2021-01-14 17:56 ` Joe Perches 2021-01-19 6:56 ` Dan Carpenter 2021-01-19 6:56 ` Dan Carpenter 2021-01-19 10:24 ` Mauro Carvalho Chehab 2021-01-14 17:35 ` [PATCH v2 4/4] phy: phy-hi3670-usb3: move driver from staging into phy Mauro Carvalho Chehab 2021-01-14 17:35 ` Mauro Carvalho Chehab 2021-01-14 22:54 ` Rob Herring 2021-01-14 22:54 ` Rob Herring 2021-01-15 1:47 ` Rob Herring 2021-01-15 1:47 ` Rob Herring 2021-01-19 10:26 ` Mauro Carvalho Chehab 2021-01-19 10:26 ` Mauro Carvalho Chehab 2021-01-22 14:51 ` Rob Herring 2021-01-22 14:51 ` Rob Herring 2021-01-22 15:57 ` Mauro Carvalho Chehab 2021-01-22 15:57 ` Mauro Carvalho Chehab
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